Update system.c to support H7.

This commit is contained in:
iabdalkader 2017-12-24 22:13:38 +02:00
parent f8ba3e4e10
commit a9c8cdb752

View File

@ -51,108 +51,50 @@
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include STM32_HAL_H #include STM32_HAL_H
#include "omv_boardconfig.h" #include "omv_boardconfig.h"
/** #if defined(STM32H743xx)
* @} #define SRAM_BASE D1_AXISRAM_BASE
*/ #define FLASH_BASE FLASH_BANK1_BASE
#endif
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions // Uncomment the following line if you need to use external SRAM or SDRAM
* @{ //#define DATA_IN_ExtSRAM
*/ //#define DATA_IN_ExtSDRAM
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in // Uncomment the following line if you need to relocate your vector Table in internal SRAM.
Internal SRAM. */ //#define VECT_TAB_SRAM
/* #define VECT_TAB_SRAM */
// Defined in board config files // Vector Table base offset field (defined in board config files).
//#define VECT_TAB_OFFSET 0x10000 /*!< Vector Table base offset field. //#define VECT_TAB_OFFSET 0x10000
// This value must be a multiple of 0x200. */
/******************************************************************************/
/** /** This variable is updated in three ways:
* @} * 1) by calling CMSIS function SystemCoreClockUpdate()
*/ * 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
* 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
/** @addtogroup STM32F4xx_System_Private_Macros * Note: If you use this function to configure the system clock; then there
* @{ * is no need to call the 2 first functions listed above, since SystemCoreClock
*/ * variable is updated automatically.
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 16000000; uint32_t SystemCoreClock = 16000000;
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
#if defined STM32H743xx
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
#else
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
#endif
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory * Initialize the FPU setting, vector table location and External memory
@ -167,35 +109,85 @@ void SystemInit(void)
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */ /* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001; RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */ /* Reset CFGR register */
RCC->CFGR = 0x00000000; RCC->CFGR = 0x00000000;
#if defined(STM32H743xx)
/* Reset HSEON, CSSON , CSION, RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEAF6ED7F;
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
#else
/* Reset HSEON, CSSON and PLLON bits */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF; RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */ /* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010; RCC->PLLCFGR = 0x24003010;
#endif
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CR &= (uint32_t)0xFFFBFFFF;
#if defined(STM32H743xx)
/* Disable all interrupts */
RCC->CIER = 0x00000000;
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001;
#else
/* Disable all interrupts */ /* Disable all interrupts */
RCC->CIR = 0x00000000; RCC->CIR = 0x00000000;
#endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address */
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ /* Vector Table Relocation in Internal SRAM */
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else #else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ /* Vector Table Relocation in Internal FLASH */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
#endif #endif
#if !defined(STM32H743xx)
SCB->CCR |= SCB_CCR_STKALIGN_Msk; SCB->CCR |= SCB_CCR_STKALIGN_Msk;
#endif
} }
/** /**
@ -234,6 +226,75 @@ void SystemInit(void)
* @param None * @param None
* @retval None * @retval None
*/ */
#if defined(MCU_SERIES_H7)
void SystemCoreClockUpdate (void)
{
float fracn1, pllvco = 0;
uint32_t tmp, pllp = 2, pllsource = 0, pllm = 2, pllfracen = 0, hsivalue = 0;
switch (RCC->CFGR & RCC_CFGR_SWS) {
case 0x00: /* HSI used as system clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) {
SystemCoreClock = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
} else {
SystemCoreClock = (uint32_t) HSI_VALUE;
}
break;
case 0x08: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
break;
case 0x10: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x18: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
switch (pllsource) {
case 0x00: /* HSI used as PLL clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) {
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)) ;
pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
} else {
pllvco = (HSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
}
break;
case 0x01: /* CSI used as PLL clock source */
pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
break;
case 0x02: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
break;
default:
pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
SystemCoreClock = (uint32_t) (pllvco/pllp);
break;
default:
SystemCoreClock = CSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#else
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
@ -241,29 +302,24 @@ void SystemCoreClockUpdate(void)
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp) {
{
case 0x00: /* HSI used as system clock source */ case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x04: /* HSE used as system clock source */ case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N case 0x08: /* PLL used as system clock source */
SYSCLK = PLL_VCO / PLL_P /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0) if (pllsource != 0) {
{
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} } else {
else
{
/* HSI used as PLL clock source */ /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} }
@ -271,6 +327,7 @@ void SystemCoreClockUpdate(void)
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp; SystemCoreClock = pllvco/pllp;
break; break;
default: default:
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
@ -281,6 +338,7 @@ void SystemCoreClockUpdate(void)
/* HCLK frequency */ /* HCLK frequency */
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
#endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/** /**
@ -293,13 +351,11 @@ void SystemCoreClockUpdate(void)
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void)
{ {
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF; register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index; register uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface /* Enable GPIO clocks */
clock */
RCC->AHB1ENR |= 0x000001F8; RCC->AHB1ENR |= 0x000001F8;
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
@ -426,9 +482,7 @@ void SystemInit_ExtMemCtl(void)
tmpreg = FMC_Bank5_6->SDCR[0]; tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(DATA_IN_ExtSRAM) #if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/ /*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
@ -499,9 +553,7 @@ void SystemInit_ExtMemCtl(void)
FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
} }
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
@ -530,23 +582,37 @@ void __fatal_error(const char *msg);
void SystemClock_Config(void) void SystemClock_Config(void)
{ {
uint32_t flash_latency;
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
#if defined (STM32H743xx)// 400MHz/48MHz
/* Supply configuration update enable */
MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
#else
/* Enable Power Control clock */ /* Enable Power Control clock */
__PWR_CLK_ENABLE(); __PWR_CLK_ENABLE();
#endif
/* The voltage scaling allows optimizing the power consumption when the device is /* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
uint32_t flash_latency; #if defined (STM32H743xx)// 400MHz/48MHz
while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {
}
#endif
/* Enable HSE Oscillator and activate PLL with HSE as source */ /* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
#if defined (STM32F407xx) // 168MHz/48MHz #if defined (STM32F407xx) // 168MHz/48MHz
flash_latency = FLASH_LATENCY_5; flash_latency = FLASH_LATENCY_5;
RCC_OscInitStruct.PLL.PLLM = 12; RCC_OscInitStruct.PLL.PLLM = 12;
@ -566,34 +632,88 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLQ = 9; RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLR = 2;
#endif //STM32F407xx #elif defined (STM32H743xx)// 400MHz/48MHz
flash_latency = FLASH_LATENCY_4;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 8;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
#endif
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
/* Initialization Error */ /* Initialization Error */
Error_Handler(); Error_Handler();
} }
#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F765xx) #if defined(STM32H743xx)
if(HAL_PWREx_ActivateOverDrive() != HAL_OK) { /* PLL3 for USB Clock */
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.PLL3.PLL3M = 6;
PeriphClkInitStruct.PLL3.PLL3N = 192;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 8;
PeriphClkInitStruct.PLL3.PLL3R = 2;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
/* Initialization Error */ /* Initialization Error */
Error_Handler(); Error_Handler();
} }
#endif #endif
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */ #if defined(MCU_SERIES_H7)
HAL_PWREx_EnableUSBVoltageDetector();
#endif
#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#endif
/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
#if defined(MCU_SERIES_H7)
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
#else
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
#endif
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK) { if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK) {
/* Initialization Error */ /* Initialization Error */
Error_Handler(); Error_Handler();
} }
#if defined(MCU_SERIES_H7)
// WTF is I/O Compensation Cell ?
///*activate CSI clock mondatory for I/O Compensation Cell*/
//__HAL_RCC_CSI_ENABLE() ;
///* Enable SYSCFG clock mondatory for I/O Compensation Cell */
__HAL_RCC_SYSCFG_CLK_ENABLE() ;
///* Enables the I/O Compensation Cell */
//HAL_EnableCompensationCell();
#endif
SystemCoreClockUpdate(); SystemCoreClockUpdate();
} }
#undef Error_Handler #undef Error_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/