Update system.c to support H7.

This commit is contained in:
iabdalkader 2017-12-24 22:13:38 +02:00
parent f8ba3e4e10
commit a9c8cdb752

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@ -6,16 +6,16 @@
* @date 18-February-2014 * @date 18-February-2014
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): This function is called at startup just after reset and * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file. * the "startup_stm32f4xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
@ -51,151 +51,143 @@
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS #include STM32_HAL_H
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include STM32_HAL_H
#include "omv_boardconfig.h" #include "omv_boardconfig.h"
/** #if defined(STM32H743xx)
* @} #define SRAM_BASE D1_AXISRAM_BASE
*/ #define FLASH_BASE FLASH_BANK1_BASE
#endif
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions // Uncomment the following line if you need to use external SRAM or SDRAM
* @{ //#define DATA_IN_ExtSRAM
*/ //#define DATA_IN_ExtSDRAM
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in // Uncomment the following line if you need to relocate your vector Table in internal SRAM.
Internal SRAM. */ //#define VECT_TAB_SRAM
/* #define VECT_TAB_SRAM */
// Defined in board config files // Vector Table base offset field (defined in board config files).
//#define VECT_TAB_OFFSET 0x10000 /*!< Vector Table base offset field. //#define VECT_TAB_OFFSET 0x10000
// This value must be a multiple of 0x200. */
/******************************************************************************/
/** /** This variable is updated in three ways:
* @} * 1) by calling CMSIS function SystemCoreClockUpdate()
*/ * 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
* 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
/** @addtogroup STM32F4xx_System_Private_Macros * Note: If you use this function to configure the system clock; then there
* @{ * is no need to call the 2 first functions listed above, since SystemCoreClock
*/ * variable is updated automatically.
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 16000000; uint32_t SystemCoreClock = 16000000;
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
#if defined STM32H743xx
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
#else
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
#endif
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory * Initialize the FPU setting, vector table location and External memory
* configuration. * configuration.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit(void) void SystemInit(void)
{ {
/* FPU settings ------------------------------------------------------------*/ /* FPU settings ------------------------------------------------------------*/
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */ /* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001; RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */ /* Reset CFGR register */
RCC->CFGR = 0x00000000; RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */ #if defined(STM32H743xx)
RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEON, CSSON , CSION, RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEAF6ED7F;
/* Reset PLLCFGR register */ /* Reset D1CFGR register */
RCC->PLLCFGR = 0x24003010; RCC->D1CFGR = 0x00000000;
/* Reset HSEBYP bit */ /* Reset D2CFGR register */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->D2CFGR = 0x00000000;
/* Disable all interrupts */ /* Reset D3CFGR register */
RCC->CIR = 0x00000000; RCC->D3CFGR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) /* Reset PLLCKSELR register */
SystemInit_ExtMemCtl(); RCC->PLLCKSELR = 0x00000000;
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/ /* Reset PLLCFGR register */
#ifdef VECT_TAB_SRAM RCC->PLLCFGR = 0x00000000;
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
#else #else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
#endif #endif
SCB->CCR |= SCB_CCR_STKALIGN_Msk; /* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
#if defined(STM32H743xx)
/* Disable all interrupts */
RCC->CIER = 0x00000000;
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001;
#else
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address */
#ifdef VECT_TAB_SRAM
/* Vector Table Relocation in Internal SRAM */
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else
/* Vector Table Relocation in Internal FLASH */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
#endif
#if !defined(STM32H743xx)
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
#endif
} }
/** /**
@ -203,84 +195,150 @@ void SystemInit(void)
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE * depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function * is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result. * may have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* *
* @param None * @param None
* @retval None * @retval None
*/ */
#if defined(MCU_SERIES_H7)
void SystemCoreClockUpdate (void)
{
float fracn1, pllvco = 0;
uint32_t tmp, pllp = 2, pllsource = 0, pllm = 2, pllfracen = 0, hsivalue = 0;
switch (RCC->CFGR & RCC_CFGR_SWS) {
case 0x00: /* HSI used as system clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) {
SystemCoreClock = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
} else {
SystemCoreClock = (uint32_t) HSI_VALUE;
}
break;
case 0x08: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
break;
case 0x10: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x18: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
switch (pllsource) {
case 0x00: /* HSI used as PLL clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) {
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)) ;
pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
} else {
pllvco = (HSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
}
break;
case 0x01: /* CSI used as PLL clock source */
pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
break;
case 0x02: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
break;
default:
pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
SystemCoreClock = (uint32_t) (pllvco/pllp);
break;
default:
SystemCoreClock = CSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#else
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) /* Get SYSCLK source -------------------------------------------------------*/
{ tmp = RCC->CFGR & RCC_CFGR_SWS;
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N switch (tmp) {
SYSCLK = PLL_VCO / PLL_P case 0x00: /* HSI used as system clock source */
*/ SystemCoreClock = HSI_VALUE;
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; break;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; case 0x04: /* HSE used as system clock source */
SystemCoreClock = pllvco/pllp; SystemCoreClock = HSE_VALUE;
break; break;
default:
SystemCoreClock = HSI_VALUE; case 0x08: /* PLL used as system clock source */
break; /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */
} pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
/* Compute HCLK frequency --------------------------------------------------*/ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; if (pllsource != 0) {
/* HCLK frequency */ /* HSE used as PLL clock source */
SystemCoreClock >>= tmp; pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} else {
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
} }
#endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/** /**
@ -293,23 +351,21 @@ void SystemCoreClockUpdate(void)
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void)
{ {
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF; register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index; register uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface /* Enable GPIO clocks */
clock */
RCC->AHB1ENR |= 0x000001F8; RCC->AHB1ENR |= 0x000001F8;
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC; GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A; GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */ /* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A; GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
@ -317,61 +373,61 @@ void SystemInit_ExtMemCtl(void)
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A; GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */ /* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A; GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA; GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */ /* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA; GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA; GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */ /* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA; GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */ /* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC; GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */ /* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0; GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */ /* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0; GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */ /* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000; GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */ /* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000; GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */ /* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0; GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */ /* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA; GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */ /* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA; GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */ /* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000; GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */ /* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000; GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration ------------------------------------------------------*/ /*-- FMC Configuration ------------------------------------------------------*/
@ -380,26 +436,26 @@ void SystemInit_ExtMemCtl(void)
/* Configure and enable SDRAM bank1 */ /* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000019E0; FMC_Bank5_6->SDCR[0] = 0x000019E0;
FMC_Bank5_6->SDTR[0] = 0x01115351; FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */ /* SDRAM initialization sequence */
/* Clock enable command */ /* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011; FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Delay */ /* Delay */
for (index = 0; index<1000; index++); for (index = 0; index<1000; index++);
/* PALL command */ /* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012; FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Auto refresh command */ /* Auto refresh command */
@ -407,7 +463,7 @@ void SystemInit_ExtMemCtl(void)
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* MRD register program */ /* MRD register program */
@ -415,7 +471,7 @@ void SystemInit_ExtMemCtl(void)
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Set refresh count */ /* Set refresh count */
@ -423,12 +479,10 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */ /* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0]; tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(DATA_IN_ExtSRAM) #if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/ /*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
@ -499,9 +553,7 @@ void SystemInit_ExtMemCtl(void)
FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
} }
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
@ -530,70 +582,138 @@ void __fatal_error(const char *msg);
void SystemClock_Config(void) void SystemClock_Config(void)
{ {
RCC_ClkInitTypeDef RCC_ClkInitStruct; uint32_t flash_latency;
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
/* Enable Power Control clock */ #if defined (STM32H743xx)// 400MHz/48MHz
__PWR_CLK_ENABLE(); /* Supply configuration update enable */
MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
/* The voltage scaling allows optimizing the power consumption when the device is #else
clocked below the maximum system frequency, to update the voltage scaling value /* Enable Power Control clock */
regarding system frequency refer to product datasheet. */ __PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
uint32_t flash_latency;
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
#if defined (STM32F407xx) // 168MHz/48MHz
flash_latency = FLASH_LATENCY_5;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLQ = 7;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
#elif defined (STM32F427xx)// 192MHz/48MHz
flash_latency = FLASH_LATENCY_7;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 384;
RCC_OscInitStruct.PLL.PLLQ = 8;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
#elif defined (STM32F765xx)// 216MHz/48MHz
flash_latency = FLASH_LATENCY_7;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 432;
RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLR = 2;
#endif //STM32F407xx
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F765xx)
if(HAL_PWREx_ActivateOverDrive() != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#endif #endif
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 /* The voltage scaling allows optimizing the power consumption when the device is
clocks dividers */ clocked below the maximum system frequency, to update the voltage scaling value
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); regarding system frequency refer to product datasheet. */
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK) { #if defined (STM32H743xx)// 400MHz/48MHz
/* Initialization Error */ while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {
Error_Handler(); }
} #endif
SystemCoreClockUpdate(); /* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
#if defined (STM32F407xx) // 168MHz/48MHz
flash_latency = FLASH_LATENCY_5;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLQ = 7;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
#elif defined (STM32F427xx)// 192MHz/48MHz
flash_latency = FLASH_LATENCY_7;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 384;
RCC_OscInitStruct.PLL.PLLQ = 8;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
#elif defined (STM32F765xx)// 216MHz/48MHz
flash_latency = FLASH_LATENCY_7;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 432;
RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLR = 2;
#elif defined (STM32H743xx)// 400MHz/48MHz
flash_latency = FLASH_LATENCY_4;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 8;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
#endif
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#if defined(STM32H743xx)
/* PLL3 for USB Clock */
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.PLL3.PLL3M = 6;
PeriphClkInitStruct.PLL3.PLL3N = 192;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 8;
PeriphClkInitStruct.PLL3.PLL3R = 2;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#endif
#if defined(MCU_SERIES_H7)
HAL_PWREx_EnableUSBVoltageDetector();
#endif
#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#endif
/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
#if defined(MCU_SERIES_H7)
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
#else
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
#endif
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK) {
/* Initialization Error */
Error_Handler();
}
#if defined(MCU_SERIES_H7)
// WTF is I/O Compensation Cell ?
///*activate CSI clock mondatory for I/O Compensation Cell*/
//__HAL_RCC_CSI_ENABLE() ;
///* Enable SYSCFG clock mondatory for I/O Compensation Cell */
__HAL_RCC_SYSCFG_CLK_ENABLE() ;
///* Enables the I/O Compensation Cell */
//HAL_EnableCompensationCell();
#endif
SystemCoreClockUpdate();
} }
#undef Error_Handler #undef Error_Handler
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