diff --git a/src/hal/cmsis/src/st/system_stm32fxxx.c b/src/hal/cmsis/src/st/system_stm32fxxx.c index e9b1719d0..97019df7d 100644 --- a/src/hal/cmsis/src/st/system_stm32fxxx.c +++ b/src/hal/cmsis/src/st/system_stm32fxxx.c @@ -61,7 +61,7 @@ uint32_t SystemCoreClock = 16000000; extern void __fatal_error(const char *msg); -#if defined(MCU_SERIES_H7) +#if defined(STM32H7) #define SRAM_BASE D1_AXISRAM_BASE #define FLASH_BASE FLASH_BANK1_BASE @@ -73,7 +73,7 @@ extern void __fatal_error(const char *msg); uint32_t SystemD2Clock = 64000000; const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -#elif defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) +#elif defined(STM32F4) || defined(STM32F7) #define CONFIG_RCC_CR_1ST (RCC_CR_HSION) #define CONFIG_RCC_CR_2ND (0xFEF6FFFF) @@ -102,7 +102,6 @@ void SystemInit(void) signal is detectable by the CPU after a WFI/WFE instruction. */ //SCB->SCR |= SCB_SCR_SEVONPEND_Msk; - #if !defined(CORE_CM4) /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= CONFIG_RCC_CR_1ST; @@ -116,7 +115,7 @@ void SystemInit(void) /* Reset PLLCFGR register */ RCC->PLLCFGR = CONFIG_RCC_PLLCFGR; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; @@ -146,39 +145,37 @@ void SystemInit(void) /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; - #endif // defined(MCU_SERIES_H7) + #endif // defined(STM32H7) /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) + #if defined(STM32F4) || defined(STM32F7) RCC->CIR = 0x00000000; - #elif defined(MCU_SERIES_L4) || defined(MCU_SERIES_H7) + #elif defined(STM32L4) || defined(STM32H7) RCC->CIER = 0x00000000; #endif - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ // See Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption" *((__IO uint32_t*)0x51008108) = 0x00000001; - #endif // defined(MCU_SERIES_H7) + #endif // defined(STM32H7) /* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */ SCB->CCR |= SCB_CCR_STKALIGN_Msk; #if !defined(NDEBUG) - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) + #if defined(STM32F4) || defined(STM32F7) DBGMCU->CR |= DBGMCU_CR_DBG_SLEEP; - #elif defined(MCU_SERIES_H7) + #elif defined(STM32H7) DBGMCU->CR |= DBGMCU_CR_DBG_SLEEPD1; DBGMCU->CR |= DBGMCU_CR_DBG_STOPD1; DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1; #endif #endif - #endif // !defined(CORE_CM4) - /* Configure the Vector Table location add offset address ------------------*/ SCB->VTOR = OMV_VTOR_BASE; } @@ -187,11 +184,11 @@ void SystemClock_Config(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; #endif - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) /* Supply configuration update enable */ HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY); #else @@ -202,7 +199,7 @@ void SystemClock_Config(void) /* The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency, to update the voltage scaling value regarding system frequency refer to product datasheet. */ - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) // Enable VSCALE0 for revision V devices. if (HAL_GetREVID() >= 0x2003) { __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -215,7 +212,7 @@ void SystemClock_Config(void) } // Wait for PWR_FLAG_VOSRDY - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET) { } #endif @@ -264,7 +261,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q; RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) // Override PLL1 frequency for revision Y devices, // with maximum frequency of 400MHz CPU 200MHz Bus. if (HAL_GetREVID() < 0x2003) { @@ -314,7 +311,7 @@ void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC; #endif - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) #if !defined(OMV_OMVPT_ERRATA_RTC) PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_RTC; @@ -385,9 +382,9 @@ void SystemClock_Config(void) // Initialization Error __fatal_error("HAL_RCCEx_PeriphCLKConfig"); } - #endif // defined(MCU_SERIES_H7) + #endif // defined(STM32H7) - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) + #if defined(STM32F4) || defined(STM32F7) if (HAL_PWREx_EnableOverDrive() != HAL_OK) { // Initialization Error __fatal_error("HAL_PWREx_EnableOverDrive"); @@ -395,7 +392,7 @@ void SystemClock_Config(void) #endif /* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */ - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -418,7 +415,7 @@ void SystemClock_Config(void) __fatal_error("HAL_RCC_ClockConfig"); } - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) // Activate CSI clock mondatory for I/O Compensation Cell __HAL_RCC_CSI_ENABLE() ; diff --git a/src/omv/common/export.mk b/src/omv/common/export.mk index 8eac49001..a98c3ac15 100644 --- a/src/omv/common/export.mk +++ b/src/omv/common/export.mk @@ -63,16 +63,12 @@ export FROZEN_MANIFEST # Export board config variables export PORT export MCU -export MCU_SERIES -export MCU_VARIANT -export MCU_CORE # Export Directories export TOP_DIR export BUILD export TOOLS export FW_DIR -export HAL_DIR export BOOT_DIR export OMV_DIR export CMSIS_DIR diff --git a/src/omv/ports/stm32/omv_csi.c b/src/omv/ports/stm32/omv_csi.c index 45ff6203f..0b30c18a5 100644 --- a/src/omv/ports/stm32/omv_csi.c +++ b/src/omv/ports/stm32/omv_csi.c @@ -80,7 +80,7 @@ void omv_csi_mdma_irq_handler(void) { static int omv_csi_dma_config() { // DMA Stream configuration DMAHandle.Instance = DMA2_Stream1; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) DMAHandle.Init.Request = DMA_REQUEST_DCMI; /* DMA Channel */ #else DMAHandle.Init.Channel = DMA_CHANNEL_1; /* DMA Channel */ @@ -215,7 +215,7 @@ int omv_csi_config(omv_csi_config_t config) { DCMIHandle.Init.CaptureRate = DCMI_CR_ALL_FRAME; // Capture rate all frames DCMIHandle.Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B; // Capture 8 bits on every pixel clock DCMIHandle.Init.JPEGMode = DCMI_JPEG_DISABLE; - #if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7) + #if defined(STM32F7) || defined(STM32H7) DCMIHandle.Init.ByteSelectMode = DCMI_BSM_ALL; // Capture all received bytes DCMIHandle.Init.ByteSelectStart = DCMI_OEBS_ODD; // Ignored DCMIHandle.Init.LineSelectMode = DCMI_LSM_ALL; // Capture all received lines diff --git a/src/omv/ports/stm32/omv_gpu.c b/src/omv/ports/stm32/omv_gpu.c index 609c2024c..4adfa1173 100644 --- a/src/omv/ports/stm32/omv_gpu.c +++ b/src/omv/ports/stm32/omv_gpu.c @@ -73,7 +73,7 @@ int omv_gpu_draw_image(image_t *src_img, } // DMA2D must always fetch the background on the F4 and F7 series so do this in software. - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) + #if defined(STM32F4) || defined(STM32F7) if (hint & IMAGE_HINT_BLACK_BACKGROUND) { return -1; } @@ -91,7 +91,7 @@ int omv_gpu_draw_image(image_t *src_img, dma2d.Init.Mode = DMA2D_M2M_BLEND; } - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) if (hint & IMAGE_HINT_BLACK_BACKGROUND) { dma2d.Init.Mode = DMA2D_M2M_BLEND_BG; } @@ -202,7 +202,7 @@ int omv_gpu_draw_image(image_t *src_img, uint32_t dst = (uint32_t) dst16; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) if (hint & IMAGE_HINT_BLACK_BACKGROUND) { dst = 0; } diff --git a/src/omv/ports/stm32/omv_portconfig.mk b/src/omv/ports/stm32/omv_portconfig.mk index 18933dddc..15416f3c5 100644 --- a/src/omv/ports/stm32/omv_portconfig.mk +++ b/src/omv/ports/stm32/omv_portconfig.mk @@ -21,12 +21,13 @@ # THE SOFTWARE. # Set startup and system files for CMSIS Makefile. -SYSTEM ?= st/system_stm32fxxx -STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]') -UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc -BOOT_DIR := boot - -LDSCRIPT ?= stm32fxxx +SYSTEM ?= st/system_stm32fxxx +LDSCRIPT ?= stm32fxxx +STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]') +UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc +MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]') +MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]') +HAL_DIR = hal/stm32/$(MCU_SERIES) # Compiler Flags CFLAGS += -std=gnu99 \ @@ -43,19 +44,18 @@ CFLAGS += -std=gnu99 \ -mcpu=$(CPU) \ -mtune=$(CPU) \ -mfpu=$(FPU) \ - -mfloat-abi=hard \ - -D$(CFLAGS_MCU) + -mfloat-abi=hard CFLAGS += -D$(MCU) \ -D$(TARGET) \ -DARM_NN_TRUNCATE \ -D__FPU_PRESENT=1 \ -D__VFP_FP__ \ + -DUSE_FULL_LL_DRIVER \ -DHSE_VALUE=$(OMV_HSE_VALUE)\ -DOMV_VTOR_BASE=$(OMV_FIRM_BASE) \ - -DSTM32_HAL_H=$(HAL_INC) \ - -DCMSIS_MCU_H=$(CMSIS_MCU_H) \ - -DUSE_FULL_LL_DRIVER \ + -DCMSIS_MCU_H='<$(MCU_LOWER).h>' \ + -DSTM32_HAL_H='' \ $(OMV_BOARD_CFLAGS) # Linker Flags diff --git a/src/omv/ports/stm32/omv_spi.c b/src/omv/ports/stm32/omv_spi.c index 3dc3787d8..b03df673d 100644 --- a/src/omv/ports/stm32/omv_spi.c +++ b/src/omv/ports/stm32/omv_spi.c @@ -95,7 +95,7 @@ DEFINE_SPI_INSTANCE(6) static omv_spi_t *omv_spi_descr_all[6] = { NULL }; static uint32_t omv_spi_clocksource(SPI_TypeDef *spi) { - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) if (spi == SPI1 || spi == SPI2 || spi == SPI3) { return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123); } else if (spi == SPI4 || spi == SPI5) { @@ -290,7 +290,7 @@ static int omv_spi_dma_init(omv_spi_t *spi, uint32_t direction, omv_spi_config_t dma_descr->Init.MemBurst = DMA_MBURST_SINGLE; dma_descr->Init.PeriphBurst = DMA_PBURST_SINGLE; dma_descr->Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) dma_descr->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; #else dma_descr->Init.PeriphDataAlignment = (config->datasize == 8) ? DMA_PDATAALIGN_BYTE : DMA_PDATAALIGN_HALFWORD; @@ -336,9 +336,9 @@ static int omv_spi_bus_init(omv_spi_t *spi, omv_spi_config_t *config) { spi_descr->Init.CLKPhase = config->clk_pha; spi_descr->Init.CLKPolarity = config->clk_pol; spi_descr->Init.BaudRatePrescaler = omv_spi_prescaler(spi_descr->Instance, config->baudrate); - #if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7) + #if defined(STM32F7) || defined(STM32H7) spi_descr->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) spi_descr->Init.NSSPolarity = (config->nss_pol == 0) ? SPI_NSS_POLARITY_LOW : SPI_NSS_POLARITY_HIGH; spi_descr->Init.FifoThreshold = SPI_FIFO_THRESHOLD_04DATA; spi_descr->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; @@ -356,7 +356,7 @@ static int omv_spi_bus_init(omv_spi_t *spi, omv_spi_config_t *config) { } else if (config->bus_mode == OMV_SPI_BUS_RX) { spi_descr->Init.Direction = SPI_DIRECTION_2LINES_RXONLY; } else { - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) spi_descr->Init.Direction = SPI_DIRECTION_2LINES_TXONLY; #else spi_descr->Init.Direction = SPI_DIRECTION_1LINE; diff --git a/src/omv/ports/stm32/stm32fxxx_hal_msp.c b/src/omv/ports/stm32/stm32fxxx_hal_msp.c index e0389a067..400a6b26c 100644 --- a/src/omv/ports/stm32/stm32fxxx_hal_msp.c +++ b/src/omv/ports/stm32/stm32fxxx_hal_msp.c @@ -92,7 +92,7 @@ void HAL_MspInit(void) { #endif // defined(OMV_DMA_MEMORY) // Enable I/D cache. - #if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7) + #if defined(STM32F7) || defined(STM32H7) #ifdef OMV_DISABLE_CACHE // Disable caches for testing. SCB_DisableICache(); @@ -147,7 +147,7 @@ void HAL_MspInit(void) { __DMA1_CLK_ENABLE(); __DMA2_CLK_ENABLE(); - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) // MDMA clock. __HAL_RCC_MDMA_CLK_ENABLE(); NVIC_SetPriority(MDMA_IRQn, IRQ_PRI_MDMA); @@ -212,7 +212,7 @@ void HAL_MspInit(void) { omv_gpio_write(OMV_FIR_LEPTON_POWER_PIN, 0); #endif - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) // This disconnects PA0/PA1 from PA0_C/PA1_C. // PA0_C/PA1_C connect to ADC1/2 Channels P0/P1 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA0, SYSCFG_SWITCH_PA0_OPEN); @@ -435,7 +435,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { return; } - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) omv_gpio_config(spi_pins.sclk_pin, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_HIGH, -1); #else // The STM32F4 and STM32F7 don't set the initial state of the clock line until transmitting the @@ -453,7 +453,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { } else { if (hspi->Init.Mode == SPI_MODE_MASTER) { omv_gpio_config(spi_pins.ssel_pin, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_HIGH, -1); - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) if (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW) { omv_gpio_write(spi_pins.ssel_pin, 1); } else { diff --git a/src/omv/ports/stm32/uvc/src/usbd_conf.c b/src/omv/ports/stm32/uvc/src/usbd_conf.c index f0b41223e..45465f77e 100644 --- a/src/omv/ports/stm32/uvc/src/usbd_conf.c +++ b/src/omv/ports/stm32/uvc/src/usbd_conf.c @@ -80,7 +80,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); #endif - #if defined(MCU_SERIES_H7) + #if defined(STM32H7) // Keep USB clock running during sleep or else __WFI() will disable the USB __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE(); __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();