Portenta: Fix PLL1.

* Generate 50MHz for SDMMC1 and SDMMC2.
This commit is contained in:
iabdalkader 2020-10-06 22:15:06 +02:00
parent a35f32525c
commit b0364b112e

View File

@ -81,7 +81,7 @@
#define OMV_OSC_PLL1M (5)
#define OMV_OSC_PLL1N (160)
#define OMV_OSC_PLL1P (2)
#define OMV_OSC_PLL1Q (20)
#define OMV_OSC_PLL1Q (16)
#define OMV_OSC_PLL1R (2)
#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)