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Make USB clock source configurable for H7 boards.
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519b9d327b
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@ -278,13 +278,13 @@ void SystemClock_Config(void)
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|RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB
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|RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC
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|RCC_PERIPHCLK_RNG;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
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PeriphClkInitStruct.UsbClockSelection = OMV_OSC_USB_CLKSOURCE;
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PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
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PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
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PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
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PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
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PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE;
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PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE;
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PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_CLKSOURCE;
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PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_CLKSOURCE;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
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@ -106,8 +106,9 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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@ -110,8 +110,9 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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@ -80,8 +80,9 @@
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#define OMV_CORE_VBAT "3.3"
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL2
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL2
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
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//PLL1 48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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@ -107,8 +107,9 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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