Make USB clock source configurable for H7 boards.

This commit is contained in:
iabdalkader 2020-09-26 16:43:49 +02:00
parent 519b9d327b
commit b07f62cc61
5 changed files with 15 additions and 11 deletions

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@ -278,13 +278,13 @@ void SystemClock_Config(void)
|RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB
|RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC
|RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
PeriphClkInitStruct.UsbClockSelection = OMV_OSC_USB_CLKSOURCE;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE;
PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE;
PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_CLKSOURCE;
PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_CLKSOURCE;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;

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@ -106,8 +106,9 @@
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)

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@ -110,8 +110,9 @@
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)

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@ -80,8 +80,9 @@
#define OMV_CORE_VBAT "3.3"
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL2
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL2
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
//PLL1 48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (3)

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@ -107,8 +107,9 @@
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)