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Merge pull request #901 from kwagyeman/kwabena/add_openmvpurethermal
Made clock sources for the SPI123/ADC adjustable
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commit
b2a92511e7
@ -98,73 +98,73 @@ void SystemInit(void)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= CONFIG_RCC_CR_1ST;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t) CONFIG_RCC_CR_2ND;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(MCU_SERIES_H7)
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x00000000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x00000000;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x00000000;
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x00000000;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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#endif // defined(MCU_SERIES_H7)
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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RCC->CIR = 0x00000000;
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#elif defined(MCU_SERIES_L4) || defined(MCU_SERIES_H7)
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RCC->CIER = 0x00000000;
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#endif
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#if defined(MCU_SERIES_H7)
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#endif // defined(MCU_SERIES_H7)
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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@ -280,10 +280,11 @@ void SystemClock_Config(void)
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PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
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PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
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PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL3;
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PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL3;
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PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE;
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PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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// Initialization Error
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@ -102,6 +102,10 @@
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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@ -106,6 +106,10 @@
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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@ -70,6 +70,9 @@
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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@ -80,9 +83,6 @@
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// PLL2 180MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (72)
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@ -103,6 +103,10 @@
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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