Merge pull request #901 from kwagyeman/kwabena/add_openmvpurethermal

Made clock sources for the SPI123/ADC adjustable
This commit is contained in:
Ibrahim Abd Elkader 2020-09-21 02:32:27 +02:00 committed by GitHub
commit b2a92511e7
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 37 additions and 24 deletions

View File

@ -280,10 +280,11 @@ void SystemClock_Config(void)
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL3;
PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL3;
PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE;
PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
// Initialization Error

View File

@ -102,6 +102,10 @@
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)

View File

@ -106,6 +106,10 @@
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)

View File

@ -70,6 +70,9 @@
// FB Heap Block Size
#define OMV_UMM_BLOCK_SIZE 256
// Core VBAT for selftests
#define OMV_CORE_VBAT "3.0"
//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (5)
#define OMV_OSC_PLL1N (160)
@ -80,9 +83,6 @@
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
#define OMV_OSC_PLL1FRAC (0)
// Core VBAT for selftests
#define OMV_CORE_VBAT "3.0"
// PLL2 180MHz for FMC and QSPI.
#define OMV_OSC_PLL2M (5)
#define OMV_OSC_PLL2N (72)
@ -103,6 +103,10 @@
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)