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Merge pull request #901 from kwagyeman/kwabena/add_openmvpurethermal
Made clock sources for the SPI123/ADC adjustable
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commit
b2a92511e7
@ -280,10 +280,11 @@ void SystemClock_Config(void)
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PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
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PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
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PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL3;
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PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL3;
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PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE;
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PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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// Initialization Error
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@ -102,6 +102,10 @@
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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@ -106,6 +106,10 @@
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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@ -70,6 +70,9 @@
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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@ -80,9 +83,6 @@
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// PLL2 180MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (72)
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@ -103,6 +103,10 @@
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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