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Add SDRAM driver
* Add SDRAM driver * Add SDRAM to linker script * Add FMC drivers to Makefile
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174
src/omv/sdram.c
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174
src/omv/sdram.c
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#include <std.h>
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#include <stdbool.h>
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#include <stm32f4xx_hal.h>
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#include "mdefs.h"
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#include "pincfg.h"
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#include "systick.h"
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//#include "sdram.h"
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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static SDRAM_HandleTypeDef hsdram;
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static FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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static FMC_SDRAM_CommandTypeDef command;
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static void sdram_init_sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command);
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extern void __fatal_error(const char *msg);
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bool sdram_init()
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{
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/* SDRAM device configuration */
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hsdram.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
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/* TMRD: 2 Clock cycles */
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SDRAM_Timing.LoadToActiveDelay = 2;
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/* TXSR: min=70ns (6x11.90ns) */
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SDRAM_Timing.ExitSelfRefreshDelay = 7;
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/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
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SDRAM_Timing.SelfRefreshTime = 4;
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/* TRC: min=63 (6x11.90ns) */
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SDRAM_Timing.RowCycleDelay = 7;
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/* TWR: 2 Clock cycles */
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SDRAM_Timing.WriteRecoveryTime = 2;
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/* TRP: 15ns => 2x11.90ns */
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SDRAM_Timing.RPDelay = 2;
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/* TRCD: 15ns => 2x11.90ns */
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SDRAM_Timing.RCDDelay = 2;
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hsdram.Init.SDBank = FMC_SDRAM_BANK1;
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hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_10;
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hsdram.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;
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hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
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hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
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hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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/* Initialize the SDRAM controller */
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if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) {
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return false;
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}
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/* Program the SDRAM external device */
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sdram_init_sequence(&hsdram, &command);
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return true;
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}
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static void sdram_init_sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
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{
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__IO uint32_t tmpmrd =0;
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/* Step 3: Configure a clock configuration enable command */
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Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 4: Insert 100 ms delay */
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HAL_Delay(100);
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/* Step 5: Configure a PALL (precharge all) command */
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Command->CommandMode = FMC_SDRAM_CMD_PALL;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 6 : Configure a Auto-Refresh command */
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Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 4;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 7: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 8: Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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/* Set the device refresh counter */
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HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
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}
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bool DISABLE_OPT sdram_test()
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{
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uint8_t pattern = 0xAA;
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uint8_t antipattern = 0x55;
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uint32_t mem_size = (16*1024*1024);
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uint8_t * const mem_base = (uint8_t*)0xC0000000;
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printf("sdram test...\n");
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/* test data bus */
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for (uint8_t i=1; i; i<<=1) {
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*mem_base = i;
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if (*mem_base != i) {
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printf("data bus lines test failed! data (%d)\n", i);
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BREAK();
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}
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}
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/* test address bus */
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/* Check individual address lines */
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for (uint32_t i=1; i<mem_size; i<<=1) {
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mem_base[i] = pattern;
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if (mem_base[i] != pattern) {
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printf("address bus lines test failed! address (%p)\n", &mem_base[i]);
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BREAK();
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}
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}
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/* Check for aliasing (overlaping addresses) */
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for (uint32_t i=1; i<mem_size; i<<=1) {
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mem_base[i] = antipattern;
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for (uint32_t p=i<<1; p<mem_size; p<<=1) {
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if (mem_base[p] != pattern) {
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printf("address bus overlap %p %p\n", &mem_base[i], &mem_base[p]);
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BREAK();
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}
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}
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}
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/* test all ram cells */
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for (uint32_t i=0; i<mem_size; i++) {
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mem_base[i] = pattern;
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if (mem_base[i] != pattern) {
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printf("address bus test failed! address (%p)\n", &mem_base[i]);
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BREAK();
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}
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}
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printf("sdram test passed\n");
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return true;
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}
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5
src/omv/sdram.h
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5
src/omv/sdram.h
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#ifndef __SDRAM_H__
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#define __SDRAM_H__
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bool sdram_init();
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bool sdram_test();
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#endif //__SDRAM_H__
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@ -87,6 +87,8 @@ void HAL_MspInit(void)
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GPIO_InitStructure.Speed = GPIO_SPEED_LOW;
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GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
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HAL_GPIO_Init(SD_CD_PORT, &GPIO_InitStructure);
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}
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void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
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@ -227,6 +229,88 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
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}
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}
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void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
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{
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/* Enable SDIO clock */
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__SDIO_CLK_ENABLE();
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/* SDIO GPIOs configuration */
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.Pull = GPIO_NOPULL;
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GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM;
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GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.Alternate = GPIO_AF12_SDIO;
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GPIO_InitStructure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
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GPIO_InitStructure.Pin = GPIO_PIN_2;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
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}
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void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
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{
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__SDIO_CLK_DISABLE();
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}
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void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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{
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/* Enable FMC clock */
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__FMC_CLK_ENABLE();
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/* Enable GPIO clocks */
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__GPIOC_CLK_ENABLE();
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__GPIOD_CLK_ENABLE();
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__GPIOE_CLK_ENABLE();
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__GPIOF_CLK_ENABLE();
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__GPIOG_CLK_ENABLE();
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/* SDRAM pins assignment
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+-------------------+--------------------+--------------------+
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| FMC_D0 <-> PD14 | FMC_A0 <-> PF0 | FMC_CLK <-> PG8 |
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| FMC_D1 <-> PD15 | FMC_A1 <-> PF1 | FMC_CLKE <-> PC3 |
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| FMC_D2 <-> PD0 | FMC_A2 <-> PF2 | FMC_WE <-> PC0 |
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| FMC_D3 <-> PD1 | FMC_A3 <-> PF3 | FMC_CS <-> PC2 |
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| FMC_D4 <-> PE7 | FMC_A4 <-> PF4 | FMC_DQM <-> PE0 |
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| FMC_D5 <-> PE8 | FMC_A5 <-> PF5 | FMC_BA0 <-> PG4 |
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| FMC_D6 <-> PE9 | FMC_A6 <-> PF12 | FMC_BA1 <-> PG5 |
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| FMC_D7 <-> PE10 | FMC_A7 <-> PF13 | FMC_RAS <-> PF11 |
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| | FMC_A8 <-> PF14 | FMC_CAS <-> PG15 |
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| | FMC_A9 <-> PF15 | |
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| | FMC_A10 <-> PG0 | |
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| | FMC_A11 <-> PG1 | |
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+-------------------+--------------------+--------------------+ */
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/* SDRAM GPIO configuration */
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GPIO_InitTypeDef GPIO_Init_Structure;
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GPIO_Init_Structure.Pull = GPIO_NOPULL;
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GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
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GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
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GPIO_Init_Structure.Alternate = GPIO_AF12_FMC;
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/* GPIOC configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3;
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HAL_GPIO_Init(GPIOC, &GPIO_Init_Structure);
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/* GPIOD configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure);
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/* GPIOE configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10;
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HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure);
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/* GPIOF configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure);
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/* GPIOG configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 |
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GPIO_PIN_8 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure);
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}
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void HAL_MspDeInit(void)
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{
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@ -14,6 +14,7 @@ MEMORY
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FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 1984K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
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CCM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K
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SDRAM (xrw) : ORIGIN = 0xC0000000, LENGTH = 16M
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}
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/* Highest address of the user mode stack */
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@ -22,12 +22,16 @@ stm32f4xx_hal_rcc_ex.c\
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stm32f4xx_hal_rng.c\
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stm32f4xx_hal_rtc.c\
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stm32f4xx_hal_rtc_ex.c\
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stm32f4xx_hal_sd.c\
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stm32f4xx_hal_sdram.c\
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stm32f4xx_hal_spi.c\
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stm32f4xx_hal_tim.c\
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stm32f4xx_hal_tim_ex.c\
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stm32f4xx_hal_uart.c\
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stm32f4xx_hal_usart.c\
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stm32f4xx_ll_usb.c\
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stm32f4xx_ll_sdmmc.c\
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stm32f4xx_ll_fmc.c\
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syscalls.c\
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)
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