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https://github.com/openmv/openmv.git
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Merge pull request #2476 from openmv/clean_flags
misc: Clean up board Make flags.
This commit is contained in:
commit
bc83f49d10
@ -38,7 +38,7 @@
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#if OMV_BOOT_AXI_FLASH_ENABLE
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#if OMV_BOOT_AXI_FLASH_ENABLE
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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#define FLASH_WORD_SIZE 32
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#define FLASH_WORD_SIZE 32
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#define FLASH_WORD_GET(x) ((uint32_t) x)
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#define FLASH_WORD_GET(x) ((uint32_t) x)
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#else
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#else
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@ -46,23 +46,23 @@
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#define FLASH_WORD_GET(x) *((uint32_t *) x)
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#define FLASH_WORD_GET(x) *((uint32_t *) x)
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#endif
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#endif
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#if defined(MCU_SERIES_F7)
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#if defined(STM32F7)
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#define FLASH_FLAG_PGSERR (FLASH_FLAG_ERSERR)
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#define FLASH_FLAG_PGSERR (FLASH_FLAG_ERSERR)
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#endif
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#endif
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#if defined(MCU_SERIES_F4)
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#if defined(STM32F4)
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static const uint32_t flash_sectors[] = {
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static const uint32_t flash_sectors[] = {
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0x08000000, 0x08004000, 0x08008000, 0x0800C000,
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0x08000000, 0x08004000, 0x08008000, 0x0800C000,
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0x08010000, 0x08020000, 0x08040000, 0x08060000,
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0x08010000, 0x08020000, 0x08040000, 0x08060000,
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0x08080000, 0x080A0000, 0x080C0000, 0x080E0000
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0x08080000, 0x080A0000, 0x080C0000, 0x080E0000
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};
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};
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#elif defined(MCU_SERIES_F7)
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#elif defined(STM32F7)
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static const uint32_t flash_sectors[] = {
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static const uint32_t flash_sectors[] = {
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0x08000000, 0x08008000, 0x08010000, 0x08018000,
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0x08000000, 0x08008000, 0x08010000, 0x08018000,
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0x08020000, 0x08040000, 0x08080000, 0x080C0000,
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0x08020000, 0x08040000, 0x08080000, 0x080C0000,
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0x08100000, 0x08140000, 0x08180000, 0x081C0000
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0x08100000, 0x08140000, 0x08180000, 0x081C0000
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};
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};
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#elif defined(MCU_SERIES_H7)
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#elif defined(STM32H7)
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static const uint32_t flash_sectors[] = {
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static const uint32_t flash_sectors[] = {
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0x08000000, 0x08020000, 0x08040000, 0x08060000,
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0x08000000, 0x08020000, 0x08040000, 0x08060000,
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0x08080000, 0x080A0000, 0x080C0000, 0x080E0000,
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0x08080000, 0x080A0000, 0x080C0000, 0x080E0000,
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@ -82,9 +82,9 @@ static int axi_flash_erase(uint32_t sector) {
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EraseInitStruct.NbSectors = 1;
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EraseInitStruct.NbSectors = 1;
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EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
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EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
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EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3;
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EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3;
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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EraseInitStruct.Sector = sector;
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EraseInitStruct.Sector = sector;
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#elif defined(MCU_SERIES_H7)
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#elif defined(STM32H7)
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EraseInitStruct.Sector = (sector % 8);
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EraseInitStruct.Sector = (sector % 8);
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EraseInitStruct.Banks = (sector < 8) ? FLASH_BANK_1 : FLASH_BANK_2;
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EraseInitStruct.Banks = (sector < 8) ? FLASH_BANK_1 : FLASH_BANK_2;
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#endif
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#endif
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@ -92,7 +92,7 @@ static int axi_flash_erase(uint32_t sector) {
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// Unlock flash
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// Unlock flash
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HAL_FLASH_Unlock();
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HAL_FLASH_Unlock();
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2);
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2);
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#else
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#else
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
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@ -30,11 +30,14 @@
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# Include OpenMV board config first to set the port.
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# Include OpenMV board config first to set the port.
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include $(OMV_BOARD_CONFIG_DIR)/omv_boardconfig.mk
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include $(OMV_BOARD_CONFIG_DIR)/omv_boardconfig.mk
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FIRMWARE := bootloader
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LDSCRIPT ?= stm32
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LDSCRIPT ?= stm32
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SYSTEM ?= st/system_stm32fxxx
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SYSTEM ?= st/system_stm32fxxx
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STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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FIRMWARE := bootloader
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MCU_LOWER = $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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MCU_SERIES_LOWER := $(shell echo $(MCU_SERIES) | tr '[:upper:]' '[:lower:]')
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MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
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MCU_SERIES_UPPER := $(shell echo $(MCU_SERIES) | tr '[:lower:]' '[:upper:]')
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HAL_DIR = hal/stm32/$(MCU_SERIES)
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# Compiler Flags
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# Compiler Flags
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CFLAGS += -std=gnu99 \
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CFLAGS += -std=gnu99 \
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@ -51,8 +54,7 @@ CFLAGS += -std=gnu99 \
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-mcpu=$(CPU) \
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-mcpu=$(CPU) \
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-mtune=$(CPU) \
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-mtune=$(CPU) \
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-mfpu=$(FPU) \
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-mfpu=$(FPU) \
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-mfloat-abi=hard \
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-mfloat-abi=hard
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-D$(CFLAGS_MCU)
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# Linker Flags
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# Linker Flags
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LDFLAGS = -mthumb \
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LDFLAGS = -mthumb \
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@ -73,9 +75,10 @@ CFLAGS += -D$(MCU) \
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-DHSE_VALUE=$(OMV_HSE_VALUE)\
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-DHSE_VALUE=$(OMV_HSE_VALUE)\
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-DOMV_VTOR_BASE=$(OMV_BOOT_BASE) \
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-DOMV_VTOR_BASE=$(OMV_BOOT_BASE) \
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-DOMV_BOOT_JUMP=$(OMV_FIRM_BASE) \
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-DOMV_BOOT_JUMP=$(OMV_FIRM_BASE) \
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-DSTM32_HAL_H=$(HAL_INC) \
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-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
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-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
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-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
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-DUSE_FULL_LL_DRIVER \
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-DUSE_FULL_LL_DRIVER \
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-DCFG_TUSB_MCU=OPT_MCU_STM32$(MCU_SERIES_UPPER) \
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$(OMV_BOARD_CFLAGS)
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$(OMV_BOARD_CFLAGS)
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CFLAGS += -I$(OMV_BOARD_CONFIG_DIR) \
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CFLAGS += -I$(OMV_BOARD_CONFIG_DIR) \
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@ -115,23 +118,23 @@ SRC_C += $(addprefix $(CMSIS_DIR)/src/,\
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)
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)
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SRC_C += $(addprefix $(HAL_DIR)/src/,\
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SRC_C += $(addprefix $(HAL_DIR)/src/,\
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$(MCU_SERIES_LOWER)_hal.c \
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stm32$(MCU_SERIES)xx_hal.c \
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$(MCU_SERIES_LOWER)_hal_cortex.c \
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stm32$(MCU_SERIES)xx_hal_cortex.c \
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$(MCU_SERIES_LOWER)_hal_gpio.c \
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stm32$(MCU_SERIES)xx_hal_gpio.c \
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$(MCU_SERIES_LOWER)_hal_pwr.c \
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stm32$(MCU_SERIES)xx_hal_pwr.c \
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$(MCU_SERIES_LOWER)_hal_pwr_ex.c \
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stm32$(MCU_SERIES)xx_hal_pwr_ex.c \
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$(MCU_SERIES_LOWER)_hal_rcc.c \
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stm32$(MCU_SERIES)xx_hal_rcc.c \
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$(MCU_SERIES_LOWER)_hal_rcc_ex.c \
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stm32$(MCU_SERIES)xx_hal_rcc_ex.c \
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$(MCU_SERIES_LOWER)_hal_rng.c \
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stm32$(MCU_SERIES)xx_hal_rng.c \
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$(MCU_SERIES_LOWER)_ll_rcc.c \
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stm32$(MCU_SERIES)xx_ll_rcc.c \
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$(MCU_SERIES_LOWER)_ll_usb.c \
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stm32$(MCU_SERIES)xx_ll_usb.c \
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)
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)
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),STM32F4xx STM32F7xx STM32H7xx))
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 h7))
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SRC_C += $(addprefix $(HAL_DIR)/src/,\
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SRC_C += $(addprefix $(HAL_DIR)/src/,\
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$(MCU_SERIES_LOWER)_hal_qspi.c \
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stm32$(MCU_SERIES)xx_hal_qspi.c \
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$(MCU_SERIES_LOWER)_hal_flash.c \
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stm32$(MCU_SERIES)xx_hal_flash.c \
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$(MCU_SERIES_LOWER)_hal_flash_ex.c \
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stm32$(MCU_SERIES)xx_hal_flash_ex.c \
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)
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)
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endif
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endif
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@ -61,7 +61,7 @@
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uint32_t SystemCoreClock = 16000000;
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uint32_t SystemCoreClock = 16000000;
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extern void __fatal_error(const char *msg);
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extern void __fatal_error(const char *msg);
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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#define SRAM_BASE D1_AXISRAM_BASE
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#define SRAM_BASE D1_AXISRAM_BASE
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#define FLASH_BASE FLASH_BANK1_BASE
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#define FLASH_BASE FLASH_BANK1_BASE
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@ -73,7 +73,7 @@ extern void __fatal_error(const char *msg);
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uint32_t SystemD2Clock = 64000000;
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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#elif defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#elif defined(STM32F4) || defined(STM32F7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (0xFEF6FFFF)
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#define CONFIG_RCC_CR_2ND (0xFEF6FFFF)
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@ -102,7 +102,6 @@ void SystemInit(void)
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signal is detectable by the CPU after a WFI/WFE instruction. */
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signal is detectable by the CPU after a WFI/WFE instruction. */
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//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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#if !defined(CORE_CM4)
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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/* Set HSION bit */
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RCC->CR |= CONFIG_RCC_CR_1ST;
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RCC->CR |= CONFIG_RCC_CR_1ST;
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@ -116,7 +115,7 @@ void SystemInit(void)
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/* Reset PLLCFGR register */
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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/* Reset D1CFGR register */
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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RCC->D1CFGR = 0x00000000;
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@ -146,39 +145,37 @@ void SystemInit(void)
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/* Reset PLL3FRACR register */
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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RCC->PLL3FRACR = 0x00000000;
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#endif // defined(MCU_SERIES_H7)
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#endif // defined(STM32H7)
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/* Reset HSEBYP bit */
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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/* Disable all interrupts */
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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RCC->CIR = 0x00000000;
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RCC->CIR = 0x00000000;
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#elif defined(MCU_SERIES_L4) || defined(MCU_SERIES_H7)
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#elif defined(STM32L4) || defined(STM32H7)
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RCC->CIER = 0x00000000;
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RCC->CIER = 0x00000000;
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#endif
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#endif
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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// See Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
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// See Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#endif // defined(MCU_SERIES_H7)
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#endif // defined(STM32H7)
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
|
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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|
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#if !defined(NDEBUG)
|
#if !defined(NDEBUG)
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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DBGMCU->CR |= DBGMCU_CR_DBG_SLEEP;
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DBGMCU->CR |= DBGMCU_CR_DBG_SLEEP;
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#elif defined(MCU_SERIES_H7)
|
#elif defined(STM32H7)
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DBGMCU->CR |= DBGMCU_CR_DBG_SLEEPD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_SLEEPD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STOPD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STOPD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
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#endif
|
#endif
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#endif
|
#endif
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|
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#endif // !defined(CORE_CM4)
|
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|
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||||||
/* Configure the Vector Table location add offset address ------------------*/
|
/* Configure the Vector Table location add offset address ------------------*/
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SCB->VTOR = OMV_VTOR_BASE;
|
SCB->VTOR = OMV_VTOR_BASE;
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}
|
}
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@ -187,11 +184,11 @@ void SystemClock_Config(void)
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|||||||
{
|
{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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||||||
#endif
|
#endif
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||||||
|
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||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
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||||||
/* Supply configuration update enable */
|
/* Supply configuration update enable */
|
||||||
HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY);
|
HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY);
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#else
|
#else
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@ -202,7 +199,7 @@ void SystemClock_Config(void)
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|||||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||||
clocked below the maximum system frequency, to update the voltage scaling value
|
clocked below the maximum system frequency, to update the voltage scaling value
|
||||||
regarding system frequency refer to product datasheet. */
|
regarding system frequency refer to product datasheet. */
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
// Enable VSCALE0 for revision V devices.
|
// Enable VSCALE0 for revision V devices.
|
||||||
if (HAL_GetREVID() >= 0x2003) {
|
if (HAL_GetREVID() >= 0x2003) {
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||||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
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@ -215,7 +212,7 @@ void SystemClock_Config(void)
|
|||||||
}
|
}
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|
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||||||
// Wait for PWR_FLAG_VOSRDY
|
// Wait for PWR_FLAG_VOSRDY
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET) {
|
while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET) {
|
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}
|
}
|
||||||
#endif
|
#endif
|
||||||
@ -264,7 +261,7 @@ void SystemClock_Config(void)
|
|||||||
RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;
|
RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;
|
||||||
RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P;
|
RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P;
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
// Override PLL1 frequency for revision Y devices,
|
// Override PLL1 frequency for revision Y devices,
|
||||||
// with maximum frequency of 400MHz CPU 200MHz Bus.
|
// with maximum frequency of 400MHz CPU 200MHz Bus.
|
||||||
if (HAL_GetREVID() < 0x2003) {
|
if (HAL_GetREVID() < 0x2003) {
|
||||||
@ -314,7 +311,7 @@ void SystemClock_Config(void)
|
|||||||
PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC;
|
PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
|
|
||||||
#if !defined(OMV_OMVPT_ERRATA_RTC)
|
#if !defined(OMV_OMVPT_ERRATA_RTC)
|
||||||
PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_RTC;
|
PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_RTC;
|
||||||
@ -385,9 +382,9 @@ void SystemClock_Config(void)
|
|||||||
// Initialization Error
|
// Initialization Error
|
||||||
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
|
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
|
||||||
}
|
}
|
||||||
#endif // defined(MCU_SERIES_H7)
|
#endif // defined(STM32H7)
|
||||||
|
|
||||||
#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
|
#if defined(STM32F4) || defined(STM32F7)
|
||||||
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
|
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
|
||||||
// Initialization Error
|
// Initialization Error
|
||||||
__fatal_error("HAL_PWREx_EnableOverDrive");
|
__fatal_error("HAL_PWREx_EnableOverDrive");
|
||||||
@ -395,7 +392,7 @@ void SystemClock_Config(void)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
|
/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
|
||||||
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
|
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
|
||||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||||
@ -418,7 +415,7 @@ void SystemClock_Config(void)
|
|||||||
__fatal_error("HAL_RCC_ClockConfig");
|
__fatal_error("HAL_RCC_ClockConfig");
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
// Activate CSI clock mondatory for I/O Compensation Cell
|
// Activate CSI clock mondatory for I/O Compensation Cell
|
||||||
__HAL_RCC_CSI_ENABLE() ;
|
__HAL_RCC_CSI_ENABLE() ;
|
||||||
|
|
||||||
|
|||||||
@ -2,10 +2,6 @@ MCU=STM32H747xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/h7
|
|
||||||
HAL_INC='<stm32h7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32h747xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_H7
|
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_BASE=0x08040000
|
||||||
OMV_HSE_VALUE=16000000
|
OMV_HSE_VALUE=16000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
|
|||||||
@ -3,17 +3,15 @@ CPU=cortex-m4
|
|||||||
FPU=fpv4-sp-d16
|
FPU=fpv4-sp-d16
|
||||||
PORT=nrf
|
PORT=nrf
|
||||||
SD=s140
|
SD=s140
|
||||||
HAL_DIR=hal/nrfx
|
|
||||||
CMSIS_MCU_H='<nrf52840.h>'
|
|
||||||
NRF_SOFTDEV=s140_nrf52_6.1.1
|
NRF_SOFTDEV=s140_nrf52_6.1.1
|
||||||
CFLAGS_MCU=NRF52_SERIES
|
|
||||||
OMV_FIRM_BASE=0x00026000
|
OMV_FIRM_BASE=0x00026000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
OMV_BOARD_CFLAGS = -DCONFIG_GPIO_AS_PINRESET \
|
OMV_BOARD_CFLAGS = -DNRF52_SERIES \
|
||||||
-DNRF52840_XXAA \
|
-DNRF52840_XXAA \
|
||||||
-DSOFTDEVICE_PRESENT \
|
-DSOFTDEVICE_PRESENT \
|
||||||
-DBLUETOOTH_SD_DEBUG=1 \
|
-DBLUETOOTH_SD_DEBUG=1 \
|
||||||
-DBLUETOOTH_SD=140
|
-DBLUETOOTH_SD=140 \
|
||||||
|
-DCONFIG_GPIO_AS_PINRESET
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
MICROPY_PY_ULAB=1
|
MICROPY_PY_ULAB=1
|
||||||
MICROPY_PY_AUDIO=1
|
MICROPY_PY_AUDIO=1
|
||||||
|
|||||||
@ -2,10 +2,6 @@ MCU=STM32H747xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/h7
|
|
||||||
HAL_INC='<stm32h7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32h747xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_H7
|
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_BASE=0x08040000
|
||||||
OMV_HSE_VALUE=25000000
|
OMV_HSE_VALUE=25000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
|
|||||||
@ -2,10 +2,6 @@ MCU=STM32H747xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/h7
|
|
||||||
HAL_INC='<stm32h7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32h747xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_H7
|
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_BASE=0x08040000
|
||||||
OMV_HSE_VALUE=25000000
|
OMV_HSE_VALUE=25000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
|
|||||||
@ -2,16 +2,13 @@ MCU=STM32F407xx
|
|||||||
CPU=cortex-m4
|
CPU=cortex-m4
|
||||||
FPU=fpv4-sp-d16
|
FPU=fpv4-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/f4
|
|
||||||
HAL_INC='<stm32f4xx_hal.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_F4
|
|
||||||
OMV_BOARD_CFLAGS=-DUSE_USB_FS
|
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_BOOT_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08010000
|
OMV_FIRM_BASE=0x08010000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
OMV_ENABLE_UVC=1
|
OMV_ENABLE_UVC=1
|
||||||
|
OMV_BOARD_CFLAGS=-DUSE_USB_FS
|
||||||
MICROPY_PY_CSI = 1
|
MICROPY_PY_CSI = 1
|
||||||
MICROPY_PY_WINC1500 = 1
|
MICROPY_PY_WINC1500 = 1
|
||||||
$(error "This camera is no longer supported :O Have fun hacking the code $(BRACKET)")
|
$(error "This camera is no longer supported :O Have fun hacking the code $(BRACKET)")
|
||||||
|
|||||||
@ -1,13 +1,7 @@
|
|||||||
MCU=STM32F427xx
|
MCU=STM32F427xx
|
||||||
MCU_SERIES=STM32F4xx
|
|
||||||
CPU=cortex-m4
|
CPU=cortex-m4
|
||||||
FPU=fpv4-sp-d16
|
FPU=fpv4-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/f4
|
|
||||||
HAL_INC='<stm32f4xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32f427xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_F4
|
|
||||||
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32F4
|
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_BOOT_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08010000
|
OMV_FIRM_BASE=0x08010000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
|
|||||||
@ -1,13 +1,7 @@
|
|||||||
MCU=STM32F765xx
|
MCU=STM32F765xx
|
||||||
MCU_SERIES=STM32F7xx
|
|
||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/f7
|
|
||||||
HAL_INC='<stm32f7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32f765xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_F7
|
|
||||||
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32F7
|
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_BOOT_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08020000
|
OMV_FIRM_BASE=0x08020000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
|
|||||||
@ -1,13 +1,7 @@
|
|||||||
MCU=STM32H743xx
|
MCU=STM32H743xx
|
||||||
MCU_SERIES=STM32H7xx
|
|
||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/h7
|
|
||||||
HAL_INC='<stm32h7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32h743xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_H7
|
|
||||||
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
|
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_BOOT_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_BASE=0x08040000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
|
|||||||
@ -1,13 +1,7 @@
|
|||||||
MCU=STM32H743xx
|
MCU=STM32H743xx
|
||||||
MCU_SERIES=STM32H7xx
|
|
||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/h7
|
|
||||||
HAL_INC='<stm32h7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32h743xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_H7
|
|
||||||
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
|
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_BOOT_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_BASE=0x08040000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
|
|||||||
@ -1,13 +1,7 @@
|
|||||||
MCU=STM32H743xx
|
MCU=STM32H743xx
|
||||||
MCU_SERIES=STM32H7xx
|
|
||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
HAL_DIR=hal/stm32/h7
|
|
||||||
HAL_INC='<stm32h7xx_hal.h>'
|
|
||||||
CMSIS_MCU_H='<stm32h743xx.h>'
|
|
||||||
CFLAGS_MCU=MCU_SERIES_H7
|
|
||||||
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
|
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_BOOT_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_BASE=0x08040000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
|
|||||||
@ -1,11 +1,8 @@
|
|||||||
MCU_SERIES = MIMXRT1062
|
MCU=MIMXRT1062DVJ6A
|
||||||
MCU_VARIANT = MIMXRT1062DVJ6A
|
|
||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
FABI=hard
|
FABI=hard
|
||||||
PORT=mimxrt
|
PORT=mimxrt
|
||||||
HAL_DIR=hal/mimxrt/MIMXRT1062
|
|
||||||
CMSIS_MCU_H='<MIMXRT1062.h>'
|
|
||||||
OMV_BOARD_CFLAGS=-DBOARD_FLASH_SIZE=0x800000
|
OMV_BOARD_CFLAGS=-DBOARD_FLASH_SIZE=0x800000
|
||||||
OMV_FIRM_BASE=0x60000000
|
OMV_FIRM_BASE=0x60000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
|
|||||||
1
src/omv/boards/RPI_PICO/omv_boardconfig.mk
Executable file
1
src/omv/boards/RPI_PICO/omv_boardconfig.mk
Executable file
@ -0,0 +1 @@
|
|||||||
|
PORT=rp2
|
||||||
@ -63,16 +63,12 @@ export FROZEN_MANIFEST
|
|||||||
# Export board config variables
|
# Export board config variables
|
||||||
export PORT
|
export PORT
|
||||||
export MCU
|
export MCU
|
||||||
export MCU_SERIES
|
|
||||||
export MCU_VARIANT
|
|
||||||
export MCU_CORE
|
|
||||||
|
|
||||||
# Export Directories
|
# Export Directories
|
||||||
export TOP_DIR
|
export TOP_DIR
|
||||||
export BUILD
|
export BUILD
|
||||||
export TOOLS
|
export TOOLS
|
||||||
export FW_DIR
|
export FW_DIR
|
||||||
export HAL_DIR
|
|
||||||
export BOOT_DIR
|
export BOOT_DIR
|
||||||
export OMV_DIR
|
export OMV_DIR
|
||||||
export CMSIS_DIR
|
export CMSIS_DIR
|
||||||
|
|||||||
@ -21,9 +21,11 @@
|
|||||||
# THE SOFTWARE.
|
# THE SOFTWARE.
|
||||||
|
|
||||||
# Set startup and system files for CMSIS Makefile.
|
# Set startup and system files for CMSIS Makefile.
|
||||||
|
MCU_SERIES := $(shell echo $(MCU) | cut -c1-10)
|
||||||
|
LDSCRIPT ?= mimxrt
|
||||||
SYSTEM ?= mimxrt/system_$(MCU_SERIES)
|
SYSTEM ?= mimxrt/system_$(MCU_SERIES)
|
||||||
STARTUP ?= mimxrt/startup_$(MCU_SERIES)
|
STARTUP ?= mimxrt/startup_$(MCU_SERIES)
|
||||||
LDSCRIPT ?= mimxrt
|
HAL_DIR ?= hal/mimxrt/$(MCU_SERIES)
|
||||||
|
|
||||||
# Compiler Flags
|
# Compiler Flags
|
||||||
# TODO: -Wdouble-promotion
|
# TODO: -Wdouble-promotion
|
||||||
@ -42,7 +44,7 @@ CFLAGS += -std=gnu99 \
|
|||||||
-mfpu=$(FPU)
|
-mfpu=$(FPU)
|
||||||
|
|
||||||
# TODO: FIX HSE
|
# TODO: FIX HSE
|
||||||
CFLAGS += -DCPU_$(MCU_VARIANT) \
|
CFLAGS += -DCPU_$(MCU) \
|
||||||
-D$(TARGET) \
|
-D$(TARGET) \
|
||||||
-DARM_NN_TRUNCATE \
|
-DARM_NN_TRUNCATE \
|
||||||
-D__FPU_PRESENT=1 \
|
-D__FPU_PRESENT=1 \
|
||||||
@ -54,7 +56,7 @@ CFLAGS += -DCPU_$(MCU_VARIANT) \
|
|||||||
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
|
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
|
||||||
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \
|
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \
|
||||||
-DCPU_HEADER_H='<$(MCU_SERIES).h>' \
|
-DCPU_HEADER_H='<$(MCU_SERIES).h>' \
|
||||||
-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
|
-DCMSIS_MCU_H='<$(MCU_SERIES).h>' \
|
||||||
-DCLOCK_CONFIG_H='<boards/$(MCU_SERIES)_clock_config.h>' \
|
-DCLOCK_CONFIG_H='<boards/$(MCU_SERIES)_clock_config.h>' \
|
||||||
-DCSI_DRIVER_FRAG_MODE=1 \
|
-DCSI_DRIVER_FRAG_MODE=1 \
|
||||||
-D__START=main \
|
-D__START=main \
|
||||||
|
|||||||
@ -21,17 +21,38 @@
|
|||||||
# THE SOFTWARE.
|
# THE SOFTWARE.
|
||||||
|
|
||||||
# Set startup and system files based on MCU.
|
# Set startup and system files based on MCU.
|
||||||
|
LDSCRIPT ?= nrf52xxx
|
||||||
|
HAL_DIR ?= hal/nrfx
|
||||||
SYSTEM ?= nrf/system_nrf52840
|
SYSTEM ?= nrf/system_nrf52840
|
||||||
STARTUP ?= nrf/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
STARTUP ?= nrf/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
||||||
LDSCRIPT ?= nrf52xxx
|
MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
||||||
|
|
||||||
export SD_DIR = $(TOP_DIR)/drivers/nrf
|
export SD_DIR = $(TOP_DIR)/drivers/nrf
|
||||||
|
|
||||||
# Compiler Flags
|
# Compiler Flags
|
||||||
CFLAGS += -std=gnu99 -Wall -Werror -Warray-bounds -mthumb -nostartfiles -fdata-sections -ffunction-sections
|
CFLAGS += -std=gnu99 \
|
||||||
CFLAGS += -D$(MCU) -D$(CFLAGS_MCU) -DARM_NN_TRUNCATE -D__FPU_PRESENT=1 -D__VFP_FP__ -D$(TARGET)\
|
-Wall \
|
||||||
-fsingle-precision-constant -Wdouble-promotion -mcpu=$(CPU) -mtune=$(CPU) -mfpu=$(FPU) -mfloat-abi=hard\
|
-Werror \
|
||||||
-DCMSIS_MCU_H=$(CMSIS_MCU_H) -DMP_PORT_NO_SOFTTIMER
|
-Warray-bounds \
|
||||||
CFLAGS += $(OMV_BOARD_CFLAGS)
|
-mthumb \
|
||||||
|
-nostartfiles \
|
||||||
|
-fdata-sections \
|
||||||
|
-ffunction-sections
|
||||||
|
|
||||||
|
CFLAGS += -D$(MCU) \
|
||||||
|
-DARM_NN_TRUNCATE \
|
||||||
|
-D__FPU_PRESENT=1 \
|
||||||
|
-D__VFP_FP__ \
|
||||||
|
-D$(TARGET) \
|
||||||
|
-fsingle-precision-constant \
|
||||||
|
-Wdouble-promotion \
|
||||||
|
-mcpu=$(CPU) \
|
||||||
|
-mtune=$(CPU) \
|
||||||
|
-mfpu=$(FPU) \
|
||||||
|
-mfloat-abi=hard \
|
||||||
|
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
|
||||||
|
-DMP_PORT_NO_SOFTTIMER \
|
||||||
|
$(OMV_BOARD_CFLAGS)
|
||||||
|
|
||||||
# Disable LTO and set the SD
|
# Disable LTO and set the SD
|
||||||
MICROPY_ARGS += LTO=0 SD=$(SD)
|
MICROPY_ARGS += LTO=0 SD=$(SD)
|
||||||
|
|||||||
@ -80,7 +80,7 @@ void omv_csi_mdma_irq_handler(void) {
|
|||||||
static int omv_csi_dma_config() {
|
static int omv_csi_dma_config() {
|
||||||
// DMA Stream configuration
|
// DMA Stream configuration
|
||||||
DMAHandle.Instance = DMA2_Stream1;
|
DMAHandle.Instance = DMA2_Stream1;
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
DMAHandle.Init.Request = DMA_REQUEST_DCMI; /* DMA Channel */
|
DMAHandle.Init.Request = DMA_REQUEST_DCMI; /* DMA Channel */
|
||||||
#else
|
#else
|
||||||
DMAHandle.Init.Channel = DMA_CHANNEL_1; /* DMA Channel */
|
DMAHandle.Init.Channel = DMA_CHANNEL_1; /* DMA Channel */
|
||||||
@ -215,7 +215,7 @@ int omv_csi_config(omv_csi_config_t config) {
|
|||||||
DCMIHandle.Init.CaptureRate = DCMI_CR_ALL_FRAME; // Capture rate all frames
|
DCMIHandle.Init.CaptureRate = DCMI_CR_ALL_FRAME; // Capture rate all frames
|
||||||
DCMIHandle.Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B; // Capture 8 bits on every pixel clock
|
DCMIHandle.Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B; // Capture 8 bits on every pixel clock
|
||||||
DCMIHandle.Init.JPEGMode = DCMI_JPEG_DISABLE;
|
DCMIHandle.Init.JPEGMode = DCMI_JPEG_DISABLE;
|
||||||
#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
|
#if defined(STM32F7) || defined(STM32H7)
|
||||||
DCMIHandle.Init.ByteSelectMode = DCMI_BSM_ALL; // Capture all received bytes
|
DCMIHandle.Init.ByteSelectMode = DCMI_BSM_ALL; // Capture all received bytes
|
||||||
DCMIHandle.Init.ByteSelectStart = DCMI_OEBS_ODD; // Ignored
|
DCMIHandle.Init.ByteSelectStart = DCMI_OEBS_ODD; // Ignored
|
||||||
DCMIHandle.Init.LineSelectMode = DCMI_LSM_ALL; // Capture all received lines
|
DCMIHandle.Init.LineSelectMode = DCMI_LSM_ALL; // Capture all received lines
|
||||||
|
|||||||
@ -73,7 +73,7 @@ int omv_gpu_draw_image(image_t *src_img,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// DMA2D must always fetch the background on the F4 and F7 series so do this in software.
|
// DMA2D must always fetch the background on the F4 and F7 series so do this in software.
|
||||||
#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
|
#if defined(STM32F4) || defined(STM32F7)
|
||||||
if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
|
if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
@ -91,7 +91,7 @@ int omv_gpu_draw_image(image_t *src_img,
|
|||||||
dma2d.Init.Mode = DMA2D_M2M_BLEND;
|
dma2d.Init.Mode = DMA2D_M2M_BLEND;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
|
if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
|
||||||
dma2d.Init.Mode = DMA2D_M2M_BLEND_BG;
|
dma2d.Init.Mode = DMA2D_M2M_BLEND_BG;
|
||||||
}
|
}
|
||||||
@ -202,7 +202,7 @@ int omv_gpu_draw_image(image_t *src_img,
|
|||||||
|
|
||||||
uint32_t dst = (uint32_t) dst16;
|
uint32_t dst = (uint32_t) dst16;
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
|
if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
|
||||||
dst = 0;
|
dst = 0;
|
||||||
}
|
}
|
||||||
|
|||||||
@ -22,11 +22,12 @@
|
|||||||
|
|
||||||
# Set startup and system files for CMSIS Makefile.
|
# Set startup and system files for CMSIS Makefile.
|
||||||
SYSTEM ?= st/system_stm32fxxx
|
SYSTEM ?= st/system_stm32fxxx
|
||||||
|
LDSCRIPT ?= stm32fxxx
|
||||||
STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
||||||
UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc
|
UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc
|
||||||
BOOT_DIR := boot
|
MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
|
||||||
|
MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
||||||
LDSCRIPT ?= stm32fxxx
|
HAL_DIR = hal/stm32/$(MCU_SERIES)
|
||||||
|
|
||||||
# Compiler Flags
|
# Compiler Flags
|
||||||
CFLAGS += -std=gnu99 \
|
CFLAGS += -std=gnu99 \
|
||||||
@ -43,19 +44,18 @@ CFLAGS += -std=gnu99 \
|
|||||||
-mcpu=$(CPU) \
|
-mcpu=$(CPU) \
|
||||||
-mtune=$(CPU) \
|
-mtune=$(CPU) \
|
||||||
-mfpu=$(FPU) \
|
-mfpu=$(FPU) \
|
||||||
-mfloat-abi=hard \
|
-mfloat-abi=hard
|
||||||
-D$(CFLAGS_MCU)
|
|
||||||
|
|
||||||
CFLAGS += -D$(MCU) \
|
CFLAGS += -D$(MCU) \
|
||||||
-D$(TARGET) \
|
-D$(TARGET) \
|
||||||
-DARM_NN_TRUNCATE \
|
-DARM_NN_TRUNCATE \
|
||||||
-D__FPU_PRESENT=1 \
|
-D__FPU_PRESENT=1 \
|
||||||
-D__VFP_FP__ \
|
-D__VFP_FP__ \
|
||||||
|
-DUSE_FULL_LL_DRIVER \
|
||||||
-DHSE_VALUE=$(OMV_HSE_VALUE)\
|
-DHSE_VALUE=$(OMV_HSE_VALUE)\
|
||||||
-DOMV_VTOR_BASE=$(OMV_FIRM_BASE) \
|
-DOMV_VTOR_BASE=$(OMV_FIRM_BASE) \
|
||||||
-DSTM32_HAL_H=$(HAL_INC) \
|
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
|
||||||
-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
|
-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
|
||||||
-DUSE_FULL_LL_DRIVER \
|
|
||||||
$(OMV_BOARD_CFLAGS)
|
$(OMV_BOARD_CFLAGS)
|
||||||
|
|
||||||
# Linker Flags
|
# Linker Flags
|
||||||
|
|||||||
@ -95,7 +95,7 @@ DEFINE_SPI_INSTANCE(6)
|
|||||||
static omv_spi_t *omv_spi_descr_all[6] = { NULL };
|
static omv_spi_t *omv_spi_descr_all[6] = { NULL };
|
||||||
|
|
||||||
static uint32_t omv_spi_clocksource(SPI_TypeDef *spi) {
|
static uint32_t omv_spi_clocksource(SPI_TypeDef *spi) {
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
if (spi == SPI1 || spi == SPI2 || spi == SPI3) {
|
if (spi == SPI1 || spi == SPI2 || spi == SPI3) {
|
||||||
return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
|
return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
|
||||||
} else if (spi == SPI4 || spi == SPI5) {
|
} else if (spi == SPI4 || spi == SPI5) {
|
||||||
@ -290,7 +290,7 @@ static int omv_spi_dma_init(omv_spi_t *spi, uint32_t direction, omv_spi_config_t
|
|||||||
dma_descr->Init.MemBurst = DMA_MBURST_SINGLE;
|
dma_descr->Init.MemBurst = DMA_MBURST_SINGLE;
|
||||||
dma_descr->Init.PeriphBurst = DMA_PBURST_SINGLE;
|
dma_descr->Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||||
dma_descr->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
dma_descr->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
dma_descr->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
dma_descr->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||||
#else
|
#else
|
||||||
dma_descr->Init.PeriphDataAlignment = (config->datasize == 8) ? DMA_PDATAALIGN_BYTE : DMA_PDATAALIGN_HALFWORD;
|
dma_descr->Init.PeriphDataAlignment = (config->datasize == 8) ? DMA_PDATAALIGN_BYTE : DMA_PDATAALIGN_HALFWORD;
|
||||||
@ -336,9 +336,9 @@ static int omv_spi_bus_init(omv_spi_t *spi, omv_spi_config_t *config) {
|
|||||||
spi_descr->Init.CLKPhase = config->clk_pha;
|
spi_descr->Init.CLKPhase = config->clk_pha;
|
||||||
spi_descr->Init.CLKPolarity = config->clk_pol;
|
spi_descr->Init.CLKPolarity = config->clk_pol;
|
||||||
spi_descr->Init.BaudRatePrescaler = omv_spi_prescaler(spi_descr->Instance, config->baudrate);
|
spi_descr->Init.BaudRatePrescaler = omv_spi_prescaler(spi_descr->Instance, config->baudrate);
|
||||||
#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
|
#if defined(STM32F7) || defined(STM32H7)
|
||||||
spi_descr->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
|
spi_descr->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
spi_descr->Init.NSSPolarity = (config->nss_pol == 0) ? SPI_NSS_POLARITY_LOW : SPI_NSS_POLARITY_HIGH;
|
spi_descr->Init.NSSPolarity = (config->nss_pol == 0) ? SPI_NSS_POLARITY_LOW : SPI_NSS_POLARITY_HIGH;
|
||||||
spi_descr->Init.FifoThreshold = SPI_FIFO_THRESHOLD_04DATA;
|
spi_descr->Init.FifoThreshold = SPI_FIFO_THRESHOLD_04DATA;
|
||||||
spi_descr->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
|
spi_descr->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
|
||||||
@ -356,7 +356,7 @@ static int omv_spi_bus_init(omv_spi_t *spi, omv_spi_config_t *config) {
|
|||||||
} else if (config->bus_mode == OMV_SPI_BUS_RX) {
|
} else if (config->bus_mode == OMV_SPI_BUS_RX) {
|
||||||
spi_descr->Init.Direction = SPI_DIRECTION_2LINES_RXONLY;
|
spi_descr->Init.Direction = SPI_DIRECTION_2LINES_RXONLY;
|
||||||
} else {
|
} else {
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
spi_descr->Init.Direction = SPI_DIRECTION_2LINES_TXONLY;
|
spi_descr->Init.Direction = SPI_DIRECTION_2LINES_TXONLY;
|
||||||
#else
|
#else
|
||||||
spi_descr->Init.Direction = SPI_DIRECTION_1LINE;
|
spi_descr->Init.Direction = SPI_DIRECTION_1LINE;
|
||||||
|
|||||||
@ -92,7 +92,7 @@ void HAL_MspInit(void) {
|
|||||||
#endif // defined(OMV_DMA_MEMORY)
|
#endif // defined(OMV_DMA_MEMORY)
|
||||||
|
|
||||||
// Enable I/D cache.
|
// Enable I/D cache.
|
||||||
#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
|
#if defined(STM32F7) || defined(STM32H7)
|
||||||
#ifdef OMV_DISABLE_CACHE
|
#ifdef OMV_DISABLE_CACHE
|
||||||
// Disable caches for testing.
|
// Disable caches for testing.
|
||||||
SCB_DisableICache();
|
SCB_DisableICache();
|
||||||
@ -147,7 +147,7 @@ void HAL_MspInit(void) {
|
|||||||
__DMA1_CLK_ENABLE();
|
__DMA1_CLK_ENABLE();
|
||||||
__DMA2_CLK_ENABLE();
|
__DMA2_CLK_ENABLE();
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
// MDMA clock.
|
// MDMA clock.
|
||||||
__HAL_RCC_MDMA_CLK_ENABLE();
|
__HAL_RCC_MDMA_CLK_ENABLE();
|
||||||
NVIC_SetPriority(MDMA_IRQn, IRQ_PRI_MDMA);
|
NVIC_SetPriority(MDMA_IRQn, IRQ_PRI_MDMA);
|
||||||
@ -212,7 +212,7 @@ void HAL_MspInit(void) {
|
|||||||
omv_gpio_write(OMV_FIR_LEPTON_POWER_PIN, 0);
|
omv_gpio_write(OMV_FIR_LEPTON_POWER_PIN, 0);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
// This disconnects PA0/PA1 from PA0_C/PA1_C.
|
// This disconnects PA0/PA1 from PA0_C/PA1_C.
|
||||||
// PA0_C/PA1_C connect to ADC1/2 Channels P0/P1
|
// PA0_C/PA1_C connect to ADC1/2 Channels P0/P1
|
||||||
HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA0, SYSCFG_SWITCH_PA0_OPEN);
|
HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA0, SYSCFG_SWITCH_PA0_OPEN);
|
||||||
@ -435,7 +435,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) {
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
omv_gpio_config(spi_pins.sclk_pin, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_HIGH, -1);
|
omv_gpio_config(spi_pins.sclk_pin, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_HIGH, -1);
|
||||||
#else
|
#else
|
||||||
// The STM32F4 and STM32F7 don't set the initial state of the clock line until transmitting the
|
// The STM32F4 and STM32F7 don't set the initial state of the clock line until transmitting the
|
||||||
@ -453,7 +453,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) {
|
|||||||
} else {
|
} else {
|
||||||
if (hspi->Init.Mode == SPI_MODE_MASTER) {
|
if (hspi->Init.Mode == SPI_MODE_MASTER) {
|
||||||
omv_gpio_config(spi_pins.ssel_pin, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_HIGH, -1);
|
omv_gpio_config(spi_pins.ssel_pin, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_HIGH, -1);
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
if (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW) {
|
if (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW) {
|
||||||
omv_gpio_write(spi_pins.ssel_pin, 1);
|
omv_gpio_write(spi_pins.ssel_pin, 1);
|
||||||
} else {
|
} else {
|
||||||
|
|||||||
@ -80,7 +80,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
|
|||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(MCU_SERIES_H7)
|
#if defined(STM32H7)
|
||||||
// Keep USB clock running during sleep or else __WFI() will disable the USB
|
// Keep USB clock running during sleep or else __WFI() will disable the USB
|
||||||
__HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE();
|
__HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE();
|
||||||
__HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
|
__HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user