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Merge pull request #985 from kwagyeman/kwabena/update_core_cm7
Update the cmsis cm7 header
This commit is contained in:
commit
c3a200e2d7
@ -1,11 +1,11 @@
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/**************************************************************************//**
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/**************************************************************************//**
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* @file core_cm7.h
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* @file core_cm7.h
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* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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* @version V5.0.8
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* @version V5.1.0
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* @date 04. June 2018
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* @date 13. March 2019
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******************************************************************************/
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******************************************************************************/
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/*
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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@ -86,7 +86,7 @@
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#endif
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#endif
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#if defined __ARM_PCS_VFP
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#if defined __ARM_FP
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#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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#define __FPU_USED 1U
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#define __FPU_USED 1U
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#else
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#else
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@ -423,7 +423,7 @@ typedef struct
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__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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uint32_t RESERVED0[24U];
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uint32_t RESERVED0[24U];
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__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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uint32_t RSERVED1[24U];
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uint32_t RESERVED1[24U];
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__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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uint32_t RESERVED2[24U];
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uint32_t RESERVED2[24U];
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__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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@ -930,6 +930,24 @@ typedef struct
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#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
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#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
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/* Auxiliary Control Register Definitions */
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/* Auxiliary Control Register Definitions */
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#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
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#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
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#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
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#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
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#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
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#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
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#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
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#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
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#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
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#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
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#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
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#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
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#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
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#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
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#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
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#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
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@ -1024,10 +1042,7 @@ typedef struct
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__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
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__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
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uint32_t RESERVED2[15U];
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uint32_t RESERVED2[15U];
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__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
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__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
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uint32_t RESERVED3[29U];
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uint32_t RESERVED3[32U];
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__OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
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__IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
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__IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
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uint32_t RESERVED4[43U];
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uint32_t RESERVED4[43U];
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__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
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__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
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__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
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__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
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@ -1078,18 +1093,6 @@ typedef struct
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#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
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#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
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#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
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#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
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/* ITM Integration Write Register Definitions */
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#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
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#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
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/* ITM Integration Read Register Definitions */
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#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
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#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
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/* ITM Integration Mode Control Register Definitions */
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#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
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#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
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/* ITM Lock Status Register Definitions */
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/* ITM Lock Status Register Definitions */
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#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
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#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
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#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
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#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
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@ -1325,13 +1328,13 @@ typedef struct
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/* TPI Integration ETM Data Register Definitions (FIFO0) */
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/* TPI Integration ETM Data Register Definitions (FIFO0) */
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#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
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#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
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#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
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#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
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#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
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#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
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#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
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#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
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#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
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#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
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#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
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#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
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#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
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#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
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#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
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#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
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@ -1354,13 +1357,13 @@ typedef struct
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/* TPI Integration ITM Data Register Definitions (FIFO1) */
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/* TPI Integration ITM Data Register Definitions (FIFO1) */
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#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
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#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
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#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
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#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
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#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
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#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
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#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
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#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
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#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
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#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
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#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
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#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
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#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
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#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
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#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
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#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
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@ -1617,6 +1620,9 @@ typedef struct
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/* Media and FP Feature Register 2 Definitions */
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/* Media and FP Feature Register 2 Definitions */
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#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
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#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
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/*@} end of group CMSIS_FPU */
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/*@} end of group CMSIS_FPU */
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@ -2120,8 +2126,8 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
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*/
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*/
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__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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{
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{
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uint32_t *vectors = (uint32_t *)SCB->VTOR;
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uint32_t vectors = (uint32_t )SCB->VTOR;
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vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
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(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
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}
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}
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@ -2135,8 +2141,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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*/
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*/
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__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
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__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
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{
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{
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uint32_t *vectors = (uint32_t *)SCB->VTOR;
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uint32_t vectors = (uint32_t )SCB->VTOR;
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return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
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return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
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}
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}
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@ -2161,6 +2167,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
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/*@} end of CMSIS_Core_NVICFunctions */
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/*@} end of CMSIS_Core_NVICFunctions */
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/* ########################## MPU functions #################################### */
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/* ########################## MPU functions #################################### */
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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@ -2169,6 +2176,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
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#endif
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#endif
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/* ########################## FPU functions #################################### */
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/* ########################## FPU functions #################################### */
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/**
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/**
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\ingroup CMSIS_Core_FunctionInterface
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\ingroup CMSIS_Core_FunctionInterface
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@ -2204,7 +2212,6 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
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}
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}
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}
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}
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/*@} end of CMSIS_Core_FpuFunctions */
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/*@} end of CMSIS_Core_FpuFunctions */
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@ -2221,14 +2228,17 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
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#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
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#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
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#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
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/**
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/**
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\brief Enable I-Cache
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\brief Enable I-Cache
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\details Turns on I-Cache
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\details Turns on I-Cache
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*/
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*/
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__STATIC_INLINE void SCB_EnableICache (void)
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__STATIC_FORCEINLINE void SCB_EnableICache (void)
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{
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
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__DSB();
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__DSB();
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__ISB();
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__ISB();
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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@ -2245,7 +2255,7 @@ __STATIC_INLINE void SCB_EnableICache (void)
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\brief Disable I-Cache
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\brief Disable I-Cache
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\details Turns off I-Cache
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\details Turns off I-Cache
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*/
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*/
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__STATIC_INLINE void SCB_DisableICache (void)
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__STATIC_FORCEINLINE void SCB_DisableICache (void)
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{
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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__DSB();
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@ -2262,7 +2272,7 @@ __STATIC_INLINE void SCB_DisableICache (void)
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\brief Invalidate I-Cache
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\brief Invalidate I-Cache
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\details Invalidates I-Cache
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\details Invalidates I-Cache
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*/
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*/
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__STATIC_INLINE void SCB_InvalidateICache (void)
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__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
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{
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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__DSB();
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@ -2278,14 +2288,16 @@ __STATIC_INLINE void SCB_InvalidateICache (void)
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\brief Enable D-Cache
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\brief Enable D-Cache
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\details Turns on D-Cache
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\details Turns on D-Cache
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*/
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*/
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__STATIC_INLINE void SCB_EnableDCache (void)
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__STATIC_FORCEINLINE void SCB_EnableDCache (void)
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{
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
uint32_t ccsidr;
|
uint32_t ccsidr;
|
||||||
uint32_t sets;
|
uint32_t sets;
|
||||||
uint32_t ways;
|
uint32_t ways;
|
||||||
|
|
||||||
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||||
|
|
||||||
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
ccsidr = SCB->CCSIDR;
|
ccsidr = SCB->CCSIDR;
|
||||||
@ -2316,14 +2328,14 @@ __STATIC_INLINE void SCB_EnableDCache (void)
|
|||||||
\brief Disable D-Cache
|
\brief Disable D-Cache
|
||||||
\details Turns off D-Cache
|
\details Turns off D-Cache
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_DisableDCache (void)
|
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
uint32_t ccsidr;
|
uint32_t ccsidr;
|
||||||
uint32_t sets;
|
uint32_t sets;
|
||||||
uint32_t ways;
|
uint32_t ways;
|
||||||
|
|
||||||
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||||
@ -2354,14 +2366,14 @@ __STATIC_INLINE void SCB_DisableDCache (void)
|
|||||||
\brief Invalidate D-Cache
|
\brief Invalidate D-Cache
|
||||||
\details Invalidates D-Cache
|
\details Invalidates D-Cache
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_InvalidateDCache (void)
|
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
uint32_t ccsidr;
|
uint32_t ccsidr;
|
||||||
uint32_t sets;
|
uint32_t sets;
|
||||||
uint32_t ways;
|
uint32_t ways;
|
||||||
|
|
||||||
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
ccsidr = SCB->CCSIDR;
|
ccsidr = SCB->CCSIDR;
|
||||||
@ -2389,14 +2401,14 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
|
|||||||
\brief Clean D-Cache
|
\brief Clean D-Cache
|
||||||
\details Cleans D-Cache
|
\details Cleans D-Cache
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_CleanDCache (void)
|
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
uint32_t ccsidr;
|
uint32_t ccsidr;
|
||||||
uint32_t sets;
|
uint32_t sets;
|
||||||
uint32_t ways;
|
uint32_t ways;
|
||||||
|
|
||||||
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
ccsidr = SCB->CCSIDR;
|
ccsidr = SCB->CCSIDR;
|
||||||
@ -2424,14 +2436,14 @@ __STATIC_INLINE void SCB_CleanDCache (void)
|
|||||||
\brief Clean & Invalidate D-Cache
|
\brief Clean & Invalidate D-Cache
|
||||||
\details Cleans and Invalidates D-Cache
|
\details Cleans and Invalidates D-Cache
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
|
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
uint32_t ccsidr;
|
uint32_t ccsidr;
|
||||||
uint32_t sets;
|
uint32_t sets;
|
||||||
uint32_t ways;
|
uint32_t ways;
|
||||||
|
|
||||||
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
ccsidr = SCB->CCSIDR;
|
ccsidr = SCB->CCSIDR;
|
||||||
@ -2457,27 +2469,30 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
|
|||||||
|
|
||||||
/**
|
/**
|
||||||
\brief D-Cache Invalidate by address
|
\brief D-Cache Invalidate by address
|
||||||
\details Invalidates D-Cache for the given address
|
\details Invalidates D-Cache for the given address.
|
||||||
\param[in] addr address (aligned to 32-byte boundary)
|
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||||
|
\param[in] addr address
|
||||||
\param[in] dsize size of memory block (in number of bytes)
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
int32_t op_size = dsize;
|
if ( dsize > 0 ) {
|
||||||
uint32_t op_addr = (uint32_t)addr;
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
while (op_size > 0) {
|
do {
|
||||||
SCB->DCIMVAC = op_addr;
|
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
op_addr += (uint32_t)linesize;
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
op_size -= linesize;
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
}
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
__DSB();
|
__DSB();
|
||||||
__ISB();
|
__ISB();
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2485,26 +2500,29 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize
|
|||||||
/**
|
/**
|
||||||
\brief D-Cache Clean by address
|
\brief D-Cache Clean by address
|
||||||
\details Cleans D-Cache for the given address
|
\details Cleans D-Cache for the given address
|
||||||
\param[in] addr address (aligned to 32-byte boundary)
|
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||||
|
\param[in] addr address
|
||||||
\param[in] dsize size of memory block (in number of bytes)
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
int32_t op_size = dsize;
|
if ( dsize > 0 ) {
|
||||||
uint32_t op_addr = (uint32_t) addr;
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
while (op_size > 0) {
|
do {
|
||||||
SCB->DCCMVAC = op_addr;
|
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
op_addr += (uint32_t)linesize;
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
op_size -= linesize;
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
}
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
__DSB();
|
__DSB();
|
||||||
__ISB();
|
__ISB();
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2512,30 +2530,32 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
|||||||
/**
|
/**
|
||||||
\brief D-Cache Clean and Invalidate by address
|
\brief D-Cache Clean and Invalidate by address
|
||||||
\details Cleans and invalidates D_Cache for the given address
|
\details Cleans and invalidates D_Cache for the given address
|
||||||
|
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||||
\param[in] addr address (aligned to 32-byte boundary)
|
\param[in] addr address (aligned to 32-byte boundary)
|
||||||
\param[in] dsize size of memory block (in number of bytes)
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||||
{
|
{
|
||||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
int32_t op_size = dsize;
|
if ( dsize > 0 ) {
|
||||||
uint32_t op_addr = (uint32_t) addr;
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
__DSB();
|
__DSB();
|
||||||
|
|
||||||
while (op_size > 0) {
|
do {
|
||||||
SCB->DCCIMVAC = op_addr;
|
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
op_addr += (uint32_t)linesize;
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
op_size -= linesize;
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
}
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
__DSB();
|
__DSB();
|
||||||
__ISB();
|
__ISB();
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_CacheFunctions */
|
/*@} end of CMSIS_Core_CacheFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user