diff --git a/.github/workflows/firmware.yml b/.github/workflows/firmware.yml index 4833446c5..cf6f82f12 100644 --- a/.github/workflows/firmware.yml +++ b/.github/workflows/firmware.yml @@ -42,6 +42,7 @@ jobs: - OPENMVPT - OPENMV_RT1060 - OPENMV_AE3 + - OPENMV_N6 - ARDUINO_PORTENTA_H7 - ARDUINO_GIGA - ARDUINO_NICLA_VISION diff --git a/boards/OPENMV_N6/imlib_config.h b/boards/OPENMV_N6/imlib_config.h new file mode 100644 index 000000000..acd20bc61 --- /dev/null +++ b/boards/OPENMV_N6/imlib_config.h @@ -0,0 +1,149 @@ +/* + * This file is part of the OpenMV project. + * + * Copyright (c) 2013-2021 Ibrahim Abdelkader + * Copyright (c) 2013-2021 Kwabena W. Agyeman + * + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * Image library configuration. + */ +#ifndef __IMLIB_CONFIG_H__ +#define __IMLIB_CONFIG_H__ + +// Enable Image I/O +#define IMLIB_ENABLE_IMAGE_IO + +// Enable Image File I/O +#define IMLIB_ENABLE_IMAGE_FILE_IO + +// Enable LAB LUT +#define IMLIB_ENABLE_LAB_LUT + +// Enable YUV LUT +//#define IMLIB_ENABLE_YUV_LUT + +// Enable ISP ops +#define IMLIB_ENABLE_ISP_OPS + +// Enable binary ops +#define IMLIB_ENABLE_BINARY_OPS + +// Enable math ops +#define IMLIB_ENABLE_MATH_OPS + +// Enable flood_fill() +#define IMLIB_ENABLE_FLOOD_FILL + +// Enable mean() +#define IMLIB_ENABLE_MEAN + +// Enable median() +#define IMLIB_ENABLE_MEDIAN + +// Enable mode() +#define IMLIB_ENABLE_MODE + +// Enable midpoint() +#define IMLIB_ENABLE_MIDPOINT + +// Enable morph() +#define IMLIB_ENABLE_MORPH + +// Enable Gaussian +#define IMLIB_ENABLE_GAUSSIAN + +// Enable Laplacian +#define IMLIB_ENABLE_LAPLACIAN + +// Enable bilateral() +#define IMLIB_ENABLE_BILATERAL + +// Enable linpolar() +#define IMLIB_ENABLE_LINPOLAR + +// Enable logpolar() +#define IMLIB_ENABLE_LOGPOLAR + +// Enable lens_corr() +#define IMLIB_ENABLE_LENS_CORR + +// Enable rotation_corr() +#define IMLIB_ENABLE_ROTATION_CORR + +// Enable phasecorrelate() +#if defined(IMLIB_ENABLE_ROTATION_CORR) +#define IMLIB_ENABLE_FIND_DISPLACEMENT +#endif + +// Enable get_similarity() +#define IMLIB_ENABLE_GET_SIMILARITY + +// Enable find_lines() +#define IMLIB_ENABLE_FIND_LINES + +// Enable find_line_segments() +#define IMLIB_ENABLE_FIND_LINE_SEGMENTS + +// Enable find_circles() +#define IMLIB_ENABLE_FIND_CIRCLES + +// Enable find_rects() +#define IMLIB_ENABLE_FIND_RECTS + +// Enable find_qrcodes() (14 KB) +#define IMLIB_ENABLE_QRCODES + +// Enable find_apriltags() (64 KB) +#define IMLIB_ENABLE_APRILTAGS +#define IMLIB_ENABLE_APRILTAGS_TAG36H11 + +// Enable fine find_apriltags() - (8-way connectivity versus 4-way connectivity) +// #define IMLIB_ENABLE_FINE_APRILTAGS + +// Enable high res find_apriltags() - uses more RAM +#define IMLIB_ENABLE_HIGH_RES_APRILTAGS + +// Enable find_datamatrices() (26 KB) +#define IMLIB_ENABLE_DATAMATRICES + +// Enable find_barcodes() (42 KB) +#define IMLIB_ENABLE_BARCODES + +// Enable find_features() and Haar cascades. +#define IMLIB_ENABLE_FEATURES + +// Enable Tensor Flow +#define IMLIB_ENABLE_STAI + +// Enable AGAST. +#define IMLIB_ENABLE_AGAST + +// Enable find_template() +#define IMLIB_FIND_TEMPLATE + +// Enable find_lbp() +#define IMLIB_ENABLE_FIND_LBP + +// Enable find_keypoints() +#if defined(IMLIB_ENABLE_FAST) || defined(IMLIB_ENABLE_AGAST) +#define IMLIB_ENABLE_FIND_KEYPOINTS +#endif + +// Enable load, save and match descriptor +#define IMLIB_ENABLE_DESCRIPTOR + +// Enable find_hog() +// #define IMLIB_ENABLE_HOG + +// Enable selective_search() +// #define IMLIB_ENABLE_SELECTIVE_SEARCH + +// Enable PNG encoder/decoder +#define IMLIB_ENABLE_PNG_ENCODER +#define IMLIB_ENABLE_PNG_DECODER + +// Stereo Imaging +// #define IMLIB_ENABLE_STEREO_DISPARITY + +#endif //__IMLIB_CONFIG_H__ diff --git a/boards/OPENMV_N6/manifest.py b/boards/OPENMV_N6/manifest.py new file mode 100644 index 000000000..c334bca5d --- /dev/null +++ b/boards/OPENMV_N6/manifest.py @@ -0,0 +1,33 @@ +include("$(MPY_DIR)/extmod/asyncio") + +# Filesystem +freeze ("$(OMV_LIB_DIR)/", "_boot.py") + +# Drivers +freeze ("$(OMV_LIB_DIR)/", "modbus.py") +freeze ("$(OMV_LIB_DIR)/", "pid.py") +freeze ("$(OMV_LIB_DIR)/", "bno055.py") +freeze ("$(OMV_LIB_DIR)/", "ssd1306.py") +freeze ("$(OMV_LIB_DIR)/", "tb6612.py") +freeze ("$(OMV_LIB_DIR)/", "vl53l1x.py") +freeze ("$(OMV_LIB_DIR)/", "machine.py") +freeze ("$(OMV_LIB_DIR)/", "display.py") +freeze ("$(OMV_LIB_DIR)/ml") + +# Networking +require("ssl") +require("ntptime") +require("webrepl") +freeze ("$(OMV_LIB_DIR)/", "rpc.py") +freeze ("$(OMV_LIB_DIR)/", "rtsp.py") +freeze ("$(OMV_LIB_DIR)/", "mqtt.py") +freeze ("$(OMV_LIB_DIR)/", "requests.py") + +# Utils +require("time") +require("logging") +require("collections-defaultdict") +require("types") + +# Bluetooth +require("aioble") diff --git a/boards/OPENMV_N6/omv_boardconfig.h b/boards/OPENMV_N6/omv_boardconfig.h new file mode 100644 index 000000000..4fe34f171 --- /dev/null +++ b/boards/OPENMV_N6/omv_boardconfig.h @@ -0,0 +1,322 @@ +/* + * This file is part of the OpenMV project. + * + * Copyright (c) 2013-2024 Ibrahim Abdelkader + * Copyright (c) 2013-2024 Kwabena W. Agyeman + * + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * Board configuration and pin definitions. + */ +#ifndef __OMV_BOARDCONFIG_H__ +#define __OMV_BOARDCONFIG_H__ + +// Architecture info +#define OMV_BOARD_ARCH "OpenMV N6" // 33 chars max +#define OMV_BOARD_TYPE "N6" +#define OMV_BOARD_UID_ADDR 0x46009014 // Unique ID address. +#define OMV_BOARD_UID_SIZE 3 // Unique ID size in words. +#define OMV_BOARD_UID_OFFSET 4 // Bytes offset for multi-word UIDs. + +// JPEG compression settings. +#define OMV_JPEG_CODEC_ENABLE (1) +#define OMV_JPEG_QUALITY_LOW (50) +#define OMV_JPEG_QUALITY_HIGH (90) +#define OMV_JPEG_QUALITY_THRESHOLD (800 * 600 * 2) + +// Enable RAW preview. +#define OMV_RAW_PREVIEW_ENABLE (1) +#define OMV_RAW_PREVIEW_WIDTH (512) +#define OMV_RAW_PREVIEW_HEIGHT (512) + +// GPU Configuration +#define OMV_GPU_ENABLE (1) +#define OMV_GPU_NEMA (1) +#define OMV_GPU_NEMA_BUFFER_SIZE (32 * 1024) + +#define OMV_OV7725_ENABLE (1) +#define OMV_OV7725_PLL_CONFIG (0x41) // x4 +#define OMV_OV7725_BANDING (0x7F) + +#define OMV_OV5640_ENABLE (1) +#define OMV_OV5640_AF_ENABLE (1) +#define OMV_OV5640_CLK_FREQ (24000000) +#define OMV_OV5640_PLL_CTRL2 (0x64) +#define OMV_OV5640_PLL_CTRL3 (0x13) +#define OMV_OV5640_REV_Y_CHECK (1) +#define OMV_OV5640_REV_Y_FREQ (25000000) +#define OMV_OV5640_REV_Y_CTRL2 (0x54) +#define OMV_OV5640_REV_Y_CTRL3 (0x13) + +#define OMV_MT9V0XX_ENABLE (1) +#define OMV_LEPTON_ENABLE (1) +#define OMV_PAG7936_ENABLE (1) +#define OMV_PAG7936_MIPI_CSI2 (1) +#define OMV_PS5520_ENABLE (1) +#define OMV_GENX320_EHC_ENABLE (1) +#define OMV_GENX320_HSYNC_VALUE (0x1) + +// FIR drivers configuration. +#define OMV_FIR_MLX90621_ENABLE (1) +#define OMV_FIR_MLX90640_ENABLE (1) +#define OMV_FIR_MLX90641_ENABLE (1) +#define OMV_FIR_AMG8833_ENABLE (1) +#define OMV_FIR_LEPTON_ENABLE (0) + +// UMM heap block size +#define OMV_UMM_BLOCK_SIZE 256 + +// USB IRQn. +#define OMV_USB_IRQN (USB1_OTG_HS_IRQn) + +//PLL1 800MHz +#define OMV_OSC_PLL1M (3) +#define OMV_OSC_PLL1N (50) +#define OMV_OSC_PLL1P1 (1) +#define OMV_OSC_PLL1P2 (1) +#define OMV_OSC_PLL1FRAC (0) +#define OMV_OSC_PLL1SOURCE RCC_PLLSOURCE_HSE + +//PLL2 1000MHz +#define OMV_OSC_PLL2M (6) +#define OMV_OSC_PLL2N (125) +#define OMV_OSC_PLL2P1 (1) +#define OMV_OSC_PLL2P2 (1) +#define OMV_OSC_PLL2FRAC (0) +#define OMV_OSC_PLL2SOURCE RCC_PLLSOURCE_HSE + +//PLL3 1200MHz +#define OMV_OSC_PLL3M (1) +#define OMV_OSC_PLL3N (25) +#define OMV_OSC_PLL3P1 (1) +#define OMV_OSC_PLL3P2 (1) +#define OMV_OSC_PLL3FRAC (0) +#define OMV_OSC_PLL3SOURCE RCC_PLLSOURCE_HSE + +//PLL4 1200MHz +#define OMV_OSC_PLL4M (1) +#define OMV_OSC_PLL4N (25) +#define OMV_OSC_PLL4P1 (1) +#define OMV_OSC_PLL4P2 (1) +#define OMV_OSC_PLL4FRAC (0) +#define OMV_OSC_PLL4SOURCE RCC_PLLSOURCE_HSE + +// Clock Sources +#define OMV_RCC_IC8_SOURCE (RCC_ICCLKSOURCE_PLL3) +#define OMV_RCC_IC8_CLKDIV (25) + +#define OMV_RCC_IC9_SOURCE (RCC_ICCLKSOURCE_PLL1) +#define OMV_RCC_IC9_CLKDIV (10) + +#define OMV_RCC_IC10_SOURCE (RCC_ICCLKSOURCE_PLL1) +#define OMV_RCC_IC10_CLKDIV (8) + +#define OMV_RCC_IC14_SOURCE (RCC_ICCLKSOURCE_PLL1) +#define OMV_RCC_IC14_CLKDIV (10) + +#define OMV_RCC_IC15_SOURCE (RCC_ICCLKSOURCE_PLL1) +#define OMV_RCC_IC15_CLKDIV (16) + +#define OMV_RCC_IC17_SOURCE (RCC_ICCLKSOURCE_PLL3) +#define OMV_RCC_IC17_CLKDIV (4) + +#define OMV_RCC_IC18_SOURCE (RCC_ICCLKSOURCE_PLL3) +#define OMV_RCC_IC18_CLKDIV (60) + +#define OMV_OSC_I2C3_SOURCE (RCC_I2C3CLKSOURCE_IC10) +#define OMV_OSC_SPI5_SOURCE (RCC_SPI5CLKSOURCE_IC9) +#define OMV_OSC_DCMIPP_SOURCE (RCC_DCMIPPCLKSOURCE_IC17) +#define OMV_OSC_CSI_SOURCE (0) // has one clock source IC18 +#define OMV_OSC_ADF1_SOURCE (RCC_ADF1CLKSOURCE_IC8) + +// HSE/HSI/CSI State +#define OMV_OSC_HSE_STATE (RCC_HSE_ON) +#define OMV_OSC_HSI_STATE (RCC_HSI_ON) +#define OMV_OSC_HSI_DIV (RCC_HSI_DIV1) +#define OMV_OSC_HSI_CAL (RCC_HSICALIBRATION_DEFAULT) + + +// Power supply configuration +#define OMV_PWR_SUPPLY (PWR_SMPS_SUPPLY) + +// Linker script constants (see the linker script template stm32fxxx.ld.S). +// Note: fb_alloc is a stack-based, dynamically allocated memory on FB. +// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp). +#define OMV_MAIN_MEMORY SRAM1 // Data/BSS memory +#define OMV_STACK_MEMORY SRAM1 // stack memory +#define OMV_RAMFUNC_MEMORY ITCM +#define OMV_STACK_SIZE (64K) +#define OMV_HEAP_MEMORY SRAM1 // libc/sbrk heap memory +#define OMV_HEAP_SIZE (256K) +#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc +#define OMV_FB_SIZE (20M) // FB memory. +#define OMV_FB_ALLOC_SIZE (11M) // minimum fb_alloc size +#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer. +#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data). +#define OMV_VOSPI_MEMORY SRAM1 // VoSPI buffer memory. +#define OMV_VOSPI_SIZE (64K) +#define OMV_DMA_MEMORY SRAM1 // Misc DMA buffers memory. +#define OMV_GC_BLOCK0_MEMORY SRAM2 // Main GC block +#define OMV_GC_BLOCK0_SIZE (1M) +#define OMV_GC_BLOCK1_MEMORY DRAM // Main GC block +#define OMV_GC_BLOCK1_SIZE (32M) +#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data + +// Memory map. +#define OMV_DTCM_ORIGIN 0x20000000 +#define OMV_DTCM_LENGTH 128K +#define OMV_ITCM_ORIGIN 0x00000000 +#define OMV_ITCM_LENGTH 64K +#define OMV_SRAM1_ORIGIN 0x24000000 // AXISRAM1 +#define OMV_SRAM1_LENGTH 1M // 1MB +#define OMV_SRAM2_ORIGIN 0x24100000 // AXISRAM2 +#define OMV_SRAM2_LENGTH 1M // 1MB +#define OMV_SRAM3_ORIGIN 0x24200000 // AXISRAM3 +#define OMV_SRAM3_LENGTH 448K // 448KB +#define OMV_SRAM4_ORIGIN 0x24270000 // AXISRAM4 +#define OMV_SRAM4_LENGTH 448K // 448KB +#define OMV_SRAM5_ORIGIN 0x242E0000 // AXISRAM5 +#define OMV_SRAM5_LENGTH 448K // 448KB +#define OMV_SRAM6_ORIGIN 0x24350000 // AXISRAM6 +#define OMV_SRAM6_LENGTH 448K // 448KB +#define OMV_SRAM7_ORIGIN 0x28000000 // AHBSRAM1 + AHBSRAM2 combined +#define OMV_SRAM7_LENGTH 32K // 16KB + 16KB = 32KB +#define OMV_DRAM_ORIGIN 0x90000000 // XSPI1 +#define OMV_DRAM_LENGTH 64M // 512 Mbits (64 MBytes) + +// Flash configuration. +#define OMV_FLASH_BOOT_ORIGIN 0x34180400 +#define OMV_FLASH_BOOT_LENGTH 512K +#define OMV_FLASH_TXT_ORIGIN 0x70080000 +#define OMV_FLASH_TXT_LENGTH 3584K +#define OMV_ROMFS_PART0_ORIGIN 0x70800000 +#define OMV_ROMFS_PART0_LENGTH 0x01800000 + +// Enable additional GPIO ports. +#define OMV_GPIO_PORT_F_ENABLE (1) +#define OMV_GPIO_PORT_G_ENABLE (1) +#define OMV_GPIO_PORT_H_ENABLE (1) +#define OMV_GPIO_PORT_N_ENABLE (1) +#define OMV_GPIO_PORT_O_ENABLE (1) +#define OMV_GPIO_PORT_P_ENABLE (1) +#define OMV_GPIO_PORT_Q_ENABLE (1) + +// Physical I2C buses. + +// I2C bus 3 +#define OMV_I2C2_ID (2) +#define OMV_I2C2_SCL_PIN (&omv_pin_B10_I2C2) +#define OMV_I2C2_SDA_PIN (&omv_pin_B11_I2C2) + +// I2C bus 3 +#define OMV_I2C3_ID (3) +#define OMV_I2C3_SCL_PIN (&omv_pin_A8_I2C3) +#define OMV_I2C3_SDA_PIN (&omv_pin_A9_I2C3) + +// I2C bus 4 +#define OMV_I2C4_ID (4) +#define OMV_I2C4_SCL_PIN (&omv_pin_E13_I2C4) +#define OMV_I2C4_SDA_PIN (&omv_pin_E14_I2C4) + +// Physical SPI buses. + +// SPI bus 5 +#define OMV_SPI5_ID (5) +#define OMV_SPI5_SCLK_PIN (&omv_pin_E15_SPI5) +#define OMV_SPI5_MISO_PIN (&omv_pin_D4_SPI5) +#define OMV_SPI5_MOSI_PIN (&omv_pin_A4_SPI5) +#define OMV_SPI5_SSEL_PIN (&omv_pin_A3_SPI5) +#define OMV_SPI5_DMA_TX_CHANNEL (GPDMA1_Channel0) +#define OMV_SPI5_DMA_TX_REQUEST (GPDMA1_REQUEST_SPI5_TX) +#define OMV_SPI5_DMA_RX_CHANNEL (GPDMA1_Channel1) +#define OMV_SPI5_DMA_RX_REQUEST (GPDMA1_REQUEST_SPI5_RX) + +// CSI SPI bus +#define OMV_CSI_SPI_ID (OMV_SPI5_ID) + +// CSI I2C bus +#define OMV_CSI_I2C_ID (OMV_I2C3_ID) +#define OMV_CSI_I2C_SPEED (OMV_I2C_SPEED_STANDARD) + +// FIR I2C bus +#define OMV_FIR_I2C_ID (OMV_I2C2_ID) +#define OMV_FIR_I2C_SPEED (OMV_I2C_SPEED_FULL) + +// IMU SPI bus +#define OMV_IMU_I2C_ID (OMV_I2C4_ID) +#define OMV_IMU_I2C_SPEED (OMV_I2C_SPEED_FULL) +#define OMV_IMU_CHIP_LSM6DSM (1) +#define OMV_IMU_X_Y_ROTATION_DEGREES 90 +#define OMV_IMU_MOUNTING_Z_DIRECTION -1 + +// MDF1 +#define OMV_MDF (ADF1_Filter0) +#define OMV_MDF_PROC_CLKDIV (2) // 48MHz / 2 = 24MHz +#define OMV_MDF_CCKY_CLKDIV (12) // 24MHz / 12 = 2 MHz +#define OMV_AUDIO_MAX_CHANNELS (2) + +#define OMV_MDF_CK_PIN (&omv_pin_E2_ADF1) +#define OMV_MDF_D1_PIN (&omv_pin_B2_ADF1) + +#define OMV_MDF_FLT0_IRQ ADF1_FLT0_IRQn +#define OMV_MDF_FLT0_IRQHandler ADF1_FLT0_IRQHandler +#define OMV_MDF_FLT0_DMA_STREAM GPDMA1_Channel6 +#define OMV_MDF_FLT0_DMA_REQUEST GPDMA1_REQUEST_ADF1_FLT0 +#define OMV_MDF_FLT0_DMA_IRQ GPDMA1_Channel6_IRQn + +// Camera Interface +#define OMV_CSI_CLK_SOURCE (OMV_CSI_CLK_SOURCE_TIM) +#define OMV_CSI_CLK_FREQUENCY (12000000) +#define OMV_CSI_TIM (TIM1) +#define OMV_CSI_TIM_PIN (&omv_pin_E9_TIM1) +#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1) +#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE() +#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE() +#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE() +#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq() +#define OMV_CSI_DMA_CHANNEL (HPDMA1_Channel12) +#define OMV_CSI_DMA_REQUEST (HPDMA1_REQUEST_DCMI_PSSI) +#define OMV_CSI_DMA_MEMCPY_ENABLE (0) +#define OMV_CSI_HW_CROP_ENABLE (1) + +#define OMV_CSI_D0_PIN (&omv_pin_A1_DCMI) +#define OMV_CSI_D1_PIN (&omv_pin_A10_DCMI) +#define OMV_CSI_D2_PIN (&omv_pin_E0_DCMI) +#define OMV_CSI_D3_PIN (&omv_pin_E10_DCMI) +#define OMV_CSI_D4_PIN (&omv_pin_B0_DCMI) +#define OMV_CSI_D5_PIN (&omv_pin_E5_DCMI) +#define OMV_CSI_D6_PIN (&omv_pin_G2_DCMI) +#define OMV_CSI_D7_PIN (&omv_pin_F1_DCMI) + +#define OMV_CSI_HSYNC_PIN (&omv_pin_D0_DCMI) +#define OMV_CSI_VSYNC_PIN (&omv_pin_E6_DCMI) +#define OMV_CSI_PXCLK_PIN (&omv_pin_G1_DCMI) +#define OMV_CSI_RESET_PIN (&omv_pin_E3_GPIO) +#define OMV_CSI_POWER_PIN (&omv_pin_E1_GPIO) +//#define OMV_CSI_FSYNC_PIN (&omv_pin_B4_GPIO) + +#define OMV_XSPI1_IO00_PIN (&omv_pin_P0_XSPIM_P1) +#define OMV_XSPI1_IO01_PIN (&omv_pin_P1_XSPIM_P1) +#define OMV_XSPI1_IO02_PIN (&omv_pin_P2_XSPIM_P1) +#define OMV_XSPI1_IO03_PIN (&omv_pin_P3_XSPIM_P1) +#define OMV_XSPI1_IO04_PIN (&omv_pin_P4_XSPIM_P1) +#define OMV_XSPI1_IO05_PIN (&omv_pin_P5_XSPIM_P1) +#define OMV_XSPI1_IO06_PIN (&omv_pin_P6_XSPIM_P1) +#define OMV_XSPI1_IO07_PIN (&omv_pin_P7_XSPIM_P1) +#define OMV_XSPI1_IO08_PIN (&omv_pin_P8_XSPIM_P1) +#define OMV_XSPI1_IO09_PIN (&omv_pin_P9_XSPIM_P1) +#define OMV_XSPI1_IO10_PIN (&omv_pin_P10_XSPIM_P1) +#define OMV_XSPI1_IO11_PIN (&omv_pin_P11_XSPIM_P1) +#define OMV_XSPI1_IO12_PIN (&omv_pin_P12_XSPIM_P1) +#define OMV_XSPI1_IO13_PIN (&omv_pin_P13_XSPIM_P1) +#define OMV_XSPI1_IO14_PIN (&omv_pin_P14_XSPIM_P1) +#define OMV_XSPI1_IO15_PIN (&omv_pin_P15_XSPIM_P1) +#define OMV_XSPI1_NCS1_PIN (&omv_pin_O0_XSPIM_P1) +#define OMV_XSPI1_DQS0_PIN (&omv_pin_O2_XSPIM_P1) +#define OMV_XSPI1_DQS1_PIN (&omv_pin_O3_XSPIM_P1) +#define OMV_XSPI1_CLKP_PIN (&omv_pin_O4_XSPIM_P1) + +#define OMV_XSPI_PSRAM_ID (1) +#define OMV_XSPI_PSRAM_SIZE (0x4000000) +#define OMV_XSPI_PSRAM_FREQUENCY (200000000) +#endif //__OMV_BOARDCONFIG_H__ diff --git a/boards/OPENMV_N6/omv_boardconfig.mk b/boards/OPENMV_N6/omv_boardconfig.mk new file mode 100755 index 000000000..35cb8202d --- /dev/null +++ b/boards/OPENMV_N6/omv_boardconfig.mk @@ -0,0 +1,42 @@ +MCU=STM32N657xx +CPU=cortex-m55 +FPU=fpv5-d16 +PORT=stm32 +SYSTEM=st/system_stm32n6 +DFU_DEVICE=0x37C5:0x9206 +JLINK_DEVICE=STM32N657L0 +OMV_FIRM_BASE=0x70000000 +OMV_FIRM_ADDR=0x70080000 +OMV_BOOT_ADDR=0x34180400 +OMV_BOOT_CFLAGS=-mcmse \ + -DOMV_BOOTLOADER \ + -DUSER_TZ_SAU_SETUP \ + -DCFG_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED \ + -DCFG_TUSB_RHPORT0_MODE=OPT_MODE_DEVICE +OMV_BOARD_CFLAGS=-mcmse \ + -DOMV_NOSYS_STUBS_ENABLE=1 \ + -DMICROPY_HW_RUNS_FROM_EXT_FLASH=1 +OMV_RAMFUNC_OBJS = bdev.o xspi.o spiflash.o +OMV_SIGN_BOOT=1 +OMV_SIGN_HDRV=2.3 +OMV_SIGN_FLAGS=0x80000000 +OMV_PROG_STLDR=MX25UM51245G_STM32N6570-NUCLEO.stldr +OMV_HSE_VALUE=48000000 +OMV_ENABLE_BL=1 +OMV_BOSON_ENABLE=1 +OMV_GENX320_ENABLE=1 +OMV_LEPTON_SDK_ENABLE=1 +MICROPY_PY_CSI = 1 +MICROPY_PY_FIR = 1 +MICROPY_PY_IMU = 1 +MICROPY_PY_ULAB = 1 +MICROPY_PY_AUDIO = 1 +MICROPY_PY_LWIP = 1 +MICROPY_PY_SSL = 1 +MICROPY_PY_SSL_ECDSA_SIGN_ALT = 0 +MICROPY_SSL_MBEDTLS = 1 +MICROPY_PY_NETWORK_CYW43 = 1 +MICROPY_PY_BLUETOOTH = 1 +MICROPY_BLUETOOTH_NIMBLE = 1 +MICROPY_PY_ML = 1 +MICROPY_PY_ML_STAI = 1 diff --git a/boards/OPENMV_N6/omv_bootconfig.h b/boards/OPENMV_N6/omv_bootconfig.h new file mode 100644 index 000000000..a81db00d9 --- /dev/null +++ b/boards/OPENMV_N6/omv_bootconfig.h @@ -0,0 +1,89 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright (C) 2013-2024 OpenMV, LLC. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * Board configuration and pin definitions. + */ +// *INDENT-OFF* +#ifndef __OMV_BOOTCONFIG_H__ +#define __OMV_BOOTCONFIG_H__ +#include STM32_HAL_H +#include "Legacy/stm32_hal_legacy.h" +#include "port.h" + +// Misc config. +#define OMV_BOOT_VID (0x37C5) +#define OMV_BOOT_PID (0x9206) +#define OMV_BOOT_DFU_TIMEOUT (1500) +#define OMV_BOOT_MAGIC_ADDR (0x3401FFFCU) +#define OMV_BOOT_LED_PIN (0) // index in omv_boot_pins + +// Flash config. +#define OMV_BOOT_AXI_FLASH_ENABLE (0) +#define OMV_BOOT_SPI_FLASH_ENABLE (1) +#define OMV_BOOT_SPI_FLASH_MMAP (1) // Memory-map the flash on exit +#define OMV_BOOT_SPI_FLASH_MMAP_DTR (1) + +// OSPI/XSPI config. +#define OMV_BOOT_XSPI_INSTANCE (2) +#define OMV_BOOT_XSPI_FREQUENCY (200000000) +#define OMV_BOOT_XSPI_FLASH_SIZE (0x2000000) // Must be a power of 2. +#define OMV_BOOT_XSPI_FLASH_RST_PIN (13) // index in omv_boot_pins + +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH + +// Boot I/O pins. +static const pin_t omv_boot_pins[] = { + { .gpio = GPIOA, .pin = GPIO_PIN_7, .speed = GPIO_SPEED_LOW, .mode = GPIO_MODE_OUTPUT_PP, .pull = GPIO_PULLUP }, + { .gpio = GPION, .pin = GPIO_PIN_0, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_1, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_2, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_3, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_4, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_5, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_6, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_7, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_8, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_9, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_10, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_11, .speed = GPIO_SPEED_HIGH, .mode = GPIO_MODE_AF_PP, .alt = GPIO_AF9_XSPIM_P2 }, + { .gpio = GPION, .pin = GPIO_PIN_12, .speed = GPIO_SPEED_LOW, .mode = GPIO_MODE_OUTPUT_PP, .pull = GPIO_PULLUP }, +}; +#define OMV_BOOT_PINS_COUNT (sizeof(omv_boot_pins) / sizeof(omv_boot_pins[0])) + +// Boot partitions. +static const partition_t OMV_BOOT_DFU_PARTITIONS[] = { + { .type = PTYPE_SPI_FLASH, .region = -1, .rdonly = 1, .start = 0x00000000, .limit = 0x00080000, .attr = 0 }, // Boot + { .type = PTYPE_SPI_FLASH, .region = -1, .rdonly = 0, .start = 0x00080000, .limit = 0x00400000, .attr = 0 }, // FIRMWARE + { .type = PTYPE_SPI_FLASH, .region = -1, .rdonly = 0, .start = 0x00400000, .limit = 0x00800000, .attr = 0 }, // FILESYSTEM + { .type = PTYPE_SPI_FLASH, .region = -1, .rdonly = 0, .start = 0x00800000, .limit = 0x02000000, .attr = 0 }, // ROMFS0 +}; +#define OMV_BOOT_DFU_PARTITIONS_COUNT 4 // Must be a literal +#define OMV_BOOT_DFU_PARTITIONS_STR "BOOTLOADER", "FIRMWARE", "FILESYSTEM", "ROMFS0" + +// XIP flash, not used for DFU. +static const partition_t OMV_BOOT_XIP_PARTITIONS[] = { + { .type = PTYPE_XIP_FLASH, .region = 0, .rdonly = 1, .start = 0x70000000, .limit = 0x78000000, .attr = MEMATTR_NORMAL_WB_RA_WA }, +}; +#define OMV_BOOT_XIP_PARTITIONS_COUNT (sizeof(OMV_BOOT_XIP_PARTITIONS) / sizeof(OMV_BOOT_XIP_PARTITIONS[0])) +#endif //__OMV_BOOTCONFIG_H__ diff --git a/boards/OPENMV_N6/omv_pins.h b/boards/OPENMV_N6/omv_pins.h new file mode 100644 index 000000000..b88fe1226 --- /dev/null +++ b/boards/OPENMV_N6/omv_pins.h @@ -0,0 +1,53 @@ +OMV_GPIO_DEFINE(E, 15, AF5, SPI5) // SCLK +OMV_GPIO_DEFINE(D, 4, AF5, SPI5) // MISO +OMV_GPIO_DEFINE(A, 4, AF5, SPI5) // MOSI +OMV_GPIO_DEFINE(A, 3, AF5, SPI5) // SSEL + +OMV_GPIO_DEFINE(B, 10, AF4, I2C2) // I2C2_SCL +OMV_GPIO_DEFINE(B, 11, AF4, I2C2) // I2C2_SDA + +OMV_GPIO_DEFINE(A, 8, AF4, I2C3) // I2C3_SCL +OMV_GPIO_DEFINE(A, 9, AF4, I2C3) // I2C3_SDA + +OMV_GPIO_DEFINE(E, 13, AF4, I2C4) // I2C4_SCL +OMV_GPIO_DEFINE(E, 14, AF4, I2C4) // I2C4_SDA + +OMV_GPIO_DEFINE(E, 2, AF3, ADF1) // ADF1_CCK0 +OMV_GPIO_DEFINE(B, 2, AF3, ADF1) // ADF1_SDI0 + +OMV_GPIO_DEFINE(A, 1, AF9, DCMI) // CSI_D0 +OMV_GPIO_DEFINE(A, 10, AF9, DCMI) // CSI_D1 +OMV_GPIO_DEFINE(E, 0, AF9, DCMI) // CSI_D2 +OMV_GPIO_DEFINE(E, 10, AF9, DCMI) // CSI_D3 +OMV_GPIO_DEFINE(B, 0, AF9, DCMI) // CSI_D4 +OMV_GPIO_DEFINE(E, 5, AF9, DCMI) // CSI_D5 +OMV_GPIO_DEFINE(G, 2, AF9, DCMI) // CSI_D6 +OMV_GPIO_DEFINE(F, 1, AF9, DCMI) // CSI_D7 +OMV_GPIO_DEFINE(E, 9, AF1, TIM1) // CSI_CLK +OMV_GPIO_DEFINE(D, 0, AF9, DCMI) // CSI_HSYNC +OMV_GPIO_DEFINE(E, 6, AF9, DCMI) // CSI_VSYNC +OMV_GPIO_DEFINE(G, 1, AF9, DCMI) // CSI_PXCLK +OMV_GPIO_DEFINE(E, 3, NONE, GPIO) // CSI_RESET +OMV_GPIO_DEFINE(E, 1, NONE, GPIO) // CSI_POWER + +OMV_GPIO_DEFINE(P, 0, AF9, XSPIM_P1) // XSPIM_IO0 +OMV_GPIO_DEFINE(P, 1, AF9, XSPIM_P1) // XSPIM_IO1 +OMV_GPIO_DEFINE(P, 2, AF9, XSPIM_P1) // XSPIM_IO2 +OMV_GPIO_DEFINE(P, 3, AF9, XSPIM_P1) // XSPIM_IO3 +OMV_GPIO_DEFINE(P, 4, AF9, XSPIM_P1) // XSPIM_IO4 +OMV_GPIO_DEFINE(P, 5, AF9, XSPIM_P1) // XSPIM_IO5 +OMV_GPIO_DEFINE(P, 6, AF9, XSPIM_P1) // XSPIM_IO6 +OMV_GPIO_DEFINE(P, 7, AF9, XSPIM_P1) // XSPIM_IO7 +OMV_GPIO_DEFINE(P, 8, AF9, XSPIM_P1) // XSPIM_IO8 +OMV_GPIO_DEFINE(P, 9, AF9, XSPIM_P1) // XSPIM_IO9 +OMV_GPIO_DEFINE(P, 10, AF9, XSPIM_P1) // XSPIM_IO10 +OMV_GPIO_DEFINE(P, 11, AF9, XSPIM_P1) // XSPIM_IO11 +OMV_GPIO_DEFINE(P, 12, AF9, XSPIM_P1) // XSPIM_IO12 +OMV_GPIO_DEFINE(P, 13, AF9, XSPIM_P1) // XSPIM_IO13 +OMV_GPIO_DEFINE(P, 14, AF9, XSPIM_P1) // XSPIM_IO14 +OMV_GPIO_DEFINE(P, 15, AF9, XSPIM_P1) // XSPIM_IO15 + +OMV_GPIO_DEFINE(O, 0, AF9, XSPIM_P1) // XSPIM_NCS1 +OMV_GPIO_DEFINE(O, 2, AF9, XSPIM_P1) // XSPIM_DQS0 +OMV_GPIO_DEFINE(O, 3, AF9, XSPIM_P1) // XSPIM_DQS1 +OMV_GPIO_DEFINE(O, 4, AF9, XSPIM_P1) // XSPIM_CLKP diff --git a/boards/OPENMV_N6/romfs.json b/boards/OPENMV_N6/romfs.json new file mode 100644 index 000000000..7ab29a3a8 --- /dev/null +++ b/boards/OPENMV_N6/romfs.json @@ -0,0 +1,25 @@ +{ + "0": { + "size": "0x1800000", + "entries": [ + { + "type": "tflite", + "path": "{TOP}/lib/models/fomo_face_detection.tflite", + "alignment": 32, + "profile": "default" + }, + { + "type": "tflite", + "path": "{TOP}/lib/models/yolo_v2_224_small.tflite", + "alignment": 32, + "profile": "default" + }, + { + "type": "tflite", + "path": "{TOP}/lib/models/yolo_v5_224_nano.tflite", + "alignment": 32, + "profile": "default" + } + ] + } +} diff --git a/boards/OPENMV_N6/ulab_config.h b/boards/OPENMV_N6/ulab_config.h new file mode 100644 index 000000000..6205c6745 --- /dev/null +++ b/boards/OPENMV_N6/ulab_config.h @@ -0,0 +1,17 @@ +/* + * This file is part of the OpenMV project. + * Copyright (c) 2013-2016 Kwabena W. Agyeman + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * Ulab config file. + * + */ +#ifndef __ULAB_CONFIG_H__ +#define __ULAB_CONFIG_H__ +// Override ulab defaults here. +#define ULAB_MAX_DIMS (4) +#define ULAB_SUPPORTS_COMPLEX (0) +#define ULAB_SCIPY_HAS_OPTIMIZE_MODULE (0) +#define ULAB_SCIPY_HAS_SPECIAL_MODULE (0) +#define ULAB_FFT_IS_NUMPY_COMPATIBLE (0) +#endif //__ULAB_CONFIG_H__