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ports/stm32: Switch IMU module to the new SPI HAL.
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a0241f1ee3
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cd9bac9558
@ -53,7 +53,7 @@
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#define OMV_ENABLE_OV7725 (0)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9V0XX (0)
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#define OMV_ENABLE_MT9M114 (1)
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#define OMV_ENABLE_MT9M114 (0)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_GC2145 (1)
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@ -218,7 +218,7 @@
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#define OMV_AXI_QOS_MDMA_R_PRI 15 // Max pri to move data.
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Image sensor I2C
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// Main image sensor I2C bus
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#define ISC_I2C (I2C3)
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#define ISC_I2C_ID (3)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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@ -229,7 +229,7 @@
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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// FIR I2C
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// Thermal image sensor I2C bus
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#define FIR_I2C (I2C1)
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#define FIR_I2C_ID (1)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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@ -240,11 +240,19 @@
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// Soft I2C bus
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#define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO)
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#define SOFT_I2C_SIOD_PIN (&omv_pin_C11_GPIO)
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#define SOFT_I2C_SPIN_DELAY 64
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/* DCMI */
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// IMU SPI bus
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#define IMU_SPI_ID (5)
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#define IMU_SPI_BAUDRATE (500000)
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#define IMU_CHIP_LSM6DSOX (1)
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#define OMV_IMU_X_Y_ROTATION_DEGREES 90
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#define OMV_IMU_MOUNTING_Z_DIRECTION -1
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// DCMI timer
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#define DCMI_TIM (TIM3)
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#define DCMI_TIM_PIN (&omv_pin_A7_TIM3)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_2)
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@ -252,6 +260,7 @@
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#define DCMI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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// DCMI pins
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//#define DCMI_RESET_PIN (&omv_pin_A10_GPIO)
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//#define DCMI_POWER_PIN (&omv_pin_G3_GPIO)
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//#define DCMI_FSYNC_PIN (&omv_pin_B4_GPIO)
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@ -292,25 +301,14 @@
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#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
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#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
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#define IMU_SPI (SPI5)
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// SPI4/5 clock source is PLL3 (160MHz/16 == 10MHz).
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#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16)
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#define IMU_SPI_RESET() __HAL_RCC_SPI5_FORCE_RESET()
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#define IMU_SPI_RELEASE() __HAL_RCC_SPI5_RELEASE_RESET()
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#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE()
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#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI5_CLK_DISABLE()
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#define IMU_SPI_SCLK_PIN (&omv_pin_F7_SPI5)
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#define IMU_SPI_MISO_PIN (&omv_pin_F8_SPI5)
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#define IMU_SPI_MOSI_PIN (&omv_pin_F11_SPI5)
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#define IMU_SPI_SSEL_PIN (&omv_pin_F6_SPI5)
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// IMU configuration
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#define OMV_IMU_X_Y_ROTATION_DEGREES 90
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#define OMV_IMU_MOUNTING_Z_DIRECTION -1
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#define IMU_CHIP_LSM6DSOX (1)
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// Physical SPI buses.
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#define SPI5_ID (5)
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#define SPI5_SCLK_PIN (&omv_pin_F7_SPI5)
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#define SPI5_MISO_PIN (&omv_pin_F8_SPI5)
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#define SPI5_MOSI_PIN (&omv_pin_F11_SPI5)
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#define SPI5_SSEL_PIN (&omv_pin_F6_SPI5)
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#define SPI5_DMA_TX_CHANNEL (DMA2_Stream4)
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#define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[3])
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@ -20,6 +20,7 @@
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#include "py_helper.h"
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#include "py_imu.h"
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#include "omv_gpio.h"
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#include "omv_spi.h"
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#if defined(IMU_CHIP_LSM6DS3)
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#include "lsm6ds3tr_c_reg.h"
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@ -69,45 +70,84 @@ typedef union {
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static bool imu_initialized = false;
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#if defined(IMU_SPI)
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static SPI_HandleTypeDef imubus = {
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.Instance = IMU_SPI,
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.Init.Mode = SPI_MODE_MASTER,
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.Init.Direction = SPI_DIRECTION_2LINES,
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.Init.DataSize = SPI_DATASIZE_8BIT,
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.Init.CLKPolarity = SPI_POLARITY_HIGH,
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.Init.CLKPhase = SPI_PHASE_2EDGE,
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.Init.NSS = SPI_NSS_SOFT,
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.Init.BaudRatePrescaler = IMU_SPI_PRESCALER,
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.Init.FirstBit = SPI_FIRSTBIT_MSB,
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};
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#if defined(IMU_SPI_ID)
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static void platform_init(void *imubus) {
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HAL_SPI_DeInit(imubus);
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HAL_SPI_Init(imubus);
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#if !defined(IMU_SPI_BUS_TIMEOUT)
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#define IMU_SPI_BUS_TIMEOUT (5000)
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#endif
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static omv_spi_t imubus;
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static void platform_init(void *imubus)
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{
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omv_spi_config_t spi_config;
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omv_spi_default_config(&spi_config, IMU_SPI_ID);
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spi_config.baudrate = IMU_SPI_BAUDRATE;
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spi_config.clk_pol = OMV_SPI_CPOL_HIGH;
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spi_config.clk_pha = OMV_SPI_CPHA_2EDGE;
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spi_config.nss_enable = false; // Soft NSS
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omv_spi_init(imubus, &spi_config);
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}
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static void platform_deinit(void *imubus) {
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HAL_SPI_DeInit(imubus);
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static void platform_deinit(void *imubus)
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{
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omv_spi_deinit(imubus);
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imu_initialized = false;
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}
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static int32_t platform_write(void *imubus, uint8_t Reg, uint8_t *Bufp, uint16_t len)
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{
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omv_gpio_write(IMU_SPI_SSEL_PIN, 0);
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HAL_SPI_Transmit(imubus, &Reg, 1, HAL_MAX_DELAY);
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HAL_SPI_Transmit(imubus, Bufp, len, HAL_MAX_DELAY);
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omv_gpio_write(IMU_SPI_SSEL_PIN, 1);
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omv_spi_t *spi_bus = imubus;
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omv_spi_transfer_t spi_xfer = {
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.timeout = IMU_SPI_BUS_TIMEOUT,
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.flags = OMV_SPI_XFER_BLOCKING,
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.callback = NULL,
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.userdata = NULL,
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};
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omv_gpio_write(spi_bus->cs, 0);
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spi_xfer.size = 1;
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spi_xfer.txbuf = &Reg;
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spi_xfer.rxbuf = NULL;
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omv_spi_transfer_start(spi_bus, &spi_xfer);
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spi_xfer.size = len;
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spi_xfer.txbuf = Bufp;
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spi_xfer.rxbuf = NULL;
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omv_spi_transfer_start(spi_bus, &spi_xfer);
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omv_gpio_write(spi_bus->cs, 1);
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return 0;
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}
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static int32_t platform_read(void *imubus, uint8_t Reg, uint8_t *Bufp, uint16_t len)
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{
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omv_spi_t *spi_bus = imubus;
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Reg |= 0x80;
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omv_gpio_write(IMU_SPI_SSEL_PIN, 0);
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HAL_SPI_Transmit(imubus, &Reg, 1, HAL_MAX_DELAY);
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HAL_SPI_Receive(imubus, Bufp, len, HAL_MAX_DELAY);
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omv_gpio_write(IMU_SPI_SSEL_PIN, 1);
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omv_spi_transfer_t spi_xfer = {
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.timeout = IMU_SPI_BUS_TIMEOUT,
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.flags = OMV_SPI_XFER_BLOCKING,
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.callback = NULL,
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.userdata = NULL,
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};
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omv_gpio_write(spi_bus->cs, 0);
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spi_xfer.size = 1;
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spi_xfer.txbuf = &Reg;
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spi_xfer.rxbuf = NULL;
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omv_spi_transfer_start(spi_bus, &spi_xfer);
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spi_xfer.size = len;
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spi_xfer.txbuf = NULL;
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spi_xfer.rxbuf = Bufp;
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omv_spi_transfer_start(spi_bus, &spi_xfer);
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omv_gpio_write(spi_bus->cs, 1);
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return 0;
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}
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#elif defined(IMU_I2C)
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