ports/stm32: Switch IMU module to the new SPI HAL.

This commit is contained in:
iabdalkader 2023-06-17 20:53:26 +02:00
parent a0241f1ee3
commit cd9bac9558
2 changed files with 86 additions and 48 deletions

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@ -53,7 +53,7 @@
#define OMV_ENABLE_OV7725 (0) #define OMV_ENABLE_OV7725 (0)
#define OMV_ENABLE_OV9650 (0) #define OMV_ENABLE_OV9650 (0)
#define OMV_ENABLE_MT9V0XX (0) #define OMV_ENABLE_MT9V0XX (0)
#define OMV_ENABLE_MT9M114 (1) #define OMV_ENABLE_MT9M114 (0)
#define OMV_ENABLE_LEPTON (0) #define OMV_ENABLE_LEPTON (0)
#define OMV_ENABLE_HM01B0 (0) #define OMV_ENABLE_HM01B0 (0)
#define OMV_ENABLE_GC2145 (1) #define OMV_ENABLE_GC2145 (1)
@ -218,7 +218,7 @@
#define OMV_AXI_QOS_MDMA_R_PRI 15 // Max pri to move data. #define OMV_AXI_QOS_MDMA_R_PRI 15 // Max pri to move data.
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data. #define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
// Image sensor I2C // Main image sensor I2C bus
#define ISC_I2C (I2C3) #define ISC_I2C (I2C3)
#define ISC_I2C_ID (3) #define ISC_I2C_ID (3)
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD) #define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
@ -229,7 +229,7 @@
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET() #define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET() #define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
// FIR I2C // Thermal image sensor I2C bus
#define FIR_I2C (I2C1) #define FIR_I2C (I2C1)
#define FIR_I2C_ID (1) #define FIR_I2C_ID (1)
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL) #define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
@ -240,11 +240,19 @@
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET() #define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET() #define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
// Soft I2C bus
#define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO) #define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO)
#define SOFT_I2C_SIOD_PIN (&omv_pin_C11_GPIO) #define SOFT_I2C_SIOD_PIN (&omv_pin_C11_GPIO)
#define SOFT_I2C_SPIN_DELAY 64 #define SOFT_I2C_SPIN_DELAY 64
/* DCMI */ // IMU SPI bus
#define IMU_SPI_ID (5)
#define IMU_SPI_BAUDRATE (500000)
#define IMU_CHIP_LSM6DSOX (1)
#define OMV_IMU_X_Y_ROTATION_DEGREES 90
#define OMV_IMU_MOUNTING_Z_DIRECTION -1
// DCMI timer
#define DCMI_TIM (TIM3) #define DCMI_TIM (TIM3)
#define DCMI_TIM_PIN (&omv_pin_A7_TIM3) #define DCMI_TIM_PIN (&omv_pin_A7_TIM3)
#define DCMI_TIM_CHANNEL (TIM_CHANNEL_2) #define DCMI_TIM_CHANNEL (TIM_CHANNEL_2)
@ -252,6 +260,7 @@
#define DCMI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE() #define DCMI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq() #define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
// DCMI pins
//#define DCMI_RESET_PIN (&omv_pin_A10_GPIO) //#define DCMI_RESET_PIN (&omv_pin_A10_GPIO)
//#define DCMI_POWER_PIN (&omv_pin_G3_GPIO) //#define DCMI_POWER_PIN (&omv_pin_G3_GPIO)
//#define DCMI_FSYNC_PIN (&omv_pin_B4_GPIO) //#define DCMI_FSYNC_PIN (&omv_pin_B4_GPIO)
@ -292,25 +301,14 @@
#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE() #define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE() #define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
#define IMU_SPI (SPI5) // Physical SPI buses.
// SPI4/5 clock source is PLL3 (160MHz/16 == 10MHz). #define SPI5_ID (5)
#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16) #define SPI5_SCLK_PIN (&omv_pin_F7_SPI5)
#define SPI5_MISO_PIN (&omv_pin_F8_SPI5)
#define IMU_SPI_RESET() __HAL_RCC_SPI5_FORCE_RESET() #define SPI5_MOSI_PIN (&omv_pin_F11_SPI5)
#define IMU_SPI_RELEASE() __HAL_RCC_SPI5_RELEASE_RESET() #define SPI5_SSEL_PIN (&omv_pin_F6_SPI5)
#define SPI5_DMA_TX_CHANNEL (DMA2_Stream4)
#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE() #define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI5_CLK_DISABLE()
#define IMU_SPI_SCLK_PIN (&omv_pin_F7_SPI5)
#define IMU_SPI_MISO_PIN (&omv_pin_F8_SPI5)
#define IMU_SPI_MOSI_PIN (&omv_pin_F11_SPI5)
#define IMU_SPI_SSEL_PIN (&omv_pin_F6_SPI5)
// IMU configuration
#define OMV_IMU_X_Y_ROTATION_DEGREES 90
#define OMV_IMU_MOUNTING_Z_DIRECTION -1
#define IMU_CHIP_LSM6DSOX (1)
// SPI LCD Interface // SPI LCD Interface
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[3]) #define OMV_SPI_LCD_CONTROLLER (&spi_obj[3])

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@ -20,6 +20,7 @@
#include "py_helper.h" #include "py_helper.h"
#include "py_imu.h" #include "py_imu.h"
#include "omv_gpio.h" #include "omv_gpio.h"
#include "omv_spi.h"
#if defined(IMU_CHIP_LSM6DS3) #if defined(IMU_CHIP_LSM6DS3)
#include "lsm6ds3tr_c_reg.h" #include "lsm6ds3tr_c_reg.h"
@ -69,45 +70,84 @@ typedef union {
static bool imu_initialized = false; static bool imu_initialized = false;
#if defined(IMU_SPI) #if defined(IMU_SPI_ID)
static SPI_HandleTypeDef imubus = {
.Instance = IMU_SPI,
.Init.Mode = SPI_MODE_MASTER,
.Init.Direction = SPI_DIRECTION_2LINES,
.Init.DataSize = SPI_DATASIZE_8BIT,
.Init.CLKPolarity = SPI_POLARITY_HIGH,
.Init.CLKPhase = SPI_PHASE_2EDGE,
.Init.NSS = SPI_NSS_SOFT,
.Init.BaudRatePrescaler = IMU_SPI_PRESCALER,
.Init.FirstBit = SPI_FIRSTBIT_MSB,
};
static void platform_init(void *imubus) { #if !defined(IMU_SPI_BUS_TIMEOUT)
HAL_SPI_DeInit(imubus); #define IMU_SPI_BUS_TIMEOUT (5000)
HAL_SPI_Init(imubus); #endif
static omv_spi_t imubus;
static void platform_init(void *imubus)
{
omv_spi_config_t spi_config;
omv_spi_default_config(&spi_config, IMU_SPI_ID);
spi_config.baudrate = IMU_SPI_BAUDRATE;
spi_config.clk_pol = OMV_SPI_CPOL_HIGH;
spi_config.clk_pha = OMV_SPI_CPHA_2EDGE;
spi_config.nss_enable = false; // Soft NSS
omv_spi_init(imubus, &spi_config);
} }
static void platform_deinit(void *imubus) { static void platform_deinit(void *imubus)
HAL_SPI_DeInit(imubus); {
omv_spi_deinit(imubus);
imu_initialized = false; imu_initialized = false;
} }
static int32_t platform_write(void *imubus, uint8_t Reg, uint8_t *Bufp, uint16_t len) static int32_t platform_write(void *imubus, uint8_t Reg, uint8_t *Bufp, uint16_t len)
{ {
omv_gpio_write(IMU_SPI_SSEL_PIN, 0); omv_spi_t *spi_bus = imubus;
HAL_SPI_Transmit(imubus, &Reg, 1, HAL_MAX_DELAY);
HAL_SPI_Transmit(imubus, Bufp, len, HAL_MAX_DELAY); omv_spi_transfer_t spi_xfer = {
omv_gpio_write(IMU_SPI_SSEL_PIN, 1); .timeout = IMU_SPI_BUS_TIMEOUT,
.flags = OMV_SPI_XFER_BLOCKING,
.callback = NULL,
.userdata = NULL,
};
omv_gpio_write(spi_bus->cs, 0);
spi_xfer.size = 1;
spi_xfer.txbuf = &Reg;
spi_xfer.rxbuf = NULL;
omv_spi_transfer_start(spi_bus, &spi_xfer);
spi_xfer.size = len;
spi_xfer.txbuf = Bufp;
spi_xfer.rxbuf = NULL;
omv_spi_transfer_start(spi_bus, &spi_xfer);
omv_gpio_write(spi_bus->cs, 1);
return 0; return 0;
} }
static int32_t platform_read(void *imubus, uint8_t Reg, uint8_t *Bufp, uint16_t len) static int32_t platform_read(void *imubus, uint8_t Reg, uint8_t *Bufp, uint16_t len)
{ {
omv_spi_t *spi_bus = imubus;
Reg |= 0x80; Reg |= 0x80;
omv_gpio_write(IMU_SPI_SSEL_PIN, 0); omv_spi_transfer_t spi_xfer = {
HAL_SPI_Transmit(imubus, &Reg, 1, HAL_MAX_DELAY); .timeout = IMU_SPI_BUS_TIMEOUT,
HAL_SPI_Receive(imubus, Bufp, len, HAL_MAX_DELAY); .flags = OMV_SPI_XFER_BLOCKING,
omv_gpio_write(IMU_SPI_SSEL_PIN, 1); .callback = NULL,
.userdata = NULL,
};
omv_gpio_write(spi_bus->cs, 0);
spi_xfer.size = 1;
spi_xfer.txbuf = &Reg;
spi_xfer.rxbuf = NULL;
omv_spi_transfer_start(spi_bus, &spi_xfer);
spi_xfer.size = len;
spi_xfer.txbuf = NULL;
spi_xfer.rxbuf = Bufp;
omv_spi_transfer_start(spi_bus, &spi_xfer);
omv_gpio_write(spi_bus->cs, 1);
return 0; return 0;
} }
#elif defined(IMU_I2C) #elif defined(IMU_I2C)