mirror of
https://github.com/openmv/openmv.git
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boards/all: Switch to new protocol.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
parent
ca547fd831
commit
d669bd7774
@ -13,6 +13,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
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-DCYW43_BT_FIRMWARE_ADDRESS=0x90FC0000 \
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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OMV_ENABLE_BL=0
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -50,10 +50,6 @@
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#define OMV_FIR_MLX90641_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (1)
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#define OMV_TUSBDBG_BUFFER (512)
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 16
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@ -49,10 +49,6 @@ extern unsigned char *OMV_BOARD_UID_ADDR; // Unique address.
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// FIR drivers configuration.
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (1)
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#define OMV_TUSBDBG_BUFFER (2048)
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 16
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@ -15,6 +15,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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OMV_ENABLE_BL = 0
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -14,6 +14,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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OMV_ENABLE_BL=0
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -9,6 +9,7 @@ OMV_HSE_VALUE=12000000
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DFU_DEVICE=0x0483:0xdf11
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -9,6 +9,7 @@ OMV_HSE_VALUE=12000000
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DFU_DEVICE=0x0483:0xdf11
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -10,6 +10,7 @@ OMV_BOOT_ADDR=0x08000000
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OMV_HSE_VALUE=12000000
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -12,6 +12,7 @@ OMV_ENABLE_BL=1
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OMV_BOSON_ENABLE=1
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OMV_GENX320_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -10,6 +10,7 @@ OMV_BOOT_ADDR=0x08000000
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OMV_HSE_VALUE=12000000
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -67,11 +67,6 @@ extern unsigned char OMV_BOARD_UID_ADDR[12]; // Unique address.
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#define OMV_FIR_MLX90641_ENABLE (0)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (CORE_M55_HP)
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#define OMV_TUSBDBG_PACKET (512)
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#define OMV_TUSBDBG_BUFFER (4096)
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 256
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@ -13,6 +13,7 @@ OMV_FIRM_ADDR=0x80020000
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OMV_HSE_VALUE=12000000
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OMV_LEPTON_SDK_ENABLE=1
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OMV_TOF_VL53L8CX_ENABLE=1
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OMV_USB_STACK_TINYUSB=1
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MICROPY_PY_CSI = $(CORE_M55_HP)
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MICROPY_PY_CSI_NG = $(CORE_M55_HP)
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MICROPY_PY_FIR = 1
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@ -62,6 +62,12 @@
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// USB IRQn.
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#define OMV_USB_IRQN (USB1_OTG_HS_IRQn)
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// Protocol hardware capabilities
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
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HAS_GPU, HAS_NPU, HAS_ISP, HAS_VENC, HAS_JPEG, HAS_DRAM, \
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HAS_CRC, HAS_PMU, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (8192)
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//PLL1 800MHz
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (50)
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@ -26,6 +26,7 @@ OMV_ENABLE_BL=1
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OMV_BOSON_ENABLE=1
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OMV_GENX320_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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@ -47,13 +47,13 @@
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#define OMV_FIR_MLX90641_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (1)
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#define OMV_TUSBDBG_BUFFER (2048)
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 256
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// Protocol hardware capabilities
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
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HAS_DRAM, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
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// USB config.
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#define OMV_USB_IRQN (USB_OTG1_IRQn)
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#define OMV_USB1_IRQ_HANDLER (USB_OTG1_IRQHandler)
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@ -81,7 +81,7 @@
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#define OMV_GC_BLOCK0_MEMORY OCRM2 // Extra GC block 0.
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#define OMV_GC_BLOCK0_SIZE (64K)
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#define OMV_GC_BLOCK1_MEMORY DTCM // Main GC block
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#define OMV_GC_BLOCK1_SIZE (272K)
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#define OMV_GC_BLOCK1_SIZE (271K)
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#define OMV_GC_BLOCK2_MEMORY DRAM // Extra GC block 1.
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#define OMV_GC_BLOCK2_SIZE (8M)
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#define OMV_RAMFUNC_MEMORY ITCM2 // RAM code memory.
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@ -11,6 +11,7 @@ OMV_HSE_VALUE=12000000
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OMV_BOSON_ENABLE=1
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OMV_GENX320_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_TINYUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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