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Use pre-defined GCC macro to test for the architecture.
* CPU macro was not actually defined, which made the test pass on all MCUs.
This commit is contained in:
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1a7bff818a
commit
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@ -6,7 +6,7 @@
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// ARM Cortex-M4/M7 Processors can access memory using unaligned 32-bit reads/writes.
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// ARM Cortex-M4/M7 Processors can access memory using unaligned 32-bit reads/writes.
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void *unaligned_memcpy(void *dest, void *src, size_t n)
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void *unaligned_memcpy(void *dest, void *src, size_t n)
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{
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{
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#if (CPU==cortex-m4) || (CPU==cortex-m7)
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#if (__ARM_ARCH > 6)
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// TODO: Make this faster using only 32-bit aligned reads/writes with data shifting.
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// TODO: Make this faster using only 32-bit aligned reads/writes with data shifting.
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uint32_t *dest32 = (uint32_t *) dest;
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uint32_t *dest32 = (uint32_t *) dest;
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uint32_t *src32 = (uint32_t *) src;
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uint32_t *src32 = (uint32_t *) src;
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@ -34,7 +34,7 @@ void *unaligned_memcpy_rev16(void *dest, void *src, size_t n)
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uint32_t *dest32 = (uint32_t *) dest;
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uint32_t *dest32 = (uint32_t *) dest;
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uint32_t *src32 = (uint32_t *) src;
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uint32_t *src32 = (uint32_t *) src;
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#if (CPU==cortex-m4) || (CPU==cortex-m7)
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#if (__ARM_ARCH > 6)
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// TODO: Make this faster using only 32-bit aligned reads/writes with data shifting.
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// TODO: Make this faster using only 32-bit aligned reads/writes with data shifting.
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for (; n > 2; n -= 2) {
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for (; n > 2; n -= 2) {
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*dest32++ = __REV16(*src32++);
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*dest32++ = __REV16(*src32++);
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@ -56,7 +56,7 @@ void *unaligned_2_to_1_memcpy(void *dest, void *src, size_t n)
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uint32_t *dest32 = (uint32_t *) dest;
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uint32_t *dest32 = (uint32_t *) dest;
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uint32_t *src32 = (uint32_t *) src;
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uint32_t *src32 = (uint32_t *) src;
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#if (CPU==cortex-m4) || (CPU==cortex-m7)
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#if (__ARM_ARCH > 6)
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// TODO: Make this faster using only 32-bit aligned reads/writes with data shifting.
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// TODO: Make this faster using only 32-bit aligned reads/writes with data shifting.
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for (; n > 4; n -= 4) {
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for (; n > 4; n -= 4) {
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uint32_t tmp1 = *src32++;
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uint32_t tmp1 = *src32++;
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@ -27,7 +27,7 @@ void mutex_init0(omv_mutex_t *mutex)
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static void _mutex_lock(omv_mutex_t *mutex, uint32_t tid, bool blocking)
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static void _mutex_lock(omv_mutex_t *mutex, uint32_t tid, bool blocking)
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{
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{
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#if (CPU==cortex-m0)
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#if (__ARM_ARCH < 7)
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do {
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do {
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__disable_irq();
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__disable_irq();
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if (mutex->lock == 0) {
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if (mutex->lock == 0) {
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@ -35,7 +35,6 @@ static void _mutex_lock(omv_mutex_t *mutex, uint32_t tid, bool blocking)
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mutex->tid = tid;
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mutex->tid = tid;
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}
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}
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__enable_irq();
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__enable_irq();
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__WFI();
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} while (mutex->tid != tid && blocking);
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} while (mutex->tid != tid && blocking);
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#else
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#else
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do {
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do {
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@ -22,6 +22,33 @@ const float __atanf_lut[4] = {
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+0.9997878412794807f //p1
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+0.9997878412794807f //p1
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};
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};
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#if (__ARM_ARCH < 7)
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#include <math.h>
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float OMV_ATTR_ALWAYS_INLINE fast_sqrtf(float x)
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{
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return sqrtf(x);
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}
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int OMV_ATTR_ALWAYS_INLINE fast_floorf(float x)
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{
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return floorf(x);
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}
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int OMV_ATTR_ALWAYS_INLINE fast_ceilf(float x)
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{
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return ceilf(x);
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}
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int OMV_ATTR_ALWAYS_INLINE fast_roundf(float x)
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{
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return roundf(x);
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}
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float OMV_ATTR_ALWAYS_INLINE fast_fabsf(float x)
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{
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return fabsf(x);
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}
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#else
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float OMV_ATTR_ALWAYS_INLINE fast_sqrtf(float x)
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float OMV_ATTR_ALWAYS_INLINE fast_sqrtf(float x)
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{
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{
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asm volatile (
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asm volatile (
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@ -62,6 +89,17 @@ int OMV_ATTR_ALWAYS_INLINE fast_roundf(float x)
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return i;
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return i;
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}
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}
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float OMV_ATTR_ALWAYS_INLINE fast_fabsf(float x)
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{
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asm volatile (
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"vabs.f32 %[r], %[x]\n"
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: [r] "=t" (x)
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: [x] "t" (x));
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return x;
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}
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#endif
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#pragma GCC diagnostic push
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wstrict-aliasing"
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#pragma GCC diagnostic ignored "-Wstrict-aliasing"
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typedef union{
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typedef union{
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@ -103,15 +141,6 @@ float fast_cbrtf(float x)
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return v.x;
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return v.x;
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}
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}
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float OMV_ATTR_ALWAYS_INLINE fast_fabsf(float x)
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{
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asm volatile (
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"vabs.f32 %[r], %[x]\n"
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: [r] "=t" (x)
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: [x] "t" (x));
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return x;
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}
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inline float fast_atanf(float xx)
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inline float fast_atanf(float xx)
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{
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{
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float x, y, z;
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float x, y, z;
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