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Update to CMSIS NN 5.4.0
This commit is contained in:
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@ -21,7 +21,7 @@
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* Title: arm_nnfunctions.h
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* Description: Public header file for CMSIS NN Library
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*
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* $Date: 17. January 2018
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* $Date: 13. July 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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@ -158,6 +158,52 @@ extern "C"
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q15_t * bufferA,
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q7_t * bufferB);
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/**
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* @brief Basic Q7 convolution function (non-sqaure shape)
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* @param[in] Im_in pointer to input tensor
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* @param[in] dim_im_in_x input tensor dimention x
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* @param[in] dim_im_in_y input tensor dimention y
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* @param[in] ch_im_in number of input tensor channels
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* @param[in] wt pointer to kernel weights
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* @param[in] ch_im_out number of filters, i.e., output tensor channels
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* @param[in] dim_kernel_x filter kernel size x
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* @param[in] dim_kernel_y filter kernel size y
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* @param[in] padding_x padding size x
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* @param[in] padding_y padding size y
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* @param[in] stride_x convolution stride x
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* @param[in] stride_y convolution stride y
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* @param[in] bias pointer to bias
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* @param[in] bias_shift amount of left-shift for bias
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* @param[in] out_shift amount of right-shift for output
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* @param[in,out] Im_out pointer to output tensor
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* @param[in] dim_im_out_x output tensor dimension x
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* @param[in] dim_im_out_y output tensor dimension y
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* @param[in,out] bufferA pointer to buffer space for input
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* @param[in,out] bufferB pointer to buffer space for output
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* @return The function returns <code>ARM_MATH_SUCCESS</code>
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*/
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arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in,
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const uint16_t dim_im_in_x,
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const uint16_t dim_im_in_y,
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const uint16_t ch_im_in,
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const q7_t * wt,
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const uint16_t ch_im_out,
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const uint16_t dim_kernel_x,
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const uint16_t dim_kernel_y,
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const uint16_t padding_x,
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const uint16_t padding_y,
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const uint16_t stride_x,
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const uint16_t stride_y,
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const q7_t * bias,
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const uint16_t bias_shift,
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const uint16_t out_shift,
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q7_t * Im_out,
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const uint16_t dim_im_out_x,
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const uint16_t dim_im_out_y,
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q15_t * bufferA,
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q7_t * bufferB);
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/**
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* @brief Basic Q15 convolution function
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* @param[in] Im_in pointer to input tensor
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@ -21,7 +21,7 @@
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* Title: arm_nnsupportfunctions.h
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* Description: Public header file of support functions for CMSIS NN Library
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*
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* $Date: 17. January 2018
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* $Date: 13. July 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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@ -135,6 +135,57 @@ __STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q3
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}
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#endif
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/**
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* @defgroup NNBasicMath Basic Math Functions for Neural Network Computation
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*
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* Basic Math Functions for Neural Network Computation
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*
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*/
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/**
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* @brief Q7 vector multiplication with variable output shifts
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* @param[in] *pSrcA pointer to the first input vector
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* @param[in] *pSrcB pointer to the second input vector
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* @param[out] *pDst pointer to the output vector
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* @param[in] out_shift amount of right-shift for output
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* @param[in] blockSize number of samples in each vector
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
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*/
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void arm_nn_mult_q15(
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q15_t * pSrcA,
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q15_t * pSrcB,
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q15_t * pDst,
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const uint16_t out_shift,
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uint32_t blockSize);
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/**
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* @brief Q7 vector multiplication with variable output shifts
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* @param[in] *pSrcA pointer to the first input vector
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* @param[in] *pSrcB pointer to the second input vector
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* @param[out] *pDst pointer to the output vector
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* @param[in] out_shift amount of right-shift for output
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* @param[in] blockSize number of samples in each vector
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
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*/
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void arm_nn_mult_q7(
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q7_t * pSrcA,
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q7_t * pSrcB,
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q7_t * pDst,
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const uint16_t out_shift,
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uint32_t blockSize);
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/**
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* @brief defition to adding rouding offset
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*/
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@ -0,0 +1,228 @@
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/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_convolve_HWC_q7_basic.c
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* Description: Q7 version of convolution
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*
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* $Date: 13. July 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "arm_nnfunctions.h"
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/**
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* @ingroup groupNN
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*/
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/**
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* @addtogroup NNConv
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* @{
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*/
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/**
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* @brief Basic Q7 convolution function (non-sqaure shape)
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* @param[in] Im_in pointer to input tensor
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* @param[in] dim_im_in_x input tensor dimention x
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* @param[in] dim_im_in_y input tensor dimention y
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* @param[in] ch_im_in number of input tensor channels
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* @param[in] wt pointer to kernel weights
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* @param[in] ch_im_out number of filters, i.e., output tensor channels
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* @param[in] dim_kernel_x filter kernel size x
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* @param[in] dim_kernel_y filter kernel size y
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* @param[in] padding_x padding size x
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* @param[in] padding_y padding size y
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* @param[in] stride_x convolution stride x
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* @param[in] stride_y convolution stride y
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* @param[in] bias pointer to bias
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* @param[in] bias_shift amount of left-shift for bias
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* @param[in] out_shift amount of right-shift for output
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* @param[in,out] Im_out pointer to output tensor
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* @param[in] dim_im_out_x output tensor dimension x
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* @param[in] dim_im_out_y output tensor dimension y
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* @param[in,out] bufferA pointer to buffer space for input
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* @param[in,out] bufferB pointer to buffer space for output
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* @return The function returns <code>ARM_MATH_SUCCESS</code>
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*/
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arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in,
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const uint16_t dim_im_in_x,
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const uint16_t dim_im_in_y,
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const uint16_t ch_im_in,
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const q7_t * wt,
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const uint16_t ch_im_out,
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const uint16_t dim_kernel_x,
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const uint16_t dim_kernel_y,
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const uint16_t padding_x,
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const uint16_t padding_y,
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const uint16_t stride_x,
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const uint16_t stride_y,
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const q7_t * bias,
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const uint16_t bias_shift,
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const uint16_t out_shift,
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q7_t * Im_out,
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const uint16_t dim_im_out_x,
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const uint16_t dim_im_out_y,
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q15_t * bufferA,
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q7_t * bufferB)
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{
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#if defined (ARM_MATH_DSP)
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/* Run the following code for Cortex-M4 and Cortex-M7 */
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int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
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/*
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* Here we use bufferA as q15_t internally as computation are done with q15_t level
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* im2col are done to output in q15_t format from q7_t input
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*/
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q15_t *pBuffer = bufferA;
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q7_t *pOut = Im_out;
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/* This part implements the im2col function */
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for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
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{
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for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
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{
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for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++)
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{
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for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++)
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{
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if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
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{
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/* Filling 0 for out-of-bound paddings */
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/* arm_fill_q15(0, pBuffer, ch_im_in); */
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memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
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} else
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{
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/* Copying the pixel data to column */
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arm_q7_to_q15_no_shift((q7_t *)
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Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
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}
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pBuffer += ch_im_in;
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}
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}
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/* Computation is filed for every 2 columns */
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if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x)
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{
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pOut =
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arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
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ch_im_out,
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ch_im_in *
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dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut);
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/* counter reset */
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pBuffer = bufferA;
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}
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}
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}
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/* left-over because odd number of output pixels */
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if (pBuffer != bufferA)
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{
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const q7_t *pA = wt;
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int i;
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for (i = 0; i < ch_im_out; i++)
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{
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/* Load the accumulator with bias first */
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q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
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/* Point to the beging of the im2col buffer */
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q15_t *pB = bufferA;
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/* Each time it process 4 entries */
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uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2;
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while (colCnt)
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{
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q31_t inA1, inA2;
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q31_t inB1, inB2;
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pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
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inB1 = *__SIMD32(pB)++;
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sum = __SMLAD(inA1, inB1, sum);
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inB2 = *__SIMD32(pB)++;
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sum = __SMLAD(inA2, inB2, sum);
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colCnt--;
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}
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colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3;
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while (colCnt)
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{
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q7_t inA1 = *pA++;
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q15_t inB1 = *pB++;
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sum += inA1 * inB1;
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colCnt--;
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}
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*pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
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}
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}
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#else
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/* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
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uint16_t i, j, k, l, m, n;
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int conv_out;
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signed char in_row, in_col;
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for (i = 0; i < ch_im_out; i++)
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{
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for (j = 0; j < dim_im_out_y; j++)
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{
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for (k = 0; k < dim_im_out_x; k++)
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{
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conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
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for (m = 0; m < dim_kernel_y; m++)
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{
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for (n = 0; n < dim_kernel_x; n++)
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{
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// if-for implementation
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in_row = stride_y * j + m - padding_y;
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in_col = stride_x * k + n - padding_x;
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if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
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{
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for (l = 0; l < ch_im_in; l++)
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{
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conv_out +=
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Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] *
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wt[i * ch_im_in * dim_kernel_y * dim_kernel_x +
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(m * dim_kernel_x + n) * ch_im_in + l];
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}
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}
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}
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}
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Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
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}
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}
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}
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#endif /* ARM_MATH_DSP */
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/* Return to application */
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return ARM_MATH_SUCCESS;
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}
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/**
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* @} end of NNConv group
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*/
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147
src/cmsis/src/nn/NNSupportFunctions/arm_nn_mult_q15.c
Normal file
147
src/cmsis/src/nn/NNSupportFunctions/arm_nn_mult_q15.c
Normal file
@ -0,0 +1,147 @@
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/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
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*
|
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_nn_mult_q15.c
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* Description: Q15 vector multiplication with variable output shifts
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*
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* $Date: 13. July 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_nnfunctions.h"
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/**
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* @ingroup groupSupport
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*/
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/**
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* @addtogroup NNBasicMath
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* @{
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*/
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/**
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* @brief Q7 vector multiplication with variable output shifts
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* @param[in] *pSrcA pointer to the first input vector
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* @param[in] *pSrcB pointer to the second input vector
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* @param[out] *pDst pointer to the output vector
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* @param[in] out_shift amount of right-shift for output
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* @param[in] blockSize number of samples in each vector
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
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*/
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void arm_nn_mult_q15(
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q15_t * pSrcA,
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q15_t * pSrcB,
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q15_t * pDst,
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const uint16_t out_shift,
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uint32_t blockSize)
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{
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uint32_t blkCnt; /* loop counters */
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#if defined (ARM_MATH_DSP)
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
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q15_t out1, out2, out3, out4; /* temporary output variables */
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q31_t mul1, mul2, mul3, mul4; /* temporary variables */
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/* loop Unrolling */
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blkCnt = blockSize >> 2U;
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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while (blkCnt > 0U)
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{
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/* read two samples at a time from sourceA */
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inA1 = *__SIMD32(pSrcA)++;
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/* read two samples at a time from sourceB */
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||||
inB1 = *__SIMD32(pSrcB)++;
|
||||
/* read two samples at a time from sourceA */
|
||||
inA2 = *__SIMD32(pSrcA)++;
|
||||
/* read two samples at a time from sourceB */
|
||||
inB2 = *__SIMD32(pSrcB)++;
|
||||
|
||||
/* multiply mul = sourceA * sourceB */
|
||||
mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
|
||||
mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
|
||||
mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
|
||||
mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
|
||||
|
||||
/* saturate result to 16 bit */
|
||||
out1 = (q15_t) __SSAT((mul1 + NN_ROUND(out_shift)) >> out_shift, 16);
|
||||
out2 = (q15_t) __SSAT((mul2 + NN_ROUND(out_shift)) >> out_shift, 16);
|
||||
out3 = (q15_t) __SSAT((mul3 + NN_ROUND(out_shift)) >> out_shift, 16);
|
||||
out4 = (q15_t) __SSAT((mul4 + NN_ROUND(out_shift)) >> out_shift, 16);
|
||||
|
||||
/* store the result */
|
||||
#ifndef ARM_MATH_BIG_ENDIAN
|
||||
|
||||
*__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
|
||||
*__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
|
||||
|
||||
#else
|
||||
|
||||
*__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
|
||||
*__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
|
||||
|
||||
#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
|
||||
|
||||
/* Decrement the blockSize loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
|
||||
** No loop unrolling is used. */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Run the below code for Cortex-M0 */
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_DSP) */
|
||||
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A * B */
|
||||
/* Multiply the inputs and store the result in the destination buffer */
|
||||
*pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16);
|
||||
|
||||
/* Decrement the blockSize loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of NNBasicMath group
|
||||
*/
|
||||
|
||||
119
src/cmsis/src/nn/NNSupportFunctions/arm_nn_mult_q7.c
Normal file
119
src/cmsis/src/nn/NNSupportFunctions/arm_nn_mult_q7.c
Normal file
@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS NN Library
|
||||
* Title: arm_nn_mult_q7.c
|
||||
* Description: Q7 vector multiplication with variable output shifts
|
||||
*
|
||||
* $Date: 13. July 2018
|
||||
* $Revision: V.1.0.0
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
*
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#include "arm_nnfunctions.h"
|
||||
|
||||
/**
|
||||
* @ingroup groupSupport
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup NNBasicMath
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Q7 vector multiplication with variable output shifts
|
||||
* @param[in] *pSrcA pointer to the first input vector
|
||||
* @param[in] *pSrcB pointer to the second input vector
|
||||
* @param[out] *pDst pointer to the output vector
|
||||
* @param[in] out_shift amount of right-shift for output
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none.
|
||||
*
|
||||
* <b>Scaling and Overflow Behavior:</b>
|
||||
* \par
|
||||
* The function uses saturating arithmetic.
|
||||
* Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
|
||||
*/
|
||||
|
||||
void arm_nn_mult_q7(
|
||||
q7_t * pSrcA,
|
||||
q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
const uint16_t out_shift,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* loop counters */
|
||||
|
||||
#if defined (ARM_MATH_DSP)
|
||||
|
||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||
q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
|
||||
|
||||
/* loop Unrolling */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
||||
** a second loop below computes the remaining 1 to 3 samples. */
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A * B */
|
||||
/* Multiply the inputs and store the results in temporary variables */
|
||||
out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
|
||||
out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
|
||||
out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
|
||||
out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
|
||||
|
||||
/* Store the results of 4 inputs in the destination buffer in single cycle by packing */
|
||||
*__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
|
||||
|
||||
/* Decrement the blockSize loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
|
||||
** No loop unrolling is used. */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Run the below code for Cortex-M0 */
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_DSP) */
|
||||
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A * B */
|
||||
/* Multiply the inputs and store the result in the destination buffer */
|
||||
*pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
|
||||
|
||||
/* Decrement the blockSize loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of NNBasicMath group
|
||||
*/
|
||||
@ -130,5 +130,5 @@ void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize)
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of q7_to_x group
|
||||
* @} end of nndata_convert group
|
||||
*/
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
* Title: arm_softmax_q15.c
|
||||
* Description: Q15 softmax function
|
||||
*
|
||||
* $Date: 17. January 2018
|
||||
* $Date: 20. February 2018
|
||||
* $Revision: V.1.0.0
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
@ -64,41 +64,53 @@ void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out
|
||||
{
|
||||
q31_t sum;
|
||||
int16_t i;
|
||||
q31_t min, max;
|
||||
max = -1 * 0x100000;
|
||||
min = 0x100000;
|
||||
uint8_t shift;
|
||||
q31_t base;
|
||||
base = -1 * 0x100000;
|
||||
for (i = 0; i < dim_vec; i++)
|
||||
{
|
||||
if (vec_in[i] > max)
|
||||
if (vec_in[i] > base)
|
||||
{
|
||||
max = vec_in[i];
|
||||
}
|
||||
if (vec_in[i] < min)
|
||||
{
|
||||
min = vec_in[i];
|
||||
base = vec_in[i];
|
||||
}
|
||||
}
|
||||
|
||||
/* we ignore really small values
|
||||
* anyway, they will be 0 after shrinking
|
||||
* to q7_t
|
||||
* to q15_t
|
||||
*/
|
||||
if (max - min > 16)
|
||||
{
|
||||
min = max - 16;
|
||||
}
|
||||
base = base - 16;
|
||||
|
||||
sum = 0;
|
||||
|
||||
for (i = 0; i < dim_vec; i++)
|
||||
{
|
||||
sum += 0x1 << (vec_in[i] - min);
|
||||
if (vec_in[i] > base)
|
||||
{
|
||||
shift = (uint8_t)__USAT(vec_in[i] - base, 5);
|
||||
sum += 0x1 << shift;
|
||||
}
|
||||
}
|
||||
|
||||
/* This is effectively (0x1 << 32) / sum */
|
||||
int64_t div_base = 0x100000000LL;
|
||||
int output_base = (int32_t)(div_base / sum);
|
||||
|
||||
/* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) )
|
||||
* so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16
|
||||
* and vec_in[i]-base = 16
|
||||
*/
|
||||
for (i = 0; i < dim_vec; i++)
|
||||
{
|
||||
/* we leave 7-bit dynamic range, so that 128 -> 100% confidence */
|
||||
p_out[i] = (q15_t) __SSAT(((0x1 << (vec_in[i] - min + 14)) / sum), 16);
|
||||
if (vec_in[i] > base)
|
||||
{
|
||||
/* Here minimum value of 17+base-vec[i] will be 1 */
|
||||
shift = (uint8_t)__USAT(17+base-vec_in[i], 5);
|
||||
p_out[i] = (q15_t) __SSAT((output_base >> shift), 16);
|
||||
} else
|
||||
{
|
||||
p_out[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user