diff --git a/lib/stai/libstai/LICENSE.md b/lib/stai/libstai/LICENSE.md new file mode 100644 index 000000000..e66295c5f --- /dev/null +++ b/lib/stai/libstai/LICENSE.md @@ -0,0 +1,86 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the SLA0044 license shall apply and are fully reproduced below: + +SLA0044 Rev5/February 2018 + +Software license agreement + +ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT + +BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE +OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS +INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES +(STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON +BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES +TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights, the redistribution, +reproduction and use in source and binary forms of the software or any part +thereof, with or without modification, are permitted provided that the following +conditions are met: + +1. Redistribution of source code (modified or not) must retain any copyright +notice, this list of conditions and the disclaimer set forth below as items 10 +and 11. + +2. Redistributions in binary form, except as embedded into microcontroller or +microprocessor device manufactured by or for STMicroelectronics or a software +update for such device, must reproduce any copyright notice provided with the +binary code, this list of conditions, and the disclaimer set forth below as +items 10 and 11, in documentation and/or other materials provided with the +distribution. + +3. Neither the name of STMicroelectronics nor the names of other contributors to +this software may be used to endorse or promote products derived from this +software or part thereof without specific written permission. + +4. This software or any part thereof, including modifications and/or derivative +works of this software, must be used and execute solely and exclusively on or in +combination with a microcontroller or microprocessor device manufactured by or +for STMicroelectronics. + +5. No use, reproduction or redistribution of this software partially or totally +may be done in any manner that would subject this software to any Open Source +Terms. “Open Source Terms” shall mean any open source license which requires as +part of distribution of software that the source code of such software is +distributed therewith or otherwise made available, or open source license that +substantially complies with the Open Source definition specified at +www.opensource.org and any other comparable open source license such as for +example GNU General Public License (GPL), Eclipse Public License (EPL), Apache +Software License, BSD license or MIT license. + +6. STMicroelectronics has no obligation to provide any maintenance, support or +updates for the software. + +7. The software is and will remain the exclusive property of STMicroelectronics +and its licensors. The recipient will not take any action that jeopardizes +STMicroelectronics and its licensors' proprietary rights or acquire any rights +in the software, except the limited rights specified hereunder. + +8. The recipient shall comply with all applicable laws and regulations affecting +the use of the software or any part thereof including any applicable export +control law or regulation. + +9. Redistribution and use of this software or any part thereof other than as +permitted under this license is void and will automatically terminate your +rights under this license. + +10. THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE +DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL +STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER +EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY +RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + diff --git a/lib/stai/libstai/include/ATON.h b/lib/stai/libstai/include/ATON.h new file mode 100644 index 000000000..f99b63ba5 --- /dev/null +++ b/lib/stai/libstai/include/ATON.h @@ -0,0 +1,100293 @@ +/** + ****************************************************************************** + * @file ATON.h + * @brief Macros related to the Neural-Art embodiement found in STM32N6 + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef ATON_H +#define ATON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + + +/* ********************************************************************************************************************************************************** */ +/* */ +/* HELPER MACROS */ +/* */ +/* ********************************************************************************************************************************************************** */ + +/** Mask for retrieving the content of a field of a register. */ +#define ATON_FIELD_MASK(OFFSET, SIZE) ((uint32_t)(((1ULL << (SIZE)) - 1ULL) << (OFFSET))) + +/** Get the content of a field of a register. */ +#define ATON_GET_FIELD(REG, OFFSET, SIZE) (((REG) & ATON_FIELD_MASK((OFFSET), (SIZE))) >> (OFFSET)) + +/** Set the content of a field of a register. */ +#define ATON_SET_FIELD(REG, OFFSET, SIZE, DATA) (((REG) & (~ATON_FIELD_MASK((OFFSET), (SIZE)))) | (((DATA) << (OFFSET)) & ATON_FIELD_MASK((OFFSET), (SIZE)))) + + +/* ********************************************************************************************************************************************************** */ +/* */ +/* ENUMERATED VALUES */ +/* */ +/* ********************************************************************************************************************************************************** */ + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* ACTIVTYPE set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Activation type: ReLU. */ +#define ATON_ACTIVTYPE_RELU (0x0UL) + +/** Activation type: Parametric ReLU. */ +#define ATON_ACTIVTYPE_PRELU (0x1UL) + +/** Activation type: Thresholded ReLU. */ +#define ATON_ACTIVTYPE_TRELU (0x2UL) + +/** Activation type: Function evaluator. */ +#define ATON_ACTIVTYPE_FUNCTION (0x3UL) + + +/** Get the name of one of the values of the ACTIVTYPE set of enumerated values. */ +#define ATON_ACTIVTYPE_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "RELU" : \ + (((VALUE) == 1UL) ? "PRELU" : \ + (((VALUE) == 2UL) ? "TRELU" : \ + (((VALUE) == 3UL) ? "FUNCTION" : "")))) + + +/** + * Check if a value of the ACTIVTYPE set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the ACTIVTYPE set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_ACTIVTYPE_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_ACTIVTYPE_RELU: + case ATON_ACTIVTYPE_PRELU: + case ATON_ACTIVTYPE_TRELU: + case ATON_ACTIVTYPE_FUNCTION: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the ACTIVTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the ACTIVTYPE set of enumerated values + */ + +static inline const int8_t *ATON_ACTIVTYPE_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ACTIVTYPE_RELU: + str = (const int8_t *)"RELU"; + break; + + case ATON_ACTIVTYPE_PRELU: + str = (const int8_t *)"PRELU"; + break; + + case ATON_ACTIVTYPE_TRELU: + str = (const int8_t *)"TRELU"; + break; + + case ATON_ACTIVTYPE_FUNCTION: + str = (const int8_t *)"FUNCTION"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the ACTIVTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the ACTIVTYPE set of enumerated values + */ + +static inline const int8_t *ATON_ACTIVTYPE_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ACTIVTYPE_RELU: + str = (const int8_t *)"ReLU"; + break; + + case ATON_ACTIVTYPE_PRELU: + str = (const int8_t *)"Parametric ReLU"; + break; + + case ATON_ACTIVTYPE_TRELU: + str = (const int8_t *)"Thresholded ReLU"; + break; + + case ATON_ACTIVTYPE_FUNCTION: + str = (const int8_t *)"Function evaluator"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* ACTIV_ROM set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Activation unit ROM offsets: Activation unit ROM 0 offset. */ +#define ATON_ACTIV_ROM_OFFSET_0 (0x400UL) + +/** Activation unit ROM offsets: Activation unit ROM 1 offset. */ +#define ATON_ACTIV_ROM_OFFSET_1 (0x800UL) + + +/** Get the name of one of the values of the ACTIV_ROM set of enumerated values. */ +#define ATON_ACTIV_ROM_GET_NAME(VALUE) \ + (((VALUE) == 1024UL) ? "OFFSET_0" : \ + (((VALUE) == 2048UL) ? "OFFSET_1" : "")) + + +/** + * Check if a value of the ACTIV_ROM set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the ACTIV_ROM set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_ACTIV_ROM_IsValid(uint32_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_ACTIV_ROM_OFFSET_0: + case ATON_ACTIV_ROM_OFFSET_1: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the ACTIV_ROM set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the ACTIV_ROM set of enumerated values + */ + +static inline const int8_t *ATON_ACTIV_ROM_GetName(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ACTIV_ROM_OFFSET_0: + str = (const int8_t *)"OFFSET_0"; + break; + + case ATON_ACTIV_ROM_OFFSET_1: + str = (const int8_t *)"OFFSET_1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the ACTIV_ROM set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the ACTIV_ROM set of enumerated values + */ + +static inline const int8_t *ATON_ACTIV_ROM_GetDesc(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ACTIV_ROM_OFFSET_0: + str = (const int8_t *)"Activation unit ROM 0 offset"; + break; + + case ATON_ACTIV_ROM_OFFSET_1: + str = (const int8_t *)"Activation unit ROM 1 offset"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* ARITHOP set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Arithmetic operation: Ax + By + C. */ +#define ATON_ARITHOP_AX_BY_C (0x0UL) + +/** Arithmetic operation: min(X,Y). */ +#define ATON_ARITHOP_MIN_X_Y (0x1UL) + +/** Arithmetic operation: max(X,Y). */ +#define ATON_ARITHOP_MAX_X_Y (0x2UL) + +/** Arithmetic operation: X*Y. */ +#define ATON_ARITHOP_XY (0x7UL) + +/** Arithmetic operation: X&Y. */ +#define ATON_ARITHOP_X_AND_Y (0xbUL) + +/** Arithmetic operation: X|Y. */ +#define ATON_ARITHOP_X_OR_Y (0xfUL) + +/** Arithmetic operation: !X. */ +#define ATON_ARITHOP_NOT_X (0x13UL) + +/** Arithmetic operation: X^Y. */ +#define ATON_ARITHOP_X_XOR_Y (0x17UL) + +/** Arithmetic operation: X==Y. */ +#define ATON_ARITHOP_X_EQ_Y (0x1bUL) + +/** Arithmetic operation: XY. */ +#define ATON_ARITHOP_X_GT_Y (0x27UL) + +/** Arithmetic operation: X>=Y. */ +#define ATON_ARITHOP_X_GE_Y (0x2bUL) + +/** Arithmetic operation: ABS(X). */ +#define ATON_ARITHOP_ABS_X (0x2fUL) + +/** Arithmetic operation: SIGN(X). */ +#define ATON_ARITHOP_SIGN_X (0x33UL) + +/** Arithmetic operation: CLIP. */ +#define ATON_ARITHOP_CLIP (0x37UL) + + +/** Get the name of one of the values of the ARITHOP set of enumerated values. */ +#define ATON_ARITHOP_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "AX_BY_C" : \ + (((VALUE) == 1UL) ? "MIN_X_Y" : \ + (((VALUE) == 2UL) ? "MAX_X_Y" : \ + (((VALUE) == 7UL) ? "XY" : \ + (((VALUE) == 11UL) ? "X_AND_Y" : \ + (((VALUE) == 15UL) ? "X_OR_Y" : \ + (((VALUE) == 19UL) ? "NOT_X" : \ + (((VALUE) == 23UL) ? "X_XOR_Y" : \ + (((VALUE) == 27UL) ? "X_EQ_Y" : \ + (((VALUE) == 31UL) ? "X_LT_Y" : \ + (((VALUE) == 35UL) ? "X_LE_Y" : \ + (((VALUE) == 39UL) ? "X_GT_Y" : \ + (((VALUE) == 43UL) ? "X_GE_Y" : \ + (((VALUE) == 47UL) ? "ABS_X" : \ + (((VALUE) == 51UL) ? "SIGN_X" : \ + (((VALUE) == 55UL) ? "CLIP" : "")))))))))))))))) + + +/** + * Check if a value of the ARITHOP set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the ARITHOP set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_ARITHOP_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_ARITHOP_AX_BY_C: + case ATON_ARITHOP_MIN_X_Y: + case ATON_ARITHOP_MAX_X_Y: + case ATON_ARITHOP_XY: + case ATON_ARITHOP_X_AND_Y: + case ATON_ARITHOP_X_OR_Y: + case ATON_ARITHOP_NOT_X: + case ATON_ARITHOP_X_XOR_Y: + case ATON_ARITHOP_X_EQ_Y: + case ATON_ARITHOP_X_LT_Y: + case ATON_ARITHOP_X_LE_Y: + case ATON_ARITHOP_X_GT_Y: + case ATON_ARITHOP_X_GE_Y: + case ATON_ARITHOP_ABS_X: + case ATON_ARITHOP_SIGN_X: + case ATON_ARITHOP_CLIP: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the ARITHOP set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the ARITHOP set of enumerated values + */ + +static inline const int8_t *ATON_ARITHOP_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ARITHOP_AX_BY_C: + str = (const int8_t *)"AX_BY_C"; + break; + + case ATON_ARITHOP_MIN_X_Y: + str = (const int8_t *)"MIN_X_Y"; + break; + + case ATON_ARITHOP_MAX_X_Y: + str = (const int8_t *)"MAX_X_Y"; + break; + + case ATON_ARITHOP_XY: + str = (const int8_t *)"XY"; + break; + + case ATON_ARITHOP_X_AND_Y: + str = (const int8_t *)"X_AND_Y"; + break; + + case ATON_ARITHOP_X_OR_Y: + str = (const int8_t *)"X_OR_Y"; + break; + + case ATON_ARITHOP_NOT_X: + str = (const int8_t *)"NOT_X"; + break; + + case ATON_ARITHOP_X_XOR_Y: + str = (const int8_t *)"X_XOR_Y"; + break; + + case ATON_ARITHOP_X_EQ_Y: + str = (const int8_t *)"X_EQ_Y"; + break; + + case ATON_ARITHOP_X_LT_Y: + str = (const int8_t *)"X_LT_Y"; + break; + + case ATON_ARITHOP_X_LE_Y: + str = (const int8_t *)"X_LE_Y"; + break; + + case ATON_ARITHOP_X_GT_Y: + str = (const int8_t *)"X_GT_Y"; + break; + + case ATON_ARITHOP_X_GE_Y: + str = (const int8_t *)"X_GE_Y"; + break; + + case ATON_ARITHOP_ABS_X: + str = (const int8_t *)"ABS_X"; + break; + + case ATON_ARITHOP_SIGN_X: + str = (const int8_t *)"SIGN_X"; + break; + + case ATON_ARITHOP_CLIP: + str = (const int8_t *)"CLIP"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the ARITHOP set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the ARITHOP set of enumerated values + */ + +static inline const int8_t *ATON_ARITHOP_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ARITHOP_AX_BY_C: + str = (const int8_t *)"Ax + By + C"; + break; + + case ATON_ARITHOP_MIN_X_Y: + str = (const int8_t *)"min(X,Y)"; + break; + + case ATON_ARITHOP_MAX_X_Y: + str = (const int8_t *)"max(X,Y)"; + break; + + case ATON_ARITHOP_XY: + str = (const int8_t *)"X*Y"; + break; + + case ATON_ARITHOP_X_AND_Y: + str = (const int8_t *)"X&Y"; + break; + + case ATON_ARITHOP_X_OR_Y: + str = (const int8_t *)"X|Y"; + break; + + case ATON_ARITHOP_NOT_X: + str = (const int8_t *)"!X"; + break; + + case ATON_ARITHOP_X_XOR_Y: + str = (const int8_t *)"X^Y"; + break; + + case ATON_ARITHOP_X_EQ_Y: + str = (const int8_t *)"X==Y"; + break; + + case ATON_ARITHOP_X_LT_Y: + str = (const int8_t *)"XY"; + break; + + case ATON_ARITHOP_X_GE_Y: + str = (const int8_t *)"X>=Y"; + break; + + case ATON_ARITHOP_ABS_X: + str = (const int8_t *)"ABS(X)"; + break; + + case ATON_ARITHOP_SIGN_X: + str = (const int8_t *)"SIGN(X)"; + break; + + case ATON_ARITHOP_CLIP: + str = (const int8_t *)"CLIP"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* ARITH_MEM set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Arithmethic unit MEM offset: Total 4K addressable. 3K starting from 0x000 to 0xbff addressable by setting translate_addr_en=1, top 1K addressable (0xc00-0xfff) by setting translate_addr_en=0. */ +#define ATON_ARITH_MEM_OFFSET (0x400UL) + + +/** Get the name of one of the values of the ARITH_MEM set of enumerated values. */ +#define ATON_ARITH_MEM_GET_NAME(VALUE) \ + (((VALUE) == 1024UL) ? "OFFSET" : "") + + +/** + * Check if a value of the ARITH_MEM set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the ARITH_MEM set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_ARITH_MEM_IsValid(uint32_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_ARITH_MEM_OFFSET: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the ARITH_MEM set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the ARITH_MEM set of enumerated values + */ + +static inline const int8_t *ATON_ARITH_MEM_GetName(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ARITH_MEM_OFFSET: + str = (const int8_t *)"OFFSET"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the ARITH_MEM set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the ARITH_MEM set of enumerated values + */ + +static inline const int8_t *ATON_ARITH_MEM_GetDesc(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_ARITH_MEM_OFFSET: + str = (const int8_t *)"Total 4K addressable. 3K starting from 0x000 to 0xbff addressable by setting translate_addr_en=1, top 1K addressable (0xc00-0xfff) by setting translate_addr_en=0"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* BLOCKTYPE set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Block type: Stream Switch. */ +#define ATON_BLOCKTYPE_STRSWITCH (0x0UL) + +/** Block type: Stream Engine. */ +#define ATON_BLOCKTYPE_STRENG (0x1UL) + +/** Block type: Sensor Interface. */ +#define ATON_BLOCKTYPE_SENSOR_IF (0x2UL) + +/** Block type: Video Output. */ +#define ATON_BLOCKTYPE_VIDEO_OUT (0x3UL) + +/** Block type: IPU Interface. */ +#define ATON_BLOCKTYPE_IPU_IF (0x4UL) + +/** Block type: ISP Interface. */ +#define ATON_BLOCKTYPE_ISP_IF (0x5UL) + +/** Block type: Morph Filter. */ +#define ATON_BLOCKTYPE_MORPH (0x6UL) + +/** Block type: Background Remove. */ +#define ATON_BLOCKTYPE_BACKREMOVE (0x7UL) + +/** Block type: Reference Frame Update. */ +#define ATON_BLOCKTYPE_REFUPDATE (0x8UL) + +/** Block type: ???. */ +#define ATON_BLOCKTYPE_CONV (0x9UL) + +/** Block type: Cropper. */ +#define ATON_BLOCKTYPE_CROP (0xaUL) + +/** Block type: Corner Detector. */ +#define ATON_BLOCKTYPE_CORNER_DETECT (0xbUL) + +/** Block type: Census. */ +#define ATON_BLOCKTYPE_CENSUS (0xcUL) + +/** Block type: Rect. */ +#define ATON_BLOCKTYPE_RECT (0xeUL) + +/** Block type: JPEG Encoder. */ +#define ATON_BLOCKTYPE_JPEG_ENC (0xfUL) + +/** Block type: JPEG Decoder. */ +#define ATON_BLOCKTYPE_JPEG_DEC (0x10UL) + +/** Block type: Debug Controller. */ +#define ATON_BLOCKTYPE_DEBUG_CTRL (0x11UL) + +/** Block type: GP Controller. */ +#define ATON_BLOCKTYPE_GP_CTRL (0x12UL) + +/** Block type: SBDOG. */ +#define ATON_BLOCKTYPE_SBDOG (0x13UL) + +/** Block type: H264 Decoder. */ +#define ATON_BLOCKTYPE_H264 (0x14UL) + +/** Block type: ????. */ +#define ATON_BLOCKTYPE_MATCH (0x15UL) + +/** Block type: ISP. */ +#define ATON_BLOCKTYPE_ISP (0x16UL) + +/** Block type: Convolution Accelerator. */ +#define ATON_BLOCKTYPE_CONVACC (0x17UL) + +/** Block type: I2C. */ +#define ATON_BLOCKTYPE_I2C (0x18UL) + +/** Block type: Decompression Unit. */ +#define ATON_BLOCKTYPE_DECUN (0x19UL) + +/** Block type: Arithmetic Unit. */ +#define ATON_BLOCKTYPE_ARITH (0x1aUL) + +/** Block type: Activation Unit. */ +#define ATON_BLOCKTYPE_ACTIV (0x1bUL) + +/** Block type: Pooling Accelerator. */ +#define ATON_BLOCKTYPE_POOL (0x1cUL) + +/** Block type: Bus Interface. */ +#define ATON_BLOCKTYPE_BUSIF (0x1dUL) + +/** Block type: Interrupt Controller. */ +#define ATON_BLOCKTYPE_INTCTRL (0x1eUL) + +/** Block type: Clock Controller. */ +#define ATON_BLOCKTYPE_CLKCTRL (0x1fUL) + +/** Block type: Reconfigurable Buffer. */ +#define ATON_BLOCKTYPE_RECBUF (0x20UL) + +/** Block type: Epoch Controller. */ +#define ATON_BLOCKTYPE_EPOCHCTRL (0x21UL) + +/** Block type: Debug Trace. */ +#define ATON_BLOCKTYPE_DEBUG_TRACE (0x22UL) + + +/** Get the name of one of the values of the BLOCKTYPE set of enumerated values. */ +#define ATON_BLOCKTYPE_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "STRSWITCH" : \ + (((VALUE) == 1UL) ? "STRENG" : \ + (((VALUE) == 2UL) ? "SENSOR_IF" : \ + (((VALUE) == 3UL) ? "VIDEO_OUT" : \ + (((VALUE) == 4UL) ? "IPU_IF" : \ + (((VALUE) == 5UL) ? "ISP_IF" : \ + (((VALUE) == 6UL) ? "MORPH" : \ + (((VALUE) == 7UL) ? "BACKREMOVE" : \ + (((VALUE) == 8UL) ? "REFUPDATE" : \ + (((VALUE) == 9UL) ? "CONV" : \ + (((VALUE) == 10UL) ? "CROP" : \ + (((VALUE) == 11UL) ? "CORNER_DETECT" : \ + (((VALUE) == 12UL) ? "CENSUS" : \ + (((VALUE) == 14UL) ? "RECT" : \ + (((VALUE) == 15UL) ? "JPEG_ENC" : \ + (((VALUE) == 16UL) ? "JPEG_DEC" : \ + (((VALUE) == 17UL) ? "DEBUG_CTRL" : \ + (((VALUE) == 18UL) ? "GP_CTRL" : \ + (((VALUE) == 19UL) ? "SBDOG" : \ + (((VALUE) == 20UL) ? "H264" : \ + (((VALUE) == 21UL) ? "MATCH" : \ + (((VALUE) == 22UL) ? "ISP" : \ + (((VALUE) == 23UL) ? "CONVACC" : \ + (((VALUE) == 24UL) ? "I2C" : \ + (((VALUE) == 25UL) ? "DECUN" : \ + (((VALUE) == 26UL) ? "ARITH" : \ + (((VALUE) == 27UL) ? "ACTIV" : \ + (((VALUE) == 28UL) ? "POOL" : \ + (((VALUE) == 29UL) ? "BUSIF" : \ + (((VALUE) == 30UL) ? "INTCTRL" : \ + (((VALUE) == 31UL) ? "CLKCTRL" : \ + (((VALUE) == 32UL) ? "RECBUF" : \ + (((VALUE) == 33UL) ? "EPOCHCTRL" : \ + (((VALUE) == 34UL) ? "DEBUG_TRACE" : "")))))))))))))))))))))))))))))))))) + + +/** + * Check if a value of the BLOCKTYPE set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the BLOCKTYPE set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_BLOCKTYPE_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_BLOCKTYPE_STRSWITCH: + case ATON_BLOCKTYPE_STRENG: + case ATON_BLOCKTYPE_SENSOR_IF: + case ATON_BLOCKTYPE_VIDEO_OUT: + case ATON_BLOCKTYPE_IPU_IF: + case ATON_BLOCKTYPE_ISP_IF: + case ATON_BLOCKTYPE_MORPH: + case ATON_BLOCKTYPE_BACKREMOVE: + case ATON_BLOCKTYPE_REFUPDATE: + case ATON_BLOCKTYPE_CONV: + case ATON_BLOCKTYPE_CROP: + case ATON_BLOCKTYPE_CORNER_DETECT: + case ATON_BLOCKTYPE_CENSUS: + case ATON_BLOCKTYPE_RECT: + case ATON_BLOCKTYPE_JPEG_ENC: + case ATON_BLOCKTYPE_JPEG_DEC: + case ATON_BLOCKTYPE_DEBUG_CTRL: + case ATON_BLOCKTYPE_GP_CTRL: + case ATON_BLOCKTYPE_SBDOG: + case ATON_BLOCKTYPE_H264: + case ATON_BLOCKTYPE_MATCH: + case ATON_BLOCKTYPE_ISP: + case ATON_BLOCKTYPE_CONVACC: + case ATON_BLOCKTYPE_I2C: + case ATON_BLOCKTYPE_DECUN: + case ATON_BLOCKTYPE_ARITH: + case ATON_BLOCKTYPE_ACTIV: + case ATON_BLOCKTYPE_POOL: + case ATON_BLOCKTYPE_BUSIF: + case ATON_BLOCKTYPE_INTCTRL: + case ATON_BLOCKTYPE_CLKCTRL: + case ATON_BLOCKTYPE_RECBUF: + case ATON_BLOCKTYPE_EPOCHCTRL: + case ATON_BLOCKTYPE_DEBUG_TRACE: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the BLOCKTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the BLOCKTYPE set of enumerated values + */ + +static inline const int8_t *ATON_BLOCKTYPE_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_BLOCKTYPE_STRSWITCH: + str = (const int8_t *)"STRSWITCH"; + break; + + case ATON_BLOCKTYPE_STRENG: + str = (const int8_t *)"STRENG"; + break; + + case ATON_BLOCKTYPE_SENSOR_IF: + str = (const int8_t *)"SENSOR_IF"; + break; + + case ATON_BLOCKTYPE_VIDEO_OUT: + str = (const int8_t *)"VIDEO_OUT"; + break; + + case ATON_BLOCKTYPE_IPU_IF: + str = (const int8_t *)"IPU_IF"; + break; + + case ATON_BLOCKTYPE_ISP_IF: + str = (const int8_t *)"ISP_IF"; + break; + + case ATON_BLOCKTYPE_MORPH: + str = (const int8_t *)"MORPH"; + break; + + case ATON_BLOCKTYPE_BACKREMOVE: + str = (const int8_t *)"BACKREMOVE"; + break; + + case ATON_BLOCKTYPE_REFUPDATE: + str = (const int8_t *)"REFUPDATE"; + break; + + case ATON_BLOCKTYPE_CONV: + str = (const int8_t *)"CONV"; + break; + + case ATON_BLOCKTYPE_CROP: + str = (const int8_t *)"CROP"; + break; + + case ATON_BLOCKTYPE_CORNER_DETECT: + str = (const int8_t *)"CORNER_DETECT"; + break; + + case ATON_BLOCKTYPE_CENSUS: + str = (const int8_t *)"CENSUS"; + break; + + case ATON_BLOCKTYPE_RECT: + str = (const int8_t *)"RECT"; + break; + + case ATON_BLOCKTYPE_JPEG_ENC: + str = (const int8_t *)"JPEG_ENC"; + break; + + case ATON_BLOCKTYPE_JPEG_DEC: + str = (const int8_t *)"JPEG_DEC"; + break; + + case ATON_BLOCKTYPE_DEBUG_CTRL: + str = (const int8_t *)"DEBUG_CTRL"; + break; + + case ATON_BLOCKTYPE_GP_CTRL: + str = (const int8_t *)"GP_CTRL"; + break; + + case ATON_BLOCKTYPE_SBDOG: + str = (const int8_t *)"SBDOG"; + break; + + case ATON_BLOCKTYPE_H264: + str = (const int8_t *)"H264"; + break; + + case ATON_BLOCKTYPE_MATCH: + str = (const int8_t *)"MATCH"; + break; + + case ATON_BLOCKTYPE_ISP: + str = (const int8_t *)"ISP"; + break; + + case ATON_BLOCKTYPE_CONVACC: + str = (const int8_t *)"CONVACC"; + break; + + case ATON_BLOCKTYPE_I2C: + str = (const int8_t *)"I2C"; + break; + + case ATON_BLOCKTYPE_DECUN: + str = (const int8_t *)"DECUN"; + break; + + case ATON_BLOCKTYPE_ARITH: + str = (const int8_t *)"ARITH"; + break; + + case ATON_BLOCKTYPE_ACTIV: + str = (const int8_t *)"ACTIV"; + break; + + case ATON_BLOCKTYPE_POOL: + str = (const int8_t *)"POOL"; + break; + + case ATON_BLOCKTYPE_BUSIF: + str = (const int8_t *)"BUSIF"; + break; + + case ATON_BLOCKTYPE_INTCTRL: + str = (const int8_t *)"INTCTRL"; + break; + + case ATON_BLOCKTYPE_CLKCTRL: + str = (const int8_t *)"CLKCTRL"; + break; + + case ATON_BLOCKTYPE_RECBUF: + str = (const int8_t *)"RECBUF"; + break; + + case ATON_BLOCKTYPE_EPOCHCTRL: + str = (const int8_t *)"EPOCHCTRL"; + break; + + case ATON_BLOCKTYPE_DEBUG_TRACE: + str = (const int8_t *)"DEBUG_TRACE"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the BLOCKTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the BLOCKTYPE set of enumerated values + */ + +static inline const int8_t *ATON_BLOCKTYPE_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_BLOCKTYPE_STRSWITCH: + str = (const int8_t *)"Stream Switch"; + break; + + case ATON_BLOCKTYPE_STRENG: + str = (const int8_t *)"Stream Engine"; + break; + + case ATON_BLOCKTYPE_SENSOR_IF: + str = (const int8_t *)"Sensor Interface"; + break; + + case ATON_BLOCKTYPE_VIDEO_OUT: + str = (const int8_t *)"Video Output"; + break; + + case ATON_BLOCKTYPE_IPU_IF: + str = (const int8_t *)"IPU Interface"; + break; + + case ATON_BLOCKTYPE_ISP_IF: + str = (const int8_t *)"ISP Interface"; + break; + + case ATON_BLOCKTYPE_MORPH: + str = (const int8_t *)"Morph Filter"; + break; + + case ATON_BLOCKTYPE_BACKREMOVE: + str = (const int8_t *)"Background Remove"; + break; + + case ATON_BLOCKTYPE_REFUPDATE: + str = (const int8_t *)"Reference Frame Update"; + break; + + case ATON_BLOCKTYPE_CONV: + str = (const int8_t *)"???"; + break; + + case ATON_BLOCKTYPE_CROP: + str = (const int8_t *)"Cropper"; + break; + + case ATON_BLOCKTYPE_CORNER_DETECT: + str = (const int8_t *)"Corner Detector"; + break; + + case ATON_BLOCKTYPE_CENSUS: + str = (const int8_t *)"Census"; + break; + + case ATON_BLOCKTYPE_RECT: + str = (const int8_t *)"Rect"; + break; + + case ATON_BLOCKTYPE_JPEG_ENC: + str = (const int8_t *)"JPEG Encoder"; + break; + + case ATON_BLOCKTYPE_JPEG_DEC: + str = (const int8_t *)"JPEG Decoder"; + break; + + case ATON_BLOCKTYPE_DEBUG_CTRL: + str = (const int8_t *)"Debug Controller"; + break; + + case ATON_BLOCKTYPE_GP_CTRL: + str = (const int8_t *)"GP Controller"; + break; + + case ATON_BLOCKTYPE_SBDOG: + str = (const int8_t *)"SBDOG"; + break; + + case ATON_BLOCKTYPE_H264: + str = (const int8_t *)"H264 Decoder"; + break; + + case ATON_BLOCKTYPE_MATCH: + str = (const int8_t *)"????"; + break; + + case ATON_BLOCKTYPE_ISP: + str = (const int8_t *)"ISP"; + break; + + case ATON_BLOCKTYPE_CONVACC: + str = (const int8_t *)"Convolution Accelerator"; + break; + + case ATON_BLOCKTYPE_I2C: + str = (const int8_t *)"I2C"; + break; + + case ATON_BLOCKTYPE_DECUN: + str = (const int8_t *)"Decompression Unit"; + break; + + case ATON_BLOCKTYPE_ARITH: + str = (const int8_t *)"Arithmetic Unit"; + break; + + case ATON_BLOCKTYPE_ACTIV: + str = (const int8_t *)"Activation Unit"; + break; + + case ATON_BLOCKTYPE_POOL: + str = (const int8_t *)"Pooling Accelerator"; + break; + + case ATON_BLOCKTYPE_BUSIF: + str = (const int8_t *)"Bus Interface"; + break; + + case ATON_BLOCKTYPE_INTCTRL: + str = (const int8_t *)"Interrupt Controller"; + break; + + case ATON_BLOCKTYPE_CLKCTRL: + str = (const int8_t *)"Clock Controller"; + break; + + case ATON_BLOCKTYPE_RECBUF: + str = (const int8_t *)"Reconfigurable Buffer"; + break; + + case ATON_BLOCKTYPE_EPOCHCTRL: + str = (const int8_t *)"Epoch Controller"; + break; + + case ATON_BLOCKTYPE_DEBUG_TRACE: + str = (const int8_t *)"Debug Trace"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* CHS set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Channels: CH0 / Red / Y. */ +#define ATON_CHS_RY (0x0UL) + +/** Channels: CH1 / Green / Cb. */ +#define ATON_CHS_GCB (0x1UL) + +/** Channels: CH2 / Blue / Cr. */ +#define ATON_CHS_BCR (0x2UL) + +/** Channels: Reserved / do not use. */ +#define ATON_CHS_RES (0x3UL) + + +/** Get the name of one of the values of the CHS set of enumerated values. */ +#define ATON_CHS_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "RY" : \ + (((VALUE) == 1UL) ? "GCB" : \ + (((VALUE) == 2UL) ? "BCR" : \ + (((VALUE) == 3UL) ? "RES" : "")))) + + +/** + * Check if a value of the CHS set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the CHS set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_CHS_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_CHS_RY: + case ATON_CHS_GCB: + case ATON_CHS_BCR: + case ATON_CHS_RES: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the CHS set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the CHS set of enumerated values + */ + +static inline const int8_t *ATON_CHS_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_CHS_RY: + str = (const int8_t *)"RY"; + break; + + case ATON_CHS_GCB: + str = (const int8_t *)"GCB"; + break; + + case ATON_CHS_BCR: + str = (const int8_t *)"BCR"; + break; + + case ATON_CHS_RES: + str = (const int8_t *)"RES"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the CHS set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the CHS set of enumerated values + */ + +static inline const int8_t *ATON_CHS_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_CHS_RY: + str = (const int8_t *)"CH0 / Red / Y"; + break; + + case ATON_CHS_GCB: + str = (const int8_t *)"CH1 / Green / Cb"; + break; + + case ATON_CHS_BCR: + str = (const int8_t *)"CH2 / Blue / Cr"; + break; + + case ATON_CHS_RES: + str = (const int8_t *)"Reserved / do not use"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* COEFFTYPE set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Coefficient type: Scalar coefficient type. */ +#define ATON_COEFFTYPE_SCALAR (0x0UL) + +/** Coefficient type: Vector coefficient type. */ +#define ATON_COEFFTYPE_VECTOR (0x1UL) + + +/** Get the name of one of the values of the COEFFTYPE set of enumerated values. */ +#define ATON_COEFFTYPE_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "SCALAR" : \ + (((VALUE) == 1UL) ? "VECTOR" : "")) + + +/** + * Check if a value of the COEFFTYPE set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the COEFFTYPE set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_COEFFTYPE_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_COEFFTYPE_SCALAR: + case ATON_COEFFTYPE_VECTOR: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the COEFFTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the COEFFTYPE set of enumerated values + */ + +static inline const int8_t *ATON_COEFFTYPE_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_COEFFTYPE_SCALAR: + str = (const int8_t *)"SCALAR"; + break; + + case ATON_COEFFTYPE_VECTOR: + str = (const int8_t *)"VECTOR"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the COEFFTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the COEFFTYPE set of enumerated values + */ + +static inline const int8_t *ATON_COEFFTYPE_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_COEFFTYPE_SCALAR: + str = (const int8_t *)"Scalar coefficient type"; + break; + + case ATON_COEFFTYPE_VECTOR: + str = (const int8_t *)"Vector coefficient type"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* DECUN_BFMT set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** BFORMAT values: CV1CW1LAST0. */ +#define ATON_DECUN_BFMT_CV1CW1LAST0 (0x0UL) + +/** BFORMAT values: CV1CW2LAST0. */ +#define ATON_DECUN_BFMT_CV1CW2LAST0 (0x100UL) + +/** BFORMAT values: CV1CW3LAST0. */ +#define ATON_DECUN_BFMT_CV1CW3LAST0 (0x200UL) + +/** BFORMAT values: CV1CW4LAST0. */ +#define ATON_DECUN_BFMT_CV1CW4LAST0 (0x300UL) + +/** BFORMAT values: CV1CW5LAST0. */ +#define ATON_DECUN_BFMT_CV1CW5LAST0 (0x400UL) + +/** BFORMAT values: CV1CW6LAST0. */ +#define ATON_DECUN_BFMT_CV1CW6LAST0 (0x500UL) + +/** BFORMAT values: CV1CW7LAST0. */ +#define ATON_DECUN_BFMT_CV1CW7LAST0 (0x600UL) + +/** BFORMAT values: CV1CW8LAST0. */ +#define ATON_DECUN_BFMT_CV1CW8LAST0 (0x700UL) + +/** BFORMAT values: CV1CW2LAST1. */ +#define ATON_DECUN_BFMT_CV1CW2LAST1 (0x1100UL) + +/** BFORMAT values: CV1CW3LAST1. */ +#define ATON_DECUN_BFMT_CV1CW3LAST1 (0x1200UL) + +/** BFORMAT values: CV1CW4LAST1. */ +#define ATON_DECUN_BFMT_CV1CW4LAST1 (0x1300UL) + +/** BFORMAT values: CV1CW5LAST1. */ +#define ATON_DECUN_BFMT_CV1CW5LAST1 (0x1400UL) + +/** BFORMAT values: CV1CW6LAST1. */ +#define ATON_DECUN_BFMT_CV1CW6LAST1 (0x1500UL) + +/** BFORMAT values: CV1CW7LAST1. */ +#define ATON_DECUN_BFMT_CV1CW7LAST1 (0x1600UL) + +/** BFORMAT values: CV1CW8LAST1. */ +#define ATON_DECUN_BFMT_CV1CW8LAST1 (0x1700UL) + +/** BFORMAT values: CV1CW3LAST2. */ +#define ATON_DECUN_BFMT_CV1CW3LAST2 (0x2200UL) + +/** BFORMAT values: CV1CW4LAST2. */ +#define ATON_DECUN_BFMT_CV1CW4LAST2 (0x2300UL) + +/** BFORMAT values: CV1CW5LAST2. */ +#define ATON_DECUN_BFMT_CV1CW5LAST2 (0x2400UL) + +/** BFORMAT values: CV1CW6LAST2. */ +#define ATON_DECUN_BFMT_CV1CW6LAST2 (0x2500UL) + +/** BFORMAT values: CV1CW7LAST2. */ +#define ATON_DECUN_BFMT_CV1CW7LAST2 (0x2600UL) + +/** BFORMAT values: CV1CW8LAST2. */ +#define ATON_DECUN_BFMT_CV1CW8LAST2 (0x2700UL) + +/** BFORMAT values: CV1CW4LAST3. */ +#define ATON_DECUN_BFMT_CV1CW4LAST3 (0x3300UL) + +/** BFORMAT values: CV1CW5LAST3. */ +#define ATON_DECUN_BFMT_CV1CW5LAST3 (0x3400UL) + +/** BFORMAT values: CV1CW6LAST3. */ +#define ATON_DECUN_BFMT_CV1CW6LAST3 (0x3500UL) + +/** BFORMAT values: CV1CW7LAST3. */ +#define ATON_DECUN_BFMT_CV1CW7LAST3 (0x3600UL) + +/** BFORMAT values: CV1CW8LAST3. */ +#define ATON_DECUN_BFMT_CV1CW8LAST3 (0x3700UL) + +/** BFORMAT values: CV1CW5LAST4. */ +#define ATON_DECUN_BFMT_CV1CW5LAST4 (0x4400UL) + +/** BFORMAT values: CV1CW6LAST4. */ +#define ATON_DECUN_BFMT_CV1CW6LAST4 (0x4500UL) + +/** BFORMAT values: CV1CW7LAST4. */ +#define ATON_DECUN_BFMT_CV1CW7LAST4 (0x4600UL) + +/** BFORMAT values: CV1CW8LAST4. */ +#define ATON_DECUN_BFMT_CV1CW8LAST4 (0x4700UL) + +/** BFORMAT values: CV1CW6LAST5. */ +#define ATON_DECUN_BFMT_CV1CW6LAST5 (0x5500UL) + +/** BFORMAT values: CV1CW7LAST5. */ +#define ATON_DECUN_BFMT_CV1CW7LAST5 (0x5600UL) + +/** BFORMAT values: CV1CW8LAST5. */ +#define ATON_DECUN_BFMT_CV1CW8LAST5 (0x5700UL) + +/** BFORMAT values: CV1CW7LAST6. */ +#define ATON_DECUN_BFMT_CV1CW7LAST6 (0x6600UL) + +/** BFORMAT values: CV1CW8LAST6. */ +#define ATON_DECUN_BFMT_CV1CW8LAST6 (0x6700UL) + +/** BFORMAT values: CV1CW8LAST7. */ +#define ATON_DECUN_BFMT_CV1CW8LAST7 (0x7700UL) + +/** BFORMAT values: CV2CW1LAST0. */ +#define ATON_DECUN_BFMT_CV2CW1LAST0 (0x1UL) + +/** BFORMAT values: CV2CW2LAST0. */ +#define ATON_DECUN_BFMT_CV2CW2LAST0 (0x101UL) + +/** BFORMAT values: CV2CW3LAST0. */ +#define ATON_DECUN_BFMT_CV2CW3LAST0 (0x201UL) + +/** BFORMAT values: CV2CW4LAST0. */ +#define ATON_DECUN_BFMT_CV2CW4LAST0 (0x301UL) + +/** BFORMAT values: CV2CW5LAST0. */ +#define ATON_DECUN_BFMT_CV2CW5LAST0 (0x401UL) + +/** BFORMAT values: CV2CW6LAST0. */ +#define ATON_DECUN_BFMT_CV2CW6LAST0 (0x501UL) + +/** BFORMAT values: CV2CW7LAST0. */ +#define ATON_DECUN_BFMT_CV2CW7LAST0 (0x601UL) + +/** BFORMAT values: CV2CW8LAST0. */ +#define ATON_DECUN_BFMT_CV2CW8LAST0 (0x701UL) + +/** BFORMAT values: CV2CW2LAST1. */ +#define ATON_DECUN_BFMT_CV2CW2LAST1 (0x1101UL) + +/** BFORMAT values: CV2CW3LAST1. */ +#define ATON_DECUN_BFMT_CV2CW3LAST1 (0x1201UL) + +/** BFORMAT values: CV2CW4LAST1. */ +#define ATON_DECUN_BFMT_CV2CW4LAST1 (0x1301UL) + +/** BFORMAT values: CV2CW5LAST1. */ +#define ATON_DECUN_BFMT_CV2CW5LAST1 (0x1401UL) + +/** BFORMAT values: CV2CW6LAST1. */ +#define ATON_DECUN_BFMT_CV2CW6LAST1 (0x1501UL) + +/** BFORMAT values: CV2CW7LAST1. */ +#define ATON_DECUN_BFMT_CV2CW7LAST1 (0x1601UL) + +/** BFORMAT values: CV2CW8LAST1. */ +#define ATON_DECUN_BFMT_CV2CW8LAST1 (0x1701UL) + +/** BFORMAT values: CV2CW3LAST2. */ +#define ATON_DECUN_BFMT_CV2CW3LAST2 (0x2201UL) + +/** BFORMAT values: CV2CW4LAST2. */ +#define ATON_DECUN_BFMT_CV2CW4LAST2 (0x2301UL) + +/** BFORMAT values: CV2CW5LAST2. */ +#define ATON_DECUN_BFMT_CV2CW5LAST2 (0x2401UL) + +/** BFORMAT values: CV2CW6LAST2. */ +#define ATON_DECUN_BFMT_CV2CW6LAST2 (0x2501UL) + +/** BFORMAT values: CV2CW7LAST2. */ +#define ATON_DECUN_BFMT_CV2CW7LAST2 (0x2601UL) + +/** BFORMAT values: CV2CW8LAST2. */ +#define ATON_DECUN_BFMT_CV2CW8LAST2 (0x2701UL) + +/** BFORMAT values: CV2CW4LAST3. */ +#define ATON_DECUN_BFMT_CV2CW4LAST3 (0x3301UL) + +/** BFORMAT values: CV2CW5LAST3. */ +#define ATON_DECUN_BFMT_CV2CW5LAST3 (0x3401UL) + +/** BFORMAT values: CV2CW6LAST3. */ +#define ATON_DECUN_BFMT_CV2CW6LAST3 (0x3501UL) + +/** BFORMAT values: CV2CW7LAST3. */ +#define ATON_DECUN_BFMT_CV2CW7LAST3 (0x3601UL) + +/** BFORMAT values: CV2CW8LAST3. */ +#define ATON_DECUN_BFMT_CV2CW8LAST3 (0x3701UL) + +/** BFORMAT values: CV2CW5LAST4. */ +#define ATON_DECUN_BFMT_CV2CW5LAST4 (0x4401UL) + +/** BFORMAT values: CV2CW6LAST4. */ +#define ATON_DECUN_BFMT_CV2CW6LAST4 (0x4501UL) + +/** BFORMAT values: CV2CW7LAST4. */ +#define ATON_DECUN_BFMT_CV2CW7LAST4 (0x4601UL) + +/** BFORMAT values: CV2CW8LAST4. */ +#define ATON_DECUN_BFMT_CV2CW8LAST4 (0x4701UL) + +/** BFORMAT values: CV2CW6LAST5. */ +#define ATON_DECUN_BFMT_CV2CW6LAST5 (0x5501UL) + +/** BFORMAT values: CV2CW7LAST5. */ +#define ATON_DECUN_BFMT_CV2CW7LAST5 (0x5601UL) + +/** BFORMAT values: CV2CW8LAST5. */ +#define ATON_DECUN_BFMT_CV2CW8LAST5 (0x5701UL) + +/** BFORMAT values: CV2CW7LAST6. */ +#define ATON_DECUN_BFMT_CV2CW7LAST6 (0x6601UL) + +/** BFORMAT values: CV2CW8LAST6. */ +#define ATON_DECUN_BFMT_CV2CW8LAST6 (0x6701UL) + +/** BFORMAT values: CV2CW8LAST7. */ +#define ATON_DECUN_BFMT_CV2CW8LAST7 (0x7701UL) + +/** BFORMAT values: CV4CW1LAST0. */ +#define ATON_DECUN_BFMT_CV4CW1LAST0 (0x3UL) + +/** BFORMAT values: CV4CW2LAST0. */ +#define ATON_DECUN_BFMT_CV4CW2LAST0 (0x103UL) + +/** BFORMAT values: CV4CW3LAST0. */ +#define ATON_DECUN_BFMT_CV4CW3LAST0 (0x203UL) + +/** BFORMAT values: CV4CW4LAST0. */ +#define ATON_DECUN_BFMT_CV4CW4LAST0 (0x303UL) + +/** BFORMAT values: CV4CW5LAST0. */ +#define ATON_DECUN_BFMT_CV4CW5LAST0 (0x403UL) + +/** BFORMAT values: CV4CW6LAST0. */ +#define ATON_DECUN_BFMT_CV4CW6LAST0 (0x503UL) + +/** BFORMAT values: CV4CW7LAST0. */ +#define ATON_DECUN_BFMT_CV4CW7LAST0 (0x603UL) + +/** BFORMAT values: CV4CW8LAST0. */ +#define ATON_DECUN_BFMT_CV4CW8LAST0 (0x703UL) + +/** BFORMAT values: CV4CW2LAST1. */ +#define ATON_DECUN_BFMT_CV4CW2LAST1 (0x1103UL) + +/** BFORMAT values: CV4CW3LAST1. */ +#define ATON_DECUN_BFMT_CV4CW3LAST1 (0x1203UL) + +/** BFORMAT values: CV4CW4LAST1. */ +#define ATON_DECUN_BFMT_CV4CW4LAST1 (0x1303UL) + +/** BFORMAT values: CV4CW5LAST1. */ +#define ATON_DECUN_BFMT_CV4CW5LAST1 (0x1403UL) + +/** BFORMAT values: CV4CW6LAST1. */ +#define ATON_DECUN_BFMT_CV4CW6LAST1 (0x1503UL) + +/** BFORMAT values: CV4CW7LAST1. */ +#define ATON_DECUN_BFMT_CV4CW7LAST1 (0x1603UL) + +/** BFORMAT values: CV4CW8LAST1. */ +#define ATON_DECUN_BFMT_CV4CW8LAST1 (0x1703UL) + +/** BFORMAT values: CV4CW3LAST2. */ +#define ATON_DECUN_BFMT_CV4CW3LAST2 (0x2203UL) + +/** BFORMAT values: CV4CW4LAST2. */ +#define ATON_DECUN_BFMT_CV4CW4LAST2 (0x2303UL) + +/** BFORMAT values: CV4CW5LAST2. */ +#define ATON_DECUN_BFMT_CV4CW5LAST2 (0x2403UL) + +/** BFORMAT values: CV4CW6LAST2. */ +#define ATON_DECUN_BFMT_CV4CW6LAST2 (0x2503UL) + +/** BFORMAT values: CV4CW7LAST2. */ +#define ATON_DECUN_BFMT_CV4CW7LAST2 (0x2603UL) + +/** BFORMAT values: CV4CW8LAST2. */ +#define ATON_DECUN_BFMT_CV4CW8LAST2 (0x2703UL) + +/** BFORMAT values: CV4CW4LAST3. */ +#define ATON_DECUN_BFMT_CV4CW4LAST3 (0x3303UL) + +/** BFORMAT values: CV4CW5LAST3. */ +#define ATON_DECUN_BFMT_CV4CW5LAST3 (0x3403UL) + +/** BFORMAT values: CV4CW6LAST3. */ +#define ATON_DECUN_BFMT_CV4CW6LAST3 (0x3503UL) + +/** BFORMAT values: CV4CW7LAST3. */ +#define ATON_DECUN_BFMT_CV4CW7LAST3 (0x3603UL) + +/** BFORMAT values: CV4CW8LAST3. */ +#define ATON_DECUN_BFMT_CV4CW8LAST3 (0x3703UL) + +/** BFORMAT values: CV4CW5LAST4. */ +#define ATON_DECUN_BFMT_CV4CW5LAST4 (0x4403UL) + +/** BFORMAT values: CV4CW6LAST4. */ +#define ATON_DECUN_BFMT_CV4CW6LAST4 (0x4503UL) + +/** BFORMAT values: CV4CW7LAST4. */ +#define ATON_DECUN_BFMT_CV4CW7LAST4 (0x4603UL) + +/** BFORMAT values: CV4CW8LAST4. */ +#define ATON_DECUN_BFMT_CV4CW8LAST4 (0x4703UL) + +/** BFORMAT values: CV4CW6LAST5. */ +#define ATON_DECUN_BFMT_CV4CW6LAST5 (0x5503UL) + +/** BFORMAT values: CV4CW7LAST5. */ +#define ATON_DECUN_BFMT_CV4CW7LAST5 (0x5603UL) + +/** BFORMAT values: CV4CW8LAST5. */ +#define ATON_DECUN_BFMT_CV4CW8LAST5 (0x5703UL) + +/** BFORMAT values: CV4CW7LAST6. */ +#define ATON_DECUN_BFMT_CV4CW7LAST6 (0x6603UL) + +/** BFORMAT values: CV4CW8LAST6. */ +#define ATON_DECUN_BFMT_CV4CW8LAST6 (0x6703UL) + +/** BFORMAT values: CV4CW8LAST7. */ +#define ATON_DECUN_BFMT_CV4CW8LAST7 (0x7703UL) + +/** BFORMAT values: CV8CW1LAST0. */ +#define ATON_DECUN_BFMT_CV8CW1LAST0 (0x7UL) + +/** BFORMAT values: CV8CW2LAST0. */ +#define ATON_DECUN_BFMT_CV8CW2LAST0 (0x107UL) + +/** BFORMAT values: CV8CW3LAST0. */ +#define ATON_DECUN_BFMT_CV8CW3LAST0 (0x207UL) + +/** BFORMAT values: CV8CW4LAST0. */ +#define ATON_DECUN_BFMT_CV8CW4LAST0 (0x307UL) + +/** BFORMAT values: CV8CW5LAST0. */ +#define ATON_DECUN_BFMT_CV8CW5LAST0 (0x407UL) + +/** BFORMAT values: CV8CW6LAST0. */ +#define ATON_DECUN_BFMT_CV8CW6LAST0 (0x507UL) + +/** BFORMAT values: CV8CW7LAST0. */ +#define ATON_DECUN_BFMT_CV8CW7LAST0 (0x607UL) + +/** BFORMAT values: CV8CW8LAST0. */ +#define ATON_DECUN_BFMT_CV8CW8LAST0 (0x707UL) + +/** BFORMAT values: CV8CW2LAST1. */ +#define ATON_DECUN_BFMT_CV8CW2LAST1 (0x1107UL) + +/** BFORMAT values: CV8CW3LAST1. */ +#define ATON_DECUN_BFMT_CV8CW3LAST1 (0x1207UL) + +/** BFORMAT values: CV8CW4LAST1. */ +#define ATON_DECUN_BFMT_CV8CW4LAST1 (0x1307UL) + +/** BFORMAT values: CV8CW5LAST1. */ +#define ATON_DECUN_BFMT_CV8CW5LAST1 (0x1407UL) + +/** BFORMAT values: CV8CW6LAST1. */ +#define ATON_DECUN_BFMT_CV8CW6LAST1 (0x1507UL) + +/** BFORMAT values: CV8CW7LAST1. */ +#define ATON_DECUN_BFMT_CV8CW7LAST1 (0x1607UL) + +/** BFORMAT values: CV8CW8LAST1. */ +#define ATON_DECUN_BFMT_CV8CW8LAST1 (0x1707UL) + +/** BFORMAT values: CV8CW3LAST2. */ +#define ATON_DECUN_BFMT_CV8CW3LAST2 (0x2207UL) + +/** BFORMAT values: CV8CW4LAST2. */ +#define ATON_DECUN_BFMT_CV8CW4LAST2 (0x2307UL) + +/** BFORMAT values: CV8CW5LAST2. */ +#define ATON_DECUN_BFMT_CV8CW5LAST2 (0x2407UL) + +/** BFORMAT values: CV8CW6LAST2. */ +#define ATON_DECUN_BFMT_CV8CW6LAST2 (0x2507UL) + +/** BFORMAT values: CV8CW7LAST2. */ +#define ATON_DECUN_BFMT_CV8CW7LAST2 (0x2607UL) + +/** BFORMAT values: CV8CW8LAST2. */ +#define ATON_DECUN_BFMT_CV8CW8LAST2 (0x2707UL) + +/** BFORMAT values: CV8CW4LAST3. */ +#define ATON_DECUN_BFMT_CV8CW4LAST3 (0x3307UL) + +/** BFORMAT values: CV8CW5LAST3. */ +#define ATON_DECUN_BFMT_CV8CW5LAST3 (0x3407UL) + +/** BFORMAT values: CV8CW6LAST3. */ +#define ATON_DECUN_BFMT_CV8CW6LAST3 (0x3507UL) + +/** BFORMAT values: CV8CW7LAST3. */ +#define ATON_DECUN_BFMT_CV8CW7LAST3 (0x3607UL) + +/** BFORMAT values: CV8CW8LAST3. */ +#define ATON_DECUN_BFMT_CV8CW8LAST3 (0x3707UL) + +/** BFORMAT values: CV8CW5LAST4. */ +#define ATON_DECUN_BFMT_CV8CW5LAST4 (0x4407UL) + +/** BFORMAT values: CV8CW6LAST4. */ +#define ATON_DECUN_BFMT_CV8CW6LAST4 (0x4507UL) + +/** BFORMAT values: CV8CW7LAST4. */ +#define ATON_DECUN_BFMT_CV8CW7LAST4 (0x4607UL) + +/** BFORMAT values: CV8CW8LAST4. */ +#define ATON_DECUN_BFMT_CV8CW8LAST4 (0x4707UL) + +/** BFORMAT values: CV8CW6LAST5. */ +#define ATON_DECUN_BFMT_CV8CW6LAST5 (0x5507UL) + +/** BFORMAT values: CV8CW7LAST5. */ +#define ATON_DECUN_BFMT_CV8CW7LAST5 (0x5607UL) + +/** BFORMAT values: CV8CW8LAST5. */ +#define ATON_DECUN_BFMT_CV8CW8LAST5 (0x5707UL) + +/** BFORMAT values: CV8CW7LAST6. */ +#define ATON_DECUN_BFMT_CV8CW7LAST6 (0x6607UL) + +/** BFORMAT values: CV8CW8LAST6. */ +#define ATON_DECUN_BFMT_CV8CW8LAST6 (0x6707UL) + +/** BFORMAT values: CV8CW8LAST7. */ +#define ATON_DECUN_BFMT_CV8CW8LAST7 (0x7707UL) + +/** BFORMAT values: CV16CW1LAST0. */ +#define ATON_DECUN_BFMT_CV16CW1LAST0 (0xfUL) + +/** BFORMAT values: CV16CW2LAST0. */ +#define ATON_DECUN_BFMT_CV16CW2LAST0 (0x10fUL) + +/** BFORMAT values: CV16CW3LAST0. */ +#define ATON_DECUN_BFMT_CV16CW3LAST0 (0x20fUL) + +/** BFORMAT values: CV16CW4LAST0. */ +#define ATON_DECUN_BFMT_CV16CW4LAST0 (0x30fUL) + +/** BFORMAT values: CV16CW5LAST0. */ +#define ATON_DECUN_BFMT_CV16CW5LAST0 (0x40fUL) + +/** BFORMAT values: CV16CW6LAST0. */ +#define ATON_DECUN_BFMT_CV16CW6LAST0 (0x50fUL) + +/** BFORMAT values: CV16CW7LAST0. */ +#define ATON_DECUN_BFMT_CV16CW7LAST0 (0x60fUL) + +/** BFORMAT values: CV16CW8LAST0. */ +#define ATON_DECUN_BFMT_CV16CW8LAST0 (0x70fUL) + +/** BFORMAT values: CV32CW1LAST0. */ +#define ATON_DECUN_BFMT_CV32CW1LAST0 (0x1fUL) + +/** BFORMAT values: CV32CW2LAST0. */ +#define ATON_DECUN_BFMT_CV32CW2LAST0 (0x11fUL) + +/** BFORMAT values: CV32CW3LAST0. */ +#define ATON_DECUN_BFMT_CV32CW3LAST0 (0x21fUL) + +/** BFORMAT values: CV32CW4LAST0. */ +#define ATON_DECUN_BFMT_CV32CW4LAST0 (0x31fUL) + +/** BFORMAT values: CV32CW5LAST0. */ +#define ATON_DECUN_BFMT_CV32CW5LAST0 (0x41fUL) + +/** BFORMAT values: CV32CW6LAST0. */ +#define ATON_DECUN_BFMT_CV32CW6LAST0 (0x51fUL) + +/** BFORMAT values: CV32CW7LAST0. */ +#define ATON_DECUN_BFMT_CV32CW7LAST0 (0x61fUL) + +/** BFORMAT values: CV32CW8LAST0. */ +#define ATON_DECUN_BFMT_CV32CW8LAST0 (0x71fUL) + +/** BFORMAT values: CV64CW1LAST0. */ +#define ATON_DECUN_BFMT_CV64CW1LAST0 (0x3fUL) + +/** BFORMAT values: CV64CW2LAST0. */ +#define ATON_DECUN_BFMT_CV64CW2LAST0 (0x13fUL) + +/** BFORMAT values: CV64CW3LAST0. */ +#define ATON_DECUN_BFMT_CV64CW3LAST0 (0x23fUL) + +/** BFORMAT values: CV64CW4LAST0. */ +#define ATON_DECUN_BFMT_CV64CW4LAST0 (0x33fUL) + +/** BFORMAT values: CV64CW5LAST0. */ +#define ATON_DECUN_BFMT_CV64CW5LAST0 (0x43fUL) + +/** BFORMAT values: CV64CW6LAST0. */ +#define ATON_DECUN_BFMT_CV64CW6LAST0 (0x53fUL) + +/** BFORMAT values: CV64CW7LAST0. */ +#define ATON_DECUN_BFMT_CV64CW7LAST0 (0x63fUL) + +/** BFORMAT values: CV64CW8LAST0. */ +#define ATON_DECUN_BFMT_CV64CW8LAST0 (0x73fUL) + +/** BFORMAT values: CV128CW1LAST0. */ +#define ATON_DECUN_BFMT_CV128CW1LAST0 (0x7fUL) + +/** BFORMAT values: CV128CW2LAST0. */ +#define ATON_DECUN_BFMT_CV128CW2LAST0 (0x17fUL) + +/** BFORMAT values: CV128CW3LAST0. */ +#define ATON_DECUN_BFMT_CV128CW3LAST0 (0x27fUL) + +/** BFORMAT values: CV128CW4LAST0. */ +#define ATON_DECUN_BFMT_CV128CW4LAST0 (0x37fUL) + +/** BFORMAT values: CV128CW5LAST0. */ +#define ATON_DECUN_BFMT_CV128CW5LAST0 (0x47fUL) + +/** BFORMAT values: CV128CW6LAST0. */ +#define ATON_DECUN_BFMT_CV128CW6LAST0 (0x57fUL) + +/** BFORMAT values: CV128CW7LAST0. */ +#define ATON_DECUN_BFMT_CV128CW7LAST0 (0x67fUL) + +/** BFORMAT values: CV128CW8LAST0. */ +#define ATON_DECUN_BFMT_CV128CW8LAST0 (0x77fUL) + +/** BFORMAT values: CV256CW1LAST0. */ +#define ATON_DECUN_BFMT_CV256CW1LAST0 (0xffUL) + +/** BFORMAT values: CV256CW2LAST0. */ +#define ATON_DECUN_BFMT_CV256CW2LAST0 (0x1ffUL) + +/** BFORMAT values: CV256CW3LAST0. */ +#define ATON_DECUN_BFMT_CV256CW3LAST0 (0x2ffUL) + +/** BFORMAT values: CV256CW4LAST0. */ +#define ATON_DECUN_BFMT_CV256CW4LAST0 (0x3ffUL) + +/** BFORMAT values: CV256CW5LAST0. */ +#define ATON_DECUN_BFMT_CV256CW5LAST0 (0x4ffUL) + +/** BFORMAT values: CV256CW6LAST0. */ +#define ATON_DECUN_BFMT_CV256CW6LAST0 (0x5ffUL) + +/** BFORMAT values: CV256CW7LAST0. */ +#define ATON_DECUN_BFMT_CV256CW7LAST0 (0x6ffUL) + +/** BFORMAT values: CV256CW8LAST0. */ +#define ATON_DECUN_BFMT_CV256CW8LAST0 (0x7ffUL) + +/** BFORMAT values: CV16CW2LAST1. */ +#define ATON_DECUN_BFMT_CV16CW2LAST1 (0x110fUL) + +/** BFORMAT values: CV16CW3LAST1. */ +#define ATON_DECUN_BFMT_CV16CW3LAST1 (0x120fUL) + +/** BFORMAT values: CV16CW3LAST2. */ +#define ATON_DECUN_BFMT_CV16CW3LAST2 (0x220fUL) + +/** BFORMAT values: CV16CW4LAST1. */ +#define ATON_DECUN_BFMT_CV16CW4LAST1 (0x130fUL) + +/** BFORMAT values: CV16CW4LAST2. */ +#define ATON_DECUN_BFMT_CV16CW4LAST2 (0x230fUL) + +/** BFORMAT values: CV16CW4LAST3. */ +#define ATON_DECUN_BFMT_CV16CW4LAST3 (0x330fUL) + +/** BFORMAT values: CV16CW5LAST1. */ +#define ATON_DECUN_BFMT_CV16CW5LAST1 (0x140fUL) + +/** BFORMAT values: CV16CW5LAST2. */ +#define ATON_DECUN_BFMT_CV16CW5LAST2 (0x240fUL) + +/** BFORMAT values: CV16CW5LAST3. */ +#define ATON_DECUN_BFMT_CV16CW5LAST3 (0x340fUL) + +/** BFORMAT values: CV16CW5LAST4. */ +#define ATON_DECUN_BFMT_CV16CW5LAST4 (0x440fUL) + +/** BFORMAT values: CV16CW6LAST1. */ +#define ATON_DECUN_BFMT_CV16CW6LAST1 (0x150fUL) + +/** BFORMAT values: CV16CW6LAST2. */ +#define ATON_DECUN_BFMT_CV16CW6LAST2 (0x250fUL) + +/** BFORMAT values: CV16CW6LAST3. */ +#define ATON_DECUN_BFMT_CV16CW6LAST3 (0x350fUL) + +/** BFORMAT values: CV16CW6LAST4. */ +#define ATON_DECUN_BFMT_CV16CW6LAST4 (0x450fUL) + +/** BFORMAT values: CV16CW6LAST5. */ +#define ATON_DECUN_BFMT_CV16CW6LAST5 (0x550fUL) + +/** BFORMAT values: CV16CW7LAST1. */ +#define ATON_DECUN_BFMT_CV16CW7LAST1 (0x160fUL) + +/** BFORMAT values: CV16CW7LAST2. */ +#define ATON_DECUN_BFMT_CV16CW7LAST2 (0x260fUL) + +/** BFORMAT values: CV16CW7LAST3. */ +#define ATON_DECUN_BFMT_CV16CW7LAST3 (0x360fUL) + +/** BFORMAT values: CV16CW7LAST4. */ +#define ATON_DECUN_BFMT_CV16CW7LAST4 (0x460fUL) + +/** BFORMAT values: CV16CW7LAST5. */ +#define ATON_DECUN_BFMT_CV16CW7LAST5 (0x560fUL) + +/** BFORMAT values: CV16CW7LAST6. */ +#define ATON_DECUN_BFMT_CV16CW7LAST6 (0x660fUL) + +/** BFORMAT values: CV16CW8LAST1. */ +#define ATON_DECUN_BFMT_CV16CW8LAST1 (0x170fUL) + +/** BFORMAT values: CV16CW8LAST2. */ +#define ATON_DECUN_BFMT_CV16CW8LAST2 (0x270fUL) + +/** BFORMAT values: CV16CW8LAST3. */ +#define ATON_DECUN_BFMT_CV16CW8LAST3 (0x370fUL) + +/** BFORMAT values: CV16CW8LAST4. */ +#define ATON_DECUN_BFMT_CV16CW8LAST4 (0x470fUL) + +/** BFORMAT values: CV16CW8LAST5. */ +#define ATON_DECUN_BFMT_CV16CW8LAST5 (0x570fUL) + +/** BFORMAT values: CV16CW8LAST6. */ +#define ATON_DECUN_BFMT_CV16CW8LAST6 (0x670fUL) + +/** BFORMAT values: CV16CW8LAST7. */ +#define ATON_DECUN_BFMT_CV16CW8LAST7 (0x770fUL) + +/** BFORMAT values: CV32CW2LAST1. */ +#define ATON_DECUN_BFMT_CV32CW2LAST1 (0x111fUL) + +/** BFORMAT values: CV32CW3LAST1. */ +#define ATON_DECUN_BFMT_CV32CW3LAST1 (0x121fUL) + +/** BFORMAT values: CV32CW3LAST2. */ +#define ATON_DECUN_BFMT_CV32CW3LAST2 (0x221fUL) + +/** BFORMAT values: CV32CW4LAST1. */ +#define ATON_DECUN_BFMT_CV32CW4LAST1 (0x131fUL) + +/** BFORMAT values: CV32CW4LAST2. */ +#define ATON_DECUN_BFMT_CV32CW4LAST2 (0x231fUL) + +/** BFORMAT values: CV32CW4LAST3. */ +#define ATON_DECUN_BFMT_CV32CW4LAST3 (0x331fUL) + +/** BFORMAT values: CV32CW5LAST1. */ +#define ATON_DECUN_BFMT_CV32CW5LAST1 (0x141fUL) + +/** BFORMAT values: CV32CW5LAST2. */ +#define ATON_DECUN_BFMT_CV32CW5LAST2 (0x241fUL) + +/** BFORMAT values: CV32CW5LAST3. */ +#define ATON_DECUN_BFMT_CV32CW5LAST3 (0x341fUL) + +/** BFORMAT values: CV32CW5LAST4. */ +#define ATON_DECUN_BFMT_CV32CW5LAST4 (0x441fUL) + +/** BFORMAT values: CV32CW6LAST1. */ +#define ATON_DECUN_BFMT_CV32CW6LAST1 (0x151fUL) + +/** BFORMAT values: CV32CW6LAST2. */ +#define ATON_DECUN_BFMT_CV32CW6LAST2 (0x251fUL) + +/** BFORMAT values: CV32CW6LAST3. */ +#define ATON_DECUN_BFMT_CV32CW6LAST3 (0x351fUL) + +/** BFORMAT values: CV32CW6LAST4. */ +#define ATON_DECUN_BFMT_CV32CW6LAST4 (0x451fUL) + +/** BFORMAT values: CV32CW6LAST5. */ +#define ATON_DECUN_BFMT_CV32CW6LAST5 (0x551fUL) + +/** BFORMAT values: CV32CW7LAST1. */ +#define ATON_DECUN_BFMT_CV32CW7LAST1 (0x161fUL) + +/** BFORMAT values: CV32CW7LAST2. */ +#define ATON_DECUN_BFMT_CV32CW7LAST2 (0x261fUL) + +/** BFORMAT values: CV32CW7LAST3. */ +#define ATON_DECUN_BFMT_CV32CW7LAST3 (0x361fUL) + +/** BFORMAT values: CV32CW7LAST4. */ +#define ATON_DECUN_BFMT_CV32CW7LAST4 (0x461fUL) + +/** BFORMAT values: CV32CW7LAST5. */ +#define ATON_DECUN_BFMT_CV32CW7LAST5 (0x561fUL) + +/** BFORMAT values: CV32CW7LAST6. */ +#define ATON_DECUN_BFMT_CV32CW7LAST6 (0x661fUL) + +/** BFORMAT values: CV32CW8LAST1. */ +#define ATON_DECUN_BFMT_CV32CW8LAST1 (0x171fUL) + +/** BFORMAT values: CV32CW8LAST2. */ +#define ATON_DECUN_BFMT_CV32CW8LAST2 (0x271fUL) + +/** BFORMAT values: CV32CW8LAST3. */ +#define ATON_DECUN_BFMT_CV32CW8LAST3 (0x371fUL) + +/** BFORMAT values: CV32CW8LAST4. */ +#define ATON_DECUN_BFMT_CV32CW8LAST4 (0x471fUL) + +/** BFORMAT values: CV32CW8LAST5. */ +#define ATON_DECUN_BFMT_CV32CW8LAST5 (0x571fUL) + +/** BFORMAT values: CV32CW8LAST6. */ +#define ATON_DECUN_BFMT_CV32CW8LAST6 (0x671fUL) + +/** BFORMAT values: CV32CW8LAST7. */ +#define ATON_DECUN_BFMT_CV32CW8LAST7 (0x771fUL) + +/** BFORMAT values: CV64CW2LAST1. */ +#define ATON_DECUN_BFMT_CV64CW2LAST1 (0x113fUL) + +/** BFORMAT values: CV64CW3LAST1. */ +#define ATON_DECUN_BFMT_CV64CW3LAST1 (0x123fUL) + +/** BFORMAT values: CV64CW3LAST2. */ +#define ATON_DECUN_BFMT_CV64CW3LAST2 (0x223fUL) + +/** BFORMAT values: CV64CW4LAST1. */ +#define ATON_DECUN_BFMT_CV64CW4LAST1 (0x133fUL) + +/** BFORMAT values: CV64CW4LAST2. */ +#define ATON_DECUN_BFMT_CV64CW4LAST2 (0x233fUL) + +/** BFORMAT values: CV64CW4LAST3. */ +#define ATON_DECUN_BFMT_CV64CW4LAST3 (0x333fUL) + +/** BFORMAT values: CV64CW5LAST1. */ +#define ATON_DECUN_BFMT_CV64CW5LAST1 (0x143fUL) + +/** BFORMAT values: CV64CW5LAST2. */ +#define ATON_DECUN_BFMT_CV64CW5LAST2 (0x243fUL) + +/** BFORMAT values: CV64CW5LAST3. */ +#define ATON_DECUN_BFMT_CV64CW5LAST3 (0x343fUL) + +/** BFORMAT values: CV64CW5LAST4. */ +#define ATON_DECUN_BFMT_CV64CW5LAST4 (0x443fUL) + +/** BFORMAT values: CV64CW6LAST1. */ +#define ATON_DECUN_BFMT_CV64CW6LAST1 (0x153fUL) + +/** BFORMAT values: CV64CW6LAST2. */ +#define ATON_DECUN_BFMT_CV64CW6LAST2 (0x253fUL) + +/** BFORMAT values: CV64CW6LAST3. */ +#define ATON_DECUN_BFMT_CV64CW6LAST3 (0x353fUL) + +/** BFORMAT values: CV64CW6LAST4. */ +#define ATON_DECUN_BFMT_CV64CW6LAST4 (0x453fUL) + +/** BFORMAT values: CV64CW6LAST5. */ +#define ATON_DECUN_BFMT_CV64CW6LAST5 (0x553fUL) + +/** BFORMAT values: CV64CW7LAST1. */ +#define ATON_DECUN_BFMT_CV64CW7LAST1 (0x163fUL) + +/** BFORMAT values: CV64CW7LAST2. */ +#define ATON_DECUN_BFMT_CV64CW7LAST2 (0x263fUL) + +/** BFORMAT values: CV64CW7LAST3. */ +#define ATON_DECUN_BFMT_CV64CW7LAST3 (0x363fUL) + +/** BFORMAT values: CV64CW7LAST4. */ +#define ATON_DECUN_BFMT_CV64CW7LAST4 (0x463fUL) + +/** BFORMAT values: CV64CW7LAST5. */ +#define ATON_DECUN_BFMT_CV64CW7LAST5 (0x563fUL) + +/** BFORMAT values: CV64CW7LAST6. */ +#define ATON_DECUN_BFMT_CV64CW7LAST6 (0x663fUL) + +/** BFORMAT values: CV64CW8LAST1. */ +#define ATON_DECUN_BFMT_CV64CW8LAST1 (0x173fUL) + +/** BFORMAT values: CV64CW8LAST2. */ +#define ATON_DECUN_BFMT_CV64CW8LAST2 (0x273fUL) + +/** BFORMAT values: CV64CW8LAST3. */ +#define ATON_DECUN_BFMT_CV64CW8LAST3 (0x373fUL) + +/** BFORMAT values: CV64CW8LAST4. */ +#define ATON_DECUN_BFMT_CV64CW8LAST4 (0x473fUL) + +/** BFORMAT values: CV64CW8LAST5. */ +#define ATON_DECUN_BFMT_CV64CW8LAST5 (0x573fUL) + +/** BFORMAT values: CV64CW8LAST6. */ +#define ATON_DECUN_BFMT_CV64CW8LAST6 (0x673fUL) + +/** BFORMAT values: CV64CW8LAST7. */ +#define ATON_DECUN_BFMT_CV64CW8LAST7 (0x773fUL) + +/** BFORMAT values: CV128CW2LAST1. */ +#define ATON_DECUN_BFMT_CV128CW2LAST1 (0x117fUL) + +/** BFORMAT values: CV128CW3LAST1. */ +#define ATON_DECUN_BFMT_CV128CW3LAST1 (0x127fUL) + +/** BFORMAT values: CV128CW3LAST2. */ +#define ATON_DECUN_BFMT_CV128CW3LAST2 (0x227fUL) + +/** BFORMAT values: CV128CW4LAST1. */ +#define ATON_DECUN_BFMT_CV128CW4LAST1 (0x137fUL) + +/** BFORMAT values: CV128CW4LAST2. */ +#define ATON_DECUN_BFMT_CV128CW4LAST2 (0x237fUL) + +/** BFORMAT values: CV128CW4LAST3. */ +#define ATON_DECUN_BFMT_CV128CW4LAST3 (0x337fUL) + +/** BFORMAT values: CV128CW5LAST1. */ +#define ATON_DECUN_BFMT_CV128CW5LAST1 (0x147fUL) + +/** BFORMAT values: CV128CW5LAST2. */ +#define ATON_DECUN_BFMT_CV128CW5LAST2 (0x247fUL) + +/** BFORMAT values: CV128CW5LAST3. */ +#define ATON_DECUN_BFMT_CV128CW5LAST3 (0x347fUL) + +/** BFORMAT values: CV128CW5LAST4. */ +#define ATON_DECUN_BFMT_CV128CW5LAST4 (0x447fUL) + +/** BFORMAT values: CV128CW6LAST1. */ +#define ATON_DECUN_BFMT_CV128CW6LAST1 (0x157fUL) + +/** BFORMAT values: CV128CW6LAST2. */ +#define ATON_DECUN_BFMT_CV128CW6LAST2 (0x257fUL) + +/** BFORMAT values: CV128CW6LAST3. */ +#define ATON_DECUN_BFMT_CV128CW6LAST3 (0x357fUL) + +/** BFORMAT values: CV128CW6LAST4. */ +#define ATON_DECUN_BFMT_CV128CW6LAST4 (0x457fUL) + +/** BFORMAT values: CV128CW6LAST5. */ +#define ATON_DECUN_BFMT_CV128CW6LAST5 (0x557fUL) + +/** BFORMAT values: CV128CW7LAST1. */ +#define ATON_DECUN_BFMT_CV128CW7LAST1 (0x167fUL) + +/** BFORMAT values: CV128CW7LAST2. */ +#define ATON_DECUN_BFMT_CV128CW7LAST2 (0x267fUL) + +/** BFORMAT values: CV128CW7LAST3. */ +#define ATON_DECUN_BFMT_CV128CW7LAST3 (0x367fUL) + +/** BFORMAT values: CV128CW7LAST4. */ +#define ATON_DECUN_BFMT_CV128CW7LAST4 (0x467fUL) + +/** BFORMAT values: CV128CW7LAST5. */ +#define ATON_DECUN_BFMT_CV128CW7LAST5 (0x567fUL) + +/** BFORMAT values: CV128CW7LAST6. */ +#define ATON_DECUN_BFMT_CV128CW7LAST6 (0x667fUL) + +/** BFORMAT values: CV128CW8LAST1. */ +#define ATON_DECUN_BFMT_CV128CW8LAST1 (0x177fUL) + +/** BFORMAT values: CV128CW8LAST2. */ +#define ATON_DECUN_BFMT_CV128CW8LAST2 (0x277fUL) + +/** BFORMAT values: CV128CW8LAST3. */ +#define ATON_DECUN_BFMT_CV128CW8LAST3 (0x377fUL) + +/** BFORMAT values: CV128CW8LAST4. */ +#define ATON_DECUN_BFMT_CV128CW8LAST4 (0x477fUL) + +/** BFORMAT values: CV128CW8LAST5. */ +#define ATON_DECUN_BFMT_CV128CW8LAST5 (0x577fUL) + +/** BFORMAT values: CV128CW8LAST6. */ +#define ATON_DECUN_BFMT_CV128CW8LAST6 (0x677fUL) + +/** BFORMAT values: CV128CW8LAST7. */ +#define ATON_DECUN_BFMT_CV128CW8LAST7 (0x777fUL) + +/** BFORMAT values: CV256CW2LAST1. */ +#define ATON_DECUN_BFMT_CV256CW2LAST1 (0x11ffUL) + +/** BFORMAT values: CV256CW3LAST1. */ +#define ATON_DECUN_BFMT_CV256CW3LAST1 (0x12ffUL) + +/** BFORMAT values: CV256CW3LAST2. */ +#define ATON_DECUN_BFMT_CV256CW3LAST2 (0x22ffUL) + +/** BFORMAT values: CV256CW4LAST1. */ +#define ATON_DECUN_BFMT_CV256CW4LAST1 (0x13ffUL) + +/** BFORMAT values: CV256CW4LAST2. */ +#define ATON_DECUN_BFMT_CV256CW4LAST2 (0x23ffUL) + +/** BFORMAT values: CV256CW4LAST3. */ +#define ATON_DECUN_BFMT_CV256CW4LAST3 (0x33ffUL) + +/** BFORMAT values: CV256CW5LAST1. */ +#define ATON_DECUN_BFMT_CV256CW5LAST1 (0x14ffUL) + +/** BFORMAT values: CV256CW5LAST2. */ +#define ATON_DECUN_BFMT_CV256CW5LAST2 (0x24ffUL) + +/** BFORMAT values: CV256CW5LAST3. */ +#define ATON_DECUN_BFMT_CV256CW5LAST3 (0x34ffUL) + +/** BFORMAT values: CV256CW5LAST4. */ +#define ATON_DECUN_BFMT_CV256CW5LAST4 (0x44ffUL) + +/** BFORMAT values: CV256CW6LAST1. */ +#define ATON_DECUN_BFMT_CV256CW6LAST1 (0x15ffUL) + +/** BFORMAT values: CV256CW6LAST2. */ +#define ATON_DECUN_BFMT_CV256CW6LAST2 (0x25ffUL) + +/** BFORMAT values: CV256CW6LAST3. */ +#define ATON_DECUN_BFMT_CV256CW6LAST3 (0x35ffUL) + +/** BFORMAT values: CV256CW6LAST4. */ +#define ATON_DECUN_BFMT_CV256CW6LAST4 (0x45ffUL) + +/** BFORMAT values: CV256CW6LAST5. */ +#define ATON_DECUN_BFMT_CV256CW6LAST5 (0x55ffUL) + +/** BFORMAT values: CV256CW7LAST1. */ +#define ATON_DECUN_BFMT_CV256CW7LAST1 (0x16ffUL) + +/** BFORMAT values: CV256CW7LAST2. */ +#define ATON_DECUN_BFMT_CV256CW7LAST2 (0x26ffUL) + +/** BFORMAT values: CV256CW7LAST3. */ +#define ATON_DECUN_BFMT_CV256CW7LAST3 (0x36ffUL) + +/** BFORMAT values: CV256CW7LAST4. */ +#define ATON_DECUN_BFMT_CV256CW7LAST4 (0x46ffUL) + +/** BFORMAT values: CV256CW7LAST5. */ +#define ATON_DECUN_BFMT_CV256CW7LAST5 (0x56ffUL) + +/** BFORMAT values: CV256CW7LAST6. */ +#define ATON_DECUN_BFMT_CV256CW7LAST6 (0x66ffUL) + +/** BFORMAT values: CV256CW8LAST1. */ +#define ATON_DECUN_BFMT_CV256CW8LAST1 (0x17ffUL) + +/** BFORMAT values: CV256CW8LAST2. */ +#define ATON_DECUN_BFMT_CV256CW8LAST2 (0x27ffUL) + +/** BFORMAT values: CV256CW8LAST3. */ +#define ATON_DECUN_BFMT_CV256CW8LAST3 (0x37ffUL) + +/** BFORMAT values: CV256CW8LAST4. */ +#define ATON_DECUN_BFMT_CV256CW8LAST4 (0x47ffUL) + +/** BFORMAT values: CV256CW8LAST5. */ +#define ATON_DECUN_BFMT_CV256CW8LAST5 (0x57ffUL) + +/** BFORMAT values: CV256CW8LAST6. */ +#define ATON_DECUN_BFMT_CV256CW8LAST6 (0x67ffUL) + +/** BFORMAT values: CV256CW8LAST7. */ +#define ATON_DECUN_BFMT_CV256CW8LAST7 (0x77ffUL) + + +/** Get the name of one of the values of the DECUN_BFMT set of enumerated values. */ +#define ATON_DECUN_BFMT_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "CV1CW1LAST0" : \ + (((VALUE) == 256UL) ? "CV1CW2LAST0" : \ + (((VALUE) == 512UL) ? "CV1CW3LAST0" : \ + (((VALUE) == 768UL) ? "CV1CW4LAST0" : \ + (((VALUE) == 1024UL) ? "CV1CW5LAST0" : \ + (((VALUE) == 1280UL) ? "CV1CW6LAST0" : \ + (((VALUE) == 1536UL) ? "CV1CW7LAST0" : \ + (((VALUE) == 1792UL) ? "CV1CW8LAST0" : \ + (((VALUE) == 4352UL) ? "CV1CW2LAST1" : \ + (((VALUE) == 4608UL) ? "CV1CW3LAST1" : \ + (((VALUE) == 4864UL) ? "CV1CW4LAST1" : \ + (((VALUE) == 5120UL) ? "CV1CW5LAST1" : \ + (((VALUE) == 5376UL) ? "CV1CW6LAST1" : \ + (((VALUE) == 5632UL) ? "CV1CW7LAST1" : \ + (((VALUE) == 5888UL) ? "CV1CW8LAST1" : \ + (((VALUE) == 8704UL) ? "CV1CW3LAST2" : \ + (((VALUE) == 8960UL) ? "CV1CW4LAST2" : \ + (((VALUE) == 9216UL) ? "CV1CW5LAST2" : \ + (((VALUE) == 9472UL) ? "CV1CW6LAST2" : \ + (((VALUE) == 9728UL) ? "CV1CW7LAST2" : \ + (((VALUE) == 9984UL) ? "CV1CW8LAST2" : \ + (((VALUE) == 13056UL) ? "CV1CW4LAST3" : \ + (((VALUE) == 13312UL) ? "CV1CW5LAST3" : \ + (((VALUE) == 13568UL) ? "CV1CW6LAST3" : \ + (((VALUE) == 13824UL) ? "CV1CW7LAST3" : \ + (((VALUE) == 14080UL) ? "CV1CW8LAST3" : \ + (((VALUE) == 17408UL) ? "CV1CW5LAST4" : \ + (((VALUE) == 17664UL) ? "CV1CW6LAST4" : \ + (((VALUE) == 17920UL) ? "CV1CW7LAST4" : \ + (((VALUE) == 18176UL) ? "CV1CW8LAST4" : \ + (((VALUE) == 21760UL) ? "CV1CW6LAST5" : \ + (((VALUE) == 22016UL) ? "CV1CW7LAST5" : \ + (((VALUE) == 22272UL) ? "CV1CW8LAST5" : \ + (((VALUE) == 26112UL) ? "CV1CW7LAST6" : \ + (((VALUE) == 26368UL) ? "CV1CW8LAST6" : \ + (((VALUE) == 30464UL) ? "CV1CW8LAST7" : \ + (((VALUE) == 1UL) ? "CV2CW1LAST0" : \ + (((VALUE) == 257UL) ? "CV2CW2LAST0" : \ + (((VALUE) == 513UL) ? "CV2CW3LAST0" : \ + (((VALUE) == 769UL) ? "CV2CW4LAST0" : \ + (((VALUE) == 1025UL) ? "CV2CW5LAST0" : \ + (((VALUE) == 1281UL) ? "CV2CW6LAST0" : \ + (((VALUE) == 1537UL) ? "CV2CW7LAST0" : \ + (((VALUE) == 1793UL) ? "CV2CW8LAST0" : \ + (((VALUE) == 4353UL) ? "CV2CW2LAST1" : \ + (((VALUE) == 4609UL) ? "CV2CW3LAST1" : \ + (((VALUE) == 4865UL) ? "CV2CW4LAST1" : \ + (((VALUE) == 5121UL) ? "CV2CW5LAST1" : \ + (((VALUE) == 5377UL) ? "CV2CW6LAST1" : \ + (((VALUE) == 5633UL) ? "CV2CW7LAST1" : \ + (((VALUE) == 5889UL) ? "CV2CW8LAST1" : \ + (((VALUE) == 8705UL) ? "CV2CW3LAST2" : \ + (((VALUE) == 8961UL) ? "CV2CW4LAST2" : \ + (((VALUE) == 9217UL) ? "CV2CW5LAST2" : \ + (((VALUE) == 9473UL) ? "CV2CW6LAST2" : \ + (((VALUE) == 9729UL) ? "CV2CW7LAST2" : \ + (((VALUE) == 9985UL) ? "CV2CW8LAST2" : \ + (((VALUE) == 13057UL) ? "CV2CW4LAST3" : \ + (((VALUE) == 13313UL) ? "CV2CW5LAST3" : \ + (((VALUE) == 13569UL) ? "CV2CW6LAST3" : \ + (((VALUE) == 13825UL) ? "CV2CW7LAST3" : \ + (((VALUE) == 14081UL) ? "CV2CW8LAST3" : \ + (((VALUE) == 17409UL) ? "CV2CW5LAST4" : \ + (((VALUE) == 17665UL) ? "CV2CW6LAST4" : \ + (((VALUE) == 17921UL) ? "CV2CW7LAST4" : \ + (((VALUE) == 18177UL) ? "CV2CW8LAST4" : \ + (((VALUE) == 21761UL) ? "CV2CW6LAST5" : \ + (((VALUE) == 22017UL) ? "CV2CW7LAST5" : \ + (((VALUE) == 22273UL) ? "CV2CW8LAST5" : \ + (((VALUE) == 26113UL) ? "CV2CW7LAST6" : \ + (((VALUE) == 26369UL) ? "CV2CW8LAST6" : \ + (((VALUE) == 30465UL) ? "CV2CW8LAST7" : \ + (((VALUE) == 3UL) ? "CV4CW1LAST0" : \ + (((VALUE) == 259UL) ? "CV4CW2LAST0" : \ + (((VALUE) == 515UL) ? "CV4CW3LAST0" : \ + (((VALUE) == 771UL) ? "CV4CW4LAST0" : \ + (((VALUE) == 1027UL) ? "CV4CW5LAST0" : \ + (((VALUE) == 1283UL) ? "CV4CW6LAST0" : \ + (((VALUE) == 1539UL) ? "CV4CW7LAST0" : \ + (((VALUE) == 1795UL) ? "CV4CW8LAST0" : \ + (((VALUE) == 4355UL) ? "CV4CW2LAST1" : \ + (((VALUE) == 4611UL) ? "CV4CW3LAST1" : \ + (((VALUE) == 4867UL) ? "CV4CW4LAST1" : \ + (((VALUE) == 5123UL) ? "CV4CW5LAST1" : \ + (((VALUE) == 5379UL) ? "CV4CW6LAST1" : \ + (((VALUE) == 5635UL) ? "CV4CW7LAST1" : \ + (((VALUE) == 5891UL) ? "CV4CW8LAST1" : \ + (((VALUE) == 8707UL) ? "CV4CW3LAST2" : \ + (((VALUE) == 8963UL) ? "CV4CW4LAST2" : \ + (((VALUE) == 9219UL) ? "CV4CW5LAST2" : \ + (((VALUE) == 9475UL) ? "CV4CW6LAST2" : \ + (((VALUE) == 9731UL) ? "CV4CW7LAST2" : \ + (((VALUE) == 9987UL) ? "CV4CW8LAST2" : \ + (((VALUE) == 13059UL) ? "CV4CW4LAST3" : \ + (((VALUE) == 13315UL) ? "CV4CW5LAST3" : \ + (((VALUE) == 13571UL) ? "CV4CW6LAST3" : \ + (((VALUE) == 13827UL) ? "CV4CW7LAST3" : \ + (((VALUE) == 14083UL) ? "CV4CW8LAST3" : \ + (((VALUE) == 17411UL) ? "CV4CW5LAST4" : \ + (((VALUE) == 17667UL) ? "CV4CW6LAST4" : \ + (((VALUE) == 17923UL) ? "CV4CW7LAST4" : \ + (((VALUE) == 18179UL) ? "CV4CW8LAST4" : \ + (((VALUE) == 21763UL) ? "CV4CW6LAST5" : \ + (((VALUE) == 22019UL) ? "CV4CW7LAST5" : \ + (((VALUE) == 22275UL) ? "CV4CW8LAST5" : \ + (((VALUE) == 26115UL) ? "CV4CW7LAST6" : \ + (((VALUE) == 26371UL) ? "CV4CW8LAST6" : \ + (((VALUE) == 30467UL) ? "CV4CW8LAST7" : \ + (((VALUE) == 7UL) ? "CV8CW1LAST0" : \ + (((VALUE) == 263UL) ? "CV8CW2LAST0" : \ + (((VALUE) == 519UL) ? "CV8CW3LAST0" : \ + (((VALUE) == 775UL) ? "CV8CW4LAST0" : \ + (((VALUE) == 1031UL) ? "CV8CW5LAST0" : \ + (((VALUE) == 1287UL) ? "CV8CW6LAST0" : \ + (((VALUE) == 1543UL) ? "CV8CW7LAST0" : \ + (((VALUE) == 1799UL) ? "CV8CW8LAST0" : \ + (((VALUE) == 4359UL) ? "CV8CW2LAST1" : \ + (((VALUE) == 4615UL) ? "CV8CW3LAST1" : \ + (((VALUE) == 4871UL) ? "CV8CW4LAST1" : \ + (((VALUE) == 5127UL) ? "CV8CW5LAST1" : \ + (((VALUE) == 5383UL) ? "CV8CW6LAST1" : \ + (((VALUE) == 5639UL) ? "CV8CW7LAST1" : \ + (((VALUE) == 5895UL) ? "CV8CW8LAST1" : \ + (((VALUE) == 8711UL) ? "CV8CW3LAST2" : \ + (((VALUE) == 8967UL) ? "CV8CW4LAST2" : \ + (((VALUE) == 9223UL) ? "CV8CW5LAST2" : \ + (((VALUE) == 9479UL) ? "CV8CW6LAST2" : \ + (((VALUE) == 9735UL) ? "CV8CW7LAST2" : \ + (((VALUE) == 9991UL) ? "CV8CW8LAST2" : \ + (((VALUE) == 13063UL) ? "CV8CW4LAST3" : \ + (((VALUE) == 13319UL) ? "CV8CW5LAST3" : \ + (((VALUE) == 13575UL) ? "CV8CW6LAST3" : \ + (((VALUE) == 13831UL) ? "CV8CW7LAST3" : \ + (((VALUE) == 14087UL) ? "CV8CW8LAST3" : \ + (((VALUE) == 17415UL) ? "CV8CW5LAST4" : \ + (((VALUE) == 17671UL) ? "CV8CW6LAST4" : \ + (((VALUE) == 17927UL) ? "CV8CW7LAST4" : \ + (((VALUE) == 18183UL) ? "CV8CW8LAST4" : \ + (((VALUE) == 21767UL) ? "CV8CW6LAST5" : \ + (((VALUE) == 22023UL) ? "CV8CW7LAST5" : \ + (((VALUE) == 22279UL) ? "CV8CW8LAST5" : \ + (((VALUE) == 26119UL) ? "CV8CW7LAST6" : \ + (((VALUE) == 26375UL) ? "CV8CW8LAST6" : \ + (((VALUE) == 30471UL) ? "CV8CW8LAST7" : \ + (((VALUE) == 15UL) ? "CV16CW1LAST0" : \ + (((VALUE) == 271UL) ? "CV16CW2LAST0" : \ + (((VALUE) == 527UL) ? "CV16CW3LAST0" : \ + (((VALUE) == 783UL) ? "CV16CW4LAST0" : \ + (((VALUE) == 1039UL) ? "CV16CW5LAST0" : \ + (((VALUE) == 1295UL) ? "CV16CW6LAST0" : \ + (((VALUE) == 1551UL) ? "CV16CW7LAST0" : \ + (((VALUE) == 1807UL) ? "CV16CW8LAST0" : \ + (((VALUE) == 31UL) ? "CV32CW1LAST0" : \ + (((VALUE) == 287UL) ? "CV32CW2LAST0" : \ + (((VALUE) == 543UL) ? "CV32CW3LAST0" : \ + (((VALUE) == 799UL) ? "CV32CW4LAST0" : \ + (((VALUE) == 1055UL) ? "CV32CW5LAST0" : \ + (((VALUE) == 1311UL) ? "CV32CW6LAST0" : \ + (((VALUE) == 1567UL) ? "CV32CW7LAST0" : \ + (((VALUE) == 1823UL) ? "CV32CW8LAST0" : \ + (((VALUE) == 63UL) ? "CV64CW1LAST0" : \ + (((VALUE) == 319UL) ? "CV64CW2LAST0" : \ + (((VALUE) == 575UL) ? "CV64CW3LAST0" : \ + (((VALUE) == 831UL) ? "CV64CW4LAST0" : \ + (((VALUE) == 1087UL) ? "CV64CW5LAST0" : \ + (((VALUE) == 1343UL) ? "CV64CW6LAST0" : \ + (((VALUE) == 1599UL) ? "CV64CW7LAST0" : \ + (((VALUE) == 1855UL) ? "CV64CW8LAST0" : \ + (((VALUE) == 127UL) ? "CV128CW1LAST0" : \ + (((VALUE) == 383UL) ? "CV128CW2LAST0" : \ + (((VALUE) == 639UL) ? "CV128CW3LAST0" : \ + (((VALUE) == 895UL) ? "CV128CW4LAST0" : \ + (((VALUE) == 1151UL) ? "CV128CW5LAST0" : \ + (((VALUE) == 1407UL) ? "CV128CW6LAST0" : \ + (((VALUE) == 1663UL) ? "CV128CW7LAST0" : \ + (((VALUE) == 1919UL) ? "CV128CW8LAST0" : \ + (((VALUE) == 255UL) ? "CV256CW1LAST0" : \ + (((VALUE) == 511UL) ? "CV256CW2LAST0" : \ + (((VALUE) == 767UL) ? "CV256CW3LAST0" : \ + (((VALUE) == 1023UL) ? "CV256CW4LAST0" : \ + (((VALUE) == 1279UL) ? "CV256CW5LAST0" : \ + (((VALUE) == 1535UL) ? "CV256CW6LAST0" : \ + (((VALUE) == 1791UL) ? "CV256CW7LAST0" : \ + (((VALUE) == 2047UL) ? "CV256CW8LAST0" : \ + (((VALUE) == 4367UL) ? "CV16CW2LAST1" : \ + (((VALUE) == 4623UL) ? "CV16CW3LAST1" : \ + (((VALUE) == 8719UL) ? "CV16CW3LAST2" : \ + (((VALUE) == 4879UL) ? "CV16CW4LAST1" : \ + (((VALUE) == 8975UL) ? "CV16CW4LAST2" : \ + (((VALUE) == 13071UL) ? "CV16CW4LAST3" : \ + (((VALUE) == 5135UL) ? "CV16CW5LAST1" : \ + (((VALUE) == 9231UL) ? "CV16CW5LAST2" : \ + (((VALUE) == 13327UL) ? "CV16CW5LAST3" : \ + (((VALUE) == 17423UL) ? "CV16CW5LAST4" : \ + (((VALUE) == 5391UL) ? "CV16CW6LAST1" : \ + (((VALUE) == 9487UL) ? "CV16CW6LAST2" : \ + (((VALUE) == 13583UL) ? "CV16CW6LAST3" : \ + (((VALUE) == 17679UL) ? "CV16CW6LAST4" : \ + (((VALUE) == 21775UL) ? "CV16CW6LAST5" : \ + (((VALUE) == 5647UL) ? "CV16CW7LAST1" : \ + (((VALUE) == 9743UL) ? "CV16CW7LAST2" : \ + (((VALUE) == 13839UL) ? "CV16CW7LAST3" : \ + (((VALUE) == 17935UL) ? "CV16CW7LAST4" : \ + (((VALUE) == 22031UL) ? "CV16CW7LAST5" : \ + (((VALUE) == 26127UL) ? "CV16CW7LAST6" : \ + (((VALUE) == 5903UL) ? "CV16CW8LAST1" : \ + (((VALUE) == 9999UL) ? "CV16CW8LAST2" : \ + (((VALUE) == 14095UL) ? "CV16CW8LAST3" : \ + (((VALUE) == 18191UL) ? "CV16CW8LAST4" : \ + (((VALUE) == 22287UL) ? "CV16CW8LAST5" : \ + (((VALUE) == 26383UL) ? "CV16CW8LAST6" : \ + (((VALUE) == 30479UL) ? "CV16CW8LAST7" : \ + (((VALUE) == 4383UL) ? "CV32CW2LAST1" : \ + (((VALUE) == 4639UL) ? "CV32CW3LAST1" : \ + (((VALUE) == 8735UL) ? "CV32CW3LAST2" : \ + (((VALUE) == 4895UL) ? "CV32CW4LAST1" : \ + (((VALUE) == 8991UL) ? "CV32CW4LAST2" : \ + (((VALUE) == 13087UL) ? "CV32CW4LAST3" : \ + (((VALUE) == 5151UL) ? "CV32CW5LAST1" : \ + (((VALUE) == 9247UL) ? "CV32CW5LAST2" : \ + (((VALUE) == 13343UL) ? "CV32CW5LAST3" : \ + (((VALUE) == 17439UL) ? "CV32CW5LAST4" : \ + (((VALUE) == 5407UL) ? "CV32CW6LAST1" : \ + (((VALUE) == 9503UL) ? "CV32CW6LAST2" : \ + (((VALUE) == 13599UL) ? "CV32CW6LAST3" : \ + (((VALUE) == 17695UL) ? "CV32CW6LAST4" : \ + (((VALUE) == 21791UL) ? "CV32CW6LAST5" : \ + (((VALUE) == 5663UL) ? "CV32CW7LAST1" : \ + (((VALUE) == 9759UL) ? "CV32CW7LAST2" : \ + (((VALUE) == 13855UL) ? "CV32CW7LAST3" : \ + (((VALUE) == 17951UL) ? "CV32CW7LAST4" : \ + (((VALUE) == 22047UL) ? "CV32CW7LAST5" : \ + (((VALUE) == 26143UL) ? "CV32CW7LAST6" : \ + (((VALUE) == 5919UL) ? "CV32CW8LAST1" : \ + (((VALUE) == 10015UL) ? "CV32CW8LAST2" : \ + (((VALUE) == 14111UL) ? "CV32CW8LAST3" : \ + (((VALUE) == 18207UL) ? "CV32CW8LAST4" : \ + (((VALUE) == 22303UL) ? "CV32CW8LAST5" : \ + (((VALUE) == 26399UL) ? "CV32CW8LAST6" : \ + (((VALUE) == 30495UL) ? "CV32CW8LAST7" : \ + (((VALUE) == 4415UL) ? "CV64CW2LAST1" : \ + (((VALUE) == 4671UL) ? "CV64CW3LAST1" : \ + (((VALUE) == 8767UL) ? "CV64CW3LAST2" : \ + (((VALUE) == 4927UL) ? "CV64CW4LAST1" : \ + (((VALUE) == 9023UL) ? "CV64CW4LAST2" : \ + (((VALUE) == 13119UL) ? "CV64CW4LAST3" : \ + (((VALUE) == 5183UL) ? "CV64CW5LAST1" : \ + (((VALUE) == 9279UL) ? "CV64CW5LAST2" : \ + (((VALUE) == 13375UL) ? "CV64CW5LAST3" : \ + (((VALUE) == 17471UL) ? "CV64CW5LAST4" : \ + (((VALUE) == 5439UL) ? "CV64CW6LAST1" : \ + (((VALUE) == 9535UL) ? "CV64CW6LAST2" : \ + (((VALUE) == 13631UL) ? "CV64CW6LAST3" : \ + (((VALUE) == 17727UL) ? "CV64CW6LAST4" : \ + (((VALUE) == 21823UL) ? "CV64CW6LAST5" : \ + (((VALUE) == 5695UL) ? "CV64CW7LAST1" : \ + (((VALUE) == 9791UL) ? "CV64CW7LAST2" : \ + (((VALUE) == 13887UL) ? "CV64CW7LAST3" : \ + (((VALUE) == 17983UL) ? "CV64CW7LAST4" : \ + (((VALUE) == 22079UL) ? "CV64CW7LAST5" : \ + (((VALUE) == 26175UL) ? "CV64CW7LAST6" : \ + (((VALUE) == 5951UL) ? "CV64CW8LAST1" : \ + (((VALUE) == 10047UL) ? "CV64CW8LAST2" : \ + (((VALUE) == 14143UL) ? "CV64CW8LAST3" : \ + (((VALUE) == 18239UL) ? "CV64CW8LAST4" : \ + (((VALUE) == 22335UL) ? "CV64CW8LAST5" : \ + (((VALUE) == 26431UL) ? "CV64CW8LAST6" : \ + (((VALUE) == 30527UL) ? "CV64CW8LAST7" : \ + (((VALUE) == 4479UL) ? "CV128CW2LAST1" : \ + (((VALUE) == 4735UL) ? "CV128CW3LAST1" : \ + (((VALUE) == 8831UL) ? "CV128CW3LAST2" : \ + (((VALUE) == 4991UL) ? "CV128CW4LAST1" : \ + (((VALUE) == 9087UL) ? "CV128CW4LAST2" : \ + (((VALUE) == 13183UL) ? "CV128CW4LAST3" : \ + (((VALUE) == 5247UL) ? "CV128CW5LAST1" : \ + (((VALUE) == 9343UL) ? "CV128CW5LAST2" : \ + (((VALUE) == 13439UL) ? "CV128CW5LAST3" : \ + (((VALUE) == 17535UL) ? "CV128CW5LAST4" : \ + (((VALUE) == 5503UL) ? "CV128CW6LAST1" : \ + (((VALUE) == 9599UL) ? "CV128CW6LAST2" : \ + (((VALUE) == 13695UL) ? "CV128CW6LAST3" : \ + (((VALUE) == 17791UL) ? "CV128CW6LAST4" : \ + (((VALUE) == 21887UL) ? "CV128CW6LAST5" : \ + (((VALUE) == 5759UL) ? "CV128CW7LAST1" : \ + (((VALUE) == 9855UL) ? "CV128CW7LAST2" : \ + (((VALUE) == 13951UL) ? "CV128CW7LAST3" : \ + (((VALUE) == 18047UL) ? "CV128CW7LAST4" : \ + (((VALUE) == 22143UL) ? "CV128CW7LAST5" : \ + (((VALUE) == 26239UL) ? "CV128CW7LAST6" : \ + (((VALUE) == 6015UL) ? "CV128CW8LAST1" : \ + (((VALUE) == 10111UL) ? "CV128CW8LAST2" : \ + (((VALUE) == 14207UL) ? "CV128CW8LAST3" : \ + (((VALUE) == 18303UL) ? "CV128CW8LAST4" : \ + (((VALUE) == 22399UL) ? "CV128CW8LAST5" : \ + (((VALUE) == 26495UL) ? "CV128CW8LAST6" : \ + (((VALUE) == 30591UL) ? "CV128CW8LAST7" : \ + (((VALUE) == 4607UL) ? "CV256CW2LAST1" : \ + (((VALUE) == 4863UL) ? "CV256CW3LAST1" : \ + (((VALUE) == 8959UL) ? "CV256CW3LAST2" : \ + (((VALUE) == 5119UL) ? "CV256CW4LAST1" : \ + (((VALUE) == 9215UL) ? "CV256CW4LAST2" : \ + (((VALUE) == 13311UL) ? "CV256CW4LAST3" : \ + (((VALUE) == 5375UL) ? "CV256CW5LAST1" : \ + (((VALUE) == 9471UL) ? "CV256CW5LAST2" : \ + (((VALUE) == 13567UL) ? "CV256CW5LAST3" : \ + (((VALUE) == 17663UL) ? "CV256CW5LAST4" : \ + (((VALUE) == 5631UL) ? "CV256CW6LAST1" : \ + (((VALUE) == 9727UL) ? "CV256CW6LAST2" : \ + (((VALUE) == 13823UL) ? "CV256CW6LAST3" : \ + (((VALUE) == 17919UL) ? "CV256CW6LAST4" : \ + (((VALUE) == 22015UL) ? "CV256CW6LAST5" : \ + (((VALUE) == 5887UL) ? "CV256CW7LAST1" : \ + (((VALUE) == 9983UL) ? "CV256CW7LAST2" : \ + (((VALUE) == 14079UL) ? "CV256CW7LAST3" : \ + (((VALUE) == 18175UL) ? "CV256CW7LAST4" : \ + (((VALUE) == 22271UL) ? "CV256CW7LAST5" : \ + (((VALUE) == 26367UL) ? "CV256CW7LAST6" : \ + (((VALUE) == 6143UL) ? "CV256CW8LAST1" : \ + (((VALUE) == 10239UL) ? "CV256CW8LAST2" : \ + (((VALUE) == 14335UL) ? "CV256CW8LAST3" : \ + (((VALUE) == 18431UL) ? "CV256CW8LAST4" : \ + (((VALUE) == 22527UL) ? "CV256CW8LAST5" : \ + (((VALUE) == 26623UL) ? "CV256CW8LAST6" : \ + (((VALUE) == 30719UL) ? "CV256CW8LAST7" : "")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) + + +/** + * Check if a value of the DECUN_BFMT set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the DECUN_BFMT set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_DECUN_BFMT_IsValid(uint32_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_DECUN_BFMT_CV1CW1LAST0: + case ATON_DECUN_BFMT_CV1CW2LAST0: + case ATON_DECUN_BFMT_CV1CW3LAST0: + case ATON_DECUN_BFMT_CV1CW4LAST0: + case ATON_DECUN_BFMT_CV1CW5LAST0: + case ATON_DECUN_BFMT_CV1CW6LAST0: + case ATON_DECUN_BFMT_CV1CW7LAST0: + case ATON_DECUN_BFMT_CV1CW8LAST0: + case ATON_DECUN_BFMT_CV1CW2LAST1: + case ATON_DECUN_BFMT_CV1CW3LAST1: + case ATON_DECUN_BFMT_CV1CW4LAST1: + case ATON_DECUN_BFMT_CV1CW5LAST1: + case ATON_DECUN_BFMT_CV1CW6LAST1: + case ATON_DECUN_BFMT_CV1CW7LAST1: + case ATON_DECUN_BFMT_CV1CW8LAST1: + case ATON_DECUN_BFMT_CV1CW3LAST2: + case ATON_DECUN_BFMT_CV1CW4LAST2: + case ATON_DECUN_BFMT_CV1CW5LAST2: + case ATON_DECUN_BFMT_CV1CW6LAST2: + case ATON_DECUN_BFMT_CV1CW7LAST2: + case ATON_DECUN_BFMT_CV1CW8LAST2: + case ATON_DECUN_BFMT_CV1CW4LAST3: + case ATON_DECUN_BFMT_CV1CW5LAST3: + case ATON_DECUN_BFMT_CV1CW6LAST3: + case ATON_DECUN_BFMT_CV1CW7LAST3: + case ATON_DECUN_BFMT_CV1CW8LAST3: + case ATON_DECUN_BFMT_CV1CW5LAST4: + case ATON_DECUN_BFMT_CV1CW6LAST4: + case ATON_DECUN_BFMT_CV1CW7LAST4: + case ATON_DECUN_BFMT_CV1CW8LAST4: + case ATON_DECUN_BFMT_CV1CW6LAST5: + case ATON_DECUN_BFMT_CV1CW7LAST5: + case ATON_DECUN_BFMT_CV1CW8LAST5: + case ATON_DECUN_BFMT_CV1CW7LAST6: + case ATON_DECUN_BFMT_CV1CW8LAST6: + case ATON_DECUN_BFMT_CV1CW8LAST7: + case ATON_DECUN_BFMT_CV2CW1LAST0: + case ATON_DECUN_BFMT_CV2CW2LAST0: + case ATON_DECUN_BFMT_CV2CW3LAST0: + case ATON_DECUN_BFMT_CV2CW4LAST0: + case ATON_DECUN_BFMT_CV2CW5LAST0: + case ATON_DECUN_BFMT_CV2CW6LAST0: + case ATON_DECUN_BFMT_CV2CW7LAST0: + case ATON_DECUN_BFMT_CV2CW8LAST0: + case ATON_DECUN_BFMT_CV2CW2LAST1: + case ATON_DECUN_BFMT_CV2CW3LAST1: + case ATON_DECUN_BFMT_CV2CW4LAST1: + case ATON_DECUN_BFMT_CV2CW5LAST1: + case ATON_DECUN_BFMT_CV2CW6LAST1: + case ATON_DECUN_BFMT_CV2CW7LAST1: + case ATON_DECUN_BFMT_CV2CW8LAST1: + case ATON_DECUN_BFMT_CV2CW3LAST2: + case ATON_DECUN_BFMT_CV2CW4LAST2: + case ATON_DECUN_BFMT_CV2CW5LAST2: + case ATON_DECUN_BFMT_CV2CW6LAST2: + case ATON_DECUN_BFMT_CV2CW7LAST2: + case ATON_DECUN_BFMT_CV2CW8LAST2: + case ATON_DECUN_BFMT_CV2CW4LAST3: + case ATON_DECUN_BFMT_CV2CW5LAST3: + case ATON_DECUN_BFMT_CV2CW6LAST3: + case ATON_DECUN_BFMT_CV2CW7LAST3: + case ATON_DECUN_BFMT_CV2CW8LAST3: + case ATON_DECUN_BFMT_CV2CW5LAST4: + case ATON_DECUN_BFMT_CV2CW6LAST4: + case ATON_DECUN_BFMT_CV2CW7LAST4: + case ATON_DECUN_BFMT_CV2CW8LAST4: + case ATON_DECUN_BFMT_CV2CW6LAST5: + case ATON_DECUN_BFMT_CV2CW7LAST5: + case ATON_DECUN_BFMT_CV2CW8LAST5: + case ATON_DECUN_BFMT_CV2CW7LAST6: + case ATON_DECUN_BFMT_CV2CW8LAST6: + case ATON_DECUN_BFMT_CV2CW8LAST7: + case ATON_DECUN_BFMT_CV4CW1LAST0: + case ATON_DECUN_BFMT_CV4CW2LAST0: + case ATON_DECUN_BFMT_CV4CW3LAST0: + case ATON_DECUN_BFMT_CV4CW4LAST0: + case ATON_DECUN_BFMT_CV4CW5LAST0: + case ATON_DECUN_BFMT_CV4CW6LAST0: + case ATON_DECUN_BFMT_CV4CW7LAST0: + case ATON_DECUN_BFMT_CV4CW8LAST0: + case ATON_DECUN_BFMT_CV4CW2LAST1: + case ATON_DECUN_BFMT_CV4CW3LAST1: + case ATON_DECUN_BFMT_CV4CW4LAST1: + case ATON_DECUN_BFMT_CV4CW5LAST1: + case ATON_DECUN_BFMT_CV4CW6LAST1: + case ATON_DECUN_BFMT_CV4CW7LAST1: + case ATON_DECUN_BFMT_CV4CW8LAST1: + case ATON_DECUN_BFMT_CV4CW3LAST2: + case ATON_DECUN_BFMT_CV4CW4LAST2: + case ATON_DECUN_BFMT_CV4CW5LAST2: + case ATON_DECUN_BFMT_CV4CW6LAST2: + case ATON_DECUN_BFMT_CV4CW7LAST2: + case ATON_DECUN_BFMT_CV4CW8LAST2: + case ATON_DECUN_BFMT_CV4CW4LAST3: + case ATON_DECUN_BFMT_CV4CW5LAST3: + case ATON_DECUN_BFMT_CV4CW6LAST3: + case ATON_DECUN_BFMT_CV4CW7LAST3: + case ATON_DECUN_BFMT_CV4CW8LAST3: + case ATON_DECUN_BFMT_CV4CW5LAST4: + case ATON_DECUN_BFMT_CV4CW6LAST4: + case ATON_DECUN_BFMT_CV4CW7LAST4: + case ATON_DECUN_BFMT_CV4CW8LAST4: + case ATON_DECUN_BFMT_CV4CW6LAST5: + case ATON_DECUN_BFMT_CV4CW7LAST5: + case ATON_DECUN_BFMT_CV4CW8LAST5: + case ATON_DECUN_BFMT_CV4CW7LAST6: + case ATON_DECUN_BFMT_CV4CW8LAST6: + case ATON_DECUN_BFMT_CV4CW8LAST7: + case ATON_DECUN_BFMT_CV8CW1LAST0: + case ATON_DECUN_BFMT_CV8CW2LAST0: + case ATON_DECUN_BFMT_CV8CW3LAST0: + case ATON_DECUN_BFMT_CV8CW4LAST0: + case ATON_DECUN_BFMT_CV8CW5LAST0: + case ATON_DECUN_BFMT_CV8CW6LAST0: + case ATON_DECUN_BFMT_CV8CW7LAST0: + case ATON_DECUN_BFMT_CV8CW8LAST0: + case ATON_DECUN_BFMT_CV8CW2LAST1: + case ATON_DECUN_BFMT_CV8CW3LAST1: + case ATON_DECUN_BFMT_CV8CW4LAST1: + case ATON_DECUN_BFMT_CV8CW5LAST1: + case ATON_DECUN_BFMT_CV8CW6LAST1: + case ATON_DECUN_BFMT_CV8CW7LAST1: + case ATON_DECUN_BFMT_CV8CW8LAST1: + case ATON_DECUN_BFMT_CV8CW3LAST2: + case ATON_DECUN_BFMT_CV8CW4LAST2: + case ATON_DECUN_BFMT_CV8CW5LAST2: + case ATON_DECUN_BFMT_CV8CW6LAST2: + case ATON_DECUN_BFMT_CV8CW7LAST2: + case ATON_DECUN_BFMT_CV8CW8LAST2: + case ATON_DECUN_BFMT_CV8CW4LAST3: + case ATON_DECUN_BFMT_CV8CW5LAST3: + case ATON_DECUN_BFMT_CV8CW6LAST3: + case ATON_DECUN_BFMT_CV8CW7LAST3: + case ATON_DECUN_BFMT_CV8CW8LAST3: + case ATON_DECUN_BFMT_CV8CW5LAST4: + case ATON_DECUN_BFMT_CV8CW6LAST4: + case ATON_DECUN_BFMT_CV8CW7LAST4: + case ATON_DECUN_BFMT_CV8CW8LAST4: + case ATON_DECUN_BFMT_CV8CW6LAST5: + case ATON_DECUN_BFMT_CV8CW7LAST5: + case ATON_DECUN_BFMT_CV8CW8LAST5: + case ATON_DECUN_BFMT_CV8CW7LAST6: + case ATON_DECUN_BFMT_CV8CW8LAST6: + case ATON_DECUN_BFMT_CV8CW8LAST7: + case ATON_DECUN_BFMT_CV16CW1LAST0: + case ATON_DECUN_BFMT_CV16CW2LAST0: + case ATON_DECUN_BFMT_CV16CW3LAST0: + case ATON_DECUN_BFMT_CV16CW4LAST0: + case ATON_DECUN_BFMT_CV16CW5LAST0: + case ATON_DECUN_BFMT_CV16CW6LAST0: + case ATON_DECUN_BFMT_CV16CW7LAST0: + case ATON_DECUN_BFMT_CV16CW8LAST0: + case ATON_DECUN_BFMT_CV32CW1LAST0: + case ATON_DECUN_BFMT_CV32CW2LAST0: + case ATON_DECUN_BFMT_CV32CW3LAST0: + case ATON_DECUN_BFMT_CV32CW4LAST0: + case ATON_DECUN_BFMT_CV32CW5LAST0: + case ATON_DECUN_BFMT_CV32CW6LAST0: + case ATON_DECUN_BFMT_CV32CW7LAST0: + case ATON_DECUN_BFMT_CV32CW8LAST0: + case ATON_DECUN_BFMT_CV64CW1LAST0: + case ATON_DECUN_BFMT_CV64CW2LAST0: + case ATON_DECUN_BFMT_CV64CW3LAST0: + case ATON_DECUN_BFMT_CV64CW4LAST0: + case ATON_DECUN_BFMT_CV64CW5LAST0: + case ATON_DECUN_BFMT_CV64CW6LAST0: + case ATON_DECUN_BFMT_CV64CW7LAST0: + case ATON_DECUN_BFMT_CV64CW8LAST0: + case ATON_DECUN_BFMT_CV128CW1LAST0: + case ATON_DECUN_BFMT_CV128CW2LAST0: + case ATON_DECUN_BFMT_CV128CW3LAST0: + case ATON_DECUN_BFMT_CV128CW4LAST0: + case ATON_DECUN_BFMT_CV128CW5LAST0: + case ATON_DECUN_BFMT_CV128CW6LAST0: + case ATON_DECUN_BFMT_CV128CW7LAST0: + case ATON_DECUN_BFMT_CV128CW8LAST0: + case ATON_DECUN_BFMT_CV256CW1LAST0: + case ATON_DECUN_BFMT_CV256CW2LAST0: + case ATON_DECUN_BFMT_CV256CW3LAST0: + case ATON_DECUN_BFMT_CV256CW4LAST0: + case ATON_DECUN_BFMT_CV256CW5LAST0: + case ATON_DECUN_BFMT_CV256CW6LAST0: + case ATON_DECUN_BFMT_CV256CW7LAST0: + case ATON_DECUN_BFMT_CV256CW8LAST0: + case ATON_DECUN_BFMT_CV16CW2LAST1: + case ATON_DECUN_BFMT_CV16CW3LAST1: + case ATON_DECUN_BFMT_CV16CW3LAST2: + case ATON_DECUN_BFMT_CV16CW4LAST1: + case ATON_DECUN_BFMT_CV16CW4LAST2: + case ATON_DECUN_BFMT_CV16CW4LAST3: + case ATON_DECUN_BFMT_CV16CW5LAST1: + case ATON_DECUN_BFMT_CV16CW5LAST2: + case ATON_DECUN_BFMT_CV16CW5LAST3: + case ATON_DECUN_BFMT_CV16CW5LAST4: + case ATON_DECUN_BFMT_CV16CW6LAST1: + case ATON_DECUN_BFMT_CV16CW6LAST2: + case ATON_DECUN_BFMT_CV16CW6LAST3: + case ATON_DECUN_BFMT_CV16CW6LAST4: + case ATON_DECUN_BFMT_CV16CW6LAST5: + case ATON_DECUN_BFMT_CV16CW7LAST1: + case ATON_DECUN_BFMT_CV16CW7LAST2: + case ATON_DECUN_BFMT_CV16CW7LAST3: + case ATON_DECUN_BFMT_CV16CW7LAST4: + case ATON_DECUN_BFMT_CV16CW7LAST5: + case ATON_DECUN_BFMT_CV16CW7LAST6: + case ATON_DECUN_BFMT_CV16CW8LAST1: + case ATON_DECUN_BFMT_CV16CW8LAST2: + case ATON_DECUN_BFMT_CV16CW8LAST3: + case ATON_DECUN_BFMT_CV16CW8LAST4: + case ATON_DECUN_BFMT_CV16CW8LAST5: + case ATON_DECUN_BFMT_CV16CW8LAST6: + case ATON_DECUN_BFMT_CV16CW8LAST7: + case ATON_DECUN_BFMT_CV32CW2LAST1: + case ATON_DECUN_BFMT_CV32CW3LAST1: + case ATON_DECUN_BFMT_CV32CW3LAST2: + case ATON_DECUN_BFMT_CV32CW4LAST1: + case ATON_DECUN_BFMT_CV32CW4LAST2: + case ATON_DECUN_BFMT_CV32CW4LAST3: + case ATON_DECUN_BFMT_CV32CW5LAST1: + case ATON_DECUN_BFMT_CV32CW5LAST2: + case ATON_DECUN_BFMT_CV32CW5LAST3: + case ATON_DECUN_BFMT_CV32CW5LAST4: + case ATON_DECUN_BFMT_CV32CW6LAST1: + case ATON_DECUN_BFMT_CV32CW6LAST2: + case ATON_DECUN_BFMT_CV32CW6LAST3: + case ATON_DECUN_BFMT_CV32CW6LAST4: + case ATON_DECUN_BFMT_CV32CW6LAST5: + case ATON_DECUN_BFMT_CV32CW7LAST1: + case ATON_DECUN_BFMT_CV32CW7LAST2: + case ATON_DECUN_BFMT_CV32CW7LAST3: + case ATON_DECUN_BFMT_CV32CW7LAST4: + case ATON_DECUN_BFMT_CV32CW7LAST5: + case ATON_DECUN_BFMT_CV32CW7LAST6: + case ATON_DECUN_BFMT_CV32CW8LAST1: + case ATON_DECUN_BFMT_CV32CW8LAST2: + case ATON_DECUN_BFMT_CV32CW8LAST3: + case ATON_DECUN_BFMT_CV32CW8LAST4: + case ATON_DECUN_BFMT_CV32CW8LAST5: + case ATON_DECUN_BFMT_CV32CW8LAST6: + case ATON_DECUN_BFMT_CV32CW8LAST7: + case ATON_DECUN_BFMT_CV64CW2LAST1: + case ATON_DECUN_BFMT_CV64CW3LAST1: + case ATON_DECUN_BFMT_CV64CW3LAST2: + case ATON_DECUN_BFMT_CV64CW4LAST1: + case ATON_DECUN_BFMT_CV64CW4LAST2: + case ATON_DECUN_BFMT_CV64CW4LAST3: + case ATON_DECUN_BFMT_CV64CW5LAST1: + case ATON_DECUN_BFMT_CV64CW5LAST2: + case ATON_DECUN_BFMT_CV64CW5LAST3: + case ATON_DECUN_BFMT_CV64CW5LAST4: + case ATON_DECUN_BFMT_CV64CW6LAST1: + case ATON_DECUN_BFMT_CV64CW6LAST2: + case ATON_DECUN_BFMT_CV64CW6LAST3: + case ATON_DECUN_BFMT_CV64CW6LAST4: + case ATON_DECUN_BFMT_CV64CW6LAST5: + case ATON_DECUN_BFMT_CV64CW7LAST1: + case ATON_DECUN_BFMT_CV64CW7LAST2: + case ATON_DECUN_BFMT_CV64CW7LAST3: + case ATON_DECUN_BFMT_CV64CW7LAST4: + case ATON_DECUN_BFMT_CV64CW7LAST5: + case ATON_DECUN_BFMT_CV64CW7LAST6: + case ATON_DECUN_BFMT_CV64CW8LAST1: + case ATON_DECUN_BFMT_CV64CW8LAST2: + case ATON_DECUN_BFMT_CV64CW8LAST3: + case ATON_DECUN_BFMT_CV64CW8LAST4: + case ATON_DECUN_BFMT_CV64CW8LAST5: + case ATON_DECUN_BFMT_CV64CW8LAST6: + case ATON_DECUN_BFMT_CV64CW8LAST7: + case ATON_DECUN_BFMT_CV128CW2LAST1: + case ATON_DECUN_BFMT_CV128CW3LAST1: + case ATON_DECUN_BFMT_CV128CW3LAST2: + case ATON_DECUN_BFMT_CV128CW4LAST1: + case ATON_DECUN_BFMT_CV128CW4LAST2: + case ATON_DECUN_BFMT_CV128CW4LAST3: + case ATON_DECUN_BFMT_CV128CW5LAST1: + case ATON_DECUN_BFMT_CV128CW5LAST2: + case ATON_DECUN_BFMT_CV128CW5LAST3: + case ATON_DECUN_BFMT_CV128CW5LAST4: + case ATON_DECUN_BFMT_CV128CW6LAST1: + case ATON_DECUN_BFMT_CV128CW6LAST2: + case ATON_DECUN_BFMT_CV128CW6LAST3: + case ATON_DECUN_BFMT_CV128CW6LAST4: + case ATON_DECUN_BFMT_CV128CW6LAST5: + case ATON_DECUN_BFMT_CV128CW7LAST1: + case ATON_DECUN_BFMT_CV128CW7LAST2: + case ATON_DECUN_BFMT_CV128CW7LAST3: + case ATON_DECUN_BFMT_CV128CW7LAST4: + case ATON_DECUN_BFMT_CV128CW7LAST5: + case ATON_DECUN_BFMT_CV128CW7LAST6: + case ATON_DECUN_BFMT_CV128CW8LAST1: + case ATON_DECUN_BFMT_CV128CW8LAST2: + case ATON_DECUN_BFMT_CV128CW8LAST3: + case ATON_DECUN_BFMT_CV128CW8LAST4: + case ATON_DECUN_BFMT_CV128CW8LAST5: + case ATON_DECUN_BFMT_CV128CW8LAST6: + case ATON_DECUN_BFMT_CV128CW8LAST7: + case ATON_DECUN_BFMT_CV256CW2LAST1: + case ATON_DECUN_BFMT_CV256CW3LAST1: + case ATON_DECUN_BFMT_CV256CW3LAST2: + case ATON_DECUN_BFMT_CV256CW4LAST1: + case ATON_DECUN_BFMT_CV256CW4LAST2: + case ATON_DECUN_BFMT_CV256CW4LAST3: + case ATON_DECUN_BFMT_CV256CW5LAST1: + case ATON_DECUN_BFMT_CV256CW5LAST2: + case ATON_DECUN_BFMT_CV256CW5LAST3: + case ATON_DECUN_BFMT_CV256CW5LAST4: + case ATON_DECUN_BFMT_CV256CW6LAST1: + case ATON_DECUN_BFMT_CV256CW6LAST2: + case ATON_DECUN_BFMT_CV256CW6LAST3: + case ATON_DECUN_BFMT_CV256CW6LAST4: + case ATON_DECUN_BFMT_CV256CW6LAST5: + case ATON_DECUN_BFMT_CV256CW7LAST1: + case ATON_DECUN_BFMT_CV256CW7LAST2: + case ATON_DECUN_BFMT_CV256CW7LAST3: + case ATON_DECUN_BFMT_CV256CW7LAST4: + case ATON_DECUN_BFMT_CV256CW7LAST5: + case ATON_DECUN_BFMT_CV256CW7LAST6: + case ATON_DECUN_BFMT_CV256CW8LAST1: + case ATON_DECUN_BFMT_CV256CW8LAST2: + case ATON_DECUN_BFMT_CV256CW8LAST3: + case ATON_DECUN_BFMT_CV256CW8LAST4: + case ATON_DECUN_BFMT_CV256CW8LAST5: + case ATON_DECUN_BFMT_CV256CW8LAST6: + case ATON_DECUN_BFMT_CV256CW8LAST7: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the DECUN_BFMT set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the DECUN_BFMT set of enumerated values + */ + +static inline const int8_t *ATON_DECUN_BFMT_GetName(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_DECUN_BFMT_CV1CW1LAST0: + str = (const int8_t *)"CV1CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW2LAST0: + str = (const int8_t *)"CV1CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW3LAST0: + str = (const int8_t *)"CV1CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST0: + str = (const int8_t *)"CV1CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST0: + str = (const int8_t *)"CV1CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST0: + str = (const int8_t *)"CV1CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST0: + str = (const int8_t *)"CV1CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST0: + str = (const int8_t *)"CV1CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW2LAST1: + str = (const int8_t *)"CV1CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW3LAST1: + str = (const int8_t *)"CV1CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST1: + str = (const int8_t *)"CV1CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST1: + str = (const int8_t *)"CV1CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST1: + str = (const int8_t *)"CV1CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST1: + str = (const int8_t *)"CV1CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST1: + str = (const int8_t *)"CV1CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW3LAST2: + str = (const int8_t *)"CV1CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST2: + str = (const int8_t *)"CV1CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST2: + str = (const int8_t *)"CV1CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST2: + str = (const int8_t *)"CV1CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST2: + str = (const int8_t *)"CV1CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST2: + str = (const int8_t *)"CV1CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST3: + str = (const int8_t *)"CV1CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST3: + str = (const int8_t *)"CV1CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST3: + str = (const int8_t *)"CV1CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST3: + str = (const int8_t *)"CV1CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST3: + str = (const int8_t *)"CV1CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST4: + str = (const int8_t *)"CV1CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST4: + str = (const int8_t *)"CV1CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST4: + str = (const int8_t *)"CV1CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST4: + str = (const int8_t *)"CV1CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST5: + str = (const int8_t *)"CV1CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST5: + str = (const int8_t *)"CV1CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST5: + str = (const int8_t *)"CV1CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST6: + str = (const int8_t *)"CV1CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST6: + str = (const int8_t *)"CV1CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST7: + str = (const int8_t *)"CV1CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV2CW1LAST0: + str = (const int8_t *)"CV2CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW2LAST0: + str = (const int8_t *)"CV2CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW3LAST0: + str = (const int8_t *)"CV2CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST0: + str = (const int8_t *)"CV2CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST0: + str = (const int8_t *)"CV2CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST0: + str = (const int8_t *)"CV2CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST0: + str = (const int8_t *)"CV2CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST0: + str = (const int8_t *)"CV2CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW2LAST1: + str = (const int8_t *)"CV2CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW3LAST1: + str = (const int8_t *)"CV2CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST1: + str = (const int8_t *)"CV2CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST1: + str = (const int8_t *)"CV2CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST1: + str = (const int8_t *)"CV2CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST1: + str = (const int8_t *)"CV2CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST1: + str = (const int8_t *)"CV2CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW3LAST2: + str = (const int8_t *)"CV2CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST2: + str = (const int8_t *)"CV2CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST2: + str = (const int8_t *)"CV2CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST2: + str = (const int8_t *)"CV2CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST2: + str = (const int8_t *)"CV2CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST2: + str = (const int8_t *)"CV2CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST3: + str = (const int8_t *)"CV2CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST3: + str = (const int8_t *)"CV2CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST3: + str = (const int8_t *)"CV2CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST3: + str = (const int8_t *)"CV2CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST3: + str = (const int8_t *)"CV2CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST4: + str = (const int8_t *)"CV2CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST4: + str = (const int8_t *)"CV2CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST4: + str = (const int8_t *)"CV2CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST4: + str = (const int8_t *)"CV2CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST5: + str = (const int8_t *)"CV2CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST5: + str = (const int8_t *)"CV2CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST5: + str = (const int8_t *)"CV2CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST6: + str = (const int8_t *)"CV2CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST6: + str = (const int8_t *)"CV2CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST7: + str = (const int8_t *)"CV2CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV4CW1LAST0: + str = (const int8_t *)"CV4CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW2LAST0: + str = (const int8_t *)"CV4CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW3LAST0: + str = (const int8_t *)"CV4CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST0: + str = (const int8_t *)"CV4CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST0: + str = (const int8_t *)"CV4CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST0: + str = (const int8_t *)"CV4CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST0: + str = (const int8_t *)"CV4CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST0: + str = (const int8_t *)"CV4CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW2LAST1: + str = (const int8_t *)"CV4CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW3LAST1: + str = (const int8_t *)"CV4CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST1: + str = (const int8_t *)"CV4CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST1: + str = (const int8_t *)"CV4CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST1: + str = (const int8_t *)"CV4CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST1: + str = (const int8_t *)"CV4CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST1: + str = (const int8_t *)"CV4CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW3LAST2: + str = (const int8_t *)"CV4CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST2: + str = (const int8_t *)"CV4CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST2: + str = (const int8_t *)"CV4CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST2: + str = (const int8_t *)"CV4CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST2: + str = (const int8_t *)"CV4CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST2: + str = (const int8_t *)"CV4CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST3: + str = (const int8_t *)"CV4CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST3: + str = (const int8_t *)"CV4CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST3: + str = (const int8_t *)"CV4CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST3: + str = (const int8_t *)"CV4CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST3: + str = (const int8_t *)"CV4CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST4: + str = (const int8_t *)"CV4CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST4: + str = (const int8_t *)"CV4CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST4: + str = (const int8_t *)"CV4CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST4: + str = (const int8_t *)"CV4CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST5: + str = (const int8_t *)"CV4CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST5: + str = (const int8_t *)"CV4CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST5: + str = (const int8_t *)"CV4CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST6: + str = (const int8_t *)"CV4CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST6: + str = (const int8_t *)"CV4CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST7: + str = (const int8_t *)"CV4CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV8CW1LAST0: + str = (const int8_t *)"CV8CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW2LAST0: + str = (const int8_t *)"CV8CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW3LAST0: + str = (const int8_t *)"CV8CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST0: + str = (const int8_t *)"CV8CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST0: + str = (const int8_t *)"CV8CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST0: + str = (const int8_t *)"CV8CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST0: + str = (const int8_t *)"CV8CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST0: + str = (const int8_t *)"CV8CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW2LAST1: + str = (const int8_t *)"CV8CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW3LAST1: + str = (const int8_t *)"CV8CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST1: + str = (const int8_t *)"CV8CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST1: + str = (const int8_t *)"CV8CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST1: + str = (const int8_t *)"CV8CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST1: + str = (const int8_t *)"CV8CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST1: + str = (const int8_t *)"CV8CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW3LAST2: + str = (const int8_t *)"CV8CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST2: + str = (const int8_t *)"CV8CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST2: + str = (const int8_t *)"CV8CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST2: + str = (const int8_t *)"CV8CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST2: + str = (const int8_t *)"CV8CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST2: + str = (const int8_t *)"CV8CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST3: + str = (const int8_t *)"CV8CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST3: + str = (const int8_t *)"CV8CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST3: + str = (const int8_t *)"CV8CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST3: + str = (const int8_t *)"CV8CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST3: + str = (const int8_t *)"CV8CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST4: + str = (const int8_t *)"CV8CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST4: + str = (const int8_t *)"CV8CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST4: + str = (const int8_t *)"CV8CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST4: + str = (const int8_t *)"CV8CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST5: + str = (const int8_t *)"CV8CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST5: + str = (const int8_t *)"CV8CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST5: + str = (const int8_t *)"CV8CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST6: + str = (const int8_t *)"CV8CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST6: + str = (const int8_t *)"CV8CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST7: + str = (const int8_t *)"CV8CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV16CW1LAST0: + str = (const int8_t *)"CV16CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW2LAST0: + str = (const int8_t *)"CV16CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW3LAST0: + str = (const int8_t *)"CV16CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST0: + str = (const int8_t *)"CV16CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST0: + str = (const int8_t *)"CV16CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST0: + str = (const int8_t *)"CV16CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST0: + str = (const int8_t *)"CV16CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST0: + str = (const int8_t *)"CV16CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW1LAST0: + str = (const int8_t *)"CV32CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW2LAST0: + str = (const int8_t *)"CV32CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW3LAST0: + str = (const int8_t *)"CV32CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST0: + str = (const int8_t *)"CV32CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST0: + str = (const int8_t *)"CV32CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST0: + str = (const int8_t *)"CV32CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST0: + str = (const int8_t *)"CV32CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST0: + str = (const int8_t *)"CV32CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW1LAST0: + str = (const int8_t *)"CV64CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW2LAST0: + str = (const int8_t *)"CV64CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW3LAST0: + str = (const int8_t *)"CV64CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST0: + str = (const int8_t *)"CV64CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST0: + str = (const int8_t *)"CV64CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST0: + str = (const int8_t *)"CV64CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST0: + str = (const int8_t *)"CV64CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST0: + str = (const int8_t *)"CV64CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW1LAST0: + str = (const int8_t *)"CV128CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW2LAST0: + str = (const int8_t *)"CV128CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW3LAST0: + str = (const int8_t *)"CV128CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST0: + str = (const int8_t *)"CV128CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST0: + str = (const int8_t *)"CV128CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST0: + str = (const int8_t *)"CV128CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST0: + str = (const int8_t *)"CV128CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST0: + str = (const int8_t *)"CV128CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW1LAST0: + str = (const int8_t *)"CV256CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW2LAST0: + str = (const int8_t *)"CV256CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW3LAST0: + str = (const int8_t *)"CV256CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST0: + str = (const int8_t *)"CV256CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST0: + str = (const int8_t *)"CV256CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST0: + str = (const int8_t *)"CV256CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST0: + str = (const int8_t *)"CV256CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST0: + str = (const int8_t *)"CV256CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW2LAST1: + str = (const int8_t *)"CV16CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW3LAST1: + str = (const int8_t *)"CV16CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW3LAST2: + str = (const int8_t *)"CV16CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST1: + str = (const int8_t *)"CV16CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST2: + str = (const int8_t *)"CV16CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST3: + str = (const int8_t *)"CV16CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST1: + str = (const int8_t *)"CV16CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST2: + str = (const int8_t *)"CV16CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST3: + str = (const int8_t *)"CV16CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST4: + str = (const int8_t *)"CV16CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST1: + str = (const int8_t *)"CV16CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST2: + str = (const int8_t *)"CV16CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST3: + str = (const int8_t *)"CV16CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST4: + str = (const int8_t *)"CV16CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST5: + str = (const int8_t *)"CV16CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST1: + str = (const int8_t *)"CV16CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST2: + str = (const int8_t *)"CV16CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST3: + str = (const int8_t *)"CV16CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST4: + str = (const int8_t *)"CV16CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST5: + str = (const int8_t *)"CV16CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST6: + str = (const int8_t *)"CV16CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST1: + str = (const int8_t *)"CV16CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST2: + str = (const int8_t *)"CV16CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST3: + str = (const int8_t *)"CV16CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST4: + str = (const int8_t *)"CV16CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST5: + str = (const int8_t *)"CV16CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST6: + str = (const int8_t *)"CV16CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST7: + str = (const int8_t *)"CV16CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV32CW2LAST1: + str = (const int8_t *)"CV32CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW3LAST1: + str = (const int8_t *)"CV32CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW3LAST2: + str = (const int8_t *)"CV32CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST1: + str = (const int8_t *)"CV32CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST2: + str = (const int8_t *)"CV32CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST3: + str = (const int8_t *)"CV32CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST1: + str = (const int8_t *)"CV32CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST2: + str = (const int8_t *)"CV32CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST3: + str = (const int8_t *)"CV32CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST4: + str = (const int8_t *)"CV32CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST1: + str = (const int8_t *)"CV32CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST2: + str = (const int8_t *)"CV32CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST3: + str = (const int8_t *)"CV32CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST4: + str = (const int8_t *)"CV32CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST5: + str = (const int8_t *)"CV32CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST1: + str = (const int8_t *)"CV32CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST2: + str = (const int8_t *)"CV32CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST3: + str = (const int8_t *)"CV32CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST4: + str = (const int8_t *)"CV32CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST5: + str = (const int8_t *)"CV32CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST6: + str = (const int8_t *)"CV32CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST1: + str = (const int8_t *)"CV32CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST2: + str = (const int8_t *)"CV32CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST3: + str = (const int8_t *)"CV32CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST4: + str = (const int8_t *)"CV32CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST5: + str = (const int8_t *)"CV32CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST6: + str = (const int8_t *)"CV32CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST7: + str = (const int8_t *)"CV32CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV64CW2LAST1: + str = (const int8_t *)"CV64CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW3LAST1: + str = (const int8_t *)"CV64CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW3LAST2: + str = (const int8_t *)"CV64CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST1: + str = (const int8_t *)"CV64CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST2: + str = (const int8_t *)"CV64CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST3: + str = (const int8_t *)"CV64CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST1: + str = (const int8_t *)"CV64CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST2: + str = (const int8_t *)"CV64CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST3: + str = (const int8_t *)"CV64CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST4: + str = (const int8_t *)"CV64CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST1: + str = (const int8_t *)"CV64CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST2: + str = (const int8_t *)"CV64CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST3: + str = (const int8_t *)"CV64CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST4: + str = (const int8_t *)"CV64CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST5: + str = (const int8_t *)"CV64CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST1: + str = (const int8_t *)"CV64CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST2: + str = (const int8_t *)"CV64CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST3: + str = (const int8_t *)"CV64CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST4: + str = (const int8_t *)"CV64CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST5: + str = (const int8_t *)"CV64CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST6: + str = (const int8_t *)"CV64CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST1: + str = (const int8_t *)"CV64CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST2: + str = (const int8_t *)"CV64CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST3: + str = (const int8_t *)"CV64CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST4: + str = (const int8_t *)"CV64CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST5: + str = (const int8_t *)"CV64CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST6: + str = (const int8_t *)"CV64CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST7: + str = (const int8_t *)"CV64CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV128CW2LAST1: + str = (const int8_t *)"CV128CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW3LAST1: + str = (const int8_t *)"CV128CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW3LAST2: + str = (const int8_t *)"CV128CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST1: + str = (const int8_t *)"CV128CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST2: + str = (const int8_t *)"CV128CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST3: + str = (const int8_t *)"CV128CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST1: + str = (const int8_t *)"CV128CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST2: + str = (const int8_t *)"CV128CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST3: + str = (const int8_t *)"CV128CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST4: + str = (const int8_t *)"CV128CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST1: + str = (const int8_t *)"CV128CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST2: + str = (const int8_t *)"CV128CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST3: + str = (const int8_t *)"CV128CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST4: + str = (const int8_t *)"CV128CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST5: + str = (const int8_t *)"CV128CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST1: + str = (const int8_t *)"CV128CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST2: + str = (const int8_t *)"CV128CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST3: + str = (const int8_t *)"CV128CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST4: + str = (const int8_t *)"CV128CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST5: + str = (const int8_t *)"CV128CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST6: + str = (const int8_t *)"CV128CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST1: + str = (const int8_t *)"CV128CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST2: + str = (const int8_t *)"CV128CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST3: + str = (const int8_t *)"CV128CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST4: + str = (const int8_t *)"CV128CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST5: + str = (const int8_t *)"CV128CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST6: + str = (const int8_t *)"CV128CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST7: + str = (const int8_t *)"CV128CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV256CW2LAST1: + str = (const int8_t *)"CV256CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW3LAST1: + str = (const int8_t *)"CV256CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW3LAST2: + str = (const int8_t *)"CV256CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST1: + str = (const int8_t *)"CV256CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST2: + str = (const int8_t *)"CV256CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST3: + str = (const int8_t *)"CV256CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST1: + str = (const int8_t *)"CV256CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST2: + str = (const int8_t *)"CV256CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST3: + str = (const int8_t *)"CV256CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST4: + str = (const int8_t *)"CV256CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST1: + str = (const int8_t *)"CV256CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST2: + str = (const int8_t *)"CV256CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST3: + str = (const int8_t *)"CV256CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST4: + str = (const int8_t *)"CV256CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST5: + str = (const int8_t *)"CV256CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST1: + str = (const int8_t *)"CV256CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST2: + str = (const int8_t *)"CV256CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST3: + str = (const int8_t *)"CV256CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST4: + str = (const int8_t *)"CV256CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST5: + str = (const int8_t *)"CV256CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST6: + str = (const int8_t *)"CV256CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST1: + str = (const int8_t *)"CV256CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST2: + str = (const int8_t *)"CV256CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST3: + str = (const int8_t *)"CV256CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST4: + str = (const int8_t *)"CV256CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST5: + str = (const int8_t *)"CV256CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST6: + str = (const int8_t *)"CV256CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST7: + str = (const int8_t *)"CV256CW8LAST7"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the DECUN_BFMT set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the DECUN_BFMT set of enumerated values + */ + +static inline const int8_t *ATON_DECUN_BFMT_GetDesc(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_DECUN_BFMT_CV1CW1LAST0: + str = (const int8_t *)"CV1CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW2LAST0: + str = (const int8_t *)"CV1CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW3LAST0: + str = (const int8_t *)"CV1CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST0: + str = (const int8_t *)"CV1CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST0: + str = (const int8_t *)"CV1CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST0: + str = (const int8_t *)"CV1CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST0: + str = (const int8_t *)"CV1CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST0: + str = (const int8_t *)"CV1CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV1CW2LAST1: + str = (const int8_t *)"CV1CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW3LAST1: + str = (const int8_t *)"CV1CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST1: + str = (const int8_t *)"CV1CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST1: + str = (const int8_t *)"CV1CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST1: + str = (const int8_t *)"CV1CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST1: + str = (const int8_t *)"CV1CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST1: + str = (const int8_t *)"CV1CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV1CW3LAST2: + str = (const int8_t *)"CV1CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST2: + str = (const int8_t *)"CV1CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST2: + str = (const int8_t *)"CV1CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST2: + str = (const int8_t *)"CV1CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST2: + str = (const int8_t *)"CV1CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST2: + str = (const int8_t *)"CV1CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV1CW4LAST3: + str = (const int8_t *)"CV1CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST3: + str = (const int8_t *)"CV1CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST3: + str = (const int8_t *)"CV1CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST3: + str = (const int8_t *)"CV1CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST3: + str = (const int8_t *)"CV1CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV1CW5LAST4: + str = (const int8_t *)"CV1CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST4: + str = (const int8_t *)"CV1CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST4: + str = (const int8_t *)"CV1CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST4: + str = (const int8_t *)"CV1CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV1CW6LAST5: + str = (const int8_t *)"CV1CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST5: + str = (const int8_t *)"CV1CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST5: + str = (const int8_t *)"CV1CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV1CW7LAST6: + str = (const int8_t *)"CV1CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST6: + str = (const int8_t *)"CV1CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV1CW8LAST7: + str = (const int8_t *)"CV1CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV2CW1LAST0: + str = (const int8_t *)"CV2CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW2LAST0: + str = (const int8_t *)"CV2CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW3LAST0: + str = (const int8_t *)"CV2CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST0: + str = (const int8_t *)"CV2CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST0: + str = (const int8_t *)"CV2CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST0: + str = (const int8_t *)"CV2CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST0: + str = (const int8_t *)"CV2CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST0: + str = (const int8_t *)"CV2CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV2CW2LAST1: + str = (const int8_t *)"CV2CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW3LAST1: + str = (const int8_t *)"CV2CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST1: + str = (const int8_t *)"CV2CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST1: + str = (const int8_t *)"CV2CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST1: + str = (const int8_t *)"CV2CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST1: + str = (const int8_t *)"CV2CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST1: + str = (const int8_t *)"CV2CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV2CW3LAST2: + str = (const int8_t *)"CV2CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST2: + str = (const int8_t *)"CV2CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST2: + str = (const int8_t *)"CV2CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST2: + str = (const int8_t *)"CV2CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST2: + str = (const int8_t *)"CV2CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST2: + str = (const int8_t *)"CV2CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV2CW4LAST3: + str = (const int8_t *)"CV2CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST3: + str = (const int8_t *)"CV2CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST3: + str = (const int8_t *)"CV2CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST3: + str = (const int8_t *)"CV2CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST3: + str = (const int8_t *)"CV2CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV2CW5LAST4: + str = (const int8_t *)"CV2CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST4: + str = (const int8_t *)"CV2CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST4: + str = (const int8_t *)"CV2CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST4: + str = (const int8_t *)"CV2CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV2CW6LAST5: + str = (const int8_t *)"CV2CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST5: + str = (const int8_t *)"CV2CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST5: + str = (const int8_t *)"CV2CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV2CW7LAST6: + str = (const int8_t *)"CV2CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST6: + str = (const int8_t *)"CV2CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV2CW8LAST7: + str = (const int8_t *)"CV2CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV4CW1LAST0: + str = (const int8_t *)"CV4CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW2LAST0: + str = (const int8_t *)"CV4CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW3LAST0: + str = (const int8_t *)"CV4CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST0: + str = (const int8_t *)"CV4CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST0: + str = (const int8_t *)"CV4CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST0: + str = (const int8_t *)"CV4CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST0: + str = (const int8_t *)"CV4CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST0: + str = (const int8_t *)"CV4CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV4CW2LAST1: + str = (const int8_t *)"CV4CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW3LAST1: + str = (const int8_t *)"CV4CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST1: + str = (const int8_t *)"CV4CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST1: + str = (const int8_t *)"CV4CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST1: + str = (const int8_t *)"CV4CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST1: + str = (const int8_t *)"CV4CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST1: + str = (const int8_t *)"CV4CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV4CW3LAST2: + str = (const int8_t *)"CV4CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST2: + str = (const int8_t *)"CV4CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST2: + str = (const int8_t *)"CV4CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST2: + str = (const int8_t *)"CV4CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST2: + str = (const int8_t *)"CV4CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST2: + str = (const int8_t *)"CV4CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV4CW4LAST3: + str = (const int8_t *)"CV4CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST3: + str = (const int8_t *)"CV4CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST3: + str = (const int8_t *)"CV4CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST3: + str = (const int8_t *)"CV4CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST3: + str = (const int8_t *)"CV4CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV4CW5LAST4: + str = (const int8_t *)"CV4CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST4: + str = (const int8_t *)"CV4CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST4: + str = (const int8_t *)"CV4CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST4: + str = (const int8_t *)"CV4CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV4CW6LAST5: + str = (const int8_t *)"CV4CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST5: + str = (const int8_t *)"CV4CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST5: + str = (const int8_t *)"CV4CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV4CW7LAST6: + str = (const int8_t *)"CV4CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST6: + str = (const int8_t *)"CV4CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV4CW8LAST7: + str = (const int8_t *)"CV4CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV8CW1LAST0: + str = (const int8_t *)"CV8CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW2LAST0: + str = (const int8_t *)"CV8CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW3LAST0: + str = (const int8_t *)"CV8CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST0: + str = (const int8_t *)"CV8CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST0: + str = (const int8_t *)"CV8CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST0: + str = (const int8_t *)"CV8CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST0: + str = (const int8_t *)"CV8CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST0: + str = (const int8_t *)"CV8CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV8CW2LAST1: + str = (const int8_t *)"CV8CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW3LAST1: + str = (const int8_t *)"CV8CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST1: + str = (const int8_t *)"CV8CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST1: + str = (const int8_t *)"CV8CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST1: + str = (const int8_t *)"CV8CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST1: + str = (const int8_t *)"CV8CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST1: + str = (const int8_t *)"CV8CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV8CW3LAST2: + str = (const int8_t *)"CV8CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST2: + str = (const int8_t *)"CV8CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST2: + str = (const int8_t *)"CV8CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST2: + str = (const int8_t *)"CV8CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST2: + str = (const int8_t *)"CV8CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST2: + str = (const int8_t *)"CV8CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV8CW4LAST3: + str = (const int8_t *)"CV8CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST3: + str = (const int8_t *)"CV8CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST3: + str = (const int8_t *)"CV8CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST3: + str = (const int8_t *)"CV8CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST3: + str = (const int8_t *)"CV8CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV8CW5LAST4: + str = (const int8_t *)"CV8CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST4: + str = (const int8_t *)"CV8CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST4: + str = (const int8_t *)"CV8CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST4: + str = (const int8_t *)"CV8CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV8CW6LAST5: + str = (const int8_t *)"CV8CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST5: + str = (const int8_t *)"CV8CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST5: + str = (const int8_t *)"CV8CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV8CW7LAST6: + str = (const int8_t *)"CV8CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST6: + str = (const int8_t *)"CV8CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV8CW8LAST7: + str = (const int8_t *)"CV8CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV16CW1LAST0: + str = (const int8_t *)"CV16CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW2LAST0: + str = (const int8_t *)"CV16CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW3LAST0: + str = (const int8_t *)"CV16CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST0: + str = (const int8_t *)"CV16CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST0: + str = (const int8_t *)"CV16CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST0: + str = (const int8_t *)"CV16CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST0: + str = (const int8_t *)"CV16CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST0: + str = (const int8_t *)"CV16CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW1LAST0: + str = (const int8_t *)"CV32CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW2LAST0: + str = (const int8_t *)"CV32CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW3LAST0: + str = (const int8_t *)"CV32CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST0: + str = (const int8_t *)"CV32CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST0: + str = (const int8_t *)"CV32CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST0: + str = (const int8_t *)"CV32CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST0: + str = (const int8_t *)"CV32CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST0: + str = (const int8_t *)"CV32CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW1LAST0: + str = (const int8_t *)"CV64CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW2LAST0: + str = (const int8_t *)"CV64CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW3LAST0: + str = (const int8_t *)"CV64CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST0: + str = (const int8_t *)"CV64CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST0: + str = (const int8_t *)"CV64CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST0: + str = (const int8_t *)"CV64CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST0: + str = (const int8_t *)"CV64CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST0: + str = (const int8_t *)"CV64CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW1LAST0: + str = (const int8_t *)"CV128CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW2LAST0: + str = (const int8_t *)"CV128CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW3LAST0: + str = (const int8_t *)"CV128CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST0: + str = (const int8_t *)"CV128CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST0: + str = (const int8_t *)"CV128CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST0: + str = (const int8_t *)"CV128CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST0: + str = (const int8_t *)"CV128CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST0: + str = (const int8_t *)"CV128CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW1LAST0: + str = (const int8_t *)"CV256CW1LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW2LAST0: + str = (const int8_t *)"CV256CW2LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW3LAST0: + str = (const int8_t *)"CV256CW3LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST0: + str = (const int8_t *)"CV256CW4LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST0: + str = (const int8_t *)"CV256CW5LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST0: + str = (const int8_t *)"CV256CW6LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST0: + str = (const int8_t *)"CV256CW7LAST0"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST0: + str = (const int8_t *)"CV256CW8LAST0"; + break; + + case ATON_DECUN_BFMT_CV16CW2LAST1: + str = (const int8_t *)"CV16CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW3LAST1: + str = (const int8_t *)"CV16CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW3LAST2: + str = (const int8_t *)"CV16CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST1: + str = (const int8_t *)"CV16CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST2: + str = (const int8_t *)"CV16CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW4LAST3: + str = (const int8_t *)"CV16CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST1: + str = (const int8_t *)"CV16CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST2: + str = (const int8_t *)"CV16CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST3: + str = (const int8_t *)"CV16CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW5LAST4: + str = (const int8_t *)"CV16CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST1: + str = (const int8_t *)"CV16CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST2: + str = (const int8_t *)"CV16CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST3: + str = (const int8_t *)"CV16CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST4: + str = (const int8_t *)"CV16CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW6LAST5: + str = (const int8_t *)"CV16CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST1: + str = (const int8_t *)"CV16CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST2: + str = (const int8_t *)"CV16CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST3: + str = (const int8_t *)"CV16CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST4: + str = (const int8_t *)"CV16CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST5: + str = (const int8_t *)"CV16CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV16CW7LAST6: + str = (const int8_t *)"CV16CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST1: + str = (const int8_t *)"CV16CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST2: + str = (const int8_t *)"CV16CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST3: + str = (const int8_t *)"CV16CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST4: + str = (const int8_t *)"CV16CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST5: + str = (const int8_t *)"CV16CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST6: + str = (const int8_t *)"CV16CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV16CW8LAST7: + str = (const int8_t *)"CV16CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV32CW2LAST1: + str = (const int8_t *)"CV32CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW3LAST1: + str = (const int8_t *)"CV32CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW3LAST2: + str = (const int8_t *)"CV32CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST1: + str = (const int8_t *)"CV32CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST2: + str = (const int8_t *)"CV32CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW4LAST3: + str = (const int8_t *)"CV32CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST1: + str = (const int8_t *)"CV32CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST2: + str = (const int8_t *)"CV32CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST3: + str = (const int8_t *)"CV32CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW5LAST4: + str = (const int8_t *)"CV32CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST1: + str = (const int8_t *)"CV32CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST2: + str = (const int8_t *)"CV32CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST3: + str = (const int8_t *)"CV32CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST4: + str = (const int8_t *)"CV32CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW6LAST5: + str = (const int8_t *)"CV32CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST1: + str = (const int8_t *)"CV32CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST2: + str = (const int8_t *)"CV32CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST3: + str = (const int8_t *)"CV32CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST4: + str = (const int8_t *)"CV32CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST5: + str = (const int8_t *)"CV32CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV32CW7LAST6: + str = (const int8_t *)"CV32CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST1: + str = (const int8_t *)"CV32CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST2: + str = (const int8_t *)"CV32CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST3: + str = (const int8_t *)"CV32CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST4: + str = (const int8_t *)"CV32CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST5: + str = (const int8_t *)"CV32CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST6: + str = (const int8_t *)"CV32CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV32CW8LAST7: + str = (const int8_t *)"CV32CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV64CW2LAST1: + str = (const int8_t *)"CV64CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW3LAST1: + str = (const int8_t *)"CV64CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW3LAST2: + str = (const int8_t *)"CV64CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST1: + str = (const int8_t *)"CV64CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST2: + str = (const int8_t *)"CV64CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW4LAST3: + str = (const int8_t *)"CV64CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST1: + str = (const int8_t *)"CV64CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST2: + str = (const int8_t *)"CV64CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST3: + str = (const int8_t *)"CV64CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW5LAST4: + str = (const int8_t *)"CV64CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST1: + str = (const int8_t *)"CV64CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST2: + str = (const int8_t *)"CV64CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST3: + str = (const int8_t *)"CV64CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST4: + str = (const int8_t *)"CV64CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW6LAST5: + str = (const int8_t *)"CV64CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST1: + str = (const int8_t *)"CV64CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST2: + str = (const int8_t *)"CV64CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST3: + str = (const int8_t *)"CV64CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST4: + str = (const int8_t *)"CV64CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST5: + str = (const int8_t *)"CV64CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV64CW7LAST6: + str = (const int8_t *)"CV64CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST1: + str = (const int8_t *)"CV64CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST2: + str = (const int8_t *)"CV64CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST3: + str = (const int8_t *)"CV64CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST4: + str = (const int8_t *)"CV64CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST5: + str = (const int8_t *)"CV64CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST6: + str = (const int8_t *)"CV64CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV64CW8LAST7: + str = (const int8_t *)"CV64CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV128CW2LAST1: + str = (const int8_t *)"CV128CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW3LAST1: + str = (const int8_t *)"CV128CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW3LAST2: + str = (const int8_t *)"CV128CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST1: + str = (const int8_t *)"CV128CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST2: + str = (const int8_t *)"CV128CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW4LAST3: + str = (const int8_t *)"CV128CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST1: + str = (const int8_t *)"CV128CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST2: + str = (const int8_t *)"CV128CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST3: + str = (const int8_t *)"CV128CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW5LAST4: + str = (const int8_t *)"CV128CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST1: + str = (const int8_t *)"CV128CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST2: + str = (const int8_t *)"CV128CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST3: + str = (const int8_t *)"CV128CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST4: + str = (const int8_t *)"CV128CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW6LAST5: + str = (const int8_t *)"CV128CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST1: + str = (const int8_t *)"CV128CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST2: + str = (const int8_t *)"CV128CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST3: + str = (const int8_t *)"CV128CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST4: + str = (const int8_t *)"CV128CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST5: + str = (const int8_t *)"CV128CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV128CW7LAST6: + str = (const int8_t *)"CV128CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST1: + str = (const int8_t *)"CV128CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST2: + str = (const int8_t *)"CV128CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST3: + str = (const int8_t *)"CV128CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST4: + str = (const int8_t *)"CV128CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST5: + str = (const int8_t *)"CV128CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST6: + str = (const int8_t *)"CV128CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV128CW8LAST7: + str = (const int8_t *)"CV128CW8LAST7"; + break; + + case ATON_DECUN_BFMT_CV256CW2LAST1: + str = (const int8_t *)"CV256CW2LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW3LAST1: + str = (const int8_t *)"CV256CW3LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW3LAST2: + str = (const int8_t *)"CV256CW3LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST1: + str = (const int8_t *)"CV256CW4LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST2: + str = (const int8_t *)"CV256CW4LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW4LAST3: + str = (const int8_t *)"CV256CW4LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST1: + str = (const int8_t *)"CV256CW5LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST2: + str = (const int8_t *)"CV256CW5LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST3: + str = (const int8_t *)"CV256CW5LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW5LAST4: + str = (const int8_t *)"CV256CW5LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST1: + str = (const int8_t *)"CV256CW6LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST2: + str = (const int8_t *)"CV256CW6LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST3: + str = (const int8_t *)"CV256CW6LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST4: + str = (const int8_t *)"CV256CW6LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW6LAST5: + str = (const int8_t *)"CV256CW6LAST5"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST1: + str = (const int8_t *)"CV256CW7LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST2: + str = (const int8_t *)"CV256CW7LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST3: + str = (const int8_t *)"CV256CW7LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST4: + str = (const int8_t *)"CV256CW7LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST5: + str = (const int8_t *)"CV256CW7LAST5"; + break; + + case ATON_DECUN_BFMT_CV256CW7LAST6: + str = (const int8_t *)"CV256CW7LAST6"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST1: + str = (const int8_t *)"CV256CW8LAST1"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST2: + str = (const int8_t *)"CV256CW8LAST2"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST3: + str = (const int8_t *)"CV256CW8LAST3"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST4: + str = (const int8_t *)"CV256CW8LAST4"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST5: + str = (const int8_t *)"CV256CW8LAST5"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST6: + str = (const int8_t *)"CV256CW8LAST6"; + break; + + case ATON_DECUN_BFMT_CV256CW8LAST7: + str = (const int8_t *)"CV256CW8LAST7"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* DECUN_DFMT set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** DFORMAT values: DATA16. */ +#define ATON_DECUN_DFMT_DATA16 (0x0UL) + +/** DFORMAT values: DATA8. */ +#define ATON_DECUN_DFMT_DATA8 (0x1UL) + + +/** Get the name of one of the values of the DECUN_DFMT set of enumerated values. */ +#define ATON_DECUN_DFMT_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "DATA16" : \ + (((VALUE) == 1UL) ? "DATA8" : "")) + + +/** + * Check if a value of the DECUN_DFMT set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the DECUN_DFMT set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_DECUN_DFMT_IsValid(uint32_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_DECUN_DFMT_DATA16: + case ATON_DECUN_DFMT_DATA8: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the DECUN_DFMT set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the DECUN_DFMT set of enumerated values + */ + +static inline const int8_t *ATON_DECUN_DFMT_GetName(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_DECUN_DFMT_DATA16: + str = (const int8_t *)"DATA16"; + break; + + case ATON_DECUN_DFMT_DATA8: + str = (const int8_t *)"DATA8"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the DECUN_DFMT set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the DECUN_DFMT set of enumerated values + */ + +static inline const int8_t *ATON_DECUN_DFMT_GetDesc(uint32_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_DECUN_DFMT_DATA16: + str = (const int8_t *)"DATA16"; + break; + + case ATON_DECUN_DFMT_DATA8: + str = (const int8_t *)"DATA8"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* EVENTTYPE set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Event type: Pixels. */ +#define ATON_EVENTTYPE_PIXELS (0x0UL) + +/** Event type: Lines. */ +#define ATON_EVENTTYPE_LINES (0x1UL) + +/** Event type: Frames. */ +#define ATON_EVENTTYPE_FRAMES (0x2UL) + + +/** Get the name of one of the values of the EVENTTYPE set of enumerated values. */ +#define ATON_EVENTTYPE_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "PIXELS" : \ + (((VALUE) == 1UL) ? "LINES" : \ + (((VALUE) == 2UL) ? "FRAMES" : ""))) + + +/** + * Check if a value of the EVENTTYPE set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the EVENTTYPE set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_EVENTTYPE_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_EVENTTYPE_PIXELS: + case ATON_EVENTTYPE_LINES: + case ATON_EVENTTYPE_FRAMES: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the EVENTTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the EVENTTYPE set of enumerated values + */ + +static inline const int8_t *ATON_EVENTTYPE_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_EVENTTYPE_PIXELS: + str = (const int8_t *)"PIXELS"; + break; + + case ATON_EVENTTYPE_LINES: + str = (const int8_t *)"LINES"; + break; + + case ATON_EVENTTYPE_FRAMES: + str = (const int8_t *)"FRAMES"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the EVENTTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the EVENTTYPE set of enumerated values + */ + +static inline const int8_t *ATON_EVENTTYPE_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_EVENTTYPE_PIXELS: + str = (const int8_t *)"Pixels"; + break; + + case ATON_EVENTTYPE_LINES: + str = (const int8_t *)"Lines"; + break; + + case ATON_EVENTTYPE_FRAMES: + str = (const int8_t *)"Frames"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* LINK set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Source port: Stream Engine 0. */ +#define ATON_LINK_STRENG0 (0x0UL) + +/** Source port: Stream Engine 1. */ +#define ATON_LINK_STRENG1 (0x1UL) + +/** Source port: Stream Engine 2. */ +#define ATON_LINK_STRENG2 (0x2UL) + +/** Source port: Stream Engine 3. */ +#define ATON_LINK_STRENG3 (0x3UL) + +/** Source port: Stream Engine 4. */ +#define ATON_LINK_STRENG4 (0x4UL) + +/** Source port: Stream Engine 5. */ +#define ATON_LINK_STRENG5 (0x5UL) + +/** Source port: Stream Engine 6. */ +#define ATON_LINK_STRENG6 (0x6UL) + +/** Source port: Stream Engine 7. */ +#define ATON_LINK_STRENG7 (0x7UL) + +/** Source port: Stream Engine 8. */ +#define ATON_LINK_STRENG8 (0x8UL) + +/** Source port: Stream Engine 9. */ +#define ATON_LINK_STRENG9 (0x9UL) + +/** Source port: Convolutional Accelerator 0. */ +#define ATON_LINK_CONVACC0 (0xaUL) + +/** Source port: Convolutional Accelerator 1. */ +#define ATON_LINK_CONVACC1 (0xbUL) + +/** Source port: Convolutional Accelerator 2. */ +#define ATON_LINK_CONVACC2 (0xcUL) + +/** Source port: Convolutional Accelerator 3. */ +#define ATON_LINK_CONVACC3 (0xdUL) + +/** Source port: Decompression Unit 0. */ +#define ATON_LINK_DECUN0 (0xeUL) + +/** Source port: Decompression Unit 1. */ +#define ATON_LINK_DECUN1 (0xfUL) + +/** Source port: Activation Accelerator 0. */ +#define ATON_LINK_ACTIV0 (0x10UL) + +/** Source port: Activation Accelerator 1. */ +#define ATON_LINK_ACTIV1 (0x11UL) + +/** Source port: Arithmetic Accelerator 0. */ +#define ATON_LINK_ARITH0 (0x12UL) + +/** Source port: Arithmetic Accelerator 1. */ +#define ATON_LINK_ARITH1 (0x13UL) + +/** Source port: Arithmetic Accelerator 2. */ +#define ATON_LINK_ARITH2 (0x14UL) + +/** Source port: Arithmetic Accelerator 3. */ +#define ATON_LINK_ARITH3 (0x15UL) + +/** Source port: Pooling Accelerator 0. */ +#define ATON_LINK_POOL0 (0x16UL) + +/** Source port: Pooling Accelerator 1. */ +#define ATON_LINK_POOL1 (0x17UL) + +/** Source port: Reconfigurable Buffer 0 port 0. */ +#define ATON_LINK_RECBUF00 (0x18UL) + +/** Source port: Reconfigurable Buffer 0 port 1. */ +#define ATON_LINK_RECBUF01 (0x19UL) + +/** Source port: Reconfigurable Buffer 0 port 2. */ +#define ATON_LINK_RECBUF02 (0x1aUL) + + +/** Get the name of one of the values of the LINK set of enumerated values. */ +#define ATON_LINK_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "STRENG0" : \ + (((VALUE) == 1UL) ? "STRENG1" : \ + (((VALUE) == 2UL) ? "STRENG2" : \ + (((VALUE) == 3UL) ? "STRENG3" : \ + (((VALUE) == 4UL) ? "STRENG4" : \ + (((VALUE) == 5UL) ? "STRENG5" : \ + (((VALUE) == 6UL) ? "STRENG6" : \ + (((VALUE) == 7UL) ? "STRENG7" : \ + (((VALUE) == 8UL) ? "STRENG8" : \ + (((VALUE) == 9UL) ? "STRENG9" : \ + (((VALUE) == 10UL) ? "CONVACC0" : \ + (((VALUE) == 11UL) ? "CONVACC1" : \ + (((VALUE) == 12UL) ? "CONVACC2" : \ + (((VALUE) == 13UL) ? "CONVACC3" : \ + (((VALUE) == 14UL) ? "DECUN0" : \ + (((VALUE) == 15UL) ? "DECUN1" : \ + (((VALUE) == 16UL) ? "ACTIV0" : \ + (((VALUE) == 17UL) ? "ACTIV1" : \ + (((VALUE) == 18UL) ? "ARITH0" : \ + (((VALUE) == 19UL) ? "ARITH1" : \ + (((VALUE) == 20UL) ? "ARITH2" : \ + (((VALUE) == 21UL) ? "ARITH3" : \ + (((VALUE) == 22UL) ? "POOL0" : \ + (((VALUE) == 23UL) ? "POOL1" : \ + (((VALUE) == 24UL) ? "RECBUF00" : \ + (((VALUE) == 25UL) ? "RECBUF01" : \ + (((VALUE) == 26UL) ? "RECBUF02" : ""))))))))))))))))))))))))))) + + +/** + * Check if a value of the LINK set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the LINK set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_LINK_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_LINK_STRENG0: + case ATON_LINK_STRENG1: + case ATON_LINK_STRENG2: + case ATON_LINK_STRENG3: + case ATON_LINK_STRENG4: + case ATON_LINK_STRENG5: + case ATON_LINK_STRENG6: + case ATON_LINK_STRENG7: + case ATON_LINK_STRENG8: + case ATON_LINK_STRENG9: + case ATON_LINK_CONVACC0: + case ATON_LINK_CONVACC1: + case ATON_LINK_CONVACC2: + case ATON_LINK_CONVACC3: + case ATON_LINK_DECUN0: + case ATON_LINK_DECUN1: + case ATON_LINK_ACTIV0: + case ATON_LINK_ACTIV1: + case ATON_LINK_ARITH0: + case ATON_LINK_ARITH1: + case ATON_LINK_ARITH2: + case ATON_LINK_ARITH3: + case ATON_LINK_POOL0: + case ATON_LINK_POOL1: + case ATON_LINK_RECBUF00: + case ATON_LINK_RECBUF01: + case ATON_LINK_RECBUF02: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the LINK set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the LINK set of enumerated values + */ + +static inline const int8_t *ATON_LINK_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_LINK_STRENG0: + str = (const int8_t *)"STRENG0"; + break; + + case ATON_LINK_STRENG1: + str = (const int8_t *)"STRENG1"; + break; + + case ATON_LINK_STRENG2: + str = (const int8_t *)"STRENG2"; + break; + + case ATON_LINK_STRENG3: + str = (const int8_t *)"STRENG3"; + break; + + case ATON_LINK_STRENG4: + str = (const int8_t *)"STRENG4"; + break; + + case ATON_LINK_STRENG5: + str = (const int8_t *)"STRENG5"; + break; + + case ATON_LINK_STRENG6: + str = (const int8_t *)"STRENG6"; + break; + + case ATON_LINK_STRENG7: + str = (const int8_t *)"STRENG7"; + break; + + case ATON_LINK_STRENG8: + str = (const int8_t *)"STRENG8"; + break; + + case ATON_LINK_STRENG9: + str = (const int8_t *)"STRENG9"; + break; + + case ATON_LINK_CONVACC0: + str = (const int8_t *)"CONVACC0"; + break; + + case ATON_LINK_CONVACC1: + str = (const int8_t *)"CONVACC1"; + break; + + case ATON_LINK_CONVACC2: + str = (const int8_t *)"CONVACC2"; + break; + + case ATON_LINK_CONVACC3: + str = (const int8_t *)"CONVACC3"; + break; + + case ATON_LINK_DECUN0: + str = (const int8_t *)"DECUN0"; + break; + + case ATON_LINK_DECUN1: + str = (const int8_t *)"DECUN1"; + break; + + case ATON_LINK_ACTIV0: + str = (const int8_t *)"ACTIV0"; + break; + + case ATON_LINK_ACTIV1: + str = (const int8_t *)"ACTIV1"; + break; + + case ATON_LINK_ARITH0: + str = (const int8_t *)"ARITH0"; + break; + + case ATON_LINK_ARITH1: + str = (const int8_t *)"ARITH1"; + break; + + case ATON_LINK_ARITH2: + str = (const int8_t *)"ARITH2"; + break; + + case ATON_LINK_ARITH3: + str = (const int8_t *)"ARITH3"; + break; + + case ATON_LINK_POOL0: + str = (const int8_t *)"POOL0"; + break; + + case ATON_LINK_POOL1: + str = (const int8_t *)"POOL1"; + break; + + case ATON_LINK_RECBUF00: + str = (const int8_t *)"RECBUF00"; + break; + + case ATON_LINK_RECBUF01: + str = (const int8_t *)"RECBUF01"; + break; + + case ATON_LINK_RECBUF02: + str = (const int8_t *)"RECBUF02"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the LINK set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the LINK set of enumerated values + */ + +static inline const int8_t *ATON_LINK_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_LINK_STRENG0: + str = (const int8_t *)"Stream Engine 0"; + break; + + case ATON_LINK_STRENG1: + str = (const int8_t *)"Stream Engine 1"; + break; + + case ATON_LINK_STRENG2: + str = (const int8_t *)"Stream Engine 2"; + break; + + case ATON_LINK_STRENG3: + str = (const int8_t *)"Stream Engine 3"; + break; + + case ATON_LINK_STRENG4: + str = (const int8_t *)"Stream Engine 4"; + break; + + case ATON_LINK_STRENG5: + str = (const int8_t *)"Stream Engine 5"; + break; + + case ATON_LINK_STRENG6: + str = (const int8_t *)"Stream Engine 6"; + break; + + case ATON_LINK_STRENG7: + str = (const int8_t *)"Stream Engine 7"; + break; + + case ATON_LINK_STRENG8: + str = (const int8_t *)"Stream Engine 8"; + break; + + case ATON_LINK_STRENG9: + str = (const int8_t *)"Stream Engine 9"; + break; + + case ATON_LINK_CONVACC0: + str = (const int8_t *)"Convolutional Accelerator 0"; + break; + + case ATON_LINK_CONVACC1: + str = (const int8_t *)"Convolutional Accelerator 1"; + break; + + case ATON_LINK_CONVACC2: + str = (const int8_t *)"Convolutional Accelerator 2"; + break; + + case ATON_LINK_CONVACC3: + str = (const int8_t *)"Convolutional Accelerator 3"; + break; + + case ATON_LINK_DECUN0: + str = (const int8_t *)"Decompression Unit 0"; + break; + + case ATON_LINK_DECUN1: + str = (const int8_t *)"Decompression Unit 1"; + break; + + case ATON_LINK_ACTIV0: + str = (const int8_t *)"Activation Accelerator 0"; + break; + + case ATON_LINK_ACTIV1: + str = (const int8_t *)"Activation Accelerator 1"; + break; + + case ATON_LINK_ARITH0: + str = (const int8_t *)"Arithmetic Accelerator 0"; + break; + + case ATON_LINK_ARITH1: + str = (const int8_t *)"Arithmetic Accelerator 1"; + break; + + case ATON_LINK_ARITH2: + str = (const int8_t *)"Arithmetic Accelerator 2"; + break; + + case ATON_LINK_ARITH3: + str = (const int8_t *)"Arithmetic Accelerator 3"; + break; + + case ATON_LINK_POOL0: + str = (const int8_t *)"Pooling Accelerator 0"; + break; + + case ATON_LINK_POOL1: + str = (const int8_t *)"Pooling Accelerator 1"; + break; + + case ATON_LINK_RECBUF00: + str = (const int8_t *)"Reconfigurable Buffer 0 port 0"; + break; + + case ATON_LINK_RECBUF01: + str = (const int8_t *)"Reconfigurable Buffer 0 port 1"; + break; + + case ATON_LINK_RECBUF02: + str = (const int8_t *)"Reconfigurable Buffer 0 port 2"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* POOLTYPE set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Pool operation type: Max pooling. */ +#define ATON_POOLTYPE_MAX_POOLING (0x0UL) + +/** Pool operation type: Min pooling. */ +#define ATON_POOLTYPE_MIN_POOLING (0x1UL) + +/** Pool operation type: Average pooling. */ +#define ATON_POOLTYPE_AVG_POOLING (0x2UL) + +/** Pool operation type: Global max pooling. */ +#define ATON_POOLTYPE_GMAX_POOLING (0x8UL) + +/** Pool operation type: Global min pooling. */ +#define ATON_POOLTYPE_GMIN_POOLING (0x9UL) + +/** Pool operation type: Global average pooling. */ +#define ATON_POOLTYPE_GAVG_POOLING (0xaUL) + + +/** Get the name of one of the values of the POOLTYPE set of enumerated values. */ +#define ATON_POOLTYPE_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "MAX_POOLING" : \ + (((VALUE) == 1UL) ? "MIN_POOLING" : \ + (((VALUE) == 2UL) ? "AVG_POOLING" : \ + (((VALUE) == 8UL) ? "GMAX_POOLING" : \ + (((VALUE) == 9UL) ? "GMIN_POOLING" : \ + (((VALUE) == 10UL) ? "GAVG_POOLING" : "")))))) + + +/** + * Check if a value of the POOLTYPE set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the POOLTYPE set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_POOLTYPE_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_POOLTYPE_MAX_POOLING: + case ATON_POOLTYPE_MIN_POOLING: + case ATON_POOLTYPE_AVG_POOLING: + case ATON_POOLTYPE_GMAX_POOLING: + case ATON_POOLTYPE_GMIN_POOLING: + case ATON_POOLTYPE_GAVG_POOLING: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the POOLTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the POOLTYPE set of enumerated values + */ + +static inline const int8_t *ATON_POOLTYPE_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_POOLTYPE_MAX_POOLING: + str = (const int8_t *)"MAX_POOLING"; + break; + + case ATON_POOLTYPE_MIN_POOLING: + str = (const int8_t *)"MIN_POOLING"; + break; + + case ATON_POOLTYPE_AVG_POOLING: + str = (const int8_t *)"AVG_POOLING"; + break; + + case ATON_POOLTYPE_GMAX_POOLING: + str = (const int8_t *)"GMAX_POOLING"; + break; + + case ATON_POOLTYPE_GMIN_POOLING: + str = (const int8_t *)"GMIN_POOLING"; + break; + + case ATON_POOLTYPE_GAVG_POOLING: + str = (const int8_t *)"GAVG_POOLING"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the POOLTYPE set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the POOLTYPE set of enumerated values + */ + +static inline const int8_t *ATON_POOLTYPE_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_POOLTYPE_MAX_POOLING: + str = (const int8_t *)"Max pooling"; + break; + + case ATON_POOLTYPE_MIN_POOLING: + str = (const int8_t *)"Min pooling"; + break; + + case ATON_POOLTYPE_AVG_POOLING: + str = (const int8_t *)"Average pooling"; + break; + + case ATON_POOLTYPE_GMAX_POOLING: + str = (const int8_t *)"Global max pooling"; + break; + + case ATON_POOLTYPE_GMIN_POOLING: + str = (const int8_t *)"Global min pooling"; + break; + + case ATON_POOLTYPE_GAVG_POOLING: + str = (const int8_t *)"Global average pooling"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* SIGN set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Signed/unsigned activations: unsigned activations. */ +#define ATON_SIGN_UNSIGNED (0x0UL) + +/** Signed/unsigned activations: signed activations. */ +#define ATON_SIGN_SIGNED (0x1UL) + + +/** Get the name of one of the values of the SIGN set of enumerated values. */ +#define ATON_SIGN_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "UNSIGNED" : \ + (((VALUE) == 1UL) ? "SIGNED" : "")) + + +/** + * Check if a value of the SIGN set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the SIGN set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_SIGN_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_SIGN_UNSIGNED: + case ATON_SIGN_SIGNED: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the SIGN set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the SIGN set of enumerated values + */ + +static inline const int8_t *ATON_SIGN_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_SIGN_UNSIGNED: + str = (const int8_t *)"UNSIGNED"; + break; + + case ATON_SIGN_SIGNED: + str = (const int8_t *)"SIGNED"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the SIGN set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the SIGN set of enumerated values + */ + +static inline const int8_t *ATON_SIGN_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_SIGN_UNSIGNED: + str = (const int8_t *)"unsigned activations"; + break; + + case ATON_SIGN_SIGNED: + str = (const int8_t *)"signed activations"; + break; + + default: + break; + } + + return str; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* STRENGDIR set of enumerated values */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Direction: Bus to Stream Engine direction. */ +#define ATON_STRENGDIR_BUS2STR (0x0UL) + +/** Direction: Stream Engine to bus direction. */ +#define ATON_STRENGDIR_STR2BUS (0x1UL) + + +/** Get the name of one of the values of the STRENGDIR set of enumerated values. */ +#define ATON_STRENGDIR_GET_NAME(VALUE) \ + (((VALUE) == 0UL) ? "BUS2STR" : \ + (((VALUE) == 1UL) ? "STR2BUS" : "")) + + +/** + * Check if a value of the STRENGDIR set of enumerated values is valid. + * + * \param[in] val is the numeric value that must be checked + * + * \retval \e true if \e val is a valid value of the STRENGDIR set of enumerated values is valid + * \retval \e false otherwise + */ + +static inline bool ATON_STRENGDIR_IsValid(uint8_t val) +{ + bool retval = false; + + switch (val) + { + case ATON_STRENGDIR_BUS2STR: + case ATON_STRENGDIR_STR2BUS: + retval = true; + break; + + default: + break; + } + + return retval; +} + + +/** + * Get the name of one of the values of the STRENGDIR set of enumerated values. + * + * \param[in] val is the numeric value whose name must be returned + * + * \return the name of value \e val of the STRENGDIR set of enumerated values + */ + +static inline const int8_t *ATON_STRENGDIR_GetName(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_STRENGDIR_BUS2STR: + str = (const int8_t *)"BUS2STR"; + break; + + case ATON_STRENGDIR_STR2BUS: + str = (const int8_t *)"STR2BUS"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the values of the STRENGDIR set of enumerated values. + * + * \param[in] val is the numeric value whose description must be returned + * + * \return the description of value \e val of the STRENGDIR set of enumerated values + */ + +static inline const int8_t *ATON_STRENGDIR_GetDesc(uint8_t val) +{ + const int8_t *str = NULL; + + switch (val) + { + case ATON_STRENGDIR_BUS2STR: + str = (const int8_t *)"Bus to Stream Engine direction"; + break; + + case ATON_STRENGDIR_STR2BUS: + str = (const int8_t *)"Stream Engine to bus direction"; + break; + + default: + break; + } + + return str; +} + + +/* ********************************************************************************************************************************************************** */ +/* */ +/* ATON */ +/* */ +/* ********************************************************************************************************************************************************** */ + +#ifndef ATON_BASE + +#warning "Using default value of ATON_BASE" + + +/** Base address of the ATON address space (this will not be redefined if already defined). */ +#define ATON_BASE 0x00010000UL + +#endif + + +/** Size in bytes of the ATON address space. */ +#define ATON_SIZE 0x20000UL + + +/** + * Get the base address of the ATON address space. + */ + +static inline uint32_t ATON_GetBase(void) +{ + return ATON_BASE; +} + + +/** + * Get the size in bytes of the ATON address space. + */ + +static inline uint32_t ATON_GetSize(void) +{ + return ATON_SIZE; +} + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* CLOCKS */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** + * \name Clocks + */ + +/*@{*/ + +#define ATON_CLK_CLKA_NR 4 + +#define ATON_INTCTRL_CLK_CLKA 0 +#define ATON_BUSIF0_CLK_CLKA 1 +#define ATON_BUSIF1_CLK_CLKA 2 +#define ATON_STRSWITCH_CLK_CLKA 3 + +#define ATON_CLK_CLKB_NR 27 + +#define ATON_STRENG0_CLK_CLKB 0 +#define ATON_STRENG1_CLK_CLKB 1 +#define ATON_STRENG2_CLK_CLKB 2 +#define ATON_STRENG3_CLK_CLKB 3 +#define ATON_STRENG4_CLK_CLKB 4 +#define ATON_STRENG5_CLK_CLKB 5 +#define ATON_STRENG6_CLK_CLKB 6 +#define ATON_STRENG7_CLK_CLKB 7 +#define ATON_STRENG8_CLK_CLKB 8 +#define ATON_STRENG9_CLK_CLKB 9 +#define ATON_CONVACC0_CLK_CLKB 10 +#define ATON_CONVACC1_CLK_CLKB 11 +#define ATON_CONVACC2_CLK_CLKB 12 +#define ATON_CONVACC3_CLK_CLKB 13 +#define ATON_DECUN0_CLK_CLKB 14 +#define ATON_DECUN1_CLK_CLKB 15 +#define ATON_ACTIV0_CLK_CLKB 16 +#define ATON_ACTIV1_CLK_CLKB 17 +#define ATON_ARITH0_CLK_CLKB 18 +#define ATON_ARITH1_CLK_CLKB 19 +#define ATON_ARITH2_CLK_CLKB 20 +#define ATON_ARITH3_CLK_CLKB 21 +#define ATON_POOL0_CLK_CLKB 22 +#define ATON_POOL1_CLK_CLKB 23 +#define ATON_RECBUF0_CLK_CLKB 24 +#define ATON_EPOCHCTRL0_CLK_CLKB 25 +#define ATON_DEBUG_TRACE0_CLK_CLKB 26 + + +/** + * Return the mask of the CLKA clock of a CLKCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_CLKCTRL_NUM is the CLKCTRL instance index, otherwise if this value is equal to #ATON_CLKCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single CLKCTRL instance if \e UNIT is smaller than #ATON_CLKCTRL_NUM + * \retval the mask of CLKA clock of all CLKCTRL instances if \e UNIT is equal to #ATON_CLKCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_CLKCTRL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a CLKCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_CLKCTRL_NUM is the CLKCTRL instance index, otherwise if this value is equal to #ATON_CLKCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single CLKCTRL instance if \e UNIT is smaller than #ATON_CLKCTRL_NUM + * \retval the mask of CLKB clock of all CLKCTRL instances if \e UNIT is equal to #ATON_CLKCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_CLKCTRL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKA clock of a INTCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_INTCTRL_NUM is the INTCTRL instance index, otherwise if this value is equal to #ATON_INTCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single INTCTRL instance if \e UNIT is smaller than #ATON_INTCTRL_NUM + * \retval the mask of CLKA clock of all INTCTRL instances if \e UNIT is equal to #ATON_INTCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_INTCTRL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000001UL : \ + 0x00000000UL) + + +/** + * Return the mask of the CLKB clock of a INTCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_INTCTRL_NUM is the INTCTRL instance index, otherwise if this value is equal to #ATON_INTCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single INTCTRL instance if \e UNIT is smaller than #ATON_INTCTRL_NUM + * \retval the mask of CLKB clock of all INTCTRL instances if \e UNIT is equal to #ATON_INTCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_INTCTRL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKA clock of a ACTIV Unit. + * + * \param[in] UNIT if smaller than #ATON_ACTIV_NUM is the ACTIV instance index, otherwise if this value is equal to #ATON_ACTIV_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single ACTIV instance if \e UNIT is smaller than #ATON_ACTIV_NUM + * \retval the mask of CLKA clock of all ACTIV instances if \e UNIT is equal to #ATON_ACTIV_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_ACTIV_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a ACTIV Unit. + * + * \param[in] UNIT if smaller than #ATON_ACTIV_NUM is the ACTIV instance index, otherwise if this value is equal to #ATON_ACTIV_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single ACTIV instance if \e UNIT is smaller than #ATON_ACTIV_NUM + * \retval the mask of CLKB clock of all ACTIV instances if \e UNIT is equal to #ATON_ACTIV_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_ACTIV_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00010000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00020000UL : \ + 0x00000000UL)) + + +/** + * Return the mask of the CLKA clock of a ARITH Unit. + * + * \param[in] UNIT if smaller than #ATON_ARITH_NUM is the ARITH instance index, otherwise if this value is equal to #ATON_ARITH_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single ARITH instance if \e UNIT is smaller than #ATON_ARITH_NUM + * \retval the mask of CLKA clock of all ARITH instances if \e UNIT is equal to #ATON_ARITH_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_ARITH_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a ARITH Unit. + * + * \param[in] UNIT if smaller than #ATON_ARITH_NUM is the ARITH instance index, otherwise if this value is equal to #ATON_ARITH_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single ARITH instance if \e UNIT is smaller than #ATON_ARITH_NUM + * \retval the mask of CLKB clock of all ARITH instances if \e UNIT is equal to #ATON_ARITH_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_ARITH_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00040000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00080000UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x00100000UL : \ + (((REG_IDX == 0) && (UNIT == 3)) ? 0x00200000UL : \ + 0x00000000UL)))) + + +/** + * Return the mask of the CLKA clock of a POOL Unit. + * + * \param[in] UNIT if smaller than #ATON_POOL_NUM is the POOL instance index, otherwise if this value is equal to #ATON_POOL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single POOL instance if \e UNIT is smaller than #ATON_POOL_NUM + * \retval the mask of CLKA clock of all POOL instances if \e UNIT is equal to #ATON_POOL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_POOL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a POOL Unit. + * + * \param[in] UNIT if smaller than #ATON_POOL_NUM is the POOL instance index, otherwise if this value is equal to #ATON_POOL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single POOL instance if \e UNIT is smaller than #ATON_POOL_NUM + * \retval the mask of CLKB clock of all POOL instances if \e UNIT is equal to #ATON_POOL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_POOL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00400000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00800000UL : \ + 0x00000000UL)) + + +/** + * Return the mask of the CLKA clock of a BUSIF Unit. + * + * \param[in] UNIT if smaller than #ATON_BUSIF_NUM is the BUSIF instance index, otherwise if this value is equal to #ATON_BUSIF_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single BUSIF instance if \e UNIT is smaller than #ATON_BUSIF_NUM + * \retval the mask of CLKA clock of all BUSIF instances if \e UNIT is equal to #ATON_BUSIF_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_BUSIF_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000002UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000004UL : \ + 0x00000000UL)) + + +/** + * Return the mask of the CLKB clock of a BUSIF Unit. + * + * \param[in] UNIT if smaller than #ATON_BUSIF_NUM is the BUSIF instance index, otherwise if this value is equal to #ATON_BUSIF_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single BUSIF instance if \e UNIT is smaller than #ATON_BUSIF_NUM + * \retval the mask of CLKB clock of all BUSIF instances if \e UNIT is equal to #ATON_BUSIF_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_BUSIF_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKA clock of a STRENG Unit. + * + * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM + * \retval the mask of CLKA clock of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRENG_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a STRENG Unit. + * + * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM + * \retval the mask of CLKB clock of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRENG_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000001UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000002UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x00000004UL : \ + (((REG_IDX == 0) && (UNIT == 3)) ? 0x00000008UL : \ + (((REG_IDX == 0) && (UNIT == 4)) ? 0x00000010UL : \ + (((REG_IDX == 0) && (UNIT == 5)) ? 0x00000020UL : \ + (((REG_IDX == 0) && (UNIT == 6)) ? 0x00000040UL : \ + (((REG_IDX == 0) && (UNIT == 7)) ? 0x00000080UL : \ + (((REG_IDX == 0) && (UNIT == 8)) ? 0x00000100UL : \ + (((REG_IDX == 0) && (UNIT == 9)) ? 0x00000200UL : \ + 0x00000000UL)))))))))) + + +/** + * Return the mask of the CLKA clock of a STRSWITCH Unit. + * + * \param[in] UNIT if smaller than #ATON_STRSWITCH_NUM is the STRSWITCH instance index, otherwise if this value is equal to #ATON_STRSWITCH_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single STRSWITCH instance if \e UNIT is smaller than #ATON_STRSWITCH_NUM + * \retval the mask of CLKA clock of all STRSWITCH instances if \e UNIT is equal to #ATON_STRSWITCH_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRSWITCH_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000008UL : \ + 0x00000000UL) + + +/** + * Return the mask of the CLKB clock of a STRSWITCH Unit. + * + * \param[in] UNIT if smaller than #ATON_STRSWITCH_NUM is the STRSWITCH instance index, otherwise if this value is equal to #ATON_STRSWITCH_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single STRSWITCH instance if \e UNIT is smaller than #ATON_STRSWITCH_NUM + * \retval the mask of CLKB clock of all STRSWITCH instances if \e UNIT is equal to #ATON_STRSWITCH_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRSWITCH_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKA clock of a CONVACC Unit. + * + * \param[in] UNIT if smaller than #ATON_CONVACC_NUM is the CONVACC instance index, otherwise if this value is equal to #ATON_CONVACC_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single CONVACC instance if \e UNIT is smaller than #ATON_CONVACC_NUM + * \retval the mask of CLKA clock of all CONVACC instances if \e UNIT is equal to #ATON_CONVACC_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_CONVACC_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a CONVACC Unit. + * + * \param[in] UNIT if smaller than #ATON_CONVACC_NUM is the CONVACC instance index, otherwise if this value is equal to #ATON_CONVACC_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single CONVACC instance if \e UNIT is smaller than #ATON_CONVACC_NUM + * \retval the mask of CLKB clock of all CONVACC instances if \e UNIT is equal to #ATON_CONVACC_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_CONVACC_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000400UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000800UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x00001000UL : \ + (((REG_IDX == 0) && (UNIT == 3)) ? 0x00002000UL : \ + 0x00000000UL)))) + + +/** + * Return the mask of the CLKA clock of a DECUN Unit. + * + * \param[in] UNIT if smaller than #ATON_DECUN_NUM is the DECUN instance index, otherwise if this value is equal to #ATON_DECUN_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single DECUN instance if \e UNIT is smaller than #ATON_DECUN_NUM + * \retval the mask of CLKA clock of all DECUN instances if \e UNIT is equal to #ATON_DECUN_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_DECUN_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a DECUN Unit. + * + * \param[in] UNIT if smaller than #ATON_DECUN_NUM is the DECUN instance index, otherwise if this value is equal to #ATON_DECUN_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single DECUN instance if \e UNIT is smaller than #ATON_DECUN_NUM + * \retval the mask of CLKB clock of all DECUN instances if \e UNIT is equal to #ATON_DECUN_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_DECUN_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00004000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00008000UL : \ + 0x00000000UL)) + + +/** + * Return the mask of the CLKA clock of a RECBUF Unit. + * + * \param[in] UNIT if smaller than #ATON_RECBUF_NUM is the RECBUF instance index, otherwise if this value is equal to #ATON_RECBUF_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single RECBUF instance if \e UNIT is smaller than #ATON_RECBUF_NUM + * \retval the mask of CLKA clock of all RECBUF instances if \e UNIT is equal to #ATON_RECBUF_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_RECBUF_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a RECBUF Unit. + * + * \param[in] UNIT if smaller than #ATON_RECBUF_NUM is the RECBUF instance index, otherwise if this value is equal to #ATON_RECBUF_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single RECBUF instance if \e UNIT is smaller than #ATON_RECBUF_NUM + * \retval the mask of CLKB clock of all RECBUF instances if \e UNIT is equal to #ATON_RECBUF_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_RECBUF_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x01000000UL : \ + 0x00000000UL) + + +/** + * Return the mask of the CLKA clock of a EPOCHCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM + * \retval the mask of CLKA clock of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_EPOCHCTRL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a EPOCHCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM + * \retval the mask of CLKB clock of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_EPOCHCTRL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x02000000UL : \ + 0x00000000UL) + + +/** + * Return the mask of the CLKA clock of a DEBUG_TRACE Unit. + * + * \param[in] UNIT if smaller than #ATON_DEBUG_TRACE_NUM is the DEBUG_TRACE instance index, otherwise if this value is equal to #ATON_DEBUG_TRACE_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKA clock of a single DEBUG_TRACE instance if \e UNIT is smaller than #ATON_DEBUG_TRACE_NUM + * \retval the mask of CLKA clock of all DEBUG_TRACE instances if \e UNIT is equal to #ATON_DEBUG_TRACE_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_DEBUG_TRACE_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ + 0x00000000UL + + +/** + * Return the mask of the CLKB clock of a DEBUG_TRACE Unit. + * + * \param[in] UNIT if smaller than #ATON_DEBUG_TRACE_NUM is the DEBUG_TRACE instance index, otherwise if this value is equal to #ATON_DEBUG_TRACE_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 + * + * \retval the mask of CLKB clock of a single DEBUG_TRACE instance if \e UNIT is smaller than #ATON_DEBUG_TRACE_NUM + * \retval the mask of CLKB clock of all DEBUG_TRACE instances if \e UNIT is equal to #ATON_DEBUG_TRACE_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_DEBUG_TRACE_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x04000000UL : \ + 0x00000000UL) + +/*@}*/ + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* INTERRUPTS */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** + * \name Interrupts + */ + +/*@{*/ + +#define ATON_INT_NR 32 + +#define ATON_STRENG0_INT 0 +#define ATON_STRENG1_INT 1 +#define ATON_STRENG2_INT 2 +#define ATON_STRENG3_INT 3 +#define ATON_STRENG4_INT 4 +#define ATON_STRENG5_INT 5 +#define ATON_STRENG6_INT 6 +#define ATON_STRENG7_INT 7 +#define ATON_STRENG8_INT 8 +#define ATON_STRENG9_INT 9 +#define ATON_STRENG0_ERR_INT 10 +#define ATON_STRENG1_ERR_INT 11 +#define ATON_STRENG2_ERR_INT 12 +#define ATON_STRENG3_ERR_INT 13 +#define ATON_STRENG4_ERR_INT 14 +#define ATON_STRENG5_ERR_INT 15 +#define ATON_STRENG6_ERR_INT 16 +#define ATON_STRENG7_ERR_INT 17 +#define ATON_STRENG8_ERR_INT 18 +#define ATON_STRENG9_ERR_INT 19 +#define ATON_CONVACC0_INT 20 +#define ATON_CONVACC1_INT 21 +#define ATON_CONVACC2_INT 22 +#define ATON_CONVACC3_INT 23 +#define ATON_RECBUF0_INT 24 +#define ATON_BUSIF0_INT 25 +#define ATON_BUSIF1_INT 26 +#define ATON_STRSWITCH_INT 27 +#define ATON_EPOCHCTRL0_INT 28 +#define ATON_EPOCHCTRL0_NOACK_INT 29 +#define ATON_EPOCHCTRL0_ERR_INT 30 +#define ATON_DEBUG_TRACE0_INT 31 + + +/** + * Return the interrupt mask of a BUSIF Unit. + * + * \param[in] UNIT if smaller than #ATON_BUSIF_NUM is the BUSIF instance index, otherwise if this value is equal to #ATON_BUSIF_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single BUSIF instance if \e UNIT is smaller than #ATON_BUSIF_NUM + * \retval the interrupt mask of all BUSIF instances if \e UNIT is equal to #ATON_BUSIF_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_BUSIF_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x02000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x04000000UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x06000000UL : \ + 0x00000000UL))) + + +/** + * Return the interrupt mask of a STRENG Unit. + * + * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM + * \retval the interrupt mask of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRENG_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000001UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000002UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x00000004UL : \ + (((REG_IDX == 0) && (UNIT == 3)) ? 0x00000008UL : \ + (((REG_IDX == 0) && (UNIT == 4)) ? 0x00000010UL : \ + (((REG_IDX == 0) && (UNIT == 5)) ? 0x00000020UL : \ + (((REG_IDX == 0) && (UNIT == 6)) ? 0x00000040UL : \ + (((REG_IDX == 0) && (UNIT == 7)) ? 0x00000080UL : \ + (((REG_IDX == 0) && (UNIT == 8)) ? 0x00000100UL : \ + (((REG_IDX == 0) && (UNIT == 9)) ? 0x00000200UL : \ + (((REG_IDX == 0) && (UNIT == 10)) ? 0x000003ffUL : \ + 0x00000000UL))))))))))) + + +/** + * Return the interrupt mask of a STRENG Unit. + * + * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM + * \retval the interrupt mask of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRENG_ERR_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000400UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000800UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x00001000UL : \ + (((REG_IDX == 0) && (UNIT == 3)) ? 0x00002000UL : \ + (((REG_IDX == 0) && (UNIT == 4)) ? 0x00004000UL : \ + (((REG_IDX == 0) && (UNIT == 5)) ? 0x00008000UL : \ + (((REG_IDX == 0) && (UNIT == 6)) ? 0x00010000UL : \ + (((REG_IDX == 0) && (UNIT == 7)) ? 0x00020000UL : \ + (((REG_IDX == 0) && (UNIT == 8)) ? 0x00040000UL : \ + (((REG_IDX == 0) && (UNIT == 9)) ? 0x00080000UL : \ + (((REG_IDX == 0) && (UNIT == 10)) ? 0x000ffc00UL : \ + 0x00000000UL))))))))))) + + +/** + * Return the interrupt mask of a STRSWITCH Unit. + * + * \param[in] UNIT if smaller than #ATON_STRSWITCH_NUM is the STRSWITCH instance index, otherwise if this value is equal to #ATON_STRSWITCH_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single STRSWITCH instance if \e UNIT is smaller than #ATON_STRSWITCH_NUM + * \retval the interrupt mask of all STRSWITCH instances if \e UNIT is equal to #ATON_STRSWITCH_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_STRSWITCH_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x08000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x08000000UL : \ + 0x00000000UL)) + + +/** + * Return the interrupt mask of a CONVACC Unit. + * + * \param[in] UNIT if smaller than #ATON_CONVACC_NUM is the CONVACC instance index, otherwise if this value is equal to #ATON_CONVACC_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single CONVACC instance if \e UNIT is smaller than #ATON_CONVACC_NUM + * \retval the interrupt mask of all CONVACC instances if \e UNIT is equal to #ATON_CONVACC_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_CONVACC_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x00100000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x00200000UL : \ + (((REG_IDX == 0) && (UNIT == 2)) ? 0x00400000UL : \ + (((REG_IDX == 0) && (UNIT == 3)) ? 0x00800000UL : \ + (((REG_IDX == 0) && (UNIT == 4)) ? 0x00f00000UL : \ + 0x00000000UL))))) + + +/** + * Return the interrupt mask of a RECBUF Unit. + * + * \param[in] UNIT if smaller than #ATON_RECBUF_NUM is the RECBUF instance index, otherwise if this value is equal to #ATON_RECBUF_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single RECBUF instance if \e UNIT is smaller than #ATON_RECBUF_NUM + * \retval the interrupt mask of all RECBUF instances if \e UNIT is equal to #ATON_RECBUF_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_RECBUF_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x01000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x01000000UL : \ + 0x00000000UL)) + + +/** + * Return the interrupt mask of a EPOCHCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM + * \retval the interrupt mask of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_EPOCHCTRL_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x10000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x10000000UL : \ + 0x00000000UL)) + + +/** + * Return the interrupt mask of a EPOCHCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM + * \retval the interrupt mask of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_EPOCHCTRL_NOACK_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x20000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x20000000UL : \ + 0x00000000UL)) + + +/** + * Return the interrupt mask of a EPOCHCTRL Unit. + * + * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM + * \retval the interrupt mask of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_EPOCHCTRL_ERR_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x40000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x40000000UL : \ + 0x00000000UL)) + + +/** + * Return the interrupt mask of a DEBUG_TRACE Unit. + * + * \param[in] UNIT if smaller than #ATON_DEBUG_TRACE_NUM is the DEBUG_TRACE instance index, otherwise if this value is equal to #ATON_DEBUG_TRACE_NUM it indicates + * that all instances will be considered + * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 + * + * \retval the interrupt mask of a single DEBUG_TRACE instance if \e UNIT is smaller than #ATON_DEBUG_TRACE_NUM + * \retval the interrupt mask of all DEBUG_TRACE instances if \e UNIT is equal to #ATON_DEBUG_TRACE_NUM + * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed + */ + +#define ATON_DEBUG_TRACE_INT_GET_MASK(UNIT, REG_IDX) \ + (((REG_IDX == 0) && (UNIT == 0)) ? 0x80000000UL : \ + (((REG_IDX == 0) && (UNIT == 1)) ? 0x80000000UL : \ + 0x00000000UL)) + +/*@}*/ + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* CLKCTRL Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of CLKCTRL Unit instances. */ +#define ATON_CLKCTRL_NUM 1 + +/** + * \name Structures, macros and functions of the CLKCTRL Units + */ +/*@{*/ + +/** + * Registers of the CLKCTRL Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e AGATES0 register (Clock enable bits). */ + uint32_t AGATES0; + + /** \e AGATES1 register (Copy of AGATES0 register). */ + uint32_t AGATES1; + + /** \e BGATES register (Clock enable bits register for B clocks). */ + uint32_t BGATES; + +} ATON_CLKCTRL_t; + + +/** Return the pointer to one of the CLKCTRL Units. */ +#define ATON_CLKCTRL(UNIT) ((ATON_CLKCTRL_t *)(intptr_t)ATON_CLKCTRL_BASE(UNIT)) + + +/** Name of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_NAME(UNIT) \ + (((UNIT) == 0) ? "CLKCTRL" : "") + + +/** Version of the CLKCTRL Units. */ +#define ATON_CLKCTRL_VERSION "1.2" + + +/** Description of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_DESC(UNIT) \ + (((UNIT) == 0) ? "Clock Controller" : "") + + +/** Base address of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_BASE(UNIT) \ + (ATON_BASE + 0x0UL + ((UNIT) * 0x0UL)) + +/** Size in bytes of the CLKCTRL Units. */ +#define ATON_CLKCTRL_SIZE 0x1000UL + + +/** + * Get the name of one of the CLKCTRL Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) + * + * \return the name of Unit having index \e instance among the CLKCTRL Units + */ + +static inline const int8_t *ATON_CLKCTRL_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"CLKCTRL"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the CLKCTRL Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) + * + * \return the description of Unit having index \e instance among the CLKCTRL Units + */ + +static inline const int8_t *ATON_CLKCTRL_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Clock Controller"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the CLKCTRL Units. + * + * \return the version of the CLKCTRL Units + */ + +static inline const int8_t *ATON_CLKCTRL_GetVersion(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION; +} + + +/** + * Get the base address of one of the CLKCTRL Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) + * + * \return the base address of Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_GetBase(uint32_t instance) +{ + return ATON_CLKCTRL_BASE(instance); +} + + +/** + * Get the size in bytes of the CLKCTRL Units. + * + * \return the size in bytes of the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_GetSize(void) +{ + return ATON_CLKCTRL_SIZE; +} + + +/* ******************************************************* CTRL register of one of the CLKCTRL Units ******************************************************** */ + +/** Offset of the CTRL register from the base address of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_CTRL_DT \ + (ATON_CLKCTRL_CTRL_EN_DT << ATON_CLKCTRL_CTRL_EN_LSB) | \ + (ATON_CLKCTRL_CTRL_CLR_DT << ATON_CLKCTRL_CTRL_CLR_LSB) | \ + (ATON_CLKCTRL_CTRL_FREEZEREQ_DT << ATON_CLKCTRL_CTRL_FREEZEREQ_LSB) | \ + (ATON_CLKCTRL_CTRL_FREEZEGNT_DT << ATON_CLKCTRL_CTRL_FREEZEGNT_LSB) | \ + (ATON_CLKCTRL_CTRL_CONFCLR_DT << ATON_CLKCTRL_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_CTRL_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_CLKCTRL_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_GetOffset(void) +{ + return ATON_CLKCTRL_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the CTRL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_GetAddr(uint32_t instance) +{ + return ATON_CLKCTRL_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Get(uint32_t instance) +{ + return ATON_CLKCTRL_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the CTRL register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CLKCTRL_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_CLKCTRL_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_EN_DESC "Enable the Clock Control Unit" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_CLKCTRL_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_CLKCTRL_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_EN_LSB, ATON_CLKCTRL_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_EN_LSB, ATON_CLKCTRL_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_CLKCTRL_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Get_EN(uint32_t reg) +{ + return ATON_CLKCTRL_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_CLKCTRL_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_CLKCTRL_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_CLR_LSB, ATON_CLKCTRL_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_CLR_LSB, ATON_CLKCTRL_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_CLKCTRL_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_CLKCTRL_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_CTRL_SET_CLR(reg, data); +} + + +/* ---------------------------------------------------------- FREEZEREQ field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_DESC "Request bus access freeze" + +/** Offset of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_LSB 2UL + +/** Size in bits of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_W (1UL) + +/** Mask for retrieving the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_DT 0x0UL + +/** Access rights of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_AC "RW" + +/** Check whether access to the FREEZEREQ field of the CTRL register is secured or not. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_S 0 + +/** Check whether access to the FREEZEREQ field of the CTRL register is privileged or not. */ +#define ATON_CLKCTRL_CTRL_FREEZEREQ_P 0 + +/** Read the content of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_GET_FREEZEREQ(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_FREEZEREQ_LSB, ATON_CLKCTRL_CTRL_FREEZEREQ_W) + +/** Modify the content of the FREEZEREQ field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_SET_FREEZEREQ(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_FREEZEREQ_LSB, ATON_CLKCTRL_CTRL_FREEZEREQ_W, DATA) + + +/** + * Get the description of the FREEZEREQ field of CTRL register. + * + * \return the description of the FREEZEREQ field of CTRL register + */ + +static inline const int8_t *ATON_CLKCTRL_CTRL_FREEZEREQ_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_CTRL_FREEZEREQ_DESC; +} + + +/** + * Read the content of the FREEZEREQ field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FREEZEREQ field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Get_FREEZEREQ(uint32_t reg) +{ + return ATON_CLKCTRL_CTRL_GET_FREEZEREQ(reg); +} + + +/** + * Write the content of the FREEZEREQ field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FREEZEREQ field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Set_FREEZEREQ(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_CTRL_SET_FREEZEREQ(reg, data); +} + + +/* ---------------------------------------------------------- FREEZEGNT field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_DESC "Freeze request grant" + +/** Offset of the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_LSB 3UL + +/** Size in bits of the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_W (1UL) + +/** Mask for retrieving the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_DT 0x0UL + +/** Access rights of the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_AC "R" + +/** Check whether access to the FREEZEGNT field of the CTRL register is secured or not. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_S 0 + +/** Check whether access to the FREEZEGNT field of the CTRL register is privileged or not. */ +#define ATON_CLKCTRL_CTRL_FREEZEGNT_P 0 + +/** Read the content of the FREEZEGNT field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_GET_FREEZEGNT(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_FREEZEGNT_LSB, ATON_CLKCTRL_CTRL_FREEZEGNT_W) + + +/** + * Get the description of the FREEZEGNT field of CTRL register. + * + * \return the description of the FREEZEGNT field of CTRL register + */ + +static inline const int8_t *ATON_CLKCTRL_CTRL_FREEZEGNT_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_CTRL_FREEZEGNT_DESC; +} + + +/** + * Read the content of the FREEZEGNT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FREEZEGNT field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Get_FREEZEGNT(uint32_t reg) +{ + return ATON_CLKCTRL_CTRL_GET_FREEZEGNT(reg); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_CLKCTRL_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_CONFCLR_LSB, ATON_CLKCTRL_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_CLKCTRL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_CONFCLR_LSB, ATON_CLKCTRL_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_CLKCTRL_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_CLKCTRL_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CLKCTRL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_CTRL_SET_CONFCLR(reg, data); +} + + +/* ****************************************************** VERSION register of one of the CLKCTRL Units ****************************************************** */ + +/** Offset of the VERSION register from the base address of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_VERSION_DT \ + (ATON_CLKCTRL_VERSION_TYPE_DT << ATON_CLKCTRL_VERSION_TYPE_LSB) | \ + (ATON_CLKCTRL_VERSION_MINOR_DT << ATON_CLKCTRL_VERSION_MINOR_LSB) | \ + (ATON_CLKCTRL_VERSION_MAJOR_DT << ATON_CLKCTRL_VERSION_MAJOR_LSB) | \ + (ATON_CLKCTRL_VERSION_AGATES_DT << ATON_CLKCTRL_VERSION_AGATES_LSB) | \ + (ATON_CLKCTRL_VERSION_BGATES_DT << ATON_CLKCTRL_VERSION_BGATES_LSB) | \ + (ATON_CLKCTRL_VERSION_CLKDIV_DT << ATON_CLKCTRL_VERSION_CLKDIV_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_VERSION_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_GetOffset(void) +{ + return ATON_CLKCTRL_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the VERSION register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_GetAddr(uint32_t instance) +{ + return ATON_CLKCTRL_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get(uint32_t instance) +{ + return ATON_CLKCTRL_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_TYPE_DT 0x1fUL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_CLKCTRL_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_CLKCTRL_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_TYPE_LSB, ATON_CLKCTRL_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_CLKCTRL_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MINOR_DT 0x2UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_CLKCTRL_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_CLKCTRL_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_MINOR_LSB, ATON_CLKCTRL_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_CLKCTRL_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_CLKCTRL_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_CLKCTRL_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_MAJOR_LSB, ATON_CLKCTRL_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_CLKCTRL_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- AGATES field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_AGATES_DESC "Number of A Clock gates (for system blocks)" + +/** Offset of the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_AGATES_LSB 16UL + +/** Size in bits of the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_AGATES_W (4UL) + +/** Mask for retrieving the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_AGATES_MASK ATON_FIELD_MASK(16UL, 4UL) + +/** Reset value of the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_AGATES_DT 0x4UL + +/** Access rights of the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_AGATES_AC "R" + +/** Check whether access to the AGATES field of the VERSION register is secured or not. */ +#define ATON_CLKCTRL_VERSION_AGATES_S 0 + +/** Check whether access to the AGATES field of the VERSION register is privileged or not. */ +#define ATON_CLKCTRL_VERSION_AGATES_P 0 + +/** Read the content of the AGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_GET_AGATES(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_AGATES_LSB, ATON_CLKCTRL_VERSION_AGATES_W) + + +/** + * Get the description of the AGATES field of VERSION register. + * + * \return the description of the AGATES field of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_AGATES_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_AGATES_DESC; +} + + +/** + * Read the content of the AGATES field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the AGATES field belonging to VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get_AGATES(uint32_t reg) +{ + return ATON_CLKCTRL_VERSION_GET_AGATES(reg); +} + + +/* ---------------------------------------------------------- BGATES field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_BGATES_DESC "Number of B Clock gates (for functional units)" + +/** Offset of the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_BGATES_LSB 20UL + +/** Size in bits of the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_BGATES_W (8UL) + +/** Mask for retrieving the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_BGATES_MASK ATON_FIELD_MASK(20UL, 8UL) + +/** Reset value of the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_BGATES_DT 0x1bUL + +/** Access rights of the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_BGATES_AC "R" + +/** Check whether access to the BGATES field of the VERSION register is secured or not. */ +#define ATON_CLKCTRL_VERSION_BGATES_S 0 + +/** Check whether access to the BGATES field of the VERSION register is privileged or not. */ +#define ATON_CLKCTRL_VERSION_BGATES_P 0 + +/** Read the content of the BGATES field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_GET_BGATES(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_BGATES_LSB, ATON_CLKCTRL_VERSION_BGATES_W) + + +/** + * Get the description of the BGATES field of VERSION register. + * + * \return the description of the BGATES field of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_BGATES_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_BGATES_DESC; +} + + +/** + * Read the content of the BGATES field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the BGATES field belonging to VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get_BGATES(uint32_t reg) +{ + return ATON_CLKCTRL_VERSION_GET_BGATES(reg); +} + + +/* ---------------------------------------------------------- CLKDIV field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_DESC "Number of clock dividers" + +/** Offset of the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_LSB 28UL + +/** Size in bits of the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_W (4UL) + +/** Mask for retrieving the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_MASK ATON_FIELD_MASK(28UL, 4UL) + +/** Reset value of the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_DT 0x0UL + +/** Access rights of the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_AC "R" + +/** Check whether access to the CLKDIV field of the VERSION register is secured or not. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_S 0 + +/** Check whether access to the CLKDIV field of the VERSION register is privileged or not. */ +#define ATON_CLKCTRL_VERSION_CLKDIV_P 0 + +/** Read the content of the CLKDIV field of the VERSION register. */ +#define ATON_CLKCTRL_VERSION_GET_CLKDIV(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_CLKDIV_LSB, ATON_CLKCTRL_VERSION_CLKDIV_W) + + +/** + * Get the description of the CLKDIV field of VERSION register. + * + * \return the description of the CLKDIV field of VERSION register + */ + +static inline const int8_t *ATON_CLKCTRL_VERSION_CLKDIV_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_VERSION_CLKDIV_DESC; +} + + +/** + * Read the content of the CLKDIV field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the CLKDIV field belonging to VERSION register + */ + +static inline uint32_t ATON_CLKCTRL_VERSION_Get_CLKDIV(uint32_t reg) +{ + return ATON_CLKCTRL_VERSION_GET_CLKDIV(reg); +} + + +/* ****************************************************** AGATES0 register of one of the CLKCTRL Units ****************************************************** */ + +/** Offset of the AGATES0 register from the base address of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_AGATES0_OFFSET 0x8UL + +/** Reset value of the AGATES0 register of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_AGATES0_DT \ + (ATON_CLKCTRL_AGATES0_INTCTRL_DT << ATON_CLKCTRL_AGATES0_INTCTRL_LSB) | \ + (ATON_CLKCTRL_AGATES0_BUSIF0_DT << ATON_CLKCTRL_AGATES0_BUSIF0_LSB) | \ + (ATON_CLKCTRL_AGATES0_BUSIF1_DT << ATON_CLKCTRL_AGATES0_BUSIF1_LSB) | \ + (ATON_CLKCTRL_AGATES0_STRSWITCH_DT << ATON_CLKCTRL_AGATES0_STRSWITCH_LSB) + + + +/** Description of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_DESC "Clock enable bits" + +/** Address of the AGATES0 register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_AGATES0_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_AGATES0_OFFSET) + +/** Get the content of the AGATES0 register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_AGATES0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES0_ADDR(UNIT))) + +/** Set the content of the AGATES0 register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_AGATES0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of AGATES0 register. + * + * \return the description of AGATES0 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES0_GetDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES0_DESC; +} + + +/** + * Get the offset of the AGATES0 register. + * + * \return the offset of AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_GetOffset(void) +{ + return ATON_CLKCTRL_AGATES0_OFFSET; +} + + +/** + * Get the address of the AGATES0 register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of AGATES0 register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_GetAddr(uint32_t instance) +{ + return ATON_CLKCTRL_AGATES0_ADDR(instance); +} + + +/** + * Read the content of the AGATES0 register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of AGATES0 register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Get(uint32_t instance) +{ + return ATON_CLKCTRL_AGATES0_GET(instance); +} + + +/** + * Write the content of the AGATES0 register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CLKCTRL_AGATES0_Set(uint32_t instance, uint32_t data) +{ + ATON_CLKCTRL_AGATES0_SET(instance, data); +} + + +/* --------------------------------------------------------- INTCTRL field of the AGATES0 register ---------------------------------------------------------- */ + +/** Description of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_DESC "Enable clock of Interrupt Controller" + +/** Offset of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_LSB 0UL + +/** Size in bits of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_W (1UL) + +/** Mask for retrieving the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_DT 0x0UL + +/** Access rights of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_AC "RW" + +/** Check whether access to the INTCTRL field of the AGATES0 register is secured or not. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_S 0 + +/** Check whether access to the INTCTRL field of the AGATES0 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES0_INTCTRL_P 0 + +/** Read the content of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_GET_INTCTRL(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_INTCTRL_LSB, ATON_CLKCTRL_AGATES0_INTCTRL_W) + +/** Modify the content of the INTCTRL field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_SET_INTCTRL(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_INTCTRL_LSB, ATON_CLKCTRL_AGATES0_INTCTRL_W, DATA) + + +/** + * Get the description of the INTCTRL field of AGATES0 register. + * + * \return the description of the INTCTRL field of AGATES0 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES0_INTCTRL_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES0_INTCTRL_DESC; +} + + +/** + * Read the content of the INTCTRL field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * + * \return the content of the INTCTRL field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Get_INTCTRL(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES0_GET_INTCTRL(reg); +} + + +/** + * Write the content of the INTCTRL field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INTCTRL field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Set_INTCTRL(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES0_SET_INTCTRL(reg, data); +} + + +/* ---------------------------------------------------------- BUSIF0 field of the AGATES0 register ---------------------------------------------------------- */ + +/** Description of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_DESC "Enable clock of Bus Interface 0" + +/** Offset of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_LSB 1UL + +/** Size in bits of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_W (1UL) + +/** Mask for retrieving the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_DT 0x0UL + +/** Access rights of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_AC "RW" + +/** Check whether access to the BUSIF0 field of the AGATES0 register is secured or not. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_S 0 + +/** Check whether access to the BUSIF0 field of the AGATES0 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES0_BUSIF0_P 0 + +/** Read the content of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_GET_BUSIF0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF0_LSB, ATON_CLKCTRL_AGATES0_BUSIF0_W) + +/** Modify the content of the BUSIF0 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_SET_BUSIF0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF0_LSB, ATON_CLKCTRL_AGATES0_BUSIF0_W, DATA) + + +/** + * Get the description of the BUSIF0 field of AGATES0 register. + * + * \return the description of the BUSIF0 field of AGATES0 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES0_BUSIF0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES0_BUSIF0_DESC; +} + + +/** + * Read the content of the BUSIF0 field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * + * \return the content of the BUSIF0 field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Get_BUSIF0(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES0_GET_BUSIF0(reg); +} + + +/** + * Write the content of the BUSIF0 field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSIF0 field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Set_BUSIF0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES0_SET_BUSIF0(reg, data); +} + + +/* ---------------------------------------------------------- BUSIF1 field of the AGATES0 register ---------------------------------------------------------- */ + +/** Description of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_DESC "Enable clock of Bus Interface 1" + +/** Offset of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_LSB 2UL + +/** Size in bits of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_W (1UL) + +/** Mask for retrieving the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_DT 0x0UL + +/** Access rights of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_AC "RW" + +/** Check whether access to the BUSIF1 field of the AGATES0 register is secured or not. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_S 0 + +/** Check whether access to the BUSIF1 field of the AGATES0 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES0_BUSIF1_P 0 + +/** Read the content of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_GET_BUSIF1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF1_LSB, ATON_CLKCTRL_AGATES0_BUSIF1_W) + +/** Modify the content of the BUSIF1 field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_SET_BUSIF1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF1_LSB, ATON_CLKCTRL_AGATES0_BUSIF1_W, DATA) + + +/** + * Get the description of the BUSIF1 field of AGATES0 register. + * + * \return the description of the BUSIF1 field of AGATES0 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES0_BUSIF1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES0_BUSIF1_DESC; +} + + +/** + * Read the content of the BUSIF1 field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * + * \return the content of the BUSIF1 field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Get_BUSIF1(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES0_GET_BUSIF1(reg); +} + + +/** + * Write the content of the BUSIF1 field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSIF1 field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Set_BUSIF1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES0_SET_BUSIF1(reg, data); +} + + +/* -------------------------------------------------------- STRSWITCH field of the AGATES0 register --------------------------------------------------------- */ + +/** Description of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_DESC "Enable clock of Stream Switch" + +/** Offset of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_LSB 3UL + +/** Size in bits of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_W (1UL) + +/** Mask for retrieving the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_DT 0x0UL + +/** Access rights of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_AC "RW" + +/** Check whether access to the STRSWITCH field of the AGATES0 register is secured or not. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_S 0 + +/** Check whether access to the STRSWITCH field of the AGATES0 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES0_STRSWITCH_P 0 + +/** Read the content of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_GET_STRSWITCH(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_STRSWITCH_LSB, ATON_CLKCTRL_AGATES0_STRSWITCH_W) + +/** Modify the content of the STRSWITCH field of the AGATES0 register. */ +#define ATON_CLKCTRL_AGATES0_SET_STRSWITCH(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_STRSWITCH_LSB, ATON_CLKCTRL_AGATES0_STRSWITCH_W, DATA) + + +/** + * Get the description of the STRSWITCH field of AGATES0 register. + * + * \return the description of the STRSWITCH field of AGATES0 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES0_STRSWITCH_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES0_STRSWITCH_DESC; +} + + +/** + * Read the content of the STRSWITCH field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * + * \return the content of the STRSWITCH field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Get_STRSWITCH(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES0_GET_STRSWITCH(reg); +} + + +/** + * Write the content of the STRSWITCH field of the AGATES0 register. + * + * \param[in] reg is the value of the AGATES0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRSWITCH field belonging to AGATES0 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES0_Set_STRSWITCH(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES0_SET_STRSWITCH(reg, data); +} + + +/* ****************************************************** AGATES1 register of one of the CLKCTRL Units ****************************************************** */ + +/** Offset of the AGATES1 register from the base address of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_AGATES1_OFFSET 0xcUL + +/** Reset value of the AGATES1 register of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_AGATES1_DT \ + (ATON_CLKCTRL_AGATES1_INTCTRL_DT << ATON_CLKCTRL_AGATES1_INTCTRL_LSB) | \ + (ATON_CLKCTRL_AGATES1_BUSIF0_DT << ATON_CLKCTRL_AGATES1_BUSIF0_LSB) | \ + (ATON_CLKCTRL_AGATES1_BUSIF1_DT << ATON_CLKCTRL_AGATES1_BUSIF1_LSB) | \ + (ATON_CLKCTRL_AGATES1_STRSWITCH_DT << ATON_CLKCTRL_AGATES1_STRSWITCH_LSB) + + + +/** Description of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_DESC "Copy of AGATES0 register" + +/** Address of the AGATES1 register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_AGATES1_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_AGATES1_OFFSET) + +/** Get the content of the AGATES1 register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_AGATES1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES1_ADDR(UNIT))) + +/** Set the content of the AGATES1 register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_AGATES1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of AGATES1 register. + * + * \return the description of AGATES1 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES1_GetDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES1_DESC; +} + + +/** + * Get the offset of the AGATES1 register. + * + * \return the offset of AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_GetOffset(void) +{ + return ATON_CLKCTRL_AGATES1_OFFSET; +} + + +/** + * Get the address of the AGATES1 register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of AGATES1 register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_GetAddr(uint32_t instance) +{ + return ATON_CLKCTRL_AGATES1_ADDR(instance); +} + + +/** + * Read the content of the AGATES1 register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of AGATES1 register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Get(uint32_t instance) +{ + return ATON_CLKCTRL_AGATES1_GET(instance); +} + + +/** + * Write the content of the AGATES1 register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CLKCTRL_AGATES1_Set(uint32_t instance, uint32_t data) +{ + ATON_CLKCTRL_AGATES1_SET(instance, data); +} + + +/* --------------------------------------------------------- INTCTRL field of the AGATES1 register ---------------------------------------------------------- */ + +/** Description of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_DESC "Enable clock of Interrupt Controller" + +/** Offset of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_LSB 0UL + +/** Size in bits of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_W (1UL) + +/** Mask for retrieving the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_DT 0x0UL + +/** Access rights of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_AC "RW" + +/** Check whether access to the INTCTRL field of the AGATES1 register is secured or not. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_S 0 + +/** Check whether access to the INTCTRL field of the AGATES1 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES1_INTCTRL_P 0 + +/** Read the content of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_GET_INTCTRL(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_INTCTRL_LSB, ATON_CLKCTRL_AGATES1_INTCTRL_W) + +/** Modify the content of the INTCTRL field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_SET_INTCTRL(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_INTCTRL_LSB, ATON_CLKCTRL_AGATES1_INTCTRL_W, DATA) + + +/** + * Get the description of the INTCTRL field of AGATES1 register. + * + * \return the description of the INTCTRL field of AGATES1 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES1_INTCTRL_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES1_INTCTRL_DESC; +} + + +/** + * Read the content of the INTCTRL field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * + * \return the content of the INTCTRL field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Get_INTCTRL(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES1_GET_INTCTRL(reg); +} + + +/** + * Write the content of the INTCTRL field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INTCTRL field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Set_INTCTRL(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES1_SET_INTCTRL(reg, data); +} + + +/* ---------------------------------------------------------- BUSIF0 field of the AGATES1 register ---------------------------------------------------------- */ + +/** Description of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_DESC "Enable clock of Bus Interface 0" + +/** Offset of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_LSB 1UL + +/** Size in bits of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_W (1UL) + +/** Mask for retrieving the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_DT 0x0UL + +/** Access rights of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_AC "RW" + +/** Check whether access to the BUSIF0 field of the AGATES1 register is secured or not. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_S 0 + +/** Check whether access to the BUSIF0 field of the AGATES1 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES1_BUSIF0_P 0 + +/** Read the content of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_GET_BUSIF0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF0_LSB, ATON_CLKCTRL_AGATES1_BUSIF0_W) + +/** Modify the content of the BUSIF0 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_SET_BUSIF0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF0_LSB, ATON_CLKCTRL_AGATES1_BUSIF0_W, DATA) + + +/** + * Get the description of the BUSIF0 field of AGATES1 register. + * + * \return the description of the BUSIF0 field of AGATES1 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES1_BUSIF0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES1_BUSIF0_DESC; +} + + +/** + * Read the content of the BUSIF0 field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * + * \return the content of the BUSIF0 field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Get_BUSIF0(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES1_GET_BUSIF0(reg); +} + + +/** + * Write the content of the BUSIF0 field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSIF0 field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Set_BUSIF0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES1_SET_BUSIF0(reg, data); +} + + +/* ---------------------------------------------------------- BUSIF1 field of the AGATES1 register ---------------------------------------------------------- */ + +/** Description of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_DESC "Enable clock of Bus Interface 1" + +/** Offset of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_LSB 2UL + +/** Size in bits of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_W (1UL) + +/** Mask for retrieving the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_DT 0x0UL + +/** Access rights of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_AC "RW" + +/** Check whether access to the BUSIF1 field of the AGATES1 register is secured or not. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_S 0 + +/** Check whether access to the BUSIF1 field of the AGATES1 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES1_BUSIF1_P 0 + +/** Read the content of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_GET_BUSIF1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF1_LSB, ATON_CLKCTRL_AGATES1_BUSIF1_W) + +/** Modify the content of the BUSIF1 field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_SET_BUSIF1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF1_LSB, ATON_CLKCTRL_AGATES1_BUSIF1_W, DATA) + + +/** + * Get the description of the BUSIF1 field of AGATES1 register. + * + * \return the description of the BUSIF1 field of AGATES1 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES1_BUSIF1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES1_BUSIF1_DESC; +} + + +/** + * Read the content of the BUSIF1 field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * + * \return the content of the BUSIF1 field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Get_BUSIF1(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES1_GET_BUSIF1(reg); +} + + +/** + * Write the content of the BUSIF1 field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSIF1 field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Set_BUSIF1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES1_SET_BUSIF1(reg, data); +} + + +/* -------------------------------------------------------- STRSWITCH field of the AGATES1 register --------------------------------------------------------- */ + +/** Description of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_DESC "Enable clock of Stream Switch" + +/** Offset of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_LSB 3UL + +/** Size in bits of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_W (1UL) + +/** Mask for retrieving the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_DT 0x0UL + +/** Access rights of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_AC "RW" + +/** Check whether access to the STRSWITCH field of the AGATES1 register is secured or not. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_S 0 + +/** Check whether access to the STRSWITCH field of the AGATES1 register is privileged or not. */ +#define ATON_CLKCTRL_AGATES1_STRSWITCH_P 0 + +/** Read the content of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_GET_STRSWITCH(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_STRSWITCH_LSB, ATON_CLKCTRL_AGATES1_STRSWITCH_W) + +/** Modify the content of the STRSWITCH field of the AGATES1 register. */ +#define ATON_CLKCTRL_AGATES1_SET_STRSWITCH(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_STRSWITCH_LSB, ATON_CLKCTRL_AGATES1_STRSWITCH_W, DATA) + + +/** + * Get the description of the STRSWITCH field of AGATES1 register. + * + * \return the description of the STRSWITCH field of AGATES1 register + */ + +static inline const int8_t *ATON_CLKCTRL_AGATES1_STRSWITCH_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_AGATES1_STRSWITCH_DESC; +} + + +/** + * Read the content of the STRSWITCH field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * + * \return the content of the STRSWITCH field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Get_STRSWITCH(uint32_t reg) +{ + return ATON_CLKCTRL_AGATES1_GET_STRSWITCH(reg); +} + + +/** + * Write the content of the STRSWITCH field of the AGATES1 register. + * + * \param[in] reg is the value of the AGATES1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRSWITCH field belonging to AGATES1 register + */ + +static inline uint32_t ATON_CLKCTRL_AGATES1_Set_STRSWITCH(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_AGATES1_SET_STRSWITCH(reg, data); +} + + +/* ****************************************************** BGATES register of one of the CLKCTRL Units ******************************************************* */ + +/** Offset of the BGATES register from the base address of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_BGATES_OFFSET 0x10UL + +/** Reset value of the BGATES register of the CLKCTRL Unit. */ +#define ATON_CLKCTRL_BGATES_DT \ + (ATON_CLKCTRL_BGATES_STRENG0_DT << ATON_CLKCTRL_BGATES_STRENG0_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG1_DT << ATON_CLKCTRL_BGATES_STRENG1_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG2_DT << ATON_CLKCTRL_BGATES_STRENG2_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG3_DT << ATON_CLKCTRL_BGATES_STRENG3_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG4_DT << ATON_CLKCTRL_BGATES_STRENG4_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG5_DT << ATON_CLKCTRL_BGATES_STRENG5_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG6_DT << ATON_CLKCTRL_BGATES_STRENG6_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG7_DT << ATON_CLKCTRL_BGATES_STRENG7_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG8_DT << ATON_CLKCTRL_BGATES_STRENG8_LSB) | \ + (ATON_CLKCTRL_BGATES_STRENG9_DT << ATON_CLKCTRL_BGATES_STRENG9_LSB) | \ + (ATON_CLKCTRL_BGATES_CONVACC0_DT << ATON_CLKCTRL_BGATES_CONVACC0_LSB) | \ + (ATON_CLKCTRL_BGATES_CONVACC1_DT << ATON_CLKCTRL_BGATES_CONVACC1_LSB) | \ + (ATON_CLKCTRL_BGATES_CONVACC2_DT << ATON_CLKCTRL_BGATES_CONVACC2_LSB) | \ + (ATON_CLKCTRL_BGATES_CONVACC3_DT << ATON_CLKCTRL_BGATES_CONVACC3_LSB) | \ + (ATON_CLKCTRL_BGATES_DECUN0_DT << ATON_CLKCTRL_BGATES_DECUN0_LSB) | \ + (ATON_CLKCTRL_BGATES_DECUN1_DT << ATON_CLKCTRL_BGATES_DECUN1_LSB) | \ + (ATON_CLKCTRL_BGATES_ACTIV0_DT << ATON_CLKCTRL_BGATES_ACTIV0_LSB) | \ + (ATON_CLKCTRL_BGATES_ACTIV1_DT << ATON_CLKCTRL_BGATES_ACTIV1_LSB) | \ + (ATON_CLKCTRL_BGATES_ARITH0_DT << ATON_CLKCTRL_BGATES_ARITH0_LSB) | \ + (ATON_CLKCTRL_BGATES_ARITH1_DT << ATON_CLKCTRL_BGATES_ARITH1_LSB) | \ + (ATON_CLKCTRL_BGATES_ARITH2_DT << ATON_CLKCTRL_BGATES_ARITH2_LSB) | \ + (ATON_CLKCTRL_BGATES_ARITH3_DT << ATON_CLKCTRL_BGATES_ARITH3_LSB) | \ + (ATON_CLKCTRL_BGATES_POOL0_DT << ATON_CLKCTRL_BGATES_POOL0_LSB) | \ + (ATON_CLKCTRL_BGATES_POOL1_DT << ATON_CLKCTRL_BGATES_POOL1_LSB) | \ + (ATON_CLKCTRL_BGATES_RECBUF0_DT << ATON_CLKCTRL_BGATES_RECBUF0_LSB) | \ + (ATON_CLKCTRL_BGATES_EPOCHCTRL0_DT << ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB) | \ + (ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DT << ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB) + + + +/** Description of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DESC "Clock enable bits register for B clocks" + +/** Address of the BGATES register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_BGATES_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_BGATES_OFFSET) + +/** Get the content of the BGATES register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_BGATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_BGATES_ADDR(UNIT))) + +/** Set the content of the BGATES register of one of the CLKCTRL Units. */ +#define ATON_CLKCTRL_BGATES_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_BGATES_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of BGATES register. + * + * \return the description of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_GetDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_DESC; +} + + +/** + * Get the offset of the BGATES register. + * + * \return the offset of BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_GetOffset(void) +{ + return ATON_CLKCTRL_BGATES_OFFSET; +} + + +/** + * Get the address of the BGATES register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the BGATES register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of BGATES register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_GetAddr(uint32_t instance) +{ + return ATON_CLKCTRL_BGATES_ADDR(instance); +} + + +/** + * Read the content of the BGATES register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the BGATES register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of BGATES register belonging to Unit having index \e instance among the CLKCTRL Units + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get(uint32_t instance) +{ + return ATON_CLKCTRL_BGATES_GET(instance); +} + + +/** + * Write the content of the BGATES register. + * + * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the BGATES register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CLKCTRL_BGATES_Set(uint32_t instance, uint32_t data) +{ + ATON_CLKCTRL_BGATES_SET(instance, data); +} + + +/* ---------------------------------------------------------- STRENG0 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG0_DESC "Enable clock of Stream Engine 0" + +/** Offset of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG0_LSB 0UL + +/** Size in bits of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG0_W (1UL) + +/** Mask for retrieving the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG0_DT 0x0UL + +/** Access rights of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG0_AC "RW" + +/** Check whether access to the STRENG0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG0_S 0 + +/** Check whether access to the STRENG0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG0_P 0 + +/** Read the content of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG0_LSB, ATON_CLKCTRL_BGATES_STRENG0_W) + +/** Modify the content of the STRENG0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG0_LSB, ATON_CLKCTRL_BGATES_STRENG0_W, DATA) + + +/** + * Get the description of the STRENG0 field of BGATES register. + * + * \return the description of the STRENG0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG0_DESC; +} + + +/** + * Read the content of the STRENG0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG0(reg); +} + + +/** + * Write the content of the STRENG0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG0(reg, data); +} + + +/* ---------------------------------------------------------- STRENG1 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG1_DESC "Enable clock of Stream Engine 1" + +/** Offset of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG1_LSB 1UL + +/** Size in bits of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG1_W (1UL) + +/** Mask for retrieving the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG1_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG1_DT 0x0UL + +/** Access rights of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG1_AC "RW" + +/** Check whether access to the STRENG1 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG1_S 0 + +/** Check whether access to the STRENG1 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG1_P 0 + +/** Read the content of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG1_LSB, ATON_CLKCTRL_BGATES_STRENG1_W) + +/** Modify the content of the STRENG1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG1_LSB, ATON_CLKCTRL_BGATES_STRENG1_W, DATA) + + +/** + * Get the description of the STRENG1 field of BGATES register. + * + * \return the description of the STRENG1 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG1_DESC; +} + + +/** + * Read the content of the STRENG1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG1(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG1(reg); +} + + +/** + * Write the content of the STRENG1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG1(reg, data); +} + + +/* ---------------------------------------------------------- STRENG2 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG2_DESC "Enable clock of Stream Engine 2" + +/** Offset of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG2_LSB 2UL + +/** Size in bits of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG2_W (1UL) + +/** Mask for retrieving the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG2_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG2_DT 0x0UL + +/** Access rights of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG2_AC "RW" + +/** Check whether access to the STRENG2 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG2_S 0 + +/** Check whether access to the STRENG2 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG2_P 0 + +/** Read the content of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG2(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG2_LSB, ATON_CLKCTRL_BGATES_STRENG2_W) + +/** Modify the content of the STRENG2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG2(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG2_LSB, ATON_CLKCTRL_BGATES_STRENG2_W, DATA) + + +/** + * Get the description of the STRENG2 field of BGATES register. + * + * \return the description of the STRENG2 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG2_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG2_DESC; +} + + +/** + * Read the content of the STRENG2 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG2 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG2(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG2(reg); +} + + +/** + * Write the content of the STRENG2 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG2 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG2(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG2(reg, data); +} + + +/* ---------------------------------------------------------- STRENG3 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG3_DESC "Enable clock of Stream Engine 3" + +/** Offset of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG3_LSB 3UL + +/** Size in bits of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG3_W (1UL) + +/** Mask for retrieving the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG3_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG3_DT 0x0UL + +/** Access rights of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG3_AC "RW" + +/** Check whether access to the STRENG3 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG3_S 0 + +/** Check whether access to the STRENG3 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG3_P 0 + +/** Read the content of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG3(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG3_LSB, ATON_CLKCTRL_BGATES_STRENG3_W) + +/** Modify the content of the STRENG3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG3(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG3_LSB, ATON_CLKCTRL_BGATES_STRENG3_W, DATA) + + +/** + * Get the description of the STRENG3 field of BGATES register. + * + * \return the description of the STRENG3 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG3_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG3_DESC; +} + + +/** + * Read the content of the STRENG3 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG3 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG3(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG3(reg); +} + + +/** + * Write the content of the STRENG3 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG3 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG3(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG3(reg, data); +} + + +/* ---------------------------------------------------------- STRENG4 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG4_DESC "Enable clock of Stream Engine 4" + +/** Offset of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG4_LSB 4UL + +/** Size in bits of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG4_W (1UL) + +/** Mask for retrieving the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG4_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG4_DT 0x0UL + +/** Access rights of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG4_AC "RW" + +/** Check whether access to the STRENG4 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG4_S 0 + +/** Check whether access to the STRENG4 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG4_P 0 + +/** Read the content of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG4(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG4_LSB, ATON_CLKCTRL_BGATES_STRENG4_W) + +/** Modify the content of the STRENG4 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG4(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG4_LSB, ATON_CLKCTRL_BGATES_STRENG4_W, DATA) + + +/** + * Get the description of the STRENG4 field of BGATES register. + * + * \return the description of the STRENG4 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG4_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG4_DESC; +} + + +/** + * Read the content of the STRENG4 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG4 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG4(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG4(reg); +} + + +/** + * Write the content of the STRENG4 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG4 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG4(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG4(reg, data); +} + + +/* ---------------------------------------------------------- STRENG5 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG5_DESC "Enable clock of Stream Engine 5" + +/** Offset of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG5_LSB 5UL + +/** Size in bits of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG5_W (1UL) + +/** Mask for retrieving the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG5_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG5_DT 0x0UL + +/** Access rights of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG5_AC "RW" + +/** Check whether access to the STRENG5 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG5_S 0 + +/** Check whether access to the STRENG5 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG5_P 0 + +/** Read the content of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG5(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG5_LSB, ATON_CLKCTRL_BGATES_STRENG5_W) + +/** Modify the content of the STRENG5 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG5(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG5_LSB, ATON_CLKCTRL_BGATES_STRENG5_W, DATA) + + +/** + * Get the description of the STRENG5 field of BGATES register. + * + * \return the description of the STRENG5 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG5_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG5_DESC; +} + + +/** + * Read the content of the STRENG5 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG5 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG5(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG5(reg); +} + + +/** + * Write the content of the STRENG5 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG5 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG5(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG5(reg, data); +} + + +/* ---------------------------------------------------------- STRENG6 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG6_DESC "Enable clock of Stream Engine 6" + +/** Offset of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG6_LSB 6UL + +/** Size in bits of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG6_W (1UL) + +/** Mask for retrieving the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG6_MASK ATON_FIELD_MASK(6UL, 1UL) + +/** Reset value of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG6_DT 0x0UL + +/** Access rights of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG6_AC "RW" + +/** Check whether access to the STRENG6 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG6_S 0 + +/** Check whether access to the STRENG6 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG6_P 0 + +/** Read the content of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG6(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG6_LSB, ATON_CLKCTRL_BGATES_STRENG6_W) + +/** Modify the content of the STRENG6 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG6(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG6_LSB, ATON_CLKCTRL_BGATES_STRENG6_W, DATA) + + +/** + * Get the description of the STRENG6 field of BGATES register. + * + * \return the description of the STRENG6 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG6_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG6_DESC; +} + + +/** + * Read the content of the STRENG6 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG6 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG6(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG6(reg); +} + + +/** + * Write the content of the STRENG6 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG6 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG6(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG6(reg, data); +} + + +/* ---------------------------------------------------------- STRENG7 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG7_DESC "Enable clock of Stream Engine 7" + +/** Offset of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG7_LSB 7UL + +/** Size in bits of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG7_W (1UL) + +/** Mask for retrieving the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG7_MASK ATON_FIELD_MASK(7UL, 1UL) + +/** Reset value of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG7_DT 0x0UL + +/** Access rights of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG7_AC "RW" + +/** Check whether access to the STRENG7 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG7_S 0 + +/** Check whether access to the STRENG7 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG7_P 0 + +/** Read the content of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG7(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG7_LSB, ATON_CLKCTRL_BGATES_STRENG7_W) + +/** Modify the content of the STRENG7 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG7(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG7_LSB, ATON_CLKCTRL_BGATES_STRENG7_W, DATA) + + +/** + * Get the description of the STRENG7 field of BGATES register. + * + * \return the description of the STRENG7 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG7_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG7_DESC; +} + + +/** + * Read the content of the STRENG7 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG7 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG7(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG7(reg); +} + + +/** + * Write the content of the STRENG7 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG7 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG7(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG7(reg, data); +} + + +/* ---------------------------------------------------------- STRENG8 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG8_DESC "Enable clock of Stream Engine 8" + +/** Offset of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG8_LSB 8UL + +/** Size in bits of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG8_W (1UL) + +/** Mask for retrieving the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG8_MASK ATON_FIELD_MASK(8UL, 1UL) + +/** Reset value of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG8_DT 0x0UL + +/** Access rights of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG8_AC "RW" + +/** Check whether access to the STRENG8 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG8_S 0 + +/** Check whether access to the STRENG8 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG8_P 0 + +/** Read the content of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG8(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG8_LSB, ATON_CLKCTRL_BGATES_STRENG8_W) + +/** Modify the content of the STRENG8 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG8(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG8_LSB, ATON_CLKCTRL_BGATES_STRENG8_W, DATA) + + +/** + * Get the description of the STRENG8 field of BGATES register. + * + * \return the description of the STRENG8 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG8_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG8_DESC; +} + + +/** + * Read the content of the STRENG8 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG8 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG8(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG8(reg); +} + + +/** + * Write the content of the STRENG8 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG8 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG8(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG8(reg, data); +} + + +/* ---------------------------------------------------------- STRENG9 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG9_DESC "Enable clock of Stream Engine 9" + +/** Offset of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG9_LSB 9UL + +/** Size in bits of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG9_W (1UL) + +/** Mask for retrieving the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG9_MASK ATON_FIELD_MASK(9UL, 1UL) + +/** Reset value of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG9_DT 0x0UL + +/** Access rights of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_STRENG9_AC "RW" + +/** Check whether access to the STRENG9 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_STRENG9_S 0 + +/** Check whether access to the STRENG9 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_STRENG9_P 0 + +/** Read the content of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_STRENG9(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG9_LSB, ATON_CLKCTRL_BGATES_STRENG9_W) + +/** Modify the content of the STRENG9 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_STRENG9(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG9_LSB, ATON_CLKCTRL_BGATES_STRENG9_W, DATA) + + +/** + * Get the description of the STRENG9 field of BGATES register. + * + * \return the description of the STRENG9 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG9_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG9_DESC; +} + + +/** + * Read the content of the STRENG9 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the STRENG9 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG9(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_STRENG9(reg); +} + + +/** + * Write the content of the STRENG9 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STRENG9 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG9(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_STRENG9(reg, data); +} + + +/* --------------------------------------------------------- CONVACC0 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_DESC "Enable clock of Convolutional Accelerator 0" + +/** Offset of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_LSB 10UL + +/** Size in bits of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_W (1UL) + +/** Mask for retrieving the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_DT 0x0UL + +/** Access rights of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_AC "RW" + +/** Check whether access to the CONVACC0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_S 0 + +/** Check whether access to the CONVACC0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC0_P 0 + +/** Read the content of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_CONVACC0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC0_LSB, ATON_CLKCTRL_BGATES_CONVACC0_W) + +/** Modify the content of the CONVACC0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_CONVACC0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC0_LSB, ATON_CLKCTRL_BGATES_CONVACC0_W, DATA) + + +/** + * Get the description of the CONVACC0 field of BGATES register. + * + * \return the description of the CONVACC0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC0_DESC; +} + + +/** + * Read the content of the CONVACC0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the CONVACC0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_CONVACC0(reg); +} + + +/** + * Write the content of the CONVACC0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONVACC0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_CONVACC0(reg, data); +} + + +/* --------------------------------------------------------- CONVACC1 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_DESC "Enable clock of Convolutional Accelerator 1" + +/** Offset of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_LSB 11UL + +/** Size in bits of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_W (1UL) + +/** Mask for retrieving the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_DT 0x0UL + +/** Access rights of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_AC "RW" + +/** Check whether access to the CONVACC1 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_S 0 + +/** Check whether access to the CONVACC1 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC1_P 0 + +/** Read the content of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_CONVACC1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC1_LSB, ATON_CLKCTRL_BGATES_CONVACC1_W) + +/** Modify the content of the CONVACC1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_CONVACC1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC1_LSB, ATON_CLKCTRL_BGATES_CONVACC1_W, DATA) + + +/** + * Get the description of the CONVACC1 field of BGATES register. + * + * \return the description of the CONVACC1 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC1_DESC; +} + + +/** + * Read the content of the CONVACC1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the CONVACC1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC1(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_CONVACC1(reg); +} + + +/** + * Write the content of the CONVACC1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONVACC1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_CONVACC1(reg, data); +} + + +/* --------------------------------------------------------- CONVACC2 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_DESC "Enable clock of Convolutional Accelerator 2" + +/** Offset of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_LSB 12UL + +/** Size in bits of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_W (1UL) + +/** Mask for retrieving the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_MASK ATON_FIELD_MASK(12UL, 1UL) + +/** Reset value of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_DT 0x0UL + +/** Access rights of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_AC "RW" + +/** Check whether access to the CONVACC2 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_S 0 + +/** Check whether access to the CONVACC2 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC2_P 0 + +/** Read the content of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_CONVACC2(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC2_LSB, ATON_CLKCTRL_BGATES_CONVACC2_W) + +/** Modify the content of the CONVACC2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_CONVACC2(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC2_LSB, ATON_CLKCTRL_BGATES_CONVACC2_W, DATA) + + +/** + * Get the description of the CONVACC2 field of BGATES register. + * + * \return the description of the CONVACC2 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC2_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC2_DESC; +} + + +/** + * Read the content of the CONVACC2 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the CONVACC2 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC2(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_CONVACC2(reg); +} + + +/** + * Write the content of the CONVACC2 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONVACC2 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC2(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_CONVACC2(reg, data); +} + + +/* --------------------------------------------------------- CONVACC3 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_DESC "Enable clock of Convolutional Accelerator 3" + +/** Offset of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_LSB 13UL + +/** Size in bits of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_W (1UL) + +/** Mask for retrieving the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_MASK ATON_FIELD_MASK(13UL, 1UL) + +/** Reset value of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_DT 0x0UL + +/** Access rights of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_AC "RW" + +/** Check whether access to the CONVACC3 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_S 0 + +/** Check whether access to the CONVACC3 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_CONVACC3_P 0 + +/** Read the content of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_CONVACC3(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC3_LSB, ATON_CLKCTRL_BGATES_CONVACC3_W) + +/** Modify the content of the CONVACC3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_CONVACC3(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC3_LSB, ATON_CLKCTRL_BGATES_CONVACC3_W, DATA) + + +/** + * Get the description of the CONVACC3 field of BGATES register. + * + * \return the description of the CONVACC3 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC3_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC3_DESC; +} + + +/** + * Read the content of the CONVACC3 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the CONVACC3 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC3(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_CONVACC3(reg); +} + + +/** + * Write the content of the CONVACC3 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONVACC3 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC3(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_CONVACC3(reg, data); +} + + +/* ---------------------------------------------------------- DECUN0 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN0_DESC "Enable clock of Decompression Unit 0" + +/** Offset of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN0_LSB 14UL + +/** Size in bits of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN0_W (1UL) + +/** Mask for retrieving the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN0_MASK ATON_FIELD_MASK(14UL, 1UL) + +/** Reset value of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN0_DT 0x0UL + +/** Access rights of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN0_AC "RW" + +/** Check whether access to the DECUN0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_DECUN0_S 0 + +/** Check whether access to the DECUN0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_DECUN0_P 0 + +/** Read the content of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_DECUN0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN0_LSB, ATON_CLKCTRL_BGATES_DECUN0_W) + +/** Modify the content of the DECUN0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_DECUN0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN0_LSB, ATON_CLKCTRL_BGATES_DECUN0_W, DATA) + + +/** + * Get the description of the DECUN0 field of BGATES register. + * + * \return the description of the DECUN0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_DECUN0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_DECUN0_DESC; +} + + +/** + * Read the content of the DECUN0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the DECUN0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_DECUN0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_DECUN0(reg); +} + + +/** + * Write the content of the DECUN0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DECUN0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_DECUN0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_DECUN0(reg, data); +} + + +/* ---------------------------------------------------------- DECUN1 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN1_DESC "Enable clock of Decompression Unit 1" + +/** Offset of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN1_LSB 15UL + +/** Size in bits of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN1_W (1UL) + +/** Mask for retrieving the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN1_MASK ATON_FIELD_MASK(15UL, 1UL) + +/** Reset value of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN1_DT 0x0UL + +/** Access rights of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DECUN1_AC "RW" + +/** Check whether access to the DECUN1 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_DECUN1_S 0 + +/** Check whether access to the DECUN1 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_DECUN1_P 0 + +/** Read the content of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_DECUN1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN1_LSB, ATON_CLKCTRL_BGATES_DECUN1_W) + +/** Modify the content of the DECUN1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_DECUN1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN1_LSB, ATON_CLKCTRL_BGATES_DECUN1_W, DATA) + + +/** + * Get the description of the DECUN1 field of BGATES register. + * + * \return the description of the DECUN1 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_DECUN1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_DECUN1_DESC; +} + + +/** + * Read the content of the DECUN1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the DECUN1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_DECUN1(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_DECUN1(reg); +} + + +/** + * Write the content of the DECUN1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DECUN1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_DECUN1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_DECUN1(reg, data); +} + + +/* ---------------------------------------------------------- ACTIV0 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_DESC "Enable clock of Activation Accelerator 0" + +/** Offset of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_LSB 16UL + +/** Size in bits of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_W (1UL) + +/** Mask for retrieving the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_DT 0x0UL + +/** Access rights of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_AC "RW" + +/** Check whether access to the ACTIV0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_S 0 + +/** Check whether access to the ACTIV0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_ACTIV0_P 0 + +/** Read the content of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_ACTIV0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV0_LSB, ATON_CLKCTRL_BGATES_ACTIV0_W) + +/** Modify the content of the ACTIV0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_ACTIV0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV0_LSB, ATON_CLKCTRL_BGATES_ACTIV0_W, DATA) + + +/** + * Get the description of the ACTIV0 field of BGATES register. + * + * \return the description of the ACTIV0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_ACTIV0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_ACTIV0_DESC; +} + + +/** + * Read the content of the ACTIV0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the ACTIV0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_ACTIV0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_ACTIV0(reg); +} + + +/** + * Write the content of the ACTIV0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ACTIV0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_ACTIV0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_ACTIV0(reg, data); +} + + +/* ---------------------------------------------------------- ACTIV1 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_DESC "Enable clock of Activation Accelerator 1" + +/** Offset of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_LSB 17UL + +/** Size in bits of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_W (1UL) + +/** Mask for retrieving the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_DT 0x0UL + +/** Access rights of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_AC "RW" + +/** Check whether access to the ACTIV1 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_S 0 + +/** Check whether access to the ACTIV1 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_ACTIV1_P 0 + +/** Read the content of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_ACTIV1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV1_LSB, ATON_CLKCTRL_BGATES_ACTIV1_W) + +/** Modify the content of the ACTIV1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_ACTIV1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV1_LSB, ATON_CLKCTRL_BGATES_ACTIV1_W, DATA) + + +/** + * Get the description of the ACTIV1 field of BGATES register. + * + * \return the description of the ACTIV1 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_ACTIV1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_ACTIV1_DESC; +} + + +/** + * Read the content of the ACTIV1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the ACTIV1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_ACTIV1(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_ACTIV1(reg); +} + + +/** + * Write the content of the ACTIV1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ACTIV1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_ACTIV1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_ACTIV1(reg, data); +} + + +/* ---------------------------------------------------------- ARITH0 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH0_DESC "Enable clock of Arithmetic Accelerator 0" + +/** Offset of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH0_LSB 18UL + +/** Size in bits of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH0_W (1UL) + +/** Mask for retrieving the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH0_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH0_DT 0x0UL + +/** Access rights of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH0_AC "RW" + +/** Check whether access to the ARITH0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_ARITH0_S 0 + +/** Check whether access to the ARITH0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_ARITH0_P 0 + +/** Read the content of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_ARITH0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH0_LSB, ATON_CLKCTRL_BGATES_ARITH0_W) + +/** Modify the content of the ARITH0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_ARITH0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH0_LSB, ATON_CLKCTRL_BGATES_ARITH0_W, DATA) + + +/** + * Get the description of the ARITH0 field of BGATES register. + * + * \return the description of the ARITH0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH0_DESC; +} + + +/** + * Read the content of the ARITH0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the ARITH0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_ARITH0(reg); +} + + +/** + * Write the content of the ARITH0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ARITH0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_ARITH0(reg, data); +} + + +/* ---------------------------------------------------------- ARITH1 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH1_DESC "Enable clock of Arithmetic Accelerator 1" + +/** Offset of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH1_LSB 19UL + +/** Size in bits of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH1_W (1UL) + +/** Mask for retrieving the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH1_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH1_DT 0x0UL + +/** Access rights of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH1_AC "RW" + +/** Check whether access to the ARITH1 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_ARITH1_S 0 + +/** Check whether access to the ARITH1 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_ARITH1_P 0 + +/** Read the content of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_ARITH1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH1_LSB, ATON_CLKCTRL_BGATES_ARITH1_W) + +/** Modify the content of the ARITH1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_ARITH1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH1_LSB, ATON_CLKCTRL_BGATES_ARITH1_W, DATA) + + +/** + * Get the description of the ARITH1 field of BGATES register. + * + * \return the description of the ARITH1 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH1_DESC; +} + + +/** + * Read the content of the ARITH1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the ARITH1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH1(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_ARITH1(reg); +} + + +/** + * Write the content of the ARITH1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ARITH1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_ARITH1(reg, data); +} + + +/* ---------------------------------------------------------- ARITH2 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH2_DESC "Enable clock of Arithmetic Accelerator 2" + +/** Offset of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH2_LSB 20UL + +/** Size in bits of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH2_W (1UL) + +/** Mask for retrieving the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH2_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH2_DT 0x0UL + +/** Access rights of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH2_AC "RW" + +/** Check whether access to the ARITH2 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_ARITH2_S 0 + +/** Check whether access to the ARITH2 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_ARITH2_P 0 + +/** Read the content of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_ARITH2(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH2_LSB, ATON_CLKCTRL_BGATES_ARITH2_W) + +/** Modify the content of the ARITH2 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_ARITH2(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH2_LSB, ATON_CLKCTRL_BGATES_ARITH2_W, DATA) + + +/** + * Get the description of the ARITH2 field of BGATES register. + * + * \return the description of the ARITH2 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH2_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH2_DESC; +} + + +/** + * Read the content of the ARITH2 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the ARITH2 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH2(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_ARITH2(reg); +} + + +/** + * Write the content of the ARITH2 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ARITH2 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH2(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_ARITH2(reg, data); +} + + +/* ---------------------------------------------------------- ARITH3 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH3_DESC "Enable clock of Arithmetic Accelerator 3" + +/** Offset of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH3_LSB 21UL + +/** Size in bits of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH3_W (1UL) + +/** Mask for retrieving the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH3_MASK ATON_FIELD_MASK(21UL, 1UL) + +/** Reset value of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH3_DT 0x0UL + +/** Access rights of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_ARITH3_AC "RW" + +/** Check whether access to the ARITH3 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_ARITH3_S 0 + +/** Check whether access to the ARITH3 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_ARITH3_P 0 + +/** Read the content of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_ARITH3(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH3_LSB, ATON_CLKCTRL_BGATES_ARITH3_W) + +/** Modify the content of the ARITH3 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_ARITH3(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH3_LSB, ATON_CLKCTRL_BGATES_ARITH3_W, DATA) + + +/** + * Get the description of the ARITH3 field of BGATES register. + * + * \return the description of the ARITH3 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH3_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH3_DESC; +} + + +/** + * Read the content of the ARITH3 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the ARITH3 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH3(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_ARITH3(reg); +} + + +/** + * Write the content of the ARITH3 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ARITH3 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH3(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_ARITH3(reg, data); +} + + +/* ----------------------------------------------------------- POOL0 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL0_DESC "Enable clock of Pooling Accelerator 0" + +/** Offset of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL0_LSB 22UL + +/** Size in bits of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL0_W (1UL) + +/** Mask for retrieving the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL0_MASK ATON_FIELD_MASK(22UL, 1UL) + +/** Reset value of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL0_DT 0x0UL + +/** Access rights of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL0_AC "RW" + +/** Check whether access to the POOL0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_POOL0_S 0 + +/** Check whether access to the POOL0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_POOL0_P 0 + +/** Read the content of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_POOL0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL0_LSB, ATON_CLKCTRL_BGATES_POOL0_W) + +/** Modify the content of the POOL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_POOL0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL0_LSB, ATON_CLKCTRL_BGATES_POOL0_W, DATA) + + +/** + * Get the description of the POOL0 field of BGATES register. + * + * \return the description of the POOL0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_POOL0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_POOL0_DESC; +} + + +/** + * Read the content of the POOL0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the POOL0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_POOL0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_POOL0(reg); +} + + +/** + * Write the content of the POOL0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the POOL0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_POOL0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_POOL0(reg, data); +} + + +/* ----------------------------------------------------------- POOL1 field of the BGATES register ----------------------------------------------------------- */ + +/** Description of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL1_DESC "Enable clock of Pooling Accelerator 1" + +/** Offset of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL1_LSB 23UL + +/** Size in bits of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL1_W (1UL) + +/** Mask for retrieving the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL1_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL1_DT 0x0UL + +/** Access rights of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_POOL1_AC "RW" + +/** Check whether access to the POOL1 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_POOL1_S 0 + +/** Check whether access to the POOL1 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_POOL1_P 0 + +/** Read the content of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_POOL1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL1_LSB, ATON_CLKCTRL_BGATES_POOL1_W) + +/** Modify the content of the POOL1 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_POOL1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL1_LSB, ATON_CLKCTRL_BGATES_POOL1_W, DATA) + + +/** + * Get the description of the POOL1 field of BGATES register. + * + * \return the description of the POOL1 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_POOL1_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_POOL1_DESC; +} + + +/** + * Read the content of the POOL1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the POOL1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_POOL1(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_POOL1(reg); +} + + +/** + * Write the content of the POOL1 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the POOL1 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_POOL1(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_POOL1(reg, data); +} + + +/* ---------------------------------------------------------- RECBUF0 field of the BGATES register ---------------------------------------------------------- */ + +/** Description of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_DESC "Enable clock of Reconfigurable Buffer 0" + +/** Offset of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_LSB 24UL + +/** Size in bits of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_W (1UL) + +/** Mask for retrieving the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_MASK ATON_FIELD_MASK(24UL, 1UL) + +/** Reset value of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_DT 0x0UL + +/** Access rights of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_AC "RW" + +/** Check whether access to the RECBUF0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_S 0 + +/** Check whether access to the RECBUF0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_RECBUF0_P 0 + +/** Read the content of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_RECBUF0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_RECBUF0_LSB, ATON_CLKCTRL_BGATES_RECBUF0_W) + +/** Modify the content of the RECBUF0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_RECBUF0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_RECBUF0_LSB, ATON_CLKCTRL_BGATES_RECBUF0_W, DATA) + + +/** + * Get the description of the RECBUF0 field of BGATES register. + * + * \return the description of the RECBUF0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_RECBUF0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_RECBUF0_DESC; +} + + +/** + * Read the content of the RECBUF0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the RECBUF0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_RECBUF0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_RECBUF0(reg); +} + + +/** + * Write the content of the RECBUF0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RECBUF0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_RECBUF0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_RECBUF0(reg, data); +} + + +/* -------------------------------------------------------- EPOCHCTRL0 field of the BGATES register --------------------------------------------------------- */ + +/** Description of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_DESC "Enable clock of Epoch Controller 0" + +/** Offset of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB 25UL + +/** Size in bits of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_W (1UL) + +/** Mask for retrieving the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_MASK ATON_FIELD_MASK(25UL, 1UL) + +/** Reset value of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_DT 0x0UL + +/** Access rights of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_AC "RW" + +/** Check whether access to the EPOCHCTRL0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_S 0 + +/** Check whether access to the EPOCHCTRL0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_EPOCHCTRL0_P 0 + +/** Read the content of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_EPOCHCTRL0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB, ATON_CLKCTRL_BGATES_EPOCHCTRL0_W) + +/** Modify the content of the EPOCHCTRL0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_EPOCHCTRL0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB, ATON_CLKCTRL_BGATES_EPOCHCTRL0_W, DATA) + + +/** + * Get the description of the EPOCHCTRL0 field of BGATES register. + * + * \return the description of the EPOCHCTRL0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_EPOCHCTRL0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_EPOCHCTRL0_DESC; +} + + +/** + * Read the content of the EPOCHCTRL0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the EPOCHCTRL0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_EPOCHCTRL0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_EPOCHCTRL0(reg); +} + + +/** + * Write the content of the EPOCHCTRL0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EPOCHCTRL0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_EPOCHCTRL0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_EPOCHCTRL0(reg, data); +} + + +/* ------------------------------------------------------- DEBUG_TRACE0 field of the BGATES register -------------------------------------------------------- */ + +/** Description of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DESC "Enable clock of Debug Trace 0" + +/** Offset of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB 26UL + +/** Size in bits of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_W (1UL) + +/** Mask for retrieving the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_MASK ATON_FIELD_MASK(26UL, 1UL) + +/** Reset value of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DT 0x0UL + +/** Access rights of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_AC "RW" + +/** Check whether access to the DEBUG_TRACE0 field of the BGATES register is secured or not. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_S 0 + +/** Check whether access to the DEBUG_TRACE0 field of the BGATES register is privileged or not. */ +#define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_P 0 + +/** Read the content of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_GET_DEBUG_TRACE0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_W) + +/** Modify the content of the DEBUG_TRACE0 field of the BGATES register. */ +#define ATON_CLKCTRL_BGATES_SET_DEBUG_TRACE0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_W, DATA) + + +/** + * Get the description of the DEBUG_TRACE0 field of BGATES register. + * + * \return the description of the DEBUG_TRACE0 field of BGATES register + */ + +static inline const int8_t *ATON_CLKCTRL_BGATES_DEBUG_TRACE0_GetdDesc(void) +{ + return (const int8_t *)ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DESC; +} + + +/** + * Read the content of the DEBUG_TRACE0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * + * \return the content of the DEBUG_TRACE0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Get_DEBUG_TRACE0(uint32_t reg) +{ + return ATON_CLKCTRL_BGATES_GET_DEBUG_TRACE0(reg); +} + + +/** + * Write the content of the DEBUG_TRACE0 field of the BGATES register. + * + * \param[in] reg is the value of the BGATES register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DEBUG_TRACE0 field belonging to BGATES register + */ + +static inline uint32_t ATON_CLKCTRL_BGATES_Set_DEBUG_TRACE0(uint32_t reg, uint32_t data) +{ + return ATON_CLKCTRL_BGATES_SET_DEBUG_TRACE0(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* INTCTRL Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of INTCTRL Unit instances. */ +#define ATON_INTCTRL_NUM 1 + +/** + * \name Structures, macros and functions of the INTCTRL Units + */ +/*@{*/ + +/** + * Registers of the INTCTRL Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e INTREG register (Interrupt register). */ + uint32_t INTREG; + + /** \e INTSET register (Set interrupts). */ + uint32_t INTSET; + + /** \e INTCLR register (Clear interrupts). */ + uint32_t INTCLR; + + /** \e INTORMSK0 register (Interrupt OR mask 0). */ + uint32_t INTORMSK0; + + /** \e INTORMSK1 register (Interrupt OR mask 1). */ + uint32_t INTORMSK1; + + /** \e INTORMSK2 register (Interrupt OR mask 2). */ + uint32_t INTORMSK2; + + /** \e INTORMSK3 register (Interrupt OR mask 3). */ + uint32_t INTORMSK3; + + /** \e INTANDMSK0 register (Interrupt AND mask 0). */ + uint32_t INTANDMSK0; + + /** \e INTANDMSK1 register (Interrupt AND mask 1). */ + uint32_t INTANDMSK1; + + /** \e INTANDMSK2 register (Interrupt AND mask 2). */ + uint32_t INTANDMSK2; + + /** \e INTANDMSK3 register (Interrupt AND mask 3). */ + uint32_t INTANDMSK3; + +} ATON_INTCTRL_t; + + +/** Return the pointer to one of the INTCTRL Units. */ +#define ATON_INTCTRL(UNIT) ((ATON_INTCTRL_t *)(intptr_t)ATON_INTCTRL_BASE(UNIT)) + + +/** Name of one of the INTCTRL Units. */ +#define ATON_INTCTRL_NAME(UNIT) \ + (((UNIT) == 0) ? "INTCTRL" : "") + + +/** Version of the INTCTRL Units. */ +#define ATON_INTCTRL_VERSION "1.1" + + +/** Description of one of the INTCTRL Units. */ +#define ATON_INTCTRL_DESC(UNIT) \ + (((UNIT) == 0) ? "Interrupt Controller" : "") + + +/** Base address of one of the INTCTRL Units. */ +#define ATON_INTCTRL_BASE(UNIT) \ + (ATON_BASE + 0x1000UL + ((UNIT) * 0x0UL)) + +/** Size in bytes of the INTCTRL Units. */ +#define ATON_INTCTRL_SIZE 0x1000UL + + +/** + * Get the name of one of the INTCTRL Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) + * + * \return the name of Unit having index \e instance among the INTCTRL Units + */ + +static inline const int8_t *ATON_INTCTRL_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"INTCTRL"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the INTCTRL Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) + * + * \return the description of Unit having index \e instance among the INTCTRL Units + */ + +static inline const int8_t *ATON_INTCTRL_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Interrupt Controller"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the INTCTRL Units. + * + * \return the version of the INTCTRL Units + */ + +static inline const int8_t *ATON_INTCTRL_GetVersion(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION; +} + + +/** + * Get the base address of one of the INTCTRL Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) + * + * \return the base address of Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_GetBase(uint32_t instance) +{ + return ATON_INTCTRL_BASE(instance); +} + + +/** + * Get the size in bytes of the INTCTRL Units. + * + * \return the size in bytes of the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_GetSize(void) +{ + return ATON_INTCTRL_SIZE; +} + + +/* ******************************************************* CTRL register of one of the INTCTRL Units ******************************************************** */ + +/** Offset of the CTRL register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the INTCTRL Unit. */ +#define ATON_INTCTRL_CTRL_DT \ + (ATON_INTCTRL_CTRL_EN_DT << ATON_INTCTRL_CTRL_EN_LSB) | \ + (ATON_INTCTRL_CTRL_CLR_DT << ATON_INTCTRL_CTRL_CLR_LSB) | \ + (ATON_INTCTRL_CTRL_CONFCLR_DT << ATON_INTCTRL_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_INTCTRL_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_CTRL_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_INTCTRL_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_GetOffset(void) +{ + return ATON_INTCTRL_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the CTRL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_CTRL_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Get(uint32_t instance) +{ + return ATON_INTCTRL_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the CTRL register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_EN_DESC "Enable the Interrupt Controller" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_INTCTRL_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_INTCTRL_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_CTRL_EN_LSB, ATON_INTCTRL_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_CTRL_EN_LSB, ATON_INTCTRL_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_INTCTRL_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Get_EN(uint32_t reg) +{ + return ATON_INTCTRL_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CLR_DESC "Clear interrupts" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_INTCTRL_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_INTCTRL_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_CTRL_CLR_LSB, ATON_INTCTRL_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_CTRL_CLR_LSB, ATON_INTCTRL_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_INTCTRL_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_INTCTRL_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_INTCTRL_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_INTCTRL_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_CTRL_CONFCLR_LSB, ATON_INTCTRL_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_INTCTRL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_CTRL_CONFCLR_LSB, ATON_INTCTRL_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_INTCTRL_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_INTCTRL_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_INTCTRL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_CTRL_SET_CONFCLR(reg, data); +} + + +/* ****************************************************** VERSION register of one of the INTCTRL Units ****************************************************** */ + +/** Offset of the VERSION register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the INTCTRL Unit. */ +#define ATON_INTCTRL_VERSION_DT \ + (ATON_INTCTRL_VERSION_TYPE_DT << ATON_INTCTRL_VERSION_TYPE_LSB) | \ + (ATON_INTCTRL_VERSION_MINOR_DT << ATON_INTCTRL_VERSION_MINOR_LSB) | \ + (ATON_INTCTRL_VERSION_MAJOR_DT << ATON_INTCTRL_VERSION_MAJOR_LSB) | \ + (ATON_INTCTRL_VERSION_NRINTS_DT << ATON_INTCTRL_VERSION_NRINTS_LSB) | \ + (ATON_INTCTRL_VERSION_HOSTINTS_DT << ATON_INTCTRL_VERSION_HOSTINTS_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_INTCTRL_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_VERSION_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_INTCTRL_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_INTCTRL_VERSION_GetOffset(void) +{ + return ATON_INTCTRL_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the VERSION register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_VERSION_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_VERSION_Get(uint32_t instance) +{ + return ATON_INTCTRL_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_TYPE_DT 0x1eUL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_INTCTRL_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_INTCTRL_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_TYPE_LSB, ATON_INTCTRL_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_INTCTRL_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_INTCTRL_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_INTCTRL_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MINOR_DT 0x1UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_INTCTRL_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_INTCTRL_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_MINOR_LSB, ATON_INTCTRL_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_INTCTRL_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_INTCTRL_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_INTCTRL_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_INTCTRL_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_INTCTRL_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_MAJOR_LSB, ATON_INTCTRL_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_INTCTRL_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_INTCTRL_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_INTCTRL_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- NRINTS field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_NRINTS_DESC "Number of internal interrupts" + +/** Offset of the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_NRINTS_LSB 16UL + +/** Size in bits of the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_NRINTS_W (8UL) + +/** Mask for retrieving the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_NRINTS_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_NRINTS_DT 0x20UL + +/** Access rights of the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_NRINTS_AC "R" + +/** Check whether access to the NRINTS field of the VERSION register is secured or not. */ +#define ATON_INTCTRL_VERSION_NRINTS_S 0 + +/** Check whether access to the NRINTS field of the VERSION register is privileged or not. */ +#define ATON_INTCTRL_VERSION_NRINTS_P 0 + +/** Read the content of the NRINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_GET_NRINTS(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_NRINTS_LSB, ATON_INTCTRL_VERSION_NRINTS_W) + + +/** + * Get the description of the NRINTS field of VERSION register. + * + * \return the description of the NRINTS field of VERSION register + */ + +static inline const int8_t *ATON_INTCTRL_VERSION_NRINTS_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION_NRINTS_DESC; +} + + +/** + * Read the content of the NRINTS field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the NRINTS field belonging to VERSION register + */ + +static inline uint32_t ATON_INTCTRL_VERSION_Get_NRINTS(uint32_t reg) +{ + return ATON_INTCTRL_VERSION_GET_NRINTS(reg); +} + + +/* --------------------------------------------------------- HOSTINTS field of the VERSION register --------------------------------------------------------- */ + +/** Description of the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_DESC "Number of host interrupt lines" + +/** Offset of the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_LSB 24UL + +/** Size in bits of the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_W (8UL) + +/** Mask for retrieving the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_DT 0x4UL + +/** Access rights of the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_AC "R" + +/** Check whether access to the HOSTINTS field of the VERSION register is secured or not. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_S 0 + +/** Check whether access to the HOSTINTS field of the VERSION register is privileged or not. */ +#define ATON_INTCTRL_VERSION_HOSTINTS_P 0 + +/** Read the content of the HOSTINTS field of the VERSION register. */ +#define ATON_INTCTRL_VERSION_GET_HOSTINTS(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_HOSTINTS_LSB, ATON_INTCTRL_VERSION_HOSTINTS_W) + + +/** + * Get the description of the HOSTINTS field of VERSION register. + * + * \return the description of the HOSTINTS field of VERSION register + */ + +static inline const int8_t *ATON_INTCTRL_VERSION_HOSTINTS_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_VERSION_HOSTINTS_DESC; +} + + +/** + * Read the content of the HOSTINTS field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the HOSTINTS field belonging to VERSION register + */ + +static inline uint32_t ATON_INTCTRL_VERSION_Get_HOSTINTS(uint32_t reg) +{ + return ATON_INTCTRL_VERSION_GET_HOSTINTS(reg); +} + + +/* ****************************************************** INTREG register of one of the INTCTRL Units ******************************************************* */ + +/** Offset of the INTREG register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTREG_OFFSET 0x8UL + +/** Reset value of the INTREG register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTREG_DT \ + (ATON_INTCTRL_INTREG_REG_DT << ATON_INTCTRL_INTREG_REG_LSB) + + + +/** Description of the INTREG register. */ +#define ATON_INTCTRL_INTREG_DESC "Interrupt register" + +/** Address of the INTREG register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTREG_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTREG_OFFSET) + +/** Get the content of the INTREG register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTREG_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTREG_ADDR(UNIT))) + + +/** + * Get the description of INTREG register. + * + * \return the description of INTREG register + */ + +static inline const int8_t *ATON_INTCTRL_INTREG_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTREG_DESC; +} + + +/** + * Get the offset of the INTREG register. + * + * \return the offset of INTREG register + */ + +static inline uint32_t ATON_INTCTRL_INTREG_GetOffset(void) +{ + return ATON_INTCTRL_INTREG_OFFSET; +} + + +/** + * Get the address of the INTREG register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTREG register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTREG register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTREG_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTREG_ADDR(instance); +} + + +/** + * Read the content of the INTREG register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTREG register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTREG register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTREG_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTREG_GET(instance); +} + + +/* ------------------------------------------------------------ REG field of the INTREG register ------------------------------------------------------------ */ + +/** Description of the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_REG_DESC "If interrupt X is set, bit X is set" + +/** Offset of the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_REG_LSB 0UL + +/** Size in bits of the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_REG_DT 0x0UL + +/** Access rights of the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_REG_AC "R" + +/** Check whether access to the REG field of the INTREG register is secured or not. */ +#define ATON_INTCTRL_INTREG_REG_S 0 + +/** Check whether access to the REG field of the INTREG register is privileged or not. */ +#define ATON_INTCTRL_INTREG_REG_P 0 + +/** Read the content of the REG field of the INTREG register. */ +#define ATON_INTCTRL_INTREG_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTREG_REG_LSB, ATON_INTCTRL_INTREG_REG_W) + + +/** + * Get the description of the REG field of INTREG register. + * + * \return the description of the REG field of INTREG register + */ + +static inline const int8_t *ATON_INTCTRL_INTREG_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTREG_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTREG register. + * + * \param[in] reg is the value of the INTREG register + * + * \return the content of the REG field belonging to INTREG register + */ + +static inline uint32_t ATON_INTCTRL_INTREG_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTREG_GET_REG(reg); +} + + +/* ****************************************************** INTSET register of one of the INTCTRL Units ******************************************************* */ + +/** Offset of the INTSET register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTSET_OFFSET 0xcUL + +/** Reset value of the INTSET register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTSET_DT \ + (ATON_INTCTRL_INTSET_REG_DT << ATON_INTCTRL_INTSET_REG_LSB) + + + +/** Description of the INTSET register. */ +#define ATON_INTCTRL_INTSET_DESC "Set interrupts" + +/** Address of the INTSET register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTSET_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTSET_OFFSET) + +/** Get the content of the INTSET register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTSET_ADDR(UNIT))) + +/** Set the content of the INTSET register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTSET_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTSET register. + * + * \return the description of INTSET register + */ + +static inline const int8_t *ATON_INTCTRL_INTSET_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTSET_DESC; +} + + +/** + * Get the offset of the INTSET register. + * + * \return the offset of INTSET register + */ + +static inline uint32_t ATON_INTCTRL_INTSET_GetOffset(void) +{ + return ATON_INTCTRL_INTSET_OFFSET; +} + + +/** + * Get the address of the INTSET register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTSET register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTSET register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTSET_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTSET_ADDR(instance); +} + + +/** + * Read the content of the INTSET register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTSET register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTSET register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTSET_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTSET_GET(instance); +} + + +/** + * Write the content of the INTSET register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTSET register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTSET_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTSET_SET(instance, data); +} + + +/* ------------------------------------------------------------ REG field of the INTSET register ------------------------------------------------------------ */ + +/** Description of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_REG_DESC "If bit X is set, interrupt X is raised. Reading this register returns same content as INTREG" + +/** Offset of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_REG_LSB 0UL + +/** Size in bits of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_REG_DT 0x0UL + +/** Access rights of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_REG_AC "RW" + +/** Check whether access to the REG field of the INTSET register is secured or not. */ +#define ATON_INTCTRL_INTSET_REG_S 0 + +/** Check whether access to the REG field of the INTSET register is privileged or not. */ +#define ATON_INTCTRL_INTSET_REG_P 0 + +/** Read the content of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTSET_REG_LSB, ATON_INTCTRL_INTSET_REG_W) + +/** Modify the content of the REG field of the INTSET register. */ +#define ATON_INTCTRL_INTSET_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTSET_REG_LSB, ATON_INTCTRL_INTSET_REG_W, DATA) + + +/** + * Get the description of the REG field of INTSET register. + * + * \return the description of the REG field of INTSET register + */ + +static inline const int8_t *ATON_INTCTRL_INTSET_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTSET_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTSET register. + * + * \param[in] reg is the value of the INTSET register + * + * \return the content of the REG field belonging to INTSET register + */ + +static inline uint32_t ATON_INTCTRL_INTSET_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTSET_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTSET register. + * + * \param[in] reg is the value of the INTSET register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTSET register + */ + +static inline uint32_t ATON_INTCTRL_INTSET_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTSET_SET_REG(reg, data); +} + + +/* ****************************************************** INTCLR register of one of the INTCTRL Units ******************************************************* */ + +/** Offset of the INTCLR register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTCLR_OFFSET 0x10UL + +/** Reset value of the INTCLR register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTCLR_DT \ + (ATON_INTCTRL_INTCLR_REG_DT << ATON_INTCTRL_INTCLR_REG_LSB) + + + +/** Description of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_DESC "Clear interrupts" + +/** Address of the INTCLR register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTCLR_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTCLR_OFFSET) + +/** Get the content of the INTCLR register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTCLR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTCLR_ADDR(UNIT))) + +/** Set the content of the INTCLR register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTCLR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTCLR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTCLR register. + * + * \return the description of INTCLR register + */ + +static inline const int8_t *ATON_INTCTRL_INTCLR_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTCLR_DESC; +} + + +/** + * Get the offset of the INTCLR register. + * + * \return the offset of INTCLR register + */ + +static inline uint32_t ATON_INTCTRL_INTCLR_GetOffset(void) +{ + return ATON_INTCTRL_INTCLR_OFFSET; +} + + +/** + * Get the address of the INTCLR register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTCLR register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTCLR register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTCLR_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTCLR_ADDR(instance); +} + + +/** + * Read the content of the INTCLR register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTCLR register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTCLR register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTCLR_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTCLR_GET(instance); +} + + +/** + * Write the content of the INTCLR register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTCLR register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTCLR_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTCLR_SET(instance, data); +} + + +/* ------------------------------------------------------------ REG field of the INTCLR register ------------------------------------------------------------ */ + +/** Description of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_REG_DESC "If bit X is set, interrupt X is cleared. Reading this register returns same content as INTREG" + +/** Offset of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_REG_LSB 0UL + +/** Size in bits of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_REG_DT 0x0UL + +/** Access rights of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_REG_AC "RW" + +/** Check whether access to the REG field of the INTCLR register is secured or not. */ +#define ATON_INTCTRL_INTCLR_REG_S 0 + +/** Check whether access to the REG field of the INTCLR register is privileged or not. */ +#define ATON_INTCTRL_INTCLR_REG_P 0 + +/** Read the content of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTCLR_REG_LSB, ATON_INTCTRL_INTCLR_REG_W) + +/** Modify the content of the REG field of the INTCLR register. */ +#define ATON_INTCTRL_INTCLR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTCLR_REG_LSB, ATON_INTCTRL_INTCLR_REG_W, DATA) + + +/** + * Get the description of the REG field of INTCLR register. + * + * \return the description of the REG field of INTCLR register + */ + +static inline const int8_t *ATON_INTCTRL_INTCLR_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTCLR_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTCLR register. + * + * \param[in] reg is the value of the INTCLR register + * + * \return the content of the REG field belonging to INTCLR register + */ + +static inline uint32_t ATON_INTCTRL_INTCLR_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTCLR_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTCLR register. + * + * \param[in] reg is the value of the INTCLR register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTCLR register + */ + +static inline uint32_t ATON_INTCTRL_INTCLR_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTCLR_SET_REG(reg, data); +} + + +/* ***************************************************** INTORMSK0 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTORMSK0 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK0_OFFSET 0x14UL + +/** Reset value of the INTORMSK0 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK0_DT \ + (ATON_INTCTRL_INTORMSK0_REG_DT << ATON_INTCTRL_INTORMSK0_REG_LSB) + + + +/** Description of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_DESC "Interrupt OR mask 0" + +/** Address of the INTORMSK0 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK0_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK0_OFFSET) + +/** Get the content of the INTORMSK0 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK0_ADDR(UNIT))) + +/** Set the content of the INTORMSK0 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTORMSK0 register. + * + * \return the description of INTORMSK0 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK0_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK0_DESC; +} + + +/** + * Get the offset of the INTORMSK0 register. + * + * \return the offset of INTORMSK0 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK0_GetOffset(void) +{ + return ATON_INTCTRL_INTORMSK0_OFFSET; +} + + +/** + * Get the address of the INTORMSK0 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTORMSK0 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK0_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK0_ADDR(instance); +} + + +/** + * Read the content of the INTORMSK0 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTORMSK0 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK0_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK0_GET(instance); +} + + +/** + * Write the content of the INTORMSK0 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTORMSK0_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTORMSK0_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTORMSK0 register ----------------------------------------------------------- */ + +/** Description of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_REG_LSB 0UL + +/** Size in bits of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_REG_AC "RW" + +/** Check whether access to the REG field of the INTORMSK0 register is secured or not. */ +#define ATON_INTCTRL_INTORMSK0_REG_S 0 + +/** Check whether access to the REG field of the INTORMSK0 register is privileged or not. */ +#define ATON_INTCTRL_INTORMSK0_REG_P 0 + +/** Read the content of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK0_REG_LSB, ATON_INTCTRL_INTORMSK0_REG_W) + +/** Modify the content of the REG field of the INTORMSK0 register. */ +#define ATON_INTCTRL_INTORMSK0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK0_REG_LSB, ATON_INTCTRL_INTORMSK0_REG_W, DATA) + + +/** + * Get the description of the REG field of INTORMSK0 register. + * + * \return the description of the REG field of INTORMSK0 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK0_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK0_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTORMSK0 register. + * + * \param[in] reg is the value of the INTORMSK0 register + * + * \return the content of the REG field belonging to INTORMSK0 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK0_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTORMSK0_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTORMSK0 register. + * + * \param[in] reg is the value of the INTORMSK0 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTORMSK0 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK0_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTORMSK0_SET_REG(reg, data); +} + + +/* ***************************************************** INTORMSK1 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTORMSK1 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK1_OFFSET 0x18UL + +/** Reset value of the INTORMSK1 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK1_DT \ + (ATON_INTCTRL_INTORMSK1_REG_DT << ATON_INTCTRL_INTORMSK1_REG_LSB) + + + +/** Description of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_DESC "Interrupt OR mask 1" + +/** Address of the INTORMSK1 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK1_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK1_OFFSET) + +/** Get the content of the INTORMSK1 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK1_ADDR(UNIT))) + +/** Set the content of the INTORMSK1 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTORMSK1 register. + * + * \return the description of INTORMSK1 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK1_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK1_DESC; +} + + +/** + * Get the offset of the INTORMSK1 register. + * + * \return the offset of INTORMSK1 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK1_GetOffset(void) +{ + return ATON_INTCTRL_INTORMSK1_OFFSET; +} + + +/** + * Get the address of the INTORMSK1 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTORMSK1 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK1_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK1_ADDR(instance); +} + + +/** + * Read the content of the INTORMSK1 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTORMSK1 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK1_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK1_GET(instance); +} + + +/** + * Write the content of the INTORMSK1 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTORMSK1_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTORMSK1_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTORMSK1 register ----------------------------------------------------------- */ + +/** Description of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_REG_LSB 0UL + +/** Size in bits of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_REG_AC "RW" + +/** Check whether access to the REG field of the INTORMSK1 register is secured or not. */ +#define ATON_INTCTRL_INTORMSK1_REG_S 0 + +/** Check whether access to the REG field of the INTORMSK1 register is privileged or not. */ +#define ATON_INTCTRL_INTORMSK1_REG_P 0 + +/** Read the content of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK1_REG_LSB, ATON_INTCTRL_INTORMSK1_REG_W) + +/** Modify the content of the REG field of the INTORMSK1 register. */ +#define ATON_INTCTRL_INTORMSK1_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK1_REG_LSB, ATON_INTCTRL_INTORMSK1_REG_W, DATA) + + +/** + * Get the description of the REG field of INTORMSK1 register. + * + * \return the description of the REG field of INTORMSK1 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK1_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK1_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTORMSK1 register. + * + * \param[in] reg is the value of the INTORMSK1 register + * + * \return the content of the REG field belonging to INTORMSK1 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK1_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTORMSK1_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTORMSK1 register. + * + * \param[in] reg is the value of the INTORMSK1 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTORMSK1 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK1_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTORMSK1_SET_REG(reg, data); +} + + +/* ***************************************************** INTORMSK2 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTORMSK2 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK2_OFFSET 0x1cUL + +/** Reset value of the INTORMSK2 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK2_DT \ + (ATON_INTCTRL_INTORMSK2_REG_DT << ATON_INTCTRL_INTORMSK2_REG_LSB) + + + +/** Description of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_DESC "Interrupt OR mask 2" + +/** Address of the INTORMSK2 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK2_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK2_OFFSET) + +/** Get the content of the INTORMSK2 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK2_ADDR(UNIT))) + +/** Set the content of the INTORMSK2 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTORMSK2 register. + * + * \return the description of INTORMSK2 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK2_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK2_DESC; +} + + +/** + * Get the offset of the INTORMSK2 register. + * + * \return the offset of INTORMSK2 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK2_GetOffset(void) +{ + return ATON_INTCTRL_INTORMSK2_OFFSET; +} + + +/** + * Get the address of the INTORMSK2 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK2 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTORMSK2 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK2_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK2_ADDR(instance); +} + + +/** + * Read the content of the INTORMSK2 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK2 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTORMSK2 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK2_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK2_GET(instance); +} + + +/** + * Write the content of the INTORMSK2 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK2 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTORMSK2_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTORMSK2_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTORMSK2 register ----------------------------------------------------------- */ + +/** Description of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_REG_LSB 0UL + +/** Size in bits of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_REG_AC "RW" + +/** Check whether access to the REG field of the INTORMSK2 register is secured or not. */ +#define ATON_INTCTRL_INTORMSK2_REG_S 0 + +/** Check whether access to the REG field of the INTORMSK2 register is privileged or not. */ +#define ATON_INTCTRL_INTORMSK2_REG_P 0 + +/** Read the content of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK2_REG_LSB, ATON_INTCTRL_INTORMSK2_REG_W) + +/** Modify the content of the REG field of the INTORMSK2 register. */ +#define ATON_INTCTRL_INTORMSK2_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK2_REG_LSB, ATON_INTCTRL_INTORMSK2_REG_W, DATA) + + +/** + * Get the description of the REG field of INTORMSK2 register. + * + * \return the description of the REG field of INTORMSK2 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK2_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK2_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTORMSK2 register. + * + * \param[in] reg is the value of the INTORMSK2 register + * + * \return the content of the REG field belonging to INTORMSK2 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK2_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTORMSK2_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTORMSK2 register. + * + * \param[in] reg is the value of the INTORMSK2 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTORMSK2 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK2_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTORMSK2_SET_REG(reg, data); +} + + +/* ***************************************************** INTORMSK3 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTORMSK3 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK3_OFFSET 0x20UL + +/** Reset value of the INTORMSK3 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTORMSK3_DT \ + (ATON_INTCTRL_INTORMSK3_REG_DT << ATON_INTCTRL_INTORMSK3_REG_LSB) + + + +/** Description of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_DESC "Interrupt OR mask 3" + +/** Address of the INTORMSK3 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK3_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK3_OFFSET) + +/** Get the content of the INTORMSK3 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK3_ADDR(UNIT))) + +/** Set the content of the INTORMSK3 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTORMSK3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK3_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTORMSK3 register. + * + * \return the description of INTORMSK3 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK3_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK3_DESC; +} + + +/** + * Get the offset of the INTORMSK3 register. + * + * \return the offset of INTORMSK3 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK3_GetOffset(void) +{ + return ATON_INTCTRL_INTORMSK3_OFFSET; +} + + +/** + * Get the address of the INTORMSK3 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK3 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTORMSK3 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK3_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK3_ADDR(instance); +} + + +/** + * Read the content of the INTORMSK3 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK3 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTORMSK3 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK3_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTORMSK3_GET(instance); +} + + +/** + * Write the content of the INTORMSK3 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK3 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTORMSK3_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTORMSK3_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTORMSK3 register ----------------------------------------------------------- */ + +/** Description of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_REG_LSB 0UL + +/** Size in bits of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_REG_AC "RW" + +/** Check whether access to the REG field of the INTORMSK3 register is secured or not. */ +#define ATON_INTCTRL_INTORMSK3_REG_S 0 + +/** Check whether access to the REG field of the INTORMSK3 register is privileged or not. */ +#define ATON_INTCTRL_INTORMSK3_REG_P 0 + +/** Read the content of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK3_REG_LSB, ATON_INTCTRL_INTORMSK3_REG_W) + +/** Modify the content of the REG field of the INTORMSK3 register. */ +#define ATON_INTCTRL_INTORMSK3_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK3_REG_LSB, ATON_INTCTRL_INTORMSK3_REG_W, DATA) + + +/** + * Get the description of the REG field of INTORMSK3 register. + * + * \return the description of the REG field of INTORMSK3 register + */ + +static inline const int8_t *ATON_INTCTRL_INTORMSK3_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTORMSK3_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTORMSK3 register. + * + * \param[in] reg is the value of the INTORMSK3 register + * + * \return the content of the REG field belonging to INTORMSK3 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK3_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTORMSK3_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTORMSK3 register. + * + * \param[in] reg is the value of the INTORMSK3 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTORMSK3 register + */ + +static inline uint32_t ATON_INTCTRL_INTORMSK3_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTORMSK3_SET_REG(reg, data); +} + + +/* **************************************************** INTANDMSK0 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTANDMSK0 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK0_OFFSET 0x24UL + +/** Reset value of the INTANDMSK0 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK0_DT \ + (ATON_INTCTRL_INTANDMSK0_REG_DT << ATON_INTCTRL_INTANDMSK0_REG_LSB) + + + +/** Description of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_DESC "Interrupt AND mask 0" + +/** Address of the INTANDMSK0 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK0_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK0_OFFSET) + +/** Get the content of the INTANDMSK0 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK0_ADDR(UNIT))) + +/** Set the content of the INTANDMSK0 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTANDMSK0 register. + * + * \return the description of INTANDMSK0 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK0_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK0_DESC; +} + + +/** + * Get the offset of the INTANDMSK0 register. + * + * \return the offset of INTANDMSK0 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK0_GetOffset(void) +{ + return ATON_INTCTRL_INTANDMSK0_OFFSET; +} + + +/** + * Get the address of the INTANDMSK0 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTANDMSK0 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK0_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK0_ADDR(instance); +} + + +/** + * Read the content of the INTANDMSK0 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTANDMSK0 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK0_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK0_GET(instance); +} + + +/** + * Write the content of the INTANDMSK0 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTANDMSK0_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTANDMSK0_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTANDMSK0 register ---------------------------------------------------------- */ + +/** Description of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_REG_LSB 0UL + +/** Size in bits of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_REG_AC "RW" + +/** Check whether access to the REG field of the INTANDMSK0 register is secured or not. */ +#define ATON_INTCTRL_INTANDMSK0_REG_S 0 + +/** Check whether access to the REG field of the INTANDMSK0 register is privileged or not. */ +#define ATON_INTCTRL_INTANDMSK0_REG_P 0 + +/** Read the content of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK0_REG_LSB, ATON_INTCTRL_INTANDMSK0_REG_W) + +/** Modify the content of the REG field of the INTANDMSK0 register. */ +#define ATON_INTCTRL_INTANDMSK0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK0_REG_LSB, ATON_INTCTRL_INTANDMSK0_REG_W, DATA) + + +/** + * Get the description of the REG field of INTANDMSK0 register. + * + * \return the description of the REG field of INTANDMSK0 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK0_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK0_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTANDMSK0 register. + * + * \param[in] reg is the value of the INTANDMSK0 register + * + * \return the content of the REG field belonging to INTANDMSK0 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK0_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTANDMSK0_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTANDMSK0 register. + * + * \param[in] reg is the value of the INTANDMSK0 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTANDMSK0 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK0_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTANDMSK0_SET_REG(reg, data); +} + + +/* **************************************************** INTANDMSK1 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTANDMSK1 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK1_OFFSET 0x28UL + +/** Reset value of the INTANDMSK1 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK1_DT \ + (ATON_INTCTRL_INTANDMSK1_REG_DT << ATON_INTCTRL_INTANDMSK1_REG_LSB) + + + +/** Description of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_DESC "Interrupt AND mask 1" + +/** Address of the INTANDMSK1 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK1_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK1_OFFSET) + +/** Get the content of the INTANDMSK1 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK1_ADDR(UNIT))) + +/** Set the content of the INTANDMSK1 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTANDMSK1 register. + * + * \return the description of INTANDMSK1 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK1_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK1_DESC; +} + + +/** + * Get the offset of the INTANDMSK1 register. + * + * \return the offset of INTANDMSK1 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK1_GetOffset(void) +{ + return ATON_INTCTRL_INTANDMSK1_OFFSET; +} + + +/** + * Get the address of the INTANDMSK1 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTANDMSK1 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK1_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK1_ADDR(instance); +} + + +/** + * Read the content of the INTANDMSK1 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTANDMSK1 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK1_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK1_GET(instance); +} + + +/** + * Write the content of the INTANDMSK1 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTANDMSK1_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTANDMSK1_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTANDMSK1 register ---------------------------------------------------------- */ + +/** Description of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_REG_LSB 0UL + +/** Size in bits of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_REG_AC "RW" + +/** Check whether access to the REG field of the INTANDMSK1 register is secured or not. */ +#define ATON_INTCTRL_INTANDMSK1_REG_S 0 + +/** Check whether access to the REG field of the INTANDMSK1 register is privileged or not. */ +#define ATON_INTCTRL_INTANDMSK1_REG_P 0 + +/** Read the content of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK1_REG_LSB, ATON_INTCTRL_INTANDMSK1_REG_W) + +/** Modify the content of the REG field of the INTANDMSK1 register. */ +#define ATON_INTCTRL_INTANDMSK1_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK1_REG_LSB, ATON_INTCTRL_INTANDMSK1_REG_W, DATA) + + +/** + * Get the description of the REG field of INTANDMSK1 register. + * + * \return the description of the REG field of INTANDMSK1 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK1_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK1_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTANDMSK1 register. + * + * \param[in] reg is the value of the INTANDMSK1 register + * + * \return the content of the REG field belonging to INTANDMSK1 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK1_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTANDMSK1_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTANDMSK1 register. + * + * \param[in] reg is the value of the INTANDMSK1 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTANDMSK1 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK1_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTANDMSK1_SET_REG(reg, data); +} + + +/* **************************************************** INTANDMSK2 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTANDMSK2 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK2_OFFSET 0x2cUL + +/** Reset value of the INTANDMSK2 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK2_DT \ + (ATON_INTCTRL_INTANDMSK2_REG_DT << ATON_INTCTRL_INTANDMSK2_REG_LSB) + + + +/** Description of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_DESC "Interrupt AND mask 2" + +/** Address of the INTANDMSK2 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK2_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK2_OFFSET) + +/** Get the content of the INTANDMSK2 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK2_ADDR(UNIT))) + +/** Set the content of the INTANDMSK2 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTANDMSK2 register. + * + * \return the description of INTANDMSK2 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK2_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK2_DESC; +} + + +/** + * Get the offset of the INTANDMSK2 register. + * + * \return the offset of INTANDMSK2 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK2_GetOffset(void) +{ + return ATON_INTCTRL_INTANDMSK2_OFFSET; +} + + +/** + * Get the address of the INTANDMSK2 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK2 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTANDMSK2 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK2_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK2_ADDR(instance); +} + + +/** + * Read the content of the INTANDMSK2 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK2 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTANDMSK2 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK2_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK2_GET(instance); +} + + +/** + * Write the content of the INTANDMSK2 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK2 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTANDMSK2_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTANDMSK2_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTANDMSK2 register ---------------------------------------------------------- */ + +/** Description of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_REG_LSB 0UL + +/** Size in bits of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_REG_AC "RW" + +/** Check whether access to the REG field of the INTANDMSK2 register is secured or not. */ +#define ATON_INTCTRL_INTANDMSK2_REG_S 0 + +/** Check whether access to the REG field of the INTANDMSK2 register is privileged or not. */ +#define ATON_INTCTRL_INTANDMSK2_REG_P 0 + +/** Read the content of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK2_REG_LSB, ATON_INTCTRL_INTANDMSK2_REG_W) + +/** Modify the content of the REG field of the INTANDMSK2 register. */ +#define ATON_INTCTRL_INTANDMSK2_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK2_REG_LSB, ATON_INTCTRL_INTANDMSK2_REG_W, DATA) + + +/** + * Get the description of the REG field of INTANDMSK2 register. + * + * \return the description of the REG field of INTANDMSK2 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK2_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK2_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTANDMSK2 register. + * + * \param[in] reg is the value of the INTANDMSK2 register + * + * \return the content of the REG field belonging to INTANDMSK2 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK2_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTANDMSK2_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTANDMSK2 register. + * + * \param[in] reg is the value of the INTANDMSK2 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTANDMSK2 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK2_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTANDMSK2_SET_REG(reg, data); +} + + +/* **************************************************** INTANDMSK3 register of one of the INTCTRL Units ***************************************************** */ + +/** Offset of the INTANDMSK3 register from the base address of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK3_OFFSET 0x30UL + +/** Reset value of the INTANDMSK3 register of the INTCTRL Unit. */ +#define ATON_INTCTRL_INTANDMSK3_DT \ + (ATON_INTCTRL_INTANDMSK3_REG_DT << ATON_INTCTRL_INTANDMSK3_REG_LSB) + + + +/** Description of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_DESC "Interrupt AND mask 3" + +/** Address of the INTANDMSK3 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK3_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK3_OFFSET) + +/** Get the content of the INTANDMSK3 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK3_ADDR(UNIT))) + +/** Set the content of the INTANDMSK3 register of one of the INTCTRL Units. */ +#define ATON_INTCTRL_INTANDMSK3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK3_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INTANDMSK3 register. + * + * \return the description of INTANDMSK3 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK3_GetDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK3_DESC; +} + + +/** + * Get the offset of the INTANDMSK3 register. + * + * \return the offset of INTANDMSK3 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK3_GetOffset(void) +{ + return ATON_INTCTRL_INTANDMSK3_OFFSET; +} + + +/** + * Get the address of the INTANDMSK3 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK3 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of INTANDMSK3 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK3_GetAddr(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK3_ADDR(instance); +} + + +/** + * Read the content of the INTANDMSK3 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK3 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of INTANDMSK3 register belonging to Unit having index \e instance among the INTCTRL Units + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK3_Get(uint32_t instance) +{ + return ATON_INTCTRL_INTANDMSK3_GET(instance); +} + + +/** + * Write the content of the INTANDMSK3 register. + * + * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK3 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_INTCTRL_INTANDMSK3_Set(uint32_t instance, uint32_t data) +{ + ATON_INTCTRL_INTANDMSK3_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the INTANDMSK3 register ---------------------------------------------------------- */ + +/** Description of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" + +/** Offset of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_REG_LSB 0UL + +/** Size in bits of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_REG_W (32UL) + +/** Mask for retrieving the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_REG_DT 0xffffffffUL + +/** Access rights of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_REG_AC "RW" + +/** Check whether access to the REG field of the INTANDMSK3 register is secured or not. */ +#define ATON_INTCTRL_INTANDMSK3_REG_S 0 + +/** Check whether access to the REG field of the INTANDMSK3 register is privileged or not. */ +#define ATON_INTCTRL_INTANDMSK3_REG_P 0 + +/** Read the content of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK3_REG_LSB, ATON_INTCTRL_INTANDMSK3_REG_W) + +/** Modify the content of the REG field of the INTANDMSK3 register. */ +#define ATON_INTCTRL_INTANDMSK3_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK3_REG_LSB, ATON_INTCTRL_INTANDMSK3_REG_W, DATA) + + +/** + * Get the description of the REG field of INTANDMSK3 register. + * + * \return the description of the REG field of INTANDMSK3 register + */ + +static inline const int8_t *ATON_INTCTRL_INTANDMSK3_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_INTCTRL_INTANDMSK3_REG_DESC; +} + + +/** + * Read the content of the REG field of the INTANDMSK3 register. + * + * \param[in] reg is the value of the INTANDMSK3 register + * + * \return the content of the REG field belonging to INTANDMSK3 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK3_Get_REG(uint32_t reg) +{ + return ATON_INTCTRL_INTANDMSK3_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the INTANDMSK3 register. + * + * \param[in] reg is the value of the INTANDMSK3 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to INTANDMSK3 register + */ + +static inline uint32_t ATON_INTCTRL_INTANDMSK3_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_INTCTRL_INTANDMSK3_SET_REG(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* ACTIV Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of ACTIV Unit instances. */ +#define ATON_ACTIV_NUM 2 + +/** + * \name Structures, macros and functions of the ACTIV Units + */ +/*@{*/ + +/** + * Registers of the ACTIV Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e ACTIVPARAM register (ReLU parameter for parametric ReLU or thresholded ReLU). */ + uint32_t ACTIVPARAM; + + /** \e FUNC register (Functional parameter). */ + uint32_t FUNC; + + /** \e ACTIVPARAM2 register (additional activation parameters). */ + uint32_t ACTIVPARAM2; + + /** \e FSUB register (Feature data subtract). */ + uint32_t FSUB; + +} ATON_ACTIV_t; + + +/** Return the pointer to one of the ACTIV Units. */ +#define ATON_ACTIV(UNIT) ((ATON_ACTIV_t *)(intptr_t)ATON_ACTIV_BASE(UNIT)) + + +/** Name of one of the ACTIV Units. */ +#define ATON_ACTIV_NAME(UNIT) \ + (((UNIT) == 0) ? "ACTIV0" : \ + (((UNIT) == 1) ? "ACTIV1" : "")) + + +/** Version of the ACTIV Units. */ +#define ATON_ACTIV_VERSION "1.1" + + +/** Description of one of the ACTIV Units. */ +#define ATON_ACTIV_DESC(UNIT) \ + (((UNIT) == 0) ? "Activation Accelerator 0" : \ + (((UNIT) == 1) ? "Activation Accelerator 1" : "")) + + +/** Base address of one of the ACTIV Units. */ +#define ATON_ACTIV_BASE(UNIT) \ + (ATON_BASE + 0x15000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the ACTIV Units. */ +#define ATON_ACTIV_SIZE 0x1000UL + + +/** + * Get the name of one of the ACTIV Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) + * + * \return the name of Unit having index \e instance among the ACTIV Units + */ + +static inline const int8_t *ATON_ACTIV_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"ACTIV0"; + break; + + case 1: + str = (const int8_t *)"ACTIV1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the ACTIV Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) + * + * \return the description of Unit having index \e instance among the ACTIV Units + */ + +static inline const int8_t *ATON_ACTIV_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Activation Accelerator 0"; + break; + + case 1: + str = (const int8_t *)"Activation Accelerator 1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the ACTIV Units. + * + * \return the version of the ACTIV Units + */ + +static inline const int8_t *ATON_ACTIV_GetVersion(void) +{ + return (const int8_t *)ATON_ACTIV_VERSION; +} + + +/** + * Get the base address of one of the ACTIV Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) + * + * \return the base address of Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_GetBase(uint32_t instance) +{ + return ATON_ACTIV_BASE(instance); +} + + +/** + * Get the size in bytes of the ACTIV Units. + * + * \return the size in bytes of the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_GetSize(void) +{ + return ATON_ACTIV_SIZE; +} + + +/* ******************************************************** CTRL register of one of the ACTIV Units ********************************************************* */ + +/** Offset of the CTRL register from the base address of the ACTIV Unit. */ +#define ATON_ACTIV_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the ACTIV Unit. */ +#define ATON_ACTIV_CTRL_DT \ + (ATON_ACTIV_CTRL_EN_DT << ATON_ACTIV_CTRL_EN_LSB) | \ + (ATON_ACTIV_CTRL_CLR_DT << ATON_ACTIV_CTRL_CLR_LSB) | \ + (ATON_ACTIV_CTRL_TYPE_DT << ATON_ACTIV_CTRL_TYPE_LSB) | \ + (ATON_ACTIV_CTRL_FBYTES_DT << ATON_ACTIV_CTRL_FBYTES_LSB) | \ + (ATON_ACTIV_CTRL_FSHIFT_DT << ATON_ACTIV_CTRL_FSHIFT_LSB) | \ + (ATON_ACTIV_CTRL_FROUND_DT << ATON_ACTIV_CTRL_FROUND_LSB) | \ + (ATON_ACTIV_CTRL_FSAT_DT << ATON_ACTIV_CTRL_FSAT_LSB) | \ + (ATON_ACTIV_CTRL_FRNDMODE_DT << ATON_ACTIV_CTRL_FRNDMODE_LSB) | \ + (ATON_ACTIV_CTRL_FOBYTES_DT << ATON_ACTIV_CTRL_FOBYTES_LSB) | \ + (ATON_ACTIV_CTRL_ROUND_DT << ATON_ACTIV_CTRL_ROUND_LSB) | \ + (ATON_ACTIV_CTRL_SAT_DT << ATON_ACTIV_CTRL_SAT_LSB) | \ + (ATON_ACTIV_CTRL_OBYTES_DT << ATON_ACTIV_CTRL_OBYTES_LSB) | \ + (ATON_ACTIV_CTRL_ORNDMODE_DT << ATON_ACTIV_CTRL_ORNDMODE_LSB) | \ + (ATON_ACTIV_CTRL_CONFCLR_DT << ATON_ACTIV_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_ACTIV_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the ACTIV Units. */ +#define ATON_ACTIV_CTRL_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the ACTIV Units. */ +#define ATON_ACTIV_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the ACTIV Units. */ +#define ATON_ACTIV_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_GetOffset(void) +{ + return ATON_ACTIV_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the CTRL register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_CTRL_GetAddr(uint32_t instance) +{ + return ATON_ACTIV_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get(uint32_t instance) +{ + return ATON_ACTIV_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the CTRL register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ACTIV_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_ACTIV_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_EN_DESC "Enable the Activation Unit" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_EN_LSB, ATON_ACTIV_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_EN_LSB, ATON_ACTIV_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_EN(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_CLR_LSB, ATON_ACTIV_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_CLR_LSB, ATON_ACTIV_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_CLR(reg, data); +} + + +/* ------------------------------------------------------------ TYPE field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_TYPE_DESC "Activation type" + +/** Offset of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_TYPE_LSB 2UL + +/** Size in bits of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_TYPE_W (2UL) + +/** Mask for retrieving the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_TYPE_MASK ATON_FIELD_MASK(2UL, 2UL) + +/** Reset value of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_TYPE_DT 0x0UL + +/** Access rights of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_TYPE_AC "RW" + +/** Check whether access to the TYPE field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_TYPE_S 0 + +/** Check whether access to the TYPE field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_TYPE_P 0 + +/** Read the content of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_TYPE_LSB, ATON_ACTIV_CTRL_TYPE_W) + +/** Modify the content of the TYPE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_TYPE_LSB, ATON_ACTIV_CTRL_TYPE_W, DATA) + + +/** + * Get the description of the TYPE field of CTRL register. + * + * \return the description of the TYPE field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the TYPE field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_TYPE(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_TYPE(reg); +} + + +/** + * Write the content of the TYPE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the TYPE field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- FBYTES field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FBYTES_DESC "Input data width in bytes. Valid values are 1,2 or 3 bytes" + +/** Offset of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FBYTES_LSB 6UL + +/** Size in bits of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FBYTES_W (2UL) + +/** Mask for retrieving the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FBYTES_MASK ATON_FIELD_MASK(6UL, 2UL) + +/** Reset value of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FBYTES_DT 0x2UL + +/** Access rights of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FBYTES_AC "RW" + +/** Check whether access to the FBYTES field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_FBYTES_S 0 + +/** Check whether access to the FBYTES field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_FBYTES_P 0 + +/** Read the content of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_FBYTES(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FBYTES_LSB, ATON_ACTIV_CTRL_FBYTES_W) + +/** Modify the content of the FBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_FBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FBYTES_LSB, ATON_ACTIV_CTRL_FBYTES_W, DATA) + + +/** + * Get the description of the FBYTES field of CTRL register. + * + * \return the description of the FBYTES field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_FBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_FBYTES_DESC; +} + + +/** + * Read the content of the FBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_FBYTES(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_FBYTES(reg); +} + + +/** + * Write the content of the FBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_FBYTES(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_FBYTES(reg, data); +} + + +/* ----------------------------------------------------------- FSHIFT field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSHIFT_DESC "Input feature data shift. Range [0-40]. For no shift, set to 16" + +/** Offset of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSHIFT_LSB 8UL + +/** Size in bits of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSHIFT_W (6UL) + +/** Mask for retrieving the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSHIFT_MASK ATON_FIELD_MASK(8UL, 6UL) + +/** Reset value of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSHIFT_DT 0x10UL + +/** Access rights of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSHIFT_AC "RW" + +/** Check whether access to the FSHIFT field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_FSHIFT_S 0 + +/** Check whether access to the FSHIFT field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_FSHIFT_P 0 + +/** Read the content of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_FSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FSHIFT_LSB, ATON_ACTIV_CTRL_FSHIFT_W) + +/** Modify the content of the FSHIFT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_FSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FSHIFT_LSB, ATON_ACTIV_CTRL_FSHIFT_W, DATA) + + +/** + * Get the description of the FSHIFT field of CTRL register. + * + * \return the description of the FSHIFT field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_FSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_FSHIFT_DESC; +} + + +/** + * Read the content of the FSHIFT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSHIFT field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_FSHIFT(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_FSHIFT(reg); +} + + +/** + * Write the content of the FSHIFT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the FSHIFT field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_FSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_FSHIFT(reg, data); +} + + +/* ----------------------------------------------------------- FROUND field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FROUND_DESC "Input feature data rounding control,1=enable,0=disable" + +/** Offset of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FROUND_LSB 14UL + +/** Size in bits of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FROUND_W (1UL) + +/** Mask for retrieving the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FROUND_MASK ATON_FIELD_MASK(14UL, 1UL) + +/** Reset value of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FROUND_DT 0x0UL + +/** Access rights of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FROUND_AC "RW" + +/** Check whether access to the FROUND field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_FROUND_S 0 + +/** Check whether access to the FROUND field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_FROUND_P 0 + +/** Read the content of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_FROUND(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FROUND_LSB, ATON_ACTIV_CTRL_FROUND_W) + +/** Modify the content of the FROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_FROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FROUND_LSB, ATON_ACTIV_CTRL_FROUND_W, DATA) + + +/** + * Get the description of the FROUND field of CTRL register. + * + * \return the description of the FROUND field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_FROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_FROUND_DESC; +} + + +/** + * Read the content of the FROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_FROUND(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_FROUND(reg); +} + + +/** + * Write the content of the FROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_FROUND(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_FROUND(reg, data); +} + + +/* ------------------------------------------------------------ FSAT field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSAT_DESC "Input feature data saturation control,1=enable,0=disable" + +/** Offset of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSAT_LSB 15UL + +/** Size in bits of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSAT_W (1UL) + +/** Mask for retrieving the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSAT_MASK ATON_FIELD_MASK(15UL, 1UL) + +/** Reset value of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSAT_DT 0x0UL + +/** Access rights of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FSAT_AC "RW" + +/** Check whether access to the FSAT field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_FSAT_S 0 + +/** Check whether access to the FSAT field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_FSAT_P 0 + +/** Read the content of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_FSAT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FSAT_LSB, ATON_ACTIV_CTRL_FSAT_W) + +/** Modify the content of the FSAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_FSAT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FSAT_LSB, ATON_ACTIV_CTRL_FSAT_W, DATA) + + +/** + * Get the description of the FSAT field of CTRL register. + * + * \return the description of the FSAT field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_FSAT_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_FSAT_DESC; +} + + +/** + * Read the content of the FSAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSAT field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_FSAT(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_FSAT(reg); +} + + +/** + * Write the content of the FSAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSAT field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_FSAT(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_FSAT(reg, data); +} + + +/* ---------------------------------------------------------- FRNDMODE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FRNDMODE_DESC "Input feature round mode. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FRNDMODE_LSB 16UL + +/** Size in bits of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FRNDMODE_W (2UL) + +/** Mask for retrieving the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FRNDMODE_MASK ATON_FIELD_MASK(16UL, 2UL) + +/** Reset value of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FRNDMODE_DT 0x0UL + +/** Access rights of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FRNDMODE_AC "RW" + +/** Check whether access to the FRNDMODE field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_FRNDMODE_S 0 + +/** Check whether access to the FRNDMODE field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_FRNDMODE_P 0 + +/** Read the content of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_FRNDMODE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FRNDMODE_LSB, ATON_ACTIV_CTRL_FRNDMODE_W) + +/** Modify the content of the FRNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_FRNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FRNDMODE_LSB, ATON_ACTIV_CTRL_FRNDMODE_W, DATA) + + +/** + * Get the description of the FRNDMODE field of CTRL register. + * + * \return the description of the FRNDMODE field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_FRNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_FRNDMODE_DESC; +} + + +/** + * Read the content of the FRNDMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FRNDMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_FRNDMODE(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_FRNDMODE(reg); +} + + +/** + * Write the content of the FRNDMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FRNDMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_FRNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_FRNDMODE(reg, data); +} + + +/* ----------------------------------------------------------- FOBYTES field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FOBYTES_DESC "Input feature out bytes after shift. Valid values are 1 or 2 bytes" + +/** Offset of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FOBYTES_LSB 18UL + +/** Size in bits of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FOBYTES_W (2UL) + +/** Mask for retrieving the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FOBYTES_MASK ATON_FIELD_MASK(18UL, 2UL) + +/** Reset value of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FOBYTES_DT 0x2UL + +/** Access rights of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_FOBYTES_AC "RW" + +/** Check whether access to the FOBYTES field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_FOBYTES_S 0 + +/** Check whether access to the FOBYTES field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_FOBYTES_P 0 + +/** Read the content of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_FOBYTES(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FOBYTES_LSB, ATON_ACTIV_CTRL_FOBYTES_W) + +/** Modify the content of the FOBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_FOBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FOBYTES_LSB, ATON_ACTIV_CTRL_FOBYTES_W, DATA) + + +/** + * Get the description of the FOBYTES field of CTRL register. + * + * \return the description of the FOBYTES field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_FOBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_FOBYTES_DESC; +} + + +/** + * Read the content of the FOBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FOBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_FOBYTES(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_FOBYTES(reg); +} + + +/** + * Write the content of the FOBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FOBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_FOBYTES(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_FOBYTES(reg, data); +} + + +/* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ROUND_DESC "output rounding control, 1=enable,0=disable" + +/** Offset of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ROUND_LSB 20UL + +/** Size in bits of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ROUND_W (1UL) + +/** Mask for retrieving the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ROUND_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ROUND_DT 0x0UL + +/** Access rights of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ROUND_AC "RW" + +/** Check whether access to the ROUND field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_ROUND_S 0 + +/** Check whether access to the ROUND field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_ROUND_P 0 + +/** Read the content of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_ROUND_LSB, ATON_ACTIV_CTRL_ROUND_W) + +/** Modify the content of the ROUND field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_ROUND_LSB, ATON_ACTIV_CTRL_ROUND_W, DATA) + + +/** + * Get the description of the ROUND field of CTRL register. + * + * \return the description of the ROUND field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_ROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_ROUND_DESC; +} + + +/** + * Read the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_ROUND(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_ROUND(reg); +} + + +/** + * Write the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_ROUND(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_ROUND(reg, data); +} + + +/* ------------------------------------------------------------- SAT field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SAT_DESC "output saturation control,1=enable,0=disable" + +/** Offset of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SAT_LSB 21UL + +/** Size in bits of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SAT_W (1UL) + +/** Mask for retrieving the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SAT_MASK ATON_FIELD_MASK(21UL, 1UL) + +/** Reset value of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SAT_DT 0x0UL + +/** Access rights of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SAT_AC "RW" + +/** Check whether access to the SAT field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_SAT_S 0 + +/** Check whether access to the SAT field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_SAT_P 0 + +/** Read the content of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_SAT_LSB, ATON_ACTIV_CTRL_SAT_W) + +/** Modify the content of the SAT field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_SAT_LSB, ATON_ACTIV_CTRL_SAT_W, DATA) + + +/** + * Get the description of the SAT field of CTRL register. + * + * \return the description of the SAT field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_SAT_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_SAT_DESC; +} + + +/** + * Read the content of the SAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SAT field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_SAT(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_SAT(reg); +} + + +/** + * Write the content of the SAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SAT field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_SAT(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_SAT(reg, data); +} + + +/* ----------------------------------------------------------- OBYTES field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_OBYTES_DESC "number of output bytes:1, 2 or 3" + +/** Offset of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_OBYTES_LSB 22UL + +/** Size in bits of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_OBYTES_W (2UL) + +/** Mask for retrieving the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_OBYTES_MASK ATON_FIELD_MASK(22UL, 2UL) + +/** Reset value of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_OBYTES_DT 0x2UL + +/** Access rights of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_OBYTES_AC "RW" + +/** Check whether access to the OBYTES field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_OBYTES_S 0 + +/** Check whether access to the OBYTES field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_OBYTES_P 0 + +/** Read the content of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_OBYTES_LSB, ATON_ACTIV_CTRL_OBYTES_W) + +/** Modify the content of the OBYTES field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_OBYTES_LSB, ATON_ACTIV_CTRL_OBYTES_W, DATA) + + +/** + * Get the description of the OBYTES field of CTRL register. + * + * \return the description of the OBYTES field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_OBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_OBYTES_DESC; +} + + +/** + * Read the content of the OBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the OBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_OBYTES(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_OBYTES(reg); +} + + +/** + * Write the content of the OBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the OBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_OBYTES(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_OBYTES(reg, data); +} + + +/* ---------------------------------------------------------- ORNDMODE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ORNDMODE_DESC "output rounding mode. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ORNDMODE_LSB 24UL + +/** Size in bits of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ORNDMODE_W (2UL) + +/** Mask for retrieving the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ORNDMODE_MASK ATON_FIELD_MASK(24UL, 2UL) + +/** Reset value of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ORNDMODE_DT 0x0UL + +/** Access rights of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_ORNDMODE_AC "RW" + +/** Check whether access to the ORNDMODE field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_ORNDMODE_S 0 + +/** Check whether access to the ORNDMODE field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_ORNDMODE_P 0 + +/** Read the content of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_ORNDMODE_LSB, ATON_ACTIV_CTRL_ORNDMODE_W) + +/** Modify the content of the ORNDMODE field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_ORNDMODE_LSB, ATON_ACTIV_CTRL_ORNDMODE_W, DATA) + + +/** + * Get the description of the ORNDMODE field of CTRL register. + * + * \return the description of the ORNDMODE field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_ORNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_ORNDMODE_DESC; +} + + +/** + * Read the content of the ORNDMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ORNDMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_ORNDMODE(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_ORNDMODE(reg); +} + + +/** + * Write the content of the ORNDMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ORNDMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_ORNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_ORNDMODE(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CONFCLR_DESC "Clear configuration registers (auto-cleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_ACTIV_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_ACTIV_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_CONFCLR_LSB, ATON_ACTIV_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_ACTIV_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_CONFCLR_LSB, ATON_ACTIV_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_ACTIV_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_ACTIV_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ACTIV_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_CTRL_SET_CONFCLR(reg, data); +} + + +/* ******************************************************* VERSION register of one of the ACTIV Units ******************************************************* */ + +/** Offset of the VERSION register from the base address of the ACTIV Unit. */ +#define ATON_ACTIV_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the ACTIV Unit. */ +#define ATON_ACTIV_VERSION_DT \ + (ATON_ACTIV_VERSION_TYPE_DT << ATON_ACTIV_VERSION_TYPE_LSB) | \ + (ATON_ACTIV_VERSION_MINOR_DT << ATON_ACTIV_VERSION_MINOR_LSB) | \ + (ATON_ACTIV_VERSION_MAJOR_DT << ATON_ACTIV_VERSION_MAJOR_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_ACTIV_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the ACTIV Units. */ +#define ATON_ACTIV_VERSION_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the ACTIV Units. */ +#define ATON_ACTIV_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_ACTIV_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_ACTIV_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_ACTIV_VERSION_GetOffset(void) +{ + return ATON_ACTIV_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the VERSION register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_VERSION_GetAddr(uint32_t instance) +{ + return ATON_ACTIV_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_VERSION_Get(uint32_t instance) +{ + return ATON_ACTIV_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_TYPE_DT 0x1bUL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_ACTIV_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_ACTIV_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_ACTIV_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_VERSION_TYPE_LSB, ATON_ACTIV_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_ACTIV_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_ACTIV_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_ACTIV_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MINOR_DT 0x1UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_ACTIV_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_ACTIV_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_VERSION_MINOR_LSB, ATON_ACTIV_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_ACTIV_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_ACTIV_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_ACTIV_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_ACTIV_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_ACTIV_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_ACTIV_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_VERSION_MAJOR_LSB, ATON_ACTIV_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_ACTIV_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_ACTIV_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_ACTIV_VERSION_GET_MAJOR(reg); +} + + +/* ***************************************************** ACTIVPARAM register of one of the ACTIV Units ****************************************************** */ + +/** Offset of the ACTIVPARAM register from the base address of the ACTIV Unit. */ +#define ATON_ACTIV_ACTIVPARAM_OFFSET 0x8UL + +/** Reset value of the ACTIVPARAM register of the ACTIV Unit. */ +#define ATON_ACTIV_ACTIVPARAM_DT \ + (ATON_ACTIV_ACTIVPARAM_PARAM_DT << ATON_ACTIV_ACTIVPARAM_PARAM_LSB) | \ + (ATON_ACTIV_ACTIVPARAM_FUNC_DT << ATON_ACTIV_ACTIVPARAM_FUNC_LSB) + + + +/** Description of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_DESC "ReLU parameter for parametric ReLU or thresholded ReLU" + +/** Address of the ACTIVPARAM register of one of the ACTIV Units. */ +#define ATON_ACTIV_ACTIVPARAM_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ACTIVPARAM_OFFSET) + +/** Get the content of the ACTIVPARAM register of one of the ACTIV Units. */ +#define ATON_ACTIV_ACTIVPARAM_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM_ADDR(UNIT))) + +/** Set the content of the ACTIVPARAM register of one of the ACTIV Units. */ +#define ATON_ACTIV_ACTIVPARAM_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ACTIVPARAM register. + * + * \return the description of ACTIVPARAM register + */ + +static inline const int8_t *ATON_ACTIV_ACTIVPARAM_GetDesc(void) +{ + return (const int8_t *)ATON_ACTIV_ACTIVPARAM_DESC; +} + + +/** + * Get the offset of the ACTIVPARAM register. + * + * \return the offset of ACTIVPARAM register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_GetOffset(void) +{ + return ATON_ACTIV_ACTIVPARAM_OFFSET; +} + + +/** + * Get the address of the ACTIVPARAM register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of ACTIVPARAM register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_GetAddr(uint32_t instance) +{ + return ATON_ACTIV_ACTIVPARAM_ADDR(instance); +} + + +/** + * Read the content of the ACTIVPARAM register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of ACTIVPARAM register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_Get(uint32_t instance) +{ + return ATON_ACTIV_ACTIVPARAM_GET(instance); +} + + +/** + * Write the content of the ACTIVPARAM register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ACTIV_ACTIVPARAM_Set(uint32_t instance, uint32_t data) +{ + ATON_ACTIV_ACTIVPARAM_SET(instance, data); +} + + +/* --------------------------------------------------------- PARAM field of the ACTIVPARAM register --------------------------------------------------------- */ + +/** Description of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_DESC "ReLU parameter" + +/** Offset of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_LSB 0UL + +/** Size in bits of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_W (16UL) + +/** Mask for retrieving the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_DT 0x0UL + +/** Access rights of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_AC "RW" + +/** Check whether access to the PARAM field of the ACTIVPARAM register is secured or not. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_S 0 + +/** Check whether access to the PARAM field of the ACTIVPARAM register is privileged or not. */ +#define ATON_ACTIV_ACTIVPARAM_PARAM_P 0 + +/** Read the content of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_GET_PARAM(REG) ATON_GET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_PARAM_LSB, ATON_ACTIV_ACTIVPARAM_PARAM_W) + +/** Modify the content of the PARAM field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_SET_PARAM(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_PARAM_LSB, ATON_ACTIV_ACTIVPARAM_PARAM_W, DATA) + + +/** + * Get the description of the PARAM field of ACTIVPARAM register. + * + * \return the description of the PARAM field of ACTIVPARAM register + */ + +static inline const int8_t *ATON_ACTIV_ACTIVPARAM_PARAM_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_ACTIVPARAM_PARAM_DESC; +} + + +/** + * Read the content of the PARAM field of the ACTIVPARAM register. + * + * \param[in] reg is the value of the ACTIVPARAM register + * + * \return the content of the PARAM field belonging to ACTIVPARAM register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_Get_PARAM(uint32_t reg) +{ + return ATON_ACTIV_ACTIVPARAM_GET_PARAM(reg); +} + + +/** + * Write the content of the PARAM field of the ACTIVPARAM register. + * + * \param[in] reg is the value of the ACTIVPARAM register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the PARAM field belonging to ACTIVPARAM register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_Set_PARAM(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_ACTIVPARAM_SET_PARAM(reg, data); +} + + +/* --------------------------------------------------------- FUNC field of the ACTIVPARAM register ---------------------------------------------------------- */ + +/** Description of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_DESC "function input range normalization left shift parameter" + +/** Offset of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_LSB 16UL + +/** Size in bits of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_W (4UL) + +/** Mask for retrieving the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_MASK ATON_FIELD_MASK(16UL, 4UL) + +/** Reset value of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_DT 0x0UL + +/** Access rights of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_AC "RW" + +/** Check whether access to the FUNC field of the ACTIVPARAM register is secured or not. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_S 0 + +/** Check whether access to the FUNC field of the ACTIVPARAM register is privileged or not. */ +#define ATON_ACTIV_ACTIVPARAM_FUNC_P 0 + +/** Read the content of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_GET_FUNC(REG) ATON_GET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_FUNC_LSB, ATON_ACTIV_ACTIVPARAM_FUNC_W) + +/** Modify the content of the FUNC field of the ACTIVPARAM register. */ +#define ATON_ACTIV_ACTIVPARAM_SET_FUNC(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_FUNC_LSB, ATON_ACTIV_ACTIVPARAM_FUNC_W, DATA) + + +/** + * Get the description of the FUNC field of ACTIVPARAM register. + * + * \return the description of the FUNC field of ACTIVPARAM register + */ + +static inline const int8_t *ATON_ACTIV_ACTIVPARAM_FUNC_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_ACTIVPARAM_FUNC_DESC; +} + + +/** + * Read the content of the FUNC field of the ACTIVPARAM register. + * + * \param[in] reg is the value of the ACTIVPARAM register + * + * \return the content of the FUNC field belonging to ACTIVPARAM register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_Get_FUNC(uint32_t reg) +{ + return ATON_ACTIV_ACTIVPARAM_GET_FUNC(reg); +} + + +/** + * Write the content of the FUNC field of the ACTIVPARAM register. + * + * \param[in] reg is the value of the ACTIVPARAM register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the FUNC field belonging to ACTIVPARAM register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM_Set_FUNC(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_ACTIVPARAM_SET_FUNC(reg, data); +} + + +/* ******************************************************** FUNC register of one of the ACTIV Units ********************************************************* */ + +/** Offset of the FUNC register from the base address of the ACTIV Unit. */ +#define ATON_ACTIV_FUNC_OFFSET 0xcUL + +/** Reset value of the FUNC register of the ACTIV Unit. */ +#define ATON_ACTIV_FUNC_DT \ + (ATON_ACTIV_FUNC_OUTSHIFT_DT << ATON_ACTIV_FUNC_OUTSHIFT_LSB) | \ + (ATON_ACTIV_FUNC_CSHIFT_DT << ATON_ACTIV_FUNC_CSHIFT_LSB) | \ + (ATON_ACTIV_FUNC_BSHIFT_DT << ATON_ACTIV_FUNC_BSHIFT_LSB) | \ + (ATON_ACTIV_FUNC_SIGNEDOP_DT << ATON_ACTIV_FUNC_SIGNEDOP_LSB) | \ + (ATON_ACTIV_FUNC_BWIDTH_DT << ATON_ACTIV_FUNC_BWIDTH_LSB) + + + +/** Description of the FUNC register. */ +#define ATON_ACTIV_FUNC_DESC "Functional parameter" + +/** Address of the FUNC register of one of the ACTIV Units. */ +#define ATON_ACTIV_FUNC_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_FUNC_OFFSET) + +/** Get the content of the FUNC register of one of the ACTIV Units. */ +#define ATON_ACTIV_FUNC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FUNC_ADDR(UNIT))) + +/** Set the content of the FUNC register of one of the ACTIV Units. */ +#define ATON_ACTIV_FUNC_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FUNC_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FUNC register. + * + * \return the description of FUNC register + */ + +static inline const int8_t *ATON_ACTIV_FUNC_GetDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FUNC_DESC; +} + + +/** + * Get the offset of the FUNC register. + * + * \return the offset of FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_GetOffset(void) +{ + return ATON_ACTIV_FUNC_OFFSET; +} + + +/** + * Get the address of the FUNC register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FUNC register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of FUNC register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_FUNC_GetAddr(uint32_t instance) +{ + return ATON_ACTIV_FUNC_ADDR(instance); +} + + +/** + * Read the content of the FUNC register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FUNC register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of FUNC register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_FUNC_Get(uint32_t instance) +{ + return ATON_ACTIV_FUNC_GET(instance); +} + + +/** + * Write the content of the FUNC register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FUNC register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ACTIV_FUNC_Set(uint32_t instance, uint32_t data) +{ + ATON_ACTIV_FUNC_SET(instance, data); +} + + +/* ---------------------------------------------------------- OUTSHIFT field of the FUNC register ----------------------------------------------------------- */ + +/** Description of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_DESC "Optional right shift to be applied to the function evaluator final result" + +/** Offset of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_LSB 0UL + +/** Size in bits of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_W (6UL) + +/** Mask for retrieving the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_MASK ATON_FIELD_MASK(0UL, 6UL) + +/** Reset value of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_DT 0x0UL + +/** Access rights of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_AC "RW" + +/** Check whether access to the OUTSHIFT field of the FUNC register is secured or not. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_S 0 + +/** Check whether access to the OUTSHIFT field of the FUNC register is privileged or not. */ +#define ATON_ACTIV_FUNC_OUTSHIFT_P 0 + +/** Read the content of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_GET_OUTSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_OUTSHIFT_LSB, ATON_ACTIV_FUNC_OUTSHIFT_W) + +/** Modify the content of the OUTSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SET_OUTSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_OUTSHIFT_LSB, ATON_ACTIV_FUNC_OUTSHIFT_W, DATA) + + +/** + * Get the description of the OUTSHIFT field of FUNC register. + * + * \return the description of the OUTSHIFT field of FUNC register + */ + +static inline const int8_t *ATON_ACTIV_FUNC_OUTSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FUNC_OUTSHIFT_DESC; +} + + +/** + * Read the content of the OUTSHIFT field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * + * \return the content of the OUTSHIFT field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Get_OUTSHIFT(uint32_t reg) +{ + return ATON_ACTIV_FUNC_GET_OUTSHIFT(reg); +} + + +/** + * Write the content of the OUTSHIFT field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the OUTSHIFT field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Set_OUTSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_FUNC_SET_OUTSHIFT(reg, data); +} + + +/* ----------------------------------------------------------- CSHIFT field of the FUNC register ------------------------------------------------------------ */ + +/** Description of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_CSHIFT_DESC "Optional left shift to be applied to coefficient C" + +/** Offset of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_CSHIFT_LSB 6UL + +/** Size in bits of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_CSHIFT_W (6UL) + +/** Mask for retrieving the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_CSHIFT_MASK ATON_FIELD_MASK(6UL, 6UL) + +/** Reset value of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_CSHIFT_DT 0x0UL + +/** Access rights of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_CSHIFT_AC "RW" + +/** Check whether access to the CSHIFT field of the FUNC register is secured or not. */ +#define ATON_ACTIV_FUNC_CSHIFT_S 0 + +/** Check whether access to the CSHIFT field of the FUNC register is privileged or not. */ +#define ATON_ACTIV_FUNC_CSHIFT_P 0 + +/** Read the content of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_GET_CSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_CSHIFT_LSB, ATON_ACTIV_FUNC_CSHIFT_W) + +/** Modify the content of the CSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SET_CSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_CSHIFT_LSB, ATON_ACTIV_FUNC_CSHIFT_W, DATA) + + +/** + * Get the description of the CSHIFT field of FUNC register. + * + * \return the description of the CSHIFT field of FUNC register + */ + +static inline const int8_t *ATON_ACTIV_FUNC_CSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FUNC_CSHIFT_DESC; +} + + +/** + * Read the content of the CSHIFT field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * + * \return the content of the CSHIFT field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Get_CSHIFT(uint32_t reg) +{ + return ATON_ACTIV_FUNC_GET_CSHIFT(reg); +} + + +/** + * Write the content of the CSHIFT field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the CSHIFT field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Set_CSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_FUNC_SET_CSHIFT(reg, data); +} + + +/* ----------------------------------------------------------- BSHIFT field of the FUNC register ------------------------------------------------------------ */ + +/** Description of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BSHIFT_DESC "Optional left shift to be applied to coefficient B" + +/** Offset of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BSHIFT_LSB 12UL + +/** Size in bits of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BSHIFT_W (5UL) + +/** Mask for retrieving the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BSHIFT_MASK ATON_FIELD_MASK(12UL, 5UL) + +/** Reset value of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BSHIFT_DT 0x0UL + +/** Access rights of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BSHIFT_AC "RW" + +/** Check whether access to the BSHIFT field of the FUNC register is secured or not. */ +#define ATON_ACTIV_FUNC_BSHIFT_S 0 + +/** Check whether access to the BSHIFT field of the FUNC register is privileged or not. */ +#define ATON_ACTIV_FUNC_BSHIFT_P 0 + +/** Read the content of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_GET_BSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_BSHIFT_LSB, ATON_ACTIV_FUNC_BSHIFT_W) + +/** Modify the content of the BSHIFT field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SET_BSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_BSHIFT_LSB, ATON_ACTIV_FUNC_BSHIFT_W, DATA) + + +/** + * Get the description of the BSHIFT field of FUNC register. + * + * \return the description of the BSHIFT field of FUNC register + */ + +static inline const int8_t *ATON_ACTIV_FUNC_BSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FUNC_BSHIFT_DESC; +} + + +/** + * Read the content of the BSHIFT field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * + * \return the content of the BSHIFT field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Get_BSHIFT(uint32_t reg) +{ + return ATON_ACTIV_FUNC_GET_BSHIFT(reg); +} + + +/** + * Write the content of the BSHIFT field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the BSHIFT field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Set_BSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_FUNC_SET_BSHIFT(reg, data); +} + + +/* ---------------------------------------------------------- SIGNEDOP field of the FUNC register ----------------------------------------------------------- */ + +/** Description of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_DESC "Signed/unsigned activations" + +/** Offset of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_LSB 20UL + +/** Size in bits of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_W (1UL) + +/** Mask for retrieving the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_DT 0x0UL + +/** Access rights of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_AC "RW" + +/** Check whether access to the SIGNEDOP field of the FUNC register is secured or not. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_S 0 + +/** Check whether access to the SIGNEDOP field of the FUNC register is privileged or not. */ +#define ATON_ACTIV_FUNC_SIGNEDOP_P 0 + +/** Read the content of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_GET_SIGNEDOP(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_SIGNEDOP_LSB, ATON_ACTIV_FUNC_SIGNEDOP_W) + +/** Modify the content of the SIGNEDOP field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SET_SIGNEDOP(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_SIGNEDOP_LSB, ATON_ACTIV_FUNC_SIGNEDOP_W, DATA) + + +/** + * Get the description of the SIGNEDOP field of FUNC register. + * + * \return the description of the SIGNEDOP field of FUNC register + */ + +static inline const int8_t *ATON_ACTIV_FUNC_SIGNEDOP_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FUNC_SIGNEDOP_DESC; +} + + +/** + * Read the content of the SIGNEDOP field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * + * \return the content of the SIGNEDOP field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Get_SIGNEDOP(uint32_t reg) +{ + return ATON_ACTIV_FUNC_GET_SIGNEDOP(reg); +} + + +/** + * Write the content of the SIGNEDOP field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SIGNEDOP field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Set_SIGNEDOP(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_FUNC_SET_SIGNEDOP(reg, data); +} + + +/* ----------------------------------------------------------- BWIDTH field of the FUNC register ------------------------------------------------------------ */ + +/** Description of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BWIDTH_DESC "Number of MSB bits of the input activation to be used to address ROM0. This field configures the number of outer segments (max outer segments = 32). Valid values range = 0,1,2,3,4 and 5 corresponding to 1,2,4,8,16 and 32 outer segment(s) respectively" + +/** Offset of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BWIDTH_LSB 23UL + +/** Size in bits of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BWIDTH_W (3UL) + +/** Mask for retrieving the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BWIDTH_MASK ATON_FIELD_MASK(23UL, 3UL) + +/** Reset value of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BWIDTH_DT 0x0UL + +/** Access rights of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_BWIDTH_AC "RW" + +/** Check whether access to the BWIDTH field of the FUNC register is secured or not. */ +#define ATON_ACTIV_FUNC_BWIDTH_S 0 + +/** Check whether access to the BWIDTH field of the FUNC register is privileged or not. */ +#define ATON_ACTIV_FUNC_BWIDTH_P 0 + +/** Read the content of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_GET_BWIDTH(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_BWIDTH_LSB, ATON_ACTIV_FUNC_BWIDTH_W) + +/** Modify the content of the BWIDTH field of the FUNC register. */ +#define ATON_ACTIV_FUNC_SET_BWIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_BWIDTH_LSB, ATON_ACTIV_FUNC_BWIDTH_W, DATA) + + +/** + * Get the description of the BWIDTH field of FUNC register. + * + * \return the description of the BWIDTH field of FUNC register + */ + +static inline const int8_t *ATON_ACTIV_FUNC_BWIDTH_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FUNC_BWIDTH_DESC; +} + + +/** + * Read the content of the BWIDTH field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * + * \return the content of the BWIDTH field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Get_BWIDTH(uint32_t reg) +{ + return ATON_ACTIV_FUNC_GET_BWIDTH(reg); +} + + +/** + * Write the content of the BWIDTH field of the FUNC register. + * + * \param[in] reg is the value of the FUNC register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the BWIDTH field belonging to FUNC register + */ + +static inline uint32_t ATON_ACTIV_FUNC_Set_BWIDTH(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_FUNC_SET_BWIDTH(reg, data); +} + + +/* ***************************************************** ACTIVPARAM2 register of one of the ACTIV Units ***************************************************** */ + +/** Offset of the ACTIVPARAM2 register from the base address of the ACTIV Unit. */ +#define ATON_ACTIV_ACTIVPARAM2_OFFSET 0x10UL + +/** Reset value of the ACTIVPARAM2 register of the ACTIV Unit. */ +#define ATON_ACTIV_ACTIVPARAM2_DT \ + (ATON_ACTIV_ACTIVPARAM2_PARAM2_DT << ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB) + + + +/** Description of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_DESC "additional activation parameters" + +/** Address of the ACTIVPARAM2 register of one of the ACTIV Units. */ +#define ATON_ACTIV_ACTIVPARAM2_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ACTIVPARAM2_OFFSET) + +/** Get the content of the ACTIVPARAM2 register of one of the ACTIV Units. */ +#define ATON_ACTIV_ACTIVPARAM2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM2_ADDR(UNIT))) + +/** Set the content of the ACTIVPARAM2 register of one of the ACTIV Units. */ +#define ATON_ACTIV_ACTIVPARAM2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ACTIVPARAM2 register. + * + * \return the description of ACTIVPARAM2 register + */ + +static inline const int8_t *ATON_ACTIV_ACTIVPARAM2_GetDesc(void) +{ + return (const int8_t *)ATON_ACTIV_ACTIVPARAM2_DESC; +} + + +/** + * Get the offset of the ACTIVPARAM2 register. + * + * \return the offset of ACTIVPARAM2 register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM2_GetOffset(void) +{ + return ATON_ACTIV_ACTIVPARAM2_OFFSET; +} + + +/** + * Get the address of the ACTIVPARAM2 register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM2 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of ACTIVPARAM2 register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM2_GetAddr(uint32_t instance) +{ + return ATON_ACTIV_ACTIVPARAM2_ADDR(instance); +} + + +/** + * Read the content of the ACTIVPARAM2 register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM2 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of ACTIVPARAM2 register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM2_Get(uint32_t instance) +{ + return ATON_ACTIV_ACTIVPARAM2_GET(instance); +} + + +/** + * Write the content of the ACTIVPARAM2 register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM2 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ACTIV_ACTIVPARAM2_Set(uint32_t instance, uint32_t data) +{ + ATON_ACTIV_ACTIVPARAM2_SET(instance, data); +} + + +/* -------------------------------------------------------- PARAM2 field of the ACTIVPARAM2 register -------------------------------------------------------- */ + +/** Description of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_DESC "zero offset for TRELU operation for use in scale/offset integer arithmetic" + +/** Offset of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB 0UL + +/** Size in bits of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_W (16UL) + +/** Mask for retrieving the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_DT 0x0UL + +/** Access rights of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_AC "RW" + +/** Check whether access to the PARAM2 field of the ACTIVPARAM2 register is secured or not. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_S 0 + +/** Check whether access to the PARAM2 field of the ACTIVPARAM2 register is privileged or not. */ +#define ATON_ACTIV_ACTIVPARAM2_PARAM2_P 0 + +/** Read the content of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_GET_PARAM2(REG) ATON_GET_FIELD(REG, ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB, ATON_ACTIV_ACTIVPARAM2_PARAM2_W) + +/** Modify the content of the PARAM2 field of the ACTIVPARAM2 register. */ +#define ATON_ACTIV_ACTIVPARAM2_SET_PARAM2(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB, ATON_ACTIV_ACTIVPARAM2_PARAM2_W, DATA) + + +/** + * Get the description of the PARAM2 field of ACTIVPARAM2 register. + * + * \return the description of the PARAM2 field of ACTIVPARAM2 register + */ + +static inline const int8_t *ATON_ACTIV_ACTIVPARAM2_PARAM2_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_ACTIVPARAM2_PARAM2_DESC; +} + + +/** + * Read the content of the PARAM2 field of the ACTIVPARAM2 register. + * + * \param[in] reg is the value of the ACTIVPARAM2 register + * + * \return the content of the PARAM2 field belonging to ACTIVPARAM2 register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM2_Get_PARAM2(uint32_t reg) +{ + return ATON_ACTIV_ACTIVPARAM2_GET_PARAM2(reg); +} + + +/** + * Write the content of the PARAM2 field of the ACTIVPARAM2 register. + * + * \param[in] reg is the value of the ACTIVPARAM2 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the PARAM2 field belonging to ACTIVPARAM2 register + */ + +static inline uint32_t ATON_ACTIV_ACTIVPARAM2_Set_PARAM2(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_ACTIVPARAM2_SET_PARAM2(reg, data); +} + + +/* ******************************************************** FSUB register of one of the ACTIV Units ********************************************************* */ + +/** Offset of the FSUB register from the base address of the ACTIV Unit. */ +#define ATON_ACTIV_FSUB_OFFSET 0x14UL + +/** Reset value of the FSUB register of the ACTIV Unit. */ +#define ATON_ACTIV_FSUB_DT \ + (ATON_ACTIV_FSUB_FSUB_DT << ATON_ACTIV_FSUB_FSUB_LSB) + + + +/** Description of the FSUB register. */ +#define ATON_ACTIV_FSUB_DESC "Feature data subtract" + +/** Address of the FSUB register of one of the ACTIV Units. */ +#define ATON_ACTIV_FSUB_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_FSUB_OFFSET) + +/** Get the content of the FSUB register of one of the ACTIV Units. */ +#define ATON_ACTIV_FSUB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FSUB_ADDR(UNIT))) + +/** Set the content of the FSUB register of one of the ACTIV Units. */ +#define ATON_ACTIV_FSUB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FSUB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FSUB register. + * + * \return the description of FSUB register + */ + +static inline const int8_t *ATON_ACTIV_FSUB_GetDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FSUB_DESC; +} + + +/** + * Get the offset of the FSUB register. + * + * \return the offset of FSUB register + */ + +static inline uint32_t ATON_ACTIV_FSUB_GetOffset(void) +{ + return ATON_ACTIV_FSUB_OFFSET; +} + + +/** + * Get the address of the FSUB register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FSUB register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of FSUB register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_FSUB_GetAddr(uint32_t instance) +{ + return ATON_ACTIV_FSUB_ADDR(instance); +} + + +/** + * Read the content of the FSUB register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FSUB register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of FSUB register belonging to Unit having index \e instance among the ACTIV Units + */ + +static inline uint32_t ATON_ACTIV_FSUB_Get(uint32_t instance) +{ + return ATON_ACTIV_FSUB_GET(instance); +} + + +/** + * Write the content of the FSUB register. + * + * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FSUB register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ACTIV_FSUB_Set(uint32_t instance, uint32_t data) +{ + ATON_ACTIV_FSUB_SET(instance, data); +} + + +/* ------------------------------------------------------------ FSUB field of the FSUB register ------------------------------------------------------------- */ + +/** Description of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_FSUB_DESC "Feature data subtract value" + +/** Offset of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_FSUB_LSB 0UL + +/** Size in bits of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_FSUB_W (24UL) + +/** Mask for retrieving the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_FSUB_MASK ATON_FIELD_MASK(0UL, 24UL) + +/** Reset value of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_FSUB_DT 0x0UL + +/** Access rights of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_FSUB_AC "RW" + +/** Check whether access to the FSUB field of the FSUB register is secured or not. */ +#define ATON_ACTIV_FSUB_FSUB_S 0 + +/** Check whether access to the FSUB field of the FSUB register is privileged or not. */ +#define ATON_ACTIV_FSUB_FSUB_P 0 + +/** Read the content of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_GET_FSUB(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FSUB_FSUB_LSB, ATON_ACTIV_FSUB_FSUB_W) + +/** Modify the content of the FSUB field of the FSUB register. */ +#define ATON_ACTIV_FSUB_SET_FSUB(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FSUB_FSUB_LSB, ATON_ACTIV_FSUB_FSUB_W, DATA) + + +/** + * Get the description of the FSUB field of FSUB register. + * + * \return the description of the FSUB field of FSUB register + */ + +static inline const int8_t *ATON_ACTIV_FSUB_FSUB_GetdDesc(void) +{ + return (const int8_t *)ATON_ACTIV_FSUB_FSUB_DESC; +} + + +/** + * Read the content of the FSUB field of the FSUB register. + * + * \param[in] reg is the value of the FSUB register + * + * \return the content of the FSUB field belonging to FSUB register + */ + +static inline uint32_t ATON_ACTIV_FSUB_Get_FSUB(uint32_t reg) +{ + return ATON_ACTIV_FSUB_GET_FSUB(reg); +} + + +/** + * Write the content of the FSUB field of the FSUB register. + * + * \param[in] reg is the value of the FSUB register + * \param[in] data is 24-bit value that must be written to the field + * + * \return the new content of the FSUB field belonging to FSUB register + */ + +static inline uint32_t ATON_ACTIV_FSUB_Set_FSUB(uint32_t reg, uint32_t data) +{ + return ATON_ACTIV_FSUB_SET_FSUB(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* ARITH Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of ARITH Unit instances. */ +#define ATON_ARITH_NUM 4 + +/** + * \name Structures, macros and functions of the ARITH Units + */ +/*@{*/ + +/** + * Registers of the ARITH Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e SHIFT register (Shift parameters). */ + uint32_t SHIFT; + + /** \e INCCNT register (Increment counter). */ + uint32_t INCCNT; + + /** \e RSTCNT1 register (Reset counter 1). */ + uint32_t RSTCNT1; + + /** \e RSTCNT2 register (Reset counter 2). */ + uint32_t RSTCNT2; + + /** \e RSTCNT3 register (Reset counter 3). */ + uint32_t RSTCNT3; + + /** \e COEFFAC register (Scalar coefficients A and C). */ + uint32_t COEFFAC; + + /** \e COEFFB register (Scalar coefficient B). */ + uint32_t COEFFB; + + /** \e ADDROFFSET register (Address offsets). */ + uint32_t ADDROFFSET; + + /** \e INCOFFSET register (Address increment offset). */ + uint32_t INCOFFSET; + + /** \e TRANSLATEADDR register (Address translation control for memory). */ + uint32_t TRANSLATEADDR; + + /** \e COEFFADDR register (Coeff Address). */ + uint32_t COEFFADDR; + + /** \e INSHIFTER register (input shifter configuration). */ + uint32_t INSHIFTER; + + /** \e CLIPRANGE register (Output clip range [min,max]). */ + uint32_t CLIPRANGE; + +} ATON_ARITH_t; + + +/** Return the pointer to one of the ARITH Units. */ +#define ATON_ARITH(UNIT) ((ATON_ARITH_t *)(intptr_t)ATON_ARITH_BASE(UNIT)) + + +/** Name of one of the ARITH Units. */ +#define ATON_ARITH_NAME(UNIT) \ + (((UNIT) == 0) ? "ARITH0" : \ + (((UNIT) == 1) ? "ARITH1" : \ + (((UNIT) == 2) ? "ARITH2" : \ + (((UNIT) == 3) ? "ARITH3" : "")))) + + +/** Version of the ARITH Units. */ +#define ATON_ARITH_VERSION "1.0" + + +/** Description of one of the ARITH Units. */ +#define ATON_ARITH_DESC(UNIT) \ + (((UNIT) == 0) ? "Arithmetic Accelerator 0" : \ + (((UNIT) == 1) ? "Arithmetic Accelerator 1" : \ + (((UNIT) == 2) ? "Arithmetic Accelerator 2" : \ + (((UNIT) == 3) ? "Arithmetic Accelerator 3" : "")))) + + +/** Base address of one of the ARITH Units. */ +#define ATON_ARITH_BASE(UNIT) \ + (ATON_BASE + 0x17000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the ARITH Units. */ +#define ATON_ARITH_SIZE 0x1000UL + + +/** + * Get the name of one of the ARITH Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 4<\em>) + * + * \return the name of Unit having index \e instance among the ARITH Units + */ + +static inline const int8_t *ATON_ARITH_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"ARITH0"; + break; + + case 1: + str = (const int8_t *)"ARITH1"; + break; + + case 2: + str = (const int8_t *)"ARITH2"; + break; + + case 3: + str = (const int8_t *)"ARITH3"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the ARITH Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 4<\em>) + * + * \return the description of Unit having index \e instance among the ARITH Units + */ + +static inline const int8_t *ATON_ARITH_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Arithmetic Accelerator 0"; + break; + + case 1: + str = (const int8_t *)"Arithmetic Accelerator 1"; + break; + + case 2: + str = (const int8_t *)"Arithmetic Accelerator 2"; + break; + + case 3: + str = (const int8_t *)"Arithmetic Accelerator 3"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the ARITH Units. + * + * \return the version of the ARITH Units + */ + +static inline const int8_t *ATON_ARITH_GetVersion(void) +{ + return (const int8_t *)ATON_ARITH_VERSION; +} + + +/** + * Get the base address of one of the ARITH Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 4<\em>) + * + * \return the base address of Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_GetBase(uint32_t instance) +{ + return ATON_ARITH_BASE(instance); +} + + +/** + * Get the size in bytes of the ARITH Units. + * + * \return the size in bytes of the ARITH Units + */ + +static inline uint32_t ATON_ARITH_GetSize(void) +{ + return ATON_ARITH_SIZE; +} + + +/* ******************************************************** CTRL register of one of the ARITH Units ********************************************************* */ + +/** Offset of the CTRL register from the base address of the ARITH Unit. */ +#define ATON_ARITH_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the ARITH Unit. */ +#define ATON_ARITH_CTRL_DT \ + (ATON_ARITH_CTRL_EN_DT << ATON_ARITH_CTRL_EN_LSB) | \ + (ATON_ARITH_CTRL_CLR_DT << ATON_ARITH_CTRL_CLR_LSB) | \ + (ATON_ARITH_CTRL_CNT1_DT << ATON_ARITH_CTRL_CNT1_LSB) | \ + (ATON_ARITH_CTRL_CNT2_DT << ATON_ARITH_CTRL_CNT2_LSB) | \ + (ATON_ARITH_CTRL_CNT3_DT << ATON_ARITH_CTRL_CNT3_LSB) | \ + (ATON_ARITH_CTRL_ROUND_DT << ATON_ARITH_CTRL_ROUND_LSB) | \ + (ATON_ARITH_CTRL_SAT_DT << ATON_ARITH_CTRL_SAT_LSB) | \ + (ATON_ARITH_CTRL_COEFFA_DT << ATON_ARITH_CTRL_COEFFA_LSB) | \ + (ATON_ARITH_CTRL_DUALIN_DT << ATON_ARITH_CTRL_DUALIN_LSB) | \ + (ATON_ARITH_CTRL_OP_DT << ATON_ARITH_CTRL_OP_LSB) | \ + (ATON_ARITH_CTRL_COEFFB_DT << ATON_ARITH_CTRL_COEFFB_LSB) | \ + (ATON_ARITH_CTRL_COEFFC_DT << ATON_ARITH_CTRL_COEFFC_LSB) | \ + (ATON_ARITH_CTRL_LOGICALOP_DT << ATON_ARITH_CTRL_LOGICALOP_LSB) | \ + (ATON_ARITH_CTRL_ORNDMODE_DT << ATON_ARITH_CTRL_ORNDMODE_LSB) | \ + (ATON_ARITH_CTRL_OBYTES_DT << ATON_ARITH_CTRL_OBYTES_LSB) | \ + (ATON_ARITH_CTRL_COMBINEBC_DT << ATON_ARITH_CTRL_COMBINEBC_LSB) | \ + (ATON_ARITH_CTRL_CLIPOUT_DT << ATON_ARITH_CTRL_CLIPOUT_LSB) | \ + (ATON_ARITH_CTRL_CONFCLR_DT << ATON_ARITH_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_ARITH_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the ARITH Units. */ +#define ATON_ARITH_CTRL_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the ARITH Units. */ +#define ATON_ARITH_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the ARITH Units. */ +#define ATON_ARITH_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_GetOffset(void) +{ + return ATON_ARITH_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CTRL register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_CTRL_GetAddr(uint32_t instance) +{ + return ATON_ARITH_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_CTRL_Get(uint32_t instance) +{ + return ATON_ARITH_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CTRL register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_EN_DESC "Enable the Arithmetic Unit" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_EN_LSB, ATON_ARITH_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_EN_LSB, ATON_ARITH_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_EN(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CLR_LSB, ATON_ARITH_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CLR_LSB, ATON_ARITH_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_CLR(reg, data); +} + + +/* ------------------------------------------------------------ CNT1 field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT1_DESC "Enable counter 1" + +/** Offset of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT1_LSB 2UL + +/** Size in bits of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT1_W (1UL) + +/** Mask for retrieving the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT1_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT1_DT 0x0UL + +/** Access rights of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT1_AC "RW" + +/** Check whether access to the CNT1 field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_CNT1_S 0 + +/** Check whether access to the CNT1 field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_CNT1_P 0 + +/** Read the content of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_CNT1(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CNT1_LSB, ATON_ARITH_CTRL_CNT1_W) + +/** Modify the content of the CNT1 field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_CNT1(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CNT1_LSB, ATON_ARITH_CTRL_CNT1_W, DATA) + + +/** + * Get the description of the CNT1 field of CTRL register. + * + * \return the description of the CNT1 field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_CNT1_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_CNT1_DESC; +} + + +/** + * Read the content of the CNT1 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CNT1 field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_CNT1(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_CNT1(reg); +} + + +/** + * Write the content of the CNT1 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT1 field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_CNT1(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_CNT1(reg, data); +} + + +/* ------------------------------------------------------------ CNT2 field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT2_DESC "Enable counter 2" + +/** Offset of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT2_LSB 3UL + +/** Size in bits of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT2_W (1UL) + +/** Mask for retrieving the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT2_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT2_DT 0x0UL + +/** Access rights of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT2_AC "RW" + +/** Check whether access to the CNT2 field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_CNT2_S 0 + +/** Check whether access to the CNT2 field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_CNT2_P 0 + +/** Read the content of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_CNT2(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CNT2_LSB, ATON_ARITH_CTRL_CNT2_W) + +/** Modify the content of the CNT2 field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_CNT2(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CNT2_LSB, ATON_ARITH_CTRL_CNT2_W, DATA) + + +/** + * Get the description of the CNT2 field of CTRL register. + * + * \return the description of the CNT2 field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_CNT2_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_CNT2_DESC; +} + + +/** + * Read the content of the CNT2 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CNT2 field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_CNT2(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_CNT2(reg); +} + + +/** + * Write the content of the CNT2 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT2 field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_CNT2(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_CNT2(reg, data); +} + + +/* ------------------------------------------------------------ CNT3 field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT3_DESC "Enable counter 3" + +/** Offset of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT3_LSB 4UL + +/** Size in bits of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT3_W (1UL) + +/** Mask for retrieving the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT3_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT3_DT 0x0UL + +/** Access rights of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_CNT3_AC "RW" + +/** Check whether access to the CNT3 field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_CNT3_S 0 + +/** Check whether access to the CNT3 field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_CNT3_P 0 + +/** Read the content of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_CNT3(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CNT3_LSB, ATON_ARITH_CTRL_CNT3_W) + +/** Modify the content of the CNT3 field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_CNT3(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CNT3_LSB, ATON_ARITH_CTRL_CNT3_W, DATA) + + +/** + * Get the description of the CNT3 field of CTRL register. + * + * \return the description of the CNT3 field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_CNT3_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_CNT3_DESC; +} + + +/** + * Read the content of the CNT3 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CNT3 field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_CNT3(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_CNT3(reg); +} + + +/** + * Write the content of the CNT3 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT3 field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_CNT3(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_CNT3(reg, data); +} + + +/* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_ROUND_DESC "Rounding control, 1=enable,0=disable" + +/** Offset of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_ROUND_LSB 5UL + +/** Size in bits of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_ROUND_W (1UL) + +/** Mask for retrieving the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_ROUND_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_ROUND_DT 0x0UL + +/** Access rights of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_ROUND_AC "RW" + +/** Check whether access to the ROUND field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_ROUND_S 0 + +/** Check whether access to the ROUND field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_ROUND_P 0 + +/** Read the content of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_ROUND_LSB, ATON_ARITH_CTRL_ROUND_W) + +/** Modify the content of the ROUND field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_ROUND_LSB, ATON_ARITH_CTRL_ROUND_W, DATA) + + +/** + * Get the description of the ROUND field of CTRL register. + * + * \return the description of the ROUND field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_ROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_ROUND_DESC; +} + + +/** + * Read the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_ROUND(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_ROUND(reg); +} + + +/** + * Write the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_ROUND(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_ROUND(reg, data); +} + + +/* ------------------------------------------------------------- SAT field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SAT_DESC "Saturation control, 1=enable,0=disable" + +/** Offset of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SAT_LSB 6UL + +/** Size in bits of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SAT_W (1UL) + +/** Mask for retrieving the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SAT_MASK ATON_FIELD_MASK(6UL, 1UL) + +/** Reset value of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SAT_DT 0x0UL + +/** Access rights of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SAT_AC "RW" + +/** Check whether access to the SAT field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_SAT_S 0 + +/** Check whether access to the SAT field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_SAT_P 0 + +/** Read the content of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_SAT_LSB, ATON_ARITH_CTRL_SAT_W) + +/** Modify the content of the SAT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_SAT_LSB, ATON_ARITH_CTRL_SAT_W, DATA) + + +/** + * Get the description of the SAT field of CTRL register. + * + * \return the description of the SAT field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_SAT_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_SAT_DESC; +} + + +/** + * Read the content of the SAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SAT field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_SAT(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_SAT(reg); +} + + +/** + * Write the content of the SAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SAT field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_SAT(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_SAT(reg, data); +} + + +/* ----------------------------------------------------------- COEFFA field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFA_DESC "Coefficient type for A" + +/** Offset of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFA_LSB 7UL + +/** Size in bits of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFA_W (1UL) + +/** Mask for retrieving the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFA_MASK ATON_FIELD_MASK(7UL, 1UL) + +/** Reset value of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFA_DT 0x0UL + +/** Access rights of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFA_AC "RW" + +/** Check whether access to the COEFFA field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_COEFFA_S 0 + +/** Check whether access to the COEFFA field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_COEFFA_P 0 + +/** Read the content of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_COEFFA(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COEFFA_LSB, ATON_ARITH_CTRL_COEFFA_W) + +/** Modify the content of the COEFFA field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_COEFFA(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COEFFA_LSB, ATON_ARITH_CTRL_COEFFA_W, DATA) + + +/** + * Get the description of the COEFFA field of CTRL register. + * + * \return the description of the COEFFA field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_COEFFA_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_COEFFA_DESC; +} + + +/** + * Read the content of the COEFFA field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the COEFFA field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_COEFFA(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_COEFFA(reg); +} + + +/** + * Write the content of the COEFFA field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the COEFFA field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_COEFFA(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_COEFFA(reg, data); +} + + +/* ----------------------------------------------------------- DUALIN field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_DUALIN_DESC "dual input control, 1=both X,Y streams valid, 0=only X stream is valid" + +/** Offset of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_DUALIN_LSB 8UL + +/** Size in bits of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_DUALIN_W (1UL) + +/** Mask for retrieving the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_DUALIN_MASK ATON_FIELD_MASK(8UL, 1UL) + +/** Reset value of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_DUALIN_DT 0x0UL + +/** Access rights of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_DUALIN_AC "RW" + +/** Check whether access to the DUALIN field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_DUALIN_S 0 + +/** Check whether access to the DUALIN field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_DUALIN_P 0 + +/** Read the content of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_DUALIN(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_DUALIN_LSB, ATON_ARITH_CTRL_DUALIN_W) + +/** Modify the content of the DUALIN field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_DUALIN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_DUALIN_LSB, ATON_ARITH_CTRL_DUALIN_W, DATA) + + +/** + * Get the description of the DUALIN field of CTRL register. + * + * \return the description of the DUALIN field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_DUALIN_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_DUALIN_DESC; +} + + +/** + * Read the content of the DUALIN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DUALIN field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_DUALIN(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_DUALIN(reg); +} + + +/** + * Write the content of the DUALIN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DUALIN field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_DUALIN(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_DUALIN(reg, data); +} + + +/* ------------------------------------------------------------- OP field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_OP_DESC "Arithmetic operation" + +/** Offset of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_OP_LSB 9UL + +/** Size in bits of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_OP_W (6UL) + +/** Mask for retrieving the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_OP_MASK ATON_FIELD_MASK(9UL, 6UL) + +/** Reset value of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_OP_DT 0x0UL + +/** Access rights of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_OP_AC "RW" + +/** Check whether access to the OP field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_OP_S 0 + +/** Check whether access to the OP field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_OP_P 0 + +/** Read the content of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_OP(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_OP_LSB, ATON_ARITH_CTRL_OP_W) + +/** Modify the content of the OP field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_OP(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_OP_LSB, ATON_ARITH_CTRL_OP_W, DATA) + + +/** + * Get the description of the OP field of CTRL register. + * + * \return the description of the OP field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_OP_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_OP_DESC; +} + + +/** + * Read the content of the OP field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the OP field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_OP(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_OP(reg); +} + + +/** + * Write the content of the OP field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the OP field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_OP(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_OP(reg, data); +} + + +/* ----------------------------------------------------------- COEFFB field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFB_DESC "Coefficient type for B" + +/** Offset of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFB_LSB 21UL + +/** Size in bits of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFB_W (1UL) + +/** Mask for retrieving the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFB_MASK ATON_FIELD_MASK(21UL, 1UL) + +/** Reset value of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFB_DT 0x0UL + +/** Access rights of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFB_AC "RW" + +/** Check whether access to the COEFFB field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_COEFFB_S 0 + +/** Check whether access to the COEFFB field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_COEFFB_P 0 + +/** Read the content of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_COEFFB(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COEFFB_LSB, ATON_ARITH_CTRL_COEFFB_W) + +/** Modify the content of the COEFFB field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_COEFFB(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COEFFB_LSB, ATON_ARITH_CTRL_COEFFB_W, DATA) + + +/** + * Get the description of the COEFFB field of CTRL register. + * + * \return the description of the COEFFB field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_COEFFB_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_COEFFB_DESC; +} + + +/** + * Read the content of the COEFFB field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the COEFFB field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_COEFFB(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_COEFFB(reg); +} + + +/** + * Write the content of the COEFFB field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the COEFFB field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_COEFFB(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_COEFFB(reg, data); +} + + +/* ----------------------------------------------------------- COEFFC field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFC_DESC "Coefficient type for C" + +/** Offset of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFC_LSB 22UL + +/** Size in bits of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFC_W (1UL) + +/** Mask for retrieving the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFC_MASK ATON_FIELD_MASK(22UL, 1UL) + +/** Reset value of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFC_DT 0x0UL + +/** Access rights of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COEFFC_AC "RW" + +/** Check whether access to the COEFFC field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_COEFFC_S 0 + +/** Check whether access to the COEFFC field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_COEFFC_P 0 + +/** Read the content of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_COEFFC(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COEFFC_LSB, ATON_ARITH_CTRL_COEFFC_W) + +/** Modify the content of the COEFFC field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_COEFFC(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COEFFC_LSB, ATON_ARITH_CTRL_COEFFC_W, DATA) + + +/** + * Get the description of the COEFFC field of CTRL register. + * + * \return the description of the COEFFC field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_COEFFC_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_COEFFC_DESC; +} + + +/** + * Read the content of the COEFFC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the COEFFC field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_COEFFC(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_COEFFC(reg); +} + + +/** + * Write the content of the COEFFC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the COEFFC field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_COEFFC(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_COEFFC(reg, data); +} + + +/* ---------------------------------------------------------- LOGICALOP field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_LOGICALOP_DESC "logical or bitwise operation for AND,OR,NOT,1=logical, 0=bitwise" + +/** Offset of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_LOGICALOP_LSB 23UL + +/** Size in bits of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_LOGICALOP_W (1UL) + +/** Mask for retrieving the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_LOGICALOP_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_LOGICALOP_DT 0x0UL + +/** Access rights of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_LOGICALOP_AC "RW" + +/** Check whether access to the LOGICALOP field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_LOGICALOP_S 0 + +/** Check whether access to the LOGICALOP field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_LOGICALOP_P 0 + +/** Read the content of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_LOGICALOP(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_LOGICALOP_LSB, ATON_ARITH_CTRL_LOGICALOP_W) + +/** Modify the content of the LOGICALOP field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_LOGICALOP(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_LOGICALOP_LSB, ATON_ARITH_CTRL_LOGICALOP_W, DATA) + + +/** + * Get the description of the LOGICALOP field of CTRL register. + * + * \return the description of the LOGICALOP field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_LOGICALOP_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_LOGICALOP_DESC; +} + + +/** + * Read the content of the LOGICALOP field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the LOGICALOP field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_LOGICALOP(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_LOGICALOP(reg); +} + + +/** + * Write the content of the LOGICALOP field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the LOGICALOP field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_LOGICALOP(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_LOGICALOP(reg, data); +} + + +/* ---------------------------------------------------------- ORNDMODE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_ORNDMODE_DESC "output rounding mode control. For more information see section: Rounding and Saturation. Valid values are 0 and 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_ORNDMODE_LSB 24UL + +/** Size in bits of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_ORNDMODE_W (2UL) + +/** Mask for retrieving the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_ORNDMODE_MASK ATON_FIELD_MASK(24UL, 2UL) + +/** Reset value of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_ORNDMODE_DT 0x0UL + +/** Access rights of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_ORNDMODE_AC "RW" + +/** Check whether access to the ORNDMODE field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_ORNDMODE_S 0 + +/** Check whether access to the ORNDMODE field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_ORNDMODE_P 0 + +/** Read the content of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_ORNDMODE_LSB, ATON_ARITH_CTRL_ORNDMODE_W) + +/** Modify the content of the ORNDMODE field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_ORNDMODE_LSB, ATON_ARITH_CTRL_ORNDMODE_W, DATA) + + +/** + * Get the description of the ORNDMODE field of CTRL register. + * + * \return the description of the ORNDMODE field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_ORNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_ORNDMODE_DESC; +} + + +/** + * Read the content of the ORNDMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ORNDMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_ORNDMODE(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_ORNDMODE(reg); +} + + +/** + * Write the content of the ORNDMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ORNDMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_ORNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_ORNDMODE(reg, data); +} + + +/* ----------------------------------------------------------- OBYTES field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_OBYTES_DESC "number of output bytes: 1 or 2" + +/** Offset of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_OBYTES_LSB 26UL + +/** Size in bits of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_OBYTES_W (2UL) + +/** Mask for retrieving the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_OBYTES_MASK ATON_FIELD_MASK(26UL, 2UL) + +/** Reset value of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_OBYTES_DT 0x2UL + +/** Access rights of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_OBYTES_AC "RW" + +/** Check whether access to the OBYTES field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_OBYTES_S 0 + +/** Check whether access to the OBYTES field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_OBYTES_P 0 + +/** Read the content of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_OBYTES_LSB, ATON_ARITH_CTRL_OBYTES_W) + +/** Modify the content of the OBYTES field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_OBYTES_LSB, ATON_ARITH_CTRL_OBYTES_W, DATA) + + +/** + * Get the description of the OBYTES field of CTRL register. + * + * \return the description of the OBYTES field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_OBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_OBYTES_DESC; +} + + +/** + * Read the content of the OBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the OBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_OBYTES(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_OBYTES(reg); +} + + +/** + * Write the content of the OBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the OBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_OBYTES(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_OBYTES(reg, data); +} + + +/* ---------------------------------------------------------- COMBINEBC field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COMBINEBC_DESC "Combine coeff B and C to form a 32b coeff BC = {B[15:0],C[15:0]}" + +/** Offset of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COMBINEBC_LSB 28UL + +/** Size in bits of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COMBINEBC_W (1UL) + +/** Mask for retrieving the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COMBINEBC_MASK ATON_FIELD_MASK(28UL, 1UL) + +/** Reset value of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COMBINEBC_DT 0x0UL + +/** Access rights of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_COMBINEBC_AC "RW" + +/** Check whether access to the COMBINEBC field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_COMBINEBC_S 0 + +/** Check whether access to the COMBINEBC field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_COMBINEBC_P 0 + +/** Read the content of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_COMBINEBC(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COMBINEBC_LSB, ATON_ARITH_CTRL_COMBINEBC_W) + +/** Modify the content of the COMBINEBC field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_COMBINEBC(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COMBINEBC_LSB, ATON_ARITH_CTRL_COMBINEBC_W, DATA) + + +/** + * Get the description of the COMBINEBC field of CTRL register. + * + * \return the description of the COMBINEBC field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_COMBINEBC_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_COMBINEBC_DESC; +} + + +/** + * Read the content of the COMBINEBC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the COMBINEBC field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_COMBINEBC(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_COMBINEBC(reg); +} + + +/** + * Write the content of the COMBINEBC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the COMBINEBC field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_COMBINEBC(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_COMBINEBC(reg, data); +} + + +/* ----------------------------------------------------------- CLIPOUT field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLIPOUT_DESC "Controls output clipping to range specified by clip range register. 1=enable,0=disable" + +/** Offset of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLIPOUT_LSB 29UL + +/** Size in bits of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLIPOUT_W (1UL) + +/** Mask for retrieving the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLIPOUT_MASK ATON_FIELD_MASK(29UL, 1UL) + +/** Reset value of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLIPOUT_DT 0x0UL + +/** Access rights of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_CLIPOUT_AC "RW" + +/** Check whether access to the CLIPOUT field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_CLIPOUT_S 0 + +/** Check whether access to the CLIPOUT field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_CLIPOUT_P 0 + +/** Read the content of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_CLIPOUT(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CLIPOUT_LSB, ATON_ARITH_CTRL_CLIPOUT_W) + +/** Modify the content of the CLIPOUT field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_CLIPOUT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CLIPOUT_LSB, ATON_ARITH_CTRL_CLIPOUT_W, DATA) + + +/** + * Get the description of the CLIPOUT field of CTRL register. + * + * \return the description of the CLIPOUT field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_CLIPOUT_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_CLIPOUT_DESC; +} + + +/** + * Read the content of the CLIPOUT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLIPOUT field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_CLIPOUT(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_CLIPOUT(reg); +} + + +/** + * Write the content of the CLIPOUT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLIPOUT field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_CLIPOUT(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_CLIPOUT(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CONFCLR_DESC "Clear configuration registers (auto-cleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_ARITH_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_ARITH_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CONFCLR_LSB, ATON_ARITH_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_ARITH_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CONFCLR_LSB, ATON_ARITH_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_ARITH_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_ARITH_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_ARITH_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CTRL_SET_CONFCLR(reg, data); +} + + +/* ******************************************************* VERSION register of one of the ARITH Units ******************************************************* */ + +/** Offset of the VERSION register from the base address of the ARITH Unit. */ +#define ATON_ARITH_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the ARITH Unit. */ +#define ATON_ARITH_VERSION_DT \ + (ATON_ARITH_VERSION_TYPE_DT << ATON_ARITH_VERSION_TYPE_LSB) | \ + (ATON_ARITH_VERSION_MINOR_DT << ATON_ARITH_VERSION_MINOR_LSB) | \ + (ATON_ARITH_VERSION_MAJOR_DT << ATON_ARITH_VERSION_MAJOR_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_ARITH_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the ARITH Units. */ +#define ATON_ARITH_VERSION_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the ARITH Units. */ +#define ATON_ARITH_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_ARITH_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_ARITH_VERSION_GetOffset(void) +{ + return ATON_ARITH_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the VERSION register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_VERSION_GetAddr(uint32_t instance) +{ + return ATON_ARITH_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_VERSION_Get(uint32_t instance) +{ + return ATON_ARITH_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_TYPE_DT 0x1aUL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_ARITH_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_ARITH_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_ARITH_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_ARITH_VERSION_TYPE_LSB, ATON_ARITH_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_ARITH_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_ARITH_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_ARITH_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MINOR_DT 0x0UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_ARITH_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_ARITH_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_ARITH_VERSION_MINOR_LSB, ATON_ARITH_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_ARITH_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_ARITH_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_ARITH_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_ARITH_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_ARITH_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_ARITH_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_ARITH_VERSION_MAJOR_LSB, ATON_ARITH_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_ARITH_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_ARITH_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_ARITH_VERSION_GET_MAJOR(reg); +} + + +/* ******************************************************** SHIFT register of one of the ARITH Units ******************************************************** */ + +/** Offset of the SHIFT register from the base address of the ARITH Unit. */ +#define ATON_ARITH_SHIFT_OFFSET 0x8UL + +/** Reset value of the SHIFT register of the ARITH Unit. */ +#define ATON_ARITH_SHIFT_DT \ + (ATON_ARITH_SHIFT_AX_DT << ATON_ARITH_SHIFT_AX_LSB) | \ + (ATON_ARITH_SHIFT_BY_DT << ATON_ARITH_SHIFT_BY_LSB) | \ + (ATON_ARITH_SHIFT_C_DT << ATON_ARITH_SHIFT_C_LSB) | \ + (ATON_ARITH_SHIFT_RES_DT << ATON_ARITH_SHIFT_RES_LSB) + + + +/** Description of the SHIFT register. */ +#define ATON_ARITH_SHIFT_DESC "Shift parameters" + +/** Address of the SHIFT register of one of the ARITH Units. */ +#define ATON_ARITH_SHIFT_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_SHIFT_OFFSET) + +/** Get the content of the SHIFT register of one of the ARITH Units. */ +#define ATON_ARITH_SHIFT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_SHIFT_ADDR(UNIT))) + +/** Set the content of the SHIFT register of one of the ARITH Units. */ +#define ATON_ARITH_SHIFT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_SHIFT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of SHIFT register. + * + * \return the description of SHIFT register + */ + +static inline const int8_t *ATON_ARITH_SHIFT_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_SHIFT_DESC; +} + + +/** + * Get the offset of the SHIFT register. + * + * \return the offset of SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_GetOffset(void) +{ + return ATON_ARITH_SHIFT_OFFSET; +} + + +/** + * Get the address of the SHIFT register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the SHIFT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of SHIFT register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_SHIFT_GetAddr(uint32_t instance) +{ + return ATON_ARITH_SHIFT_ADDR(instance); +} + + +/** + * Read the content of the SHIFT register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the SHIFT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of SHIFT register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_SHIFT_Get(uint32_t instance) +{ + return ATON_ARITH_SHIFT_GET(instance); +} + + +/** + * Write the content of the SHIFT register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the SHIFT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_SHIFT_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_SHIFT_SET(instance, data); +} + + +/* ------------------------------------------------------------- AX field of the SHIFT register ------------------------------------------------------------- */ + +/** Description of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_AX_DESC "Optional right shift to result of Ax" + +/** Offset of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_AX_LSB 0UL + +/** Size in bits of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_AX_W (5UL) + +/** Mask for retrieving the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_AX_MASK ATON_FIELD_MASK(0UL, 5UL) + +/** Reset value of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_AX_DT 0x0UL + +/** Access rights of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_AX_AC "RW" + +/** Check whether access to the AX field of the SHIFT register is secured or not. */ +#define ATON_ARITH_SHIFT_AX_S 0 + +/** Check whether access to the AX field of the SHIFT register is privileged or not. */ +#define ATON_ARITH_SHIFT_AX_P 0 + +/** Read the content of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_GET_AX(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_AX_LSB, ATON_ARITH_SHIFT_AX_W) + +/** Modify the content of the AX field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_SET_AX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_AX_LSB, ATON_ARITH_SHIFT_AX_W, DATA) + + +/** + * Get the description of the AX field of SHIFT register. + * + * \return the description of the AX field of SHIFT register + */ + +static inline const int8_t *ATON_ARITH_SHIFT_AX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_SHIFT_AX_DESC; +} + + +/** + * Read the content of the AX field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * + * \return the content of the AX field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Get_AX(uint32_t reg) +{ + return ATON_ARITH_SHIFT_GET_AX(reg); +} + + +/** + * Write the content of the AX field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the AX field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Set_AX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_SHIFT_SET_AX(reg, data); +} + + +/* ------------------------------------------------------------- BY field of the SHIFT register ------------------------------------------------------------- */ + +/** Description of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_BY_DESC "Optional right shift to result of By" + +/** Offset of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_BY_LSB 5UL + +/** Size in bits of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_BY_W (5UL) + +/** Mask for retrieving the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_BY_MASK ATON_FIELD_MASK(5UL, 5UL) + +/** Reset value of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_BY_DT 0x0UL + +/** Access rights of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_BY_AC "RW" + +/** Check whether access to the BY field of the SHIFT register is secured or not. */ +#define ATON_ARITH_SHIFT_BY_S 0 + +/** Check whether access to the BY field of the SHIFT register is privileged or not. */ +#define ATON_ARITH_SHIFT_BY_P 0 + +/** Read the content of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_GET_BY(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_BY_LSB, ATON_ARITH_SHIFT_BY_W) + +/** Modify the content of the BY field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_SET_BY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_BY_LSB, ATON_ARITH_SHIFT_BY_W, DATA) + + +/** + * Get the description of the BY field of SHIFT register. + * + * \return the description of the BY field of SHIFT register + */ + +static inline const int8_t *ATON_ARITH_SHIFT_BY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_SHIFT_BY_DESC; +} + + +/** + * Read the content of the BY field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * + * \return the content of the BY field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Get_BY(uint32_t reg) +{ + return ATON_ARITH_SHIFT_GET_BY(reg); +} + + +/** + * Write the content of the BY field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the BY field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Set_BY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_SHIFT_SET_BY(reg, data); +} + + +/* ------------------------------------------------------------- C field of the SHIFT register -------------------------------------------------------------- */ + +/** Description of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_C_DESC "Optional left shift to apply to C" + +/** Offset of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_C_LSB 10UL + +/** Size in bits of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_C_W (5UL) + +/** Mask for retrieving the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_C_MASK ATON_FIELD_MASK(10UL, 5UL) + +/** Reset value of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_C_DT 0x0UL + +/** Access rights of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_C_AC "RW" + +/** Check whether access to the C field of the SHIFT register is secured or not. */ +#define ATON_ARITH_SHIFT_C_S 0 + +/** Check whether access to the C field of the SHIFT register is privileged or not. */ +#define ATON_ARITH_SHIFT_C_P 0 + +/** Read the content of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_GET_C(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_C_LSB, ATON_ARITH_SHIFT_C_W) + +/** Modify the content of the C field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_SET_C(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_C_LSB, ATON_ARITH_SHIFT_C_W, DATA) + + +/** + * Get the description of the C field of SHIFT register. + * + * \return the description of the C field of SHIFT register + */ + +static inline const int8_t *ATON_ARITH_SHIFT_C_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_SHIFT_C_DESC; +} + + +/** + * Read the content of the C field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * + * \return the content of the C field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Get_C(uint32_t reg) +{ + return ATON_ARITH_SHIFT_GET_C(reg); +} + + +/** + * Write the content of the C field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the C field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Set_C(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_SHIFT_SET_C(reg, data); +} + + +/* ------------------------------------------------------------ RES field of the SHIFT register ------------------------------------------------------------- */ + +/** Description of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_RES_DESC "Optional right shift to apply to final result of operation" + +/** Offset of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_RES_LSB 15UL + +/** Size in bits of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_RES_W (6UL) + +/** Mask for retrieving the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_RES_MASK ATON_FIELD_MASK(15UL, 6UL) + +/** Reset value of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_RES_DT 0x0UL + +/** Access rights of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_RES_AC "RW" + +/** Check whether access to the RES field of the SHIFT register is secured or not. */ +#define ATON_ARITH_SHIFT_RES_S 0 + +/** Check whether access to the RES field of the SHIFT register is privileged or not. */ +#define ATON_ARITH_SHIFT_RES_P 0 + +/** Read the content of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_GET_RES(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_RES_LSB, ATON_ARITH_SHIFT_RES_W) + +/** Modify the content of the RES field of the SHIFT register. */ +#define ATON_ARITH_SHIFT_SET_RES(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_RES_LSB, ATON_ARITH_SHIFT_RES_W, DATA) + + +/** + * Get the description of the RES field of SHIFT register. + * + * \return the description of the RES field of SHIFT register + */ + +static inline const int8_t *ATON_ARITH_SHIFT_RES_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_SHIFT_RES_DESC; +} + + +/** + * Read the content of the RES field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * + * \return the content of the RES field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Get_RES(uint32_t reg) +{ + return ATON_ARITH_SHIFT_GET_RES(reg); +} + + +/** + * Write the content of the RES field of the SHIFT register. + * + * \param[in] reg is the value of the SHIFT register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the RES field belonging to SHIFT register + */ + +static inline uint32_t ATON_ARITH_SHIFT_Set_RES(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_SHIFT_SET_RES(reg, data); +} + + +/* ******************************************************* INCCNT register of one of the ARITH Units ******************************************************** */ + +/** Offset of the INCCNT register from the base address of the ARITH Unit. */ +#define ATON_ARITH_INCCNT_OFFSET 0xcUL + +/** Reset value of the INCCNT register of the ARITH Unit. */ +#define ATON_ARITH_INCCNT_DT \ + (ATON_ARITH_INCCNT_INCVAL_DT << ATON_ARITH_INCCNT_INCVAL_LSB) + + + +/** Description of the INCCNT register. */ +#define ATON_ARITH_INCCNT_DESC "Increment counter" + +/** Address of the INCCNT register of one of the ARITH Units. */ +#define ATON_ARITH_INCCNT_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_INCCNT_OFFSET) + +/** Get the content of the INCCNT register of one of the ARITH Units. */ +#define ATON_ARITH_INCCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCCNT_ADDR(UNIT))) + +/** Set the content of the INCCNT register of one of the ARITH Units. */ +#define ATON_ARITH_INCCNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCCNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INCCNT register. + * + * \return the description of INCCNT register + */ + +static inline const int8_t *ATON_ARITH_INCCNT_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_INCCNT_DESC; +} + + +/** + * Get the offset of the INCCNT register. + * + * \return the offset of INCCNT register + */ + +static inline uint32_t ATON_ARITH_INCCNT_GetOffset(void) +{ + return ATON_ARITH_INCCNT_OFFSET; +} + + +/** + * Get the address of the INCCNT register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCCNT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of INCCNT register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_INCCNT_GetAddr(uint32_t instance) +{ + return ATON_ARITH_INCCNT_ADDR(instance); +} + + +/** + * Read the content of the INCCNT register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCCNT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of INCCNT register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_INCCNT_Get(uint32_t instance) +{ + return ATON_ARITH_INCCNT_GET(instance); +} + + +/** + * Write the content of the INCCNT register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCCNT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_INCCNT_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_INCCNT_SET(instance, data); +} + + +/* ---------------------------------------------------------- INCVAL field of the INCCNT register ----------------------------------------------------------- */ + +/** Description of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_INCVAL_DESC "Counter value, this controls when the address will be updated (INCOFFSET will be added to the current address when this counter with its programmed value, INCVAL, expires)" + +/** Offset of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_INCVAL_LSB 0UL + +/** Size in bits of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_INCVAL_W (27UL) + +/** Mask for retrieving the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_INCVAL_MASK ATON_FIELD_MASK(0UL, 27UL) + +/** Reset value of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_INCVAL_DT 0x0UL + +/** Access rights of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_INCVAL_AC "RW" + +/** Check whether access to the INCVAL field of the INCCNT register is secured or not. */ +#define ATON_ARITH_INCCNT_INCVAL_S 0 + +/** Check whether access to the INCVAL field of the INCCNT register is privileged or not. */ +#define ATON_ARITH_INCCNT_INCVAL_P 0 + +/** Read the content of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_GET_INCVAL(REG) ATON_GET_FIELD(REG, ATON_ARITH_INCCNT_INCVAL_LSB, ATON_ARITH_INCCNT_INCVAL_W) + +/** Modify the content of the INCVAL field of the INCCNT register. */ +#define ATON_ARITH_INCCNT_SET_INCVAL(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INCCNT_INCVAL_LSB, ATON_ARITH_INCCNT_INCVAL_W, DATA) + + +/** + * Get the description of the INCVAL field of INCCNT register. + * + * \return the description of the INCVAL field of INCCNT register + */ + +static inline const int8_t *ATON_ARITH_INCCNT_INCVAL_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INCCNT_INCVAL_DESC; +} + + +/** + * Read the content of the INCVAL field of the INCCNT register. + * + * \param[in] reg is the value of the INCCNT register + * + * \return the content of the INCVAL field belonging to INCCNT register + */ + +static inline uint32_t ATON_ARITH_INCCNT_Get_INCVAL(uint32_t reg) +{ + return ATON_ARITH_INCCNT_GET_INCVAL(reg); +} + + +/** + * Write the content of the INCVAL field of the INCCNT register. + * + * \param[in] reg is the value of the INCCNT register + * \param[in] data is 27-bit value that must be written to the field + * + * \return the new content of the INCVAL field belonging to INCCNT register + */ + +static inline uint32_t ATON_ARITH_INCCNT_Set_INCVAL(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INCCNT_SET_INCVAL(reg, data); +} + + +/* ******************************************************* RSTCNT1 register of one of the ARITH Units ******************************************************* */ + +/** Offset of the RSTCNT1 register from the base address of the ARITH Unit. */ +#define ATON_ARITH_RSTCNT1_OFFSET 0x10UL + +/** Reset value of the RSTCNT1 register of the ARITH Unit. */ +#define ATON_ARITH_RSTCNT1_DT \ + (ATON_ARITH_RSTCNT1_RSTCNT_DT << ATON_ARITH_RSTCNT1_RSTCNT_LSB) + + + +/** Description of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_DESC "Reset counter 1" + +/** Address of the RSTCNT1 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT1_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_RSTCNT1_OFFSET) + +/** Get the content of the RSTCNT1 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT1_ADDR(UNIT))) + +/** Set the content of the RSTCNT1 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of RSTCNT1 register. + * + * \return the description of RSTCNT1 register + */ + +static inline const int8_t *ATON_ARITH_RSTCNT1_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_RSTCNT1_DESC; +} + + +/** + * Get the offset of the RSTCNT1 register. + * + * \return the offset of RSTCNT1 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT1_GetOffset(void) +{ + return ATON_ARITH_RSTCNT1_OFFSET; +} + + +/** + * Get the address of the RSTCNT1 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT1 register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of RSTCNT1 register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_RSTCNT1_GetAddr(uint32_t instance) +{ + return ATON_ARITH_RSTCNT1_ADDR(instance); +} + + +/** + * Read the content of the RSTCNT1 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT1 register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of RSTCNT1 register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_RSTCNT1_Get(uint32_t instance) +{ + return ATON_ARITH_RSTCNT1_GET(instance); +} + + +/** + * Write the content of the RSTCNT1 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT1 register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_RSTCNT1_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_RSTCNT1_SET(instance, data); +} + + +/* ---------------------------------------------------------- RSTCNT field of the RSTCNT1 register ---------------------------------------------------------- */ + +/** Description of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_DESC "Counter value, this controls when the address will be updated (the corresponding OFFSETx in ADDROFFSET will be added to the current address when this counter with its programmed value, RSTCNTx, expires)" + +/** Offset of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_LSB 0UL + +/** Size in bits of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_W (27UL) + +/** Mask for retrieving the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_MASK ATON_FIELD_MASK(0UL, 27UL) + +/** Reset value of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_DT 0x0UL + +/** Access rights of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_AC "RW" + +/** Check whether access to the RSTCNT field of the RSTCNT1 register is secured or not. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_S 0 + +/** Check whether access to the RSTCNT field of the RSTCNT1 register is privileged or not. */ +#define ATON_ARITH_RSTCNT1_RSTCNT_P 0 + +/** Read the content of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_GET_RSTCNT(REG) ATON_GET_FIELD(REG, ATON_ARITH_RSTCNT1_RSTCNT_LSB, ATON_ARITH_RSTCNT1_RSTCNT_W) + +/** Modify the content of the RSTCNT field of the RSTCNT1 register. */ +#define ATON_ARITH_RSTCNT1_SET_RSTCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_RSTCNT1_RSTCNT_LSB, ATON_ARITH_RSTCNT1_RSTCNT_W, DATA) + + +/** + * Get the description of the RSTCNT field of RSTCNT1 register. + * + * \return the description of the RSTCNT field of RSTCNT1 register + */ + +static inline const int8_t *ATON_ARITH_RSTCNT1_RSTCNT_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_RSTCNT1_RSTCNT_DESC; +} + + +/** + * Read the content of the RSTCNT field of the RSTCNT1 register. + * + * \param[in] reg is the value of the RSTCNT1 register + * + * \return the content of the RSTCNT field belonging to RSTCNT1 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT1_Get_RSTCNT(uint32_t reg) +{ + return ATON_ARITH_RSTCNT1_GET_RSTCNT(reg); +} + + +/** + * Write the content of the RSTCNT field of the RSTCNT1 register. + * + * \param[in] reg is the value of the RSTCNT1 register + * \param[in] data is 27-bit value that must be written to the field + * + * \return the new content of the RSTCNT field belonging to RSTCNT1 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT1_Set_RSTCNT(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_RSTCNT1_SET_RSTCNT(reg, data); +} + + +/* ******************************************************* RSTCNT2 register of one of the ARITH Units ******************************************************* */ + +/** Offset of the RSTCNT2 register from the base address of the ARITH Unit. */ +#define ATON_ARITH_RSTCNT2_OFFSET 0x14UL + +/** Reset value of the RSTCNT2 register of the ARITH Unit. */ +#define ATON_ARITH_RSTCNT2_DT \ + (ATON_ARITH_RSTCNT2_RSTCNT_DT << ATON_ARITH_RSTCNT2_RSTCNT_LSB) + + + +/** Description of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_DESC "Reset counter 2" + +/** Address of the RSTCNT2 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT2_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_RSTCNT2_OFFSET) + +/** Get the content of the RSTCNT2 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT2_ADDR(UNIT))) + +/** Set the content of the RSTCNT2 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of RSTCNT2 register. + * + * \return the description of RSTCNT2 register + */ + +static inline const int8_t *ATON_ARITH_RSTCNT2_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_RSTCNT2_DESC; +} + + +/** + * Get the offset of the RSTCNT2 register. + * + * \return the offset of RSTCNT2 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT2_GetOffset(void) +{ + return ATON_ARITH_RSTCNT2_OFFSET; +} + + +/** + * Get the address of the RSTCNT2 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT2 register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of RSTCNT2 register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_RSTCNT2_GetAddr(uint32_t instance) +{ + return ATON_ARITH_RSTCNT2_ADDR(instance); +} + + +/** + * Read the content of the RSTCNT2 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT2 register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of RSTCNT2 register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_RSTCNT2_Get(uint32_t instance) +{ + return ATON_ARITH_RSTCNT2_GET(instance); +} + + +/** + * Write the content of the RSTCNT2 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT2 register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_RSTCNT2_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_RSTCNT2_SET(instance, data); +} + + +/* ---------------------------------------------------------- RSTCNT field of the RSTCNT2 register ---------------------------------------------------------- */ + +/** Description of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_DESC "Counter value, this controls when the address will be updated (the corresponding OFFSETx in ADDROFFSET will be added to the current address when this counter with its programmed value, RSTCNTx, expires)" + +/** Offset of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_LSB 0UL + +/** Size in bits of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_W (27UL) + +/** Mask for retrieving the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_MASK ATON_FIELD_MASK(0UL, 27UL) + +/** Reset value of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_DT 0x0UL + +/** Access rights of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_AC "RW" + +/** Check whether access to the RSTCNT field of the RSTCNT2 register is secured or not. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_S 0 + +/** Check whether access to the RSTCNT field of the RSTCNT2 register is privileged or not. */ +#define ATON_ARITH_RSTCNT2_RSTCNT_P 0 + +/** Read the content of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_GET_RSTCNT(REG) ATON_GET_FIELD(REG, ATON_ARITH_RSTCNT2_RSTCNT_LSB, ATON_ARITH_RSTCNT2_RSTCNT_W) + +/** Modify the content of the RSTCNT field of the RSTCNT2 register. */ +#define ATON_ARITH_RSTCNT2_SET_RSTCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_RSTCNT2_RSTCNT_LSB, ATON_ARITH_RSTCNT2_RSTCNT_W, DATA) + + +/** + * Get the description of the RSTCNT field of RSTCNT2 register. + * + * \return the description of the RSTCNT field of RSTCNT2 register + */ + +static inline const int8_t *ATON_ARITH_RSTCNT2_RSTCNT_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_RSTCNT2_RSTCNT_DESC; +} + + +/** + * Read the content of the RSTCNT field of the RSTCNT2 register. + * + * \param[in] reg is the value of the RSTCNT2 register + * + * \return the content of the RSTCNT field belonging to RSTCNT2 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT2_Get_RSTCNT(uint32_t reg) +{ + return ATON_ARITH_RSTCNT2_GET_RSTCNT(reg); +} + + +/** + * Write the content of the RSTCNT field of the RSTCNT2 register. + * + * \param[in] reg is the value of the RSTCNT2 register + * \param[in] data is 27-bit value that must be written to the field + * + * \return the new content of the RSTCNT field belonging to RSTCNT2 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT2_Set_RSTCNT(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_RSTCNT2_SET_RSTCNT(reg, data); +} + + +/* ******************************************************* RSTCNT3 register of one of the ARITH Units ******************************************************* */ + +/** Offset of the RSTCNT3 register from the base address of the ARITH Unit. */ +#define ATON_ARITH_RSTCNT3_OFFSET 0x18UL + +/** Reset value of the RSTCNT3 register of the ARITH Unit. */ +#define ATON_ARITH_RSTCNT3_DT \ + (ATON_ARITH_RSTCNT3_RSTCNT_DT << ATON_ARITH_RSTCNT3_RSTCNT_LSB) + + + +/** Description of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_DESC "Reset counter 3" + +/** Address of the RSTCNT3 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT3_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_RSTCNT3_OFFSET) + +/** Get the content of the RSTCNT3 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT3_ADDR(UNIT))) + +/** Set the content of the RSTCNT3 register of one of the ARITH Units. */ +#define ATON_ARITH_RSTCNT3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT3_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of RSTCNT3 register. + * + * \return the description of RSTCNT3 register + */ + +static inline const int8_t *ATON_ARITH_RSTCNT3_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_RSTCNT3_DESC; +} + + +/** + * Get the offset of the RSTCNT3 register. + * + * \return the offset of RSTCNT3 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT3_GetOffset(void) +{ + return ATON_ARITH_RSTCNT3_OFFSET; +} + + +/** + * Get the address of the RSTCNT3 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT3 register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of RSTCNT3 register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_RSTCNT3_GetAddr(uint32_t instance) +{ + return ATON_ARITH_RSTCNT3_ADDR(instance); +} + + +/** + * Read the content of the RSTCNT3 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT3 register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of RSTCNT3 register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_RSTCNT3_Get(uint32_t instance) +{ + return ATON_ARITH_RSTCNT3_GET(instance); +} + + +/** + * Write the content of the RSTCNT3 register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT3 register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_RSTCNT3_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_RSTCNT3_SET(instance, data); +} + + +/* ---------------------------------------------------------- RSTCNT field of the RSTCNT3 register ---------------------------------------------------------- */ + +/** Description of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_DESC "Counter value, this controls when the address will be updated (the corresponding OFFSETx in ADDROFFSET will be added to the current address when this counter with its programmed value, RSTCNTx, expires)" + +/** Offset of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_LSB 0UL + +/** Size in bits of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_W (27UL) + +/** Mask for retrieving the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_MASK ATON_FIELD_MASK(0UL, 27UL) + +/** Reset value of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_DT 0x0UL + +/** Access rights of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_AC "RW" + +/** Check whether access to the RSTCNT field of the RSTCNT3 register is secured or not. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_S 0 + +/** Check whether access to the RSTCNT field of the RSTCNT3 register is privileged or not. */ +#define ATON_ARITH_RSTCNT3_RSTCNT_P 0 + +/** Read the content of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_GET_RSTCNT(REG) ATON_GET_FIELD(REG, ATON_ARITH_RSTCNT3_RSTCNT_LSB, ATON_ARITH_RSTCNT3_RSTCNT_W) + +/** Modify the content of the RSTCNT field of the RSTCNT3 register. */ +#define ATON_ARITH_RSTCNT3_SET_RSTCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_RSTCNT3_RSTCNT_LSB, ATON_ARITH_RSTCNT3_RSTCNT_W, DATA) + + +/** + * Get the description of the RSTCNT field of RSTCNT3 register. + * + * \return the description of the RSTCNT field of RSTCNT3 register + */ + +static inline const int8_t *ATON_ARITH_RSTCNT3_RSTCNT_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_RSTCNT3_RSTCNT_DESC; +} + + +/** + * Read the content of the RSTCNT field of the RSTCNT3 register. + * + * \param[in] reg is the value of the RSTCNT3 register + * + * \return the content of the RSTCNT field belonging to RSTCNT3 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT3_Get_RSTCNT(uint32_t reg) +{ + return ATON_ARITH_RSTCNT3_GET_RSTCNT(reg); +} + + +/** + * Write the content of the RSTCNT field of the RSTCNT3 register. + * + * \param[in] reg is the value of the RSTCNT3 register + * \param[in] data is 27-bit value that must be written to the field + * + * \return the new content of the RSTCNT field belonging to RSTCNT3 register + */ + +static inline uint32_t ATON_ARITH_RSTCNT3_Set_RSTCNT(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_RSTCNT3_SET_RSTCNT(reg, data); +} + + +/* ******************************************************* COEFFAC register of one of the ARITH Units ******************************************************* */ + +/** Offset of the COEFFAC register from the base address of the ARITH Unit. */ +#define ATON_ARITH_COEFFAC_OFFSET 0x1cUL + +/** Reset value of the COEFFAC register of the ARITH Unit. */ +#define ATON_ARITH_COEFFAC_DT \ + (ATON_ARITH_COEFFAC_A_DT << ATON_ARITH_COEFFAC_A_LSB) | \ + (ATON_ARITH_COEFFAC_C_DT << ATON_ARITH_COEFFAC_C_LSB) + + + +/** Description of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_DESC "Scalar coefficients A and C" + +/** Address of the COEFFAC register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFAC_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFFAC_OFFSET) + +/** Get the content of the COEFFAC register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFAC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFAC_ADDR(UNIT))) + +/** Set the content of the COEFFAC register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFAC_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFAC_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of COEFFAC register. + * + * \return the description of COEFFAC register + */ + +static inline const int8_t *ATON_ARITH_COEFFAC_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFAC_DESC; +} + + +/** + * Get the offset of the COEFFAC register. + * + * \return the offset of COEFFAC register + */ + +static inline uint32_t ATON_ARITH_COEFFAC_GetOffset(void) +{ + return ATON_ARITH_COEFFAC_OFFSET; +} + + +/** + * Get the address of the COEFFAC register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFAC register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of COEFFAC register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_COEFFAC_GetAddr(uint32_t instance) +{ + return ATON_ARITH_COEFFAC_ADDR(instance); +} + + +/** + * Read the content of the COEFFAC register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFAC register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of COEFFAC register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_COEFFAC_Get(uint32_t instance) +{ + return ATON_ARITH_COEFFAC_GET(instance); +} + + +/** + * Write the content of the COEFFAC register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFAC register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_COEFFAC_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_COEFFAC_SET(instance, data); +} + + +/* ------------------------------------------------------------ A field of the COEFFAC register ------------------------------------------------------------- */ + +/** Description of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_A_DESC "Scalar coefficient A" + +/** Offset of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_A_LSB 0UL + +/** Size in bits of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_A_W (16UL) + +/** Mask for retrieving the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_A_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_A_DT 0x0UL + +/** Access rights of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_A_AC "RW" + +/** Check whether access to the A field of the COEFFAC register is secured or not. */ +#define ATON_ARITH_COEFFAC_A_S 0 + +/** Check whether access to the A field of the COEFFAC register is privileged or not. */ +#define ATON_ARITH_COEFFAC_A_P 0 + +/** Read the content of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_GET_A(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFAC_A_LSB, ATON_ARITH_COEFFAC_A_W) + +/** Modify the content of the A field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_SET_A(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFAC_A_LSB, ATON_ARITH_COEFFAC_A_W, DATA) + + +/** + * Get the description of the A field of COEFFAC register. + * + * \return the description of the A field of COEFFAC register + */ + +static inline const int8_t *ATON_ARITH_COEFFAC_A_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFAC_A_DESC; +} + + +/** + * Read the content of the A field of the COEFFAC register. + * + * \param[in] reg is the value of the COEFFAC register + * + * \return the content of the A field belonging to COEFFAC register + */ + +static inline uint32_t ATON_ARITH_COEFFAC_Get_A(uint32_t reg) +{ + return ATON_ARITH_COEFFAC_GET_A(reg); +} + + +/** + * Write the content of the A field of the COEFFAC register. + * + * \param[in] reg is the value of the COEFFAC register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the A field belonging to COEFFAC register + */ + +static inline uint32_t ATON_ARITH_COEFFAC_Set_A(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_COEFFAC_SET_A(reg, data); +} + + +/* ------------------------------------------------------------ C field of the COEFFAC register ------------------------------------------------------------- */ + +/** Description of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_C_DESC "Scalar coefficient C" + +/** Offset of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_C_LSB 16UL + +/** Size in bits of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_C_W (16UL) + +/** Mask for retrieving the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_C_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_C_DT 0x0UL + +/** Access rights of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_C_AC "RW" + +/** Check whether access to the C field of the COEFFAC register is secured or not. */ +#define ATON_ARITH_COEFFAC_C_S 0 + +/** Check whether access to the C field of the COEFFAC register is privileged or not. */ +#define ATON_ARITH_COEFFAC_C_P 0 + +/** Read the content of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_GET_C(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFAC_C_LSB, ATON_ARITH_COEFFAC_C_W) + +/** Modify the content of the C field of the COEFFAC register. */ +#define ATON_ARITH_COEFFAC_SET_C(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFAC_C_LSB, ATON_ARITH_COEFFAC_C_W, DATA) + + +/** + * Get the description of the C field of COEFFAC register. + * + * \return the description of the C field of COEFFAC register + */ + +static inline const int8_t *ATON_ARITH_COEFFAC_C_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFAC_C_DESC; +} + + +/** + * Read the content of the C field of the COEFFAC register. + * + * \param[in] reg is the value of the COEFFAC register + * + * \return the content of the C field belonging to COEFFAC register + */ + +static inline uint32_t ATON_ARITH_COEFFAC_Get_C(uint32_t reg) +{ + return ATON_ARITH_COEFFAC_GET_C(reg); +} + + +/** + * Write the content of the C field of the COEFFAC register. + * + * \param[in] reg is the value of the COEFFAC register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the C field belonging to COEFFAC register + */ + +static inline uint32_t ATON_ARITH_COEFFAC_Set_C(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_COEFFAC_SET_C(reg, data); +} + + +/* ******************************************************* COEFFB register of one of the ARITH Units ******************************************************** */ + +/** Offset of the COEFFB register from the base address of the ARITH Unit. */ +#define ATON_ARITH_COEFFB_OFFSET 0x20UL + +/** Reset value of the COEFFB register of the ARITH Unit. */ +#define ATON_ARITH_COEFFB_DT \ + (ATON_ARITH_COEFFB_B_DT << ATON_ARITH_COEFFB_B_LSB) + + + +/** Description of the COEFFB register. */ +#define ATON_ARITH_COEFFB_DESC "Scalar coefficient B" + +/** Address of the COEFFB register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFB_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFFB_OFFSET) + +/** Get the content of the COEFFB register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFB_ADDR(UNIT))) + +/** Set the content of the COEFFB register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of COEFFB register. + * + * \return the description of COEFFB register + */ + +static inline const int8_t *ATON_ARITH_COEFFB_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFB_DESC; +} + + +/** + * Get the offset of the COEFFB register. + * + * \return the offset of COEFFB register + */ + +static inline uint32_t ATON_ARITH_COEFFB_GetOffset(void) +{ + return ATON_ARITH_COEFFB_OFFSET; +} + + +/** + * Get the address of the COEFFB register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFB register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of COEFFB register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_COEFFB_GetAddr(uint32_t instance) +{ + return ATON_ARITH_COEFFB_ADDR(instance); +} + + +/** + * Read the content of the COEFFB register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFB register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of COEFFB register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_COEFFB_Get(uint32_t instance) +{ + return ATON_ARITH_COEFFB_GET(instance); +} + + +/** + * Write the content of the COEFFB register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFB register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_COEFFB_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_COEFFB_SET(instance, data); +} + + +/* ------------------------------------------------------------- B field of the COEFFB register ------------------------------------------------------------- */ + +/** Description of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_B_DESC "Scalar coefficient B" + +/** Offset of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_B_LSB 0UL + +/** Size in bits of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_B_W (16UL) + +/** Mask for retrieving the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_B_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_B_DT 0x0UL + +/** Access rights of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_B_AC "RW" + +/** Check whether access to the B field of the COEFFB register is secured or not. */ +#define ATON_ARITH_COEFFB_B_S 0 + +/** Check whether access to the B field of the COEFFB register is privileged or not. */ +#define ATON_ARITH_COEFFB_B_P 0 + +/** Read the content of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_GET_B(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFB_B_LSB, ATON_ARITH_COEFFB_B_W) + +/** Modify the content of the B field of the COEFFB register. */ +#define ATON_ARITH_COEFFB_SET_B(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFB_B_LSB, ATON_ARITH_COEFFB_B_W, DATA) + + +/** + * Get the description of the B field of COEFFB register. + * + * \return the description of the B field of COEFFB register + */ + +static inline const int8_t *ATON_ARITH_COEFFB_B_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFB_B_DESC; +} + + +/** + * Read the content of the B field of the COEFFB register. + * + * \param[in] reg is the value of the COEFFB register + * + * \return the content of the B field belonging to COEFFB register + */ + +static inline uint32_t ATON_ARITH_COEFFB_Get_B(uint32_t reg) +{ + return ATON_ARITH_COEFFB_GET_B(reg); +} + + +/** + * Write the content of the B field of the COEFFB register. + * + * \param[in] reg is the value of the COEFFB register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the B field belonging to COEFFB register + */ + +static inline uint32_t ATON_ARITH_COEFFB_Set_B(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_COEFFB_SET_B(reg, data); +} + + +/* ***************************************************** ADDROFFSET register of one of the ARITH Units ****************************************************** */ + +/** Offset of the ADDROFFSET register from the base address of the ARITH Unit. */ +#define ATON_ARITH_ADDROFFSET_OFFSET 0x24UL + +/** Reset value of the ADDROFFSET register of the ARITH Unit. */ +#define ATON_ARITH_ADDROFFSET_DT \ + (ATON_ARITH_ADDROFFSET_OFFSET1_DT << ATON_ARITH_ADDROFFSET_OFFSET1_LSB) | \ + (ATON_ARITH_ADDROFFSET_OFFSET2_DT << ATON_ARITH_ADDROFFSET_OFFSET2_LSB) | \ + (ATON_ARITH_ADDROFFSET_OFFSET3_DT << ATON_ARITH_ADDROFFSET_OFFSET3_LSB) + + + +/** Description of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_DESC "Address offsets" + +/** Address of the ADDROFFSET register of one of the ARITH Units. */ +#define ATON_ARITH_ADDROFFSET_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_ADDROFFSET_OFFSET) + +/** Get the content of the ADDROFFSET register of one of the ARITH Units. */ +#define ATON_ARITH_ADDROFFSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_ADDROFFSET_ADDR(UNIT))) + +/** Set the content of the ADDROFFSET register of one of the ARITH Units. */ +#define ATON_ARITH_ADDROFFSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_ADDROFFSET_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ADDROFFSET register. + * + * \return the description of ADDROFFSET register + */ + +static inline const int8_t *ATON_ARITH_ADDROFFSET_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_ADDROFFSET_DESC; +} + + +/** + * Get the offset of the ADDROFFSET register. + * + * \return the offset of ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_GetOffset(void) +{ + return ATON_ARITH_ADDROFFSET_OFFSET; +} + + +/** + * Get the address of the ADDROFFSET register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the ADDROFFSET register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of ADDROFFSET register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_GetAddr(uint32_t instance) +{ + return ATON_ARITH_ADDROFFSET_ADDR(instance); +} + + +/** + * Read the content of the ADDROFFSET register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the ADDROFFSET register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of ADDROFFSET register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Get(uint32_t instance) +{ + return ATON_ARITH_ADDROFFSET_GET(instance); +} + + +/** + * Write the content of the ADDROFFSET register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the ADDROFFSET register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_ADDROFFSET_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_ADDROFFSET_SET(instance, data); +} + + +/* -------------------------------------------------------- OFFSET1 field of the ADDROFFSET register -------------------------------------------------------- */ + +/** Description of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_DESC "Offset to be added to address when reset counter RSTCNT1 expires" + +/** Offset of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_LSB 0UL + +/** Size in bits of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_W (9UL) + +/** Mask for retrieving the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_MASK ATON_FIELD_MASK(0UL, 9UL) + +/** Reset value of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_DT 0x0UL + +/** Access rights of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_AC "RW" + +/** Check whether access to the OFFSET1 field of the ADDROFFSET register is secured or not. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_S 0 + +/** Check whether access to the OFFSET1 field of the ADDROFFSET register is privileged or not. */ +#define ATON_ARITH_ADDROFFSET_OFFSET1_P 0 + +/** Read the content of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_GET_OFFSET1(REG) ATON_GET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET1_LSB, ATON_ARITH_ADDROFFSET_OFFSET1_W) + +/** Modify the content of the OFFSET1 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_SET_OFFSET1(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET1_LSB, ATON_ARITH_ADDROFFSET_OFFSET1_W, DATA) + + +/** + * Get the description of the OFFSET1 field of ADDROFFSET register. + * + * \return the description of the OFFSET1 field of ADDROFFSET register + */ + +static inline const int8_t *ATON_ARITH_ADDROFFSET_OFFSET1_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_ADDROFFSET_OFFSET1_DESC; +} + + +/** + * Read the content of the OFFSET1 field of the ADDROFFSET register. + * + * \param[in] reg is the value of the ADDROFFSET register + * + * \return the content of the OFFSET1 field belonging to ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Get_OFFSET1(uint32_t reg) +{ + return ATON_ARITH_ADDROFFSET_GET_OFFSET1(reg); +} + + +/** + * Write the content of the OFFSET1 field of the ADDROFFSET register. + * + * \param[in] reg is the value of the ADDROFFSET register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the OFFSET1 field belonging to ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Set_OFFSET1(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_ADDROFFSET_SET_OFFSET1(reg, data); +} + + +/* -------------------------------------------------------- OFFSET2 field of the ADDROFFSET register -------------------------------------------------------- */ + +/** Description of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_DESC "Offset to be added to address when reset counter RSTCNT2 expires" + +/** Offset of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_LSB 9UL + +/** Size in bits of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_W (9UL) + +/** Mask for retrieving the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_MASK ATON_FIELD_MASK(9UL, 9UL) + +/** Reset value of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_DT 0x0UL + +/** Access rights of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_AC "RW" + +/** Check whether access to the OFFSET2 field of the ADDROFFSET register is secured or not. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_S 0 + +/** Check whether access to the OFFSET2 field of the ADDROFFSET register is privileged or not. */ +#define ATON_ARITH_ADDROFFSET_OFFSET2_P 0 + +/** Read the content of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_GET_OFFSET2(REG) ATON_GET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET2_LSB, ATON_ARITH_ADDROFFSET_OFFSET2_W) + +/** Modify the content of the OFFSET2 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_SET_OFFSET2(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET2_LSB, ATON_ARITH_ADDROFFSET_OFFSET2_W, DATA) + + +/** + * Get the description of the OFFSET2 field of ADDROFFSET register. + * + * \return the description of the OFFSET2 field of ADDROFFSET register + */ + +static inline const int8_t *ATON_ARITH_ADDROFFSET_OFFSET2_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_ADDROFFSET_OFFSET2_DESC; +} + + +/** + * Read the content of the OFFSET2 field of the ADDROFFSET register. + * + * \param[in] reg is the value of the ADDROFFSET register + * + * \return the content of the OFFSET2 field belonging to ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Get_OFFSET2(uint32_t reg) +{ + return ATON_ARITH_ADDROFFSET_GET_OFFSET2(reg); +} + + +/** + * Write the content of the OFFSET2 field of the ADDROFFSET register. + * + * \param[in] reg is the value of the ADDROFFSET register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the OFFSET2 field belonging to ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Set_OFFSET2(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_ADDROFFSET_SET_OFFSET2(reg, data); +} + + +/* -------------------------------------------------------- OFFSET3 field of the ADDROFFSET register -------------------------------------------------------- */ + +/** Description of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_DESC "Offset to be added to address when reset counter RSTCNT3 expires" + +/** Offset of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_LSB 18UL + +/** Size in bits of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_W (9UL) + +/** Mask for retrieving the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_MASK ATON_FIELD_MASK(18UL, 9UL) + +/** Reset value of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_DT 0x0UL + +/** Access rights of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_AC "RW" + +/** Check whether access to the OFFSET3 field of the ADDROFFSET register is secured or not. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_S 0 + +/** Check whether access to the OFFSET3 field of the ADDROFFSET register is privileged or not. */ +#define ATON_ARITH_ADDROFFSET_OFFSET3_P 0 + +/** Read the content of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_GET_OFFSET3(REG) ATON_GET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET3_LSB, ATON_ARITH_ADDROFFSET_OFFSET3_W) + +/** Modify the content of the OFFSET3 field of the ADDROFFSET register. */ +#define ATON_ARITH_ADDROFFSET_SET_OFFSET3(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET3_LSB, ATON_ARITH_ADDROFFSET_OFFSET3_W, DATA) + + +/** + * Get the description of the OFFSET3 field of ADDROFFSET register. + * + * \return the description of the OFFSET3 field of ADDROFFSET register + */ + +static inline const int8_t *ATON_ARITH_ADDROFFSET_OFFSET3_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_ADDROFFSET_OFFSET3_DESC; +} + + +/** + * Read the content of the OFFSET3 field of the ADDROFFSET register. + * + * \param[in] reg is the value of the ADDROFFSET register + * + * \return the content of the OFFSET3 field belonging to ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Get_OFFSET3(uint32_t reg) +{ + return ATON_ARITH_ADDROFFSET_GET_OFFSET3(reg); +} + + +/** + * Write the content of the OFFSET3 field of the ADDROFFSET register. + * + * \param[in] reg is the value of the ADDROFFSET register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the OFFSET3 field belonging to ADDROFFSET register + */ + +static inline uint32_t ATON_ARITH_ADDROFFSET_Set_OFFSET3(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_ADDROFFSET_SET_OFFSET3(reg, data); +} + + +/* ****************************************************** INCOFFSET register of one of the ARITH Units ****************************************************** */ + +/** Offset of the INCOFFSET register from the base address of the ARITH Unit. */ +#define ATON_ARITH_INCOFFSET_OFFSET 0x28UL + +/** Reset value of the INCOFFSET register of the ARITH Unit. */ +#define ATON_ARITH_INCOFFSET_DT \ + (ATON_ARITH_INCOFFSET_VAL_DT << ATON_ARITH_INCOFFSET_VAL_LSB) + + + +/** Description of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_DESC "Address increment offset" + +/** Address of the INCOFFSET register of one of the ARITH Units. */ +#define ATON_ARITH_INCOFFSET_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_INCOFFSET_OFFSET) + +/** Get the content of the INCOFFSET register of one of the ARITH Units. */ +#define ATON_ARITH_INCOFFSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCOFFSET_ADDR(UNIT))) + +/** Set the content of the INCOFFSET register of one of the ARITH Units. */ +#define ATON_ARITH_INCOFFSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCOFFSET_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INCOFFSET register. + * + * \return the description of INCOFFSET register + */ + +static inline const int8_t *ATON_ARITH_INCOFFSET_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_INCOFFSET_DESC; +} + + +/** + * Get the offset of the INCOFFSET register. + * + * \return the offset of INCOFFSET register + */ + +static inline uint32_t ATON_ARITH_INCOFFSET_GetOffset(void) +{ + return ATON_ARITH_INCOFFSET_OFFSET; +} + + +/** + * Get the address of the INCOFFSET register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCOFFSET register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of INCOFFSET register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_INCOFFSET_GetAddr(uint32_t instance) +{ + return ATON_ARITH_INCOFFSET_ADDR(instance); +} + + +/** + * Read the content of the INCOFFSET register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCOFFSET register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of INCOFFSET register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_INCOFFSET_Get(uint32_t instance) +{ + return ATON_ARITH_INCOFFSET_GET(instance); +} + + +/** + * Write the content of the INCOFFSET register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCOFFSET register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_INCOFFSET_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_INCOFFSET_SET(instance, data); +} + + +/* ---------------------------------------------------------- VAL field of the INCOFFSET register ----------------------------------------------------------- */ + +/** Description of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_VAL_DESC "Offset to be added to address when increment counter INCCNT expires" + +/** Offset of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_VAL_LSB 0UL + +/** Size in bits of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_VAL_W (9UL) + +/** Mask for retrieving the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_VAL_MASK ATON_FIELD_MASK(0UL, 9UL) + +/** Reset value of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_VAL_DT 0x0UL + +/** Access rights of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_VAL_AC "RW" + +/** Check whether access to the VAL field of the INCOFFSET register is secured or not. */ +#define ATON_ARITH_INCOFFSET_VAL_S 0 + +/** Check whether access to the VAL field of the INCOFFSET register is privileged or not. */ +#define ATON_ARITH_INCOFFSET_VAL_P 0 + +/** Read the content of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_GET_VAL(REG) ATON_GET_FIELD(REG, ATON_ARITH_INCOFFSET_VAL_LSB, ATON_ARITH_INCOFFSET_VAL_W) + +/** Modify the content of the VAL field of the INCOFFSET register. */ +#define ATON_ARITH_INCOFFSET_SET_VAL(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INCOFFSET_VAL_LSB, ATON_ARITH_INCOFFSET_VAL_W, DATA) + + +/** + * Get the description of the VAL field of INCOFFSET register. + * + * \return the description of the VAL field of INCOFFSET register + */ + +static inline const int8_t *ATON_ARITH_INCOFFSET_VAL_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INCOFFSET_VAL_DESC; +} + + +/** + * Read the content of the VAL field of the INCOFFSET register. + * + * \param[in] reg is the value of the INCOFFSET register + * + * \return the content of the VAL field belonging to INCOFFSET register + */ + +static inline uint32_t ATON_ARITH_INCOFFSET_Get_VAL(uint32_t reg) +{ + return ATON_ARITH_INCOFFSET_GET_VAL(reg); +} + + +/** + * Write the content of the VAL field of the INCOFFSET register. + * + * \param[in] reg is the value of the INCOFFSET register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the VAL field belonging to INCOFFSET register + */ + +static inline uint32_t ATON_ARITH_INCOFFSET_Set_VAL(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INCOFFSET_SET_VAL(reg, data); +} + + +/* **************************************************** TRANSLATEADDR register of one of the ARITH Units **************************************************** */ + +/** Offset of the TRANSLATEADDR register from the base address of the ARITH Unit. */ +#define ATON_ARITH_TRANSLATEADDR_OFFSET 0x2cUL + +/** Reset value of the TRANSLATEADDR register of the ARITH Unit. */ +#define ATON_ARITH_TRANSLATEADDR_DT \ + (ATON_ARITH_TRANSLATEADDR_EN_DT << ATON_ARITH_TRANSLATEADDR_EN_LSB) + + + +/** Description of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_DESC "Address translation control for memory" + +/** Address of the TRANSLATEADDR register of one of the ARITH Units. */ +#define ATON_ARITH_TRANSLATEADDR_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_TRANSLATEADDR_OFFSET) + +/** Get the content of the TRANSLATEADDR register of one of the ARITH Units. */ +#define ATON_ARITH_TRANSLATEADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_TRANSLATEADDR_ADDR(UNIT))) + +/** Set the content of the TRANSLATEADDR register of one of the ARITH Units. */ +#define ATON_ARITH_TRANSLATEADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_TRANSLATEADDR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRANSLATEADDR register. + * + * \return the description of TRANSLATEADDR register + */ + +static inline const int8_t *ATON_ARITH_TRANSLATEADDR_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_TRANSLATEADDR_DESC; +} + + +/** + * Get the offset of the TRANSLATEADDR register. + * + * \return the offset of TRANSLATEADDR register + */ + +static inline uint32_t ATON_ARITH_TRANSLATEADDR_GetOffset(void) +{ + return ATON_ARITH_TRANSLATEADDR_OFFSET; +} + + +/** + * Get the address of the TRANSLATEADDR register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the TRANSLATEADDR register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of TRANSLATEADDR register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_TRANSLATEADDR_GetAddr(uint32_t instance) +{ + return ATON_ARITH_TRANSLATEADDR_ADDR(instance); +} + + +/** + * Read the content of the TRANSLATEADDR register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the TRANSLATEADDR register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of TRANSLATEADDR register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_TRANSLATEADDR_Get(uint32_t instance) +{ + return ATON_ARITH_TRANSLATEADDR_GET(instance); +} + + +/** + * Write the content of the TRANSLATEADDR register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the TRANSLATEADDR register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_TRANSLATEADDR_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_TRANSLATEADDR_SET(instance, data); +} + + +/* --------------------------------------------------------- EN field of the TRANSLATEADDR register --------------------------------------------------------- */ + +/** Description of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_EN_DESC "address translation control" + +/** Offset of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_EN_LSB 0UL + +/** Size in bits of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_EN_DT 0x0UL + +/** Access rights of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_EN_AC "RW" + +/** Check whether access to the EN field of the TRANSLATEADDR register is secured or not. */ +#define ATON_ARITH_TRANSLATEADDR_EN_S 0 + +/** Check whether access to the EN field of the TRANSLATEADDR register is privileged or not. */ +#define ATON_ARITH_TRANSLATEADDR_EN_P 0 + +/** Read the content of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_GET_EN(REG) ATON_GET_FIELD(REG, ATON_ARITH_TRANSLATEADDR_EN_LSB, ATON_ARITH_TRANSLATEADDR_EN_W) + +/** Modify the content of the EN field of the TRANSLATEADDR register. */ +#define ATON_ARITH_TRANSLATEADDR_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_TRANSLATEADDR_EN_LSB, ATON_ARITH_TRANSLATEADDR_EN_W, DATA) + + +/** + * Get the description of the EN field of TRANSLATEADDR register. + * + * \return the description of the EN field of TRANSLATEADDR register + */ + +static inline const int8_t *ATON_ARITH_TRANSLATEADDR_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_TRANSLATEADDR_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRANSLATEADDR register. + * + * \param[in] reg is the value of the TRANSLATEADDR register + * + * \return the content of the EN field belonging to TRANSLATEADDR register + */ + +static inline uint32_t ATON_ARITH_TRANSLATEADDR_Get_EN(uint32_t reg) +{ + return ATON_ARITH_TRANSLATEADDR_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRANSLATEADDR register. + * + * \param[in] reg is the value of the TRANSLATEADDR register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRANSLATEADDR register + */ + +static inline uint32_t ATON_ARITH_TRANSLATEADDR_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_TRANSLATEADDR_SET_EN(reg, data); +} + + +/* ****************************************************** COEFFADDR register of one of the ARITH Units ****************************************************** */ + +/** Offset of the COEFFADDR register from the base address of the ARITH Unit. */ +#define ATON_ARITH_COEFFADDR_OFFSET 0x30UL + +/** Reset value of the COEFFADDR register of the ARITH Unit. */ +#define ATON_ARITH_COEFFADDR_DT \ + (ATON_ARITH_COEFFADDR_ADDR_DT << ATON_ARITH_COEFFADDR_ADDR_LSB) + + + +/** Description of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_DESC "Coeff Address" + +/** Address of the COEFFADDR register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFADDR_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFFADDR_OFFSET) + +/** Get the content of the COEFFADDR register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFADDR_ADDR(UNIT))) + +/** Set the content of the COEFFADDR register of one of the ARITH Units. */ +#define ATON_ARITH_COEFFADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFADDR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of COEFFADDR register. + * + * \return the description of COEFFADDR register + */ + +static inline const int8_t *ATON_ARITH_COEFFADDR_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFADDR_DESC; +} + + +/** + * Get the offset of the COEFFADDR register. + * + * \return the offset of COEFFADDR register + */ + +static inline uint32_t ATON_ARITH_COEFFADDR_GetOffset(void) +{ + return ATON_ARITH_COEFFADDR_OFFSET; +} + + +/** + * Get the address of the COEFFADDR register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFADDR register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of COEFFADDR register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_COEFFADDR_GetAddr(uint32_t instance) +{ + return ATON_ARITH_COEFFADDR_ADDR(instance); +} + + +/** + * Read the content of the COEFFADDR register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFADDR register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of COEFFADDR register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_COEFFADDR_Get(uint32_t instance) +{ + return ATON_ARITH_COEFFADDR_GET(instance); +} + + +/** + * Write the content of the COEFFADDR register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFADDR register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_COEFFADDR_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_COEFFADDR_SET(instance, data); +} + + +/* ---------------------------------------------------------- ADDR field of the COEFFADDR register ---------------------------------------------------------- */ + +/** Description of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_ADDR_DESC "Writing will set the start address of coeff memory. Reading this register will return the current address in use in the datapath, ie. the address of the coeffs to be read next. The address will take effect only after the block has been enabled and a valid stream is input. Subsequent updates to this register will take effect only after the clear bit has been set in the control register" + +/** Offset of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_ADDR_LSB 0UL + +/** Size in bits of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_ADDR_W (9UL) + +/** Mask for retrieving the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_ADDR_MASK ATON_FIELD_MASK(0UL, 9UL) + +/** Reset value of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_ADDR_DT 0x0UL + +/** Access rights of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_ADDR_AC "RW" + +/** Check whether access to the ADDR field of the COEFFADDR register is secured or not. */ +#define ATON_ARITH_COEFFADDR_ADDR_S 0 + +/** Check whether access to the ADDR field of the COEFFADDR register is privileged or not. */ +#define ATON_ARITH_COEFFADDR_ADDR_P 0 + +/** Read the content of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_GET_ADDR(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFADDR_ADDR_LSB, ATON_ARITH_COEFFADDR_ADDR_W) + +/** Modify the content of the ADDR field of the COEFFADDR register. */ +#define ATON_ARITH_COEFFADDR_SET_ADDR(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFADDR_ADDR_LSB, ATON_ARITH_COEFFADDR_ADDR_W, DATA) + + +/** + * Get the description of the ADDR field of COEFFADDR register. + * + * \return the description of the ADDR field of COEFFADDR register + */ + +static inline const int8_t *ATON_ARITH_COEFFADDR_ADDR_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_COEFFADDR_ADDR_DESC; +} + + +/** + * Read the content of the ADDR field of the COEFFADDR register. + * + * \param[in] reg is the value of the COEFFADDR register + * + * \return the content of the ADDR field belonging to COEFFADDR register + */ + +static inline uint32_t ATON_ARITH_COEFFADDR_Get_ADDR(uint32_t reg) +{ + return ATON_ARITH_COEFFADDR_GET_ADDR(reg); +} + + +/** + * Write the content of the ADDR field of the COEFFADDR register. + * + * \param[in] reg is the value of the COEFFADDR register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the ADDR field belonging to COEFFADDR register + */ + +static inline uint32_t ATON_ARITH_COEFFADDR_Set_ADDR(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_COEFFADDR_SET_ADDR(reg, data); +} + + +/* ****************************************************** INSHIFTER register of one of the ARITH Units ****************************************************** */ + +/** Offset of the INSHIFTER register from the base address of the ARITH Unit. */ +#define ATON_ARITH_INSHIFTER_OFFSET 0x34UL + +/** Reset value of the INSHIFTER register of the ARITH Unit. */ +#define ATON_ARITH_INSHIFTER_DT \ + (ATON_ARITH_INSHIFTER_FBYTESX_DT << ATON_ARITH_INSHIFTER_FBYTESX_LSB) | \ + (ATON_ARITH_INSHIFTER_FSHIFTX_DT << ATON_ARITH_INSHIFTER_FSHIFTX_LSB) | \ + (ATON_ARITH_INSHIFTER_FROUNDX_DT << ATON_ARITH_INSHIFTER_FROUNDX_LSB) | \ + (ATON_ARITH_INSHIFTER_FSATX_DT << ATON_ARITH_INSHIFTER_FSATX_LSB) | \ + (ATON_ARITH_INSHIFTER_FRNDMODEX_DT << ATON_ARITH_INSHIFTER_FRNDMODEX_LSB) | \ + (ATON_ARITH_INSHIFTER_FOBYTESX_DT << ATON_ARITH_INSHIFTER_FOBYTESX_LSB) | \ + (ATON_ARITH_INSHIFTER_FBYTESY_DT << ATON_ARITH_INSHIFTER_FBYTESY_LSB) | \ + (ATON_ARITH_INSHIFTER_FSHIFTY_DT << ATON_ARITH_INSHIFTER_FSHIFTY_LSB) | \ + (ATON_ARITH_INSHIFTER_FROUNDY_DT << ATON_ARITH_INSHIFTER_FROUNDY_LSB) | \ + (ATON_ARITH_INSHIFTER_FSATY_DT << ATON_ARITH_INSHIFTER_FSATY_LSB) | \ + (ATON_ARITH_INSHIFTER_FRNDMODEY_DT << ATON_ARITH_INSHIFTER_FRNDMODEY_LSB) | \ + (ATON_ARITH_INSHIFTER_FOBYTESY_DT << ATON_ARITH_INSHIFTER_FOBYTESY_LSB) + + + +/** Description of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_DESC "input shifter configuration" + +/** Address of the INSHIFTER register of one of the ARITH Units. */ +#define ATON_ARITH_INSHIFTER_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_INSHIFTER_OFFSET) + +/** Get the content of the INSHIFTER register of one of the ARITH Units. */ +#define ATON_ARITH_INSHIFTER_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_INSHIFTER_ADDR(UNIT))) + +/** Set the content of the INSHIFTER register of one of the ARITH Units. */ +#define ATON_ARITH_INSHIFTER_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_INSHIFTER_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of INSHIFTER register. + * + * \return the description of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_DESC; +} + + +/** + * Get the offset of the INSHIFTER register. + * + * \return the offset of INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_GetOffset(void) +{ + return ATON_ARITH_INSHIFTER_OFFSET; +} + + +/** + * Get the address of the INSHIFTER register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INSHIFTER register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of INSHIFTER register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_GetAddr(uint32_t instance) +{ + return ATON_ARITH_INSHIFTER_ADDR(instance); +} + + +/** + * Read the content of the INSHIFTER register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INSHIFTER register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of INSHIFTER register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get(uint32_t instance) +{ + return ATON_ARITH_INSHIFTER_GET(instance); +} + + +/** + * Write the content of the INSHIFTER register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INSHIFTER register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_INSHIFTER_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_INSHIFTER_SET(instance, data); +} + + +/* -------------------------------------------------------- FBYTESX field of the INSHIFTER register --------------------------------------------------------- */ + +/** Description of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_DESC "Input data width in bytes for stream X. Valid values are 1,2 or 3 bytes" + +/** Offset of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_LSB 0UL + +/** Size in bits of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_W (2UL) + +/** Mask for retrieving the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_DT 0x2UL + +/** Access rights of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_AC "RW" + +/** Check whether access to the FBYTESX field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_S 0 + +/** Check whether access to the FBYTESX field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FBYTESX_P 0 + +/** Read the content of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FBYTESX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESX_LSB, ATON_ARITH_INSHIFTER_FBYTESX_W) + +/** Modify the content of the FBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FBYTESX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESX_LSB, ATON_ARITH_INSHIFTER_FBYTESX_W, DATA) + + +/** + * Get the description of the FBYTESX field of INSHIFTER register. + * + * \return the description of the FBYTESX field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FBYTESX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FBYTESX_DESC; +} + + +/** + * Read the content of the FBYTESX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FBYTESX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FBYTESX(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FBYTESX(reg); +} + + +/** + * Write the content of the FBYTESX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FBYTESX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FBYTESX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FBYTESX(reg, data); +} + + +/* -------------------------------------------------------- FSHIFTX field of the INSHIFTER register --------------------------------------------------------- */ + +/** Description of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_DESC "Input feature data shift for stream X. Range [0-40]. For no shift, set to 16" + +/** Offset of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_LSB 2UL + +/** Size in bits of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_W (6UL) + +/** Mask for retrieving the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_MASK ATON_FIELD_MASK(2UL, 6UL) + +/** Reset value of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_DT 0x10UL + +/** Access rights of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_AC "RW" + +/** Check whether access to the FSHIFTX field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_S 0 + +/** Check whether access to the FSHIFTX field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FSHIFTX_P 0 + +/** Read the content of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FSHIFTX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTX_LSB, ATON_ARITH_INSHIFTER_FSHIFTX_W) + +/** Modify the content of the FSHIFTX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FSHIFTX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTX_LSB, ATON_ARITH_INSHIFTER_FSHIFTX_W, DATA) + + +/** + * Get the description of the FSHIFTX field of INSHIFTER register. + * + * \return the description of the FSHIFTX field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FSHIFTX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FSHIFTX_DESC; +} + + +/** + * Read the content of the FSHIFTX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FSHIFTX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSHIFTX(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FSHIFTX(reg); +} + + +/** + * Write the content of the FSHIFTX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the FSHIFTX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSHIFTX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FSHIFTX(reg, data); +} + + +/* -------------------------------------------------------- FROUNDX field of the INSHIFTER register --------------------------------------------------------- */ + +/** Description of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_DESC "Input feature data rounding for stream X" + +/** Offset of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_LSB 8UL + +/** Size in bits of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_W (1UL) + +/** Mask for retrieving the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_MASK ATON_FIELD_MASK(8UL, 1UL) + +/** Reset value of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_DT 0x0UL + +/** Access rights of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_AC "RW" + +/** Check whether access to the FROUNDX field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_S 0 + +/** Check whether access to the FROUNDX field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FROUNDX_P 0 + +/** Read the content of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FROUNDX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDX_LSB, ATON_ARITH_INSHIFTER_FROUNDX_W) + +/** Modify the content of the FROUNDX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FROUNDX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDX_LSB, ATON_ARITH_INSHIFTER_FROUNDX_W, DATA) + + +/** + * Get the description of the FROUNDX field of INSHIFTER register. + * + * \return the description of the FROUNDX field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FROUNDX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FROUNDX_DESC; +} + + +/** + * Read the content of the FROUNDX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FROUNDX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FROUNDX(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FROUNDX(reg); +} + + +/** + * Write the content of the FROUNDX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FROUNDX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FROUNDX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FROUNDX(reg, data); +} + + +/* --------------------------------------------------------- FSATX field of the INSHIFTER register ---------------------------------------------------------- */ + +/** Description of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATX_DESC "Input feature data saturation for stream X" + +/** Offset of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATX_LSB 9UL + +/** Size in bits of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATX_W (1UL) + +/** Mask for retrieving the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATX_MASK ATON_FIELD_MASK(9UL, 1UL) + +/** Reset value of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATX_DT 0x0UL + +/** Access rights of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATX_AC "RW" + +/** Check whether access to the FSATX field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FSATX_S 0 + +/** Check whether access to the FSATX field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FSATX_P 0 + +/** Read the content of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FSATX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATX_LSB, ATON_ARITH_INSHIFTER_FSATX_W) + +/** Modify the content of the FSATX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FSATX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATX_LSB, ATON_ARITH_INSHIFTER_FSATX_W, DATA) + + +/** + * Get the description of the FSATX field of INSHIFTER register. + * + * \return the description of the FSATX field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FSATX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FSATX_DESC; +} + + +/** + * Read the content of the FSATX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FSATX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSATX(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FSATX(reg); +} + + +/** + * Write the content of the FSATX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSATX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSATX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FSATX(reg, data); +} + + +/* ------------------------------------------------------- FRNDMODEX field of the INSHIFTER register -------------------------------------------------------- */ + +/** Description of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_DESC "Input feature data rounding mode for stream X. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_LSB 10UL + +/** Size in bits of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_W (2UL) + +/** Mask for retrieving the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_MASK ATON_FIELD_MASK(10UL, 2UL) + +/** Reset value of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_DT 0x0UL + +/** Access rights of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_AC "RW" + +/** Check whether access to the FRNDMODEX field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_S 0 + +/** Check whether access to the FRNDMODEX field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEX_P 0 + +/** Read the content of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FRNDMODEX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEX_LSB, ATON_ARITH_INSHIFTER_FRNDMODEX_W) + +/** Modify the content of the FRNDMODEX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FRNDMODEX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEX_LSB, ATON_ARITH_INSHIFTER_FRNDMODEX_W, DATA) + + +/** + * Get the description of the FRNDMODEX field of INSHIFTER register. + * + * \return the description of the FRNDMODEX field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FRNDMODEX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FRNDMODEX_DESC; +} + + +/** + * Read the content of the FRNDMODEX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FRNDMODEX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FRNDMODEX(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FRNDMODEX(reg); +} + + +/** + * Write the content of the FRNDMODEX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FRNDMODEX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FRNDMODEX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FRNDMODEX(reg, data); +} + + +/* -------------------------------------------------------- FOBYTESX field of the INSHIFTER register -------------------------------------------------------- */ + +/** Description of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_DESC "Number of output bytes to use for input feature data of stream X after rounding or saturation. Valid values are 1 or 2 bytes" + +/** Offset of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_LSB 12UL + +/** Size in bits of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_W (2UL) + +/** Mask for retrieving the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_MASK ATON_FIELD_MASK(12UL, 2UL) + +/** Reset value of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_DT 0x2UL + +/** Access rights of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_AC "RW" + +/** Check whether access to the FOBYTESX field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_S 0 + +/** Check whether access to the FOBYTESX field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FOBYTESX_P 0 + +/** Read the content of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FOBYTESX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESX_LSB, ATON_ARITH_INSHIFTER_FOBYTESX_W) + +/** Modify the content of the FOBYTESX field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FOBYTESX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESX_LSB, ATON_ARITH_INSHIFTER_FOBYTESX_W, DATA) + + +/** + * Get the description of the FOBYTESX field of INSHIFTER register. + * + * \return the description of the FOBYTESX field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FOBYTESX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FOBYTESX_DESC; +} + + +/** + * Read the content of the FOBYTESX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FOBYTESX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FOBYTESX(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FOBYTESX(reg); +} + + +/** + * Write the content of the FOBYTESX field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FOBYTESX field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FOBYTESX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FOBYTESX(reg, data); +} + + +/* -------------------------------------------------------- FBYTESY field of the INSHIFTER register --------------------------------------------------------- */ + +/** Description of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_DESC "Input data width in bytes for stream Y. Valid values are 1,2 or 3 bytes" + +/** Offset of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_LSB 16UL + +/** Size in bits of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_W (2UL) + +/** Mask for retrieving the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_MASK ATON_FIELD_MASK(16UL, 2UL) + +/** Reset value of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_DT 0x2UL + +/** Access rights of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_AC "RW" + +/** Check whether access to the FBYTESY field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_S 0 + +/** Check whether access to the FBYTESY field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FBYTESY_P 0 + +/** Read the content of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FBYTESY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESY_LSB, ATON_ARITH_INSHIFTER_FBYTESY_W) + +/** Modify the content of the FBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FBYTESY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESY_LSB, ATON_ARITH_INSHIFTER_FBYTESY_W, DATA) + + +/** + * Get the description of the FBYTESY field of INSHIFTER register. + * + * \return the description of the FBYTESY field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FBYTESY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FBYTESY_DESC; +} + + +/** + * Read the content of the FBYTESY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FBYTESY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FBYTESY(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FBYTESY(reg); +} + + +/** + * Write the content of the FBYTESY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FBYTESY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FBYTESY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FBYTESY(reg, data); +} + + +/* -------------------------------------------------------- FSHIFTY field of the INSHIFTER register --------------------------------------------------------- */ + +/** Description of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_DESC "Input feature data shift for stream Y. Range [0-40]. For no shift, set to 16" + +/** Offset of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_LSB 18UL + +/** Size in bits of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_W (6UL) + +/** Mask for retrieving the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_MASK ATON_FIELD_MASK(18UL, 6UL) + +/** Reset value of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_DT 0x10UL + +/** Access rights of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_AC "RW" + +/** Check whether access to the FSHIFTY field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_S 0 + +/** Check whether access to the FSHIFTY field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FSHIFTY_P 0 + +/** Read the content of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FSHIFTY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTY_LSB, ATON_ARITH_INSHIFTER_FSHIFTY_W) + +/** Modify the content of the FSHIFTY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FSHIFTY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTY_LSB, ATON_ARITH_INSHIFTER_FSHIFTY_W, DATA) + + +/** + * Get the description of the FSHIFTY field of INSHIFTER register. + * + * \return the description of the FSHIFTY field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FSHIFTY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FSHIFTY_DESC; +} + + +/** + * Read the content of the FSHIFTY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FSHIFTY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSHIFTY(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FSHIFTY(reg); +} + + +/** + * Write the content of the FSHIFTY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the FSHIFTY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSHIFTY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FSHIFTY(reg, data); +} + + +/* -------------------------------------------------------- FROUNDY field of the INSHIFTER register --------------------------------------------------------- */ + +/** Description of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_DESC "Input feature data rounding for stream Y" + +/** Offset of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_LSB 24UL + +/** Size in bits of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_W (1UL) + +/** Mask for retrieving the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_MASK ATON_FIELD_MASK(24UL, 1UL) + +/** Reset value of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_DT 0x0UL + +/** Access rights of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_AC "RW" + +/** Check whether access to the FROUNDY field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_S 0 + +/** Check whether access to the FROUNDY field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FROUNDY_P 0 + +/** Read the content of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FROUNDY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDY_LSB, ATON_ARITH_INSHIFTER_FROUNDY_W) + +/** Modify the content of the FROUNDY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FROUNDY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDY_LSB, ATON_ARITH_INSHIFTER_FROUNDY_W, DATA) + + +/** + * Get the description of the FROUNDY field of INSHIFTER register. + * + * \return the description of the FROUNDY field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FROUNDY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FROUNDY_DESC; +} + + +/** + * Read the content of the FROUNDY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FROUNDY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FROUNDY(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FROUNDY(reg); +} + + +/** + * Write the content of the FROUNDY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FROUNDY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FROUNDY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FROUNDY(reg, data); +} + + +/* --------------------------------------------------------- FSATY field of the INSHIFTER register ---------------------------------------------------------- */ + +/** Description of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATY_DESC "Input feature data saturation for stream Y" + +/** Offset of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATY_LSB 25UL + +/** Size in bits of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATY_W (1UL) + +/** Mask for retrieving the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATY_MASK ATON_FIELD_MASK(25UL, 1UL) + +/** Reset value of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATY_DT 0x0UL + +/** Access rights of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FSATY_AC "RW" + +/** Check whether access to the FSATY field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FSATY_S 0 + +/** Check whether access to the FSATY field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FSATY_P 0 + +/** Read the content of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FSATY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATY_LSB, ATON_ARITH_INSHIFTER_FSATY_W) + +/** Modify the content of the FSATY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FSATY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATY_LSB, ATON_ARITH_INSHIFTER_FSATY_W, DATA) + + +/** + * Get the description of the FSATY field of INSHIFTER register. + * + * \return the description of the FSATY field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FSATY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FSATY_DESC; +} + + +/** + * Read the content of the FSATY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FSATY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSATY(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FSATY(reg); +} + + +/** + * Write the content of the FSATY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSATY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSATY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FSATY(reg, data); +} + + +/* ------------------------------------------------------- FRNDMODEY field of the INSHIFTER register -------------------------------------------------------- */ + +/** Description of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_DESC "Input feature data rounding mode for stream Y. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_LSB 26UL + +/** Size in bits of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_W (2UL) + +/** Mask for retrieving the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_MASK ATON_FIELD_MASK(26UL, 2UL) + +/** Reset value of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_DT 0x0UL + +/** Access rights of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_AC "RW" + +/** Check whether access to the FRNDMODEY field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_S 0 + +/** Check whether access to the FRNDMODEY field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FRNDMODEY_P 0 + +/** Read the content of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FRNDMODEY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEY_LSB, ATON_ARITH_INSHIFTER_FRNDMODEY_W) + +/** Modify the content of the FRNDMODEY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FRNDMODEY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEY_LSB, ATON_ARITH_INSHIFTER_FRNDMODEY_W, DATA) + + +/** + * Get the description of the FRNDMODEY field of INSHIFTER register. + * + * \return the description of the FRNDMODEY field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FRNDMODEY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FRNDMODEY_DESC; +} + + +/** + * Read the content of the FRNDMODEY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FRNDMODEY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FRNDMODEY(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FRNDMODEY(reg); +} + + +/** + * Write the content of the FRNDMODEY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FRNDMODEY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FRNDMODEY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FRNDMODEY(reg, data); +} + + +/* -------------------------------------------------------- FOBYTESY field of the INSHIFTER register -------------------------------------------------------- */ + +/** Description of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_DESC "Number of output bytes to use for input feature data of stream Y after rounding or saturation. Valid values are 1 or 2 bytes" + +/** Offset of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_LSB 28UL + +/** Size in bits of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_W (2UL) + +/** Mask for retrieving the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_MASK ATON_FIELD_MASK(28UL, 2UL) + +/** Reset value of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_DT 0x2UL + +/** Access rights of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_AC "RW" + +/** Check whether access to the FOBYTESY field of the INSHIFTER register is secured or not. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_S 0 + +/** Check whether access to the FOBYTESY field of the INSHIFTER register is privileged or not. */ +#define ATON_ARITH_INSHIFTER_FOBYTESY_P 0 + +/** Read the content of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_GET_FOBYTESY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESY_LSB, ATON_ARITH_INSHIFTER_FOBYTESY_W) + +/** Modify the content of the FOBYTESY field of the INSHIFTER register. */ +#define ATON_ARITH_INSHIFTER_SET_FOBYTESY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESY_LSB, ATON_ARITH_INSHIFTER_FOBYTESY_W, DATA) + + +/** + * Get the description of the FOBYTESY field of INSHIFTER register. + * + * \return the description of the FOBYTESY field of INSHIFTER register + */ + +static inline const int8_t *ATON_ARITH_INSHIFTER_FOBYTESY_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_INSHIFTER_FOBYTESY_DESC; +} + + +/** + * Read the content of the FOBYTESY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * + * \return the content of the FOBYTESY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Get_FOBYTESY(uint32_t reg) +{ + return ATON_ARITH_INSHIFTER_GET_FOBYTESY(reg); +} + + +/** + * Write the content of the FOBYTESY field of the INSHIFTER register. + * + * \param[in] reg is the value of the INSHIFTER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FOBYTESY field belonging to INSHIFTER register + */ + +static inline uint32_t ATON_ARITH_INSHIFTER_Set_FOBYTESY(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_INSHIFTER_SET_FOBYTESY(reg, data); +} + + +/* ****************************************************** CLIPRANGE register of one of the ARITH Units ****************************************************** */ + +/** Offset of the CLIPRANGE register from the base address of the ARITH Unit. */ +#define ATON_ARITH_CLIPRANGE_OFFSET 0x38UL + +/** Reset value of the CLIPRANGE register of the ARITH Unit. */ +#define ATON_ARITH_CLIPRANGE_DT \ + (ATON_ARITH_CLIPRANGE_CLIPMAX_DT << ATON_ARITH_CLIPRANGE_CLIPMAX_LSB) | \ + (ATON_ARITH_CLIPRANGE_CLIPMIN_DT << ATON_ARITH_CLIPRANGE_CLIPMIN_LSB) + + + +/** Description of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_DESC "Output clip range [min,max]" + +/** Address of the CLIPRANGE register of one of the ARITH Units. */ +#define ATON_ARITH_CLIPRANGE_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_CLIPRANGE_OFFSET) + +/** Get the content of the CLIPRANGE register of one of the ARITH Units. */ +#define ATON_ARITH_CLIPRANGE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_CLIPRANGE_ADDR(UNIT))) + +/** Set the content of the CLIPRANGE register of one of the ARITH Units. */ +#define ATON_ARITH_CLIPRANGE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_CLIPRANGE_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CLIPRANGE register. + * + * \return the description of CLIPRANGE register + */ + +static inline const int8_t *ATON_ARITH_CLIPRANGE_GetDesc(void) +{ + return (const int8_t *)ATON_ARITH_CLIPRANGE_DESC; +} + + +/** + * Get the offset of the CLIPRANGE register. + * + * \return the offset of CLIPRANGE register + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_GetOffset(void) +{ + return ATON_ARITH_CLIPRANGE_OFFSET; +} + + +/** + * Get the address of the CLIPRANGE register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CLIPRANGE register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of CLIPRANGE register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_GetAddr(uint32_t instance) +{ + return ATON_ARITH_CLIPRANGE_ADDR(instance); +} + + +/** + * Read the content of the CLIPRANGE register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CLIPRANGE register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of CLIPRANGE register belonging to Unit having index \e instance among the ARITH Units + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_Get(uint32_t instance) +{ + return ATON_ARITH_CLIPRANGE_GET(instance); +} + + +/** + * Write the content of the CLIPRANGE register. + * + * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CLIPRANGE register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_ARITH_CLIPRANGE_Set(uint32_t instance, uint32_t data) +{ + ATON_ARITH_CLIPRANGE_SET(instance, data); +} + + +/* -------------------------------------------------------- CLIPMAX field of the CLIPRANGE register --------------------------------------------------------- */ + +/** Description of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_DESC "signed 16b value specifying output clip max" + +/** Offset of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_LSB 0UL + +/** Size in bits of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_W (16UL) + +/** Mask for retrieving the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_DT 0x0UL + +/** Access rights of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_AC "RW" + +/** Check whether access to the CLIPMAX field of the CLIPRANGE register is secured or not. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_S 0 + +/** Check whether access to the CLIPMAX field of the CLIPRANGE register is privileged or not. */ +#define ATON_ARITH_CLIPRANGE_CLIPMAX_P 0 + +/** Read the content of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_GET_CLIPMAX(REG) ATON_GET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMAX_LSB, ATON_ARITH_CLIPRANGE_CLIPMAX_W) + +/** Modify the content of the CLIPMAX field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_SET_CLIPMAX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMAX_LSB, ATON_ARITH_CLIPRANGE_CLIPMAX_W, DATA) + + +/** + * Get the description of the CLIPMAX field of CLIPRANGE register. + * + * \return the description of the CLIPMAX field of CLIPRANGE register + */ + +static inline const int8_t *ATON_ARITH_CLIPRANGE_CLIPMAX_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CLIPRANGE_CLIPMAX_DESC; +} + + +/** + * Read the content of the CLIPMAX field of the CLIPRANGE register. + * + * \param[in] reg is the value of the CLIPRANGE register + * + * \return the content of the CLIPMAX field belonging to CLIPRANGE register + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_Get_CLIPMAX(uint32_t reg) +{ + return ATON_ARITH_CLIPRANGE_GET_CLIPMAX(reg); +} + + +/** + * Write the content of the CLIPMAX field of the CLIPRANGE register. + * + * \param[in] reg is the value of the CLIPRANGE register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the CLIPMAX field belonging to CLIPRANGE register + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_Set_CLIPMAX(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CLIPRANGE_SET_CLIPMAX(reg, data); +} + + +/* -------------------------------------------------------- CLIPMIN field of the CLIPRANGE register --------------------------------------------------------- */ + +/** Description of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_DESC "signed 16b value specifying output clip min" + +/** Offset of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_LSB 16UL + +/** Size in bits of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_W (16UL) + +/** Mask for retrieving the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_DT 0x0UL + +/** Access rights of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_AC "RW" + +/** Check whether access to the CLIPMIN field of the CLIPRANGE register is secured or not. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_S 0 + +/** Check whether access to the CLIPMIN field of the CLIPRANGE register is privileged or not. */ +#define ATON_ARITH_CLIPRANGE_CLIPMIN_P 0 + +/** Read the content of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_GET_CLIPMIN(REG) ATON_GET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMIN_LSB, ATON_ARITH_CLIPRANGE_CLIPMIN_W) + +/** Modify the content of the CLIPMIN field of the CLIPRANGE register. */ +#define ATON_ARITH_CLIPRANGE_SET_CLIPMIN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMIN_LSB, ATON_ARITH_CLIPRANGE_CLIPMIN_W, DATA) + + +/** + * Get the description of the CLIPMIN field of CLIPRANGE register. + * + * \return the description of the CLIPMIN field of CLIPRANGE register + */ + +static inline const int8_t *ATON_ARITH_CLIPRANGE_CLIPMIN_GetdDesc(void) +{ + return (const int8_t *)ATON_ARITH_CLIPRANGE_CLIPMIN_DESC; +} + + +/** + * Read the content of the CLIPMIN field of the CLIPRANGE register. + * + * \param[in] reg is the value of the CLIPRANGE register + * + * \return the content of the CLIPMIN field belonging to CLIPRANGE register + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_Get_CLIPMIN(uint32_t reg) +{ + return ATON_ARITH_CLIPRANGE_GET_CLIPMIN(reg); +} + + +/** + * Write the content of the CLIPMIN field of the CLIPRANGE register. + * + * \param[in] reg is the value of the CLIPRANGE register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the CLIPMIN field belonging to CLIPRANGE register + */ + +static inline uint32_t ATON_ARITH_CLIPRANGE_Set_CLIPMIN(uint32_t reg, uint32_t data) +{ + return ATON_ARITH_CLIPRANGE_SET_CLIPMIN(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* POOL Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of POOL Unit instances. */ +#define ATON_POOL_NUM 2 + +/** + * \name Structures, macros and functions of the POOL Units + */ +/*@{*/ + +/** + * Registers of the POOL Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e PDIMS register (Pool dimensions). */ + uint32_t PDIMS; + + /** \e FDIMS register (Feature dimensions). */ + uint32_t FDIMS; + + /** \e OUTDIMS register (Output feature dimensions). */ + uint32_t OUTDIMS; + + /** \e MULVAL register (average pooling data). */ + uint32_t MULVAL; + + /** \e XCROP register (left/right cropping dimensions). */ + uint32_t XCROP; + + /** \e YCROP register (top/bottom cropping dimensions). */ + uint32_t YCROP; + + /** \e RNDCTRL register (input and output rounding control). */ + uint32_t RNDCTRL; + +} ATON_POOL_t; + + +/** Return the pointer to one of the POOL Units. */ +#define ATON_POOL(UNIT) ((ATON_POOL_t *)(intptr_t)ATON_POOL_BASE(UNIT)) + + +/** Name of one of the POOL Units. */ +#define ATON_POOL_NAME(UNIT) \ + (((UNIT) == 0) ? "POOL0" : \ + (((UNIT) == 1) ? "POOL1" : "")) + + +/** Version of the POOL Units. */ +#define ATON_POOL_VERSION "1.1" + + +/** Description of one of the POOL Units. */ +#define ATON_POOL_DESC(UNIT) \ + (((UNIT) == 0) ? "Pooling Accelerator 0" : \ + (((UNIT) == 1) ? "Pooling Accelerator 1" : "")) + + +/** Base address of one of the POOL Units. */ +#define ATON_POOL_BASE(UNIT) \ + (ATON_BASE + 0x1b000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the POOL Units. */ +#define ATON_POOL_SIZE 0x1000UL + + +/** + * Get the name of one of the POOL Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) + * + * \return the name of Unit having index \e instance among the POOL Units + */ + +static inline const int8_t *ATON_POOL_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"POOL0"; + break; + + case 1: + str = (const int8_t *)"POOL1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the POOL Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) + * + * \return the description of Unit having index \e instance among the POOL Units + */ + +static inline const int8_t *ATON_POOL_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Pooling Accelerator 0"; + break; + + case 1: + str = (const int8_t *)"Pooling Accelerator 1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the POOL Units. + * + * \return the version of the POOL Units + */ + +static inline const int8_t *ATON_POOL_GetVersion(void) +{ + return (const int8_t *)ATON_POOL_VERSION; +} + + +/** + * Get the base address of one of the POOL Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) + * + * \return the base address of Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_GetBase(uint32_t instance) +{ + return ATON_POOL_BASE(instance); +} + + +/** + * Get the size in bytes of the POOL Units. + * + * \return the size in bytes of the POOL Units + */ + +static inline uint32_t ATON_POOL_GetSize(void) +{ + return ATON_POOL_SIZE; +} + + +/* ********************************************************* CTRL register of one of the POOL Units ********************************************************* */ + +/** Offset of the CTRL register from the base address of the POOL Unit. */ +#define ATON_POOL_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the POOL Unit. */ +#define ATON_POOL_CTRL_DT \ + (ATON_POOL_CTRL_EN_DT << ATON_POOL_CTRL_EN_LSB) | \ + (ATON_POOL_CTRL_CLR_DT << ATON_POOL_CTRL_CLR_LSB) | \ + (ATON_POOL_CTRL_TYPE_DT << ATON_POOL_CTRL_TYPE_LSB) | \ + (ATON_POOL_CTRL_ROUND_DT << ATON_POOL_CTRL_ROUND_LSB) | \ + (ATON_POOL_CTRL_SAT_DT << ATON_POOL_CTRL_SAT_LSB) | \ + (ATON_POOL_CTRL_OUTSHIFT_DT << ATON_POOL_CTRL_OUTSHIFT_LSB) | \ + (ATON_POOL_CTRL_DUALLINE_DT << ATON_POOL_CTRL_DUALLINE_LSB) | \ + (ATON_POOL_CTRL_CROPEN_DT << ATON_POOL_CTRL_CROPEN_LSB) | \ + (ATON_POOL_CTRL_FBYTES_DT << ATON_POOL_CTRL_FBYTES_LSB) | \ + (ATON_POOL_CTRL_FSHIFT_DT << ATON_POOL_CTRL_FSHIFT_LSB) | \ + (ATON_POOL_CTRL_FROUND_DT << ATON_POOL_CTRL_FROUND_LSB) | \ + (ATON_POOL_CTRL_FSAT_DT << ATON_POOL_CTRL_FSAT_LSB) | \ + (ATON_POOL_CTRL_CONFCLR_DT << ATON_POOL_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_POOL_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the POOL Units. */ +#define ATON_POOL_CTRL_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the POOL Units. */ +#define ATON_POOL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the POOL Units. */ +#define ATON_POOL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_GetOffset(void) +{ + return ATON_POOL_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the CTRL register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_CTRL_GetAddr(uint32_t instance) +{ + return ATON_POOL_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_CTRL_Get(uint32_t instance) +{ + return ATON_POOL_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the CTRL register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_EN_DESC "Enable the Pooling Accelerator" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_EN_LSB, ATON_POOL_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_EN_LSB, ATON_POOL_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_EN(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_CLR_LSB, ATON_POOL_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_CLR_LSB, ATON_POOL_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_CLR(reg, data); +} + + +/* ------------------------------------------------------------ TYPE field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_TYPE_DESC "Pool operation type" + +/** Offset of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_TYPE_LSB 2UL + +/** Size in bits of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_TYPE_W (4UL) + +/** Mask for retrieving the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_TYPE_MASK ATON_FIELD_MASK(2UL, 4UL) + +/** Reset value of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_TYPE_DT 0x0UL + +/** Access rights of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_TYPE_AC "RW" + +/** Check whether access to the TYPE field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_TYPE_S 0 + +/** Check whether access to the TYPE field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_TYPE_P 0 + +/** Read the content of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_TYPE_LSB, ATON_POOL_CTRL_TYPE_W) + +/** Modify the content of the TYPE field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_TYPE_LSB, ATON_POOL_CTRL_TYPE_W, DATA) + + +/** + * Get the description of the TYPE field of CTRL register. + * + * \return the description of the TYPE field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the TYPE field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_TYPE(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_TYPE(reg); +} + + +/** + * Write the content of the TYPE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the TYPE field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_TYPE(reg, data); +} + + +/* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_ROUND_DESC "Enable output rounding using round-to-nearest (round up) (applicable to average pooling operations)" + +/** Offset of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_ROUND_LSB 6UL + +/** Size in bits of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_ROUND_W (1UL) + +/** Mask for retrieving the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_ROUND_MASK ATON_FIELD_MASK(6UL, 1UL) + +/** Reset value of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_ROUND_DT 0x0UL + +/** Access rights of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_ROUND_AC "RW" + +/** Check whether access to the ROUND field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_ROUND_S 0 + +/** Check whether access to the ROUND field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_ROUND_P 0 + +/** Read the content of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_ROUND_LSB, ATON_POOL_CTRL_ROUND_W) + +/** Modify the content of the ROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_ROUND_LSB, ATON_POOL_CTRL_ROUND_W, DATA) + + +/** + * Get the description of the ROUND field of CTRL register. + * + * \return the description of the ROUND field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_ROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_ROUND_DESC; +} + + +/** + * Read the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_ROUND(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_ROUND(reg); +} + + +/** + * Write the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_ROUND(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_ROUND(reg, data); +} + + +/* ------------------------------------------------------------- SAT field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SAT_DESC "Enable output saturation (applicable to average pooling operations)" + +/** Offset of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SAT_LSB 7UL + +/** Size in bits of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SAT_W (1UL) + +/** Mask for retrieving the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SAT_MASK ATON_FIELD_MASK(7UL, 1UL) + +/** Reset value of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SAT_DT 0x0UL + +/** Access rights of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SAT_AC "RW" + +/** Check whether access to the SAT field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_SAT_S 0 + +/** Check whether access to the SAT field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_SAT_P 0 + +/** Read the content of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_SAT_LSB, ATON_POOL_CTRL_SAT_W) + +/** Modify the content of the SAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_SAT_LSB, ATON_POOL_CTRL_SAT_W, DATA) + + +/** + * Get the description of the SAT field of CTRL register. + * + * \return the description of the SAT field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_SAT_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_SAT_DESC; +} + + +/** + * Read the content of the SAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SAT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_SAT(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_SAT(reg); +} + + +/** + * Write the content of the SAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SAT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_SAT(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_SAT(reg, data); +} + + +/* ---------------------------------------------------------- OUTSHIFT field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_OUTSHIFT_DESC "Optional right shift to apply the average pooling output" + +/** Offset of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_OUTSHIFT_LSB 8UL + +/** Size in bits of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_OUTSHIFT_W (6UL) + +/** Mask for retrieving the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_OUTSHIFT_MASK ATON_FIELD_MASK(8UL, 6UL) + +/** Reset value of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_OUTSHIFT_DT 0x0UL + +/** Access rights of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_OUTSHIFT_AC "RW" + +/** Check whether access to the OUTSHIFT field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_OUTSHIFT_S 0 + +/** Check whether access to the OUTSHIFT field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_OUTSHIFT_P 0 + +/** Read the content of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_OUTSHIFT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_OUTSHIFT_LSB, ATON_POOL_CTRL_OUTSHIFT_W) + +/** Modify the content of the OUTSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_OUTSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_OUTSHIFT_LSB, ATON_POOL_CTRL_OUTSHIFT_W, DATA) + + +/** + * Get the description of the OUTSHIFT field of CTRL register. + * + * \return the description of the OUTSHIFT field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_OUTSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_OUTSHIFT_DESC; +} + + +/** + * Read the content of the OUTSHIFT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the OUTSHIFT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_OUTSHIFT(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_OUTSHIFT(reg); +} + + +/** + * Write the content of the OUTSHIFT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the OUTSHIFT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_OUTSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_OUTSHIFT(reg, data); +} + + +/* ---------------------------------------------------------- DUALLINE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_DUALLINE_DESC "Enable dual line, allows each linebuffer line to work as 2 lines, applicable for 8-bit data" + +/** Offset of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_DUALLINE_LSB 14UL + +/** Size in bits of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_DUALLINE_W (1UL) + +/** Mask for retrieving the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_DUALLINE_MASK ATON_FIELD_MASK(14UL, 1UL) + +/** Reset value of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_DUALLINE_DT 0x0UL + +/** Access rights of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_DUALLINE_AC "RW" + +/** Check whether access to the DUALLINE field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_DUALLINE_S 0 + +/** Check whether access to the DUALLINE field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_DUALLINE_P 0 + +/** Read the content of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_DUALLINE(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_DUALLINE_LSB, ATON_POOL_CTRL_DUALLINE_W) + +/** Modify the content of the DUALLINE field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_DUALLINE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_DUALLINE_LSB, ATON_POOL_CTRL_DUALLINE_W, DATA) + + +/** + * Get the description of the DUALLINE field of CTRL register. + * + * \return the description of the DUALLINE field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_DUALLINE_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_DUALLINE_DESC; +} + + +/** + * Read the content of the DUALLINE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DUALLINE field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_DUALLINE(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_DUALLINE(reg); +} + + +/** + * Write the content of the DUALLINE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DUALLINE field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_DUALLINE(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_DUALLINE(reg, data); +} + + +/* ----------------------------------------------------------- CROPEN field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_CROPEN_DESC "Enable input feature cropping" + +/** Offset of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_CROPEN_LSB 15UL + +/** Size in bits of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_CROPEN_W (1UL) + +/** Mask for retrieving the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_CROPEN_MASK ATON_FIELD_MASK(15UL, 1UL) + +/** Reset value of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_CROPEN_DT 0x0UL + +/** Access rights of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_CROPEN_AC "RW" + +/** Check whether access to the CROPEN field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_CROPEN_S 0 + +/** Check whether access to the CROPEN field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_CROPEN_P 0 + +/** Read the content of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_CROPEN(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_CROPEN_LSB, ATON_POOL_CTRL_CROPEN_W) + +/** Modify the content of the CROPEN field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_CROPEN(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_CROPEN_LSB, ATON_POOL_CTRL_CROPEN_W, DATA) + + +/** + * Get the description of the CROPEN field of CTRL register. + * + * \return the description of the CROPEN field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_CROPEN_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_CROPEN_DESC; +} + + +/** + * Read the content of the CROPEN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CROPEN field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_CROPEN(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_CROPEN(reg); +} + + +/** + * Write the content of the CROPEN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CROPEN field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_CROPEN(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_CROPEN(reg, data); +} + + +/* ----------------------------------------------------------- FBYTES field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_FBYTES_DESC "Input data width in bytes. Valid values are 1,2 or 3 bytes" + +/** Offset of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_FBYTES_LSB 16UL + +/** Size in bits of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_FBYTES_W (2UL) + +/** Mask for retrieving the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_FBYTES_MASK ATON_FIELD_MASK(16UL, 2UL) + +/** Reset value of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_FBYTES_DT 0x2UL + +/** Access rights of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_FBYTES_AC "RW" + +/** Check whether access to the FBYTES field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_FBYTES_S 0 + +/** Check whether access to the FBYTES field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_FBYTES_P 0 + +/** Read the content of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_FBYTES(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FBYTES_LSB, ATON_POOL_CTRL_FBYTES_W) + +/** Modify the content of the FBYTES field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_FBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FBYTES_LSB, ATON_POOL_CTRL_FBYTES_W, DATA) + + +/** + * Get the description of the FBYTES field of CTRL register. + * + * \return the description of the FBYTES field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_FBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_FBYTES_DESC; +} + + +/** + * Read the content of the FBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_FBYTES(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_FBYTES(reg); +} + + +/** + * Write the content of the FBYTES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FBYTES field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_FBYTES(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_FBYTES(reg, data); +} + + +/* ----------------------------------------------------------- FSHIFT field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSHIFT_DESC "Input feature data shift. Range [0,40]. For no shift, set to 16" + +/** Offset of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSHIFT_LSB 18UL + +/** Size in bits of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSHIFT_W (6UL) + +/** Mask for retrieving the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSHIFT_MASK ATON_FIELD_MASK(18UL, 6UL) + +/** Reset value of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSHIFT_DT 0x10UL + +/** Access rights of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSHIFT_AC "RW" + +/** Check whether access to the FSHIFT field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_FSHIFT_S 0 + +/** Check whether access to the FSHIFT field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_FSHIFT_P 0 + +/** Read the content of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_FSHIFT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FSHIFT_LSB, ATON_POOL_CTRL_FSHIFT_W) + +/** Modify the content of the FSHIFT field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_FSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FSHIFT_LSB, ATON_POOL_CTRL_FSHIFT_W, DATA) + + +/** + * Get the description of the FSHIFT field of CTRL register. + * + * \return the description of the FSHIFT field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_FSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_FSHIFT_DESC; +} + + +/** + * Read the content of the FSHIFT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSHIFT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_FSHIFT(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_FSHIFT(reg); +} + + +/** + * Write the content of the FSHIFT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the FSHIFT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_FSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_FSHIFT(reg, data); +} + + +/* ----------------------------------------------------------- FROUND field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_FROUND_DESC "Input feature data rounding" + +/** Offset of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_FROUND_LSB 24UL + +/** Size in bits of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_FROUND_W (1UL) + +/** Mask for retrieving the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_FROUND_MASK ATON_FIELD_MASK(24UL, 1UL) + +/** Reset value of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_FROUND_DT 0x0UL + +/** Access rights of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_FROUND_AC "RW" + +/** Check whether access to the FROUND field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_FROUND_S 0 + +/** Check whether access to the FROUND field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_FROUND_P 0 + +/** Read the content of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_FROUND(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FROUND_LSB, ATON_POOL_CTRL_FROUND_W) + +/** Modify the content of the FROUND field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_FROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FROUND_LSB, ATON_POOL_CTRL_FROUND_W, DATA) + + +/** + * Get the description of the FROUND field of CTRL register. + * + * \return the description of the FROUND field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_FROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_FROUND_DESC; +} + + +/** + * Read the content of the FROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_FROUND(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_FROUND(reg); +} + + +/** + * Write the content of the FROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_FROUND(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_FROUND(reg, data); +} + + +/* ------------------------------------------------------------ FSAT field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSAT_DESC "Input feature data saturation" + +/** Offset of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSAT_LSB 25UL + +/** Size in bits of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSAT_W (1UL) + +/** Mask for retrieving the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSAT_MASK ATON_FIELD_MASK(25UL, 1UL) + +/** Reset value of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSAT_DT 0x0UL + +/** Access rights of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_FSAT_AC "RW" + +/** Check whether access to the FSAT field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_FSAT_S 0 + +/** Check whether access to the FSAT field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_FSAT_P 0 + +/** Read the content of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_FSAT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FSAT_LSB, ATON_POOL_CTRL_FSAT_W) + +/** Modify the content of the FSAT field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_FSAT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FSAT_LSB, ATON_POOL_CTRL_FSAT_W, DATA) + + +/** + * Get the description of the FSAT field of CTRL register. + * + * \return the description of the FSAT field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_FSAT_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_FSAT_DESC; +} + + +/** + * Read the content of the FSAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSAT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_FSAT(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_FSAT(reg); +} + + +/** + * Write the content of the FSAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSAT field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_FSAT(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_FSAT(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CONFCLR_DESC "Clear configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_POOL_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_POOL_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_CONFCLR_LSB, ATON_POOL_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_POOL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_CONFCLR_LSB, ATON_POOL_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_POOL_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_POOL_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_POOL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_POOL_CTRL_SET_CONFCLR(reg, data); +} + + +/* ******************************************************* VERSION register of one of the POOL Units ******************************************************** */ + +/** Offset of the VERSION register from the base address of the POOL Unit. */ +#define ATON_POOL_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the POOL Unit. */ +#define ATON_POOL_VERSION_DT \ + (ATON_POOL_VERSION_TYPE_DT << ATON_POOL_VERSION_TYPE_LSB) | \ + (ATON_POOL_VERSION_MINOR_DT << ATON_POOL_VERSION_MINOR_LSB) | \ + (ATON_POOL_VERSION_MAJOR_DT << ATON_POOL_VERSION_MAJOR_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_POOL_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the POOL Units. */ +#define ATON_POOL_VERSION_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the POOL Units. */ +#define ATON_POOL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_POOL_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_POOL_VERSION_GetOffset(void) +{ + return ATON_POOL_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the VERSION register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_VERSION_GetAddr(uint32_t instance) +{ + return ATON_POOL_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_VERSION_Get(uint32_t instance) +{ + return ATON_POOL_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_TYPE_DT 0x1cUL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_POOL_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_POOL_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_POOL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_POOL_VERSION_TYPE_LSB, ATON_POOL_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_POOL_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_POOL_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_POOL_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MINOR_DT 0x1UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_POOL_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_POOL_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_POOL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_POOL_VERSION_MINOR_LSB, ATON_POOL_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_POOL_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_POOL_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_POOL_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_POOL_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_POOL_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_POOL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_POOL_VERSION_MAJOR_LSB, ATON_POOL_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_POOL_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_POOL_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_POOL_VERSION_GET_MAJOR(reg); +} + + +/* ******************************************************** PDIMS register of one of the POOL Units ********************************************************* */ + +/** Offset of the PDIMS register from the base address of the POOL Unit. */ +#define ATON_POOL_PDIMS_OFFSET 0x8UL + +/** Reset value of the PDIMS register of the POOL Unit. */ +#define ATON_POOL_PDIMS_DT \ + (ATON_POOL_PDIMS_WINX_DT << ATON_POOL_PDIMS_WINX_LSB) | \ + (ATON_POOL_PDIMS_WINY_DT << ATON_POOL_PDIMS_WINY_LSB) | \ + (ATON_POOL_PDIMS_STRDX_DT << ATON_POOL_PDIMS_STRDX_LSB) | \ + (ATON_POOL_PDIMS_STRDY_DT << ATON_POOL_PDIMS_STRDY_LSB) | \ + (ATON_POOL_PDIMS_TPAD_DT << ATON_POOL_PDIMS_TPAD_LSB) | \ + (ATON_POOL_PDIMS_BPAD_DT << ATON_POOL_PDIMS_BPAD_LSB) | \ + (ATON_POOL_PDIMS_LPAD_DT << ATON_POOL_PDIMS_LPAD_LSB) | \ + (ATON_POOL_PDIMS_RPAD_DT << ATON_POOL_PDIMS_RPAD_LSB) | \ + (ATON_POOL_PDIMS_BSIZE_DT << ATON_POOL_PDIMS_BSIZE_LSB) + + + +/** Description of the PDIMS register. */ +#define ATON_POOL_PDIMS_DESC "Pool dimensions" + +/** Address of the PDIMS register of one of the POOL Units. */ +#define ATON_POOL_PDIMS_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_PDIMS_OFFSET) + +/** Get the content of the PDIMS register of one of the POOL Units. */ +#define ATON_POOL_PDIMS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_PDIMS_ADDR(UNIT))) + +/** Set the content of the PDIMS register of one of the POOL Units. */ +#define ATON_POOL_PDIMS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_PDIMS_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of PDIMS register. + * + * \return the description of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_DESC; +} + + +/** + * Get the offset of the PDIMS register. + * + * \return the offset of PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_GetOffset(void) +{ + return ATON_POOL_PDIMS_OFFSET; +} + + +/** + * Get the address of the PDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the PDIMS register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of PDIMS register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_PDIMS_GetAddr(uint32_t instance) +{ + return ATON_POOL_PDIMS_ADDR(instance); +} + + +/** + * Read the content of the PDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the PDIMS register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of PDIMS register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_PDIMS_Get(uint32_t instance) +{ + return ATON_POOL_PDIMS_GET(instance); +} + + +/** + * Write the content of the PDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the PDIMS register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_PDIMS_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_PDIMS_SET(instance, data); +} + + +/* ------------------------------------------------------------ WINX field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINX_DESC "Pool window width" + +/** Offset of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINX_LSB 0UL + +/** Size in bits of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINX_W (3UL) + +/** Mask for retrieving the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINX_MASK ATON_FIELD_MASK(0UL, 3UL) + +/** Reset value of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINX_DT 0x0UL + +/** Access rights of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINX_AC "RW" + +/** Check whether access to the WINX field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_WINX_S 0 + +/** Check whether access to the WINX field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_WINX_P 0 + +/** Read the content of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_WINX(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_WINX_LSB, ATON_POOL_PDIMS_WINX_W) + +/** Modify the content of the WINX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_WINX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_WINX_LSB, ATON_POOL_PDIMS_WINX_W, DATA) + + +/** + * Get the description of the WINX field of PDIMS register. + * + * \return the description of the WINX field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_WINX_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_WINX_DESC; +} + + +/** + * Read the content of the WINX field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the WINX field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_WINX(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_WINX(reg); +} + + +/** + * Write the content of the WINX field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the WINX field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_WINX(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_WINX(reg, data); +} + + +/* ------------------------------------------------------------ WINY field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINY_DESC "Pool window height" + +/** Offset of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINY_LSB 3UL + +/** Size in bits of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINY_W (3UL) + +/** Mask for retrieving the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINY_MASK ATON_FIELD_MASK(3UL, 3UL) + +/** Reset value of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINY_DT 0x0UL + +/** Access rights of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_WINY_AC "RW" + +/** Check whether access to the WINY field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_WINY_S 0 + +/** Check whether access to the WINY field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_WINY_P 0 + +/** Read the content of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_WINY(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_WINY_LSB, ATON_POOL_PDIMS_WINY_W) + +/** Modify the content of the WINY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_WINY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_WINY_LSB, ATON_POOL_PDIMS_WINY_W, DATA) + + +/** + * Get the description of the WINY field of PDIMS register. + * + * \return the description of the WINY field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_WINY_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_WINY_DESC; +} + + +/** + * Read the content of the WINY field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the WINY field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_WINY(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_WINY(reg); +} + + +/** + * Write the content of the WINY field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the WINY field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_WINY(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_WINY(reg, data); +} + + +/* ----------------------------------------------------------- STRDX field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDX_DESC "Window stride in X direction along width" + +/** Offset of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDX_LSB 6UL + +/** Size in bits of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDX_W (4UL) + +/** Mask for retrieving the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDX_MASK ATON_FIELD_MASK(6UL, 4UL) + +/** Reset value of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDX_DT 0x0UL + +/** Access rights of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDX_AC "RW" + +/** Check whether access to the STRDX field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_STRDX_S 0 + +/** Check whether access to the STRDX field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_STRDX_P 0 + +/** Read the content of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_STRDX(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_STRDX_LSB, ATON_POOL_PDIMS_STRDX_W) + +/** Modify the content of the STRDX field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_STRDX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_STRDX_LSB, ATON_POOL_PDIMS_STRDX_W, DATA) + + +/** + * Get the description of the STRDX field of PDIMS register. + * + * \return the description of the STRDX field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_STRDX_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_STRDX_DESC; +} + + +/** + * Read the content of the STRDX field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the STRDX field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_STRDX(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_STRDX(reg); +} + + +/** + * Write the content of the STRDX field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STRDX field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_STRDX(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_STRDX(reg, data); +} + + +/* ----------------------------------------------------------- STRDY field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDY_DESC "Window stride in Y direction along height" + +/** Offset of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDY_LSB 10UL + +/** Size in bits of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDY_W (4UL) + +/** Mask for retrieving the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDY_MASK ATON_FIELD_MASK(10UL, 4UL) + +/** Reset value of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDY_DT 0x0UL + +/** Access rights of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_STRDY_AC "RW" + +/** Check whether access to the STRDY field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_STRDY_S 0 + +/** Check whether access to the STRDY field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_STRDY_P 0 + +/** Read the content of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_STRDY(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_STRDY_LSB, ATON_POOL_PDIMS_STRDY_W) + +/** Modify the content of the STRDY field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_STRDY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_STRDY_LSB, ATON_POOL_PDIMS_STRDY_W, DATA) + + +/** + * Get the description of the STRDY field of PDIMS register. + * + * \return the description of the STRDY field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_STRDY_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_STRDY_DESC; +} + + +/** + * Read the content of the STRDY field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the STRDY field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_STRDY(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_STRDY(reg); +} + + +/** + * Write the content of the STRDY field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STRDY field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_STRDY(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_STRDY(reg, data); +} + + +/* ------------------------------------------------------------ TPAD field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_TPAD_DESC "Padding applied to top" + +/** Offset of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_TPAD_LSB 14UL + +/** Size in bits of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_TPAD_W (3UL) + +/** Mask for retrieving the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_TPAD_MASK ATON_FIELD_MASK(14UL, 3UL) + +/** Reset value of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_TPAD_DT 0x0UL + +/** Access rights of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_TPAD_AC "RW" + +/** Check whether access to the TPAD field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_TPAD_S 0 + +/** Check whether access to the TPAD field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_TPAD_P 0 + +/** Read the content of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_TPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_TPAD_LSB, ATON_POOL_PDIMS_TPAD_W) + +/** Modify the content of the TPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_TPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_TPAD_LSB, ATON_POOL_PDIMS_TPAD_W, DATA) + + +/** + * Get the description of the TPAD field of PDIMS register. + * + * \return the description of the TPAD field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_TPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_TPAD_DESC; +} + + +/** + * Read the content of the TPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the TPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_TPAD(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_TPAD(reg); +} + + +/** + * Write the content of the TPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the TPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_TPAD(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_TPAD(reg, data); +} + + +/* ------------------------------------------------------------ BPAD field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BPAD_DESC "Padding applied to bottom" + +/** Offset of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BPAD_LSB 17UL + +/** Size in bits of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BPAD_W (3UL) + +/** Mask for retrieving the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BPAD_MASK ATON_FIELD_MASK(17UL, 3UL) + +/** Reset value of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BPAD_DT 0x0UL + +/** Access rights of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BPAD_AC "RW" + +/** Check whether access to the BPAD field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_BPAD_S 0 + +/** Check whether access to the BPAD field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_BPAD_P 0 + +/** Read the content of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_BPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_BPAD_LSB, ATON_POOL_PDIMS_BPAD_W) + +/** Modify the content of the BPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_BPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_BPAD_LSB, ATON_POOL_PDIMS_BPAD_W, DATA) + + +/** + * Get the description of the BPAD field of PDIMS register. + * + * \return the description of the BPAD field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_BPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_BPAD_DESC; +} + + +/** + * Read the content of the BPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the BPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_BPAD(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_BPAD(reg); +} + + +/** + * Write the content of the BPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the BPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_BPAD(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_BPAD(reg, data); +} + + +/* ------------------------------------------------------------ LPAD field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_LPAD_DESC "Padding applied to left" + +/** Offset of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_LPAD_LSB 20UL + +/** Size in bits of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_LPAD_W (3UL) + +/** Mask for retrieving the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_LPAD_MASK ATON_FIELD_MASK(20UL, 3UL) + +/** Reset value of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_LPAD_DT 0x0UL + +/** Access rights of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_LPAD_AC "RW" + +/** Check whether access to the LPAD field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_LPAD_S 0 + +/** Check whether access to the LPAD field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_LPAD_P 0 + +/** Read the content of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_LPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_LPAD_LSB, ATON_POOL_PDIMS_LPAD_W) + +/** Modify the content of the LPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_LPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_LPAD_LSB, ATON_POOL_PDIMS_LPAD_W, DATA) + + +/** + * Get the description of the LPAD field of PDIMS register. + * + * \return the description of the LPAD field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_LPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_LPAD_DESC; +} + + +/** + * Read the content of the LPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the LPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_LPAD(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_LPAD(reg); +} + + +/** + * Write the content of the LPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the LPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_LPAD(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_LPAD(reg, data); +} + + +/* ------------------------------------------------------------ RPAD field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_RPAD_DESC "Padding applied to right" + +/** Offset of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_RPAD_LSB 23UL + +/** Size in bits of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_RPAD_W (3UL) + +/** Mask for retrieving the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_RPAD_MASK ATON_FIELD_MASK(23UL, 3UL) + +/** Reset value of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_RPAD_DT 0x0UL + +/** Access rights of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_RPAD_AC "RW" + +/** Check whether access to the RPAD field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_RPAD_S 0 + +/** Check whether access to the RPAD field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_RPAD_P 0 + +/** Read the content of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_RPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_RPAD_LSB, ATON_POOL_PDIMS_RPAD_W) + +/** Modify the content of the RPAD field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_RPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_RPAD_LSB, ATON_POOL_PDIMS_RPAD_W, DATA) + + +/** + * Get the description of the RPAD field of PDIMS register. + * + * \return the description of the RPAD field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_RPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_RPAD_DESC; +} + + +/** + * Read the content of the RPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the RPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_RPAD(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_RPAD(reg); +} + + +/** + * Write the content of the RPAD field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the RPAD field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_RPAD(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_RPAD(reg, data); +} + + +/* ----------------------------------------------------------- BSIZE field of the PDIMS register ------------------------------------------------------------ */ + +/** Description of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BSIZE_DESC "Batch size" + +/** Offset of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BSIZE_LSB 26UL + +/** Size in bits of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BSIZE_W (4UL) + +/** Mask for retrieving the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BSIZE_MASK ATON_FIELD_MASK(26UL, 4UL) + +/** Reset value of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BSIZE_DT 0x0UL + +/** Access rights of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_BSIZE_AC "RW" + +/** Check whether access to the BSIZE field of the PDIMS register is secured or not. */ +#define ATON_POOL_PDIMS_BSIZE_S 0 + +/** Check whether access to the BSIZE field of the PDIMS register is privileged or not. */ +#define ATON_POOL_PDIMS_BSIZE_P 0 + +/** Read the content of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_GET_BSIZE(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_BSIZE_LSB, ATON_POOL_PDIMS_BSIZE_W) + +/** Modify the content of the BSIZE field of the PDIMS register. */ +#define ATON_POOL_PDIMS_SET_BSIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_BSIZE_LSB, ATON_POOL_PDIMS_BSIZE_W, DATA) + + +/** + * Get the description of the BSIZE field of PDIMS register. + * + * \return the description of the BSIZE field of PDIMS register + */ + +static inline const int8_t *ATON_POOL_PDIMS_BSIZE_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_PDIMS_BSIZE_DESC; +} + + +/** + * Read the content of the BSIZE field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * + * \return the content of the BSIZE field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Get_BSIZE(uint32_t reg) +{ + return ATON_POOL_PDIMS_GET_BSIZE(reg); +} + + +/** + * Write the content of the BSIZE field of the PDIMS register. + * + * \param[in] reg is the value of the PDIMS register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the BSIZE field belonging to PDIMS register + */ + +static inline uint32_t ATON_POOL_PDIMS_Set_BSIZE(uint32_t reg, uint32_t data) +{ + return ATON_POOL_PDIMS_SET_BSIZE(reg, data); +} + + +/* ******************************************************** FDIMS register of one of the POOL Units ********************************************************* */ + +/** Offset of the FDIMS register from the base address of the POOL Unit. */ +#define ATON_POOL_FDIMS_OFFSET 0xcUL + +/** Reset value of the FDIMS register of the POOL Unit. */ +#define ATON_POOL_FDIMS_DT \ + (ATON_POOL_FDIMS_FEATX_DT << ATON_POOL_FDIMS_FEATX_LSB) | \ + (ATON_POOL_FDIMS_FEATY_DT << ATON_POOL_FDIMS_FEATY_LSB) + + + +/** Description of the FDIMS register. */ +#define ATON_POOL_FDIMS_DESC "Feature dimensions" + +/** Address of the FDIMS register of one of the POOL Units. */ +#define ATON_POOL_FDIMS_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_FDIMS_OFFSET) + +/** Get the content of the FDIMS register of one of the POOL Units. */ +#define ATON_POOL_FDIMS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_FDIMS_ADDR(UNIT))) + +/** Set the content of the FDIMS register of one of the POOL Units. */ +#define ATON_POOL_FDIMS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_FDIMS_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FDIMS register. + * + * \return the description of FDIMS register + */ + +static inline const int8_t *ATON_POOL_FDIMS_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_FDIMS_DESC; +} + + +/** + * Get the offset of the FDIMS register. + * + * \return the offset of FDIMS register + */ + +static inline uint32_t ATON_POOL_FDIMS_GetOffset(void) +{ + return ATON_POOL_FDIMS_OFFSET; +} + + +/** + * Get the address of the FDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the FDIMS register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of FDIMS register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_FDIMS_GetAddr(uint32_t instance) +{ + return ATON_POOL_FDIMS_ADDR(instance); +} + + +/** + * Read the content of the FDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the FDIMS register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of FDIMS register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_FDIMS_Get(uint32_t instance) +{ + return ATON_POOL_FDIMS_GET(instance); +} + + +/** + * Write the content of the FDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the FDIMS register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_FDIMS_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_FDIMS_SET(instance, data); +} + + +/* ----------------------------------------------------------- FEATX field of the FDIMS register ------------------------------------------------------------ */ + +/** Description of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATX_DESC "Input feature width (actual feature width x batch size)" + +/** Offset of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATX_LSB 0UL + +/** Size in bits of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATX_W (12UL) + +/** Mask for retrieving the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATX_MASK ATON_FIELD_MASK(0UL, 12UL) + +/** Reset value of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATX_DT 0x0UL + +/** Access rights of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATX_AC "RW" + +/** Check whether access to the FEATX field of the FDIMS register is secured or not. */ +#define ATON_POOL_FDIMS_FEATX_S 0 + +/** Check whether access to the FEATX field of the FDIMS register is privileged or not. */ +#define ATON_POOL_FDIMS_FEATX_P 0 + +/** Read the content of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_GET_FEATX(REG) ATON_GET_FIELD(REG, ATON_POOL_FDIMS_FEATX_LSB, ATON_POOL_FDIMS_FEATX_W) + +/** Modify the content of the FEATX field of the FDIMS register. */ +#define ATON_POOL_FDIMS_SET_FEATX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_FDIMS_FEATX_LSB, ATON_POOL_FDIMS_FEATX_W, DATA) + + +/** + * Get the description of the FEATX field of FDIMS register. + * + * \return the description of the FEATX field of FDIMS register + */ + +static inline const int8_t *ATON_POOL_FDIMS_FEATX_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_FDIMS_FEATX_DESC; +} + + +/** + * Read the content of the FEATX field of the FDIMS register. + * + * \param[in] reg is the value of the FDIMS register + * + * \return the content of the FEATX field belonging to FDIMS register + */ + +static inline uint32_t ATON_POOL_FDIMS_Get_FEATX(uint32_t reg) +{ + return ATON_POOL_FDIMS_GET_FEATX(reg); +} + + +/** + * Write the content of the FEATX field of the FDIMS register. + * + * \param[in] reg is the value of the FDIMS register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the FEATX field belonging to FDIMS register + */ + +static inline uint32_t ATON_POOL_FDIMS_Set_FEATX(uint32_t reg, uint32_t data) +{ + return ATON_POOL_FDIMS_SET_FEATX(reg, data); +} + + +/* ----------------------------------------------------------- FEATY field of the FDIMS register ------------------------------------------------------------ */ + +/** Description of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATY_DESC "Input feature height (actual feature height)" + +/** Offset of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATY_LSB 16UL + +/** Size in bits of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATY_W (12UL) + +/** Mask for retrieving the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATY_MASK ATON_FIELD_MASK(16UL, 12UL) + +/** Reset value of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATY_DT 0x0UL + +/** Access rights of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_FEATY_AC "RW" + +/** Check whether access to the FEATY field of the FDIMS register is secured or not. */ +#define ATON_POOL_FDIMS_FEATY_S 0 + +/** Check whether access to the FEATY field of the FDIMS register is privileged or not. */ +#define ATON_POOL_FDIMS_FEATY_P 0 + +/** Read the content of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_GET_FEATY(REG) ATON_GET_FIELD(REG, ATON_POOL_FDIMS_FEATY_LSB, ATON_POOL_FDIMS_FEATY_W) + +/** Modify the content of the FEATY field of the FDIMS register. */ +#define ATON_POOL_FDIMS_SET_FEATY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_FDIMS_FEATY_LSB, ATON_POOL_FDIMS_FEATY_W, DATA) + + +/** + * Get the description of the FEATY field of FDIMS register. + * + * \return the description of the FEATY field of FDIMS register + */ + +static inline const int8_t *ATON_POOL_FDIMS_FEATY_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_FDIMS_FEATY_DESC; +} + + +/** + * Read the content of the FEATY field of the FDIMS register. + * + * \param[in] reg is the value of the FDIMS register + * + * \return the content of the FEATY field belonging to FDIMS register + */ + +static inline uint32_t ATON_POOL_FDIMS_Get_FEATY(uint32_t reg) +{ + return ATON_POOL_FDIMS_GET_FEATY(reg); +} + + +/** + * Write the content of the FEATY field of the FDIMS register. + * + * \param[in] reg is the value of the FDIMS register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the FEATY field belonging to FDIMS register + */ + +static inline uint32_t ATON_POOL_FDIMS_Set_FEATY(uint32_t reg, uint32_t data) +{ + return ATON_POOL_FDIMS_SET_FEATY(reg, data); +} + + +/* ******************************************************* OUTDIMS register of one of the POOL Units ******************************************************** */ + +/** Offset of the OUTDIMS register from the base address of the POOL Unit. */ +#define ATON_POOL_OUTDIMS_OFFSET 0x10UL + +/** Reset value of the OUTDIMS register of the POOL Unit. */ +#define ATON_POOL_OUTDIMS_DT \ + (ATON_POOL_OUTDIMS_FEATX_DT << ATON_POOL_OUTDIMS_FEATX_LSB) | \ + (ATON_POOL_OUTDIMS_FEATY_DT << ATON_POOL_OUTDIMS_FEATY_LSB) + + + +/** Description of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_DESC "Output feature dimensions" + +/** Address of the OUTDIMS register of one of the POOL Units. */ +#define ATON_POOL_OUTDIMS_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_OUTDIMS_OFFSET) + +/** Get the content of the OUTDIMS register of one of the POOL Units. */ +#define ATON_POOL_OUTDIMS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_OUTDIMS_ADDR(UNIT))) + +/** Set the content of the OUTDIMS register of one of the POOL Units. */ +#define ATON_POOL_OUTDIMS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_OUTDIMS_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of OUTDIMS register. + * + * \return the description of OUTDIMS register + */ + +static inline const int8_t *ATON_POOL_OUTDIMS_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_OUTDIMS_DESC; +} + + +/** + * Get the offset of the OUTDIMS register. + * + * \return the offset of OUTDIMS register + */ + +static inline uint32_t ATON_POOL_OUTDIMS_GetOffset(void) +{ + return ATON_POOL_OUTDIMS_OFFSET; +} + + +/** + * Get the address of the OUTDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the OUTDIMS register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of OUTDIMS register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_OUTDIMS_GetAddr(uint32_t instance) +{ + return ATON_POOL_OUTDIMS_ADDR(instance); +} + + +/** + * Read the content of the OUTDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the OUTDIMS register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of OUTDIMS register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_OUTDIMS_Get(uint32_t instance) +{ + return ATON_POOL_OUTDIMS_GET(instance); +} + + +/** + * Write the content of the OUTDIMS register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the OUTDIMS register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_OUTDIMS_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_OUTDIMS_SET(instance, data); +} + + +/* ---------------------------------------------------------- FEATX field of the OUTDIMS register ----------------------------------------------------------- */ + +/** Description of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATX_DESC "Output feature width" + +/** Offset of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATX_LSB 0UL + +/** Size in bits of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATX_W (12UL) + +/** Mask for retrieving the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATX_MASK ATON_FIELD_MASK(0UL, 12UL) + +/** Reset value of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATX_DT 0x0UL + +/** Access rights of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATX_AC "RW" + +/** Check whether access to the FEATX field of the OUTDIMS register is secured or not. */ +#define ATON_POOL_OUTDIMS_FEATX_S 0 + +/** Check whether access to the FEATX field of the OUTDIMS register is privileged or not. */ +#define ATON_POOL_OUTDIMS_FEATX_P 0 + +/** Read the content of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_GET_FEATX(REG) ATON_GET_FIELD(REG, ATON_POOL_OUTDIMS_FEATX_LSB, ATON_POOL_OUTDIMS_FEATX_W) + +/** Modify the content of the FEATX field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_SET_FEATX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_OUTDIMS_FEATX_LSB, ATON_POOL_OUTDIMS_FEATX_W, DATA) + + +/** + * Get the description of the FEATX field of OUTDIMS register. + * + * \return the description of the FEATX field of OUTDIMS register + */ + +static inline const int8_t *ATON_POOL_OUTDIMS_FEATX_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_OUTDIMS_FEATX_DESC; +} + + +/** + * Read the content of the FEATX field of the OUTDIMS register. + * + * \param[in] reg is the value of the OUTDIMS register + * + * \return the content of the FEATX field belonging to OUTDIMS register + */ + +static inline uint32_t ATON_POOL_OUTDIMS_Get_FEATX(uint32_t reg) +{ + return ATON_POOL_OUTDIMS_GET_FEATX(reg); +} + + +/** + * Write the content of the FEATX field of the OUTDIMS register. + * + * \param[in] reg is the value of the OUTDIMS register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the FEATX field belonging to OUTDIMS register + */ + +static inline uint32_t ATON_POOL_OUTDIMS_Set_FEATX(uint32_t reg, uint32_t data) +{ + return ATON_POOL_OUTDIMS_SET_FEATX(reg, data); +} + + +/* ---------------------------------------------------------- FEATY field of the OUTDIMS register ----------------------------------------------------------- */ + +/** Description of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATY_DESC "Output feature height" + +/** Offset of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATY_LSB 16UL + +/** Size in bits of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATY_W (12UL) + +/** Mask for retrieving the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATY_MASK ATON_FIELD_MASK(16UL, 12UL) + +/** Reset value of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATY_DT 0x0UL + +/** Access rights of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_FEATY_AC "RW" + +/** Check whether access to the FEATY field of the OUTDIMS register is secured or not. */ +#define ATON_POOL_OUTDIMS_FEATY_S 0 + +/** Check whether access to the FEATY field of the OUTDIMS register is privileged or not. */ +#define ATON_POOL_OUTDIMS_FEATY_P 0 + +/** Read the content of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_GET_FEATY(REG) ATON_GET_FIELD(REG, ATON_POOL_OUTDIMS_FEATY_LSB, ATON_POOL_OUTDIMS_FEATY_W) + +/** Modify the content of the FEATY field of the OUTDIMS register. */ +#define ATON_POOL_OUTDIMS_SET_FEATY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_OUTDIMS_FEATY_LSB, ATON_POOL_OUTDIMS_FEATY_W, DATA) + + +/** + * Get the description of the FEATY field of OUTDIMS register. + * + * \return the description of the FEATY field of OUTDIMS register + */ + +static inline const int8_t *ATON_POOL_OUTDIMS_FEATY_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_OUTDIMS_FEATY_DESC; +} + + +/** + * Read the content of the FEATY field of the OUTDIMS register. + * + * \param[in] reg is the value of the OUTDIMS register + * + * \return the content of the FEATY field belonging to OUTDIMS register + */ + +static inline uint32_t ATON_POOL_OUTDIMS_Get_FEATY(uint32_t reg) +{ + return ATON_POOL_OUTDIMS_GET_FEATY(reg); +} + + +/** + * Write the content of the FEATY field of the OUTDIMS register. + * + * \param[in] reg is the value of the OUTDIMS register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the FEATY field belonging to OUTDIMS register + */ + +static inline uint32_t ATON_POOL_OUTDIMS_Set_FEATY(uint32_t reg, uint32_t data) +{ + return ATON_POOL_OUTDIMS_SET_FEATY(reg, data); +} + + +/* ******************************************************** MULVAL register of one of the POOL Units ******************************************************** */ + +/** Offset of the MULVAL register from the base address of the POOL Unit. */ +#define ATON_POOL_MULVAL_OFFSET 0x14UL + +/** Reset value of the MULVAL register of the POOL Unit. */ +#define ATON_POOL_MULVAL_DT \ + (ATON_POOL_MULVAL_MULVAL_DT << ATON_POOL_MULVAL_MULVAL_LSB) + + + +/** Description of the MULVAL register. */ +#define ATON_POOL_MULVAL_DESC "average pooling data" + +/** Address of the MULVAL register of one of the POOL Units. */ +#define ATON_POOL_MULVAL_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_MULVAL_OFFSET) + +/** Get the content of the MULVAL register of one of the POOL Units. */ +#define ATON_POOL_MULVAL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_MULVAL_ADDR(UNIT))) + +/** Set the content of the MULVAL register of one of the POOL Units. */ +#define ATON_POOL_MULVAL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_MULVAL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of MULVAL register. + * + * \return the description of MULVAL register + */ + +static inline const int8_t *ATON_POOL_MULVAL_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_MULVAL_DESC; +} + + +/** + * Get the offset of the MULVAL register. + * + * \return the offset of MULVAL register + */ + +static inline uint32_t ATON_POOL_MULVAL_GetOffset(void) +{ + return ATON_POOL_MULVAL_OFFSET; +} + + +/** + * Get the address of the MULVAL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the MULVAL register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of MULVAL register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_MULVAL_GetAddr(uint32_t instance) +{ + return ATON_POOL_MULVAL_ADDR(instance); +} + + +/** + * Read the content of the MULVAL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the MULVAL register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of MULVAL register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_MULVAL_Get(uint32_t instance) +{ + return ATON_POOL_MULVAL_GET(instance); +} + + +/** + * Write the content of the MULVAL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the MULVAL register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_MULVAL_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_MULVAL_SET(instance, data); +} + + +/* ---------------------------------------------------------- MULVAL field of the MULVAL register ----------------------------------------------------------- */ + +/** Description of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_MULVAL_DESC "constant to be multiplied to accumulated sum of pooling window. For average operation, it represents the reciprocal of the divisor in 16-bit fixed point. The average is computed by multiplying this constant with the accumulated sum and then applying the relevant right shift at the output. (Applicable to average pooling operations)" + +/** Offset of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_MULVAL_LSB 0UL + +/** Size in bits of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_MULVAL_W (16UL) + +/** Mask for retrieving the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_MULVAL_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_MULVAL_DT 0x0UL + +/** Access rights of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_MULVAL_AC "RW" + +/** Check whether access to the MULVAL field of the MULVAL register is secured or not. */ +#define ATON_POOL_MULVAL_MULVAL_S 0 + +/** Check whether access to the MULVAL field of the MULVAL register is privileged or not. */ +#define ATON_POOL_MULVAL_MULVAL_P 0 + +/** Read the content of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_GET_MULVAL(REG) ATON_GET_FIELD(REG, ATON_POOL_MULVAL_MULVAL_LSB, ATON_POOL_MULVAL_MULVAL_W) + +/** Modify the content of the MULVAL field of the MULVAL register. */ +#define ATON_POOL_MULVAL_SET_MULVAL(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_MULVAL_MULVAL_LSB, ATON_POOL_MULVAL_MULVAL_W, DATA) + + +/** + * Get the description of the MULVAL field of MULVAL register. + * + * \return the description of the MULVAL field of MULVAL register + */ + +static inline const int8_t *ATON_POOL_MULVAL_MULVAL_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_MULVAL_MULVAL_DESC; +} + + +/** + * Read the content of the MULVAL field of the MULVAL register. + * + * \param[in] reg is the value of the MULVAL register + * + * \return the content of the MULVAL field belonging to MULVAL register + */ + +static inline uint32_t ATON_POOL_MULVAL_Get_MULVAL(uint32_t reg) +{ + return ATON_POOL_MULVAL_GET_MULVAL(reg); +} + + +/** + * Write the content of the MULVAL field of the MULVAL register. + * + * \param[in] reg is the value of the MULVAL register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the MULVAL field belonging to MULVAL register + */ + +static inline uint32_t ATON_POOL_MULVAL_Set_MULVAL(uint32_t reg, uint32_t data) +{ + return ATON_POOL_MULVAL_SET_MULVAL(reg, data); +} + + +/* ******************************************************** XCROP register of one of the POOL Units ********************************************************* */ + +/** Offset of the XCROP register from the base address of the POOL Unit. */ +#define ATON_POOL_XCROP_OFFSET 0x18UL + +/** Reset value of the XCROP register of the POOL Unit. */ +#define ATON_POOL_XCROP_DT \ + (ATON_POOL_XCROP_LCROP_DT << ATON_POOL_XCROP_LCROP_LSB) | \ + (ATON_POOL_XCROP_RCROP_DT << ATON_POOL_XCROP_RCROP_LSB) + + + +/** Description of the XCROP register. */ +#define ATON_POOL_XCROP_DESC "left/right cropping dimensions" + +/** Address of the XCROP register of one of the POOL Units. */ +#define ATON_POOL_XCROP_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_XCROP_OFFSET) + +/** Get the content of the XCROP register of one of the POOL Units. */ +#define ATON_POOL_XCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_XCROP_ADDR(UNIT))) + +/** Set the content of the XCROP register of one of the POOL Units. */ +#define ATON_POOL_XCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_XCROP_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of XCROP register. + * + * \return the description of XCROP register + */ + +static inline const int8_t *ATON_POOL_XCROP_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_XCROP_DESC; +} + + +/** + * Get the offset of the XCROP register. + * + * \return the offset of XCROP register + */ + +static inline uint32_t ATON_POOL_XCROP_GetOffset(void) +{ + return ATON_POOL_XCROP_OFFSET; +} + + +/** + * Get the address of the XCROP register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the XCROP register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of XCROP register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_XCROP_GetAddr(uint32_t instance) +{ + return ATON_POOL_XCROP_ADDR(instance); +} + + +/** + * Read the content of the XCROP register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the XCROP register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of XCROP register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_XCROP_Get(uint32_t instance) +{ + return ATON_POOL_XCROP_GET(instance); +} + + +/** + * Write the content of the XCROP register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the XCROP register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_XCROP_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_XCROP_SET(instance, data); +} + + +/* ----------------------------------------------------------- LCROP field of the XCROP register ------------------------------------------------------------ */ + +/** Description of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_LCROP_DESC "left crop index (zero-indexed) to be included in the crop" + +/** Offset of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_LCROP_LSB 0UL + +/** Size in bits of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_LCROP_W (12UL) + +/** Mask for retrieving the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_LCROP_MASK ATON_FIELD_MASK(0UL, 12UL) + +/** Reset value of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_LCROP_DT 0x0UL + +/** Access rights of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_LCROP_AC "RW" + +/** Check whether access to the LCROP field of the XCROP register is secured or not. */ +#define ATON_POOL_XCROP_LCROP_S 0 + +/** Check whether access to the LCROP field of the XCROP register is privileged or not. */ +#define ATON_POOL_XCROP_LCROP_P 0 + +/** Read the content of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_GET_LCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_XCROP_LCROP_LSB, ATON_POOL_XCROP_LCROP_W) + +/** Modify the content of the LCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_SET_LCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_XCROP_LCROP_LSB, ATON_POOL_XCROP_LCROP_W, DATA) + + +/** + * Get the description of the LCROP field of XCROP register. + * + * \return the description of the LCROP field of XCROP register + */ + +static inline const int8_t *ATON_POOL_XCROP_LCROP_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_XCROP_LCROP_DESC; +} + + +/** + * Read the content of the LCROP field of the XCROP register. + * + * \param[in] reg is the value of the XCROP register + * + * \return the content of the LCROP field belonging to XCROP register + */ + +static inline uint32_t ATON_POOL_XCROP_Get_LCROP(uint32_t reg) +{ + return ATON_POOL_XCROP_GET_LCROP(reg); +} + + +/** + * Write the content of the LCROP field of the XCROP register. + * + * \param[in] reg is the value of the XCROP register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the LCROP field belonging to XCROP register + */ + +static inline uint32_t ATON_POOL_XCROP_Set_LCROP(uint32_t reg, uint32_t data) +{ + return ATON_POOL_XCROP_SET_LCROP(reg, data); +} + + +/* ----------------------------------------------------------- RCROP field of the XCROP register ------------------------------------------------------------ */ + +/** Description of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_RCROP_DESC "right crop index (zero-indexed) to be included in the crop" + +/** Offset of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_RCROP_LSB 16UL + +/** Size in bits of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_RCROP_W (12UL) + +/** Mask for retrieving the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_RCROP_MASK ATON_FIELD_MASK(16UL, 12UL) + +/** Reset value of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_RCROP_DT 0x0UL + +/** Access rights of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_RCROP_AC "RW" + +/** Check whether access to the RCROP field of the XCROP register is secured or not. */ +#define ATON_POOL_XCROP_RCROP_S 0 + +/** Check whether access to the RCROP field of the XCROP register is privileged or not. */ +#define ATON_POOL_XCROP_RCROP_P 0 + +/** Read the content of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_GET_RCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_XCROP_RCROP_LSB, ATON_POOL_XCROP_RCROP_W) + +/** Modify the content of the RCROP field of the XCROP register. */ +#define ATON_POOL_XCROP_SET_RCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_XCROP_RCROP_LSB, ATON_POOL_XCROP_RCROP_W, DATA) + + +/** + * Get the description of the RCROP field of XCROP register. + * + * \return the description of the RCROP field of XCROP register + */ + +static inline const int8_t *ATON_POOL_XCROP_RCROP_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_XCROP_RCROP_DESC; +} + + +/** + * Read the content of the RCROP field of the XCROP register. + * + * \param[in] reg is the value of the XCROP register + * + * \return the content of the RCROP field belonging to XCROP register + */ + +static inline uint32_t ATON_POOL_XCROP_Get_RCROP(uint32_t reg) +{ + return ATON_POOL_XCROP_GET_RCROP(reg); +} + + +/** + * Write the content of the RCROP field of the XCROP register. + * + * \param[in] reg is the value of the XCROP register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the RCROP field belonging to XCROP register + */ + +static inline uint32_t ATON_POOL_XCROP_Set_RCROP(uint32_t reg, uint32_t data) +{ + return ATON_POOL_XCROP_SET_RCROP(reg, data); +} + + +/* ******************************************************** YCROP register of one of the POOL Units ********************************************************* */ + +/** Offset of the YCROP register from the base address of the POOL Unit. */ +#define ATON_POOL_YCROP_OFFSET 0x1cUL + +/** Reset value of the YCROP register of the POOL Unit. */ +#define ATON_POOL_YCROP_DT \ + (ATON_POOL_YCROP_TCROP_DT << ATON_POOL_YCROP_TCROP_LSB) | \ + (ATON_POOL_YCROP_BCROP_DT << ATON_POOL_YCROP_BCROP_LSB) + + + +/** Description of the YCROP register. */ +#define ATON_POOL_YCROP_DESC "top/bottom cropping dimensions" + +/** Address of the YCROP register of one of the POOL Units. */ +#define ATON_POOL_YCROP_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_YCROP_OFFSET) + +/** Get the content of the YCROP register of one of the POOL Units. */ +#define ATON_POOL_YCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_YCROP_ADDR(UNIT))) + +/** Set the content of the YCROP register of one of the POOL Units. */ +#define ATON_POOL_YCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_YCROP_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of YCROP register. + * + * \return the description of YCROP register + */ + +static inline const int8_t *ATON_POOL_YCROP_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_YCROP_DESC; +} + + +/** + * Get the offset of the YCROP register. + * + * \return the offset of YCROP register + */ + +static inline uint32_t ATON_POOL_YCROP_GetOffset(void) +{ + return ATON_POOL_YCROP_OFFSET; +} + + +/** + * Get the address of the YCROP register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the YCROP register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of YCROP register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_YCROP_GetAddr(uint32_t instance) +{ + return ATON_POOL_YCROP_ADDR(instance); +} + + +/** + * Read the content of the YCROP register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the YCROP register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of YCROP register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_YCROP_Get(uint32_t instance) +{ + return ATON_POOL_YCROP_GET(instance); +} + + +/** + * Write the content of the YCROP register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the YCROP register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_YCROP_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_YCROP_SET(instance, data); +} + + +/* ----------------------------------------------------------- TCROP field of the YCROP register ------------------------------------------------------------ */ + +/** Description of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_TCROP_DESC "top crop index (zero-indexed) to be included in the crop" + +/** Offset of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_TCROP_LSB 0UL + +/** Size in bits of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_TCROP_W (12UL) + +/** Mask for retrieving the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_TCROP_MASK ATON_FIELD_MASK(0UL, 12UL) + +/** Reset value of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_TCROP_DT 0x0UL + +/** Access rights of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_TCROP_AC "RW" + +/** Check whether access to the TCROP field of the YCROP register is secured or not. */ +#define ATON_POOL_YCROP_TCROP_S 0 + +/** Check whether access to the TCROP field of the YCROP register is privileged or not. */ +#define ATON_POOL_YCROP_TCROP_P 0 + +/** Read the content of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_GET_TCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_YCROP_TCROP_LSB, ATON_POOL_YCROP_TCROP_W) + +/** Modify the content of the TCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_SET_TCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_YCROP_TCROP_LSB, ATON_POOL_YCROP_TCROP_W, DATA) + + +/** + * Get the description of the TCROP field of YCROP register. + * + * \return the description of the TCROP field of YCROP register + */ + +static inline const int8_t *ATON_POOL_YCROP_TCROP_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_YCROP_TCROP_DESC; +} + + +/** + * Read the content of the TCROP field of the YCROP register. + * + * \param[in] reg is the value of the YCROP register + * + * \return the content of the TCROP field belonging to YCROP register + */ + +static inline uint32_t ATON_POOL_YCROP_Get_TCROP(uint32_t reg) +{ + return ATON_POOL_YCROP_GET_TCROP(reg); +} + + +/** + * Write the content of the TCROP field of the YCROP register. + * + * \param[in] reg is the value of the YCROP register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the TCROP field belonging to YCROP register + */ + +static inline uint32_t ATON_POOL_YCROP_Set_TCROP(uint32_t reg, uint32_t data) +{ + return ATON_POOL_YCROP_SET_TCROP(reg, data); +} + + +/* ----------------------------------------------------------- BCROP field of the YCROP register ------------------------------------------------------------ */ + +/** Description of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_BCROP_DESC "bottom crop index (zero-indexed) to be included in the crop" + +/** Offset of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_BCROP_LSB 16UL + +/** Size in bits of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_BCROP_W (12UL) + +/** Mask for retrieving the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_BCROP_MASK ATON_FIELD_MASK(16UL, 12UL) + +/** Reset value of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_BCROP_DT 0x0UL + +/** Access rights of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_BCROP_AC "RW" + +/** Check whether access to the BCROP field of the YCROP register is secured or not. */ +#define ATON_POOL_YCROP_BCROP_S 0 + +/** Check whether access to the BCROP field of the YCROP register is privileged or not. */ +#define ATON_POOL_YCROP_BCROP_P 0 + +/** Read the content of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_GET_BCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_YCROP_BCROP_LSB, ATON_POOL_YCROP_BCROP_W) + +/** Modify the content of the BCROP field of the YCROP register. */ +#define ATON_POOL_YCROP_SET_BCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_YCROP_BCROP_LSB, ATON_POOL_YCROP_BCROP_W, DATA) + + +/** + * Get the description of the BCROP field of YCROP register. + * + * \return the description of the BCROP field of YCROP register + */ + +static inline const int8_t *ATON_POOL_YCROP_BCROP_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_YCROP_BCROP_DESC; +} + + +/** + * Read the content of the BCROP field of the YCROP register. + * + * \param[in] reg is the value of the YCROP register + * + * \return the content of the BCROP field belonging to YCROP register + */ + +static inline uint32_t ATON_POOL_YCROP_Get_BCROP(uint32_t reg) +{ + return ATON_POOL_YCROP_GET_BCROP(reg); +} + + +/** + * Write the content of the BCROP field of the YCROP register. + * + * \param[in] reg is the value of the YCROP register + * \param[in] data is 12-bit value that must be written to the field + * + * \return the new content of the BCROP field belonging to YCROP register + */ + +static inline uint32_t ATON_POOL_YCROP_Set_BCROP(uint32_t reg, uint32_t data) +{ + return ATON_POOL_YCROP_SET_BCROP(reg, data); +} + + +/* ******************************************************* RNDCTRL register of one of the POOL Units ******************************************************** */ + +/** Offset of the RNDCTRL register from the base address of the POOL Unit. */ +#define ATON_POOL_RNDCTRL_OFFSET 0x20UL + +/** Reset value of the RNDCTRL register of the POOL Unit. */ +#define ATON_POOL_RNDCTRL_DT \ + (ATON_POOL_RNDCTRL_FOBYTES_DT << ATON_POOL_RNDCTRL_FOBYTES_LSB) | \ + (ATON_POOL_RNDCTRL_FRNDMODE_DT << ATON_POOL_RNDCTRL_FRNDMODE_LSB) | \ + (ATON_POOL_RNDCTRL_OBYTES_DT << ATON_POOL_RNDCTRL_OBYTES_LSB) | \ + (ATON_POOL_RNDCTRL_ORNDMODE_DT << ATON_POOL_RNDCTRL_ORNDMODE_LSB) + + + +/** Description of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_DESC "input and output rounding control" + +/** Address of the RNDCTRL register of one of the POOL Units. */ +#define ATON_POOL_RNDCTRL_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_RNDCTRL_OFFSET) + +/** Get the content of the RNDCTRL register of one of the POOL Units. */ +#define ATON_POOL_RNDCTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_RNDCTRL_ADDR(UNIT))) + +/** Set the content of the RNDCTRL register of one of the POOL Units. */ +#define ATON_POOL_RNDCTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_RNDCTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of RNDCTRL register. + * + * \return the description of RNDCTRL register + */ + +static inline const int8_t *ATON_POOL_RNDCTRL_GetDesc(void) +{ + return (const int8_t *)ATON_POOL_RNDCTRL_DESC; +} + + +/** + * Get the offset of the RNDCTRL register. + * + * \return the offset of RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_GetOffset(void) +{ + return ATON_POOL_RNDCTRL_OFFSET; +} + + +/** + * Get the address of the RNDCTRL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the RNDCTRL register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of RNDCTRL register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_RNDCTRL_GetAddr(uint32_t instance) +{ + return ATON_POOL_RNDCTRL_ADDR(instance); +} + + +/** + * Read the content of the RNDCTRL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the RNDCTRL register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of RNDCTRL register belonging to Unit having index \e instance among the POOL Units + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Get(uint32_t instance) +{ + return ATON_POOL_RNDCTRL_GET(instance); +} + + +/** + * Write the content of the RNDCTRL register. + * + * \param[in] instance is the index of the Unit (among the POOL Units) containing the RNDCTRL register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_POOL_RNDCTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_POOL_RNDCTRL_SET(instance, data); +} + + +/* --------------------------------------------------------- FOBYTES field of the RNDCTRL register ---------------------------------------------------------- */ + +/** Description of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FOBYTES_DESC "Number of output bytes to use for input feature data after rounding or saturation. Valid values are 1 or 2 bytes" + +/** Offset of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FOBYTES_LSB 0UL + +/** Size in bits of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FOBYTES_W (2UL) + +/** Mask for retrieving the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FOBYTES_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FOBYTES_DT 0x2UL + +/** Access rights of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FOBYTES_AC "RW" + +/** Check whether access to the FOBYTES field of the RNDCTRL register is secured or not. */ +#define ATON_POOL_RNDCTRL_FOBYTES_S 0 + +/** Check whether access to the FOBYTES field of the RNDCTRL register is privileged or not. */ +#define ATON_POOL_RNDCTRL_FOBYTES_P 0 + +/** Read the content of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_GET_FOBYTES(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_FOBYTES_LSB, ATON_POOL_RNDCTRL_FOBYTES_W) + +/** Modify the content of the FOBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_SET_FOBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_FOBYTES_LSB, ATON_POOL_RNDCTRL_FOBYTES_W, DATA) + + +/** + * Get the description of the FOBYTES field of RNDCTRL register. + * + * \return the description of the FOBYTES field of RNDCTRL register + */ + +static inline const int8_t *ATON_POOL_RNDCTRL_FOBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_RNDCTRL_FOBYTES_DESC; +} + + +/** + * Read the content of the FOBYTES field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * + * \return the content of the FOBYTES field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Get_FOBYTES(uint32_t reg) +{ + return ATON_POOL_RNDCTRL_GET_FOBYTES(reg); +} + + +/** + * Write the content of the FOBYTES field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FOBYTES field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Set_FOBYTES(uint32_t reg, uint32_t data) +{ + return ATON_POOL_RNDCTRL_SET_FOBYTES(reg, data); +} + + +/* --------------------------------------------------------- FRNDMODE field of the RNDCTRL register --------------------------------------------------------- */ + +/** Description of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_DESC "rounding mode to apply to input feature data. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_LSB 2UL + +/** Size in bits of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_W (2UL) + +/** Mask for retrieving the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_MASK ATON_FIELD_MASK(2UL, 2UL) + +/** Reset value of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_DT 0x0UL + +/** Access rights of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_AC "RW" + +/** Check whether access to the FRNDMODE field of the RNDCTRL register is secured or not. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_S 0 + +/** Check whether access to the FRNDMODE field of the RNDCTRL register is privileged or not. */ +#define ATON_POOL_RNDCTRL_FRNDMODE_P 0 + +/** Read the content of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_GET_FRNDMODE(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_FRNDMODE_LSB, ATON_POOL_RNDCTRL_FRNDMODE_W) + +/** Modify the content of the FRNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_SET_FRNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_FRNDMODE_LSB, ATON_POOL_RNDCTRL_FRNDMODE_W, DATA) + + +/** + * Get the description of the FRNDMODE field of RNDCTRL register. + * + * \return the description of the FRNDMODE field of RNDCTRL register + */ + +static inline const int8_t *ATON_POOL_RNDCTRL_FRNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_RNDCTRL_FRNDMODE_DESC; +} + + +/** + * Read the content of the FRNDMODE field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * + * \return the content of the FRNDMODE field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Get_FRNDMODE(uint32_t reg) +{ + return ATON_POOL_RNDCTRL_GET_FRNDMODE(reg); +} + + +/** + * Write the content of the FRNDMODE field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FRNDMODE field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Set_FRNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_POOL_RNDCTRL_SET_FRNDMODE(reg, data); +} + + +/* ---------------------------------------------------------- OBYTES field of the RNDCTRL register ---------------------------------------------------------- */ + +/** Description of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_OBYTES_DESC "Number of output bytes to use for final result after rounding or saturation. Valid values are 1 or 2 bytes" + +/** Offset of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_OBYTES_LSB 16UL + +/** Size in bits of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_OBYTES_W (2UL) + +/** Mask for retrieving the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_OBYTES_MASK ATON_FIELD_MASK(16UL, 2UL) + +/** Reset value of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_OBYTES_DT 0x2UL + +/** Access rights of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_OBYTES_AC "RW" + +/** Check whether access to the OBYTES field of the RNDCTRL register is secured or not. */ +#define ATON_POOL_RNDCTRL_OBYTES_S 0 + +/** Check whether access to the OBYTES field of the RNDCTRL register is privileged or not. */ +#define ATON_POOL_RNDCTRL_OBYTES_P 0 + +/** Read the content of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_OBYTES_LSB, ATON_POOL_RNDCTRL_OBYTES_W) + +/** Modify the content of the OBYTES field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_OBYTES_LSB, ATON_POOL_RNDCTRL_OBYTES_W, DATA) + + +/** + * Get the description of the OBYTES field of RNDCTRL register. + * + * \return the description of the OBYTES field of RNDCTRL register + */ + +static inline const int8_t *ATON_POOL_RNDCTRL_OBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_RNDCTRL_OBYTES_DESC; +} + + +/** + * Read the content of the OBYTES field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * + * \return the content of the OBYTES field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Get_OBYTES(uint32_t reg) +{ + return ATON_POOL_RNDCTRL_GET_OBYTES(reg); +} + + +/** + * Write the content of the OBYTES field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the OBYTES field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Set_OBYTES(uint32_t reg, uint32_t data) +{ + return ATON_POOL_RNDCTRL_SET_OBYTES(reg, data); +} + + +/* --------------------------------------------------------- ORNDMODE field of the RNDCTRL register --------------------------------------------------------- */ + +/** Description of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_DESC "rounding mode to apply to output feature data. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" + +/** Offset of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_LSB 18UL + +/** Size in bits of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_W (2UL) + +/** Mask for retrieving the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_MASK ATON_FIELD_MASK(18UL, 2UL) + +/** Reset value of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_DT 0x0UL + +/** Access rights of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_AC "RW" + +/** Check whether access to the ORNDMODE field of the RNDCTRL register is secured or not. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_S 0 + +/** Check whether access to the ORNDMODE field of the RNDCTRL register is privileged or not. */ +#define ATON_POOL_RNDCTRL_ORNDMODE_P 0 + +/** Read the content of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_ORNDMODE_LSB, ATON_POOL_RNDCTRL_ORNDMODE_W) + +/** Modify the content of the ORNDMODE field of the RNDCTRL register. */ +#define ATON_POOL_RNDCTRL_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_ORNDMODE_LSB, ATON_POOL_RNDCTRL_ORNDMODE_W, DATA) + + +/** + * Get the description of the ORNDMODE field of RNDCTRL register. + * + * \return the description of the ORNDMODE field of RNDCTRL register + */ + +static inline const int8_t *ATON_POOL_RNDCTRL_ORNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_POOL_RNDCTRL_ORNDMODE_DESC; +} + + +/** + * Read the content of the ORNDMODE field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * + * \return the content of the ORNDMODE field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Get_ORNDMODE(uint32_t reg) +{ + return ATON_POOL_RNDCTRL_GET_ORNDMODE(reg); +} + + +/** + * Write the content of the ORNDMODE field of the RNDCTRL register. + * + * \param[in] reg is the value of the RNDCTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ORNDMODE field belonging to RNDCTRL register + */ + +static inline uint32_t ATON_POOL_RNDCTRL_Set_ORNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_POOL_RNDCTRL_SET_ORNDMODE(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* BUSIF Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of BUSIF Unit instances. */ +#define ATON_BUSIF_NUM 2 + +/** + * \name Structures, macros and functions of the BUSIF Units + */ +/*@{*/ + +/** + * Registers of the BUSIF Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e PRIO1 register (Priority register 1). */ + uint32_t PRIO1; + + /** \e PRIO2 register (Priority register 2). */ + uint32_t PRIO2; + + /** \e ERR register (Error register). */ + uint32_t ERR; + + /** \e KEY0_31_0 register (Encryption key 0 (bits 31:0)). */ + uint32_t KEY0_31_0; + + /** \e KEY0_63_32 register (Encryption key 0 (bits 63:32)). */ + uint32_t KEY0_63_32; + + /** \e KEY0_95_64 register (Encryption key 0 (bits 95:64)). */ + uint32_t KEY0_95_64; + + /** \e KEY0_127_96 register (Encryption key 0 (bits 127:96)). */ + uint32_t KEY0_127_96; + + /** \e KEY1_31_0 register (Encryption key 1 (bits 31:0)). */ + uint32_t KEY1_31_0; + + /** \e KEY1_63_32 register (Encryption key 1 (bits 63:32)). */ + uint32_t KEY1_63_32; + + /** \e KEY1_95_64 register (Encryption key 1 (bits 95:64)). */ + uint32_t KEY1_95_64; + + /** \e KEY1_127_96 register (Encryption key 1 (bits 127:96)). */ + uint32_t KEY1_127_96; + +} ATON_BUSIF_t; + + +/** Return the pointer to one of the BUSIF Units. */ +#define ATON_BUSIF(UNIT) ((ATON_BUSIF_t *)(intptr_t)ATON_BUSIF_BASE(UNIT)) + + +/** Name of one of the BUSIF Units. */ +#define ATON_BUSIF_NAME(UNIT) \ + (((UNIT) == 0) ? "BUSIF0" : \ + (((UNIT) == 1) ? "BUSIF1" : "")) + + +/** Version of the BUSIF Units. */ +#define ATON_BUSIF_VERSION "5.0" + + +/** Description of one of the BUSIF Units. */ +#define ATON_BUSIF_DESC(UNIT) \ + (((UNIT) == 0) ? "Bus Interface 0" : \ + (((UNIT) == 1) ? "Bus Interface 1" : "")) + + +/** Base address of one of the BUSIF Units. */ +#define ATON_BUSIF_BASE(UNIT) \ + (ATON_BASE + 0x2000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the BUSIF Units. */ +#define ATON_BUSIF_SIZE 0x1000UL + + +/** + * Get the name of one of the BUSIF Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) + * + * \return the name of Unit having index \e instance among the BUSIF Units + */ + +static inline const int8_t *ATON_BUSIF_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"BUSIF0"; + break; + + case 1: + str = (const int8_t *)"BUSIF1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the BUSIF Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) + * + * \return the description of Unit having index \e instance among the BUSIF Units + */ + +static inline const int8_t *ATON_BUSIF_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Bus Interface 0"; + break; + + case 1: + str = (const int8_t *)"Bus Interface 1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the BUSIF Units. + * + * \return the version of the BUSIF Units + */ + +static inline const int8_t *ATON_BUSIF_GetVersion(void) +{ + return (const int8_t *)ATON_BUSIF_VERSION; +} + + +/** + * Get the base address of one of the BUSIF Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) + * + * \return the base address of Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_GetBase(uint32_t instance) +{ + return ATON_BUSIF_BASE(instance); +} + + +/** + * Get the size in bytes of the BUSIF Units. + * + * \return the size in bytes of the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_GetSize(void) +{ + return ATON_BUSIF_SIZE; +} + + +/* ******************************************************** CTRL register of one of the BUSIF Units ********************************************************* */ + +/** Offset of the CTRL register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the BUSIF Unit. */ +#define ATON_BUSIF_CTRL_DT \ + (ATON_BUSIF_CTRL_EN_DT << ATON_BUSIF_CTRL_EN_LSB) | \ + (ATON_BUSIF_CTRL_CLR_DT << ATON_BUSIF_CTRL_CLR_LSB) | \ + (ATON_BUSIF_CTRL_KEY0_VALID_DT << ATON_BUSIF_CTRL_KEY0_VALID_LSB) | \ + (ATON_BUSIF_CTRL_KEY1_VALID_DT << ATON_BUSIF_CTRL_KEY1_VALID_LSB) | \ + (ATON_BUSIF_CTRL_CONFCLR_DT << ATON_BUSIF_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_BUSIF_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the BUSIF Units. */ +#define ATON_BUSIF_CTRL_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the BUSIF Units. */ +#define ATON_BUSIF_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the BUSIF Units. */ +#define ATON_BUSIF_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_BUSIF_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_GetOffset(void) +{ + return ATON_BUSIF_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the CTRL register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_CTRL_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_CTRL_Get(uint32_t instance) +{ + return ATON_BUSIF_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the CTRL register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_EN_DESC "Enable the Bus Interface" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_BUSIF_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_BUSIF_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_EN_LSB, ATON_BUSIF_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_BUSIF_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_CTRL_EN_LSB, ATON_BUSIF_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_BUSIF_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Get_EN(uint32_t reg) +{ + return ATON_BUSIF_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_BUSIF_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_BUSIF_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_CLR_LSB, ATON_BUSIF_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_CTRL_CLR_LSB, ATON_BUSIF_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_BUSIF_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_BUSIF_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_CTRL_SET_CLR(reg, data); +} + + +/* --------------------------------------------------------- KEY0_VALID field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_DESC "Reports key 0 validity" + +/** Offset of the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_LSB 16UL + +/** Size in bits of the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_W (1UL) + +/** Mask for retrieving the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_DT 0x0UL + +/** Access rights of the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_AC "R" + +/** Check whether access to the KEY0_VALID field of the CTRL register is secured or not. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_S 0 + +/** Check whether access to the KEY0_VALID field of the CTRL register is privileged or not. */ +#define ATON_BUSIF_CTRL_KEY0_VALID_P 0 + +/** Read the content of the KEY0_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_GET_KEY0_VALID(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_KEY0_VALID_LSB, ATON_BUSIF_CTRL_KEY0_VALID_W) + + +/** + * Get the description of the KEY0_VALID field of CTRL register. + * + * \return the description of the KEY0_VALID field of CTRL register + */ + +static inline const int8_t *ATON_BUSIF_CTRL_KEY0_VALID_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_CTRL_KEY0_VALID_DESC; +} + + +/** + * Read the content of the KEY0_VALID field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the KEY0_VALID field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Get_KEY0_VALID(uint32_t reg) +{ + return ATON_BUSIF_CTRL_GET_KEY0_VALID(reg); +} + + +/* --------------------------------------------------------- KEY1_VALID field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_DESC "Reports key 1 validity" + +/** Offset of the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_LSB 17UL + +/** Size in bits of the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_W (1UL) + +/** Mask for retrieving the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_DT 0x0UL + +/** Access rights of the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_AC "R" + +/** Check whether access to the KEY1_VALID field of the CTRL register is secured or not. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_S 0 + +/** Check whether access to the KEY1_VALID field of the CTRL register is privileged or not. */ +#define ATON_BUSIF_CTRL_KEY1_VALID_P 0 + +/** Read the content of the KEY1_VALID field of the CTRL register. */ +#define ATON_BUSIF_CTRL_GET_KEY1_VALID(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_KEY1_VALID_LSB, ATON_BUSIF_CTRL_KEY1_VALID_W) + + +/** + * Get the description of the KEY1_VALID field of CTRL register. + * + * \return the description of the KEY1_VALID field of CTRL register + */ + +static inline const int8_t *ATON_BUSIF_CTRL_KEY1_VALID_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_CTRL_KEY1_VALID_DESC; +} + + +/** + * Read the content of the KEY1_VALID field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the KEY1_VALID field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Get_KEY1_VALID(uint32_t reg) +{ + return ATON_BUSIF_CTRL_GET_KEY1_VALID(reg); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_BUSIF_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_BUSIF_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_CONFCLR_LSB, ATON_BUSIF_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_BUSIF_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_CTRL_CONFCLR_LSB, ATON_BUSIF_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_BUSIF_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_BUSIF_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_BUSIF_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_CTRL_SET_CONFCLR(reg, data); +} + + +/* ******************************************************* VERSION register of one of the BUSIF Units ******************************************************* */ + +/** Offset of the VERSION register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_VERSION_OFFSET 0x4UL + +/** + * Get the reset value of the VERSION register of the BUSIF Unit. + * + * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') + * + * \return the reset value of the VERSION register of the BUSIF Unit + */ + +#define ATON_BUSIF_VERSION_DT(UNIT) \ + (((UNIT) == 0) ? ((ATON_BUSIF_VERSION_TYPE_DT << ATON_BUSIF_VERSION_TYPE_LSB) | \ + (ATON_BUSIF_VERSION_MINOR_DT << ATON_BUSIF_VERSION_MINOR_LSB) | \ + (ATON_BUSIF_VERSION_MAJOR_DT << ATON_BUSIF_VERSION_MAJOR_LSB) | \ + (ATON_BUSIF_VERSION_PORTNR_DT(UNIT) << ATON_BUSIF_VERSION_PORTNR_LSB)) : \ + (((UNIT) == 1) ? ((ATON_BUSIF_VERSION_TYPE_DT << ATON_BUSIF_VERSION_TYPE_LSB) | \ + (ATON_BUSIF_VERSION_MINOR_DT << ATON_BUSIF_VERSION_MINOR_LSB) | \ + (ATON_BUSIF_VERSION_MAJOR_DT << ATON_BUSIF_VERSION_MAJOR_LSB) | \ + (ATON_BUSIF_VERSION_PORTNR_DT(UNIT) << ATON_BUSIF_VERSION_PORTNR_LSB)) : \ + 0)) + +/** Description of the VERSION register. */ +#define ATON_BUSIF_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the BUSIF Units. */ +#define ATON_BUSIF_VERSION_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the BUSIF Units. */ +#define ATON_BUSIF_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_BUSIF_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_BUSIF_VERSION_GetOffset(void) +{ + return ATON_BUSIF_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the VERSION register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_VERSION_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_VERSION_Get(uint32_t instance) +{ + return ATON_BUSIF_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_TYPE_DT 0x1dUL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_BUSIF_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_BUSIF_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_BUSIF_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_TYPE_LSB, ATON_BUSIF_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_BUSIF_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_BUSIF_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_BUSIF_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MINOR_DT 0x0UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_BUSIF_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_BUSIF_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_MINOR_LSB, ATON_BUSIF_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_BUSIF_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_BUSIF_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_BUSIF_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MAJOR_DT 0x5UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_BUSIF_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_BUSIF_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_MAJOR_LSB, ATON_BUSIF_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_BUSIF_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_BUSIF_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_BUSIF_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- PORTNR field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the PORTNR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_PORTNR_DESC "Number of stream engines bus muxed into AXI" + +/** Offset of the PORTNR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_PORTNR_LSB 16UL + +/** Size in bits of the PORTNR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_PORTNR_W (8UL) + +/** Mask for retrieving the PORTNR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_PORTNR_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** + * Get the reset value of the PORTNR field of the VERSION register. + * + * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') + * + * \return the reset value of the PORTNR field of the VERSION register + */ + +#define ATON_BUSIF_VERSION_PORTNR_DT(UNIT) \ + (((UNIT) == 0) ? 0x6 : \ + (((UNIT) == 1) ? 0x6 : 0)) + + +/** Access rights of the PORTNR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_PORTNR_AC "R" + +/** Check whether access to the PORTNR field of the VERSION register is secured or not. */ +#define ATON_BUSIF_VERSION_PORTNR_S 0 + +/** Check whether access to the PORTNR field of the VERSION register is privileged or not. */ +#define ATON_BUSIF_VERSION_PORTNR_P 0 + +/** Read the content of the PORTNR field of the VERSION register. */ +#define ATON_BUSIF_VERSION_GET_PORTNR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_PORTNR_LSB, ATON_BUSIF_VERSION_PORTNR_W) + + +/** + * Get the description of the PORTNR field of VERSION register. + * + * \return the description of the PORTNR field of VERSION register + */ + +static inline const int8_t *ATON_BUSIF_VERSION_PORTNR_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_VERSION_PORTNR_DESC; +} + + +/** + * Read the content of the PORTNR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the PORTNR field belonging to VERSION register + */ + +static inline uint32_t ATON_BUSIF_VERSION_Get_PORTNR(uint32_t reg) +{ + return ATON_BUSIF_VERSION_GET_PORTNR(reg); +} + + +/* ******************************************************** PRIO1 register of one of the BUSIF Units ******************************************************** */ + +/** Offset of the PRIO1 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_PRIO1_OFFSET 0x8UL + +/** + * Get the reset value of the PRIO1 register of the BUSIF Unit. + * + * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') + * + * \return the reset value of the PRIO1 register of the BUSIF Unit + */ + +#define ATON_BUSIF_PRIO1_DT(UNIT) \ + (((UNIT) == 0) ? ((ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(0)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(1)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(2)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(3)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(4)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(5))) : \ + (((UNIT) == 1) ? ((ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(0)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(1)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(2)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(3)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(4)) | \ + (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(5))) : \ + 0)) + +/** Description of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_DESC "Priority register 1" + +/** Address of the PRIO1 register of one of the BUSIF Units. */ +#define ATON_BUSIF_PRIO1_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_PRIO1_OFFSET) + +/** Get the content of the PRIO1 register of one of the BUSIF Units. */ +#define ATON_BUSIF_PRIO1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO1_ADDR(UNIT))) + +/** Set the content of the PRIO1 register of one of the BUSIF Units. */ +#define ATON_BUSIF_PRIO1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of PRIO1 register. + * + * \return the description of PRIO1 register + */ + +static inline const int8_t *ATON_BUSIF_PRIO1_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_PRIO1_DESC; +} + + +/** + * Get the offset of the PRIO1 register. + * + * \return the offset of PRIO1 register + */ + +static inline uint32_t ATON_BUSIF_PRIO1_GetOffset(void) +{ + return ATON_BUSIF_PRIO1_OFFSET; +} + + +/** + * Get the address of the PRIO1 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO1 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of PRIO1 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_PRIO1_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_PRIO1_ADDR(instance); +} + + +/** + * Read the content of the PRIO1 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO1 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of PRIO1 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_PRIO1_Get(uint32_t instance) +{ + return ATON_BUSIF_PRIO1_GET(instance); +} + + +/** + * Write the content of the PRIO1 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO1 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_PRIO1_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_PRIO1_SET(instance, data); +} + + +/* ---------------------------------------------------------- BUSPORTN field of the PRIO1 register ---------------------------------------------------------- */ + +/** Description of one of the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_DESC "Priority mask 1 for busport N of the current instance (see the table for busports connections) [where N = ]" + +/** Number of BUSPORTN fields in the different instances of the PRIO1 register of the BUSIF Unit template. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_NUM(UNIT) \ + (((UNIT) == 0) ? 6 : \ + (((UNIT) == 1) ? 6 : 0)) +/** Displacement in bits among the various BUSPORTN fields (due to template specialization). */ +#define ATON_BUSIF_PRIO1_BUSPORTN_DISPL 1 + +/** Offset of one of the BUSPORTN fields of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_LSB(IDX) (0UL + (IDX) * ATON_BUSIF_PRIO1_BUSPORTN_DISPL) + +/** Size in bits of the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_W (1UL) + +/** Mask for retrieving the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_DT 0x0UL + +/** Access rights of the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_AC "RW" + +/** Check whether access to the BUSPORTN field of the PRIO1 register is secured or not. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_S 0 + +/** Check whether access to the BUSPORTN field of the PRIO1 register is privileged or not. */ +#define ATON_BUSIF_PRIO1_BUSPORTN_P 0 + +/** Read the content of one of the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_GET_BUSPORTN(REG, IDX) ATON_GET_FIELD(REG, ATON_BUSIF_PRIO1_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO1_BUSPORTN_W) + +/** Modify the content of one of the BUSPORTN field of the PRIO1 register. */ +#define ATON_BUSIF_PRIO1_SET_BUSPORTN(REG, IDX, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_PRIO1_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO1_BUSPORTN_W, DATA) + + +/** + * Get the description of the BUSPORTN field of PRIO1 register. + * + * \return the description of the BUSPORTN field of PRIO1 register + */ + +static inline const int8_t *ATON_BUSIF_PRIO1_BUSPORTN_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_PRIO1_BUSPORTN_DESC; +} + + +/** + * Read the content of one of the BUSPORTN field of the PRIO1 register. + * + * \param[in] reg is the value of the PRIO1 register + * + * \return the content of the BUSPORTN field having index \e idx and belonging to PRIO1 register + */ + +static inline uint32_t ATON_BUSIF_PRIO1_Get_BUSPORTN(uint32_t reg, uint32_t idx) +{ + return ATON_BUSIF_PRIO1_GET_BUSPORTN(reg, idx); +} + + +/** + * Write the content of one of the BUSPORTN field of the PRIO1 register. + * + * \param[in] reg is the value of the PRIO1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSPORTN field having index \e idx and belonging to PRIO1 register + */ + +static inline uint32_t ATON_BUSIF_PRIO1_Set_BUSPORTN(uint32_t reg, uint32_t idx, uint32_t data) +{ + return ATON_BUSIF_PRIO1_SET_BUSPORTN(reg, idx, data); +} + + +/* ******************************************************** PRIO2 register of one of the BUSIF Units ******************************************************** */ + +/** Offset of the PRIO2 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_PRIO2_OFFSET 0xcUL + +/** + * Get the reset value of the PRIO2 register of the BUSIF Unit. + * + * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') + * + * \return the reset value of the PRIO2 register of the BUSIF Unit + */ + +#define ATON_BUSIF_PRIO2_DT(UNIT) \ + (((UNIT) == 0) ? ((ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(0)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(1)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(2)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(3)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(4)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(5))) : \ + (((UNIT) == 1) ? ((ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(0)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(1)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(2)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(3)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(4)) | \ + (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(5))) : \ + 0)) + +/** Description of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_DESC "Priority register 2" + +/** Address of the PRIO2 register of one of the BUSIF Units. */ +#define ATON_BUSIF_PRIO2_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_PRIO2_OFFSET) + +/** Get the content of the PRIO2 register of one of the BUSIF Units. */ +#define ATON_BUSIF_PRIO2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO2_ADDR(UNIT))) + +/** Set the content of the PRIO2 register of one of the BUSIF Units. */ +#define ATON_BUSIF_PRIO2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of PRIO2 register. + * + * \return the description of PRIO2 register + */ + +static inline const int8_t *ATON_BUSIF_PRIO2_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_PRIO2_DESC; +} + + +/** + * Get the offset of the PRIO2 register. + * + * \return the offset of PRIO2 register + */ + +static inline uint32_t ATON_BUSIF_PRIO2_GetOffset(void) +{ + return ATON_BUSIF_PRIO2_OFFSET; +} + + +/** + * Get the address of the PRIO2 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO2 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of PRIO2 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_PRIO2_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_PRIO2_ADDR(instance); +} + + +/** + * Read the content of the PRIO2 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO2 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of PRIO2 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_PRIO2_Get(uint32_t instance) +{ + return ATON_BUSIF_PRIO2_GET(instance); +} + + +/** + * Write the content of the PRIO2 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO2 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_PRIO2_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_PRIO2_SET(instance, data); +} + + +/* ---------------------------------------------------------- BUSPORTN field of the PRIO2 register ---------------------------------------------------------- */ + +/** Description of one of the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_DESC "Priority mask 2 for busport N of the current instance (see the table for busports connections) [where N = ]" + +/** Number of BUSPORTN fields in the different instances of the PRIO2 register of the BUSIF Unit template. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_NUM(UNIT) \ + (((UNIT) == 0) ? 6 : \ + (((UNIT) == 1) ? 6 : 0)) +/** Displacement in bits among the various BUSPORTN fields (due to template specialization). */ +#define ATON_BUSIF_PRIO2_BUSPORTN_DISPL 1 + +/** Offset of one of the BUSPORTN fields of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_LSB(IDX) (0UL + (IDX) * ATON_BUSIF_PRIO2_BUSPORTN_DISPL) + +/** Size in bits of the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_W (1UL) + +/** Mask for retrieving the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_DT 0x0UL + +/** Access rights of the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_AC "RW" + +/** Check whether access to the BUSPORTN field of the PRIO2 register is secured or not. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_S 0 + +/** Check whether access to the BUSPORTN field of the PRIO2 register is privileged or not. */ +#define ATON_BUSIF_PRIO2_BUSPORTN_P 0 + +/** Read the content of one of the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_GET_BUSPORTN(REG, IDX) ATON_GET_FIELD(REG, ATON_BUSIF_PRIO2_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO2_BUSPORTN_W) + +/** Modify the content of one of the BUSPORTN field of the PRIO2 register. */ +#define ATON_BUSIF_PRIO2_SET_BUSPORTN(REG, IDX, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_PRIO2_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO2_BUSPORTN_W, DATA) + + +/** + * Get the description of the BUSPORTN field of PRIO2 register. + * + * \return the description of the BUSPORTN field of PRIO2 register + */ + +static inline const int8_t *ATON_BUSIF_PRIO2_BUSPORTN_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_PRIO2_BUSPORTN_DESC; +} + + +/** + * Read the content of one of the BUSPORTN field of the PRIO2 register. + * + * \param[in] reg is the value of the PRIO2 register + * + * \return the content of the BUSPORTN field having index \e idx and belonging to PRIO2 register + */ + +static inline uint32_t ATON_BUSIF_PRIO2_Get_BUSPORTN(uint32_t reg, uint32_t idx) +{ + return ATON_BUSIF_PRIO2_GET_BUSPORTN(reg, idx); +} + + +/** + * Write the content of one of the BUSPORTN field of the PRIO2 register. + * + * \param[in] reg is the value of the PRIO2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSPORTN field having index \e idx and belonging to PRIO2 register + */ + +static inline uint32_t ATON_BUSIF_PRIO2_Set_BUSPORTN(uint32_t reg, uint32_t idx, uint32_t data) +{ + return ATON_BUSIF_PRIO2_SET_BUSPORTN(reg, idx, data); +} + + +/* ********************************************************* ERR register of one of the BUSIF Units ********************************************************* */ + +/** Offset of the ERR register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_ERR_OFFSET 0x10UL + +/** + * Get the reset value of the ERR register of the BUSIF Unit. + * + * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') + * + * \return the reset value of the ERR register of the BUSIF Unit + */ + +#define ATON_BUSIF_ERR_DT(UNIT) \ + (((UNIT) == 0) ? ((ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(0)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(1)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(2)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(3)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(4)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(5))) : \ + (((UNIT) == 1) ? ((ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(0)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(1)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(2)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(3)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(4)) | \ + (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(5))) : \ + 0)) + +/** Description of the ERR register. */ +#define ATON_BUSIF_ERR_DESC "Error register" + +/** Address of the ERR register of one of the BUSIF Units. */ +#define ATON_BUSIF_ERR_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_ERR_OFFSET) + +/** Get the content of the ERR register of one of the BUSIF Units. */ +#define ATON_BUSIF_ERR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_ERR_ADDR(UNIT))) + +/** Set the content of the ERR register of one of the BUSIF Units. */ +#define ATON_BUSIF_ERR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_ERR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ERR register. + * + * \return the description of ERR register + */ + +static inline const int8_t *ATON_BUSIF_ERR_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_ERR_DESC; +} + + +/** + * Get the offset of the ERR register. + * + * \return the offset of ERR register + */ + +static inline uint32_t ATON_BUSIF_ERR_GetOffset(void) +{ + return ATON_BUSIF_ERR_OFFSET; +} + + +/** + * Get the address of the ERR register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the ERR register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of ERR register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_ERR_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_ERR_ADDR(instance); +} + + +/** + * Read the content of the ERR register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the ERR register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of ERR register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_ERR_Get(uint32_t instance) +{ + return ATON_BUSIF_ERR_GET(instance); +} + + +/** + * Write the content of the ERR register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the ERR register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_ERR_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_ERR_SET(instance, data); +} + + +/* ----------------------------------------------------------- BUSPORTN field of the ERR register ----------------------------------------------------------- */ + +/** Description of one of the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_BUSPORTN_DESC "Errors from AXI bus related to busport N of the current instance (see the table for busports connections). Writing 1 will clear the error (and the interrupt source), writing 0 has no effect. [where N = ]" + +/** Number of BUSPORTN fields in the different instances of the ERR register of the BUSIF Unit template. */ +#define ATON_BUSIF_ERR_BUSPORTN_NUM(UNIT) \ + (((UNIT) == 0) ? 6 : \ + (((UNIT) == 1) ? 6 : 0)) +/** Displacement in bits among the various BUSPORTN fields (due to template specialization). */ +#define ATON_BUSIF_ERR_BUSPORTN_DISPL 1 + +/** Offset of one of the BUSPORTN fields of the ERR register. */ +#define ATON_BUSIF_ERR_BUSPORTN_LSB(IDX) (0UL + (IDX) * ATON_BUSIF_ERR_BUSPORTN_DISPL) + +/** Size in bits of the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_BUSPORTN_W (1UL) + +/** Mask for retrieving the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_BUSPORTN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_BUSPORTN_DT 0x0UL + +/** Access rights of the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_BUSPORTN_AC "RW" + +/** Check whether access to the BUSPORTN field of the ERR register is secured or not. */ +#define ATON_BUSIF_ERR_BUSPORTN_S 0 + +/** Check whether access to the BUSPORTN field of the ERR register is privileged or not. */ +#define ATON_BUSIF_ERR_BUSPORTN_P 0 + +/** Read the content of one of the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_GET_BUSPORTN(REG, IDX) ATON_GET_FIELD(REG, ATON_BUSIF_ERR_BUSPORTN_LSB(IDX), ATON_BUSIF_ERR_BUSPORTN_W) + +/** Modify the content of one of the BUSPORTN field of the ERR register. */ +#define ATON_BUSIF_ERR_SET_BUSPORTN(REG, IDX, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_ERR_BUSPORTN_LSB(IDX), ATON_BUSIF_ERR_BUSPORTN_W, DATA) + + +/** + * Get the description of the BUSPORTN field of ERR register. + * + * \return the description of the BUSPORTN field of ERR register + */ + +static inline const int8_t *ATON_BUSIF_ERR_BUSPORTN_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_ERR_BUSPORTN_DESC; +} + + +/** + * Read the content of one of the BUSPORTN field of the ERR register. + * + * \param[in] reg is the value of the ERR register + * + * \return the content of the BUSPORTN field having index \e idx and belonging to ERR register + */ + +static inline uint32_t ATON_BUSIF_ERR_Get_BUSPORTN(uint32_t reg, uint32_t idx) +{ + return ATON_BUSIF_ERR_GET_BUSPORTN(reg, idx); +} + + +/** + * Write the content of one of the BUSPORTN field of the ERR register. + * + * \param[in] reg is the value of the ERR register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BUSPORTN field having index \e idx and belonging to ERR register + */ + +static inline uint32_t ATON_BUSIF_ERR_Set_BUSPORTN(uint32_t reg, uint32_t idx, uint32_t data) +{ + return ATON_BUSIF_ERR_SET_BUSPORTN(reg, idx, data); +} + + +/* ****************************************************** KEY0_31_0 register of one of the BUSIF Units ****************************************************** */ + +/** Offset of the KEY0_31_0 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_31_0_OFFSET 0x14UL + +/** Reset value of the KEY0_31_0 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_31_0_DT \ + (ATON_BUSIF_KEY0_31_0_REG_DT << ATON_BUSIF_KEY0_31_0_REG_LSB) + + + +/** Description of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_DESC "Encryption key 0 (bits 31:0)" + +/** Address of the KEY0_31_0 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_31_0_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_31_0_OFFSET) + +/** Get the content of the KEY0_31_0 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_31_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_31_0_ADDR(UNIT))) + +/** Set the content of the KEY0_31_0 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_31_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_31_0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY0_31_0 register. + * + * \return the description of KEY0_31_0 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_31_0_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_31_0_DESC; +} + + +/** + * Get the offset of the KEY0_31_0 register. + * + * \return the offset of KEY0_31_0 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_31_0_GetOffset(void) +{ + return ATON_BUSIF_KEY0_31_0_OFFSET; +} + + +/** + * Get the address of the KEY0_31_0 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_31_0 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY0_31_0 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_31_0_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY0_31_0_ADDR(instance); +} + + +/** + * Read the content of the KEY0_31_0 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_31_0 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY0_31_0 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_31_0_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY0_31_0_GET(instance); +} + + +/** + * Write the content of the KEY0_31_0 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_31_0 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY0_31_0_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY0_31_0_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the KEY0_31_0 register ----------------------------------------------------------- */ + +/** Description of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_REG_DESC "Encryption key 0 (bits 31:0)" + +/** Offset of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_REG_AC "W" + +/** Check whether access to the REG field of the KEY0_31_0 register is secured or not. */ +#define ATON_BUSIF_KEY0_31_0_REG_S 0 + +/** Check whether access to the REG field of the KEY0_31_0 register is privileged or not. */ +#define ATON_BUSIF_KEY0_31_0_REG_P 0 + +/** Read the content of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_31_0_REG_LSB, ATON_BUSIF_KEY0_31_0_REG_W) + +/** Modify the content of the REG field of the KEY0_31_0 register. */ +#define ATON_BUSIF_KEY0_31_0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_31_0_REG_LSB, ATON_BUSIF_KEY0_31_0_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY0_31_0 register. + * + * \return the description of the REG field of KEY0_31_0 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_31_0_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_31_0_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY0_31_0 register. + * + * \param[in] reg is the value of the KEY0_31_0 register + * + * \return the content of the REG field belonging to KEY0_31_0 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_31_0_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY0_31_0_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY0_31_0 register. + * + * \param[in] reg is the value of the KEY0_31_0 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY0_31_0 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_31_0_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY0_31_0_SET_REG(reg, data); +} + + +/* ***************************************************** KEY0_63_32 register of one of the BUSIF Units ****************************************************** */ + +/** Offset of the KEY0_63_32 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_63_32_OFFSET 0x18UL + +/** Reset value of the KEY0_63_32 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_63_32_DT \ + (ATON_BUSIF_KEY0_63_32_REG_DT << ATON_BUSIF_KEY0_63_32_REG_LSB) + + + +/** Description of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_DESC "Encryption key 0 (bits 63:32)" + +/** Address of the KEY0_63_32 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_63_32_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_63_32_OFFSET) + +/** Get the content of the KEY0_63_32 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_63_32_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_63_32_ADDR(UNIT))) + +/** Set the content of the KEY0_63_32 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_63_32_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_63_32_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY0_63_32 register. + * + * \return the description of KEY0_63_32 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_63_32_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_63_32_DESC; +} + + +/** + * Get the offset of the KEY0_63_32 register. + * + * \return the offset of KEY0_63_32 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_63_32_GetOffset(void) +{ + return ATON_BUSIF_KEY0_63_32_OFFSET; +} + + +/** + * Get the address of the KEY0_63_32 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_63_32 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY0_63_32 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_63_32_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY0_63_32_ADDR(instance); +} + + +/** + * Read the content of the KEY0_63_32 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_63_32 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY0_63_32 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_63_32_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY0_63_32_GET(instance); +} + + +/** + * Write the content of the KEY0_63_32 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_63_32 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY0_63_32_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY0_63_32_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the KEY0_63_32 register ---------------------------------------------------------- */ + +/** Description of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_REG_DESC "Encryption key 0 (bits 63:32)" + +/** Offset of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_REG_AC "W" + +/** Check whether access to the REG field of the KEY0_63_32 register is secured or not. */ +#define ATON_BUSIF_KEY0_63_32_REG_S 0 + +/** Check whether access to the REG field of the KEY0_63_32 register is privileged or not. */ +#define ATON_BUSIF_KEY0_63_32_REG_P 0 + +/** Read the content of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_63_32_REG_LSB, ATON_BUSIF_KEY0_63_32_REG_W) + +/** Modify the content of the REG field of the KEY0_63_32 register. */ +#define ATON_BUSIF_KEY0_63_32_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_63_32_REG_LSB, ATON_BUSIF_KEY0_63_32_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY0_63_32 register. + * + * \return the description of the REG field of KEY0_63_32 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_63_32_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_63_32_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY0_63_32 register. + * + * \param[in] reg is the value of the KEY0_63_32 register + * + * \return the content of the REG field belonging to KEY0_63_32 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_63_32_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY0_63_32_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY0_63_32 register. + * + * \param[in] reg is the value of the KEY0_63_32 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY0_63_32 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_63_32_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY0_63_32_SET_REG(reg, data); +} + + +/* ***************************************************** KEY0_95_64 register of one of the BUSIF Units ****************************************************** */ + +/** Offset of the KEY0_95_64 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_95_64_OFFSET 0x1cUL + +/** Reset value of the KEY0_95_64 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_95_64_DT \ + (ATON_BUSIF_KEY0_95_64_REG_DT << ATON_BUSIF_KEY0_95_64_REG_LSB) + + + +/** Description of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_DESC "Encryption key 0 (bits 95:64)" + +/** Address of the KEY0_95_64 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_95_64_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_95_64_OFFSET) + +/** Get the content of the KEY0_95_64 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_95_64_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_95_64_ADDR(UNIT))) + +/** Set the content of the KEY0_95_64 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_95_64_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_95_64_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY0_95_64 register. + * + * \return the description of KEY0_95_64 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_95_64_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_95_64_DESC; +} + + +/** + * Get the offset of the KEY0_95_64 register. + * + * \return the offset of KEY0_95_64 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_95_64_GetOffset(void) +{ + return ATON_BUSIF_KEY0_95_64_OFFSET; +} + + +/** + * Get the address of the KEY0_95_64 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_95_64 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY0_95_64 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_95_64_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY0_95_64_ADDR(instance); +} + + +/** + * Read the content of the KEY0_95_64 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_95_64 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY0_95_64 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_95_64_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY0_95_64_GET(instance); +} + + +/** + * Write the content of the KEY0_95_64 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_95_64 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY0_95_64_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY0_95_64_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the KEY0_95_64 register ---------------------------------------------------------- */ + +/** Description of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_REG_DESC "Encryption key 0 (bits 95:64)" + +/** Offset of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_REG_AC "W" + +/** Check whether access to the REG field of the KEY0_95_64 register is secured or not. */ +#define ATON_BUSIF_KEY0_95_64_REG_S 0 + +/** Check whether access to the REG field of the KEY0_95_64 register is privileged or not. */ +#define ATON_BUSIF_KEY0_95_64_REG_P 0 + +/** Read the content of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_95_64_REG_LSB, ATON_BUSIF_KEY0_95_64_REG_W) + +/** Modify the content of the REG field of the KEY0_95_64 register. */ +#define ATON_BUSIF_KEY0_95_64_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_95_64_REG_LSB, ATON_BUSIF_KEY0_95_64_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY0_95_64 register. + * + * \return the description of the REG field of KEY0_95_64 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_95_64_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_95_64_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY0_95_64 register. + * + * \param[in] reg is the value of the KEY0_95_64 register + * + * \return the content of the REG field belonging to KEY0_95_64 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_95_64_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY0_95_64_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY0_95_64 register. + * + * \param[in] reg is the value of the KEY0_95_64 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY0_95_64 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_95_64_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY0_95_64_SET_REG(reg, data); +} + + +/* ***************************************************** KEY0_127_96 register of one of the BUSIF Units ***************************************************** */ + +/** Offset of the KEY0_127_96 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_127_96_OFFSET 0x20UL + +/** Reset value of the KEY0_127_96 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY0_127_96_DT \ + (ATON_BUSIF_KEY0_127_96_REG_DT << ATON_BUSIF_KEY0_127_96_REG_LSB) + + + +/** Description of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_DESC "Encryption key 0 (bits 127:96)" + +/** Address of the KEY0_127_96 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_127_96_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_127_96_OFFSET) + +/** Get the content of the KEY0_127_96 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_127_96_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_127_96_ADDR(UNIT))) + +/** Set the content of the KEY0_127_96 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY0_127_96_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_127_96_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY0_127_96 register. + * + * \return the description of KEY0_127_96 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_127_96_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_127_96_DESC; +} + + +/** + * Get the offset of the KEY0_127_96 register. + * + * \return the offset of KEY0_127_96 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_127_96_GetOffset(void) +{ + return ATON_BUSIF_KEY0_127_96_OFFSET; +} + + +/** + * Get the address of the KEY0_127_96 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_127_96 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY0_127_96 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_127_96_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY0_127_96_ADDR(instance); +} + + +/** + * Read the content of the KEY0_127_96 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_127_96 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY0_127_96 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY0_127_96_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY0_127_96_GET(instance); +} + + +/** + * Write the content of the KEY0_127_96 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_127_96 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY0_127_96_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY0_127_96_SET(instance, data); +} + + +/* --------------------------------------------------------- REG field of the KEY0_127_96 register ---------------------------------------------------------- */ + +/** Description of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_REG_DESC "Encryption key 0 (bits 127:96)" + +/** Offset of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_REG_AC "W" + +/** Check whether access to the REG field of the KEY0_127_96 register is secured or not. */ +#define ATON_BUSIF_KEY0_127_96_REG_S 0 + +/** Check whether access to the REG field of the KEY0_127_96 register is privileged or not. */ +#define ATON_BUSIF_KEY0_127_96_REG_P 0 + +/** Read the content of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_127_96_REG_LSB, ATON_BUSIF_KEY0_127_96_REG_W) + +/** Modify the content of the REG field of the KEY0_127_96 register. */ +#define ATON_BUSIF_KEY0_127_96_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_127_96_REG_LSB, ATON_BUSIF_KEY0_127_96_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY0_127_96 register. + * + * \return the description of the REG field of KEY0_127_96 register + */ + +static inline const int8_t *ATON_BUSIF_KEY0_127_96_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY0_127_96_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY0_127_96 register. + * + * \param[in] reg is the value of the KEY0_127_96 register + * + * \return the content of the REG field belonging to KEY0_127_96 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_127_96_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY0_127_96_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY0_127_96 register. + * + * \param[in] reg is the value of the KEY0_127_96 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY0_127_96 register + */ + +static inline uint32_t ATON_BUSIF_KEY0_127_96_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY0_127_96_SET_REG(reg, data); +} + + +/* ****************************************************** KEY1_31_0 register of one of the BUSIF Units ****************************************************** */ + +/** Offset of the KEY1_31_0 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_31_0_OFFSET 0x24UL + +/** Reset value of the KEY1_31_0 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_31_0_DT \ + (ATON_BUSIF_KEY1_31_0_REG_DT << ATON_BUSIF_KEY1_31_0_REG_LSB) + + + +/** Description of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_DESC "Encryption key 1 (bits 31:0)" + +/** Address of the KEY1_31_0 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_31_0_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_31_0_OFFSET) + +/** Get the content of the KEY1_31_0 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_31_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_31_0_ADDR(UNIT))) + +/** Set the content of the KEY1_31_0 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_31_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_31_0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY1_31_0 register. + * + * \return the description of KEY1_31_0 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_31_0_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_31_0_DESC; +} + + +/** + * Get the offset of the KEY1_31_0 register. + * + * \return the offset of KEY1_31_0 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_31_0_GetOffset(void) +{ + return ATON_BUSIF_KEY1_31_0_OFFSET; +} + + +/** + * Get the address of the KEY1_31_0 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_31_0 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY1_31_0 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_31_0_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY1_31_0_ADDR(instance); +} + + +/** + * Read the content of the KEY1_31_0 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_31_0 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY1_31_0 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_31_0_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY1_31_0_GET(instance); +} + + +/** + * Write the content of the KEY1_31_0 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_31_0 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY1_31_0_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY1_31_0_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the KEY1_31_0 register ----------------------------------------------------------- */ + +/** Description of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_REG_DESC "Encryption key 1 (bits 31:0)" + +/** Offset of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_REG_AC "W" + +/** Check whether access to the REG field of the KEY1_31_0 register is secured or not. */ +#define ATON_BUSIF_KEY1_31_0_REG_S 0 + +/** Check whether access to the REG field of the KEY1_31_0 register is privileged or not. */ +#define ATON_BUSIF_KEY1_31_0_REG_P 0 + +/** Read the content of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_31_0_REG_LSB, ATON_BUSIF_KEY1_31_0_REG_W) + +/** Modify the content of the REG field of the KEY1_31_0 register. */ +#define ATON_BUSIF_KEY1_31_0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_31_0_REG_LSB, ATON_BUSIF_KEY1_31_0_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY1_31_0 register. + * + * \return the description of the REG field of KEY1_31_0 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_31_0_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_31_0_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY1_31_0 register. + * + * \param[in] reg is the value of the KEY1_31_0 register + * + * \return the content of the REG field belonging to KEY1_31_0 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_31_0_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY1_31_0_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY1_31_0 register. + * + * \param[in] reg is the value of the KEY1_31_0 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY1_31_0 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_31_0_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY1_31_0_SET_REG(reg, data); +} + + +/* ***************************************************** KEY1_63_32 register of one of the BUSIF Units ****************************************************** */ + +/** Offset of the KEY1_63_32 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_63_32_OFFSET 0x28UL + +/** Reset value of the KEY1_63_32 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_63_32_DT \ + (ATON_BUSIF_KEY1_63_32_REG_DT << ATON_BUSIF_KEY1_63_32_REG_LSB) + + + +/** Description of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_DESC "Encryption key 1 (bits 63:32)" + +/** Address of the KEY1_63_32 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_63_32_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_63_32_OFFSET) + +/** Get the content of the KEY1_63_32 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_63_32_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_63_32_ADDR(UNIT))) + +/** Set the content of the KEY1_63_32 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_63_32_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_63_32_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY1_63_32 register. + * + * \return the description of KEY1_63_32 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_63_32_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_63_32_DESC; +} + + +/** + * Get the offset of the KEY1_63_32 register. + * + * \return the offset of KEY1_63_32 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_63_32_GetOffset(void) +{ + return ATON_BUSIF_KEY1_63_32_OFFSET; +} + + +/** + * Get the address of the KEY1_63_32 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_63_32 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY1_63_32 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_63_32_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY1_63_32_ADDR(instance); +} + + +/** + * Read the content of the KEY1_63_32 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_63_32 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY1_63_32 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_63_32_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY1_63_32_GET(instance); +} + + +/** + * Write the content of the KEY1_63_32 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_63_32 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY1_63_32_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY1_63_32_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the KEY1_63_32 register ---------------------------------------------------------- */ + +/** Description of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_REG_DESC "Encryption key 1 (bits 63:32)" + +/** Offset of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_REG_AC "W" + +/** Check whether access to the REG field of the KEY1_63_32 register is secured or not. */ +#define ATON_BUSIF_KEY1_63_32_REG_S 0 + +/** Check whether access to the REG field of the KEY1_63_32 register is privileged or not. */ +#define ATON_BUSIF_KEY1_63_32_REG_P 0 + +/** Read the content of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_63_32_REG_LSB, ATON_BUSIF_KEY1_63_32_REG_W) + +/** Modify the content of the REG field of the KEY1_63_32 register. */ +#define ATON_BUSIF_KEY1_63_32_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_63_32_REG_LSB, ATON_BUSIF_KEY1_63_32_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY1_63_32 register. + * + * \return the description of the REG field of KEY1_63_32 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_63_32_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_63_32_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY1_63_32 register. + * + * \param[in] reg is the value of the KEY1_63_32 register + * + * \return the content of the REG field belonging to KEY1_63_32 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_63_32_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY1_63_32_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY1_63_32 register. + * + * \param[in] reg is the value of the KEY1_63_32 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY1_63_32 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_63_32_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY1_63_32_SET_REG(reg, data); +} + + +/* ***************************************************** KEY1_95_64 register of one of the BUSIF Units ****************************************************** */ + +/** Offset of the KEY1_95_64 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_95_64_OFFSET 0x2cUL + +/** Reset value of the KEY1_95_64 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_95_64_DT \ + (ATON_BUSIF_KEY1_95_64_REG_DT << ATON_BUSIF_KEY1_95_64_REG_LSB) + + + +/** Description of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_DESC "Encryption key 1 (bits 95:64)" + +/** Address of the KEY1_95_64 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_95_64_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_95_64_OFFSET) + +/** Get the content of the KEY1_95_64 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_95_64_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_95_64_ADDR(UNIT))) + +/** Set the content of the KEY1_95_64 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_95_64_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_95_64_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY1_95_64 register. + * + * \return the description of KEY1_95_64 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_95_64_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_95_64_DESC; +} + + +/** + * Get the offset of the KEY1_95_64 register. + * + * \return the offset of KEY1_95_64 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_95_64_GetOffset(void) +{ + return ATON_BUSIF_KEY1_95_64_OFFSET; +} + + +/** + * Get the address of the KEY1_95_64 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_95_64 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY1_95_64 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_95_64_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY1_95_64_ADDR(instance); +} + + +/** + * Read the content of the KEY1_95_64 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_95_64 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY1_95_64 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_95_64_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY1_95_64_GET(instance); +} + + +/** + * Write the content of the KEY1_95_64 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_95_64 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY1_95_64_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY1_95_64_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the KEY1_95_64 register ---------------------------------------------------------- */ + +/** Description of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_REG_DESC "Encryption key 1 (bits 95:64)" + +/** Offset of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_REG_AC "W" + +/** Check whether access to the REG field of the KEY1_95_64 register is secured or not. */ +#define ATON_BUSIF_KEY1_95_64_REG_S 0 + +/** Check whether access to the REG field of the KEY1_95_64 register is privileged or not. */ +#define ATON_BUSIF_KEY1_95_64_REG_P 0 + +/** Read the content of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_95_64_REG_LSB, ATON_BUSIF_KEY1_95_64_REG_W) + +/** Modify the content of the REG field of the KEY1_95_64 register. */ +#define ATON_BUSIF_KEY1_95_64_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_95_64_REG_LSB, ATON_BUSIF_KEY1_95_64_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY1_95_64 register. + * + * \return the description of the REG field of KEY1_95_64 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_95_64_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_95_64_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY1_95_64 register. + * + * \param[in] reg is the value of the KEY1_95_64 register + * + * \return the content of the REG field belonging to KEY1_95_64 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_95_64_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY1_95_64_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY1_95_64 register. + * + * \param[in] reg is the value of the KEY1_95_64 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY1_95_64 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_95_64_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY1_95_64_SET_REG(reg, data); +} + + +/* ***************************************************** KEY1_127_96 register of one of the BUSIF Units ***************************************************** */ + +/** Offset of the KEY1_127_96 register from the base address of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_127_96_OFFSET 0x30UL + +/** Reset value of the KEY1_127_96 register of the BUSIF Unit. */ +#define ATON_BUSIF_KEY1_127_96_DT \ + (ATON_BUSIF_KEY1_127_96_REG_DT << ATON_BUSIF_KEY1_127_96_REG_LSB) + + + +/** Description of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_DESC "Encryption key 1 (bits 127:96)" + +/** Address of the KEY1_127_96 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_127_96_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_127_96_OFFSET) + +/** Get the content of the KEY1_127_96 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_127_96_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_127_96_ADDR(UNIT))) + +/** Set the content of the KEY1_127_96 register of one of the BUSIF Units. */ +#define ATON_BUSIF_KEY1_127_96_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_127_96_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KEY1_127_96 register. + * + * \return the description of KEY1_127_96 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_127_96_GetDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_127_96_DESC; +} + + +/** + * Get the offset of the KEY1_127_96 register. + * + * \return the offset of KEY1_127_96 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_127_96_GetOffset(void) +{ + return ATON_BUSIF_KEY1_127_96_OFFSET; +} + + +/** + * Get the address of the KEY1_127_96 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_127_96 register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of KEY1_127_96 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_127_96_GetAddr(uint32_t instance) +{ + return ATON_BUSIF_KEY1_127_96_ADDR(instance); +} + + +/** + * Read the content of the KEY1_127_96 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_127_96 register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of KEY1_127_96 register belonging to Unit having index \e instance among the BUSIF Units + */ + +static inline uint32_t ATON_BUSIF_KEY1_127_96_Get(uint32_t instance) +{ + return ATON_BUSIF_KEY1_127_96_GET(instance); +} + + +/** + * Write the content of the KEY1_127_96 register. + * + * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_127_96 register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_BUSIF_KEY1_127_96_Set(uint32_t instance, uint32_t data) +{ + ATON_BUSIF_KEY1_127_96_SET(instance, data); +} + + +/* --------------------------------------------------------- REG field of the KEY1_127_96 register ---------------------------------------------------------- */ + +/** Description of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_REG_DESC "Encryption key 1 (bits 127:96)" + +/** Offset of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_REG_LSB 0UL + +/** Size in bits of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_REG_W (32UL) + +/** Mask for retrieving the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_REG_DT 0x0UL + +/** Access rights of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_REG_AC "W" + +/** Check whether access to the REG field of the KEY1_127_96 register is secured or not. */ +#define ATON_BUSIF_KEY1_127_96_REG_S 0 + +/** Check whether access to the REG field of the KEY1_127_96 register is privileged or not. */ +#define ATON_BUSIF_KEY1_127_96_REG_P 0 + +/** Read the content of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_127_96_REG_LSB, ATON_BUSIF_KEY1_127_96_REG_W) + +/** Modify the content of the REG field of the KEY1_127_96 register. */ +#define ATON_BUSIF_KEY1_127_96_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_127_96_REG_LSB, ATON_BUSIF_KEY1_127_96_REG_W, DATA) + + +/** + * Get the description of the REG field of KEY1_127_96 register. + * + * \return the description of the REG field of KEY1_127_96 register + */ + +static inline const int8_t *ATON_BUSIF_KEY1_127_96_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_BUSIF_KEY1_127_96_REG_DESC; +} + + +/** + * Read the content of the REG field of the KEY1_127_96 register. + * + * \param[in] reg is the value of the KEY1_127_96 register + * + * \return the content of the REG field belonging to KEY1_127_96 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_127_96_Get_REG(uint32_t reg) +{ + return ATON_BUSIF_KEY1_127_96_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the KEY1_127_96 register. + * + * \param[in] reg is the value of the KEY1_127_96 register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to KEY1_127_96 register + */ + +static inline uint32_t ATON_BUSIF_KEY1_127_96_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_BUSIF_KEY1_127_96_SET_REG(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* STRENG Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of STRENG Unit instances. */ +#define ATON_STRENG_NUM 10 + +/** + * \name Structures, macros and functions of the STRENG Units + */ +/*@{*/ + +/** + * Registers of the STRENG Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e ADDR register (Source/destination address). */ + uint32_t ADDR; + + /** \e FSIZE register (Frame size). */ + uint32_t FSIZE; + + /** \e DEPTH register (Depth for batch mode). */ + uint32_t DEPTH; + + /** \e STRD register (Stride). */ + uint32_t STRD; + + /** \e FOFFSET register (Frame offset within frame repetition loop). */ + uint32_t FOFFSET; + + /** \e FRAME_RPT register (Number of frames to loop on). */ + uint32_t FRAME_RPT; + + /** \e FRPTOFF register (Frame offset between frame repetition loops). */ + uint32_t FRPTOFF; + + /** \e POS register (Position). */ + uint32_t POS; + + /** \e EVENT register (Event). */ + uint32_t EVENT; + + /** \e STOPTAG register (RAW file stop tag). */ + uint32_t STOPTAG; + + /** \e LIMITEN register (Limiter enables). */ + uint32_t LIMITEN; + + /** \e LIMIT register (Limiter). */ + uint32_t LIMIT; + + /** \e LIMITADDR register (Limiter address). */ + uint32_t LIMITADDR; + + /** \e IRQ register (Events and interrupt enable). */ + uint32_t IRQ; + + /** \e ENCR_LSB register (Encryption ID LSB (RO when CTRL.RUNNING)). */ + uint32_t ENCR_LSB; + + /** \e ENCR_MSB register (Encryption ID MSB (RO when CTRL.RUNNING)). */ + uint32_t ENCR_MSB; + + /** \e CID_CACHE register (Compartment ID / Cache register (RO when CTRL.RUNNING)). */ + uint32_t CID_CACHE; + + /** \e EXTSYNC register (External triggers 1st control register (RO when CTRL.RUNNING)). */ + uint32_t EXTSYNC; + + /** \e EXTSYNC2 register (External triggers 2st control register (RO when CTRL.RUNNING)). */ + uint32_t EXTSYNC2; + + /** \e DESCRADDR register (Descriptor fetch address). */ + uint32_t DESCRADDR; + + /** \e LASTADDR register (Address of the last transaction on master bus IF). */ + uint32_t LASTADDR; + + /** \e DEPTHCNT register (Current processed sub-pixel (1 to depth size)). */ + uint32_t DEPTHCNT; + + /** \e PIXCNT register (Current processed pixel (1 to line width)). */ + uint32_t PIXCNT; + + /** \e LINECNT register (Current processed line (1 to frame height)). */ + uint32_t LINECNT; + + /** \e FCNT register (Frame counter). */ + uint32_t FCNT; + +} ATON_STRENG_t; + + +/** Return the pointer to one of the STRENG Units. */ +#define ATON_STRENG(UNIT) ((ATON_STRENG_t *)(intptr_t)ATON_STRENG_BASE(UNIT)) + + +/** Name of one of the STRENG Units. */ +#define ATON_STRENG_NAME(UNIT) \ + (((UNIT) == 0) ? "STRENG0" : \ + (((UNIT) == 1) ? "STRENG1" : \ + (((UNIT) == 2) ? "STRENG2" : \ + (((UNIT) == 3) ? "STRENG3" : \ + (((UNIT) == 4) ? "STRENG4" : \ + (((UNIT) == 5) ? "STRENG5" : \ + (((UNIT) == 6) ? "STRENG6" : \ + (((UNIT) == 7) ? "STRENG7" : \ + (((UNIT) == 8) ? "STRENG8" : \ + (((UNIT) == 9) ? "STRENG9" : "")))))))))) + + +/** Version of the STRENG Units. */ +#define ATON_STRENG_VERSION "5.0" + + +/** Description of one of the STRENG Units. */ +#define ATON_STRENG_DESC(UNIT) \ + (((UNIT) == 0) ? "Stream Engine 0" : \ + (((UNIT) == 1) ? "Stream Engine 1" : \ + (((UNIT) == 2) ? "Stream Engine 2" : \ + (((UNIT) == 3) ? "Stream Engine 3" : \ + (((UNIT) == 4) ? "Stream Engine 4" : \ + (((UNIT) == 5) ? "Stream Engine 5" : \ + (((UNIT) == 6) ? "Stream Engine 6" : \ + (((UNIT) == 7) ? "Stream Engine 7" : \ + (((UNIT) == 8) ? "Stream Engine 8" : \ + (((UNIT) == 9) ? "Stream Engine 9" : "")))))))))) + + +/** Base address of one of the STRENG Units. */ +#define ATON_STRENG_BASE(UNIT) \ + (ATON_BASE + 0x5000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the STRENG Units. */ +#define ATON_STRENG_SIZE 0x1000UL + + +/** + * Get the name of one of the STRENG Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 10<\em>) + * + * \return the name of Unit having index \e instance among the STRENG Units + */ + +static inline const int8_t *ATON_STRENG_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"STRENG0"; + break; + + case 1: + str = (const int8_t *)"STRENG1"; + break; + + case 2: + str = (const int8_t *)"STRENG2"; + break; + + case 3: + str = (const int8_t *)"STRENG3"; + break; + + case 4: + str = (const int8_t *)"STRENG4"; + break; + + case 5: + str = (const int8_t *)"STRENG5"; + break; + + case 6: + str = (const int8_t *)"STRENG6"; + break; + + case 7: + str = (const int8_t *)"STRENG7"; + break; + + case 8: + str = (const int8_t *)"STRENG8"; + break; + + case 9: + str = (const int8_t *)"STRENG9"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the STRENG Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 10<\em>) + * + * \return the description of Unit having index \e instance among the STRENG Units + */ + +static inline const int8_t *ATON_STRENG_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Stream Engine 0"; + break; + + case 1: + str = (const int8_t *)"Stream Engine 1"; + break; + + case 2: + str = (const int8_t *)"Stream Engine 2"; + break; + + case 3: + str = (const int8_t *)"Stream Engine 3"; + break; + + case 4: + str = (const int8_t *)"Stream Engine 4"; + break; + + case 5: + str = (const int8_t *)"Stream Engine 5"; + break; + + case 6: + str = (const int8_t *)"Stream Engine 6"; + break; + + case 7: + str = (const int8_t *)"Stream Engine 7"; + break; + + case 8: + str = (const int8_t *)"Stream Engine 8"; + break; + + case 9: + str = (const int8_t *)"Stream Engine 9"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the STRENG Units. + * + * \return the version of the STRENG Units + */ + +static inline const int8_t *ATON_STRENG_GetVersion(void) +{ + return (const int8_t *)ATON_STRENG_VERSION; +} + + +/** + * Get the base address of one of the STRENG Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 10<\em>) + * + * \return the base address of Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_GetBase(uint32_t instance) +{ + return ATON_STRENG_BASE(instance); +} + + +/** + * Get the size in bytes of the STRENG Units. + * + * \return the size in bytes of the STRENG Units + */ + +static inline uint32_t ATON_STRENG_GetSize(void) +{ + return ATON_STRENG_SIZE; +} + + +/* ******************************************************** CTRL register of one of the STRENG Units ******************************************************** */ + +/** Offset of the CTRL register from the base address of the STRENG Unit. */ +#define ATON_STRENG_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the STRENG Unit. */ +#define ATON_STRENG_CTRL_DT \ + (ATON_STRENG_CTRL_EN_DT << ATON_STRENG_CTRL_EN_LSB) | \ + (ATON_STRENG_CTRL_CLR_DT << ATON_STRENG_CTRL_CLR_LSB) | \ + (ATON_STRENG_CTRL_SINGLE_DT << ATON_STRENG_CTRL_SINGLE_LSB) | \ + (ATON_STRENG_CTRL_DIR_DT << ATON_STRENG_CTRL_DIR_LSB) | \ + (ATON_STRENG_CTRL_NOINC_DT << ATON_STRENG_CTRL_NOINC_LSB) | \ + (ATON_STRENG_CTRL_ISTART_DT << ATON_STRENG_CTRL_ISTART_LSB) | \ + (ATON_STRENG_CTRL_SUBSAMPLE_DT << ATON_STRENG_CTRL_SUBSAMPLE_LSB) | \ + (ATON_STRENG_CTRL_CONT_DT << ATON_STRENG_CTRL_CONT_LSB) | \ + (ATON_STRENG_CTRL_RAW_DT << ATON_STRENG_CTRL_RAW_LSB) | \ + (ATON_STRENG_CTRL_RAW_OUT_DT << ATON_STRENG_CTRL_RAW_OUT_LSB) | \ + (ATON_STRENG_CTRL_DESCR_DT << ATON_STRENG_CTRL_DESCR_LSB) | \ + (ATON_STRENG_CTRL_NOBLK_DT << ATON_STRENG_CTRL_NOBLK_LSB) | \ + (ATON_STRENG_CTRL_ROUND_DT << ATON_STRENG_CTRL_ROUND_LSB) | \ + (ATON_STRENG_CTRL_BEFORCE_DT << ATON_STRENG_CTRL_BEFORCE_LSB) | \ + (ATON_STRENG_CTRL_LSBMODE_DT << ATON_STRENG_CTRL_LSBMODE_LSB) | \ + (ATON_STRENG_CTRL_SIGNEXT_DT << ATON_STRENG_CTRL_SIGNEXT_LSB) | \ + (ATON_STRENG_CTRL_SIZE0_DT << ATON_STRENG_CTRL_SIZE0_LSB) | \ + (ATON_STRENG_CTRL_SIZE1_DT << ATON_STRENG_CTRL_SIZE1_LSB) | \ + (ATON_STRENG_CTRL_SIZE2_DT << ATON_STRENG_CTRL_SIZE2_LSB) | \ + (ATON_STRENG_CTRL_SERDES_DT << ATON_STRENG_CTRL_SERDES_LSB) | \ + (ATON_STRENG_CTRL_CONFCLR_DT << ATON_STRENG_CTRL_CONFCLR_LSB) | \ + (ATON_STRENG_CTRL_RUNNING_DT << ATON_STRENG_CTRL_RUNNING_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_STRENG_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the STRENG Units. */ +#define ATON_STRENG_CTRL_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the STRENG Units. */ +#define ATON_STRENG_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the STRENG Units. */ +#define ATON_STRENG_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_GetOffset(void) +{ + return ATON_STRENG_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CTRL register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_CTRL_GetAddr(uint32_t instance) +{ + return ATON_STRENG_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_CTRL_Get(uint32_t instance) +{ + return ATON_STRENG_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CTRL register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_EN_DESC "Enable the Stream Engine" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_EN_LSB, ATON_STRENG_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_EN_LSB, ATON_STRENG_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_EN(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_CLR_LSB, ATON_STRENG_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_CLR_LSB, ATON_STRENG_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- SINGLE field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SINGLE_DESC "Stop after one frame (RO when CTRL.RUNNING)" + +/** Offset of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SINGLE_LSB 2UL + +/** Size in bits of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SINGLE_W (1UL) + +/** Mask for retrieving the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SINGLE_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SINGLE_DT 0x0UL + +/** Access rights of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SINGLE_AC "RW" + +/** Check whether access to the SINGLE field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SINGLE_S 0 + +/** Check whether access to the SINGLE field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SINGLE_P 0 + +/** Read the content of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SINGLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SINGLE_LSB, ATON_STRENG_CTRL_SINGLE_W) + +/** Modify the content of the SINGLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SINGLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SINGLE_LSB, ATON_STRENG_CTRL_SINGLE_W, DATA) + + +/** + * Get the description of the SINGLE field of CTRL register. + * + * \return the description of the SINGLE field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SINGLE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SINGLE_DESC; +} + + +/** + * Read the content of the SINGLE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SINGLE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SINGLE(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SINGLE(reg); +} + + +/** + * Write the content of the SINGLE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SINGLE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SINGLE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SINGLE(reg, data); +} + + +/* ------------------------------------------------------------- DIR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DIR_DESC "Direction (RO when CTRL.RUNNING)" + +/** Offset of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DIR_LSB 3UL + +/** Size in bits of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DIR_W (1UL) + +/** Mask for retrieving the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DIR_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DIR_DT 0x0UL + +/** Access rights of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DIR_AC "RW" + +/** Check whether access to the DIR field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_DIR_S 0 + +/** Check whether access to the DIR field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_DIR_P 0 + +/** Read the content of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_DIR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_DIR_LSB, ATON_STRENG_CTRL_DIR_W) + +/** Modify the content of the DIR field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_DIR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_DIR_LSB, ATON_STRENG_CTRL_DIR_W, DATA) + + +/** + * Get the description of the DIR field of CTRL register. + * + * \return the description of the DIR field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_DIR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_DIR_DESC; +} + + +/** + * Read the content of the DIR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DIR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_DIR(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_DIR(reg); +} + + +/** + * Write the content of the DIR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DIR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_DIR(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_DIR(reg, data); +} + + +/* ------------------------------------------------------------ NOINC field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOINC_DESC "Do not increment address (RO when CTRL.RUNNING)" + +/** Offset of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOINC_LSB 4UL + +/** Size in bits of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOINC_W (1UL) + +/** Mask for retrieving the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOINC_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOINC_DT 0x0UL + +/** Access rights of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOINC_AC "RW" + +/** Check whether access to the NOINC field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_NOINC_S 0 + +/** Check whether access to the NOINC field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_NOINC_P 0 + +/** Read the content of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_NOINC(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_NOINC_LSB, ATON_STRENG_CTRL_NOINC_W) + +/** Modify the content of the NOINC field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_NOINC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_NOINC_LSB, ATON_STRENG_CTRL_NOINC_W, DATA) + + +/** + * Get the description of the NOINC field of CTRL register. + * + * \return the description of the NOINC field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_NOINC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_NOINC_DESC; +} + + +/** + * Read the content of the NOINC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the NOINC field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_NOINC(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_NOINC(reg); +} + + +/** + * Write the content of the NOINC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the NOINC field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_NOINC(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_NOINC(reg, data); +} + + +/* ----------------------------------------------------------- ISTART field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_ISTART_DESC "Do not wait for frame start (RO when CTRL.RUNNING)" + +/** Offset of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_ISTART_LSB 5UL + +/** Size in bits of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_ISTART_W (1UL) + +/** Mask for retrieving the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_ISTART_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_ISTART_DT 0x0UL + +/** Access rights of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_ISTART_AC "RW" + +/** Check whether access to the ISTART field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_ISTART_S 0 + +/** Check whether access to the ISTART field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_ISTART_P 0 + +/** Read the content of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_ISTART(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_ISTART_LSB, ATON_STRENG_CTRL_ISTART_W) + +/** Modify the content of the ISTART field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_ISTART(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_ISTART_LSB, ATON_STRENG_CTRL_ISTART_W, DATA) + + +/** + * Get the description of the ISTART field of CTRL register. + * + * \return the description of the ISTART field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_ISTART_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_ISTART_DESC; +} + + +/** + * Read the content of the ISTART field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ISTART field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_ISTART(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_ISTART(reg); +} + + +/** + * Write the content of the ISTART field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ISTART field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_ISTART(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_ISTART(reg, data); +} + + +/* ---------------------------------------------------------- SUBSAMPLE field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_DESC "Handle data as 4:2:2 (RO when CTRL.RUNNING)" + +/** Offset of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_LSB 6UL + +/** Size in bits of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_W (1UL) + +/** Mask for retrieving the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_MASK ATON_FIELD_MASK(6UL, 1UL) + +/** Reset value of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_DT 0x0UL + +/** Access rights of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_AC "RW" + +/** Check whether access to the SUBSAMPLE field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_S 0 + +/** Check whether access to the SUBSAMPLE field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SUBSAMPLE_P 0 + +/** Read the content of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SUBSAMPLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SUBSAMPLE_LSB, ATON_STRENG_CTRL_SUBSAMPLE_W) + +/** Modify the content of the SUBSAMPLE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SUBSAMPLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SUBSAMPLE_LSB, ATON_STRENG_CTRL_SUBSAMPLE_W, DATA) + + +/** + * Get the description of the SUBSAMPLE field of CTRL register. + * + * \return the description of the SUBSAMPLE field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SUBSAMPLE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SUBSAMPLE_DESC; +} + + +/** + * Read the content of the SUBSAMPLE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SUBSAMPLE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SUBSAMPLE(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SUBSAMPLE(reg); +} + + +/** + * Write the content of the SUBSAMPLE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SUBSAMPLE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SUBSAMPLE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SUBSAMPLE(reg, data); +} + + +/* ------------------------------------------------------------ CONT field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONT_DESC "Do not restart address pointer at end of frame (RO when CTRL.RUNNING)" + +/** Offset of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONT_LSB 7UL + +/** Size in bits of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONT_W (1UL) + +/** Mask for retrieving the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONT_MASK ATON_FIELD_MASK(7UL, 1UL) + +/** Reset value of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONT_DT 0x0UL + +/** Access rights of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONT_AC "RW" + +/** Check whether access to the CONT field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_CONT_S 0 + +/** Check whether access to the CONT field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_CONT_P 0 + +/** Read the content of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_CONT(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_CONT_LSB, ATON_STRENG_CTRL_CONT_W) + +/** Modify the content of the CONT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_CONT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_CONT_LSB, ATON_STRENG_CTRL_CONT_W, DATA) + + +/** + * Get the description of the CONT field of CTRL register. + * + * \return the description of the CONT field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_CONT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_CONT_DESC; +} + + +/** + * Read the content of the CONT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONT field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_CONT(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_CONT(reg); +} + + +/** + * Write the content of the CONT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONT field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_CONT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_CONT(reg, data); +} + + +/* ------------------------------------------------------------- RAW field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_DESC "Send RAW files (RO when CTRL.RUNNING)" + +/** Offset of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_LSB 8UL + +/** Size in bits of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_W (1UL) + +/** Mask for retrieving the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_MASK ATON_FIELD_MASK(8UL, 1UL) + +/** Reset value of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_DT 0x0UL + +/** Access rights of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_AC "RW" + +/** Check whether access to the RAW field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_RAW_S 0 + +/** Check whether access to the RAW field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_RAW_P 0 + +/** Read the content of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_RAW(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_RAW_LSB, ATON_STRENG_CTRL_RAW_W) + +/** Modify the content of the RAW field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_RAW(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_RAW_LSB, ATON_STRENG_CTRL_RAW_W, DATA) + + +/** + * Get the description of the RAW field of CTRL register. + * + * \return the description of the RAW field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_RAW_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_RAW_DESC; +} + + +/** + * Read the content of the RAW field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the RAW field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_RAW(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_RAW(reg); +} + + +/** + * Write the content of the RAW field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_RAW(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_RAW(reg, data); +} + + +/* ----------------------------------------------------------- RAW_OUT field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_OUT_DESC "Force RAW output (bus to stream only) even if the engine is programmed in raster mode (RO when CTRL.RUNNING)" + +/** Offset of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_OUT_LSB 9UL + +/** Size in bits of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_OUT_W (1UL) + +/** Mask for retrieving the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_OUT_MASK ATON_FIELD_MASK(9UL, 1UL) + +/** Reset value of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_OUT_DT 0x0UL + +/** Access rights of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_RAW_OUT_AC "RW" + +/** Check whether access to the RAW_OUT field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_RAW_OUT_S 0 + +/** Check whether access to the RAW_OUT field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_RAW_OUT_P 0 + +/** Read the content of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_RAW_OUT(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_RAW_OUT_LSB, ATON_STRENG_CTRL_RAW_OUT_W) + +/** Modify the content of the RAW_OUT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_RAW_OUT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_RAW_OUT_LSB, ATON_STRENG_CTRL_RAW_OUT_W, DATA) + + +/** + * Get the description of the RAW_OUT field of CTRL register. + * + * \return the description of the RAW_OUT field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_RAW_OUT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_RAW_OUT_DESC; +} + + +/** + * Read the content of the RAW_OUT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the RAW_OUT field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_RAW_OUT(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_RAW_OUT(reg); +} + + +/** + * Write the content of the RAW_OUT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_OUT field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_RAW_OUT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_RAW_OUT(reg, data); +} + + +/* ------------------------------------------------------------ DESCR field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DESCR_DESC "Fetch descriptor from memory (RO when CTRL.RUNNING)" + +/** Offset of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DESCR_LSB 10UL + +/** Size in bits of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DESCR_W (1UL) + +/** Mask for retrieving the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DESCR_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DESCR_DT 0x0UL + +/** Access rights of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_DESCR_AC "RW" + +/** Check whether access to the DESCR field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_DESCR_S 0 + +/** Check whether access to the DESCR field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_DESCR_P 0 + +/** Read the content of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_DESCR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_DESCR_LSB, ATON_STRENG_CTRL_DESCR_W) + +/** Modify the content of the DESCR field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_DESCR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_DESCR_LSB, ATON_STRENG_CTRL_DESCR_W, DATA) + + +/** + * Get the description of the DESCR field of CTRL register. + * + * \return the description of the DESCR field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_DESCR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_DESCR_DESC; +} + + +/** + * Read the content of the DESCR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DESCR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_DESCR(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_DESCR(reg); +} + + +/** + * Write the content of the DESCR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DESCR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_DESCR(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_DESCR(reg, data); +} + + +/* ------------------------------------------------------------ NOBLK field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOBLK_DESC "Do not use blocks wider that the native bus size (RO when CTRL.RUNNING)" + +/** Offset of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOBLK_LSB 11UL + +/** Size in bits of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOBLK_W (1UL) + +/** Mask for retrieving the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOBLK_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOBLK_DT 0x0UL + +/** Access rights of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_NOBLK_AC "RW" + +/** Check whether access to the NOBLK field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_NOBLK_S 0 + +/** Check whether access to the NOBLK field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_NOBLK_P 0 + +/** Read the content of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_NOBLK(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_NOBLK_LSB, ATON_STRENG_CTRL_NOBLK_W) + +/** Modify the content of the NOBLK field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_NOBLK(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_NOBLK_LSB, ATON_STRENG_CTRL_NOBLK_W, DATA) + + +/** + * Get the description of the NOBLK field of CTRL register. + * + * \return the description of the NOBLK field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_NOBLK_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_NOBLK_DESC; +} + + +/** + * Read the content of the NOBLK field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the NOBLK field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_NOBLK(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_NOBLK(reg); +} + + +/** + * Write the content of the NOBLK field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the NOBLK field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_NOBLK(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_NOBLK(reg, data); +} + + +/* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_ROUND_DESC "Channels data rounding enable (RO when CTRL.RUNNING)" + +/** Offset of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_ROUND_LSB 12UL + +/** Size in bits of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_ROUND_W (1UL) + +/** Mask for retrieving the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_ROUND_MASK ATON_FIELD_MASK(12UL, 1UL) + +/** Reset value of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_ROUND_DT 0x0UL + +/** Access rights of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_ROUND_AC "RW" + +/** Check whether access to the ROUND field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_ROUND_S 0 + +/** Check whether access to the ROUND field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_ROUND_P 0 + +/** Read the content of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_ROUND_LSB, ATON_STRENG_CTRL_ROUND_W) + +/** Modify the content of the ROUND field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_ROUND_LSB, ATON_STRENG_CTRL_ROUND_W, DATA) + + +/** + * Get the description of the ROUND field of CTRL register. + * + * \return the description of the ROUND field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_ROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_ROUND_DESC; +} + + +/** + * Read the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_ROUND(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_ROUND(reg); +} + + +/** + * Write the content of the ROUND field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUND field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_ROUND(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_ROUND(reg, data); +} + + +/* ----------------------------------------------------------- BEFORCE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_BEFORCE_DESC "Force bus-wide write (RO when CTRL.RUNNING)" + +/** Offset of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_BEFORCE_LSB 13UL + +/** Size in bits of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_BEFORCE_W (1UL) + +/** Mask for retrieving the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_BEFORCE_MASK ATON_FIELD_MASK(13UL, 1UL) + +/** Reset value of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_BEFORCE_DT 0x0UL + +/** Access rights of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_BEFORCE_AC "RW" + +/** Check whether access to the BEFORCE field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_BEFORCE_S 0 + +/** Check whether access to the BEFORCE field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_BEFORCE_P 0 + +/** Read the content of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_BEFORCE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_BEFORCE_LSB, ATON_STRENG_CTRL_BEFORCE_W) + +/** Modify the content of the BEFORCE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_BEFORCE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_BEFORCE_LSB, ATON_STRENG_CTRL_BEFORCE_W, DATA) + + +/** + * Get the description of the BEFORCE field of CTRL register. + * + * \return the description of the BEFORCE field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_BEFORCE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_BEFORCE_DESC; +} + + +/** + * Read the content of the BEFORCE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the BEFORCE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_BEFORCE(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_BEFORCE(reg); +} + + +/** + * Write the content of the BEFORCE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BEFORCE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_BEFORCE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_BEFORCE(reg, data); +} + + +/* ----------------------------------------------------------- LSBMODE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_LSBMODE_DESC "Use the three 8 bits channels as a unique 24 bit channel LSB aligned (RO when CTRL.RUNNING)" + +/** Offset of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_LSBMODE_LSB 14UL + +/** Size in bits of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_LSBMODE_W (1UL) + +/** Mask for retrieving the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_LSBMODE_MASK ATON_FIELD_MASK(14UL, 1UL) + +/** Reset value of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_LSBMODE_DT 0x0UL + +/** Access rights of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_LSBMODE_AC "RW" + +/** Check whether access to the LSBMODE field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_LSBMODE_S 0 + +/** Check whether access to the LSBMODE field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_LSBMODE_P 0 + +/** Read the content of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_LSBMODE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_LSBMODE_LSB, ATON_STRENG_CTRL_LSBMODE_W) + +/** Modify the content of the LSBMODE field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_LSBMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_LSBMODE_LSB, ATON_STRENG_CTRL_LSBMODE_W, DATA) + + +/** + * Get the description of the LSBMODE field of CTRL register. + * + * \return the description of the LSBMODE field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_LSBMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_LSBMODE_DESC; +} + + +/** + * Read the content of the LSBMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the LSBMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_LSBMODE(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_LSBMODE(reg); +} + + +/** + * Write the content of the LSBMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the LSBMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_LSBMODE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_LSBMODE(reg, data); +} + + +/* ----------------------------------------------------------- SIGNEXT field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIGNEXT_DESC "24 bit sign extension (valid only if LSBMODE is set to 1 and direction is bus to stream) (RO when CTRL.RUNNING)" + +/** Offset of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIGNEXT_LSB 15UL + +/** Size in bits of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIGNEXT_W (1UL) + +/** Mask for retrieving the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIGNEXT_MASK ATON_FIELD_MASK(15UL, 1UL) + +/** Reset value of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIGNEXT_DT 0x0UL + +/** Access rights of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIGNEXT_AC "RW" + +/** Check whether access to the SIGNEXT field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SIGNEXT_S 0 + +/** Check whether access to the SIGNEXT field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SIGNEXT_P 0 + +/** Read the content of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SIGNEXT(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIGNEXT_LSB, ATON_STRENG_CTRL_SIGNEXT_W) + +/** Modify the content of the SIGNEXT field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SIGNEXT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIGNEXT_LSB, ATON_STRENG_CTRL_SIGNEXT_W, DATA) + + +/** + * Get the description of the SIGNEXT field of CTRL register. + * + * \return the description of the SIGNEXT field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SIGNEXT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SIGNEXT_DESC; +} + + +/** + * Read the content of the SIGNEXT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SIGNEXT field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SIGNEXT(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SIGNEXT(reg); +} + + +/** + * Write the content of the SIGNEXT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SIGNEXT field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SIGNEXT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SIGNEXT(reg, data); +} + + +/* ------------------------------------------------------------ SIZE0 field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE0_DESC "Size in bits of channel 0 (values greater than 8 will be refused) (RO when CTRL.RUNNING)" + +/** Offset of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE0_LSB 16UL + +/** Size in bits of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE0_W (4UL) + +/** Mask for retrieving the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE0_MASK ATON_FIELD_MASK(16UL, 4UL) + +/** Reset value of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE0_DT 0x0UL + +/** Access rights of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE0_AC "RW" + +/** Check whether access to the SIZE0 field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SIZE0_S 0 + +/** Check whether access to the SIZE0 field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SIZE0_P 0 + +/** Read the content of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SIZE0(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIZE0_LSB, ATON_STRENG_CTRL_SIZE0_W) + +/** Modify the content of the SIZE0 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SIZE0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIZE0_LSB, ATON_STRENG_CTRL_SIZE0_W, DATA) + + +/** + * Get the description of the SIZE0 field of CTRL register. + * + * \return the description of the SIZE0 field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SIZE0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SIZE0_DESC; +} + + +/** + * Read the content of the SIZE0 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SIZE0 field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SIZE0(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SIZE0(reg); +} + + +/** + * Write the content of the SIZE0 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the SIZE0 field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SIZE0(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SIZE0(reg, data); +} + + +/* ------------------------------------------------------------ SIZE1 field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE1_DESC "Size in bits of channel 1 (values greater than 8 will be refused) (RO when CTRL.RUNNING)" + +/** Offset of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE1_LSB 20UL + +/** Size in bits of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE1_W (4UL) + +/** Mask for retrieving the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE1_MASK ATON_FIELD_MASK(20UL, 4UL) + +/** Reset value of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE1_DT 0x0UL + +/** Access rights of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE1_AC "RW" + +/** Check whether access to the SIZE1 field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SIZE1_S 0 + +/** Check whether access to the SIZE1 field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SIZE1_P 0 + +/** Read the content of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SIZE1(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIZE1_LSB, ATON_STRENG_CTRL_SIZE1_W) + +/** Modify the content of the SIZE1 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SIZE1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIZE1_LSB, ATON_STRENG_CTRL_SIZE1_W, DATA) + + +/** + * Get the description of the SIZE1 field of CTRL register. + * + * \return the description of the SIZE1 field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SIZE1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SIZE1_DESC; +} + + +/** + * Read the content of the SIZE1 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SIZE1 field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SIZE1(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SIZE1(reg); +} + + +/** + * Write the content of the SIZE1 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the SIZE1 field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SIZE1(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SIZE1(reg, data); +} + + +/* ------------------------------------------------------------ SIZE2 field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE2_DESC "Size in bits of channel 2 (values greater than 8 will be refused) (RO when CTRL.RUNNING - ignored, 0 used instead, if CTRL.SUBSAMPLE is set)" + +/** Offset of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE2_LSB 24UL + +/** Size in bits of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE2_W (4UL) + +/** Mask for retrieving the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE2_MASK ATON_FIELD_MASK(24UL, 4UL) + +/** Reset value of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE2_DT 0x0UL + +/** Access rights of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SIZE2_AC "RW" + +/** Check whether access to the SIZE2 field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SIZE2_S 0 + +/** Check whether access to the SIZE2 field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SIZE2_P 0 + +/** Read the content of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SIZE2(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIZE2_LSB, ATON_STRENG_CTRL_SIZE2_W) + +/** Modify the content of the SIZE2 field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SIZE2(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIZE2_LSB, ATON_STRENG_CTRL_SIZE2_W, DATA) + + +/** + * Get the description of the SIZE2 field of CTRL register. + * + * \return the description of the SIZE2 field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SIZE2_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SIZE2_DESC; +} + + +/** + * Read the content of the SIZE2 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SIZE2 field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SIZE2(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SIZE2(reg); +} + + +/** + * Write the content of the SIZE2 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the SIZE2 field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SIZE2(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SIZE2(reg, data); +} + + +/* ----------------------------------------------------------- SERDES field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SERDES_DESC "Enable serdes feature (00/01 -> disable, 10 -> CH0/1, 11 -> CH0/1/2) (RO when CTRL.RUNNING)" + +/** Offset of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SERDES_LSB 28UL + +/** Size in bits of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SERDES_W (2UL) + +/** Mask for retrieving the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SERDES_MASK ATON_FIELD_MASK(28UL, 2UL) + +/** Reset value of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SERDES_DT 0x0UL + +/** Access rights of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SERDES_AC "RW" + +/** Check whether access to the SERDES field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_SERDES_S 0 + +/** Check whether access to the SERDES field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_SERDES_P 0 + +/** Read the content of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_SERDES(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SERDES_LSB, ATON_STRENG_CTRL_SERDES_W) + +/** Modify the content of the SERDES field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_SERDES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SERDES_LSB, ATON_STRENG_CTRL_SERDES_W, DATA) + + +/** + * Get the description of the SERDES field of CTRL register. + * + * \return the description of the SERDES field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_SERDES_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_SERDES_DESC; +} + + +/** + * Read the content of the SERDES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SERDES field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_SERDES(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_SERDES(reg); +} + + +/** + * Write the content of the SERDES field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the SERDES field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_SERDES(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_SERDES(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared) (RO when CTRL.RUNNING)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_CONFCLR_LSB, ATON_STRENG_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_STRENG_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_CONFCLR_LSB, ATON_STRENG_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CTRL_SET_CONFCLR(reg, data); +} + + +/* ----------------------------------------------------------- RUNNING field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_RUNNING_DESC "Running condition" + +/** Offset of the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_RUNNING_LSB 31UL + +/** Size in bits of the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_RUNNING_W (1UL) + +/** Mask for retrieving the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_RUNNING_MASK ATON_FIELD_MASK(31UL, 1UL) + +/** Reset value of the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_RUNNING_DT 0x0UL + +/** Access rights of the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_RUNNING_AC "R" + +/** Check whether access to the RUNNING field of the CTRL register is secured or not. */ +#define ATON_STRENG_CTRL_RUNNING_S 0 + +/** Check whether access to the RUNNING field of the CTRL register is privileged or not. */ +#define ATON_STRENG_CTRL_RUNNING_P 0 + +/** Read the content of the RUNNING field of the CTRL register. */ +#define ATON_STRENG_CTRL_GET_RUNNING(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_RUNNING_LSB, ATON_STRENG_CTRL_RUNNING_W) + + +/** + * Get the description of the RUNNING field of CTRL register. + * + * \return the description of the RUNNING field of CTRL register + */ + +static inline const int8_t *ATON_STRENG_CTRL_RUNNING_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CTRL_RUNNING_DESC; +} + + +/** + * Read the content of the RUNNING field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the RUNNING field belonging to CTRL register + */ + +static inline uint32_t ATON_STRENG_CTRL_Get_RUNNING(uint32_t reg) +{ + return ATON_STRENG_CTRL_GET_RUNNING(reg); +} + + +/* ****************************************************** VERSION register of one of the STRENG Units ******************************************************* */ + +/** Offset of the VERSION register from the base address of the STRENG Unit. */ +#define ATON_STRENG_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the STRENG Unit. */ +#define ATON_STRENG_VERSION_DT \ + (ATON_STRENG_VERSION_TYPE_DT << ATON_STRENG_VERSION_TYPE_LSB) | \ + (ATON_STRENG_VERSION_MINOR_DT << ATON_STRENG_VERSION_MINOR_LSB) | \ + (ATON_STRENG_VERSION_MAJOR_DT << ATON_STRENG_VERSION_MAJOR_LSB) | \ + (ATON_STRENG_VERSION_STRCMD_DT << ATON_STRENG_VERSION_STRCMD_LSB) | \ + (ATON_STRENG_VERSION_SERDES_DT << ATON_STRENG_VERSION_SERDES_LSB) | \ + (ATON_STRENG_VERSION_ENCR_DT << ATON_STRENG_VERSION_ENCR_LSB) | \ + (ATON_STRENG_VERSION_CACHE_DT << ATON_STRENG_VERSION_CACHE_LSB) | \ + (ATON_STRENG_VERSION_CID_DT << ATON_STRENG_VERSION_CID_LSB) | \ + (ATON_STRENG_VERSION_EXTSYNC_DT << ATON_STRENG_VERSION_EXTSYNC_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_STRENG_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the STRENG Units. */ +#define ATON_STRENG_VERSION_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the STRENG Units. */ +#define ATON_STRENG_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_GetOffset(void) +{ + return ATON_STRENG_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the VERSION register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_VERSION_GetAddr(uint32_t instance) +{ + return ATON_STRENG_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_VERSION_Get(uint32_t instance) +{ + return ATON_STRENG_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_TYPE_DT 0x1UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_TYPE_LSB, ATON_STRENG_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MINOR_DT 0x0UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_MINOR_LSB, ATON_STRENG_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MAJOR_DT 0x5UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_MAJOR_LSB, ATON_STRENG_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- STRCMD field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_STRCMD_DESC "Stream commands support" + +/** Offset of the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_STRCMD_LSB 16UL + +/** Size in bits of the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_STRCMD_W (1UL) + +/** Mask for retrieving the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_STRCMD_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_STRCMD_DT 0x0UL + +/** Access rights of the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_STRCMD_AC "R" + +/** Check whether access to the STRCMD field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_STRCMD_S 0 + +/** Check whether access to the STRCMD field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_STRCMD_P 0 + +/** Read the content of the STRCMD field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_STRCMD(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_STRCMD_LSB, ATON_STRENG_VERSION_STRCMD_W) + + +/** + * Get the description of the STRCMD field of VERSION register. + * + * \return the description of the STRCMD field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_STRCMD_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_STRCMD_DESC; +} + + +/** + * Read the content of the STRCMD field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the STRCMD field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_STRCMD(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_STRCMD(reg); +} + + +/* ---------------------------------------------------------- SERDES field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_SERDES_DESC "Serdes support" + +/** Offset of the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_SERDES_LSB 17UL + +/** Size in bits of the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_SERDES_W (1UL) + +/** Mask for retrieving the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_SERDES_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_SERDES_DT 0x1UL + +/** Access rights of the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_SERDES_AC "R" + +/** Check whether access to the SERDES field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_SERDES_S 0 + +/** Check whether access to the SERDES field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_SERDES_P 0 + +/** Read the content of the SERDES field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_SERDES(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_SERDES_LSB, ATON_STRENG_VERSION_SERDES_W) + + +/** + * Get the description of the SERDES field of VERSION register. + * + * \return the description of the SERDES field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_SERDES_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_SERDES_DESC; +} + + +/** + * Read the content of the SERDES field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the SERDES field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_SERDES(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_SERDES(reg); +} + + +/* ----------------------------------------------------------- ENCR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_ENCR_DESC "Encription support" + +/** Offset of the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_ENCR_LSB 18UL + +/** Size in bits of the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_ENCR_W (1UL) + +/** Mask for retrieving the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_ENCR_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_ENCR_DT 0x1UL + +/** Access rights of the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_ENCR_AC "R" + +/** Check whether access to the ENCR field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_ENCR_S 0 + +/** Check whether access to the ENCR field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_ENCR_P 0 + +/** Read the content of the ENCR field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_ENCR(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_ENCR_LSB, ATON_STRENG_VERSION_ENCR_W) + + +/** + * Get the description of the ENCR field of VERSION register. + * + * \return the description of the ENCR field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_ENCR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_ENCR_DESC; +} + + +/** + * Read the content of the ENCR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the ENCR field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_ENCR(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_ENCR(reg); +} + + +/* ---------------------------------------------------------- CACHE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_CACHE_DESC "Cache support" + +/** Offset of the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_CACHE_LSB 19UL + +/** Size in bits of the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_CACHE_W (1UL) + +/** Mask for retrieving the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_CACHE_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_CACHE_DT 0x1UL + +/** Access rights of the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_CACHE_AC "R" + +/** Check whether access to the CACHE field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_CACHE_S 0 + +/** Check whether access to the CACHE field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_CACHE_P 0 + +/** Read the content of the CACHE field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_CACHE(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_CACHE_LSB, ATON_STRENG_VERSION_CACHE_W) + + +/** + * Get the description of the CACHE field of VERSION register. + * + * \return the description of the CACHE field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_CACHE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_CACHE_DESC; +} + + +/** + * Read the content of the CACHE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the CACHE field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_CACHE(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_CACHE(reg); +} + + +/* ----------------------------------------------------------- CID field of the VERSION register ------------------------------------------------------------ */ + +/** Description of the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_CID_DESC "Compartment ID support" + +/** Offset of the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_CID_LSB 20UL + +/** Size in bits of the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_CID_W (1UL) + +/** Mask for retrieving the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_CID_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_CID_DT 0x1UL + +/** Access rights of the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_CID_AC "R" + +/** Check whether access to the CID field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_CID_S 0 + +/** Check whether access to the CID field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_CID_P 0 + +/** Read the content of the CID field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_CID(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_CID_LSB, ATON_STRENG_VERSION_CID_W) + + +/** + * Get the description of the CID field of VERSION register. + * + * \return the description of the CID field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_CID_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_CID_DESC; +} + + +/** + * Read the content of the CID field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the CID field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_CID(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_CID(reg); +} + + +/* --------------------------------------------------------- EXTSYNC field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_EXTSYNC_DESC "External triggers support" + +/** Offset of the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_EXTSYNC_LSB 21UL + +/** Size in bits of the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_EXTSYNC_W (1UL) + +/** Mask for retrieving the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_EXTSYNC_MASK ATON_FIELD_MASK(21UL, 1UL) + +/** Reset value of the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_EXTSYNC_DT 0x1UL + +/** Access rights of the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_EXTSYNC_AC "R" + +/** Check whether access to the EXTSYNC field of the VERSION register is secured or not. */ +#define ATON_STRENG_VERSION_EXTSYNC_S 0 + +/** Check whether access to the EXTSYNC field of the VERSION register is privileged or not. */ +#define ATON_STRENG_VERSION_EXTSYNC_P 0 + +/** Read the content of the EXTSYNC field of the VERSION register. */ +#define ATON_STRENG_VERSION_GET_EXTSYNC(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_EXTSYNC_LSB, ATON_STRENG_VERSION_EXTSYNC_W) + + +/** + * Get the description of the EXTSYNC field of VERSION register. + * + * \return the description of the EXTSYNC field of VERSION register + */ + +static inline const int8_t *ATON_STRENG_VERSION_EXTSYNC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_VERSION_EXTSYNC_DESC; +} + + +/** + * Read the content of the EXTSYNC field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the EXTSYNC field belonging to VERSION register + */ + +static inline uint32_t ATON_STRENG_VERSION_Get_EXTSYNC(uint32_t reg) +{ + return ATON_STRENG_VERSION_GET_EXTSYNC(reg); +} + + +/* ******************************************************** ADDR register of one of the STRENG Units ******************************************************** */ + +/** Offset of the ADDR register from the base address of the STRENG Unit. */ +#define ATON_STRENG_ADDR_OFFSET 0x8UL + +/** Reset value of the ADDR register of the STRENG Unit. */ +#define ATON_STRENG_ADDR_DT \ + (ATON_STRENG_ADDR_REG_DT << ATON_STRENG_ADDR_REG_LSB) + + + +/** Description of the ADDR register. */ +#define ATON_STRENG_ADDR_DESC "Source/destination address" + +/** Address of the ADDR register of one of the STRENG Units. */ +#define ATON_STRENG_ADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_ADDR_OFFSET) + +/** Get the content of the ADDR register of one of the STRENG Units. */ +#define ATON_STRENG_ADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_ADDR_ADDR(UNIT))) + +/** Set the content of the ADDR register of one of the STRENG Units. */ +#define ATON_STRENG_ADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_ADDR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ADDR register. + * + * \return the description of ADDR register + */ + +static inline const int8_t *ATON_STRENG_ADDR_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_ADDR_DESC; +} + + +/** + * Get the offset of the ADDR register. + * + * \return the offset of ADDR register + */ + +static inline uint32_t ATON_STRENG_ADDR_GetOffset(void) +{ + return ATON_STRENG_ADDR_OFFSET; +} + + +/** + * Get the address of the ADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ADDR register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of ADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_ADDR_GetAddr(uint32_t instance) +{ + return ATON_STRENG_ADDR_ADDR(instance); +} + + +/** + * Read the content of the ADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ADDR register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of ADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_ADDR_Get(uint32_t instance) +{ + return ATON_STRENG_ADDR_GET(instance); +} + + +/** + * Write the content of the ADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ADDR register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_ADDR_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_ADDR_SET(instance, data); +} + + +/* ------------------------------------------------------------- REG field of the ADDR register ------------------------------------------------------------- */ + +/** Description of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_REG_DESC "Address (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_REG_LSB 0UL + +/** Size in bits of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_REG_W (32UL) + +/** Mask for retrieving the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_REG_DT 0x0UL + +/** Access rights of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_REG_AC "RW" + +/** Check whether access to the REG field of the ADDR register is secured or not. */ +#define ATON_STRENG_ADDR_REG_S 0 + +/** Check whether access to the REG field of the ADDR register is privileged or not. */ +#define ATON_STRENG_ADDR_REG_P 0 + +/** Read the content of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_ADDR_REG_LSB, ATON_STRENG_ADDR_REG_W) + +/** Modify the content of the REG field of the ADDR register. */ +#define ATON_STRENG_ADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ADDR_REG_LSB, ATON_STRENG_ADDR_REG_W, DATA) + + +/** + * Get the description of the REG field of ADDR register. + * + * \return the description of the REG field of ADDR register + */ + +static inline const int8_t *ATON_STRENG_ADDR_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ADDR_REG_DESC; +} + + +/** + * Read the content of the REG field of the ADDR register. + * + * \param[in] reg is the value of the ADDR register + * + * \return the content of the REG field belonging to ADDR register + */ + +static inline uint32_t ATON_STRENG_ADDR_Get_REG(uint32_t reg) +{ + return ATON_STRENG_ADDR_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the ADDR register. + * + * \param[in] reg is the value of the ADDR register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to ADDR register + */ + +static inline uint32_t ATON_STRENG_ADDR_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ADDR_SET_REG(reg, data); +} + + +/* ******************************************************* FSIZE register of one of the STRENG Units ******************************************************** */ + +/** Offset of the FSIZE register from the base address of the STRENG Unit. */ +#define ATON_STRENG_FSIZE_OFFSET 0xcUL + +/** Reset value of the FSIZE register of the STRENG Unit. */ +#define ATON_STRENG_FSIZE_DT \ + (ATON_STRENG_FSIZE_WIDTH_DT << ATON_STRENG_FSIZE_WIDTH_LSB) | \ + (ATON_STRENG_FSIZE_HEIGHT_DT << ATON_STRENG_FSIZE_HEIGHT_LSB) + + + +/** Description of the FSIZE register. */ +#define ATON_STRENG_FSIZE_DESC "Frame size" + +/** Address of the FSIZE register of one of the STRENG Units. */ +#define ATON_STRENG_FSIZE_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FSIZE_OFFSET) + +/** Get the content of the FSIZE register of one of the STRENG Units. */ +#define ATON_STRENG_FSIZE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FSIZE_ADDR(UNIT))) + +/** Set the content of the FSIZE register of one of the STRENG Units. */ +#define ATON_STRENG_FSIZE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FSIZE_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FSIZE register. + * + * \return the description of FSIZE register + */ + +static inline const int8_t *ATON_STRENG_FSIZE_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_FSIZE_DESC; +} + + +/** + * Get the offset of the FSIZE register. + * + * \return the offset of FSIZE register + */ + +static inline uint32_t ATON_STRENG_FSIZE_GetOffset(void) +{ + return ATON_STRENG_FSIZE_OFFSET; +} + + +/** + * Get the address of the FSIZE register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FSIZE register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of FSIZE register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FSIZE_GetAddr(uint32_t instance) +{ + return ATON_STRENG_FSIZE_ADDR(instance); +} + + +/** + * Read the content of the FSIZE register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FSIZE register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of FSIZE register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FSIZE_Get(uint32_t instance) +{ + return ATON_STRENG_FSIZE_GET(instance); +} + + +/** + * Write the content of the FSIZE register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FSIZE register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_FSIZE_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_FSIZE_SET(instance, data); +} + + +/* ----------------------------------------------------------- WIDTH field of the FSIZE register ------------------------------------------------------------ */ + +/** Description of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_WIDTH_DESC "Frame width (pixl per line). In RAW mode this register contains the lower part of the frame length (RO when CTRL.RUNNING)" + +/** Offset of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_WIDTH_LSB 0UL + +/** Size in bits of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_WIDTH_W (16UL) + +/** Mask for retrieving the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_WIDTH_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_WIDTH_DT 0x0UL + +/** Access rights of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_WIDTH_AC "RW" + +/** Check whether access to the WIDTH field of the FSIZE register is secured or not. */ +#define ATON_STRENG_FSIZE_WIDTH_S 0 + +/** Check whether access to the WIDTH field of the FSIZE register is privileged or not. */ +#define ATON_STRENG_FSIZE_WIDTH_P 0 + +/** Read the content of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_GET_WIDTH(REG) ATON_GET_FIELD(REG, ATON_STRENG_FSIZE_WIDTH_LSB, ATON_STRENG_FSIZE_WIDTH_W) + +/** Modify the content of the WIDTH field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_SET_WIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FSIZE_WIDTH_LSB, ATON_STRENG_FSIZE_WIDTH_W, DATA) + + +/** + * Get the description of the WIDTH field of FSIZE register. + * + * \return the description of the WIDTH field of FSIZE register + */ + +static inline const int8_t *ATON_STRENG_FSIZE_WIDTH_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_FSIZE_WIDTH_DESC; +} + + +/** + * Read the content of the WIDTH field of the FSIZE register. + * + * \param[in] reg is the value of the FSIZE register + * + * \return the content of the WIDTH field belonging to FSIZE register + */ + +static inline uint32_t ATON_STRENG_FSIZE_Get_WIDTH(uint32_t reg) +{ + return ATON_STRENG_FSIZE_GET_WIDTH(reg); +} + + +/** + * Write the content of the WIDTH field of the FSIZE register. + * + * \param[in] reg is the value of the FSIZE register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the WIDTH field belonging to FSIZE register + */ + +static inline uint32_t ATON_STRENG_FSIZE_Set_WIDTH(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_FSIZE_SET_WIDTH(reg, data); +} + + +/* ----------------------------------------------------------- HEIGHT field of the FSIZE register ----------------------------------------------------------- */ + +/** Description of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_HEIGHT_DESC "Frame height (number of lines). In RAW mode this register contains the higher part of the frame length (RO when CTRL.RUNNING)" + +/** Offset of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_HEIGHT_LSB 16UL + +/** Size in bits of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_HEIGHT_W (16UL) + +/** Mask for retrieving the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_HEIGHT_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_HEIGHT_DT 0x0UL + +/** Access rights of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_HEIGHT_AC "RW" + +/** Check whether access to the HEIGHT field of the FSIZE register is secured or not. */ +#define ATON_STRENG_FSIZE_HEIGHT_S 0 + +/** Check whether access to the HEIGHT field of the FSIZE register is privileged or not. */ +#define ATON_STRENG_FSIZE_HEIGHT_P 0 + +/** Read the content of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_GET_HEIGHT(REG) ATON_GET_FIELD(REG, ATON_STRENG_FSIZE_HEIGHT_LSB, ATON_STRENG_FSIZE_HEIGHT_W) + +/** Modify the content of the HEIGHT field of the FSIZE register. */ +#define ATON_STRENG_FSIZE_SET_HEIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FSIZE_HEIGHT_LSB, ATON_STRENG_FSIZE_HEIGHT_W, DATA) + + +/** + * Get the description of the HEIGHT field of FSIZE register. + * + * \return the description of the HEIGHT field of FSIZE register + */ + +static inline const int8_t *ATON_STRENG_FSIZE_HEIGHT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_FSIZE_HEIGHT_DESC; +} + + +/** + * Read the content of the HEIGHT field of the FSIZE register. + * + * \param[in] reg is the value of the FSIZE register + * + * \return the content of the HEIGHT field belonging to FSIZE register + */ + +static inline uint32_t ATON_STRENG_FSIZE_Get_HEIGHT(uint32_t reg) +{ + return ATON_STRENG_FSIZE_GET_HEIGHT(reg); +} + + +/** + * Write the content of the HEIGHT field of the FSIZE register. + * + * \param[in] reg is the value of the FSIZE register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the HEIGHT field belonging to FSIZE register + */ + +static inline uint32_t ATON_STRENG_FSIZE_Set_HEIGHT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_FSIZE_SET_HEIGHT(reg, data); +} + + +/* ******************************************************* DEPTH register of one of the STRENG Units ******************************************************** */ + +/** Offset of the DEPTH register from the base address of the STRENG Unit. */ +#define ATON_STRENG_DEPTH_OFFSET 0x10UL + +/** Reset value of the DEPTH register of the STRENG Unit. */ +#define ATON_STRENG_DEPTH_DT \ + (ATON_STRENG_DEPTH_SIZE_DT << ATON_STRENG_DEPTH_SIZE_LSB) | \ + (ATON_STRENG_DEPTH_OFFSET_DT << ATON_STRENG_DEPTH_OFFSET_LSB) + + + +/** Description of the DEPTH register. */ +#define ATON_STRENG_DEPTH_DESC "Depth for batch mode" + +/** Address of the DEPTH register of one of the STRENG Units. */ +#define ATON_STRENG_DEPTH_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_DEPTH_OFFSET) + +/** Get the content of the DEPTH register of one of the STRENG Units. */ +#define ATON_STRENG_DEPTH_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_DEPTH_ADDR(UNIT))) + +/** Set the content of the DEPTH register of one of the STRENG Units. */ +#define ATON_STRENG_DEPTH_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_DEPTH_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DEPTH register. + * + * \return the description of DEPTH register + */ + +static inline const int8_t *ATON_STRENG_DEPTH_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_DEPTH_DESC; +} + + +/** + * Get the offset of the DEPTH register. + * + * \return the offset of DEPTH register + */ + +static inline uint32_t ATON_STRENG_DEPTH_GetOffset(void) +{ + return ATON_STRENG_DEPTH_OFFSET; +} + + +/** + * Get the address of the DEPTH register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTH register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of DEPTH register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_DEPTH_GetAddr(uint32_t instance) +{ + return ATON_STRENG_DEPTH_ADDR(instance); +} + + +/** + * Read the content of the DEPTH register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTH register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of DEPTH register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_DEPTH_Get(uint32_t instance) +{ + return ATON_STRENG_DEPTH_GET(instance); +} + + +/** + * Write the content of the DEPTH register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTH register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_DEPTH_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_DEPTH_SET(instance, data); +} + + +/* ------------------------------------------------------------ SIZE field of the DEPTH register ------------------------------------------------------------ */ + +/** Description of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SIZE_DESC "Batch depth (subpix per pixel) (RO when CTRL.RUNNING)" + +/** Offset of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SIZE_LSB 0UL + +/** Size in bits of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SIZE_W (16UL) + +/** Mask for retrieving the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SIZE_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SIZE_DT 0x0UL + +/** Access rights of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SIZE_AC "RW" + +/** Check whether access to the SIZE field of the DEPTH register is secured or not. */ +#define ATON_STRENG_DEPTH_SIZE_S 0 + +/** Check whether access to the SIZE field of the DEPTH register is privileged or not. */ +#define ATON_STRENG_DEPTH_SIZE_P 0 + +/** Read the content of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_GET_SIZE(REG) ATON_GET_FIELD(REG, ATON_STRENG_DEPTH_SIZE_LSB, ATON_STRENG_DEPTH_SIZE_W) + +/** Modify the content of the SIZE field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SET_SIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_DEPTH_SIZE_LSB, ATON_STRENG_DEPTH_SIZE_W, DATA) + + +/** + * Get the description of the SIZE field of DEPTH register. + * + * \return the description of the SIZE field of DEPTH register + */ + +static inline const int8_t *ATON_STRENG_DEPTH_SIZE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_DEPTH_SIZE_DESC; +} + + +/** + * Read the content of the SIZE field of the DEPTH register. + * + * \param[in] reg is the value of the DEPTH register + * + * \return the content of the SIZE field belonging to DEPTH register + */ + +static inline uint32_t ATON_STRENG_DEPTH_Get_SIZE(uint32_t reg) +{ + return ATON_STRENG_DEPTH_GET_SIZE(reg); +} + + +/** + * Write the content of the SIZE field of the DEPTH register. + * + * \param[in] reg is the value of the DEPTH register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the SIZE field belonging to DEPTH register + */ + +static inline uint32_t ATON_STRENG_DEPTH_Set_SIZE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_DEPTH_SET_SIZE(reg, data); +} + + +/* ----------------------------------------------------------- OFFSET field of the DEPTH register ----------------------------------------------------------- */ + +/** Description of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_OFFSET_DESC "Offset (bytes) between batches (RO when CTRL.RUNNING)" + +/** Offset of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_OFFSET_LSB 16UL + +/** Size in bits of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_OFFSET_W (16UL) + +/** Mask for retrieving the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_OFFSET_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_OFFSET_DT 0x0UL + +/** Access rights of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_OFFSET_AC "RW" + +/** Check whether access to the OFFSET field of the DEPTH register is secured or not. */ +#define ATON_STRENG_DEPTH_OFFSET_S 0 + +/** Check whether access to the OFFSET field of the DEPTH register is privileged or not. */ +#define ATON_STRENG_DEPTH_OFFSET_P 0 + +/** Read the content of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_GET_OFFSET(REG) ATON_GET_FIELD(REG, ATON_STRENG_DEPTH_OFFSET_LSB, ATON_STRENG_DEPTH_OFFSET_W) + +/** Modify the content of the OFFSET field of the DEPTH register. */ +#define ATON_STRENG_DEPTH_SET_OFFSET(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_DEPTH_OFFSET_LSB, ATON_STRENG_DEPTH_OFFSET_W, DATA) + + +/** + * Get the description of the OFFSET field of DEPTH register. + * + * \return the description of the OFFSET field of DEPTH register + */ + +static inline const int8_t *ATON_STRENG_DEPTH_OFFSET_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_DEPTH_OFFSET_DESC; +} + + +/** + * Read the content of the OFFSET field of the DEPTH register. + * + * \param[in] reg is the value of the DEPTH register + * + * \return the content of the OFFSET field belonging to DEPTH register + */ + +static inline uint32_t ATON_STRENG_DEPTH_Get_OFFSET(uint32_t reg) +{ + return ATON_STRENG_DEPTH_GET_OFFSET(reg); +} + + +/** + * Write the content of the OFFSET field of the DEPTH register. + * + * \param[in] reg is the value of the DEPTH register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the OFFSET field belonging to DEPTH register + */ + +static inline uint32_t ATON_STRENG_DEPTH_Set_OFFSET(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_DEPTH_SET_OFFSET(reg, data); +} + + +/* ******************************************************** STRD register of one of the STRENG Units ******************************************************** */ + +/** Offset of the STRD register from the base address of the STRENG Unit. */ +#define ATON_STRENG_STRD_OFFSET 0x14UL + +/** Reset value of the STRD register of the STRENG Unit. */ +#define ATON_STRENG_STRD_DT \ + (ATON_STRENG_STRD_LOFF_DT << ATON_STRENG_STRD_LOFF_LSB) | \ + (ATON_STRENG_STRD_FGAP_DT << ATON_STRENG_STRD_FGAP_LSB) | \ + (ATON_STRENG_STRD_BGAP_DT << ATON_STRENG_STRD_BGAP_LSB) + + + +/** Description of the STRD register. */ +#define ATON_STRENG_STRD_DESC "Stride" + +/** Address of the STRD register of one of the STRENG Units. */ +#define ATON_STRENG_STRD_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_STRD_OFFSET) + +/** Get the content of the STRD register of one of the STRENG Units. */ +#define ATON_STRENG_STRD_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_STRD_ADDR(UNIT))) + +/** Set the content of the STRD register of one of the STRENG Units. */ +#define ATON_STRENG_STRD_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_STRD_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of STRD register. + * + * \return the description of STRD register + */ + +static inline const int8_t *ATON_STRENG_STRD_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_STRD_DESC; +} + + +/** + * Get the offset of the STRD register. + * + * \return the offset of STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_GetOffset(void) +{ + return ATON_STRENG_STRD_OFFSET; +} + + +/** + * Get the address of the STRD register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STRD register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of STRD register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_STRD_GetAddr(uint32_t instance) +{ + return ATON_STRENG_STRD_ADDR(instance); +} + + +/** + * Read the content of the STRD register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STRD register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of STRD register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_STRD_Get(uint32_t instance) +{ + return ATON_STRENG_STRD_GET(instance); +} + + +/** + * Write the content of the STRD register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STRD register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_STRD_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_STRD_SET(instance, data); +} + + +/* ------------------------------------------------------------ LOFF field of the STRD register ------------------------------------------------------------- */ + +/** Description of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_LOFF_DESC "Memory offset (bytes) between line starts (RO when CTRL.RUNNING)" + +/** Offset of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_LOFF_LSB 0UL + +/** Size in bits of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_LOFF_W (16UL) + +/** Mask for retrieving the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_LOFF_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_LOFF_DT 0x0UL + +/** Access rights of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_LOFF_AC "RW" + +/** Check whether access to the LOFF field of the STRD register is secured or not. */ +#define ATON_STRENG_STRD_LOFF_S 0 + +/** Check whether access to the LOFF field of the STRD register is privileged or not. */ +#define ATON_STRENG_STRD_LOFF_P 0 + +/** Read the content of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_GET_LOFF(REG) ATON_GET_FIELD(REG, ATON_STRENG_STRD_LOFF_LSB, ATON_STRENG_STRD_LOFF_W) + +/** Modify the content of the LOFF field of the STRD register. */ +#define ATON_STRENG_STRD_SET_LOFF(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STRD_LOFF_LSB, ATON_STRENG_STRD_LOFF_W, DATA) + + +/** + * Get the description of the LOFF field of STRD register. + * + * \return the description of the LOFF field of STRD register + */ + +static inline const int8_t *ATON_STRENG_STRD_LOFF_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_STRD_LOFF_DESC; +} + + +/** + * Read the content of the LOFF field of the STRD register. + * + * \param[in] reg is the value of the STRD register + * + * \return the content of the LOFF field belonging to STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_Get_LOFF(uint32_t reg) +{ + return ATON_STRENG_STRD_GET_LOFF(reg); +} + + +/** + * Write the content of the LOFF field of the STRD register. + * + * \param[in] reg is the value of the STRD register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the LOFF field belonging to STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_Set_LOFF(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_STRD_SET_LOFF(reg, data); +} + + +/* ------------------------------------------------------------ FGAP field of the STRD register ------------------------------------------------------------- */ + +/** Description of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_FGAP_DESC "Memory gap in bits in front of each pixel (RO when CTRL.RUNNING)" + +/** Offset of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_FGAP_LSB 16UL + +/** Size in bits of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_FGAP_W (6UL) + +/** Mask for retrieving the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_FGAP_MASK ATON_FIELD_MASK(16UL, 6UL) + +/** Reset value of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_FGAP_DT 0x0UL + +/** Access rights of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_FGAP_AC "RW" + +/** Check whether access to the FGAP field of the STRD register is secured or not. */ +#define ATON_STRENG_STRD_FGAP_S 0 + +/** Check whether access to the FGAP field of the STRD register is privileged or not. */ +#define ATON_STRENG_STRD_FGAP_P 0 + +/** Read the content of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_GET_FGAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_STRD_FGAP_LSB, ATON_STRENG_STRD_FGAP_W) + +/** Modify the content of the FGAP field of the STRD register. */ +#define ATON_STRENG_STRD_SET_FGAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STRD_FGAP_LSB, ATON_STRENG_STRD_FGAP_W, DATA) + + +/** + * Get the description of the FGAP field of STRD register. + * + * \return the description of the FGAP field of STRD register + */ + +static inline const int8_t *ATON_STRENG_STRD_FGAP_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_STRD_FGAP_DESC; +} + + +/** + * Read the content of the FGAP field of the STRD register. + * + * \param[in] reg is the value of the STRD register + * + * \return the content of the FGAP field belonging to STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_Get_FGAP(uint32_t reg) +{ + return ATON_STRENG_STRD_GET_FGAP(reg); +} + + +/** + * Write the content of the FGAP field of the STRD register. + * + * \param[in] reg is the value of the STRD register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the FGAP field belonging to STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_Set_FGAP(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_STRD_SET_FGAP(reg, data); +} + + +/* ------------------------------------------------------------ BGAP field of the STRD register ------------------------------------------------------------- */ + +/** Description of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_BGAP_DESC "Memory gap in bits after each pixel (RO when CTRL.RUNNING)" + +/** Offset of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_BGAP_LSB 24UL + +/** Size in bits of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_BGAP_W (6UL) + +/** Mask for retrieving the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_BGAP_MASK ATON_FIELD_MASK(24UL, 6UL) + +/** Reset value of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_BGAP_DT 0x0UL + +/** Access rights of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_BGAP_AC "RW" + +/** Check whether access to the BGAP field of the STRD register is secured or not. */ +#define ATON_STRENG_STRD_BGAP_S 0 + +/** Check whether access to the BGAP field of the STRD register is privileged or not. */ +#define ATON_STRENG_STRD_BGAP_P 0 + +/** Read the content of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_GET_BGAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_STRD_BGAP_LSB, ATON_STRENG_STRD_BGAP_W) + +/** Modify the content of the BGAP field of the STRD register. */ +#define ATON_STRENG_STRD_SET_BGAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STRD_BGAP_LSB, ATON_STRENG_STRD_BGAP_W, DATA) + + +/** + * Get the description of the BGAP field of STRD register. + * + * \return the description of the BGAP field of STRD register + */ + +static inline const int8_t *ATON_STRENG_STRD_BGAP_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_STRD_BGAP_DESC; +} + + +/** + * Read the content of the BGAP field of the STRD register. + * + * \param[in] reg is the value of the STRD register + * + * \return the content of the BGAP field belonging to STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_Get_BGAP(uint32_t reg) +{ + return ATON_STRENG_STRD_GET_BGAP(reg); +} + + +/** + * Write the content of the BGAP field of the STRD register. + * + * \param[in] reg is the value of the STRD register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the BGAP field belonging to STRD register + */ + +static inline uint32_t ATON_STRENG_STRD_Set_BGAP(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_STRD_SET_BGAP(reg, data); +} + + +/* ****************************************************** FOFFSET register of one of the STRENG Units ******************************************************* */ + +/** Offset of the FOFFSET register from the base address of the STRENG Unit. */ +#define ATON_STRENG_FOFFSET_OFFSET 0x18UL + +/** Reset value of the FOFFSET register of the STRENG Unit. */ +#define ATON_STRENG_FOFFSET_DT \ + (ATON_STRENG_FOFFSET_REG_DT << ATON_STRENG_FOFFSET_REG_LSB) + + + +/** Description of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_DESC "Frame offset within frame repetition loop" + +/** Address of the FOFFSET register of one of the STRENG Units. */ +#define ATON_STRENG_FOFFSET_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FOFFSET_OFFSET) + +/** Get the content of the FOFFSET register of one of the STRENG Units. */ +#define ATON_STRENG_FOFFSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FOFFSET_ADDR(UNIT))) + +/** Set the content of the FOFFSET register of one of the STRENG Units. */ +#define ATON_STRENG_FOFFSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FOFFSET_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FOFFSET register. + * + * \return the description of FOFFSET register + */ + +static inline const int8_t *ATON_STRENG_FOFFSET_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_FOFFSET_DESC; +} + + +/** + * Get the offset of the FOFFSET register. + * + * \return the offset of FOFFSET register + */ + +static inline uint32_t ATON_STRENG_FOFFSET_GetOffset(void) +{ + return ATON_STRENG_FOFFSET_OFFSET; +} + + +/** + * Get the address of the FOFFSET register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FOFFSET register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of FOFFSET register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FOFFSET_GetAddr(uint32_t instance) +{ + return ATON_STRENG_FOFFSET_ADDR(instance); +} + + +/** + * Read the content of the FOFFSET register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FOFFSET register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of FOFFSET register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FOFFSET_Get(uint32_t instance) +{ + return ATON_STRENG_FOFFSET_GET(instance); +} + + +/** + * Write the content of the FOFFSET register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FOFFSET register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_FOFFSET_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_FOFFSET_SET(instance, data); +} + + +/* ----------------------------------------------------------- REG field of the FOFFSET register ------------------------------------------------------------ */ + +/** Description of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_REG_DESC "Offset between multiple frames within frame repetition loop (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_REG_LSB 0UL + +/** Size in bits of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_REG_W (32UL) + +/** Mask for retrieving the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_REG_DT 0x0UL + +/** Access rights of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_REG_AC "RW" + +/** Check whether access to the REG field of the FOFFSET register is secured or not. */ +#define ATON_STRENG_FOFFSET_REG_S 0 + +/** Check whether access to the REG field of the FOFFSET register is privileged or not. */ +#define ATON_STRENG_FOFFSET_REG_P 0 + +/** Read the content of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FOFFSET_REG_LSB, ATON_STRENG_FOFFSET_REG_W) + +/** Modify the content of the REG field of the FOFFSET register. */ +#define ATON_STRENG_FOFFSET_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FOFFSET_REG_LSB, ATON_STRENG_FOFFSET_REG_W, DATA) + + +/** + * Get the description of the REG field of FOFFSET register. + * + * \return the description of the REG field of FOFFSET register + */ + +static inline const int8_t *ATON_STRENG_FOFFSET_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_FOFFSET_REG_DESC; +} + + +/** + * Read the content of the REG field of the FOFFSET register. + * + * \param[in] reg is the value of the FOFFSET register + * + * \return the content of the REG field belonging to FOFFSET register + */ + +static inline uint32_t ATON_STRENG_FOFFSET_Get_REG(uint32_t reg) +{ + return ATON_STRENG_FOFFSET_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the FOFFSET register. + * + * \param[in] reg is the value of the FOFFSET register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to FOFFSET register + */ + +static inline uint32_t ATON_STRENG_FOFFSET_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_FOFFSET_SET_REG(reg, data); +} + + +/* ***************************************************** FRAME_RPT register of one of the STRENG Units ****************************************************** */ + +/** Offset of the FRAME_RPT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_FRAME_RPT_OFFSET 0x1cUL + +/** Reset value of the FRAME_RPT register of the STRENG Unit. */ +#define ATON_STRENG_FRAME_RPT_DT \ + (ATON_STRENG_FRAME_RPT_REG_DT << ATON_STRENG_FRAME_RPT_REG_LSB) + + + +/** Description of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_DESC "Number of frames to loop on" + +/** Address of the FRAME_RPT register of one of the STRENG Units. */ +#define ATON_STRENG_FRAME_RPT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FRAME_RPT_OFFSET) + +/** Get the content of the FRAME_RPT register of one of the STRENG Units. */ +#define ATON_STRENG_FRAME_RPT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRAME_RPT_ADDR(UNIT))) + +/** Set the content of the FRAME_RPT register of one of the STRENG Units. */ +#define ATON_STRENG_FRAME_RPT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRAME_RPT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FRAME_RPT register. + * + * \return the description of FRAME_RPT register + */ + +static inline const int8_t *ATON_STRENG_FRAME_RPT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_FRAME_RPT_DESC; +} + + +/** + * Get the offset of the FRAME_RPT register. + * + * \return the offset of FRAME_RPT register + */ + +static inline uint32_t ATON_STRENG_FRAME_RPT_GetOffset(void) +{ + return ATON_STRENG_FRAME_RPT_OFFSET; +} + + +/** + * Get the address of the FRAME_RPT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRAME_RPT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of FRAME_RPT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FRAME_RPT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_FRAME_RPT_ADDR(instance); +} + + +/** + * Read the content of the FRAME_RPT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRAME_RPT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of FRAME_RPT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FRAME_RPT_Get(uint32_t instance) +{ + return ATON_STRENG_FRAME_RPT_GET(instance); +} + + +/** + * Write the content of the FRAME_RPT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRAME_RPT register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_FRAME_RPT_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_FRAME_RPT_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the FRAME_RPT register ----------------------------------------------------------- */ + +/** Description of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_REG_DESC "Number of frames to loop on (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_REG_LSB 0UL + +/** Size in bits of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_REG_W (32UL) + +/** Mask for retrieving the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_REG_DT 0x0UL + +/** Access rights of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_REG_AC "RW" + +/** Check whether access to the REG field of the FRAME_RPT register is secured or not. */ +#define ATON_STRENG_FRAME_RPT_REG_S 0 + +/** Check whether access to the REG field of the FRAME_RPT register is privileged or not. */ +#define ATON_STRENG_FRAME_RPT_REG_P 0 + +/** Read the content of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FRAME_RPT_REG_LSB, ATON_STRENG_FRAME_RPT_REG_W) + +/** Modify the content of the REG field of the FRAME_RPT register. */ +#define ATON_STRENG_FRAME_RPT_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FRAME_RPT_REG_LSB, ATON_STRENG_FRAME_RPT_REG_W, DATA) + + +/** + * Get the description of the REG field of FRAME_RPT register. + * + * \return the description of the REG field of FRAME_RPT register + */ + +static inline const int8_t *ATON_STRENG_FRAME_RPT_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_FRAME_RPT_REG_DESC; +} + + +/** + * Read the content of the REG field of the FRAME_RPT register. + * + * \param[in] reg is the value of the FRAME_RPT register + * + * \return the content of the REG field belonging to FRAME_RPT register + */ + +static inline uint32_t ATON_STRENG_FRAME_RPT_Get_REG(uint32_t reg) +{ + return ATON_STRENG_FRAME_RPT_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the FRAME_RPT register. + * + * \param[in] reg is the value of the FRAME_RPT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to FRAME_RPT register + */ + +static inline uint32_t ATON_STRENG_FRAME_RPT_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_FRAME_RPT_SET_REG(reg, data); +} + + +/* ****************************************************** FRPTOFF register of one of the STRENG Units ******************************************************* */ + +/** Offset of the FRPTOFF register from the base address of the STRENG Unit. */ +#define ATON_STRENG_FRPTOFF_OFFSET 0x20UL + +/** Reset value of the FRPTOFF register of the STRENG Unit. */ +#define ATON_STRENG_FRPTOFF_DT \ + (ATON_STRENG_FRPTOFF_REG_DT << ATON_STRENG_FRPTOFF_REG_LSB) + + + +/** Description of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_DESC "Frame offset between frame repetition loops" + +/** Address of the FRPTOFF register of one of the STRENG Units. */ +#define ATON_STRENG_FRPTOFF_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FRPTOFF_OFFSET) + +/** Get the content of the FRPTOFF register of one of the STRENG Units. */ +#define ATON_STRENG_FRPTOFF_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRPTOFF_ADDR(UNIT))) + +/** Set the content of the FRPTOFF register of one of the STRENG Units. */ +#define ATON_STRENG_FRPTOFF_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRPTOFF_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FRPTOFF register. + * + * \return the description of FRPTOFF register + */ + +static inline const int8_t *ATON_STRENG_FRPTOFF_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_FRPTOFF_DESC; +} + + +/** + * Get the offset of the FRPTOFF register. + * + * \return the offset of FRPTOFF register + */ + +static inline uint32_t ATON_STRENG_FRPTOFF_GetOffset(void) +{ + return ATON_STRENG_FRPTOFF_OFFSET; +} + + +/** + * Get the address of the FRPTOFF register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRPTOFF register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of FRPTOFF register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FRPTOFF_GetAddr(uint32_t instance) +{ + return ATON_STRENG_FRPTOFF_ADDR(instance); +} + + +/** + * Read the content of the FRPTOFF register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRPTOFF register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of FRPTOFF register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FRPTOFF_Get(uint32_t instance) +{ + return ATON_STRENG_FRPTOFF_GET(instance); +} + + +/** + * Write the content of the FRPTOFF register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRPTOFF register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_FRPTOFF_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_FRPTOFF_SET(instance, data); +} + + +/* ----------------------------------------------------------- REG field of the FRPTOFF register ------------------------------------------------------------ */ + +/** Description of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_REG_DESC "Offset between frame repetition loops (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_REG_LSB 0UL + +/** Size in bits of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_REG_W (32UL) + +/** Mask for retrieving the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_REG_DT 0x0UL + +/** Access rights of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_REG_AC "RW" + +/** Check whether access to the REG field of the FRPTOFF register is secured or not. */ +#define ATON_STRENG_FRPTOFF_REG_S 0 + +/** Check whether access to the REG field of the FRPTOFF register is privileged or not. */ +#define ATON_STRENG_FRPTOFF_REG_P 0 + +/** Read the content of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FRPTOFF_REG_LSB, ATON_STRENG_FRPTOFF_REG_W) + +/** Modify the content of the REG field of the FRPTOFF register. */ +#define ATON_STRENG_FRPTOFF_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FRPTOFF_REG_LSB, ATON_STRENG_FRPTOFF_REG_W, DATA) + + +/** + * Get the description of the REG field of FRPTOFF register. + * + * \return the description of the REG field of FRPTOFF register + */ + +static inline const int8_t *ATON_STRENG_FRPTOFF_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_FRPTOFF_REG_DESC; +} + + +/** + * Read the content of the REG field of the FRPTOFF register. + * + * \param[in] reg is the value of the FRPTOFF register + * + * \return the content of the REG field belonging to FRPTOFF register + */ + +static inline uint32_t ATON_STRENG_FRPTOFF_Get_REG(uint32_t reg) +{ + return ATON_STRENG_FRPTOFF_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the FRPTOFF register. + * + * \param[in] reg is the value of the FRPTOFF register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to FRPTOFF register + */ + +static inline uint32_t ATON_STRENG_FRPTOFF_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_FRPTOFF_SET_REG(reg, data); +} + + +/* ******************************************************** POS register of one of the STRENG Units ********************************************************* */ + +/** Offset of the POS register from the base address of the STRENG Unit. */ +#define ATON_STRENG_POS_OFFSET 0x24UL + +/** Reset value of the POS register of the STRENG Unit. */ +#define ATON_STRENG_POS_DT \ + (ATON_STRENG_POS_POS0_DT << ATON_STRENG_POS_POS0_LSB) | \ + (ATON_STRENG_POS_POS1_DT << ATON_STRENG_POS_POS1_LSB) | \ + (ATON_STRENG_POS_POS2_DT << ATON_STRENG_POS_POS2_LSB) | \ + (ATON_STRENG_POS_WSWAP_DT << ATON_STRENG_POS_WSWAP_LSB) | \ + (ATON_STRENG_POS_HSWAP_DT << ATON_STRENG_POS_HSWAP_LSB) | \ + (ATON_STRENG_POS_BSWAP_DT << ATON_STRENG_POS_BSWAP_LSB) | \ + (ATON_STRENG_POS_THROTTLE_DT << ATON_STRENG_POS_THROTTLE_LSB) | \ + (ATON_STRENG_POS_GAPCYCLES_DT << ATON_STRENG_POS_GAPCYCLES_LSB) + + + +/** Description of the POS register. */ +#define ATON_STRENG_POS_DESC "Position" + +/** Address of the POS register of one of the STRENG Units. */ +#define ATON_STRENG_POS_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_POS_OFFSET) + +/** Get the content of the POS register of one of the STRENG Units. */ +#define ATON_STRENG_POS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_POS_ADDR(UNIT))) + +/** Set the content of the POS register of one of the STRENG Units. */ +#define ATON_STRENG_POS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_POS_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of POS register. + * + * \return the description of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_DESC; +} + + +/** + * Get the offset of the POS register. + * + * \return the offset of POS register + */ + +static inline uint32_t ATON_STRENG_POS_GetOffset(void) +{ + return ATON_STRENG_POS_OFFSET; +} + + +/** + * Get the address of the POS register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the POS register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of POS register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_POS_GetAddr(uint32_t instance) +{ + return ATON_STRENG_POS_ADDR(instance); +} + + +/** + * Read the content of the POS register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the POS register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of POS register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_POS_Get(uint32_t instance) +{ + return ATON_STRENG_POS_GET(instance); +} + + +/** + * Write the content of the POS register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the POS register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_POS_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_POS_SET(instance, data); +} + + +/* ------------------------------------------------------------- POS0 field of the POS register ------------------------------------------------------------- */ + +/** Description of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_POS0_DESC "Data at position 0 (RO when CTRL.RUNNING)" + +/** Offset of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_POS0_LSB 0UL + +/** Size in bits of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_POS0_W (2UL) + +/** Mask for retrieving the POS0 field of the POS register. */ +#define ATON_STRENG_POS_POS0_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_POS0_DT 0x0UL + +/** Access rights of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_POS0_AC "RW" + +/** Check whether access to the POS0 field of the POS register is secured or not. */ +#define ATON_STRENG_POS_POS0_S 0 + +/** Check whether access to the POS0 field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_POS0_P 0 + +/** Read the content of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_GET_POS0(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_POS0_LSB, ATON_STRENG_POS_POS0_W) + +/** Modify the content of the POS0 field of the POS register. */ +#define ATON_STRENG_POS_SET_POS0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_POS0_LSB, ATON_STRENG_POS_POS0_W, DATA) + + +/** + * Get the description of the POS0 field of POS register. + * + * \return the description of the POS0 field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_POS0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_POS0_DESC; +} + + +/** + * Read the content of the POS0 field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the POS0 field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_POS0(uint32_t reg) +{ + return ATON_STRENG_POS_GET_POS0(reg); +} + + +/** + * Write the content of the POS0 field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the POS0 field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_POS0(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_POS0(reg, data); +} + + +/* ------------------------------------------------------------- POS1 field of the POS register ------------------------------------------------------------- */ + +/** Description of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_POS1_DESC "Data at position 1 (RO when CTRL.RUNNING)" + +/** Offset of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_POS1_LSB 2UL + +/** Size in bits of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_POS1_W (2UL) + +/** Mask for retrieving the POS1 field of the POS register. */ +#define ATON_STRENG_POS_POS1_MASK ATON_FIELD_MASK(2UL, 2UL) + +/** Reset value of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_POS1_DT 0x1UL + +/** Access rights of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_POS1_AC "RW" + +/** Check whether access to the POS1 field of the POS register is secured or not. */ +#define ATON_STRENG_POS_POS1_S 0 + +/** Check whether access to the POS1 field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_POS1_P 0 + +/** Read the content of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_GET_POS1(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_POS1_LSB, ATON_STRENG_POS_POS1_W) + +/** Modify the content of the POS1 field of the POS register. */ +#define ATON_STRENG_POS_SET_POS1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_POS1_LSB, ATON_STRENG_POS_POS1_W, DATA) + + +/** + * Get the description of the POS1 field of POS register. + * + * \return the description of the POS1 field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_POS1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_POS1_DESC; +} + + +/** + * Read the content of the POS1 field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the POS1 field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_POS1(uint32_t reg) +{ + return ATON_STRENG_POS_GET_POS1(reg); +} + + +/** + * Write the content of the POS1 field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the POS1 field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_POS1(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_POS1(reg, data); +} + + +/* ------------------------------------------------------------- POS2 field of the POS register ------------------------------------------------------------- */ + +/** Description of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_POS2_DESC "Data at position 2 (RO when CTRL.RUNNING)" + +/** Offset of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_POS2_LSB 4UL + +/** Size in bits of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_POS2_W (2UL) + +/** Mask for retrieving the POS2 field of the POS register. */ +#define ATON_STRENG_POS_POS2_MASK ATON_FIELD_MASK(4UL, 2UL) + +/** Reset value of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_POS2_DT 0x2UL + +/** Access rights of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_POS2_AC "RW" + +/** Check whether access to the POS2 field of the POS register is secured or not. */ +#define ATON_STRENG_POS_POS2_S 0 + +/** Check whether access to the POS2 field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_POS2_P 0 + +/** Read the content of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_GET_POS2(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_POS2_LSB, ATON_STRENG_POS_POS2_W) + +/** Modify the content of the POS2 field of the POS register. */ +#define ATON_STRENG_POS_SET_POS2(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_POS2_LSB, ATON_STRENG_POS_POS2_W, DATA) + + +/** + * Get the description of the POS2 field of POS register. + * + * \return the description of the POS2 field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_POS2_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_POS2_DESC; +} + + +/** + * Read the content of the POS2 field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the POS2 field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_POS2(uint32_t reg) +{ + return ATON_STRENG_POS_GET_POS2(reg); +} + + +/** + * Write the content of the POS2 field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the POS2 field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_POS2(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_POS2(reg, data); +} + + +/* ------------------------------------------------------------ WSWAP field of the POS register ------------------------------------------------------------- */ + +/** Description of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_WSWAP_DESC "Swap 32 bits in 64 bits (RO when CTRL.RUNNING)" + +/** Offset of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_WSWAP_LSB 8UL + +/** Size in bits of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_WSWAP_W (1UL) + +/** Mask for retrieving the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_WSWAP_MASK ATON_FIELD_MASK(8UL, 1UL) + +/** Reset value of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_WSWAP_DT 0x0UL + +/** Access rights of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_WSWAP_AC "RW" + +/** Check whether access to the WSWAP field of the POS register is secured or not. */ +#define ATON_STRENG_POS_WSWAP_S 0 + +/** Check whether access to the WSWAP field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_WSWAP_P 0 + +/** Read the content of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_GET_WSWAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_WSWAP_LSB, ATON_STRENG_POS_WSWAP_W) + +/** Modify the content of the WSWAP field of the POS register. */ +#define ATON_STRENG_POS_SET_WSWAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_WSWAP_LSB, ATON_STRENG_POS_WSWAP_W, DATA) + + +/** + * Get the description of the WSWAP field of POS register. + * + * \return the description of the WSWAP field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_WSWAP_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_WSWAP_DESC; +} + + +/** + * Read the content of the WSWAP field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the WSWAP field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_WSWAP(uint32_t reg) +{ + return ATON_STRENG_POS_GET_WSWAP(reg); +} + + +/** + * Write the content of the WSWAP field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WSWAP field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_WSWAP(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_WSWAP(reg, data); +} + + +/* ------------------------------------------------------------ HSWAP field of the POS register ------------------------------------------------------------- */ + +/** Description of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_HSWAP_DESC "Swap 16 bits in 32 bits (RO when CTRL.RUNNING)" + +/** Offset of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_HSWAP_LSB 9UL + +/** Size in bits of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_HSWAP_W (1UL) + +/** Mask for retrieving the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_HSWAP_MASK ATON_FIELD_MASK(9UL, 1UL) + +/** Reset value of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_HSWAP_DT 0x0UL + +/** Access rights of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_HSWAP_AC "RW" + +/** Check whether access to the HSWAP field of the POS register is secured or not. */ +#define ATON_STRENG_POS_HSWAP_S 0 + +/** Check whether access to the HSWAP field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_HSWAP_P 0 + +/** Read the content of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_GET_HSWAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_HSWAP_LSB, ATON_STRENG_POS_HSWAP_W) + +/** Modify the content of the HSWAP field of the POS register. */ +#define ATON_STRENG_POS_SET_HSWAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_HSWAP_LSB, ATON_STRENG_POS_HSWAP_W, DATA) + + +/** + * Get the description of the HSWAP field of POS register. + * + * \return the description of the HSWAP field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_HSWAP_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_HSWAP_DESC; +} + + +/** + * Read the content of the HSWAP field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the HSWAP field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_HSWAP(uint32_t reg) +{ + return ATON_STRENG_POS_GET_HSWAP(reg); +} + + +/** + * Write the content of the HSWAP field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the HSWAP field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_HSWAP(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_HSWAP(reg, data); +} + + +/* ------------------------------------------------------------ BSWAP field of the POS register ------------------------------------------------------------- */ + +/** Description of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_BSWAP_DESC "Swap 8 bits in 16 bits (RO when CTRL.RUNNING)" + +/** Offset of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_BSWAP_LSB 10UL + +/** Size in bits of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_BSWAP_W (1UL) + +/** Mask for retrieving the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_BSWAP_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_BSWAP_DT 0x0UL + +/** Access rights of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_BSWAP_AC "RW" + +/** Check whether access to the BSWAP field of the POS register is secured or not. */ +#define ATON_STRENG_POS_BSWAP_S 0 + +/** Check whether access to the BSWAP field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_BSWAP_P 0 + +/** Read the content of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_GET_BSWAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_BSWAP_LSB, ATON_STRENG_POS_BSWAP_W) + +/** Modify the content of the BSWAP field of the POS register. */ +#define ATON_STRENG_POS_SET_BSWAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_BSWAP_LSB, ATON_STRENG_POS_BSWAP_W, DATA) + + +/** + * Get the description of the BSWAP field of POS register. + * + * \return the description of the BSWAP field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_BSWAP_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_BSWAP_DESC; +} + + +/** + * Read the content of the BSWAP field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the BSWAP field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_BSWAP(uint32_t reg) +{ + return ATON_STRENG_POS_GET_BSWAP(reg); +} + + +/** + * Write the content of the BSWAP field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the BSWAP field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_BSWAP(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_BSWAP(reg, data); +} + + +/* ----------------------------------------------------------- THROTTLE field of the POS register ----------------------------------------------------------- */ + +/** Description of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_THROTTLE_DESC "Transmit only ever N cycles (RO when CTRL.RUNNING)" + +/** Offset of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_THROTTLE_LSB 12UL + +/** Size in bits of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_THROTTLE_W (4UL) + +/** Mask for retrieving the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_THROTTLE_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_THROTTLE_DT 0x0UL + +/** Access rights of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_THROTTLE_AC "RW" + +/** Check whether access to the THROTTLE field of the POS register is secured or not. */ +#define ATON_STRENG_POS_THROTTLE_S 0 + +/** Check whether access to the THROTTLE field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_THROTTLE_P 0 + +/** Read the content of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_GET_THROTTLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_THROTTLE_LSB, ATON_STRENG_POS_THROTTLE_W) + +/** Modify the content of the THROTTLE field of the POS register. */ +#define ATON_STRENG_POS_SET_THROTTLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_THROTTLE_LSB, ATON_STRENG_POS_THROTTLE_W, DATA) + + +/** + * Get the description of the THROTTLE field of POS register. + * + * \return the description of the THROTTLE field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_THROTTLE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_THROTTLE_DESC; +} + + +/** + * Read the content of the THROTTLE field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the THROTTLE field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_THROTTLE(uint32_t reg) +{ + return ATON_STRENG_POS_GET_THROTTLE(reg); +} + + +/** + * Write the content of the THROTTLE field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the THROTTLE field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_THROTTLE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_THROTTLE(reg, data); +} + + +/* ---------------------------------------------------------- GAPCYCLES field of the POS register ----------------------------------------------------------- */ + +/** Description of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GAPCYCLES_DESC "Dead cycles among lines (RO when CTRL.RUNNING)" + +/** Offset of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GAPCYCLES_LSB 16UL + +/** Size in bits of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GAPCYCLES_W (16UL) + +/** Mask for retrieving the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GAPCYCLES_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GAPCYCLES_DT 0x8UL + +/** Access rights of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GAPCYCLES_AC "RW" + +/** Check whether access to the GAPCYCLES field of the POS register is secured or not. */ +#define ATON_STRENG_POS_GAPCYCLES_S 0 + +/** Check whether access to the GAPCYCLES field of the POS register is privileged or not. */ +#define ATON_STRENG_POS_GAPCYCLES_P 0 + +/** Read the content of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_GET_GAPCYCLES(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_GAPCYCLES_LSB, ATON_STRENG_POS_GAPCYCLES_W) + +/** Modify the content of the GAPCYCLES field of the POS register. */ +#define ATON_STRENG_POS_SET_GAPCYCLES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_GAPCYCLES_LSB, ATON_STRENG_POS_GAPCYCLES_W, DATA) + + +/** + * Get the description of the GAPCYCLES field of POS register. + * + * \return the description of the GAPCYCLES field of POS register + */ + +static inline const int8_t *ATON_STRENG_POS_GAPCYCLES_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_POS_GAPCYCLES_DESC; +} + + +/** + * Read the content of the GAPCYCLES field of the POS register. + * + * \param[in] reg is the value of the POS register + * + * \return the content of the GAPCYCLES field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Get_GAPCYCLES(uint32_t reg) +{ + return ATON_STRENG_POS_GET_GAPCYCLES(reg); +} + + +/** + * Write the content of the GAPCYCLES field of the POS register. + * + * \param[in] reg is the value of the POS register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the GAPCYCLES field belonging to POS register + */ + +static inline uint32_t ATON_STRENG_POS_Set_GAPCYCLES(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_POS_SET_GAPCYCLES(reg, data); +} + + +/* ******************************************************* EVENT register of one of the STRENG Units ******************************************************** */ + +/** Offset of the EVENT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_EVENT_OFFSET 0x28UL + +/** Reset value of the EVENT register of the STRENG Unit. */ +#define ATON_STRENG_EVENT_DT \ + (ATON_STRENG_EVENT_LEVEL_DT << ATON_STRENG_EVENT_LEVEL_LSB) | \ + (ATON_STRENG_EVENT_TYPE_DT << ATON_STRENG_EVENT_TYPE_LSB) | \ + (ATON_STRENG_EVENT_SET_DT << ATON_STRENG_EVENT_SET_LSB) | \ + (ATON_STRENG_EVENT_EN_BUFBL_DT << ATON_STRENG_EVENT_EN_BUFBL_LSB) | \ + (ATON_STRENG_EVENT_EN_MRK_DT << ATON_STRENG_EVENT_EN_MRK_LSB) | \ + (ATON_STRENG_EVENT_EN_OFLOW_ADD_DT << ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB) | \ + (ATON_STRENG_EVENT_EN_OFLOW_FRM_DT << ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB) | \ + (ATON_STRENG_EVENT_EN_ILLCFG_DT << ATON_STRENG_EVENT_EN_ILLCFG_LSB) | \ + (ATON_STRENG_EVENT_EN_FMTMM_DT << ATON_STRENG_EVENT_EN_FMTMM_LSB) | \ + (ATON_STRENG_EVENT_EN_CLRMSGRCV_DT << ATON_STRENG_EVENT_EN_CLRMSGRCV_LSB) | \ + (ATON_STRENG_EVENT_FRMTRG_EN_DT << ATON_STRENG_EVENT_FRMTRG_EN_LSB) | \ + (ATON_STRENG_EVENT_FRMTRG_SRC_DT << ATON_STRENG_EVENT_FRMTRG_SRC_LSB) + + + +/** Description of the EVENT register. */ +#define ATON_STRENG_EVENT_DESC "Event" + +/** Address of the EVENT register of one of the STRENG Units. */ +#define ATON_STRENG_EVENT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_EVENT_OFFSET) + +/** Get the content of the EVENT register of one of the STRENG Units. */ +#define ATON_STRENG_EVENT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_EVENT_ADDR(UNIT))) + +/** Set the content of the EVENT register of one of the STRENG Units. */ +#define ATON_STRENG_EVENT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_EVENT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT register. + * + * \return the description of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_DESC; +} + + +/** + * Get the offset of the EVENT register. + * + * \return the offset of EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_GetOffset(void) +{ + return ATON_STRENG_EVENT_OFFSET; +} + + +/** + * Get the address of the EVENT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EVENT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of EVENT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_EVENT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_EVENT_ADDR(instance); +} + + +/** + * Read the content of the EVENT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EVENT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of EVENT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_EVENT_Get(uint32_t instance) +{ + return ATON_STRENG_EVENT_GET(instance); +} + + +/** + * Write the content of the EVENT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EVENT register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_EVENT_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_EVENT_SET(instance, data); +} + + +/* ----------------------------------------------------------- LEVEL field of the EVENT register ------------------------------------------------------------ */ + +/** Description of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_LEVEL_DESC "Event level" + +/** Offset of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_LEVEL_LSB 0UL + +/** Size in bits of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_LEVEL_W (13UL) + +/** Mask for retrieving the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_LEVEL_MASK ATON_FIELD_MASK(0UL, 13UL) + +/** Reset value of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_LEVEL_DT 0x0UL + +/** Access rights of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_LEVEL_AC "RW" + +/** Check whether access to the LEVEL field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_LEVEL_S 0 + +/** Check whether access to the LEVEL field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_LEVEL_P 0 + +/** Read the content of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_LEVEL(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_LEVEL_LSB, ATON_STRENG_EVENT_LEVEL_W) + +/** Modify the content of the LEVEL field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_LEVEL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_LEVEL_LSB, ATON_STRENG_EVENT_LEVEL_W, DATA) + + +/** + * Get the description of the LEVEL field of EVENT register. + * + * \return the description of the LEVEL field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_LEVEL_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_LEVEL_DESC; +} + + +/** + * Read the content of the LEVEL field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the LEVEL field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_LEVEL(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_LEVEL(reg); +} + + +/** + * Write the content of the LEVEL field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the LEVEL field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_LEVEL(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_LEVEL(reg, data); +} + + +/* ------------------------------------------------------------ TYPE field of the EVENT register ------------------------------------------------------------ */ + +/** Description of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_TYPE_DESC "Event type" + +/** Offset of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_TYPE_LSB 13UL + +/** Size in bits of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_TYPE_MASK ATON_FIELD_MASK(13UL, 2UL) + +/** Reset value of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_TYPE_DT 0x0UL + +/** Access rights of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_TYPE_AC "RW" + +/** Check whether access to the TYPE field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_TYPE_S 0 + +/** Check whether access to the TYPE field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_TYPE_P 0 + +/** Read the content of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_TYPE_LSB, ATON_STRENG_EVENT_TYPE_W) + +/** Modify the content of the TYPE field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_TYPE_LSB, ATON_STRENG_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the TYPE field of EVENT register. + * + * \return the description of the TYPE field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the TYPE field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_TYPE(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_TYPE(reg); +} + + +/** + * Write the content of the TYPE field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the TYPE field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_TYPE(reg, data); +} + + +/* ------------------------------------------------------------ SET field of the EVENT register ------------------------------------------------------------- */ + +/** Description of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_DESC "Activate event trigger" + +/** Offset of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_LSB 15UL + +/** Size in bits of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_W (1UL) + +/** Mask for retrieving the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_MASK ATON_FIELD_MASK(15UL, 1UL) + +/** Reset value of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_DT 0x0UL + +/** Access rights of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_AC "RW" + +/** Check whether access to the SET field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_SET_S 0 + +/** Check whether access to the SET field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_SET_P 0 + +/** Read the content of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_SET(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_SET_LSB, ATON_STRENG_EVENT_SET_W) + +/** Modify the content of the SET field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_SET(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_SET_LSB, ATON_STRENG_EVENT_SET_W, DATA) + + +/** + * Get the description of the SET field of EVENT register. + * + * \return the description of the SET field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_SET_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_SET_DESC; +} + + +/** + * Read the content of the SET field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the SET field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_SET(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_SET(reg); +} + + +/** + * Write the content of the SET field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SET field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_SET(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_SET(reg, data); +} + + +/* ---------------------------------------------------------- EN_BUFBL field of the EVENT register ---------------------------------------------------------- */ + +/** Description of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_BUFBL_DESC "Enable buffer bandwith limit hit irq" + +/** Offset of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_BUFBL_LSB 16UL + +/** Size in bits of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_BUFBL_W (1UL) + +/** Mask for retrieving the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_BUFBL_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_BUFBL_DT 0x0UL + +/** Access rights of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_BUFBL_AC "RW" + +/** Check whether access to the EN_BUFBL field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_BUFBL_S 0 + +/** Check whether access to the EN_BUFBL field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_BUFBL_P 0 + +/** Read the content of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_BUFBL(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_BUFBL_LSB, ATON_STRENG_EVENT_EN_BUFBL_W) + +/** Modify the content of the EN_BUFBL field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_EN_BUFBL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_BUFBL_LSB, ATON_STRENG_EVENT_EN_BUFBL_W, DATA) + + +/** + * Get the description of the EN_BUFBL field of EVENT register. + * + * \return the description of the EN_BUFBL field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_BUFBL_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_BUFBL_DESC; +} + + +/** + * Read the content of the EN_BUFBL field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_BUFBL field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_BUFBL(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_BUFBL(reg); +} + + +/** + * Write the content of the EN_BUFBL field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN_BUFBL field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_EN_BUFBL(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_EN_BUFBL(reg, data); +} + + +/* ----------------------------------------------------------- EN_MRK field of the EVENT register ----------------------------------------------------------- */ + +/** Description of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_MRK_DESC "Enable marker hit irq" + +/** Offset of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_MRK_LSB 17UL + +/** Size in bits of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_MRK_W (1UL) + +/** Mask for retrieving the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_MRK_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_MRK_DT 0x0UL + +/** Access rights of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_MRK_AC "RW" + +/** Check whether access to the EN_MRK field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_MRK_S 0 + +/** Check whether access to the EN_MRK field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_MRK_P 0 + +/** Read the content of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_MRK(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_MRK_LSB, ATON_STRENG_EVENT_EN_MRK_W) + +/** Modify the content of the EN_MRK field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_EN_MRK(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_MRK_LSB, ATON_STRENG_EVENT_EN_MRK_W, DATA) + + +/** + * Get the description of the EN_MRK field of EVENT register. + * + * \return the description of the EN_MRK field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_MRK_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_MRK_DESC; +} + + +/** + * Read the content of the EN_MRK field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_MRK field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_MRK(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_MRK(reg); +} + + +/** + * Write the content of the EN_MRK field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN_MRK field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_EN_MRK(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_EN_MRK(reg, data); +} + + +/* -------------------------------------------------------- EN_OFLOW_ADD field of the EVENT register -------------------------------------------------------- */ + +/** Description of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_DESC "Enable address limiter hit irq" + +/** Offset of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB 18UL + +/** Size in bits of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_W (1UL) + +/** Mask for retrieving the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_DT 0x0UL + +/** Access rights of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_AC "RW" + +/** Check whether access to the EN_OFLOW_ADD field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_S 0 + +/** Check whether access to the EN_OFLOW_ADD field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_OFLOW_ADD_P 0 + +/** Read the content of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_OFLOW_ADD(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB, ATON_STRENG_EVENT_EN_OFLOW_ADD_W) + +/** Modify the content of the EN_OFLOW_ADD field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_EN_OFLOW_ADD(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB, ATON_STRENG_EVENT_EN_OFLOW_ADD_W, DATA) + + +/** + * Get the description of the EN_OFLOW_ADD field of EVENT register. + * + * \return the description of the EN_OFLOW_ADD field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_OFLOW_ADD_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_OFLOW_ADD_DESC; +} + + +/** + * Read the content of the EN_OFLOW_ADD field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_OFLOW_ADD field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_OFLOW_ADD(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_OFLOW_ADD(reg); +} + + +/** + * Write the content of the EN_OFLOW_ADD field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN_OFLOW_ADD field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_EN_OFLOW_ADD(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_EN_OFLOW_ADD(reg, data); +} + + +/* -------------------------------------------------------- EN_OFLOW_FRM field of the EVENT register -------------------------------------------------------- */ + +/** Description of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_DESC "Enable frame limiter hit irq" + +/** Offset of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB 19UL + +/** Size in bits of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_W (1UL) + +/** Mask for retrieving the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_DT 0x0UL + +/** Access rights of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_AC "RW" + +/** Check whether access to the EN_OFLOW_FRM field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_S 0 + +/** Check whether access to the EN_OFLOW_FRM field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_OFLOW_FRM_P 0 + +/** Read the content of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_OFLOW_FRM(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB, ATON_STRENG_EVENT_EN_OFLOW_FRM_W) + +/** Modify the content of the EN_OFLOW_FRM field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_EN_OFLOW_FRM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB, ATON_STRENG_EVENT_EN_OFLOW_FRM_W, DATA) + + +/** + * Get the description of the EN_OFLOW_FRM field of EVENT register. + * + * \return the description of the EN_OFLOW_FRM field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_OFLOW_FRM_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_OFLOW_FRM_DESC; +} + + +/** + * Read the content of the EN_OFLOW_FRM field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_OFLOW_FRM field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_OFLOW_FRM(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_OFLOW_FRM(reg); +} + + +/** + * Write the content of the EN_OFLOW_FRM field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN_OFLOW_FRM field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_EN_OFLOW_FRM(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_EN_OFLOW_FRM(reg, data); +} + + +/* --------------------------------------------------------- EN_ILLCFG field of the EVENT register ---------------------------------------------------------- */ + +/** Description of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_DESC "Enable illegal configuration irq" + +/** Offset of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_LSB 20UL + +/** Size in bits of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_W (1UL) + +/** Mask for retrieving the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_DT 0x0UL + +/** Access rights of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_AC "RW" + +/** Check whether access to the EN_ILLCFG field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_S 0 + +/** Check whether access to the EN_ILLCFG field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_ILLCFG_P 0 + +/** Read the content of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_ILLCFG(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_ILLCFG_LSB, ATON_STRENG_EVENT_EN_ILLCFG_W) + +/** Modify the content of the EN_ILLCFG field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_EN_ILLCFG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_ILLCFG_LSB, ATON_STRENG_EVENT_EN_ILLCFG_W, DATA) + + +/** + * Get the description of the EN_ILLCFG field of EVENT register. + * + * \return the description of the EN_ILLCFG field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_ILLCFG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_ILLCFG_DESC; +} + + +/** + * Read the content of the EN_ILLCFG field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_ILLCFG field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_ILLCFG(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_ILLCFG(reg); +} + + +/** + * Write the content of the EN_ILLCFG field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN_ILLCFG field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_EN_ILLCFG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_EN_ILLCFG(reg, data); +} + + +/* ---------------------------------------------------------- EN_FMTMM field of the EVENT register ---------------------------------------------------------- */ + +/** Description of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_FMTMM_DESC "Enable format mismatch irq" + +/** Offset of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_FMTMM_LSB 21UL + +/** Size in bits of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_FMTMM_W (1UL) + +/** Mask for retrieving the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_FMTMM_MASK ATON_FIELD_MASK(21UL, 1UL) + +/** Reset value of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_FMTMM_DT 0x0UL + +/** Access rights of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_FMTMM_AC "RW" + +/** Check whether access to the EN_FMTMM field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_FMTMM_S 0 + +/** Check whether access to the EN_FMTMM field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_FMTMM_P 0 + +/** Read the content of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_FMTMM(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_FMTMM_LSB, ATON_STRENG_EVENT_EN_FMTMM_W) + +/** Modify the content of the EN_FMTMM field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_EN_FMTMM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_FMTMM_LSB, ATON_STRENG_EVENT_EN_FMTMM_W, DATA) + + +/** + * Get the description of the EN_FMTMM field of EVENT register. + * + * \return the description of the EN_FMTMM field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_FMTMM_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_FMTMM_DESC; +} + + +/** + * Read the content of the EN_FMTMM field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_FMTMM field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_FMTMM(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_FMTMM(reg); +} + + +/** + * Write the content of the EN_FMTMM field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN_FMTMM field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_EN_FMTMM(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_EN_FMTMM(reg, data); +} + + +/* -------------------------------------------------------- EN_CLRMSGRCV field of the EVENT register -------------------------------------------------------- */ + +/** Description of the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_DESC "Reserved" + +/** Offset of the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_LSB 22UL + +/** Size in bits of the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_W (1UL) + +/** Mask for retrieving the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_MASK ATON_FIELD_MASK(22UL, 1UL) + +/** Reset value of the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_DT 0x0UL + +/** Access rights of the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_AC "R" + +/** Check whether access to the EN_CLRMSGRCV field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_S 0 + +/** Check whether access to the EN_CLRMSGRCV field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_EN_CLRMSGRCV_P 0 + +/** Read the content of the EN_CLRMSGRCV field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_EN_CLRMSGRCV(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_CLRMSGRCV_LSB, ATON_STRENG_EVENT_EN_CLRMSGRCV_W) + + +/** + * Get the description of the EN_CLRMSGRCV field of EVENT register. + * + * \return the description of the EN_CLRMSGRCV field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_EN_CLRMSGRCV_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_EN_CLRMSGRCV_DESC; +} + + +/** + * Read the content of the EN_CLRMSGRCV field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the EN_CLRMSGRCV field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_EN_CLRMSGRCV(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_EN_CLRMSGRCV(reg); +} + + +/* --------------------------------------------------------- FRMTRG_EN field of the EVENT register ---------------------------------------------------------- */ + +/** Description of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_DESC "Enable synchronizations signals between engines (RO when CTRL.RUNNING)" + +/** Offset of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_LSB 23UL + +/** Size in bits of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_W (1UL) + +/** Mask for retrieving the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_DT 0x0UL + +/** Access rights of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_AC "RW" + +/** Check whether access to the FRMTRG_EN field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_S 0 + +/** Check whether access to the FRMTRG_EN field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_FRMTRG_EN_P 0 + +/** Read the content of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_FRMTRG_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_EN_LSB, ATON_STRENG_EVENT_FRMTRG_EN_W) + +/** Modify the content of the FRMTRG_EN field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_FRMTRG_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_EN_LSB, ATON_STRENG_EVENT_FRMTRG_EN_W, DATA) + + +/** + * Get the description of the FRMTRG_EN field of EVENT register. + * + * \return the description of the FRMTRG_EN field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_FRMTRG_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_FRMTRG_EN_DESC; +} + + +/** + * Read the content of the FRMTRG_EN field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the FRMTRG_EN field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_FRMTRG_EN(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_FRMTRG_EN(reg); +} + + +/** + * Write the content of the FRMTRG_EN field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FRMTRG_EN field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_FRMTRG_EN(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_FRMTRG_EN(reg, data); +} + + +/* --------------------------------------------------------- FRMTRG_SRC field of the EVENT register --------------------------------------------------------- */ + +/** Description of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_DESC "Synchronization signals source engine (RO when CTRL.RUNNING)" + +/** Offset of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_LSB 24UL + +/** Size in bits of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_W (5UL) + +/** Mask for retrieving the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_MASK ATON_FIELD_MASK(24UL, 5UL) + +/** Reset value of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_DT 0x0UL + +/** Access rights of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_AC "RW" + +/** Check whether access to the FRMTRG_SRC field of the EVENT register is secured or not. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_S 0 + +/** Check whether access to the FRMTRG_SRC field of the EVENT register is privileged or not. */ +#define ATON_STRENG_EVENT_FRMTRG_SRC_P 0 + +/** Read the content of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_GET_FRMTRG_SRC(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_SRC_LSB, ATON_STRENG_EVENT_FRMTRG_SRC_W) + +/** Modify the content of the FRMTRG_SRC field of the EVENT register. */ +#define ATON_STRENG_EVENT_SET_FRMTRG_SRC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_SRC_LSB, ATON_STRENG_EVENT_FRMTRG_SRC_W, DATA) + + +/** + * Get the description of the FRMTRG_SRC field of EVENT register. + * + * \return the description of the FRMTRG_SRC field of EVENT register + */ + +static inline const int8_t *ATON_STRENG_EVENT_FRMTRG_SRC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EVENT_FRMTRG_SRC_DESC; +} + + +/** + * Read the content of the FRMTRG_SRC field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * + * \return the content of the FRMTRG_SRC field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Get_FRMTRG_SRC(uint32_t reg) +{ + return ATON_STRENG_EVENT_GET_FRMTRG_SRC(reg); +} + + +/** + * Write the content of the FRMTRG_SRC field of the EVENT register. + * + * \param[in] reg is the value of the EVENT register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the FRMTRG_SRC field belonging to EVENT register + */ + +static inline uint32_t ATON_STRENG_EVENT_Set_FRMTRG_SRC(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EVENT_SET_FRMTRG_SRC(reg, data); +} + + +/* ****************************************************** STOPTAG register of one of the STRENG Units ******************************************************* */ + +/** Offset of the STOPTAG register from the base address of the STRENG Unit. */ +#define ATON_STRENG_STOPTAG_OFFSET 0x2cUL + +/** Reset value of the STOPTAG register of the STRENG Unit. */ +#define ATON_STRENG_STOPTAG_DT \ + (ATON_STRENG_STOPTAG_EN_DT << ATON_STRENG_STOPTAG_EN_LSB) | \ + (ATON_STRENG_STOPTAG_TAG_DT << ATON_STRENG_STOPTAG_TAG_LSB) + + + +/** Description of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_DESC "RAW file stop tag" + +/** Address of the STOPTAG register of one of the STRENG Units. */ +#define ATON_STRENG_STOPTAG_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_STOPTAG_OFFSET) + +/** Get the content of the STOPTAG register of one of the STRENG Units. */ +#define ATON_STRENG_STOPTAG_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_STOPTAG_ADDR(UNIT))) + +/** Set the content of the STOPTAG register of one of the STRENG Units. */ +#define ATON_STRENG_STOPTAG_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_STOPTAG_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of STOPTAG register. + * + * \return the description of STOPTAG register + */ + +static inline const int8_t *ATON_STRENG_STOPTAG_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_STOPTAG_DESC; +} + + +/** + * Get the offset of the STOPTAG register. + * + * \return the offset of STOPTAG register + */ + +static inline uint32_t ATON_STRENG_STOPTAG_GetOffset(void) +{ + return ATON_STRENG_STOPTAG_OFFSET; +} + + +/** + * Get the address of the STOPTAG register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STOPTAG register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of STOPTAG register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_STOPTAG_GetAddr(uint32_t instance) +{ + return ATON_STRENG_STOPTAG_ADDR(instance); +} + + +/** + * Read the content of the STOPTAG register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STOPTAG register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of STOPTAG register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_STOPTAG_Get(uint32_t instance) +{ + return ATON_STRENG_STOPTAG_GET(instance); +} + + +/** + * Write the content of the STOPTAG register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STOPTAG register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_STOPTAG_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_STOPTAG_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the STOPTAG register ------------------------------------------------------------ */ + +/** Description of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_EN_DESC "Enable RAW file stop tag (RO when CTRL.RUNNING)" + +/** Offset of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_EN_LSB 0UL + +/** Size in bits of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_EN_W (1UL) + +/** Mask for retrieving the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_EN_DT 0x0UL + +/** Access rights of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_EN_AC "RW" + +/** Check whether access to the EN field of the STOPTAG register is secured or not. */ +#define ATON_STRENG_STOPTAG_EN_S 0 + +/** Check whether access to the EN field of the STOPTAG register is privileged or not. */ +#define ATON_STRENG_STOPTAG_EN_P 0 + +/** Read the content of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_STOPTAG_EN_LSB, ATON_STRENG_STOPTAG_EN_W) + +/** Modify the content of the EN field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STOPTAG_EN_LSB, ATON_STRENG_STOPTAG_EN_W, DATA) + + +/** + * Get the description of the EN field of STOPTAG register. + * + * \return the description of the EN field of STOPTAG register + */ + +static inline const int8_t *ATON_STRENG_STOPTAG_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_STOPTAG_EN_DESC; +} + + +/** + * Read the content of the EN field of the STOPTAG register. + * + * \param[in] reg is the value of the STOPTAG register + * + * \return the content of the EN field belonging to STOPTAG register + */ + +static inline uint32_t ATON_STRENG_STOPTAG_Get_EN(uint32_t reg) +{ + return ATON_STRENG_STOPTAG_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the STOPTAG register. + * + * \param[in] reg is the value of the STOPTAG register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to STOPTAG register + */ + +static inline uint32_t ATON_STRENG_STOPTAG_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_STOPTAG_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- TAG field of the STOPTAG register ------------------------------------------------------------ */ + +/** Description of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_TAG_DESC "Stop tag (RO when CTRL.RUNNING)" + +/** Offset of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_TAG_LSB 16UL + +/** Size in bits of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_TAG_W (16UL) + +/** Mask for retrieving the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_TAG_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_TAG_DT 0xffd9UL + +/** Access rights of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_TAG_AC "RW" + +/** Check whether access to the TAG field of the STOPTAG register is secured or not. */ +#define ATON_STRENG_STOPTAG_TAG_S 0 + +/** Check whether access to the TAG field of the STOPTAG register is privileged or not. */ +#define ATON_STRENG_STOPTAG_TAG_P 0 + +/** Read the content of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_GET_TAG(REG) ATON_GET_FIELD(REG, ATON_STRENG_STOPTAG_TAG_LSB, ATON_STRENG_STOPTAG_TAG_W) + +/** Modify the content of the TAG field of the STOPTAG register. */ +#define ATON_STRENG_STOPTAG_SET_TAG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STOPTAG_TAG_LSB, ATON_STRENG_STOPTAG_TAG_W, DATA) + + +/** + * Get the description of the TAG field of STOPTAG register. + * + * \return the description of the TAG field of STOPTAG register + */ + +static inline const int8_t *ATON_STRENG_STOPTAG_TAG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_STOPTAG_TAG_DESC; +} + + +/** + * Read the content of the TAG field of the STOPTAG register. + * + * \param[in] reg is the value of the STOPTAG register + * + * \return the content of the TAG field belonging to STOPTAG register + */ + +static inline uint32_t ATON_STRENG_STOPTAG_Get_TAG(uint32_t reg) +{ + return ATON_STRENG_STOPTAG_GET_TAG(reg); +} + + +/** + * Write the content of the TAG field of the STOPTAG register. + * + * \param[in] reg is the value of the STOPTAG register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the TAG field belonging to STOPTAG register + */ + +static inline uint32_t ATON_STRENG_STOPTAG_Set_TAG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_STOPTAG_SET_TAG(reg, data); +} + + +/* ****************************************************** LIMITEN register of one of the STRENG Units ******************************************************* */ + +/** Offset of the LIMITEN register from the base address of the STRENG Unit. */ +#define ATON_STRENG_LIMITEN_OFFSET 0x30UL + +/** Reset value of the LIMITEN register of the STRENG Unit. */ +#define ATON_STRENG_LIMITEN_DT \ + (ATON_STRENG_LIMITEN_ADDRLIMIT_DT << ATON_STRENG_LIMITEN_ADDRLIMIT_LSB) | \ + (ATON_STRENG_LIMITEN_STOPPREFTC_DT << ATON_STRENG_LIMITEN_STOPPREFTC_LSB) | \ + (ATON_STRENG_LIMITEN_FRAMELIMIT_DT << ATON_STRENG_LIMITEN_FRAMELIMIT_LSB) | \ + (ATON_STRENG_LIMITEN_AUTOCLR_DT << ATON_STRENG_LIMITEN_AUTOCLR_LSB) | \ + (ATON_STRENG_LIMITEN_CLRMSGSENT_DT << ATON_STRENG_LIMITEN_CLRMSGSENT_LSB) | \ + (ATON_STRENG_LIMITEN_DOFF_MSB_DT << ATON_STRENG_LIMITEN_DOFF_MSB_LSB) + + + +/** Description of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DESC "Limiter enables" + +/** Address of the LIMITEN register of one of the STRENG Units. */ +#define ATON_STRENG_LIMITEN_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LIMITEN_OFFSET) + +/** Get the content of the LIMITEN register of one of the STRENG Units. */ +#define ATON_STRENG_LIMITEN_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITEN_ADDR(UNIT))) + +/** Set the content of the LIMITEN register of one of the STRENG Units. */ +#define ATON_STRENG_LIMITEN_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITEN_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of LIMITEN register. + * + * \return the description of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_DESC; +} + + +/** + * Get the offset of the LIMITEN register. + * + * \return the offset of LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_GetOffset(void) +{ + return ATON_STRENG_LIMITEN_OFFSET; +} + + +/** + * Get the address of the LIMITEN register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITEN register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of LIMITEN register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LIMITEN_GetAddr(uint32_t instance) +{ + return ATON_STRENG_LIMITEN_ADDR(instance); +} + + +/** + * Read the content of the LIMITEN register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITEN register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of LIMITEN register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get(uint32_t instance) +{ + return ATON_STRENG_LIMITEN_GET(instance); +} + + +/** + * Write the content of the LIMITEN register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITEN register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_LIMITEN_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_LIMITEN_SET(instance, data); +} + + +/* -------------------------------------------------------- ADDRLIMIT field of the LIMITEN register --------------------------------------------------------- */ + +/** Description of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_DESC "Address limiter enable (RO when CTRL.RUNNING)" + +/** Offset of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_LSB 0UL + +/** Size in bits of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_W (1UL) + +/** Mask for retrieving the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_DT 0x0UL + +/** Access rights of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_AC "RW" + +/** Check whether access to the ADDRLIMIT field of the LIMITEN register is secured or not. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_S 0 + +/** Check whether access to the ADDRLIMIT field of the LIMITEN register is privileged or not. */ +#define ATON_STRENG_LIMITEN_ADDRLIMIT_P 0 + +/** Read the content of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_GET_ADDRLIMIT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_ADDRLIMIT_LSB, ATON_STRENG_LIMITEN_ADDRLIMIT_W) + +/** Modify the content of the ADDRLIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_SET_ADDRLIMIT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_ADDRLIMIT_LSB, ATON_STRENG_LIMITEN_ADDRLIMIT_W, DATA) + + +/** + * Get the description of the ADDRLIMIT field of LIMITEN register. + * + * \return the description of the ADDRLIMIT field of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_ADDRLIMIT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_ADDRLIMIT_DESC; +} + + +/** + * Read the content of the ADDRLIMIT field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * + * \return the content of the ADDRLIMIT field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get_ADDRLIMIT(uint32_t reg) +{ + return ATON_STRENG_LIMITEN_GET_ADDRLIMIT(reg); +} + + +/** + * Write the content of the ADDRLIMIT field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ADDRLIMIT field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Set_ADDRLIMIT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMITEN_SET_ADDRLIMIT(reg, data); +} + + +/* -------------------------------------------------------- STOPPREFTC field of the LIMITEN register -------------------------------------------------------- */ + +/** Description of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_DESC "Address limiter stop prefetch (instead of error while in bus to stream direction) (RO when CTRL.RUNNING)" + +/** Offset of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_LSB 1UL + +/** Size in bits of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_W (1UL) + +/** Mask for retrieving the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_DT 0x1UL + +/** Access rights of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_AC "RW" + +/** Check whether access to the STOPPREFTC field of the LIMITEN register is secured or not. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_S 0 + +/** Check whether access to the STOPPREFTC field of the LIMITEN register is privileged or not. */ +#define ATON_STRENG_LIMITEN_STOPPREFTC_P 0 + +/** Read the content of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_GET_STOPPREFTC(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_STOPPREFTC_LSB, ATON_STRENG_LIMITEN_STOPPREFTC_W) + +/** Modify the content of the STOPPREFTC field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_SET_STOPPREFTC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_STOPPREFTC_LSB, ATON_STRENG_LIMITEN_STOPPREFTC_W, DATA) + + +/** + * Get the description of the STOPPREFTC field of LIMITEN register. + * + * \return the description of the STOPPREFTC field of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_STOPPREFTC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_STOPPREFTC_DESC; +} + + +/** + * Read the content of the STOPPREFTC field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * + * \return the content of the STOPPREFTC field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get_STOPPREFTC(uint32_t reg) +{ + return ATON_STRENG_LIMITEN_GET_STOPPREFTC(reg); +} + + +/** + * Write the content of the STOPPREFTC field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOPPREFTC field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Set_STOPPREFTC(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMITEN_SET_STOPPREFTC(reg, data); +} + + +/* -------------------------------------------------------- FRAMELIMIT field of the LIMITEN register -------------------------------------------------------- */ + +/** Description of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_DESC "Frame limiter enable (RO when CTRL.RUNNING)" + +/** Offset of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_LSB 2UL + +/** Size in bits of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_W (1UL) + +/** Mask for retrieving the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_DT 0x0UL + +/** Access rights of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_AC "RW" + +/** Check whether access to the FRAMELIMIT field of the LIMITEN register is secured or not. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_S 0 + +/** Check whether access to the FRAMELIMIT field of the LIMITEN register is privileged or not. */ +#define ATON_STRENG_LIMITEN_FRAMELIMIT_P 0 + +/** Read the content of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_GET_FRAMELIMIT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_FRAMELIMIT_LSB, ATON_STRENG_LIMITEN_FRAMELIMIT_W) + +/** Modify the content of the FRAMELIMIT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_SET_FRAMELIMIT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_FRAMELIMIT_LSB, ATON_STRENG_LIMITEN_FRAMELIMIT_W, DATA) + + +/** + * Get the description of the FRAMELIMIT field of LIMITEN register. + * + * \return the description of the FRAMELIMIT field of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_FRAMELIMIT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_FRAMELIMIT_DESC; +} + + +/** + * Read the content of the FRAMELIMIT field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * + * \return the content of the FRAMELIMIT field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get_FRAMELIMIT(uint32_t reg) +{ + return ATON_STRENG_LIMITEN_GET_FRAMELIMIT(reg); +} + + +/** + * Write the content of the FRAMELIMIT field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FRAMELIMIT field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Set_FRAMELIMIT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMITEN_SET_FRAMELIMIT(reg, data); +} + + +/* --------------------------------------------------------- AUTOCLR field of the LIMITEN register ---------------------------------------------------------- */ + +/** Description of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_DESC "If 1, trigger clear if limiter is hit (RO when CTRL.RUNNING)" + +/** Offset of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_LSB 3UL + +/** Size in bits of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_W (1UL) + +/** Mask for retrieving the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_DT 0x0UL + +/** Access rights of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_AC "RW" + +/** Check whether access to the AUTOCLR field of the LIMITEN register is secured or not. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_S 0 + +/** Check whether access to the AUTOCLR field of the LIMITEN register is privileged or not. */ +#define ATON_STRENG_LIMITEN_AUTOCLR_P 0 + +/** Read the content of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_GET_AUTOCLR(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_AUTOCLR_LSB, ATON_STRENG_LIMITEN_AUTOCLR_W) + +/** Modify the content of the AUTOCLR field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_SET_AUTOCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_AUTOCLR_LSB, ATON_STRENG_LIMITEN_AUTOCLR_W, DATA) + + +/** + * Get the description of the AUTOCLR field of LIMITEN register. + * + * \return the description of the AUTOCLR field of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_AUTOCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_AUTOCLR_DESC; +} + + +/** + * Read the content of the AUTOCLR field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * + * \return the content of the AUTOCLR field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get_AUTOCLR(uint32_t reg) +{ + return ATON_STRENG_LIMITEN_GET_AUTOCLR(reg); +} + + +/** + * Write the content of the AUTOCLR field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the AUTOCLR field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Set_AUTOCLR(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMITEN_SET_AUTOCLR(reg, data); +} + + +/* -------------------------------------------------------- CLRMSGSENT field of the LIMITEN register -------------------------------------------------------- */ + +/** Description of the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_DESC "Reserved" + +/** Offset of the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_LSB 8UL + +/** Size in bits of the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_W (1UL) + +/** Mask for retrieving the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_MASK ATON_FIELD_MASK(8UL, 1UL) + +/** Reset value of the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_DT 0x0UL + +/** Access rights of the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_AC "R" + +/** Check whether access to the CLRMSGSENT field of the LIMITEN register is secured or not. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_S 0 + +/** Check whether access to the CLRMSGSENT field of the LIMITEN register is privileged or not. */ +#define ATON_STRENG_LIMITEN_CLRMSGSENT_P 0 + +/** Read the content of the CLRMSGSENT field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_GET_CLRMSGSENT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_CLRMSGSENT_LSB, ATON_STRENG_LIMITEN_CLRMSGSENT_W) + + +/** + * Get the description of the CLRMSGSENT field of LIMITEN register. + * + * \return the description of the CLRMSGSENT field of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_CLRMSGSENT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_CLRMSGSENT_DESC; +} + + +/** + * Read the content of the CLRMSGSENT field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * + * \return the content of the CLRMSGSENT field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get_CLRMSGSENT(uint32_t reg) +{ + return ATON_STRENG_LIMITEN_GET_CLRMSGSENT(reg); +} + + +/* --------------------------------------------------------- DOFF_MSB field of the LIMITEN register --------------------------------------------------------- */ + +/** Description of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_DESC "MSB depth offset extension (RO when CTRL.RUNNING)" + +/** Offset of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_LSB 16UL + +/** Size in bits of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_W (16UL) + +/** Mask for retrieving the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_DT 0x0UL + +/** Access rights of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_AC "RW" + +/** Check whether access to the DOFF_MSB field of the LIMITEN register is secured or not. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_S 0 + +/** Check whether access to the DOFF_MSB field of the LIMITEN register is privileged or not. */ +#define ATON_STRENG_LIMITEN_DOFF_MSB_P 0 + +/** Read the content of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_GET_DOFF_MSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_DOFF_MSB_LSB, ATON_STRENG_LIMITEN_DOFF_MSB_W) + +/** Modify the content of the DOFF_MSB field of the LIMITEN register. */ +#define ATON_STRENG_LIMITEN_SET_DOFF_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_DOFF_MSB_LSB, ATON_STRENG_LIMITEN_DOFF_MSB_W, DATA) + + +/** + * Get the description of the DOFF_MSB field of LIMITEN register. + * + * \return the description of the DOFF_MSB field of LIMITEN register + */ + +static inline const int8_t *ATON_STRENG_LIMITEN_DOFF_MSB_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITEN_DOFF_MSB_DESC; +} + + +/** + * Read the content of the DOFF_MSB field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * + * \return the content of the DOFF_MSB field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Get_DOFF_MSB(uint32_t reg) +{ + return ATON_STRENG_LIMITEN_GET_DOFF_MSB(reg); +} + + +/** + * Write the content of the DOFF_MSB field of the LIMITEN register. + * + * \param[in] reg is the value of the LIMITEN register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the DOFF_MSB field belonging to LIMITEN register + */ + +static inline uint32_t ATON_STRENG_LIMITEN_Set_DOFF_MSB(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMITEN_SET_DOFF_MSB(reg, data); +} + + +/* ******************************************************* LIMIT register of one of the STRENG Units ******************************************************** */ + +/** Offset of the LIMIT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_LIMIT_OFFSET 0x34UL + +/** Reset value of the LIMIT register of the STRENG Unit. */ +#define ATON_STRENG_LIMIT_DT \ + (ATON_STRENG_LIMIT_CNT_DT << ATON_STRENG_LIMIT_CNT_LSB) + + + +/** Description of the LIMIT register. */ +#define ATON_STRENG_LIMIT_DESC "Limiter" + +/** Address of the LIMIT register of one of the STRENG Units. */ +#define ATON_STRENG_LIMIT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LIMIT_OFFSET) + +/** Get the content of the LIMIT register of one of the STRENG Units. */ +#define ATON_STRENG_LIMIT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMIT_ADDR(UNIT))) + +/** Set the content of the LIMIT register of one of the STRENG Units. */ +#define ATON_STRENG_LIMIT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMIT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of LIMIT register. + * + * \return the description of LIMIT register + */ + +static inline const int8_t *ATON_STRENG_LIMIT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMIT_DESC; +} + + +/** + * Get the offset of the LIMIT register. + * + * \return the offset of LIMIT register + */ + +static inline uint32_t ATON_STRENG_LIMIT_GetOffset(void) +{ + return ATON_STRENG_LIMIT_OFFSET; +} + + +/** + * Get the address of the LIMIT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMIT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of LIMIT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LIMIT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_LIMIT_ADDR(instance); +} + + +/** + * Read the content of the LIMIT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMIT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of LIMIT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LIMIT_Get(uint32_t instance) +{ + return ATON_STRENG_LIMIT_GET(instance); +} + + +/** + * Write the content of the LIMIT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMIT register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_LIMIT_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_LIMIT_SET(instance, data); +} + + +/* ------------------------------------------------------------ CNT field of the LIMIT register ------------------------------------------------------------- */ + +/** Description of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_CNT_DESC "Frame limit (RO when CTRL.RUNNING)" + +/** Offset of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_CNT_AC "RW" + +/** Check whether access to the CNT field of the LIMIT register is secured or not. */ +#define ATON_STRENG_LIMIT_CNT_S 0 + +/** Check whether access to the CNT field of the LIMIT register is privileged or not. */ +#define ATON_STRENG_LIMIT_CNT_P 0 + +/** Read the content of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMIT_CNT_LSB, ATON_STRENG_LIMIT_CNT_W) + +/** Modify the content of the CNT field of the LIMIT register. */ +#define ATON_STRENG_LIMIT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMIT_CNT_LSB, ATON_STRENG_LIMIT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of LIMIT register. + * + * \return the description of the CNT field of LIMIT register + */ + +static inline const int8_t *ATON_STRENG_LIMIT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMIT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the LIMIT register. + * + * \param[in] reg is the value of the LIMIT register + * + * \return the content of the CNT field belonging to LIMIT register + */ + +static inline uint32_t ATON_STRENG_LIMIT_Get_CNT(uint32_t reg) +{ + return ATON_STRENG_LIMIT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the LIMIT register. + * + * \param[in] reg is the value of the LIMIT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to LIMIT register + */ + +static inline uint32_t ATON_STRENG_LIMIT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMIT_SET_CNT(reg, data); +} + + +/* ***************************************************** LIMITADDR register of one of the STRENG Units ****************************************************** */ + +/** Offset of the LIMITADDR register from the base address of the STRENG Unit. */ +#define ATON_STRENG_LIMITADDR_OFFSET 0x38UL + +/** Reset value of the LIMITADDR register of the STRENG Unit. */ +#define ATON_STRENG_LIMITADDR_DT \ + (ATON_STRENG_LIMITADDR_REG_DT << ATON_STRENG_LIMITADDR_REG_LSB) + + + +/** Description of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_DESC "Limiter address" + +/** Address of the LIMITADDR register of one of the STRENG Units. */ +#define ATON_STRENG_LIMITADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LIMITADDR_OFFSET) + +/** Get the content of the LIMITADDR register of one of the STRENG Units. */ +#define ATON_STRENG_LIMITADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITADDR_ADDR(UNIT))) + +/** Set the content of the LIMITADDR register of one of the STRENG Units. */ +#define ATON_STRENG_LIMITADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITADDR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of LIMITADDR register. + * + * \return the description of LIMITADDR register + */ + +static inline const int8_t *ATON_STRENG_LIMITADDR_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITADDR_DESC; +} + + +/** + * Get the offset of the LIMITADDR register. + * + * \return the offset of LIMITADDR register + */ + +static inline uint32_t ATON_STRENG_LIMITADDR_GetOffset(void) +{ + return ATON_STRENG_LIMITADDR_OFFSET; +} + + +/** + * Get the address of the LIMITADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITADDR register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of LIMITADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LIMITADDR_GetAddr(uint32_t instance) +{ + return ATON_STRENG_LIMITADDR_ADDR(instance); +} + + +/** + * Read the content of the LIMITADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITADDR register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of LIMITADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LIMITADDR_Get(uint32_t instance) +{ + return ATON_STRENG_LIMITADDR_GET(instance); +} + + +/** + * Write the content of the LIMITADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITADDR register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_LIMITADDR_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_LIMITADDR_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the LIMITADDR register ----------------------------------------------------------- */ + +/** Description of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_REG_DESC "Limiter address, bits 2:0 are RO (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_REG_LSB 0UL + +/** Size in bits of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_REG_W (32UL) + +/** Mask for retrieving the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_REG_DT 0x0UL + +/** Access rights of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_REG_AC "RW" + +/** Check whether access to the REG field of the LIMITADDR register is secured or not. */ +#define ATON_STRENG_LIMITADDR_REG_S 0 + +/** Check whether access to the REG field of the LIMITADDR register is privileged or not. */ +#define ATON_STRENG_LIMITADDR_REG_P 0 + +/** Read the content of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITADDR_REG_LSB, ATON_STRENG_LIMITADDR_REG_W) + +/** Modify the content of the REG field of the LIMITADDR register. */ +#define ATON_STRENG_LIMITADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITADDR_REG_LSB, ATON_STRENG_LIMITADDR_REG_W, DATA) + + +/** + * Get the description of the REG field of LIMITADDR register. + * + * \return the description of the REG field of LIMITADDR register + */ + +static inline const int8_t *ATON_STRENG_LIMITADDR_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LIMITADDR_REG_DESC; +} + + +/** + * Read the content of the REG field of the LIMITADDR register. + * + * \param[in] reg is the value of the LIMITADDR register + * + * \return the content of the REG field belonging to LIMITADDR register + */ + +static inline uint32_t ATON_STRENG_LIMITADDR_Get_REG(uint32_t reg) +{ + return ATON_STRENG_LIMITADDR_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the LIMITADDR register. + * + * \param[in] reg is the value of the LIMITADDR register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to LIMITADDR register + */ + +static inline uint32_t ATON_STRENG_LIMITADDR_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_LIMITADDR_SET_REG(reg, data); +} + + +/* ******************************************************** IRQ register of one of the STRENG Units ********************************************************* */ + +/** Offset of the IRQ register from the base address of the STRENG Unit. */ +#define ATON_STRENG_IRQ_OFFSET 0x3cUL + +/** Reset value of the IRQ register of the STRENG Unit. */ +#define ATON_STRENG_IRQ_DT \ + (ATON_STRENG_IRQ_RAW_BUFBL_DT << ATON_STRENG_IRQ_RAW_BUFBL_LSB) | \ + (ATON_STRENG_IRQ_RAW_MRK_DT << ATON_STRENG_IRQ_RAW_MRK_LSB) | \ + (ATON_STRENG_IRQ_RAW_OFLOW_ADD_DT << ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB) | \ + (ATON_STRENG_IRQ_RAW_OFLOW_FRM_DT << ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB) | \ + (ATON_STRENG_IRQ_RAW_ILLCFG_DT << ATON_STRENG_IRQ_RAW_ILLCFG_LSB) | \ + (ATON_STRENG_IRQ_RAW_FMTMM_DT << ATON_STRENG_IRQ_RAW_FMTMM_LSB) | \ + (ATON_STRENG_IRQ_RAW_CLRMSGRCV_DT << ATON_STRENG_IRQ_RAW_CLRMSGRCV_LSB) + + + +/** Description of the IRQ register. */ +#define ATON_STRENG_IRQ_DESC "Events and interrupt enable" + +/** Address of the IRQ register of one of the STRENG Units. */ +#define ATON_STRENG_IRQ_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_IRQ_OFFSET) + +/** Get the content of the IRQ register of one of the STRENG Units. */ +#define ATON_STRENG_IRQ_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_IRQ_ADDR(UNIT))) + +/** Set the content of the IRQ register of one of the STRENG Units. */ +#define ATON_STRENG_IRQ_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_IRQ_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of IRQ register. + * + * \return the description of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_DESC; +} + + +/** + * Get the offset of the IRQ register. + * + * \return the offset of IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_GetOffset(void) +{ + return ATON_STRENG_IRQ_OFFSET; +} + + +/** + * Get the address of the IRQ register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the IRQ register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of IRQ register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_IRQ_GetAddr(uint32_t instance) +{ + return ATON_STRENG_IRQ_ADDR(instance); +} + + +/** + * Read the content of the IRQ register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the IRQ register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of IRQ register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_IRQ_Get(uint32_t instance) +{ + return ATON_STRENG_IRQ_GET(instance); +} + + +/** + * Write the content of the IRQ register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the IRQ register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_IRQ_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_IRQ_SET(instance, data); +} + + +/* ---------------------------------------------------------- RAW_BUFBL field of the IRQ register ----------------------------------------------------------- */ + +/** Description of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_DESC "Buffer bandwith limit hit (write 1 to clear irq, write 0 has no effects)" + +/** Offset of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_LSB 0UL + +/** Size in bits of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_W (1UL) + +/** Mask for retrieving the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_DT 0x0UL + +/** Access rights of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_AC "RW" + +/** Check whether access to the RAW_BUFBL field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_S 0 + +/** Check whether access to the RAW_BUFBL field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_BUFBL_P 0 + +/** Read the content of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_BUFBL(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_BUFBL_LSB, ATON_STRENG_IRQ_RAW_BUFBL_W) + +/** Modify the content of the RAW_BUFBL field of the IRQ register. */ +#define ATON_STRENG_IRQ_SET_RAW_BUFBL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_BUFBL_LSB, ATON_STRENG_IRQ_RAW_BUFBL_W, DATA) + + +/** + * Get the description of the RAW_BUFBL field of IRQ register. + * + * \return the description of the RAW_BUFBL field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_BUFBL_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_BUFBL_DESC; +} + + +/** + * Read the content of the RAW_BUFBL field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_BUFBL field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_BUFBL(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_BUFBL(reg); +} + + +/** + * Write the content of the RAW_BUFBL field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_BUFBL field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Set_RAW_BUFBL(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_IRQ_SET_RAW_BUFBL(reg, data); +} + + +/* ----------------------------------------------------------- RAW_MRK field of the IRQ register ------------------------------------------------------------ */ + +/** Description of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_MRK_DESC "Marker hit (write 1 to clear irq, write 0 has no effects)" + +/** Offset of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_MRK_LSB 1UL + +/** Size in bits of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_MRK_W (1UL) + +/** Mask for retrieving the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_MRK_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_MRK_DT 0x0UL + +/** Access rights of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_MRK_AC "RW" + +/** Check whether access to the RAW_MRK field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_MRK_S 0 + +/** Check whether access to the RAW_MRK field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_MRK_P 0 + +/** Read the content of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_MRK(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_MRK_LSB, ATON_STRENG_IRQ_RAW_MRK_W) + +/** Modify the content of the RAW_MRK field of the IRQ register. */ +#define ATON_STRENG_IRQ_SET_RAW_MRK(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_MRK_LSB, ATON_STRENG_IRQ_RAW_MRK_W, DATA) + + +/** + * Get the description of the RAW_MRK field of IRQ register. + * + * \return the description of the RAW_MRK field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_MRK_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_MRK_DESC; +} + + +/** + * Read the content of the RAW_MRK field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_MRK field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_MRK(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_MRK(reg); +} + + +/** + * Write the content of the RAW_MRK field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_MRK field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Set_RAW_MRK(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_IRQ_SET_RAW_MRK(reg, data); +} + + +/* -------------------------------------------------------- RAW_OFLOW_ADD field of the IRQ register --------------------------------------------------------- */ + +/** Description of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_DESC "Address limiter hit (write 1 to clear irq, write 0 has no effects)" + +/** Offset of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB 2UL + +/** Size in bits of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_W (1UL) + +/** Mask for retrieving the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_DT 0x0UL + +/** Access rights of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_AC "RW" + +/** Check whether access to the RAW_OFLOW_ADD field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_S 0 + +/** Check whether access to the RAW_OFLOW_ADD field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_ADD_P 0 + +/** Read the content of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_OFLOW_ADD(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB, ATON_STRENG_IRQ_RAW_OFLOW_ADD_W) + +/** Modify the content of the RAW_OFLOW_ADD field of the IRQ register. */ +#define ATON_STRENG_IRQ_SET_RAW_OFLOW_ADD(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB, ATON_STRENG_IRQ_RAW_OFLOW_ADD_W, DATA) + + +/** + * Get the description of the RAW_OFLOW_ADD field of IRQ register. + * + * \return the description of the RAW_OFLOW_ADD field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_OFLOW_ADD_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_OFLOW_ADD_DESC; +} + + +/** + * Read the content of the RAW_OFLOW_ADD field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_OFLOW_ADD field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_OFLOW_ADD(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_OFLOW_ADD(reg); +} + + +/** + * Write the content of the RAW_OFLOW_ADD field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_OFLOW_ADD field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Set_RAW_OFLOW_ADD(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_IRQ_SET_RAW_OFLOW_ADD(reg, data); +} + + +/* -------------------------------------------------------- RAW_OFLOW_FRM field of the IRQ register --------------------------------------------------------- */ + +/** Description of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_DESC "Frame limiter hit (write 1 to clear irq, write 0 has no effects)" + +/** Offset of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB 3UL + +/** Size in bits of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_W (1UL) + +/** Mask for retrieving the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_DT 0x0UL + +/** Access rights of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_AC "RW" + +/** Check whether access to the RAW_OFLOW_FRM field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_S 0 + +/** Check whether access to the RAW_OFLOW_FRM field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_OFLOW_FRM_P 0 + +/** Read the content of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_OFLOW_FRM(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB, ATON_STRENG_IRQ_RAW_OFLOW_FRM_W) + +/** Modify the content of the RAW_OFLOW_FRM field of the IRQ register. */ +#define ATON_STRENG_IRQ_SET_RAW_OFLOW_FRM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB, ATON_STRENG_IRQ_RAW_OFLOW_FRM_W, DATA) + + +/** + * Get the description of the RAW_OFLOW_FRM field of IRQ register. + * + * \return the description of the RAW_OFLOW_FRM field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_OFLOW_FRM_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_OFLOW_FRM_DESC; +} + + +/** + * Read the content of the RAW_OFLOW_FRM field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_OFLOW_FRM field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_OFLOW_FRM(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_OFLOW_FRM(reg); +} + + +/** + * Write the content of the RAW_OFLOW_FRM field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_OFLOW_FRM field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Set_RAW_OFLOW_FRM(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_IRQ_SET_RAW_OFLOW_FRM(reg, data); +} + + +/* ---------------------------------------------------------- RAW_ILLCFG field of the IRQ register ---------------------------------------------------------- */ + +/** Description of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_DESC "Illegal configuration (write 1 to clear irq, write 0 has no effects)" + +/** Offset of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_LSB 4UL + +/** Size in bits of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_W (1UL) + +/** Mask for retrieving the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_DT 0x0UL + +/** Access rights of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_AC "RW" + +/** Check whether access to the RAW_ILLCFG field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_S 0 + +/** Check whether access to the RAW_ILLCFG field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_ILLCFG_P 0 + +/** Read the content of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_ILLCFG(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_ILLCFG_LSB, ATON_STRENG_IRQ_RAW_ILLCFG_W) + +/** Modify the content of the RAW_ILLCFG field of the IRQ register. */ +#define ATON_STRENG_IRQ_SET_RAW_ILLCFG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_ILLCFG_LSB, ATON_STRENG_IRQ_RAW_ILLCFG_W, DATA) + + +/** + * Get the description of the RAW_ILLCFG field of IRQ register. + * + * \return the description of the RAW_ILLCFG field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_ILLCFG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_ILLCFG_DESC; +} + + +/** + * Read the content of the RAW_ILLCFG field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_ILLCFG field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_ILLCFG(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_ILLCFG(reg); +} + + +/** + * Write the content of the RAW_ILLCFG field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_ILLCFG field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Set_RAW_ILLCFG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_IRQ_SET_RAW_ILLCFG(reg, data); +} + + +/* ---------------------------------------------------------- RAW_FMTMM field of the IRQ register ----------------------------------------------------------- */ + +/** Description of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_DESC "Format mismatch (write 1 to clear irq, write 0 has no effects)" + +/** Offset of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_LSB 5UL + +/** Size in bits of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_W (1UL) + +/** Mask for retrieving the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_DT 0x0UL + +/** Access rights of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_AC "RW" + +/** Check whether access to the RAW_FMTMM field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_S 0 + +/** Check whether access to the RAW_FMTMM field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_FMTMM_P 0 + +/** Read the content of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_FMTMM(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_FMTMM_LSB, ATON_STRENG_IRQ_RAW_FMTMM_W) + +/** Modify the content of the RAW_FMTMM field of the IRQ register. */ +#define ATON_STRENG_IRQ_SET_RAW_FMTMM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_FMTMM_LSB, ATON_STRENG_IRQ_RAW_FMTMM_W, DATA) + + +/** + * Get the description of the RAW_FMTMM field of IRQ register. + * + * \return the description of the RAW_FMTMM field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_FMTMM_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_FMTMM_DESC; +} + + +/** + * Read the content of the RAW_FMTMM field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_FMTMM field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_FMTMM(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_FMTMM(reg); +} + + +/** + * Write the content of the RAW_FMTMM field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW_FMTMM field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Set_RAW_FMTMM(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_IRQ_SET_RAW_FMTMM(reg, data); +} + + +/* -------------------------------------------------------- RAW_CLRMSGRCV field of the IRQ register --------------------------------------------------------- */ + +/** Description of the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_DESC "Reserved" + +/** Offset of the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_LSB 6UL + +/** Size in bits of the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_W (1UL) + +/** Mask for retrieving the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_MASK ATON_FIELD_MASK(6UL, 1UL) + +/** Reset value of the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_DT 0x0UL + +/** Access rights of the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_AC "R" + +/** Check whether access to the RAW_CLRMSGRCV field of the IRQ register is secured or not. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_S 0 + +/** Check whether access to the RAW_CLRMSGRCV field of the IRQ register is privileged or not. */ +#define ATON_STRENG_IRQ_RAW_CLRMSGRCV_P 0 + +/** Read the content of the RAW_CLRMSGRCV field of the IRQ register. */ +#define ATON_STRENG_IRQ_GET_RAW_CLRMSGRCV(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_CLRMSGRCV_LSB, ATON_STRENG_IRQ_RAW_CLRMSGRCV_W) + + +/** + * Get the description of the RAW_CLRMSGRCV field of IRQ register. + * + * \return the description of the RAW_CLRMSGRCV field of IRQ register + */ + +static inline const int8_t *ATON_STRENG_IRQ_RAW_CLRMSGRCV_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_IRQ_RAW_CLRMSGRCV_DESC; +} + + +/** + * Read the content of the RAW_CLRMSGRCV field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the RAW_CLRMSGRCV field belonging to IRQ register + */ + +static inline uint32_t ATON_STRENG_IRQ_Get_RAW_CLRMSGRCV(uint32_t reg) +{ + return ATON_STRENG_IRQ_GET_RAW_CLRMSGRCV(reg); +} + + +/* ****************************************************** ENCR_LSB register of one of the STRENG Units ****************************************************** */ + +/** Offset of the ENCR_LSB register from the base address of the STRENG Unit. */ +#define ATON_STRENG_ENCR_LSB_OFFSET 0x40UL + +/** Reset value of the ENCR_LSB register of the STRENG Unit. */ +#define ATON_STRENG_ENCR_LSB_DT \ + (ATON_STRENG_ENCR_LSB_ID_LSB_DT << ATON_STRENG_ENCR_LSB_ID_LSB_LSB) + + + +/** Description of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" + +/** Address of the ENCR_LSB register of one of the STRENG Units. */ +#define ATON_STRENG_ENCR_LSB_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_ENCR_LSB_OFFSET) + +/** Get the content of the ENCR_LSB register of one of the STRENG Units. */ +#define ATON_STRENG_ENCR_LSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_LSB_ADDR(UNIT))) + +/** Set the content of the ENCR_LSB register of one of the STRENG Units. */ +#define ATON_STRENG_ENCR_LSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_LSB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ENCR_LSB register. + * + * \return the description of ENCR_LSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_LSB_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_LSB_DESC; +} + + +/** + * Get the offset of the ENCR_LSB register. + * + * \return the offset of ENCR_LSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_LSB_GetOffset(void) +{ + return ATON_STRENG_ENCR_LSB_OFFSET; +} + + +/** + * Get the address of the ENCR_LSB register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_LSB register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of ENCR_LSB register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_ENCR_LSB_GetAddr(uint32_t instance) +{ + return ATON_STRENG_ENCR_LSB_ADDR(instance); +} + + +/** + * Read the content of the ENCR_LSB register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_LSB register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of ENCR_LSB register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_ENCR_LSB_Get(uint32_t instance) +{ + return ATON_STRENG_ENCR_LSB_GET(instance); +} + + +/** + * Write the content of the ENCR_LSB register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_LSB register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_ENCR_LSB_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_ENCR_LSB_SET(instance, data); +} + + +/* --------------------------------------------------------- ID_LSB field of the ENCR_LSB register ---------------------------------------------------------- */ + +/** Description of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" + +/** Offset of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_LSB 0UL + +/** Size in bits of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_W (32UL) + +/** Mask for retrieving the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_DT 0x0UL + +/** Access rights of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_AC "RW" + +/** Check whether access to the ID_LSB field of the ENCR_LSB register is secured or not. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_S 0 + +/** Check whether access to the ID_LSB field of the ENCR_LSB register is privileged or not. */ +#define ATON_STRENG_ENCR_LSB_ID_LSB_P 0 + +/** Read the content of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_GET_ID_LSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_LSB_ID_LSB_LSB, ATON_STRENG_ENCR_LSB_ID_LSB_W) + +/** Modify the content of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_STRENG_ENCR_LSB_SET_ID_LSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_LSB_ID_LSB_LSB, ATON_STRENG_ENCR_LSB_ID_LSB_W, DATA) + + +/** + * Get the description of the ID_LSB field of ENCR_LSB register. + * + * \return the description of the ID_LSB field of ENCR_LSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_LSB_ID_LSB_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_LSB_ID_LSB_DESC; +} + + +/** + * Read the content of the ID_LSB field of the ENCR_LSB register. + * + * \param[in] reg is the value of the ENCR_LSB register + * + * \return the content of the ID_LSB field belonging to ENCR_LSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_LSB_Get_ID_LSB(uint32_t reg) +{ + return ATON_STRENG_ENCR_LSB_GET_ID_LSB(reg); +} + + +/** + * Write the content of the ID_LSB field of the ENCR_LSB register. + * + * \param[in] reg is the value of the ENCR_LSB register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the ID_LSB field belonging to ENCR_LSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_LSB_Set_ID_LSB(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ENCR_LSB_SET_ID_LSB(reg, data); +} + + +/* ****************************************************** ENCR_MSB register of one of the STRENG Units ****************************************************** */ + +/** Offset of the ENCR_MSB register from the base address of the STRENG Unit. */ +#define ATON_STRENG_ENCR_MSB_OFFSET 0x44UL + +/** Reset value of the ENCR_MSB register of the STRENG Unit. */ +#define ATON_STRENG_ENCR_MSB_DT \ + (ATON_STRENG_ENCR_MSB_ID_MSB_DT << ATON_STRENG_ENCR_MSB_ID_MSB_LSB) | \ + (ATON_STRENG_ENCR_MSB_EN_DT << ATON_STRENG_ENCR_MSB_EN_LSB) | \ + (ATON_STRENG_ENCR_MSB_ROUNDS_DT << ATON_STRENG_ENCR_MSB_ROUNDS_LSB) | \ + (ATON_STRENG_ENCR_MSB_KEY_SEL_DT << ATON_STRENG_ENCR_MSB_KEY_SEL_LSB) | \ + (ATON_STRENG_ENCR_MSB_INC_DT << ATON_STRENG_ENCR_MSB_INC_LSB) + + + +/** Description of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" + +/** Address of the ENCR_MSB register of one of the STRENG Units. */ +#define ATON_STRENG_ENCR_MSB_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_ENCR_MSB_OFFSET) + +/** Get the content of the ENCR_MSB register of one of the STRENG Units. */ +#define ATON_STRENG_ENCR_MSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_MSB_ADDR(UNIT))) + +/** Set the content of the ENCR_MSB register of one of the STRENG Units. */ +#define ATON_STRENG_ENCR_MSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_MSB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ENCR_MSB register. + * + * \return the description of ENCR_MSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_MSB_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_MSB_DESC; +} + + +/** + * Get the offset of the ENCR_MSB register. + * + * \return the offset of ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_GetOffset(void) +{ + return ATON_STRENG_ENCR_MSB_OFFSET; +} + + +/** + * Get the address of the ENCR_MSB register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_MSB register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of ENCR_MSB register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_GetAddr(uint32_t instance) +{ + return ATON_STRENG_ENCR_MSB_ADDR(instance); +} + + +/** + * Read the content of the ENCR_MSB register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_MSB register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of ENCR_MSB register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Get(uint32_t instance) +{ + return ATON_STRENG_ENCR_MSB_GET(instance); +} + + +/** + * Write the content of the ENCR_MSB register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_MSB register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_ENCR_MSB_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_ENCR_MSB_SET(instance, data); +} + + +/* --------------------------------------------------------- ID_MSB field of the ENCR_MSB register ---------------------------------------------------------- */ + +/** Description of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" + +/** Offset of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_LSB 0UL + +/** Size in bits of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_W (11UL) + +/** Mask for retrieving the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_MASK ATON_FIELD_MASK(0UL, 11UL) + +/** Reset value of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_DT 0x0UL + +/** Access rights of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_AC "RW" + +/** Check whether access to the ID_MSB field of the ENCR_MSB register is secured or not. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_S 0 + +/** Check whether access to the ID_MSB field of the ENCR_MSB register is privileged or not. */ +#define ATON_STRENG_ENCR_MSB_ID_MSB_P 0 + +/** Read the content of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_GET_ID_MSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_ID_MSB_LSB, ATON_STRENG_ENCR_MSB_ID_MSB_W) + +/** Modify the content of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_SET_ID_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ID_MSB_LSB, ATON_STRENG_ENCR_MSB_ID_MSB_W, DATA) + + +/** + * Get the description of the ID_MSB field of ENCR_MSB register. + * + * \return the description of the ID_MSB field of ENCR_MSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_MSB_ID_MSB_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_MSB_ID_MSB_DESC; +} + + +/** + * Read the content of the ID_MSB field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the ID_MSB field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Get_ID_MSB(uint32_t reg) +{ + return ATON_STRENG_ENCR_MSB_GET_ID_MSB(reg); +} + + +/** + * Write the content of the ID_MSB field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 11-bit value that must be written to the field + * + * \return the new content of the ID_MSB field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Set_ID_MSB(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ENCR_MSB_SET_ID_MSB(reg, data); +} + + +/* ----------------------------------------------------------- EN field of the ENCR_MSB register ------------------------------------------------------------ */ + +/** Description of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_EN_DESC "Encryption enable (RO when CTRL.RUNNING)" + +/** Offset of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_EN_LSB 12UL + +/** Size in bits of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_EN_W (1UL) + +/** Mask for retrieving the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_EN_MASK ATON_FIELD_MASK(12UL, 1UL) + +/** Reset value of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_EN_DT 0x0UL + +/** Access rights of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_EN_AC "RW" + +/** Check whether access to the EN field of the ENCR_MSB register is secured or not. */ +#define ATON_STRENG_ENCR_MSB_EN_S 0 + +/** Check whether access to the EN field of the ENCR_MSB register is privileged or not. */ +#define ATON_STRENG_ENCR_MSB_EN_P 0 + +/** Read the content of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_EN_LSB, ATON_STRENG_ENCR_MSB_EN_W) + +/** Modify the content of the EN field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_EN_LSB, ATON_STRENG_ENCR_MSB_EN_W, DATA) + + +/** + * Get the description of the EN field of ENCR_MSB register. + * + * \return the description of the EN field of ENCR_MSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_MSB_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_MSB_EN_DESC; +} + + +/** + * Read the content of the EN field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the EN field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Get_EN(uint32_t reg) +{ + return ATON_STRENG_ENCR_MSB_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ENCR_MSB_SET_EN(reg, data); +} + + +/* --------------------------------------------------------- ROUNDS field of the ENCR_MSB register ---------------------------------------------------------- */ + +/** Description of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_DESC "Encryption number of rounds: 0->12, 1->9 (RO when CTRL.RUNNING)" + +/** Offset of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_LSB 13UL + +/** Size in bits of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_W (1UL) + +/** Mask for retrieving the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_MASK ATON_FIELD_MASK(13UL, 1UL) + +/** Reset value of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_DT 0x0UL + +/** Access rights of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_AC "RW" + +/** Check whether access to the ROUNDS field of the ENCR_MSB register is secured or not. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_S 0 + +/** Check whether access to the ROUNDS field of the ENCR_MSB register is privileged or not. */ +#define ATON_STRENG_ENCR_MSB_ROUNDS_P 0 + +/** Read the content of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_GET_ROUNDS(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_ROUNDS_LSB, ATON_STRENG_ENCR_MSB_ROUNDS_W) + +/** Modify the content of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_SET_ROUNDS(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ROUNDS_LSB, ATON_STRENG_ENCR_MSB_ROUNDS_W, DATA) + + +/** + * Get the description of the ROUNDS field of ENCR_MSB register. + * + * \return the description of the ROUNDS field of ENCR_MSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_MSB_ROUNDS_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_MSB_ROUNDS_DESC; +} + + +/** + * Read the content of the ROUNDS field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the ROUNDS field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Get_ROUNDS(uint32_t reg) +{ + return ATON_STRENG_ENCR_MSB_GET_ROUNDS(reg); +} + + +/** + * Write the content of the ROUNDS field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUNDS field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Set_ROUNDS(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ENCR_MSB_SET_ROUNDS(reg, data); +} + + +/* --------------------------------------------------------- KEY_SEL field of the ENCR_MSB register --------------------------------------------------------- */ + +/** Description of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_DESC "Encryption key selection (RO when CTRL.RUNNING)" + +/** Offset of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_LSB 14UL + +/** Size in bits of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_W (2UL) + +/** Mask for retrieving the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_DT 0x0UL + +/** Access rights of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_AC "RW" + +/** Check whether access to the KEY_SEL field of the ENCR_MSB register is secured or not. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_S 0 + +/** Check whether access to the KEY_SEL field of the ENCR_MSB register is privileged or not. */ +#define ATON_STRENG_ENCR_MSB_KEY_SEL_P 0 + +/** Read the content of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_GET_KEY_SEL(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_KEY_SEL_LSB, ATON_STRENG_ENCR_MSB_KEY_SEL_W) + +/** Modify the content of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_SET_KEY_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_KEY_SEL_LSB, ATON_STRENG_ENCR_MSB_KEY_SEL_W, DATA) + + +/** + * Get the description of the KEY_SEL field of ENCR_MSB register. + * + * \return the description of the KEY_SEL field of ENCR_MSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_MSB_KEY_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_MSB_KEY_SEL_DESC; +} + + +/** + * Read the content of the KEY_SEL field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the KEY_SEL field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Get_KEY_SEL(uint32_t reg) +{ + return ATON_STRENG_ENCR_MSB_GET_KEY_SEL(reg); +} + + +/** + * Write the content of the KEY_SEL field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the KEY_SEL field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Set_KEY_SEL(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ENCR_MSB_SET_KEY_SEL(reg, data); +} + + +/* ----------------------------------------------------------- INC field of the ENCR_MSB register ----------------------------------------------------------- */ + +/** Description of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_INC_DESC "Encryption ID increment rate: 0 -> no increment, -> +1 every n frames (RO when CTRL.RUNNING)" + +/** Offset of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_INC_LSB 16UL + +/** Size in bits of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_INC_W (16UL) + +/** Mask for retrieving the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_INC_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_INC_DT 0x0UL + +/** Access rights of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_INC_AC "RW" + +/** Check whether access to the INC field of the ENCR_MSB register is secured or not. */ +#define ATON_STRENG_ENCR_MSB_INC_S 0 + +/** Check whether access to the INC field of the ENCR_MSB register is privileged or not. */ +#define ATON_STRENG_ENCR_MSB_INC_P 0 + +/** Read the content of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_GET_INC(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_INC_LSB, ATON_STRENG_ENCR_MSB_INC_W) + +/** Modify the content of the INC field of the ENCR_MSB register. */ +#define ATON_STRENG_ENCR_MSB_SET_INC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_INC_LSB, ATON_STRENG_ENCR_MSB_INC_W, DATA) + + +/** + * Get the description of the INC field of ENCR_MSB register. + * + * \return the description of the INC field of ENCR_MSB register + */ + +static inline const int8_t *ATON_STRENG_ENCR_MSB_INC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_ENCR_MSB_INC_DESC; +} + + +/** + * Read the content of the INC field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the INC field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Get_INC(uint32_t reg) +{ + return ATON_STRENG_ENCR_MSB_GET_INC(reg); +} + + +/** + * Write the content of the INC field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the INC field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_STRENG_ENCR_MSB_Set_INC(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_ENCR_MSB_SET_INC(reg, data); +} + + +/* ***************************************************** CID_CACHE register of one of the STRENG Units ****************************************************** */ + +/** Offset of the CID_CACHE register from the base address of the STRENG Unit. */ +#define ATON_STRENG_CID_CACHE_OFFSET 0x48UL + +/** Reset value of the CID_CACHE register of the STRENG Unit. */ +#define ATON_STRENG_CID_CACHE_DT \ + (ATON_STRENG_CID_CACHE_CID_DT << ATON_STRENG_CID_CACHE_CID_LSB) | \ + (ATON_STRENG_CID_CACHE_CACHEABLE_DT << ATON_STRENG_CID_CACHE_CACHEABLE_LSB) | \ + (ATON_STRENG_CID_CACHE_ALLOC_DT << ATON_STRENG_CID_CACHE_ALLOC_LSB) | \ + (ATON_STRENG_CID_CACHE_PFETCH_DT << ATON_STRENG_CID_CACHE_PFETCH_LSB) | \ + (ATON_STRENG_CID_CACHE_LINESIZE_DT << ATON_STRENG_CID_CACHE_LINESIZE_LSB) | \ + (ATON_STRENG_CID_CACHE_LOFF_MSB_DT << ATON_STRENG_CID_CACHE_LOFF_MSB_LSB) + + + +/** Description of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_DESC "Compartment ID / Cache register (RO when CTRL.RUNNING)" + +/** Address of the CID_CACHE register of one of the STRENG Units. */ +#define ATON_STRENG_CID_CACHE_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_CID_CACHE_OFFSET) + +/** Get the content of the CID_CACHE register of one of the STRENG Units. */ +#define ATON_STRENG_CID_CACHE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_CID_CACHE_ADDR(UNIT))) + +/** Set the content of the CID_CACHE register of one of the STRENG Units. */ +#define ATON_STRENG_CID_CACHE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_CID_CACHE_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CID_CACHE register. + * + * \return the description of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_DESC; +} + + +/** + * Get the offset of the CID_CACHE register. + * + * \return the offset of CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_GetOffset(void) +{ + return ATON_STRENG_CID_CACHE_OFFSET; +} + + +/** + * Get the address of the CID_CACHE register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CID_CACHE register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of CID_CACHE register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_GetAddr(uint32_t instance) +{ + return ATON_STRENG_CID_CACHE_ADDR(instance); +} + + +/** + * Read the content of the CID_CACHE register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CID_CACHE register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of CID_CACHE register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get(uint32_t instance) +{ + return ATON_STRENG_CID_CACHE_GET(instance); +} + + +/** + * Write the content of the CID_CACHE register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CID_CACHE register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_CID_CACHE_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_CID_CACHE_SET(instance, data); +} + + +/* ---------------------------------------------------------- CID field of the CID_CACHE register ----------------------------------------------------------- */ + +/** Description of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CID_DESC "Compartment ID (RO when CTRL.RUNNING)" + +/** Offset of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CID_LSB 0UL + +/** Size in bits of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CID_W (3UL) + +/** Mask for retrieving the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CID_MASK ATON_FIELD_MASK(0UL, 3UL) + +/** Reset value of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CID_DT 0x0UL + +/** Access rights of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CID_AC "RW" + +/** Check whether access to the CID field of the CID_CACHE register is secured or not. */ +#define ATON_STRENG_CID_CACHE_CID_S 0 + +/** Check whether access to the CID field of the CID_CACHE register is privileged or not. */ +#define ATON_STRENG_CID_CACHE_CID_P 0 + +/** Read the content of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_GET_CID(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_CID_LSB, ATON_STRENG_CID_CACHE_CID_W) + +/** Modify the content of the CID field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_SET_CID(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_CID_LSB, ATON_STRENG_CID_CACHE_CID_W, DATA) + + +/** + * Get the description of the CID field of CID_CACHE register. + * + * \return the description of the CID field of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_CID_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_CID_DESC; +} + + +/** + * Read the content of the CID field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the CID field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get_CID(uint32_t reg) +{ + return ATON_STRENG_CID_CACHE_GET_CID(reg); +} + + +/** + * Write the content of the CID field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the CID field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Set_CID(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CID_CACHE_SET_CID(reg, data); +} + + +/* ------------------------------------------------------- CACHEABLE field of the CID_CACHE register -------------------------------------------------------- */ + +/** Description of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_DESC "Cacheable (RO when CTRL.RUNNING)" + +/** Offset of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_LSB 3UL + +/** Size in bits of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_W (1UL) + +/** Mask for retrieving the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_DT 0x0UL + +/** Access rights of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_AC "RW" + +/** Check whether access to the CACHEABLE field of the CID_CACHE register is secured or not. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_S 0 + +/** Check whether access to the CACHEABLE field of the CID_CACHE register is privileged or not. */ +#define ATON_STRENG_CID_CACHE_CACHEABLE_P 0 + +/** Read the content of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_GET_CACHEABLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_CACHEABLE_LSB, ATON_STRENG_CID_CACHE_CACHEABLE_W) + +/** Modify the content of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_SET_CACHEABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_CACHEABLE_LSB, ATON_STRENG_CID_CACHE_CACHEABLE_W, DATA) + + +/** + * Get the description of the CACHEABLE field of CID_CACHE register. + * + * \return the description of the CACHEABLE field of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_CACHEABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_CACHEABLE_DESC; +} + + +/** + * Read the content of the CACHEABLE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the CACHEABLE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get_CACHEABLE(uint32_t reg) +{ + return ATON_STRENG_CID_CACHE_GET_CACHEABLE(reg); +} + + +/** + * Write the content of the CACHEABLE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CACHEABLE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Set_CACHEABLE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CID_CACHE_SET_CACHEABLE(reg, data); +} + + +/* --------------------------------------------------------- ALLOC field of the CID_CACHE register ---------------------------------------------------------- */ + +/** Description of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_ALLOC_DESC "Allocate (RO when CTRL.RUNNING)" + +/** Offset of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_ALLOC_LSB 4UL + +/** Size in bits of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_ALLOC_W (1UL) + +/** Mask for retrieving the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_ALLOC_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_ALLOC_DT 0x0UL + +/** Access rights of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_ALLOC_AC "RW" + +/** Check whether access to the ALLOC field of the CID_CACHE register is secured or not. */ +#define ATON_STRENG_CID_CACHE_ALLOC_S 0 + +/** Check whether access to the ALLOC field of the CID_CACHE register is privileged or not. */ +#define ATON_STRENG_CID_CACHE_ALLOC_P 0 + +/** Read the content of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_GET_ALLOC(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_ALLOC_LSB, ATON_STRENG_CID_CACHE_ALLOC_W) + +/** Modify the content of the ALLOC field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_SET_ALLOC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_ALLOC_LSB, ATON_STRENG_CID_CACHE_ALLOC_W, DATA) + + +/** + * Get the description of the ALLOC field of CID_CACHE register. + * + * \return the description of the ALLOC field of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_ALLOC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_ALLOC_DESC; +} + + +/** + * Read the content of the ALLOC field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the ALLOC field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get_ALLOC(uint32_t reg) +{ + return ATON_STRENG_CID_CACHE_GET_ALLOC(reg); +} + + +/** + * Write the content of the ALLOC field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ALLOC field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Set_ALLOC(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CID_CACHE_SET_ALLOC(reg, data); +} + + +/* --------------------------------------------------------- PFETCH field of the CID_CACHE register --------------------------------------------------------- */ + +/** Description of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_PFETCH_DESC "Prefetch (RO when CTRL.RUNNING)" + +/** Offset of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_PFETCH_LSB 5UL + +/** Size in bits of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_PFETCH_W (1UL) + +/** Mask for retrieving the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_PFETCH_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_PFETCH_DT 0x0UL + +/** Access rights of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_PFETCH_AC "RW" + +/** Check whether access to the PFETCH field of the CID_CACHE register is secured or not. */ +#define ATON_STRENG_CID_CACHE_PFETCH_S 0 + +/** Check whether access to the PFETCH field of the CID_CACHE register is privileged or not. */ +#define ATON_STRENG_CID_CACHE_PFETCH_P 0 + +/** Read the content of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_GET_PFETCH(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_PFETCH_LSB, ATON_STRENG_CID_CACHE_PFETCH_W) + +/** Modify the content of the PFETCH field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_SET_PFETCH(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_PFETCH_LSB, ATON_STRENG_CID_CACHE_PFETCH_W, DATA) + + +/** + * Get the description of the PFETCH field of CID_CACHE register. + * + * \return the description of the PFETCH field of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_PFETCH_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_PFETCH_DESC; +} + + +/** + * Read the content of the PFETCH field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the PFETCH field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get_PFETCH(uint32_t reg) +{ + return ATON_STRENG_CID_CACHE_GET_PFETCH(reg); +} + + +/** + * Write the content of the PFETCH field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the PFETCH field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Set_PFETCH(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CID_CACHE_SET_PFETCH(reg, data); +} + + +/* -------------------------------------------------------- LINESIZE field of the CID_CACHE register -------------------------------------------------------- */ + +/** Description of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_DESC "Line size: 0 -> 64B, 1 -> 128B, 2 -> 256B, 3 -> 512B (RO when CTRL.RUNNING)" + +/** Offset of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_LSB 6UL + +/** Size in bits of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_W (2UL) + +/** Mask for retrieving the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_MASK ATON_FIELD_MASK(6UL, 2UL) + +/** Reset value of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_DT 0x0UL + +/** Access rights of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_AC "RW" + +/** Check whether access to the LINESIZE field of the CID_CACHE register is secured or not. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_S 0 + +/** Check whether access to the LINESIZE field of the CID_CACHE register is privileged or not. */ +#define ATON_STRENG_CID_CACHE_LINESIZE_P 0 + +/** Read the content of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_GET_LINESIZE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_LINESIZE_LSB, ATON_STRENG_CID_CACHE_LINESIZE_W) + +/** Modify the content of the LINESIZE field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_SET_LINESIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_LINESIZE_LSB, ATON_STRENG_CID_CACHE_LINESIZE_W, DATA) + + +/** + * Get the description of the LINESIZE field of CID_CACHE register. + * + * \return the description of the LINESIZE field of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_LINESIZE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_LINESIZE_DESC; +} + + +/** + * Read the content of the LINESIZE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the LINESIZE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get_LINESIZE(uint32_t reg) +{ + return ATON_STRENG_CID_CACHE_GET_LINESIZE(reg); +} + + +/** + * Write the content of the LINESIZE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the LINESIZE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Set_LINESIZE(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CID_CACHE_SET_LINESIZE(reg, data); +} + + +/* -------------------------------------------------------- LOFF_MSB field of the CID_CACHE register -------------------------------------------------------- */ + +/** Description of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_DESC "MSB line offset extension (RO when CTRL.RUNNING)" + +/** Offset of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_LSB 16UL + +/** Size in bits of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_W (16UL) + +/** Mask for retrieving the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_DT 0x0UL + +/** Access rights of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_AC "RW" + +/** Check whether access to the LOFF_MSB field of the CID_CACHE register is secured or not. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_S 0 + +/** Check whether access to the LOFF_MSB field of the CID_CACHE register is privileged or not. */ +#define ATON_STRENG_CID_CACHE_LOFF_MSB_P 0 + +/** Read the content of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_GET_LOFF_MSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_LOFF_MSB_LSB, ATON_STRENG_CID_CACHE_LOFF_MSB_W) + +/** Modify the content of the LOFF_MSB field of the CID_CACHE register. */ +#define ATON_STRENG_CID_CACHE_SET_LOFF_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_LOFF_MSB_LSB, ATON_STRENG_CID_CACHE_LOFF_MSB_W, DATA) + + +/** + * Get the description of the LOFF_MSB field of CID_CACHE register. + * + * \return the description of the LOFF_MSB field of CID_CACHE register + */ + +static inline const int8_t *ATON_STRENG_CID_CACHE_LOFF_MSB_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_CID_CACHE_LOFF_MSB_DESC; +} + + +/** + * Read the content of the LOFF_MSB field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the LOFF_MSB field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Get_LOFF_MSB(uint32_t reg) +{ + return ATON_STRENG_CID_CACHE_GET_LOFF_MSB(reg); +} + + +/** + * Write the content of the LOFF_MSB field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the LOFF_MSB field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_STRENG_CID_CACHE_Set_LOFF_MSB(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_CID_CACHE_SET_LOFF_MSB(reg, data); +} + + +/* ****************************************************** EXTSYNC register of one of the STRENG Units ******************************************************* */ + +/** Offset of the EXTSYNC register from the base address of the STRENG Unit. */ +#define ATON_STRENG_EXTSYNC_OFFSET 0x4cUL + +/** Reset value of the EXTSYNC register of the STRENG Unit. */ +#define ATON_STRENG_EXTSYNC_DT \ + (ATON_STRENG_EXTSYNC_EN_DT << ATON_STRENG_EXTSYNC_EN_LSB) | \ + (ATON_STRENG_EXTSYNC_SRC_DT << ATON_STRENG_EXTSYNC_SRC_LSB) | \ + (ATON_STRENG_EXTSYNC_LINES_DT << ATON_STRENG_EXTSYNC_LINES_LSB) + + + +/** Description of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_DESC "External triggers 1st control register (RO when CTRL.RUNNING)" + +/** Address of the EXTSYNC register of one of the STRENG Units. */ +#define ATON_STRENG_EXTSYNC_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_EXTSYNC_OFFSET) + +/** Get the content of the EXTSYNC register of one of the STRENG Units. */ +#define ATON_STRENG_EXTSYNC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC_ADDR(UNIT))) + +/** Set the content of the EXTSYNC register of one of the STRENG Units. */ +#define ATON_STRENG_EXTSYNC_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EXTSYNC register. + * + * \return the description of EXTSYNC register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC_DESC; +} + + +/** + * Get the offset of the EXTSYNC register. + * + * \return the offset of EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_GetOffset(void) +{ + return ATON_STRENG_EXTSYNC_OFFSET; +} + + +/** + * Get the address of the EXTSYNC register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of EXTSYNC register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_GetAddr(uint32_t instance) +{ + return ATON_STRENG_EXTSYNC_ADDR(instance); +} + + +/** + * Read the content of the EXTSYNC register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of EXTSYNC register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Get(uint32_t instance) +{ + return ATON_STRENG_EXTSYNC_GET(instance); +} + + +/** + * Write the content of the EXTSYNC register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_EXTSYNC_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_EXTSYNC_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EXTSYNC register ------------------------------------------------------------ */ + +/** Description of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_EN_DESC "Enable external sync trigger mode (RO when CTRL.RUNNING)" + +/** Offset of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_EN_LSB 0UL + +/** Size in bits of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_EN_W (1UL) + +/** Mask for retrieving the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_EN_DT 0x0UL + +/** Access rights of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_EN_AC "RW" + +/** Check whether access to the EN field of the EXTSYNC register is secured or not. */ +#define ATON_STRENG_EXTSYNC_EN_S 0 + +/** Check whether access to the EN field of the EXTSYNC register is privileged or not. */ +#define ATON_STRENG_EXTSYNC_EN_P 0 + +/** Read the content of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC_EN_LSB, ATON_STRENG_EXTSYNC_EN_W) + +/** Modify the content of the EN field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC_EN_LSB, ATON_STRENG_EXTSYNC_EN_W, DATA) + + +/** + * Get the description of the EN field of EXTSYNC register. + * + * \return the description of the EN field of EXTSYNC register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC_EN_DESC; +} + + +/** + * Read the content of the EN field of the EXTSYNC register. + * + * \param[in] reg is the value of the EXTSYNC register + * + * \return the content of the EN field belonging to EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Get_EN(uint32_t reg) +{ + return ATON_STRENG_EXTSYNC_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EXTSYNC register. + * + * \param[in] reg is the value of the EXTSYNC register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EXTSYNC_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SRC field of the EXTSYNC register ------------------------------------------------------------ */ + +/** Description of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SRC_DESC "External sync trigger source: range is 0 - 3, values not in range will be refused (RO when CTRL.RUNNING)" + +/** Offset of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SRC_LSB 4UL + +/** Size in bits of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SRC_W (4UL) + +/** Mask for retrieving the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SRC_MASK ATON_FIELD_MASK(4UL, 4UL) + +/** Reset value of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SRC_DT 0x0UL + +/** Access rights of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SRC_AC "RW" + +/** Check whether access to the SRC field of the EXTSYNC register is secured or not. */ +#define ATON_STRENG_EXTSYNC_SRC_S 0 + +/** Check whether access to the SRC field of the EXTSYNC register is privileged or not. */ +#define ATON_STRENG_EXTSYNC_SRC_P 0 + +/** Read the content of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_GET_SRC(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC_SRC_LSB, ATON_STRENG_EXTSYNC_SRC_W) + +/** Modify the content of the SRC field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SET_SRC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC_SRC_LSB, ATON_STRENG_EXTSYNC_SRC_W, DATA) + + +/** + * Get the description of the SRC field of EXTSYNC register. + * + * \return the description of the SRC field of EXTSYNC register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC_SRC_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC_SRC_DESC; +} + + +/** + * Read the content of the SRC field of the EXTSYNC register. + * + * \param[in] reg is the value of the EXTSYNC register + * + * \return the content of the SRC field belonging to EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Get_SRC(uint32_t reg) +{ + return ATON_STRENG_EXTSYNC_GET_SRC(reg); +} + + +/** + * Write the content of the SRC field of the EXTSYNC register. + * + * \param[in] reg is the value of the EXTSYNC register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the SRC field belonging to EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Set_SRC(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EXTSYNC_SET_SRC(reg, data); +} + + +/* ---------------------------------------------------------- LINES field of the EXTSYNC register ----------------------------------------------------------- */ + +/** Description of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_LINES_DESC "Number of lines associated to each trigger rising edge (RO when CTRL.RUNNING)" + +/** Offset of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_LINES_LSB 16UL + +/** Size in bits of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_LINES_W (16UL) + +/** Mask for retrieving the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_LINES_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_LINES_DT 0x0UL + +/** Access rights of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_LINES_AC "RW" + +/** Check whether access to the LINES field of the EXTSYNC register is secured or not. */ +#define ATON_STRENG_EXTSYNC_LINES_S 0 + +/** Check whether access to the LINES field of the EXTSYNC register is privileged or not. */ +#define ATON_STRENG_EXTSYNC_LINES_P 0 + +/** Read the content of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_GET_LINES(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC_LINES_LSB, ATON_STRENG_EXTSYNC_LINES_W) + +/** Modify the content of the LINES field of the EXTSYNC register. */ +#define ATON_STRENG_EXTSYNC_SET_LINES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC_LINES_LSB, ATON_STRENG_EXTSYNC_LINES_W, DATA) + + +/** + * Get the description of the LINES field of EXTSYNC register. + * + * \return the description of the LINES field of EXTSYNC register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC_LINES_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC_LINES_DESC; +} + + +/** + * Read the content of the LINES field of the EXTSYNC register. + * + * \param[in] reg is the value of the EXTSYNC register + * + * \return the content of the LINES field belonging to EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Get_LINES(uint32_t reg) +{ + return ATON_STRENG_EXTSYNC_GET_LINES(reg); +} + + +/** + * Write the content of the LINES field of the EXTSYNC register. + * + * \param[in] reg is the value of the EXTSYNC register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the LINES field belonging to EXTSYNC register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC_Set_LINES(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EXTSYNC_SET_LINES(reg, data); +} + + +/* ****************************************************** EXTSYNC2 register of one of the STRENG Units ****************************************************** */ + +/** Offset of the EXTSYNC2 register from the base address of the STRENG Unit. */ +#define ATON_STRENG_EXTSYNC2_OFFSET 0x50UL + +/** Reset value of the EXTSYNC2 register of the STRENG Unit. */ +#define ATON_STRENG_EXTSYNC2_DT \ + (ATON_STRENG_EXTSYNC2_LINES_DT << ATON_STRENG_EXTSYNC2_LINES_LSB) | \ + (ATON_STRENG_EXTSYNC2_OFF_DT << ATON_STRENG_EXTSYNC2_OFF_LSB) + + + +/** Description of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_DESC "External triggers 2st control register (RO when CTRL.RUNNING)" + +/** Address of the EXTSYNC2 register of one of the STRENG Units. */ +#define ATON_STRENG_EXTSYNC2_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_EXTSYNC2_OFFSET) + +/** Get the content of the EXTSYNC2 register of one of the STRENG Units. */ +#define ATON_STRENG_EXTSYNC2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC2_ADDR(UNIT))) + +/** Set the content of the EXTSYNC2 register of one of the STRENG Units. */ +#define ATON_STRENG_EXTSYNC2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EXTSYNC2 register. + * + * \return the description of EXTSYNC2 register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC2_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC2_DESC; +} + + +/** + * Get the offset of the EXTSYNC2 register. + * + * \return the offset of EXTSYNC2 register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_GetOffset(void) +{ + return ATON_STRENG_EXTSYNC2_OFFSET; +} + + +/** + * Get the address of the EXTSYNC2 register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC2 register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of EXTSYNC2 register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_GetAddr(uint32_t instance) +{ + return ATON_STRENG_EXTSYNC2_ADDR(instance); +} + + +/** + * Read the content of the EXTSYNC2 register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC2 register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of EXTSYNC2 register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_Get(uint32_t instance) +{ + return ATON_STRENG_EXTSYNC2_GET(instance); +} + + +/** + * Write the content of the EXTSYNC2 register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC2 register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_EXTSYNC2_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_EXTSYNC2_SET(instance, data); +} + + +/* ---------------------------------------------------------- LINES field of the EXTSYNC2 register ---------------------------------------------------------- */ + +/** Description of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_LINES_DESC "Number of lines after which the special offset will be applied (RO when CTRL.RUNNING)" + +/** Offset of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_LINES_LSB 0UL + +/** Size in bits of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_LINES_W (16UL) + +/** Mask for retrieving the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_LINES_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_LINES_DT 0x0UL + +/** Access rights of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_LINES_AC "RW" + +/** Check whether access to the LINES field of the EXTSYNC2 register is secured or not. */ +#define ATON_STRENG_EXTSYNC2_LINES_S 0 + +/** Check whether access to the LINES field of the EXTSYNC2 register is privileged or not. */ +#define ATON_STRENG_EXTSYNC2_LINES_P 0 + +/** Read the content of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_GET_LINES(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC2_LINES_LSB, ATON_STRENG_EXTSYNC2_LINES_W) + +/** Modify the content of the LINES field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_SET_LINES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC2_LINES_LSB, ATON_STRENG_EXTSYNC2_LINES_W, DATA) + + +/** + * Get the description of the LINES field of EXTSYNC2 register. + * + * \return the description of the LINES field of EXTSYNC2 register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC2_LINES_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC2_LINES_DESC; +} + + +/** + * Read the content of the LINES field of the EXTSYNC2 register. + * + * \param[in] reg is the value of the EXTSYNC2 register + * + * \return the content of the LINES field belonging to EXTSYNC2 register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_Get_LINES(uint32_t reg) +{ + return ATON_STRENG_EXTSYNC2_GET_LINES(reg); +} + + +/** + * Write the content of the LINES field of the EXTSYNC2 register. + * + * \param[in] reg is the value of the EXTSYNC2 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the LINES field belonging to EXTSYNC2 register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_Set_LINES(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EXTSYNC2_SET_LINES(reg, data); +} + + +/* ----------------------------------------------------------- OFF field of the EXTSYNC2 register ----------------------------------------------------------- */ + +/** Description of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_OFF_DESC "Special line offset (RO when CTRL.RUNNING)" + +/** Offset of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_OFF_LSB 16UL + +/** Size in bits of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_OFF_W (16UL) + +/** Mask for retrieving the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_OFF_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_OFF_DT 0x0UL + +/** Access rights of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_OFF_AC "RW" + +/** Check whether access to the OFF field of the EXTSYNC2 register is secured or not. */ +#define ATON_STRENG_EXTSYNC2_OFF_S 0 + +/** Check whether access to the OFF field of the EXTSYNC2 register is privileged or not. */ +#define ATON_STRENG_EXTSYNC2_OFF_P 0 + +/** Read the content of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_GET_OFF(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC2_OFF_LSB, ATON_STRENG_EXTSYNC2_OFF_W) + +/** Modify the content of the OFF field of the EXTSYNC2 register. */ +#define ATON_STRENG_EXTSYNC2_SET_OFF(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC2_OFF_LSB, ATON_STRENG_EXTSYNC2_OFF_W, DATA) + + +/** + * Get the description of the OFF field of EXTSYNC2 register. + * + * \return the description of the OFF field of EXTSYNC2 register + */ + +static inline const int8_t *ATON_STRENG_EXTSYNC2_OFF_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_EXTSYNC2_OFF_DESC; +} + + +/** + * Read the content of the OFF field of the EXTSYNC2 register. + * + * \param[in] reg is the value of the EXTSYNC2 register + * + * \return the content of the OFF field belonging to EXTSYNC2 register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_Get_OFF(uint32_t reg) +{ + return ATON_STRENG_EXTSYNC2_GET_OFF(reg); +} + + +/** + * Write the content of the OFF field of the EXTSYNC2 register. + * + * \param[in] reg is the value of the EXTSYNC2 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the OFF field belonging to EXTSYNC2 register + */ + +static inline uint32_t ATON_STRENG_EXTSYNC2_Set_OFF(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_EXTSYNC2_SET_OFF(reg, data); +} + + +/* ***************************************************** DESCRADDR register of one of the STRENG Units ****************************************************** */ + +/** Offset of the DESCRADDR register from the base address of the STRENG Unit. */ +#define ATON_STRENG_DESCRADDR_OFFSET 0x54UL + +/** Reset value of the DESCRADDR register of the STRENG Unit. */ +#define ATON_STRENG_DESCRADDR_DT \ + (ATON_STRENG_DESCRADDR_REG_DT << ATON_STRENG_DESCRADDR_REG_LSB) + + + +/** Description of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_DESC "Descriptor fetch address" + +/** Address of the DESCRADDR register of one of the STRENG Units. */ +#define ATON_STRENG_DESCRADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_DESCRADDR_OFFSET) + +/** Get the content of the DESCRADDR register of one of the STRENG Units. */ +#define ATON_STRENG_DESCRADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_DESCRADDR_ADDR(UNIT))) + +/** Set the content of the DESCRADDR register of one of the STRENG Units. */ +#define ATON_STRENG_DESCRADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_DESCRADDR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DESCRADDR register. + * + * \return the description of DESCRADDR register + */ + +static inline const int8_t *ATON_STRENG_DESCRADDR_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_DESCRADDR_DESC; +} + + +/** + * Get the offset of the DESCRADDR register. + * + * \return the offset of DESCRADDR register + */ + +static inline uint32_t ATON_STRENG_DESCRADDR_GetOffset(void) +{ + return ATON_STRENG_DESCRADDR_OFFSET; +} + + +/** + * Get the address of the DESCRADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DESCRADDR register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of DESCRADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_DESCRADDR_GetAddr(uint32_t instance) +{ + return ATON_STRENG_DESCRADDR_ADDR(instance); +} + + +/** + * Read the content of the DESCRADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DESCRADDR register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of DESCRADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_DESCRADDR_Get(uint32_t instance) +{ + return ATON_STRENG_DESCRADDR_GET(instance); +} + + +/** + * Write the content of the DESCRADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DESCRADDR register whose content must be modified + * (it must be instance \< 10<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRENG_DESCRADDR_Set(uint32_t instance, uint32_t data) +{ + ATON_STRENG_DESCRADDR_SET(instance, data); +} + + +/* ---------------------------------------------------------- REG field of the DESCRADDR register ----------------------------------------------------------- */ + +/** Description of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_REG_DESC "Descriptor fetch address. Must be 64 bit aligned (values not 64 bits aligned will be refused) (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_REG_LSB 0UL + +/** Size in bits of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_REG_W (32UL) + +/** Mask for retrieving the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_REG_DT 0x0UL + +/** Access rights of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_REG_AC "RW" + +/** Check whether access to the REG field of the DESCRADDR register is secured or not. */ +#define ATON_STRENG_DESCRADDR_REG_S 0 + +/** Check whether access to the REG field of the DESCRADDR register is privileged or not. */ +#define ATON_STRENG_DESCRADDR_REG_P 0 + +/** Read the content of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_DESCRADDR_REG_LSB, ATON_STRENG_DESCRADDR_REG_W) + +/** Modify the content of the REG field of the DESCRADDR register. */ +#define ATON_STRENG_DESCRADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_DESCRADDR_REG_LSB, ATON_STRENG_DESCRADDR_REG_W, DATA) + + +/** + * Get the description of the REG field of DESCRADDR register. + * + * \return the description of the REG field of DESCRADDR register + */ + +static inline const int8_t *ATON_STRENG_DESCRADDR_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_DESCRADDR_REG_DESC; +} + + +/** + * Read the content of the REG field of the DESCRADDR register. + * + * \param[in] reg is the value of the DESCRADDR register + * + * \return the content of the REG field belonging to DESCRADDR register + */ + +static inline uint32_t ATON_STRENG_DESCRADDR_Get_REG(uint32_t reg) +{ + return ATON_STRENG_DESCRADDR_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the DESCRADDR register. + * + * \param[in] reg is the value of the DESCRADDR register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to DESCRADDR register + */ + +static inline uint32_t ATON_STRENG_DESCRADDR_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_STRENG_DESCRADDR_SET_REG(reg, data); +} + + +/* ****************************************************** LASTADDR register of one of the STRENG Units ****************************************************** */ + +/** Offset of the LASTADDR register from the base address of the STRENG Unit. */ +#define ATON_STRENG_LASTADDR_OFFSET 0x58UL + +/** Reset value of the LASTADDR register of the STRENG Unit. */ +#define ATON_STRENG_LASTADDR_DT \ + (ATON_STRENG_LASTADDR_REG_DT << ATON_STRENG_LASTADDR_REG_LSB) + + + +/** Description of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_DESC "Address of the last transaction on master bus IF" + +/** Address of the LASTADDR register of one of the STRENG Units. */ +#define ATON_STRENG_LASTADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LASTADDR_OFFSET) + +/** Get the content of the LASTADDR register of one of the STRENG Units. */ +#define ATON_STRENG_LASTADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LASTADDR_ADDR(UNIT))) + + +/** + * Get the description of LASTADDR register. + * + * \return the description of LASTADDR register + */ + +static inline const int8_t *ATON_STRENG_LASTADDR_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_LASTADDR_DESC; +} + + +/** + * Get the offset of the LASTADDR register. + * + * \return the offset of LASTADDR register + */ + +static inline uint32_t ATON_STRENG_LASTADDR_GetOffset(void) +{ + return ATON_STRENG_LASTADDR_OFFSET; +} + + +/** + * Get the address of the LASTADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LASTADDR register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of LASTADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LASTADDR_GetAddr(uint32_t instance) +{ + return ATON_STRENG_LASTADDR_ADDR(instance); +} + + +/** + * Read the content of the LASTADDR register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LASTADDR register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of LASTADDR register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LASTADDR_Get(uint32_t instance) +{ + return ATON_STRENG_LASTADDR_GET(instance); +} + + +/* ----------------------------------------------------------- REG field of the LASTADDR register ----------------------------------------------------------- */ + +/** Description of the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_REG_DESC "Address of the last transaction on master bus IF" + +/** Offset of the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_REG_LSB 0UL + +/** Size in bits of the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_REG_W (32UL) + +/** Mask for retrieving the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_REG_DT 0x0UL + +/** Access rights of the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_REG_AC "R" + +/** Check whether access to the REG field of the LASTADDR register is secured or not. */ +#define ATON_STRENG_LASTADDR_REG_S 0 + +/** Check whether access to the REG field of the LASTADDR register is privileged or not. */ +#define ATON_STRENG_LASTADDR_REG_P 0 + +/** Read the content of the REG field of the LASTADDR register. */ +#define ATON_STRENG_LASTADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_LASTADDR_REG_LSB, ATON_STRENG_LASTADDR_REG_W) + + +/** + * Get the description of the REG field of LASTADDR register. + * + * \return the description of the REG field of LASTADDR register + */ + +static inline const int8_t *ATON_STRENG_LASTADDR_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LASTADDR_REG_DESC; +} + + +/** + * Read the content of the REG field of the LASTADDR register. + * + * \param[in] reg is the value of the LASTADDR register + * + * \return the content of the REG field belonging to LASTADDR register + */ + +static inline uint32_t ATON_STRENG_LASTADDR_Get_REG(uint32_t reg) +{ + return ATON_STRENG_LASTADDR_GET_REG(reg); +} + + +/* ****************************************************** DEPTHCNT register of one of the STRENG Units ****************************************************** */ + +/** Offset of the DEPTHCNT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_DEPTHCNT_OFFSET 0x5cUL + +/** Reset value of the DEPTHCNT register of the STRENG Unit. */ +#define ATON_STRENG_DEPTHCNT_DT \ + (ATON_STRENG_DEPTHCNT_REG_DT << ATON_STRENG_DEPTHCNT_REG_LSB) + + + +/** Description of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_DESC "Current processed sub-pixel (1 to depth size)" + +/** Address of the DEPTHCNT register of one of the STRENG Units. */ +#define ATON_STRENG_DEPTHCNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_DEPTHCNT_OFFSET) + +/** Get the content of the DEPTHCNT register of one of the STRENG Units. */ +#define ATON_STRENG_DEPTHCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_DEPTHCNT_ADDR(UNIT))) + + +/** + * Get the description of DEPTHCNT register. + * + * \return the description of DEPTHCNT register + */ + +static inline const int8_t *ATON_STRENG_DEPTHCNT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_DEPTHCNT_DESC; +} + + +/** + * Get the offset of the DEPTHCNT register. + * + * \return the offset of DEPTHCNT register + */ + +static inline uint32_t ATON_STRENG_DEPTHCNT_GetOffset(void) +{ + return ATON_STRENG_DEPTHCNT_OFFSET; +} + + +/** + * Get the address of the DEPTHCNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTHCNT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of DEPTHCNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_DEPTHCNT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_DEPTHCNT_ADDR(instance); +} + + +/** + * Read the content of the DEPTHCNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTHCNT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of DEPTHCNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_DEPTHCNT_Get(uint32_t instance) +{ + return ATON_STRENG_DEPTHCNT_GET(instance); +} + + +/* ----------------------------------------------------------- REG field of the DEPTHCNT register ----------------------------------------------------------- */ + +/** Description of the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_REG_DESC "Current processed sub-pixel (1 to depth size)" + +/** Offset of the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_REG_LSB 0UL + +/** Size in bits of the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_REG_W (32UL) + +/** Mask for retrieving the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_REG_DT 0x1UL + +/** Access rights of the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_REG_AC "R" + +/** Check whether access to the REG field of the DEPTHCNT register is secured or not. */ +#define ATON_STRENG_DEPTHCNT_REG_S 0 + +/** Check whether access to the REG field of the DEPTHCNT register is privileged or not. */ +#define ATON_STRENG_DEPTHCNT_REG_P 0 + +/** Read the content of the REG field of the DEPTHCNT register. */ +#define ATON_STRENG_DEPTHCNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_DEPTHCNT_REG_LSB, ATON_STRENG_DEPTHCNT_REG_W) + + +/** + * Get the description of the REG field of DEPTHCNT register. + * + * \return the description of the REG field of DEPTHCNT register + */ + +static inline const int8_t *ATON_STRENG_DEPTHCNT_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_DEPTHCNT_REG_DESC; +} + + +/** + * Read the content of the REG field of the DEPTHCNT register. + * + * \param[in] reg is the value of the DEPTHCNT register + * + * \return the content of the REG field belonging to DEPTHCNT register + */ + +static inline uint32_t ATON_STRENG_DEPTHCNT_Get_REG(uint32_t reg) +{ + return ATON_STRENG_DEPTHCNT_GET_REG(reg); +} + + +/* ******************************************************* PIXCNT register of one of the STRENG Units ******************************************************* */ + +/** Offset of the PIXCNT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_PIXCNT_OFFSET 0x60UL + +/** Reset value of the PIXCNT register of the STRENG Unit. */ +#define ATON_STRENG_PIXCNT_DT \ + (ATON_STRENG_PIXCNT_REG_DT << ATON_STRENG_PIXCNT_REG_LSB) + + + +/** Description of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_DESC "Current processed pixel (1 to line width)" + +/** Address of the PIXCNT register of one of the STRENG Units. */ +#define ATON_STRENG_PIXCNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_PIXCNT_OFFSET) + +/** Get the content of the PIXCNT register of one of the STRENG Units. */ +#define ATON_STRENG_PIXCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_PIXCNT_ADDR(UNIT))) + + +/** + * Get the description of PIXCNT register. + * + * \return the description of PIXCNT register + */ + +static inline const int8_t *ATON_STRENG_PIXCNT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_PIXCNT_DESC; +} + + +/** + * Get the offset of the PIXCNT register. + * + * \return the offset of PIXCNT register + */ + +static inline uint32_t ATON_STRENG_PIXCNT_GetOffset(void) +{ + return ATON_STRENG_PIXCNT_OFFSET; +} + + +/** + * Get the address of the PIXCNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the PIXCNT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of PIXCNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_PIXCNT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_PIXCNT_ADDR(instance); +} + + +/** + * Read the content of the PIXCNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the PIXCNT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of PIXCNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_PIXCNT_Get(uint32_t instance) +{ + return ATON_STRENG_PIXCNT_GET(instance); +} + + +/* ------------------------------------------------------------ REG field of the PIXCNT register ------------------------------------------------------------ */ + +/** Description of the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_REG_DESC "Current processed pixel (1 to frame width)" + +/** Offset of the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_REG_LSB 0UL + +/** Size in bits of the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_REG_W (32UL) + +/** Mask for retrieving the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_REG_DT 0x1UL + +/** Access rights of the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_REG_AC "R" + +/** Check whether access to the REG field of the PIXCNT register is secured or not. */ +#define ATON_STRENG_PIXCNT_REG_S 0 + +/** Check whether access to the REG field of the PIXCNT register is privileged or not. */ +#define ATON_STRENG_PIXCNT_REG_P 0 + +/** Read the content of the REG field of the PIXCNT register. */ +#define ATON_STRENG_PIXCNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_PIXCNT_REG_LSB, ATON_STRENG_PIXCNT_REG_W) + + +/** + * Get the description of the REG field of PIXCNT register. + * + * \return the description of the REG field of PIXCNT register + */ + +static inline const int8_t *ATON_STRENG_PIXCNT_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_PIXCNT_REG_DESC; +} + + +/** + * Read the content of the REG field of the PIXCNT register. + * + * \param[in] reg is the value of the PIXCNT register + * + * \return the content of the REG field belonging to PIXCNT register + */ + +static inline uint32_t ATON_STRENG_PIXCNT_Get_REG(uint32_t reg) +{ + return ATON_STRENG_PIXCNT_GET_REG(reg); +} + + +/* ****************************************************** LINECNT register of one of the STRENG Units ******************************************************* */ + +/** Offset of the LINECNT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_LINECNT_OFFSET 0x64UL + +/** Reset value of the LINECNT register of the STRENG Unit. */ +#define ATON_STRENG_LINECNT_DT \ + (ATON_STRENG_LINECNT_REG_DT << ATON_STRENG_LINECNT_REG_LSB) + + + +/** Description of the LINECNT register. */ +#define ATON_STRENG_LINECNT_DESC "Current processed line (1 to frame height)" + +/** Address of the LINECNT register of one of the STRENG Units. */ +#define ATON_STRENG_LINECNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LINECNT_OFFSET) + +/** Get the content of the LINECNT register of one of the STRENG Units. */ +#define ATON_STRENG_LINECNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LINECNT_ADDR(UNIT))) + + +/** + * Get the description of LINECNT register. + * + * \return the description of LINECNT register + */ + +static inline const int8_t *ATON_STRENG_LINECNT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_LINECNT_DESC; +} + + +/** + * Get the offset of the LINECNT register. + * + * \return the offset of LINECNT register + */ + +static inline uint32_t ATON_STRENG_LINECNT_GetOffset(void) +{ + return ATON_STRENG_LINECNT_OFFSET; +} + + +/** + * Get the address of the LINECNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LINECNT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of LINECNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LINECNT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_LINECNT_ADDR(instance); +} + + +/** + * Read the content of the LINECNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LINECNT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of LINECNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_LINECNT_Get(uint32_t instance) +{ + return ATON_STRENG_LINECNT_GET(instance); +} + + +/* ----------------------------------------------------------- REG field of the LINECNT register ------------------------------------------------------------ */ + +/** Description of the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_REG_DESC "Current processed line (1 to frame height)" + +/** Offset of the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_REG_LSB 0UL + +/** Size in bits of the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_REG_W (32UL) + +/** Mask for retrieving the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_REG_DT 0x1UL + +/** Access rights of the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_REG_AC "R" + +/** Check whether access to the REG field of the LINECNT register is secured or not. */ +#define ATON_STRENG_LINECNT_REG_S 0 + +/** Check whether access to the REG field of the LINECNT register is privileged or not. */ +#define ATON_STRENG_LINECNT_REG_P 0 + +/** Read the content of the REG field of the LINECNT register. */ +#define ATON_STRENG_LINECNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_LINECNT_REG_LSB, ATON_STRENG_LINECNT_REG_W) + + +/** + * Get the description of the REG field of LINECNT register. + * + * \return the description of the REG field of LINECNT register + */ + +static inline const int8_t *ATON_STRENG_LINECNT_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_LINECNT_REG_DESC; +} + + +/** + * Read the content of the REG field of the LINECNT register. + * + * \param[in] reg is the value of the LINECNT register + * + * \return the content of the REG field belonging to LINECNT register + */ + +static inline uint32_t ATON_STRENG_LINECNT_Get_REG(uint32_t reg) +{ + return ATON_STRENG_LINECNT_GET_REG(reg); +} + + +/* ******************************************************** FCNT register of one of the STRENG Units ******************************************************** */ + +/** Offset of the FCNT register from the base address of the STRENG Unit. */ +#define ATON_STRENG_FCNT_OFFSET 0x68UL + +/** Reset value of the FCNT register of the STRENG Unit. */ +#define ATON_STRENG_FCNT_DT \ + (ATON_STRENG_FCNT_REG_DT << ATON_STRENG_FCNT_REG_LSB) + + + +/** Description of the FCNT register. */ +#define ATON_STRENG_FCNT_DESC "Frame counter" + +/** Address of the FCNT register of one of the STRENG Units. */ +#define ATON_STRENG_FCNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FCNT_OFFSET) + +/** Get the content of the FCNT register of one of the STRENG Units. */ +#define ATON_STRENG_FCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FCNT_ADDR(UNIT))) + + +/** + * Get the description of FCNT register. + * + * \return the description of FCNT register + */ + +static inline const int8_t *ATON_STRENG_FCNT_GetDesc(void) +{ + return (const int8_t *)ATON_STRENG_FCNT_DESC; +} + + +/** + * Get the offset of the FCNT register. + * + * \return the offset of FCNT register + */ + +static inline uint32_t ATON_STRENG_FCNT_GetOffset(void) +{ + return ATON_STRENG_FCNT_OFFSET; +} + + +/** + * Get the address of the FCNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FCNT register whose address must be returned + * (it must be instance \< 10<\em>) + * + * \return the address of FCNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FCNT_GetAddr(uint32_t instance) +{ + return ATON_STRENG_FCNT_ADDR(instance); +} + + +/** + * Read the content of the FCNT register. + * + * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FCNT register whose content must be retrieved + * (it must be instance \< 10<\em>) + * + * \return the content of FCNT register belonging to Unit having index \e instance among the STRENG Units + */ + +static inline uint32_t ATON_STRENG_FCNT_Get(uint32_t instance) +{ + return ATON_STRENG_FCNT_GET(instance); +} + + +/* ------------------------------------------------------------- REG field of the FCNT register ------------------------------------------------------------- */ + +/** Description of the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_REG_DESC "Frame counter" + +/** Offset of the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_REG_LSB 0UL + +/** Size in bits of the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_REG_W (32UL) + +/** Mask for retrieving the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_REG_DT 0x1UL + +/** Access rights of the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_REG_AC "R" + +/** Check whether access to the REG field of the FCNT register is secured or not. */ +#define ATON_STRENG_FCNT_REG_S 0 + +/** Check whether access to the REG field of the FCNT register is privileged or not. */ +#define ATON_STRENG_FCNT_REG_P 0 + +/** Read the content of the REG field of the FCNT register. */ +#define ATON_STRENG_FCNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FCNT_REG_LSB, ATON_STRENG_FCNT_REG_W) + + +/** + * Get the description of the REG field of FCNT register. + * + * \return the description of the REG field of FCNT register + */ + +static inline const int8_t *ATON_STRENG_FCNT_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_STRENG_FCNT_REG_DESC; +} + + +/** + * Read the content of the REG field of the FCNT register. + * + * \param[in] reg is the value of the FCNT register + * + * \return the content of the REG field belonging to FCNT register + */ + +static inline uint32_t ATON_STRENG_FCNT_Get_REG(uint32_t reg) +{ + return ATON_STRENG_FCNT_GET_REG(reg); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* STRSWITCH Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of STRSWITCH Unit instances. */ +#define ATON_STRSWITCH_NUM 1 + +/** + * \name Structures, macros and functions of the STRSWITCH Units + */ +/*@{*/ + +/** + * Registers of the STRSWITCH Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e DSTSTRENG0 register (Connection to input port of Stream Engine 0). */ + uint32_t DSTSTRENG0; + + /** \e DSTSTRENG1 register (Connection to input port of Stream Engine 1). */ + uint32_t DSTSTRENG1; + + /** \e DSTSTRENG2 register (Connection to input port of Stream Engine 2). */ + uint32_t DSTSTRENG2; + + /** \e DSTSTRENG3 register (Connection to input port of Stream Engine 3). */ + uint32_t DSTSTRENG3; + + /** \e DSTSTRENG4 register (Connection to input port of Stream Engine 4). */ + uint32_t DSTSTRENG4; + + /** \e DSTSTRENG5 register (Connection to input port of Stream Engine 5). */ + uint32_t DSTSTRENG5; + + /** \e DSTSTRENG6 register (Connection to input port of Stream Engine 6). */ + uint32_t DSTSTRENG6; + + /** \e DSTSTRENG7 register (Connection to input port of Stream Engine 7). */ + uint32_t DSTSTRENG7; + + /** \e DSTSTRENG8 register (Connection to input port of Stream Engine 8). */ + uint32_t DSTSTRENG8; + + /** \e DSTSTRENG9 register (Connection to input port of Stream Engine 9). */ + uint32_t DSTSTRENG9; + + /** \e DSTCONVACC00 register (Connection to input port 0 of Convolutional Accelerator 0). */ + uint32_t DSTCONVACC00; + + /** \e DSTCONVACC01 register (Connection to input port 1 of Convolutional Accelerator 0). */ + uint32_t DSTCONVACC01; + + /** \e DSTCONVACC02 register (Connection to input port 2 of Convolutional Accelerator 0). */ + uint32_t DSTCONVACC02; + + /** \e DSTCONVACC10 register (Connection to input port 0 of Convolutional Accelerator 1). */ + uint32_t DSTCONVACC10; + + /** \e DSTCONVACC11 register (Connection to input port 1 of Convolutional Accelerator 1). */ + uint32_t DSTCONVACC11; + + /** \e DSTCONVACC12 register (Connection to input port 2 of Convolutional Accelerator 1). */ + uint32_t DSTCONVACC12; + + /** \e DSTCONVACC20 register (Connection to input port 0 of Convolutional Accelerator 2). */ + uint32_t DSTCONVACC20; + + /** \e DSTCONVACC21 register (Connection to input port 1 of Convolutional Accelerator 2). */ + uint32_t DSTCONVACC21; + + /** \e DSTCONVACC22 register (Connection to input port 2 of Convolutional Accelerator 2). */ + uint32_t DSTCONVACC22; + + /** \e DSTCONVACC30 register (Connection to input port 0 of Convolutional Accelerator 3). */ + uint32_t DSTCONVACC30; + + /** \e DSTCONVACC31 register (Connection to input port 1 of Convolutional Accelerator 3). */ + uint32_t DSTCONVACC31; + + /** \e DSTCONVACC32 register (Connection to input port 2 of Convolutional Accelerator 3). */ + uint32_t DSTCONVACC32; + + /** \e DSTDECUN00 register (Connection to input port 0 of Decompression Unit 0). */ + uint32_t DSTDECUN00; + + /** \e DSTDECUN01 register (Connection to input port 1 of Decompression Unit 0). */ + uint32_t DSTDECUN01; + + /** \e DSTDECUN10 register (Connection to input port 0 of Decompression Unit 1). */ + uint32_t DSTDECUN10; + + /** \e DSTDECUN11 register (Connection to input port 1 of Decompression Unit 1). */ + uint32_t DSTDECUN11; + + /** \e DSTACTIV0 register (Connection to input port of Activation Accelerator 0). */ + uint32_t DSTACTIV0; + + /** \e DSTACTIV1 register (Connection to input port of Activation Accelerator 1). */ + uint32_t DSTACTIV1; + + /** \e DSTARITH00 register (Connection to input port 0 of Arithmetic Accelerator 0). */ + uint32_t DSTARITH00; + + /** \e DSTARITH01 register (Connection to input port 1 of Arithmetic Accelerator 0). */ + uint32_t DSTARITH01; + + /** \e DSTARITH10 register (Connection to input port 0 of Arithmetic Accelerator 1). */ + uint32_t DSTARITH10; + + /** \e DSTARITH11 register (Connection to input port 1 of Arithmetic Accelerator 1). */ + uint32_t DSTARITH11; + + /** \e DSTARITH20 register (Connection to input port 0 of Arithmetic Accelerator 2). */ + uint32_t DSTARITH20; + + /** \e DSTARITH21 register (Connection to input port 1 of Arithmetic Accelerator 2). */ + uint32_t DSTARITH21; + + /** \e DSTARITH30 register (Connection to input port 0 of Arithmetic Accelerator 3). */ + uint32_t DSTARITH30; + + /** \e DSTARITH31 register (Connection to input port 1 of Arithmetic Accelerator 3). */ + uint32_t DSTARITH31; + + /** \e DSTPOOL0 register (Connection to input port of Pooling Accelerator 0). */ + uint32_t DSTPOOL0; + + /** \e DSTPOOL1 register (Connection to input port of Pooling Accelerator 1). */ + uint32_t DSTPOOL1; + + /** \e DSTRECBUF00 register (Connection to input port 0 of Reconfigurable Buffer 0). */ + uint32_t DSTRECBUF00; + + /** \e DSTRECBUF01 register (Connection to input port 1 of Reconfigurable Buffer 0). */ + uint32_t DSTRECBUF01; + + /** \e DSTRECBUF02 register (Connection to input port 2 of Reconfigurable Buffer 0). */ + uint32_t DSTRECBUF02; + +} ATON_STRSWITCH_t; + + +/** Return the pointer to one of the STRSWITCH Units. */ +#define ATON_STRSWITCH(UNIT) ((ATON_STRSWITCH_t *)(intptr_t)ATON_STRSWITCH_BASE(UNIT)) + + +/** Name of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_NAME(UNIT) \ + (((UNIT) == 0) ? "STRSWITCH" : "") + + +/** Version of the STRSWITCH Units. */ +#define ATON_STRSWITCH_VERSION "1.6" + + +/** Description of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DESC(UNIT) \ + (((UNIT) == 0) ? "Stream Switch" : "") + + +/** Base address of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_BASE(UNIT) \ + (ATON_BASE + 0x4000UL + ((UNIT) * 0x0UL)) + +/** Size in bytes of the STRSWITCH Units. */ +#define ATON_STRSWITCH_SIZE 0x1000UL + + +/** + * Get the name of one of the STRSWITCH Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) + * + * \return the name of Unit having index \e instance among the STRSWITCH Units + */ + +static inline const int8_t *ATON_STRSWITCH_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"STRSWITCH"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the STRSWITCH Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) + * + * \return the description of Unit having index \e instance among the STRSWITCH Units + */ + +static inline const int8_t *ATON_STRSWITCH_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Stream Switch"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the STRSWITCH Units. + * + * \return the version of the STRSWITCH Units + */ + +static inline const int8_t *ATON_STRSWITCH_GetVersion(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION; +} + + +/** + * Get the base address of one of the STRSWITCH Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) + * + * \return the base address of Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_GetBase(uint32_t instance) +{ + return ATON_STRSWITCH_BASE(instance); +} + + +/** + * Get the size in bytes of the STRSWITCH Units. + * + * \return the size in bytes of the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_GetSize(void) +{ + return ATON_STRSWITCH_SIZE; +} + + +/* ****************************************************** CTRL register of one of the STRSWITCH Units ******************************************************* */ + +/** Offset of the CTRL register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_CTRL_DT \ + (ATON_STRSWITCH_CTRL_EN_DT << ATON_STRSWITCH_CTRL_EN_LSB) | \ + (ATON_STRSWITCH_CTRL_CLR_DT << ATON_STRSWITCH_CTRL_CLR_LSB) | \ + (ATON_STRSWITCH_CTRL_CONFCLR_DT << ATON_STRSWITCH_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_CTRL_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_STRSWITCH_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_GetOffset(void) +{ + return ATON_STRSWITCH_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the CTRL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Get(uint32_t instance) +{ + return ATON_STRSWITCH_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the CTRL register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_EN_DESC "Enable the Stream Switch" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_STRSWITCH_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_STRSWITCH_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_CTRL_EN_LSB, ATON_STRSWITCH_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_CTRL_EN_LSB, ATON_STRSWITCH_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_STRSWITCH_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Get_EN(uint32_t reg) +{ + return ATON_STRSWITCH_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_STRSWITCH_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_STRSWITCH_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_CTRL_CLR_LSB, ATON_STRSWITCH_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_CTRL_CLR_LSB, ATON_STRSWITCH_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_STRSWITCH_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_STRSWITCH_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_STRSWITCH_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_CTRL_CONFCLR_LSB, ATON_STRSWITCH_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_STRSWITCH_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_CTRL_CONFCLR_LSB, ATON_STRSWITCH_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_STRSWITCH_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_STRSWITCH_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_STRSWITCH_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_CTRL_SET_CONFCLR(reg, data); +} + + +/* ***************************************************** VERSION register of one of the STRSWITCH Units ***************************************************** */ + +/** Offset of the VERSION register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_VERSION_DT \ + (ATON_STRSWITCH_VERSION_TYPE_DT << ATON_STRSWITCH_VERSION_TYPE_LSB) | \ + (ATON_STRSWITCH_VERSION_MINOR_DT << ATON_STRSWITCH_VERSION_MINOR_LSB) | \ + (ATON_STRSWITCH_VERSION_MAJOR_DT << ATON_STRSWITCH_VERSION_MAJOR_LSB) | \ + (ATON_STRSWITCH_VERSION_IPORTS_DT << ATON_STRSWITCH_VERSION_IPORTS_LSB) | \ + (ATON_STRSWITCH_VERSION_OPORTS_DT << ATON_STRSWITCH_VERSION_OPORTS_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_VERSION_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_STRSWITCH_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_GetOffset(void) +{ + return ATON_STRSWITCH_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the VERSION register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_Get(uint32_t instance) +{ + return ATON_STRSWITCH_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_TYPE_DT 0x0UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_STRSWITCH_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_STRSWITCH_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_TYPE_LSB, ATON_STRSWITCH_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_STRSWITCH_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_STRSWITCH_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MINOR_DT 0x6UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_STRSWITCH_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_STRSWITCH_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_MINOR_LSB, ATON_STRSWITCH_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_STRSWITCH_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_STRSWITCH_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_STRSWITCH_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_STRSWITCH_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_MAJOR_LSB, ATON_STRSWITCH_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_STRSWITCH_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_STRSWITCH_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- IPORTS field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_IPORTS_DESC "Input Stream Links" + +/** Offset of the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_IPORTS_LSB 16UL + +/** Size in bits of the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_IPORTS_W (8UL) + +/** Mask for retrieving the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_IPORTS_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_IPORTS_DT 0x1bUL + +/** Access rights of the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_IPORTS_AC "R" + +/** Check whether access to the IPORTS field of the VERSION register is secured or not. */ +#define ATON_STRSWITCH_VERSION_IPORTS_S 0 + +/** Check whether access to the IPORTS field of the VERSION register is privileged or not. */ +#define ATON_STRSWITCH_VERSION_IPORTS_P 0 + +/** Read the content of the IPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_GET_IPORTS(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_IPORTS_LSB, ATON_STRSWITCH_VERSION_IPORTS_W) + + +/** + * Get the description of the IPORTS field of VERSION register. + * + * \return the description of the IPORTS field of VERSION register + */ + +static inline const int8_t *ATON_STRSWITCH_VERSION_IPORTS_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION_IPORTS_DESC; +} + + +/** + * Read the content of the IPORTS field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the IPORTS field belonging to VERSION register + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_Get_IPORTS(uint32_t reg) +{ + return ATON_STRSWITCH_VERSION_GET_IPORTS(reg); +} + + +/* ---------------------------------------------------------- OPORTS field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_OPORTS_DESC "Output Stream Links" + +/** Offset of the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_OPORTS_LSB 24UL + +/** Size in bits of the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_OPORTS_W (8UL) + +/** Mask for retrieving the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_OPORTS_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_OPORTS_DT 0x29UL + +/** Access rights of the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_OPORTS_AC "R" + +/** Check whether access to the OPORTS field of the VERSION register is secured or not. */ +#define ATON_STRSWITCH_VERSION_OPORTS_S 0 + +/** Check whether access to the OPORTS field of the VERSION register is privileged or not. */ +#define ATON_STRSWITCH_VERSION_OPORTS_P 0 + +/** Read the content of the OPORTS field of the VERSION register. */ +#define ATON_STRSWITCH_VERSION_GET_OPORTS(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_OPORTS_LSB, ATON_STRSWITCH_VERSION_OPORTS_W) + + +/** + * Get the description of the OPORTS field of VERSION register. + * + * \return the description of the OPORTS field of VERSION register + */ + +static inline const int8_t *ATON_STRSWITCH_VERSION_OPORTS_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_VERSION_OPORTS_DESC; +} + + +/** + * Read the content of the OPORTS field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the OPORTS field belonging to VERSION register + */ + +static inline uint32_t ATON_STRSWITCH_VERSION_Get_OPORTS(uint32_t reg) +{ + return ATON_STRSWITCH_VERSION_GET_OPORTS(reg); +} + + +/* *************************************************** DSTSTRENG0 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG0 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG0_OFFSET 0x8UL + +/** Reset value of the DSTSTRENG0 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG0_DT \ + (ATON_STRSWITCH_DSTSTRENG0_EN0_DT << ATON_STRSWITCH_DSTSTRENG0_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG0_LINK0_DT << ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG0_FNR0_DT << ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG0_EN1_DT << ATON_STRSWITCH_DSTSTRENG0_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG0_LINK1_DT << ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG0_FNR1_DT << ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB) + + + +/** Description of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_DESC "Connection to input port of Stream Engine 0" + +/** Address of the DSTSTRENG0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG0_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG0_OFFSET) + +/** Get the content of the DSTSTRENG0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG0_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG0 register. + * + * \return the description of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_DESC; +} + + +/** + * Get the offset of the DSTSTRENG0 register. + * + * \return the offset of DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG0_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG0 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG0_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG0 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG0_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG0_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG0 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN0_LSB, ATON_STRSWITCH_DSTSTRENG0_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN0_LSB, ATON_STRSWITCH_DSTSTRENG0_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG0 register. + * + * \return the description of the EN0 field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the EN0 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG0 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG0 register. + * + * \return the description of the LINK0 field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG0 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG0 register. + * + * \return the description of the FNR0 field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG0 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN1_LSB, ATON_STRSWITCH_DSTSTRENG0_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN1_LSB, ATON_STRSWITCH_DSTSTRENG0_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG0 register. + * + * \return the description of the EN1 field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the EN1 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG0 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG0 register. + * + * \return the description of the LINK1 field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG0 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG0 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG0 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG0 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG0_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG0 register. */ +#define ATON_STRSWITCH_DSTSTRENG0_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG0 register. + * + * \return the description of the FNR1 field of DSTSTRENG0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG0_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG0 register. + * + * \param[in] reg is the value of the DSTSTRENG0 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG0_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG1 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG1 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG1_OFFSET 0xcUL + +/** Reset value of the DSTSTRENG1 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG1_DT \ + (ATON_STRSWITCH_DSTSTRENG1_EN0_DT << ATON_STRSWITCH_DSTSTRENG1_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG1_LINK0_DT << ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG1_FNR0_DT << ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG1_EN1_DT << ATON_STRSWITCH_DSTSTRENG1_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG1_LINK1_DT << ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG1_FNR1_DT << ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB) + + + +/** Description of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_DESC "Connection to input port of Stream Engine 1" + +/** Address of the DSTSTRENG1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG1_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG1_OFFSET) + +/** Get the content of the DSTSTRENG1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG1_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG1 register. + * + * \return the description of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_DESC; +} + + +/** + * Get the offset of the DSTSTRENG1 register. + * + * \return the offset of DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG1_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG1 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG1_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG1 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG1_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG1_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG1 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN0_LSB, ATON_STRSWITCH_DSTSTRENG1_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN0_LSB, ATON_STRSWITCH_DSTSTRENG1_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG1 register. + * + * \return the description of the EN0 field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the EN0 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG1 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG1 register. + * + * \return the description of the LINK0 field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG1 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG1 register. + * + * \return the description of the FNR0 field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG1 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN1_LSB, ATON_STRSWITCH_DSTSTRENG1_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN1_LSB, ATON_STRSWITCH_DSTSTRENG1_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG1 register. + * + * \return the description of the EN1 field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the EN1 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG1 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG1 register. + * + * \return the description of the LINK1 field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG1 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG1 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG1 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG1 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG1_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG1 register. */ +#define ATON_STRSWITCH_DSTSTRENG1_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG1 register. + * + * \return the description of the FNR1 field of DSTSTRENG1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG1_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG1 register. + * + * \param[in] reg is the value of the DSTSTRENG1 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG1_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG2 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG2 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG2_OFFSET 0x10UL + +/** Reset value of the DSTSTRENG2 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG2_DT \ + (ATON_STRSWITCH_DSTSTRENG2_EN0_DT << ATON_STRSWITCH_DSTSTRENG2_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG2_LINK0_DT << ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG2_FNR0_DT << ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG2_EN1_DT << ATON_STRSWITCH_DSTSTRENG2_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG2_LINK1_DT << ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG2_FNR1_DT << ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB) + + + +/** Description of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_DESC "Connection to input port of Stream Engine 2" + +/** Address of the DSTSTRENG2 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG2_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG2_OFFSET) + +/** Get the content of the DSTSTRENG2 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG2_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG2 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG2 register. + * + * \return the description of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_DESC; +} + + +/** + * Get the offset of the DSTSTRENG2 register. + * + * \return the offset of DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG2_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG2 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG2 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG2 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG2_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG2 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG2 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG2 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG2 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG2 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG2_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG2_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG2 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN0_LSB, ATON_STRSWITCH_DSTSTRENG2_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN0_LSB, ATON_STRSWITCH_DSTSTRENG2_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG2 register. + * + * \return the description of the EN0 field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the EN0 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG2 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG2 register. + * + * \return the description of the LINK0 field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG2 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG2 register. + * + * \return the description of the FNR0 field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG2 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN1_LSB, ATON_STRSWITCH_DSTSTRENG2_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN1_LSB, ATON_STRSWITCH_DSTSTRENG2_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG2 register. + * + * \return the description of the EN1 field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the EN1 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG2 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG2 register. + * + * \return the description of the LINK1 field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG2 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG2 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG2 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG2 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG2 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG2_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG2 register. */ +#define ATON_STRSWITCH_DSTSTRENG2_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG2 register. + * + * \return the description of the FNR1 field of DSTSTRENG2 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG2_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG2 register. + * + * \param[in] reg is the value of the DSTSTRENG2 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG2 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG2_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG3 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG3 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG3_OFFSET 0x14UL + +/** Reset value of the DSTSTRENG3 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG3_DT \ + (ATON_STRSWITCH_DSTSTRENG3_EN0_DT << ATON_STRSWITCH_DSTSTRENG3_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG3_LINK0_DT << ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG3_FNR0_DT << ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG3_EN1_DT << ATON_STRSWITCH_DSTSTRENG3_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG3_LINK1_DT << ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG3_FNR1_DT << ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB) + + + +/** Description of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_DESC "Connection to input port of Stream Engine 3" + +/** Address of the DSTSTRENG3 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG3_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG3_OFFSET) + +/** Get the content of the DSTSTRENG3 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG3_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG3 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG3_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG3 register. + * + * \return the description of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_DESC; +} + + +/** + * Get the offset of the DSTSTRENG3 register. + * + * \return the offset of DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG3_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG3 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG3 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG3 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG3_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG3 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG3 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG3 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG3 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG3 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG3_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG3_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG3 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN0_LSB, ATON_STRSWITCH_DSTSTRENG3_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN0_LSB, ATON_STRSWITCH_DSTSTRENG3_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG3 register. + * + * \return the description of the EN0 field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the EN0 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG3 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG3 register. + * + * \return the description of the LINK0 field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG3 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG3 register. + * + * \return the description of the FNR0 field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG3 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN1_LSB, ATON_STRSWITCH_DSTSTRENG3_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN1_LSB, ATON_STRSWITCH_DSTSTRENG3_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG3 register. + * + * \return the description of the EN1 field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the EN1 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG3 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG3 register. + * + * \return the description of the LINK1 field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG3 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG3 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG3 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG3 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG3 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG3_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG3 register. */ +#define ATON_STRSWITCH_DSTSTRENG3_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG3 register. + * + * \return the description of the FNR1 field of DSTSTRENG3 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG3_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG3 register. + * + * \param[in] reg is the value of the DSTSTRENG3 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG3 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG3_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG4 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG4 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG4_OFFSET 0x18UL + +/** Reset value of the DSTSTRENG4 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG4_DT \ + (ATON_STRSWITCH_DSTSTRENG4_EN0_DT << ATON_STRSWITCH_DSTSTRENG4_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG4_LINK0_DT << ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG4_FNR0_DT << ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG4_EN1_DT << ATON_STRSWITCH_DSTSTRENG4_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG4_LINK1_DT << ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG4_FNR1_DT << ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB) + + + +/** Description of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_DESC "Connection to input port of Stream Engine 4" + +/** Address of the DSTSTRENG4 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG4_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG4_OFFSET) + +/** Get the content of the DSTSTRENG4 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG4_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG4 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG4_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG4 register. + * + * \return the description of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_DESC; +} + + +/** + * Get the offset of the DSTSTRENG4 register. + * + * \return the offset of DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG4_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG4 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG4 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG4 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG4_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG4 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG4 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG4 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG4 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG4 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG4_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG4_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG4 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN0_LSB, ATON_STRSWITCH_DSTSTRENG4_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN0_LSB, ATON_STRSWITCH_DSTSTRENG4_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG4 register. + * + * \return the description of the EN0 field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the EN0 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG4 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG4 register. + * + * \return the description of the LINK0 field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG4 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG4 register. + * + * \return the description of the FNR0 field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG4 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN1_LSB, ATON_STRSWITCH_DSTSTRENG4_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN1_LSB, ATON_STRSWITCH_DSTSTRENG4_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG4 register. + * + * \return the description of the EN1 field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the EN1 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG4 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG4 register. + * + * \return the description of the LINK1 field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG4 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG4 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG4 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG4 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG4 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG4_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG4 register. */ +#define ATON_STRSWITCH_DSTSTRENG4_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG4 register. + * + * \return the description of the FNR1 field of DSTSTRENG4 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG4_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG4 register. + * + * \param[in] reg is the value of the DSTSTRENG4 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG4 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG4_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG5 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG5 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG5_OFFSET 0x1cUL + +/** Reset value of the DSTSTRENG5 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG5_DT \ + (ATON_STRSWITCH_DSTSTRENG5_EN0_DT << ATON_STRSWITCH_DSTSTRENG5_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG5_LINK0_DT << ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG5_FNR0_DT << ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG5_EN1_DT << ATON_STRSWITCH_DSTSTRENG5_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG5_LINK1_DT << ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG5_FNR1_DT << ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB) + + + +/** Description of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_DESC "Connection to input port of Stream Engine 5" + +/** Address of the DSTSTRENG5 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG5_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG5_OFFSET) + +/** Get the content of the DSTSTRENG5 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG5_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG5 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG5_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG5 register. + * + * \return the description of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_DESC; +} + + +/** + * Get the offset of the DSTSTRENG5 register. + * + * \return the offset of DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG5_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG5 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG5 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG5 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG5_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG5 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG5 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG5 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG5 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG5 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG5_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG5_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG5 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN0_LSB, ATON_STRSWITCH_DSTSTRENG5_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN0_LSB, ATON_STRSWITCH_DSTSTRENG5_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG5 register. + * + * \return the description of the EN0 field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the EN0 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG5 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG5 register. + * + * \return the description of the LINK0 field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG5 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG5 register. + * + * \return the description of the FNR0 field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG5 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN1_LSB, ATON_STRSWITCH_DSTSTRENG5_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN1_LSB, ATON_STRSWITCH_DSTSTRENG5_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG5 register. + * + * \return the description of the EN1 field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the EN1 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG5 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG5 register. + * + * \return the description of the LINK1 field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG5 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG5 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG5 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG5 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG5 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG5_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG5 register. */ +#define ATON_STRSWITCH_DSTSTRENG5_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG5 register. + * + * \return the description of the FNR1 field of DSTSTRENG5 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG5_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG5 register. + * + * \param[in] reg is the value of the DSTSTRENG5 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG5 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG5_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG6 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG6 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG6_OFFSET 0x20UL + +/** Reset value of the DSTSTRENG6 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG6_DT \ + (ATON_STRSWITCH_DSTSTRENG6_EN0_DT << ATON_STRSWITCH_DSTSTRENG6_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG6_LINK0_DT << ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG6_FNR0_DT << ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG6_EN1_DT << ATON_STRSWITCH_DSTSTRENG6_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG6_LINK1_DT << ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG6_FNR1_DT << ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB) + + + +/** Description of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_DESC "Connection to input port of Stream Engine 6" + +/** Address of the DSTSTRENG6 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG6_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG6_OFFSET) + +/** Get the content of the DSTSTRENG6 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG6_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG6 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG6_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG6 register. + * + * \return the description of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_DESC; +} + + +/** + * Get the offset of the DSTSTRENG6 register. + * + * \return the offset of DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG6_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG6 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG6 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG6 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG6_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG6 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG6 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG6 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG6 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG6 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG6_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG6_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG6 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN0_LSB, ATON_STRSWITCH_DSTSTRENG6_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN0_LSB, ATON_STRSWITCH_DSTSTRENG6_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG6 register. + * + * \return the description of the EN0 field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the EN0 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG6 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG6 register. + * + * \return the description of the LINK0 field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG6 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG6 register. + * + * \return the description of the FNR0 field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG6 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN1_LSB, ATON_STRSWITCH_DSTSTRENG6_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN1_LSB, ATON_STRSWITCH_DSTSTRENG6_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG6 register. + * + * \return the description of the EN1 field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the EN1 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG6 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG6 register. + * + * \return the description of the LINK1 field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG6 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG6 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG6 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG6 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG6 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG6_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG6 register. */ +#define ATON_STRSWITCH_DSTSTRENG6_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG6 register. + * + * \return the description of the FNR1 field of DSTSTRENG6 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG6_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG6 register. + * + * \param[in] reg is the value of the DSTSTRENG6 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG6 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG6_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG7 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG7 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG7_OFFSET 0x24UL + +/** Reset value of the DSTSTRENG7 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG7_DT \ + (ATON_STRSWITCH_DSTSTRENG7_EN0_DT << ATON_STRSWITCH_DSTSTRENG7_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG7_LINK0_DT << ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG7_FNR0_DT << ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG7_EN1_DT << ATON_STRSWITCH_DSTSTRENG7_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG7_LINK1_DT << ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG7_FNR1_DT << ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB) + + + +/** Description of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_DESC "Connection to input port of Stream Engine 7" + +/** Address of the DSTSTRENG7 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG7_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG7_OFFSET) + +/** Get the content of the DSTSTRENG7 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG7_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG7 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG7_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG7 register. + * + * \return the description of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_DESC; +} + + +/** + * Get the offset of the DSTSTRENG7 register. + * + * \return the offset of DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG7_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG7 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG7 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG7 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG7_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG7 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG7 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG7 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG7 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG7 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG7_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG7_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG7 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN0_LSB, ATON_STRSWITCH_DSTSTRENG7_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN0_LSB, ATON_STRSWITCH_DSTSTRENG7_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG7 register. + * + * \return the description of the EN0 field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the EN0 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG7 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG7 register. + * + * \return the description of the LINK0 field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG7 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG7 register. + * + * \return the description of the FNR0 field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG7 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN1_LSB, ATON_STRSWITCH_DSTSTRENG7_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN1_LSB, ATON_STRSWITCH_DSTSTRENG7_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG7 register. + * + * \return the description of the EN1 field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the EN1 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG7 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG7 register. + * + * \return the description of the LINK1 field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG7 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG7 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG7 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG7 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG7 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG7_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG7 register. */ +#define ATON_STRSWITCH_DSTSTRENG7_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG7 register. + * + * \return the description of the FNR1 field of DSTSTRENG7 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG7_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG7 register. + * + * \param[in] reg is the value of the DSTSTRENG7 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG7 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG7_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG8 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG8 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG8_OFFSET 0x28UL + +/** Reset value of the DSTSTRENG8 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG8_DT \ + (ATON_STRSWITCH_DSTSTRENG8_EN0_DT << ATON_STRSWITCH_DSTSTRENG8_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG8_LINK0_DT << ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG8_FNR0_DT << ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG8_EN1_DT << ATON_STRSWITCH_DSTSTRENG8_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG8_LINK1_DT << ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG8_FNR1_DT << ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB) + + + +/** Description of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_DESC "Connection to input port of Stream Engine 8" + +/** Address of the DSTSTRENG8 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG8_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG8_OFFSET) + +/** Get the content of the DSTSTRENG8 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG8_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG8 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG8_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG8 register. + * + * \return the description of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_DESC; +} + + +/** + * Get the offset of the DSTSTRENG8 register. + * + * \return the offset of DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG8_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG8 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG8 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG8 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG8_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG8 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG8 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG8 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG8 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG8 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG8_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG8_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG8 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN0_LSB, ATON_STRSWITCH_DSTSTRENG8_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN0_LSB, ATON_STRSWITCH_DSTSTRENG8_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG8 register. + * + * \return the description of the EN0 field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the EN0 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG8 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG8 register. + * + * \return the description of the LINK0 field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG8 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG8 register. + * + * \return the description of the FNR0 field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG8 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN1_LSB, ATON_STRSWITCH_DSTSTRENG8_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN1_LSB, ATON_STRSWITCH_DSTSTRENG8_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG8 register. + * + * \return the description of the EN1 field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the EN1 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG8 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG8 register. + * + * \return the description of the LINK1 field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG8 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG8 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG8 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG8 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG8 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG8_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG8 register. */ +#define ATON_STRSWITCH_DSTSTRENG8_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG8 register. + * + * \return the description of the FNR1 field of DSTSTRENG8 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG8_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG8 register. + * + * \param[in] reg is the value of the DSTSTRENG8 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG8 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG8_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTSTRENG9 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTSTRENG9 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG9_OFFSET 0x2cUL + +/** Reset value of the DSTSTRENG9 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTSTRENG9_DT \ + (ATON_STRSWITCH_DSTSTRENG9_EN0_DT << ATON_STRSWITCH_DSTSTRENG9_EN0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG9_LINK0_DT << ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG9_FNR0_DT << ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG9_EN1_DT << ATON_STRSWITCH_DSTSTRENG9_EN1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG9_LINK1_DT << ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTSTRENG9_FNR1_DT << ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB) + + + +/** Description of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_DESC "Connection to input port of Stream Engine 9" + +/** Address of the DSTSTRENG9 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG9_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG9_OFFSET) + +/** Get the content of the DSTSTRENG9 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG9_ADDR(UNIT))) + +/** Set the content of the DSTSTRENG9 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG9_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTSTRENG9 register. + * + * \return the description of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_DESC; +} + + +/** + * Get the offset of the DSTSTRENG9 register. + * + * \return the offset of DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_GetOffset(void) +{ + return ATON_STRSWITCH_DSTSTRENG9_OFFSET; +} + + +/** + * Get the address of the DSTSTRENG9 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG9 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTSTRENG9 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG9_ADDR(instance); +} + + +/** + * Read the content of the DSTSTRENG9 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG9 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTSTRENG9 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET(instance); +} + + +/** + * Write the content of the DSTSTRENG9 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG9 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTSTRENG9_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTSTRENG9_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTSTRENG9 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN0_P 0 + +/** Read the content of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN0_LSB, ATON_STRSWITCH_DSTSTRENG9_EN0_W) + +/** Modify the content of the EN0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN0_LSB, ATON_STRSWITCH_DSTSTRENG9_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTSTRENG9 register. + * + * \return the description of the EN0 field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the EN0 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTSTRENG9 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTSTRENG9 register. + * + * \return the description of the LINK0 field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the LINK0 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTSTRENG9 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTSTRENG9 register. + * + * \return the description of the FNR0 field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the FNR0 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTSTRENG9 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_EN1_P 0 + +/** Read the content of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN1_LSB, ATON_STRSWITCH_DSTSTRENG9_EN1_W) + +/** Modify the content of the EN1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN1_LSB, ATON_STRSWITCH_DSTSTRENG9_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTSTRENG9 register. + * + * \return the description of the EN1 field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the EN1 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTSTRENG9 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTSTRENG9 register. + * + * \return the description of the LINK1 field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the LINK1 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG9 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTSTRENG9 register. + * + * \return the description of the TICKTYPE field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the TICKTYPE field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTSTRENG9 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTSTRENG9 register is secured or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTSTRENG9 register is privileged or not. */ +#define ATON_STRSWITCH_DSTSTRENG9_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTSTRENG9 register. */ +#define ATON_STRSWITCH_DSTSTRENG9_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTSTRENG9 register. + * + * \return the description of the FNR1 field of DSTSTRENG9 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * + * \return the content of the FNR1 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTSTRENG9_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTSTRENG9 register. + * + * \param[in] reg is the value of the DSTSTRENG9 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTSTRENG9 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTSTRENG9_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC00 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC00 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC00_OFFSET 0x30UL + +/** Reset value of the DSTCONVACC00 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC00_DT \ + (ATON_STRSWITCH_DSTCONVACC00_EN0_DT << ATON_STRSWITCH_DSTCONVACC00_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC00_LINK0_DT << ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC00_FNR0_DT << ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC00_EN1_DT << ATON_STRSWITCH_DSTCONVACC00_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC00_LINK1_DT << ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC00_FNR1_DT << ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB) + + + +/** Description of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_DESC "Connection to input port 0 of Convolutional Accelerator 0" + +/** Address of the DSTCONVACC00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC00_OFFSET) + +/** Get the content of the DSTCONVACC00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC00_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC00_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC00 register. + * + * \return the description of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_DESC; +} + + +/** + * Get the offset of the DSTCONVACC00 register. + * + * \return the offset of DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC00_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC00 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC00_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC00 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC00 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC00_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC00_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC00 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN0_LSB, ATON_STRSWITCH_DSTCONVACC00_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN0_LSB, ATON_STRSWITCH_DSTCONVACC00_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC00 register. + * + * \return the description of the EN0 field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the EN0 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC00 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC00 register. + * + * \return the description of the LINK0 field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC00 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC00 register. + * + * \return the description of the FNR0 field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC00 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN1_LSB, ATON_STRSWITCH_DSTCONVACC00_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN1_LSB, ATON_STRSWITCH_DSTCONVACC00_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC00 register. + * + * \return the description of the EN1 field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the EN1 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC00 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC00 register. + * + * \return the description of the LINK1 field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC00 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC00 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC00 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC00 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC00_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC00 register. */ +#define ATON_STRSWITCH_DSTCONVACC00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC00 register. + * + * \return the description of the FNR1 field of DSTCONVACC00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC00_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC00 register. + * + * \param[in] reg is the value of the DSTCONVACC00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC00_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC01 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC01 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC01_OFFSET 0x34UL + +/** Reset value of the DSTCONVACC01 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC01_DT \ + (ATON_STRSWITCH_DSTCONVACC01_EN0_DT << ATON_STRSWITCH_DSTCONVACC01_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC01_LINK0_DT << ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC01_FNR0_DT << ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC01_EN1_DT << ATON_STRSWITCH_DSTCONVACC01_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC01_LINK1_DT << ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC01_FNR1_DT << ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB) + + + +/** Description of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_DESC "Connection to input port 1 of Convolutional Accelerator 0" + +/** Address of the DSTCONVACC01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC01_OFFSET) + +/** Get the content of the DSTCONVACC01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC01_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC01_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC01 register. + * + * \return the description of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_DESC; +} + + +/** + * Get the offset of the DSTCONVACC01 register. + * + * \return the offset of DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC01_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC01 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC01_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC01 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC01 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC01_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC01_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC01 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN0_LSB, ATON_STRSWITCH_DSTCONVACC01_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN0_LSB, ATON_STRSWITCH_DSTCONVACC01_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC01 register. + * + * \return the description of the EN0 field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the EN0 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC01 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC01 register. + * + * \return the description of the LINK0 field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC01 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC01 register. + * + * \return the description of the FNR0 field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC01 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN1_LSB, ATON_STRSWITCH_DSTCONVACC01_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN1_LSB, ATON_STRSWITCH_DSTCONVACC01_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC01 register. + * + * \return the description of the EN1 field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the EN1 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC01 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC01 register. + * + * \return the description of the LINK1 field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC01 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC01 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC01 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC01 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC01_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC01 register. */ +#define ATON_STRSWITCH_DSTCONVACC01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC01 register. + * + * \return the description of the FNR1 field of DSTCONVACC01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC01_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC01 register. + * + * \param[in] reg is the value of the DSTCONVACC01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC01_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC02 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC02 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC02_OFFSET 0x38UL + +/** Reset value of the DSTCONVACC02 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC02_DT \ + (ATON_STRSWITCH_DSTCONVACC02_EN0_DT << ATON_STRSWITCH_DSTCONVACC02_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC02_LINK0_DT << ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC02_FNR0_DT << ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC02_EN1_DT << ATON_STRSWITCH_DSTCONVACC02_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC02_LINK1_DT << ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC02_FNR1_DT << ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB) + + + +/** Description of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_DESC "Connection to input port 2 of Convolutional Accelerator 0" + +/** Address of the DSTCONVACC02 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC02_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC02_OFFSET) + +/** Get the content of the DSTCONVACC02 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC02_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC02 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC02_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC02 register. + * + * \return the description of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_DESC; +} + + +/** + * Get the offset of the DSTCONVACC02 register. + * + * \return the offset of DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC02_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC02 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC02 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC02 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC02_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC02 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC02 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC02 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC02 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC02 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC02_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC02_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC02 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN0_LSB, ATON_STRSWITCH_DSTCONVACC02_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN0_LSB, ATON_STRSWITCH_DSTCONVACC02_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC02 register. + * + * \return the description of the EN0 field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the EN0 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC02 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC02 register. + * + * \return the description of the LINK0 field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC02 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC02 register. + * + * \return the description of the FNR0 field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC02 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN1_LSB, ATON_STRSWITCH_DSTCONVACC02_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN1_LSB, ATON_STRSWITCH_DSTCONVACC02_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC02 register. + * + * \return the description of the EN1 field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the EN1 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC02 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC02 register. + * + * \return the description of the LINK1 field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC02 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC02 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC02 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC02 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC02_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC02 register. */ +#define ATON_STRSWITCH_DSTCONVACC02_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC02 register. + * + * \return the description of the FNR1 field of DSTCONVACC02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC02_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC02 register. + * + * \param[in] reg is the value of the DSTCONVACC02 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC02_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC10 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC10 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC10_OFFSET 0x3cUL + +/** Reset value of the DSTCONVACC10 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC10_DT \ + (ATON_STRSWITCH_DSTCONVACC10_EN0_DT << ATON_STRSWITCH_DSTCONVACC10_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC10_LINK0_DT << ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC10_FNR0_DT << ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC10_EN1_DT << ATON_STRSWITCH_DSTCONVACC10_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC10_LINK1_DT << ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC10_FNR1_DT << ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB) + + + +/** Description of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_DESC "Connection to input port 0 of Convolutional Accelerator 1" + +/** Address of the DSTCONVACC10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC10_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC10_OFFSET) + +/** Get the content of the DSTCONVACC10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC10_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC10_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC10 register. + * + * \return the description of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_DESC; +} + + +/** + * Get the offset of the DSTCONVACC10 register. + * + * \return the offset of DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC10_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC10 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC10 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC10_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC10 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC10 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC10 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC10_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC10_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC10 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN0_LSB, ATON_STRSWITCH_DSTCONVACC10_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN0_LSB, ATON_STRSWITCH_DSTCONVACC10_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC10 register. + * + * \return the description of the EN0 field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the EN0 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC10 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC10 register. + * + * \return the description of the LINK0 field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC10 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC10 register. + * + * \return the description of the FNR0 field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC10 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN1_LSB, ATON_STRSWITCH_DSTCONVACC10_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN1_LSB, ATON_STRSWITCH_DSTCONVACC10_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC10 register. + * + * \return the description of the EN1 field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the EN1 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC10 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC10 register. + * + * \return the description of the LINK1 field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC10 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC10 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC10 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC10 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC10_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC10 register. */ +#define ATON_STRSWITCH_DSTCONVACC10_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC10 register. + * + * \return the description of the FNR1 field of DSTCONVACC10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC10_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC10 register. + * + * \param[in] reg is the value of the DSTCONVACC10 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC10_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC11 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC11 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC11_OFFSET 0x40UL + +/** Reset value of the DSTCONVACC11 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC11_DT \ + (ATON_STRSWITCH_DSTCONVACC11_EN0_DT << ATON_STRSWITCH_DSTCONVACC11_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC11_LINK0_DT << ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC11_FNR0_DT << ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC11_EN1_DT << ATON_STRSWITCH_DSTCONVACC11_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC11_LINK1_DT << ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC11_FNR1_DT << ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB) + + + +/** Description of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_DESC "Connection to input port 1 of Convolutional Accelerator 1" + +/** Address of the DSTCONVACC11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC11_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC11_OFFSET) + +/** Get the content of the DSTCONVACC11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC11_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC11_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC11 register. + * + * \return the description of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_DESC; +} + + +/** + * Get the offset of the DSTCONVACC11 register. + * + * \return the offset of DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC11_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC11 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC11 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC11_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC11 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC11 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC11 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC11_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC11_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC11 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN0_LSB, ATON_STRSWITCH_DSTCONVACC11_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN0_LSB, ATON_STRSWITCH_DSTCONVACC11_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC11 register. + * + * \return the description of the EN0 field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the EN0 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC11 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC11 register. + * + * \return the description of the LINK0 field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC11 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC11 register. + * + * \return the description of the FNR0 field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC11 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN1_LSB, ATON_STRSWITCH_DSTCONVACC11_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN1_LSB, ATON_STRSWITCH_DSTCONVACC11_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC11 register. + * + * \return the description of the EN1 field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the EN1 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC11 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC11 register. + * + * \return the description of the LINK1 field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC11 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC11 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC11 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC11 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC11_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC11 register. */ +#define ATON_STRSWITCH_DSTCONVACC11_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC11 register. + * + * \return the description of the FNR1 field of DSTCONVACC11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC11_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC11 register. + * + * \param[in] reg is the value of the DSTCONVACC11 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC11_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC12 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC12 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC12_OFFSET 0x44UL + +/** Reset value of the DSTCONVACC12 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC12_DT \ + (ATON_STRSWITCH_DSTCONVACC12_EN0_DT << ATON_STRSWITCH_DSTCONVACC12_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC12_LINK0_DT << ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC12_FNR0_DT << ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC12_EN1_DT << ATON_STRSWITCH_DSTCONVACC12_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC12_LINK1_DT << ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC12_FNR1_DT << ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB) + + + +/** Description of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_DESC "Connection to input port 2 of Convolutional Accelerator 1" + +/** Address of the DSTCONVACC12 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC12_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC12_OFFSET) + +/** Get the content of the DSTCONVACC12 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC12_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC12 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC12_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC12 register. + * + * \return the description of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_DESC; +} + + +/** + * Get the offset of the DSTCONVACC12 register. + * + * \return the offset of DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC12_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC12 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC12 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC12 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC12_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC12 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC12 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC12 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC12 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC12 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC12_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC12_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC12 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN0_LSB, ATON_STRSWITCH_DSTCONVACC12_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN0_LSB, ATON_STRSWITCH_DSTCONVACC12_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC12 register. + * + * \return the description of the EN0 field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the EN0 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC12 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC12 register. + * + * \return the description of the LINK0 field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC12 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC12 register. + * + * \return the description of the FNR0 field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC12 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN1_LSB, ATON_STRSWITCH_DSTCONVACC12_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN1_LSB, ATON_STRSWITCH_DSTCONVACC12_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC12 register. + * + * \return the description of the EN1 field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the EN1 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC12 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC12 register. + * + * \return the description of the LINK1 field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC12 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC12 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC12 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC12 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC12 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC12_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC12 register. */ +#define ATON_STRSWITCH_DSTCONVACC12_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC12 register. + * + * \return the description of the FNR1 field of DSTCONVACC12 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC12_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC12 register. + * + * \param[in] reg is the value of the DSTCONVACC12 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC12 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC12_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC20 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC20 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC20_OFFSET 0x48UL + +/** Reset value of the DSTCONVACC20 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC20_DT \ + (ATON_STRSWITCH_DSTCONVACC20_EN0_DT << ATON_STRSWITCH_DSTCONVACC20_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC20_LINK0_DT << ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC20_FNR0_DT << ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC20_EN1_DT << ATON_STRSWITCH_DSTCONVACC20_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC20_LINK1_DT << ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC20_FNR1_DT << ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB) + + + +/** Description of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_DESC "Connection to input port 0 of Convolutional Accelerator 2" + +/** Address of the DSTCONVACC20 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC20_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC20_OFFSET) + +/** Get the content of the DSTCONVACC20 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC20_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC20 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC20_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC20 register. + * + * \return the description of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_DESC; +} + + +/** + * Get the offset of the DSTCONVACC20 register. + * + * \return the offset of DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC20_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC20 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC20 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC20 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC20_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC20 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC20 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC20 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC20 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC20 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC20_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC20_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC20 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN0_LSB, ATON_STRSWITCH_DSTCONVACC20_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN0_LSB, ATON_STRSWITCH_DSTCONVACC20_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC20 register. + * + * \return the description of the EN0 field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the EN0 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC20 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC20 register. + * + * \return the description of the LINK0 field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC20 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC20 register. + * + * \return the description of the FNR0 field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC20 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN1_LSB, ATON_STRSWITCH_DSTCONVACC20_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN1_LSB, ATON_STRSWITCH_DSTCONVACC20_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC20 register. + * + * \return the description of the EN1 field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the EN1 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC20 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC20 register. + * + * \return the description of the LINK1 field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC20 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC20 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC20 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC20 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC20_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC20 register. */ +#define ATON_STRSWITCH_DSTCONVACC20_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC20 register. + * + * \return the description of the FNR1 field of DSTCONVACC20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC20_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC20 register. + * + * \param[in] reg is the value of the DSTCONVACC20 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC20_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC21 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC21 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC21_OFFSET 0x4cUL + +/** Reset value of the DSTCONVACC21 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC21_DT \ + (ATON_STRSWITCH_DSTCONVACC21_EN0_DT << ATON_STRSWITCH_DSTCONVACC21_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC21_LINK0_DT << ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC21_FNR0_DT << ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC21_EN1_DT << ATON_STRSWITCH_DSTCONVACC21_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC21_LINK1_DT << ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC21_FNR1_DT << ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB) + + + +/** Description of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_DESC "Connection to input port 1 of Convolutional Accelerator 2" + +/** Address of the DSTCONVACC21 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC21_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC21_OFFSET) + +/** Get the content of the DSTCONVACC21 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC21_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC21 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC21_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC21 register. + * + * \return the description of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_DESC; +} + + +/** + * Get the offset of the DSTCONVACC21 register. + * + * \return the offset of DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC21_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC21 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC21 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC21 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC21_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC21 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC21 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC21 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC21 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC21 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC21_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC21_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC21 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN0_LSB, ATON_STRSWITCH_DSTCONVACC21_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN0_LSB, ATON_STRSWITCH_DSTCONVACC21_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC21 register. + * + * \return the description of the EN0 field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the EN0 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC21 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC21 register. + * + * \return the description of the LINK0 field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC21 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC21 register. + * + * \return the description of the FNR0 field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC21 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN1_LSB, ATON_STRSWITCH_DSTCONVACC21_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN1_LSB, ATON_STRSWITCH_DSTCONVACC21_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC21 register. + * + * \return the description of the EN1 field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the EN1 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC21 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC21 register. + * + * \return the description of the LINK1 field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC21 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC21 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC21 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC21 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC21_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC21 register. */ +#define ATON_STRSWITCH_DSTCONVACC21_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC21 register. + * + * \return the description of the FNR1 field of DSTCONVACC21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC21_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC21 register. + * + * \param[in] reg is the value of the DSTCONVACC21 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC21_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC22 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC22 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC22_OFFSET 0x50UL + +/** Reset value of the DSTCONVACC22 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC22_DT \ + (ATON_STRSWITCH_DSTCONVACC22_EN0_DT << ATON_STRSWITCH_DSTCONVACC22_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC22_LINK0_DT << ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC22_FNR0_DT << ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC22_EN1_DT << ATON_STRSWITCH_DSTCONVACC22_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC22_LINK1_DT << ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC22_FNR1_DT << ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB) + + + +/** Description of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_DESC "Connection to input port 2 of Convolutional Accelerator 2" + +/** Address of the DSTCONVACC22 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC22_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC22_OFFSET) + +/** Get the content of the DSTCONVACC22 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC22_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC22 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC22_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC22 register. + * + * \return the description of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_DESC; +} + + +/** + * Get the offset of the DSTCONVACC22 register. + * + * \return the offset of DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC22_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC22 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC22 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC22 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC22_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC22 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC22 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC22 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC22 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC22 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC22_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC22_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC22 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN0_LSB, ATON_STRSWITCH_DSTCONVACC22_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN0_LSB, ATON_STRSWITCH_DSTCONVACC22_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC22 register. + * + * \return the description of the EN0 field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the EN0 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC22 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC22 register. + * + * \return the description of the LINK0 field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC22 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC22 register. + * + * \return the description of the FNR0 field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC22 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN1_LSB, ATON_STRSWITCH_DSTCONVACC22_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN1_LSB, ATON_STRSWITCH_DSTCONVACC22_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC22 register. + * + * \return the description of the EN1 field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the EN1 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC22 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC22 register. + * + * \return the description of the LINK1 field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC22 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC22 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC22 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC22 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC22 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC22_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC22 register. */ +#define ATON_STRSWITCH_DSTCONVACC22_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC22 register. + * + * \return the description of the FNR1 field of DSTCONVACC22 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC22_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC22 register. + * + * \param[in] reg is the value of the DSTCONVACC22 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC22 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC22_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC30 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC30 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC30_OFFSET 0x54UL + +/** Reset value of the DSTCONVACC30 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC30_DT \ + (ATON_STRSWITCH_DSTCONVACC30_EN0_DT << ATON_STRSWITCH_DSTCONVACC30_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC30_LINK0_DT << ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC30_FNR0_DT << ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC30_EN1_DT << ATON_STRSWITCH_DSTCONVACC30_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC30_LINK1_DT << ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC30_FNR1_DT << ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB) + + + +/** Description of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_DESC "Connection to input port 0 of Convolutional Accelerator 3" + +/** Address of the DSTCONVACC30 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC30_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC30_OFFSET) + +/** Get the content of the DSTCONVACC30 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC30_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC30 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC30_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC30 register. + * + * \return the description of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_DESC; +} + + +/** + * Get the offset of the DSTCONVACC30 register. + * + * \return the offset of DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC30_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC30 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC30 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC30 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC30_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC30 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC30 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC30 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC30 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC30 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC30_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC30_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC30 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN0_LSB, ATON_STRSWITCH_DSTCONVACC30_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN0_LSB, ATON_STRSWITCH_DSTCONVACC30_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC30 register. + * + * \return the description of the EN0 field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the EN0 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC30 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC30 register. + * + * \return the description of the LINK0 field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC30 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC30 register. + * + * \return the description of the FNR0 field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC30 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN1_LSB, ATON_STRSWITCH_DSTCONVACC30_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN1_LSB, ATON_STRSWITCH_DSTCONVACC30_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC30 register. + * + * \return the description of the EN1 field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the EN1 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC30 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC30 register. + * + * \return the description of the LINK1 field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC30 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC30 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC30 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC30 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC30_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC30 register. */ +#define ATON_STRSWITCH_DSTCONVACC30_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC30 register. + * + * \return the description of the FNR1 field of DSTCONVACC30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC30_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC30 register. + * + * \param[in] reg is the value of the DSTCONVACC30 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC30_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC31 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC31 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC31_OFFSET 0x58UL + +/** Reset value of the DSTCONVACC31 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC31_DT \ + (ATON_STRSWITCH_DSTCONVACC31_EN0_DT << ATON_STRSWITCH_DSTCONVACC31_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC31_LINK0_DT << ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC31_FNR0_DT << ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC31_EN1_DT << ATON_STRSWITCH_DSTCONVACC31_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC31_LINK1_DT << ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC31_FNR1_DT << ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB) + + + +/** Description of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_DESC "Connection to input port 1 of Convolutional Accelerator 3" + +/** Address of the DSTCONVACC31 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC31_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC31_OFFSET) + +/** Get the content of the DSTCONVACC31 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC31_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC31 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC31_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC31 register. + * + * \return the description of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_DESC; +} + + +/** + * Get the offset of the DSTCONVACC31 register. + * + * \return the offset of DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC31_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC31 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC31 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC31 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC31_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC31 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC31 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC31 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC31 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC31 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC31_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC31_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC31 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN0_LSB, ATON_STRSWITCH_DSTCONVACC31_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN0_LSB, ATON_STRSWITCH_DSTCONVACC31_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC31 register. + * + * \return the description of the EN0 field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the EN0 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC31 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC31 register. + * + * \return the description of the LINK0 field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC31 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC31 register. + * + * \return the description of the FNR0 field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC31 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN1_LSB, ATON_STRSWITCH_DSTCONVACC31_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN1_LSB, ATON_STRSWITCH_DSTCONVACC31_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC31 register. + * + * \return the description of the EN1 field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the EN1 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC31 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC31 register. + * + * \return the description of the LINK1 field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC31 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC31 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC31 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC31 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC31_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC31 register. */ +#define ATON_STRSWITCH_DSTCONVACC31_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC31 register. + * + * \return the description of the FNR1 field of DSTCONVACC31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC31_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC31 register. + * + * \param[in] reg is the value of the DSTCONVACC31 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC31_SET_FNR1(reg, data); +} + + +/* ************************************************** DSTCONVACC32 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTCONVACC32 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC32_OFFSET 0x5cUL + +/** Reset value of the DSTCONVACC32 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTCONVACC32_DT \ + (ATON_STRSWITCH_DSTCONVACC32_EN0_DT << ATON_STRSWITCH_DSTCONVACC32_EN0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC32_LINK0_DT << ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC32_FNR0_DT << ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC32_EN1_DT << ATON_STRSWITCH_DSTCONVACC32_EN1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC32_LINK1_DT << ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTCONVACC32_FNR1_DT << ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB) + + + +/** Description of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_DESC "Connection to input port 2 of Convolutional Accelerator 3" + +/** Address of the DSTCONVACC32 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC32_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC32_OFFSET) + +/** Get the content of the DSTCONVACC32 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC32_ADDR(UNIT))) + +/** Set the content of the DSTCONVACC32 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC32_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTCONVACC32 register. + * + * \return the description of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_DESC; +} + + +/** + * Get the offset of the DSTCONVACC32 register. + * + * \return the offset of DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_GetOffset(void) +{ + return ATON_STRSWITCH_DSTCONVACC32_OFFSET; +} + + +/** + * Get the address of the DSTCONVACC32 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC32 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTCONVACC32 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC32_ADDR(instance); +} + + +/** + * Read the content of the DSTCONVACC32 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC32 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTCONVACC32 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET(instance); +} + + +/** + * Write the content of the DSTCONVACC32 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC32 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTCONVACC32_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTCONVACC32_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTCONVACC32 register --------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN0_P 0 + +/** Read the content of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN0_LSB, ATON_STRSWITCH_DSTCONVACC32_EN0_W) + +/** Modify the content of the EN0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN0_LSB, ATON_STRSWITCH_DSTCONVACC32_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTCONVACC32 register. + * + * \return the description of the EN0 field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the EN0 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTCONVACC32 register -------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTCONVACC32 register. + * + * \return the description of the LINK0 field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the LINK0 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_LINK0(reg, data); +} + + +/* -------------------------------------------------------- FNR0 field of the DSTCONVACC32 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTCONVACC32 register. + * + * \return the description of the FNR0 field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the FNR0 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTCONVACC32 register --------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_EN1_P 0 + +/** Read the content of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN1_LSB, ATON_STRSWITCH_DSTCONVACC32_EN1_W) + +/** Modify the content of the EN1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN1_LSB, ATON_STRSWITCH_DSTCONVACC32_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTCONVACC32 register. + * + * \return the description of the EN1 field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the EN1 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTCONVACC32 register -------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTCONVACC32 register. + * + * \return the description of the LINK1 field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the LINK1 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC32 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTCONVACC32 register. + * + * \return the description of the TICKTYPE field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the TICKTYPE field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_TICKTYPE(reg, data); +} + + +/* -------------------------------------------------------- FNR1 field of the DSTCONVACC32 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTCONVACC32 register is secured or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTCONVACC32 register is privileged or not. */ +#define ATON_STRSWITCH_DSTCONVACC32_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTCONVACC32 register. */ +#define ATON_STRSWITCH_DSTCONVACC32_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTCONVACC32 register. + * + * \return the description of the FNR1 field of DSTCONVACC32 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * + * \return the content of the FNR1 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTCONVACC32_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTCONVACC32 register. + * + * \param[in] reg is the value of the DSTCONVACC32 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTCONVACC32 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTCONVACC32_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTDECUN00 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTDECUN00 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN00_OFFSET 0x60UL + +/** Reset value of the DSTDECUN00 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN00_DT \ + (ATON_STRSWITCH_DSTDECUN00_EN0_DT << ATON_STRSWITCH_DSTDECUN00_EN0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN00_LINK0_DT << ATON_STRSWITCH_DSTDECUN00_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN00_FNR0_DT << ATON_STRSWITCH_DSTDECUN00_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN00_EN1_DT << ATON_STRSWITCH_DSTDECUN00_EN1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN00_LINK1_DT << ATON_STRSWITCH_DSTDECUN00_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTDECUN00_FNR1_DT << ATON_STRSWITCH_DSTDECUN00_FNR1_LSB) + + + +/** Description of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_DESC "Connection to input port 0 of Decompression Unit 0" + +/** Address of the DSTDECUN00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN00_OFFSET) + +/** Get the content of the DSTDECUN00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN00_ADDR(UNIT))) + +/** Set the content of the DSTDECUN00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN00_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTDECUN00 register. + * + * \return the description of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_DESC; +} + + +/** + * Get the offset of the DSTDECUN00 register. + * + * \return the offset of DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_GetOffset(void) +{ + return ATON_STRSWITCH_DSTDECUN00_OFFSET; +} + + +/** + * Get the address of the DSTDECUN00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN00 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTDECUN00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN00_ADDR(instance); +} + + +/** + * Read the content of the DSTDECUN00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN00 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTDECUN00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN00_GET(instance); +} + + +/** + * Write the content of the DSTDECUN00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN00 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTDECUN00_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTDECUN00_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTDECUN00 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_EN0_P 0 + +/** Read the content of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN0_LSB, ATON_STRSWITCH_DSTDECUN00_EN0_W) + +/** Modify the content of the EN0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN0_LSB, ATON_STRSWITCH_DSTDECUN00_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTDECUN00 register. + * + * \return the description of the EN0 field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the EN0 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTDECUN00 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK0_LSB, ATON_STRSWITCH_DSTDECUN00_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK0_LSB, ATON_STRSWITCH_DSTDECUN00_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTDECUN00 register. + * + * \return the description of the LINK0 field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the LINK0 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTDECUN00 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR0_LSB, ATON_STRSWITCH_DSTDECUN00_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR0_LSB, ATON_STRSWITCH_DSTDECUN00_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTDECUN00 register. + * + * \return the description of the FNR0 field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the FNR0 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTDECUN00 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_EN1_P 0 + +/** Read the content of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN1_LSB, ATON_STRSWITCH_DSTDECUN00_EN1_W) + +/** Modify the content of the EN1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN1_LSB, ATON_STRSWITCH_DSTDECUN00_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTDECUN00 register. + * + * \return the description of the EN1 field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the EN1 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTDECUN00 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK1_LSB, ATON_STRSWITCH_DSTDECUN00_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK1_LSB, ATON_STRSWITCH_DSTDECUN00_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTDECUN00 register. + * + * \return the description of the LINK1 field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the LINK1 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTDECUN00 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTDECUN00 register. + * + * \return the description of the TICKTYPE field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the TICKTYPE field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTDECUN00 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTDECUN00 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTDECUN00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN00_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR1_LSB, ATON_STRSWITCH_DSTDECUN00_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTDECUN00 register. */ +#define ATON_STRSWITCH_DSTDECUN00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR1_LSB, ATON_STRSWITCH_DSTDECUN00_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTDECUN00 register. + * + * \return the description of the FNR1 field of DSTDECUN00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * + * \return the content of the FNR1 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN00_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTDECUN00 register. + * + * \param[in] reg is the value of the DSTDECUN00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTDECUN00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN00_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTDECUN01 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTDECUN01 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN01_OFFSET 0x64UL + +/** Reset value of the DSTDECUN01 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN01_DT \ + (ATON_STRSWITCH_DSTDECUN01_EN0_DT << ATON_STRSWITCH_DSTDECUN01_EN0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN01_LINK0_DT << ATON_STRSWITCH_DSTDECUN01_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN01_FNR0_DT << ATON_STRSWITCH_DSTDECUN01_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN01_EN1_DT << ATON_STRSWITCH_DSTDECUN01_EN1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN01_LINK1_DT << ATON_STRSWITCH_DSTDECUN01_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTDECUN01_FNR1_DT << ATON_STRSWITCH_DSTDECUN01_FNR1_LSB) + + + +/** Description of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_DESC "Connection to input port 1 of Decompression Unit 0" + +/** Address of the DSTDECUN01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN01_OFFSET) + +/** Get the content of the DSTDECUN01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN01_ADDR(UNIT))) + +/** Set the content of the DSTDECUN01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN01_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTDECUN01 register. + * + * \return the description of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_DESC; +} + + +/** + * Get the offset of the DSTDECUN01 register. + * + * \return the offset of DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_GetOffset(void) +{ + return ATON_STRSWITCH_DSTDECUN01_OFFSET; +} + + +/** + * Get the address of the DSTDECUN01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN01 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTDECUN01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN01_ADDR(instance); +} + + +/** + * Read the content of the DSTDECUN01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN01 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTDECUN01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN01_GET(instance); +} + + +/** + * Write the content of the DSTDECUN01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN01 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTDECUN01_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTDECUN01_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTDECUN01 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_EN0_P 0 + +/** Read the content of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN0_LSB, ATON_STRSWITCH_DSTDECUN01_EN0_W) + +/** Modify the content of the EN0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN0_LSB, ATON_STRSWITCH_DSTDECUN01_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTDECUN01 register. + * + * \return the description of the EN0 field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the EN0 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTDECUN01 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK0_LSB, ATON_STRSWITCH_DSTDECUN01_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK0_LSB, ATON_STRSWITCH_DSTDECUN01_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTDECUN01 register. + * + * \return the description of the LINK0 field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the LINK0 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTDECUN01 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR0_LSB, ATON_STRSWITCH_DSTDECUN01_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR0_LSB, ATON_STRSWITCH_DSTDECUN01_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTDECUN01 register. + * + * \return the description of the FNR0 field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the FNR0 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTDECUN01 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_EN1_P 0 + +/** Read the content of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN1_LSB, ATON_STRSWITCH_DSTDECUN01_EN1_W) + +/** Modify the content of the EN1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN1_LSB, ATON_STRSWITCH_DSTDECUN01_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTDECUN01 register. + * + * \return the description of the EN1 field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the EN1 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTDECUN01 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK1_LSB, ATON_STRSWITCH_DSTDECUN01_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK1_LSB, ATON_STRSWITCH_DSTDECUN01_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTDECUN01 register. + * + * \return the description of the LINK1 field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the LINK1 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTDECUN01 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTDECUN01 register. + * + * \return the description of the TICKTYPE field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the TICKTYPE field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTDECUN01 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTDECUN01 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTDECUN01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN01_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR1_LSB, ATON_STRSWITCH_DSTDECUN01_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTDECUN01 register. */ +#define ATON_STRSWITCH_DSTDECUN01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR1_LSB, ATON_STRSWITCH_DSTDECUN01_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTDECUN01 register. + * + * \return the description of the FNR1 field of DSTDECUN01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * + * \return the content of the FNR1 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN01_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTDECUN01 register. + * + * \param[in] reg is the value of the DSTDECUN01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTDECUN01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN01_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTDECUN10 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTDECUN10 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN10_OFFSET 0x68UL + +/** Reset value of the DSTDECUN10 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN10_DT \ + (ATON_STRSWITCH_DSTDECUN10_EN0_DT << ATON_STRSWITCH_DSTDECUN10_EN0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN10_LINK0_DT << ATON_STRSWITCH_DSTDECUN10_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN10_FNR0_DT << ATON_STRSWITCH_DSTDECUN10_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN10_EN1_DT << ATON_STRSWITCH_DSTDECUN10_EN1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN10_LINK1_DT << ATON_STRSWITCH_DSTDECUN10_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTDECUN10_FNR1_DT << ATON_STRSWITCH_DSTDECUN10_FNR1_LSB) + + + +/** Description of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_DESC "Connection to input port 0 of Decompression Unit 1" + +/** Address of the DSTDECUN10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN10_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN10_OFFSET) + +/** Get the content of the DSTDECUN10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN10_ADDR(UNIT))) + +/** Set the content of the DSTDECUN10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN10_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTDECUN10 register. + * + * \return the description of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_DESC; +} + + +/** + * Get the offset of the DSTDECUN10 register. + * + * \return the offset of DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_GetOffset(void) +{ + return ATON_STRSWITCH_DSTDECUN10_OFFSET; +} + + +/** + * Get the address of the DSTDECUN10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN10 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTDECUN10 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN10_ADDR(instance); +} + + +/** + * Read the content of the DSTDECUN10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN10 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTDECUN10 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN10_GET(instance); +} + + +/** + * Write the content of the DSTDECUN10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN10 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTDECUN10_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTDECUN10_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTDECUN10 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_EN0_P 0 + +/** Read the content of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN0_LSB, ATON_STRSWITCH_DSTDECUN10_EN0_W) + +/** Modify the content of the EN0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN0_LSB, ATON_STRSWITCH_DSTDECUN10_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTDECUN10 register. + * + * \return the description of the EN0 field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the EN0 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTDECUN10 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK0_LSB, ATON_STRSWITCH_DSTDECUN10_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK0_LSB, ATON_STRSWITCH_DSTDECUN10_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTDECUN10 register. + * + * \return the description of the LINK0 field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the LINK0 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTDECUN10 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR0_LSB, ATON_STRSWITCH_DSTDECUN10_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR0_LSB, ATON_STRSWITCH_DSTDECUN10_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTDECUN10 register. + * + * \return the description of the FNR0 field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the FNR0 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTDECUN10 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_EN1_P 0 + +/** Read the content of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN1_LSB, ATON_STRSWITCH_DSTDECUN10_EN1_W) + +/** Modify the content of the EN1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN1_LSB, ATON_STRSWITCH_DSTDECUN10_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTDECUN10 register. + * + * \return the description of the EN1 field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the EN1 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTDECUN10 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK1_LSB, ATON_STRSWITCH_DSTDECUN10_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK1_LSB, ATON_STRSWITCH_DSTDECUN10_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTDECUN10 register. + * + * \return the description of the LINK1 field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the LINK1 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTDECUN10 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTDECUN10 register. + * + * \return the description of the TICKTYPE field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the TICKTYPE field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTDECUN10 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTDECUN10 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTDECUN10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN10_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR1_LSB, ATON_STRSWITCH_DSTDECUN10_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTDECUN10 register. */ +#define ATON_STRSWITCH_DSTDECUN10_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR1_LSB, ATON_STRSWITCH_DSTDECUN10_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTDECUN10 register. + * + * \return the description of the FNR1 field of DSTDECUN10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * + * \return the content of the FNR1 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN10_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTDECUN10 register. + * + * \param[in] reg is the value of the DSTDECUN10 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTDECUN10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN10_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTDECUN11 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTDECUN11 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN11_OFFSET 0x6cUL + +/** Reset value of the DSTDECUN11 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTDECUN11_DT \ + (ATON_STRSWITCH_DSTDECUN11_EN0_DT << ATON_STRSWITCH_DSTDECUN11_EN0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN11_LINK0_DT << ATON_STRSWITCH_DSTDECUN11_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN11_FNR0_DT << ATON_STRSWITCH_DSTDECUN11_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTDECUN11_EN1_DT << ATON_STRSWITCH_DSTDECUN11_EN1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN11_LINK1_DT << ATON_STRSWITCH_DSTDECUN11_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTDECUN11_FNR1_DT << ATON_STRSWITCH_DSTDECUN11_FNR1_LSB) + + + +/** Description of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_DESC "Connection to input port 1 of Decompression Unit 1" + +/** Address of the DSTDECUN11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN11_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN11_OFFSET) + +/** Get the content of the DSTDECUN11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN11_ADDR(UNIT))) + +/** Set the content of the DSTDECUN11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTDECUN11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN11_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTDECUN11 register. + * + * \return the description of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_DESC; +} + + +/** + * Get the offset of the DSTDECUN11 register. + * + * \return the offset of DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_GetOffset(void) +{ + return ATON_STRSWITCH_DSTDECUN11_OFFSET; +} + + +/** + * Get the address of the DSTDECUN11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN11 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTDECUN11 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN11_ADDR(instance); +} + + +/** + * Read the content of the DSTDECUN11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN11 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTDECUN11 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTDECUN11_GET(instance); +} + + +/** + * Write the content of the DSTDECUN11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN11 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTDECUN11_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTDECUN11_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTDECUN11 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_EN0_P 0 + +/** Read the content of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN0_LSB, ATON_STRSWITCH_DSTDECUN11_EN0_W) + +/** Modify the content of the EN0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN0_LSB, ATON_STRSWITCH_DSTDECUN11_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTDECUN11 register. + * + * \return the description of the EN0 field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the EN0 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTDECUN11 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK0_LSB, ATON_STRSWITCH_DSTDECUN11_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK0_LSB, ATON_STRSWITCH_DSTDECUN11_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTDECUN11 register. + * + * \return the description of the LINK0 field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the LINK0 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTDECUN11 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR0_LSB, ATON_STRSWITCH_DSTDECUN11_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR0_LSB, ATON_STRSWITCH_DSTDECUN11_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTDECUN11 register. + * + * \return the description of the FNR0 field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the FNR0 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTDECUN11 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_EN1_P 0 + +/** Read the content of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN1_LSB, ATON_STRSWITCH_DSTDECUN11_EN1_W) + +/** Modify the content of the EN1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN1_LSB, ATON_STRSWITCH_DSTDECUN11_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTDECUN11 register. + * + * \return the description of the EN1 field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the EN1 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTDECUN11 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK1_LSB, ATON_STRSWITCH_DSTDECUN11_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK1_LSB, ATON_STRSWITCH_DSTDECUN11_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTDECUN11 register. + * + * \return the description of the LINK1 field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the LINK1 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTDECUN11 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTDECUN11 register. + * + * \return the description of the TICKTYPE field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the TICKTYPE field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTDECUN11 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTDECUN11 register is secured or not. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTDECUN11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTDECUN11_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR1_LSB, ATON_STRSWITCH_DSTDECUN11_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTDECUN11 register. */ +#define ATON_STRSWITCH_DSTDECUN11_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR1_LSB, ATON_STRSWITCH_DSTDECUN11_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTDECUN11 register. + * + * \return the description of the FNR1 field of DSTDECUN11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * + * \return the content of the FNR1 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTDECUN11_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTDECUN11 register. + * + * \param[in] reg is the value of the DSTDECUN11 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTDECUN11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTDECUN11_SET_FNR1(reg, data); +} + + +/* **************************************************** DSTACTIV0 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTACTIV0 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTACTIV0_OFFSET 0x70UL + +/** Reset value of the DSTACTIV0 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTACTIV0_DT \ + (ATON_STRSWITCH_DSTACTIV0_EN0_DT << ATON_STRSWITCH_DSTACTIV0_EN0_LSB) | \ + (ATON_STRSWITCH_DSTACTIV0_LINK0_DT << ATON_STRSWITCH_DSTACTIV0_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTACTIV0_FNR0_DT << ATON_STRSWITCH_DSTACTIV0_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTACTIV0_EN1_DT << ATON_STRSWITCH_DSTACTIV0_EN1_LSB) | \ + (ATON_STRSWITCH_DSTACTIV0_LINK1_DT << ATON_STRSWITCH_DSTACTIV0_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DT << ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTACTIV0_FNR1_DT << ATON_STRSWITCH_DSTACTIV0_FNR1_LSB) + + + +/** Description of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_DESC "Connection to input port of Activation Accelerator 0" + +/** Address of the DSTACTIV0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTACTIV0_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTACTIV0_OFFSET) + +/** Get the content of the DSTACTIV0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTACTIV0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV0_ADDR(UNIT))) + +/** Set the content of the DSTACTIV0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTACTIV0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTACTIV0 register. + * + * \return the description of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_DESC; +} + + +/** + * Get the offset of the DSTACTIV0 register. + * + * \return the offset of DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_GetOffset(void) +{ + return ATON_STRSWITCH_DSTACTIV0_OFFSET; +} + + +/** + * Get the address of the DSTACTIV0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTACTIV0 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTACTIV0_ADDR(instance); +} + + +/** + * Read the content of the DSTACTIV0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTACTIV0 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTACTIV0_GET(instance); +} + + +/** + * Write the content of the DSTACTIV0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTACTIV0_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTACTIV0_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTACTIV0 register ----------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_EN0_P 0 + +/** Read the content of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN0_LSB, ATON_STRSWITCH_DSTACTIV0_EN0_W) + +/** Modify the content of the EN0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN0_LSB, ATON_STRSWITCH_DSTACTIV0_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTACTIV0 register. + * + * \return the description of the EN0 field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the EN0 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTACTIV0 register ---------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK0_LSB, ATON_STRSWITCH_DSTACTIV0_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK0_LSB, ATON_STRSWITCH_DSTACTIV0_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTACTIV0 register. + * + * \return the description of the LINK0 field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the LINK0 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_LINK0(reg, data); +} + + +/* ---------------------------------------------------------- FNR0 field of the DSTACTIV0 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR0_LSB, ATON_STRSWITCH_DSTACTIV0_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR0_LSB, ATON_STRSWITCH_DSTACTIV0_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTACTIV0 register. + * + * \return the description of the FNR0 field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the FNR0 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTACTIV0 register ----------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_EN1_P 0 + +/** Read the content of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN1_LSB, ATON_STRSWITCH_DSTACTIV0_EN1_W) + +/** Modify the content of the EN1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN1_LSB, ATON_STRSWITCH_DSTACTIV0_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTACTIV0 register. + * + * \return the description of the EN1 field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the EN1 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTACTIV0 register ---------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK1_LSB, ATON_STRSWITCH_DSTACTIV0_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK1_LSB, ATON_STRSWITCH_DSTACTIV0_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTACTIV0 register. + * + * \return the description of the LINK1 field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the LINK1 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_LINK1(reg, data); +} + + +/* -------------------------------------------------------- TICKTYPE field of the DSTACTIV0 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTACTIV0 register. + * + * \return the description of the TICKTYPE field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the TICKTYPE field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_TICKTYPE(reg, data); +} + + +/* ---------------------------------------------------------- FNR1 field of the DSTACTIV0 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTACTIV0 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTACTIV0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV0_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR1_LSB, ATON_STRSWITCH_DSTACTIV0_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTACTIV0 register. */ +#define ATON_STRSWITCH_DSTACTIV0_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR1_LSB, ATON_STRSWITCH_DSTACTIV0_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTACTIV0 register. + * + * \return the description of the FNR1 field of DSTACTIV0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * + * \return the content of the FNR1 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV0_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTACTIV0 register. + * + * \param[in] reg is the value of the DSTACTIV0 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTACTIV0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV0_SET_FNR1(reg, data); +} + + +/* **************************************************** DSTACTIV1 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTACTIV1 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTACTIV1_OFFSET 0x74UL + +/** Reset value of the DSTACTIV1 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTACTIV1_DT \ + (ATON_STRSWITCH_DSTACTIV1_EN0_DT << ATON_STRSWITCH_DSTACTIV1_EN0_LSB) | \ + (ATON_STRSWITCH_DSTACTIV1_LINK0_DT << ATON_STRSWITCH_DSTACTIV1_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTACTIV1_FNR0_DT << ATON_STRSWITCH_DSTACTIV1_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTACTIV1_EN1_DT << ATON_STRSWITCH_DSTACTIV1_EN1_LSB) | \ + (ATON_STRSWITCH_DSTACTIV1_LINK1_DT << ATON_STRSWITCH_DSTACTIV1_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DT << ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTACTIV1_FNR1_DT << ATON_STRSWITCH_DSTACTIV1_FNR1_LSB) + + + +/** Description of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_DESC "Connection to input port of Activation Accelerator 1" + +/** Address of the DSTACTIV1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTACTIV1_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTACTIV1_OFFSET) + +/** Get the content of the DSTACTIV1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTACTIV1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV1_ADDR(UNIT))) + +/** Set the content of the DSTACTIV1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTACTIV1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTACTIV1 register. + * + * \return the description of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_DESC; +} + + +/** + * Get the offset of the DSTACTIV1 register. + * + * \return the offset of DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_GetOffset(void) +{ + return ATON_STRSWITCH_DSTACTIV1_OFFSET; +} + + +/** + * Get the address of the DSTACTIV1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTACTIV1 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTACTIV1_ADDR(instance); +} + + +/** + * Read the content of the DSTACTIV1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTACTIV1 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTACTIV1_GET(instance); +} + + +/** + * Write the content of the DSTACTIV1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTACTIV1_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTACTIV1_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTACTIV1 register ----------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_EN0_P 0 + +/** Read the content of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN0_LSB, ATON_STRSWITCH_DSTACTIV1_EN0_W) + +/** Modify the content of the EN0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN0_LSB, ATON_STRSWITCH_DSTACTIV1_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTACTIV1 register. + * + * \return the description of the EN0 field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the EN0 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTACTIV1 register ---------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK0_LSB, ATON_STRSWITCH_DSTACTIV1_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK0_LSB, ATON_STRSWITCH_DSTACTIV1_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTACTIV1 register. + * + * \return the description of the LINK0 field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the LINK0 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_LINK0(reg, data); +} + + +/* ---------------------------------------------------------- FNR0 field of the DSTACTIV1 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR0_LSB, ATON_STRSWITCH_DSTACTIV1_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR0_LSB, ATON_STRSWITCH_DSTACTIV1_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTACTIV1 register. + * + * \return the description of the FNR0 field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the FNR0 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTACTIV1 register ----------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_EN1_P 0 + +/** Read the content of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN1_LSB, ATON_STRSWITCH_DSTACTIV1_EN1_W) + +/** Modify the content of the EN1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN1_LSB, ATON_STRSWITCH_DSTACTIV1_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTACTIV1 register. + * + * \return the description of the EN1 field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the EN1 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTACTIV1 register ---------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK1_LSB, ATON_STRSWITCH_DSTACTIV1_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK1_LSB, ATON_STRSWITCH_DSTACTIV1_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTACTIV1 register. + * + * \return the description of the LINK1 field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the LINK1 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_LINK1(reg, data); +} + + +/* -------------------------------------------------------- TICKTYPE field of the DSTACTIV1 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTACTIV1 register. + * + * \return the description of the TICKTYPE field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the TICKTYPE field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_TICKTYPE(reg, data); +} + + +/* ---------------------------------------------------------- FNR1 field of the DSTACTIV1 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTACTIV1 register is secured or not. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTACTIV1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTACTIV1_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR1_LSB, ATON_STRSWITCH_DSTACTIV1_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTACTIV1 register. */ +#define ATON_STRSWITCH_DSTACTIV1_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR1_LSB, ATON_STRSWITCH_DSTACTIV1_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTACTIV1 register. + * + * \return the description of the FNR1 field of DSTACTIV1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * + * \return the content of the FNR1 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTACTIV1_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTACTIV1 register. + * + * \param[in] reg is the value of the DSTACTIV1 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTACTIV1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTACTIV1_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH00 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH00 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH00_OFFSET 0x78UL + +/** Reset value of the DSTARITH00 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH00_DT \ + (ATON_STRSWITCH_DSTARITH00_EN0_DT << ATON_STRSWITCH_DSTARITH00_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH00_LINK0_DT << ATON_STRSWITCH_DSTARITH00_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH00_FNR0_DT << ATON_STRSWITCH_DSTARITH00_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH00_EN1_DT << ATON_STRSWITCH_DSTARITH00_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH00_LINK1_DT << ATON_STRSWITCH_DSTARITH00_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH00_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH00_FNR1_DT << ATON_STRSWITCH_DSTARITH00_FNR1_LSB) + + + +/** Description of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_DESC "Connection to input port 0 of Arithmetic Accelerator 0" + +/** Address of the DSTARITH00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH00_OFFSET) + +/** Get the content of the DSTARITH00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH00_ADDR(UNIT))) + +/** Set the content of the DSTARITH00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH00_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH00 register. + * + * \return the description of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_DESC; +} + + +/** + * Get the offset of the DSTARITH00 register. + * + * \return the offset of DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH00_OFFSET; +} + + +/** + * Get the address of the DSTARITH00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH00 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH00_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH00 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH00_GET(instance); +} + + +/** + * Write the content of the DSTARITH00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH00 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH00_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH00_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH00 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN0_LSB, ATON_STRSWITCH_DSTARITH00_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN0_LSB, ATON_STRSWITCH_DSTARITH00_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH00 register. + * + * \return the description of the EN0 field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the EN0 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH00 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK0_LSB, ATON_STRSWITCH_DSTARITH00_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK0_LSB, ATON_STRSWITCH_DSTARITH00_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH00 register. + * + * \return the description of the LINK0 field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the LINK0 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH00 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR0_LSB, ATON_STRSWITCH_DSTARITH00_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR0_LSB, ATON_STRSWITCH_DSTARITH00_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH00 register. + * + * \return the description of the FNR0 field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the FNR0 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH00 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN1_LSB, ATON_STRSWITCH_DSTARITH00_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN1_LSB, ATON_STRSWITCH_DSTARITH00_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH00 register. + * + * \return the description of the EN1 field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the EN1 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH00 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK1_LSB, ATON_STRSWITCH_DSTARITH00_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK1_LSB, ATON_STRSWITCH_DSTARITH00_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH00 register. + * + * \return the description of the LINK1 field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the LINK1 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH00 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH00_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH00_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH00 register. + * + * \return the description of the TICKTYPE field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH00 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH00 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH00_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR1_LSB, ATON_STRSWITCH_DSTARITH00_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH00 register. */ +#define ATON_STRSWITCH_DSTARITH00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR1_LSB, ATON_STRSWITCH_DSTARITH00_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH00 register. + * + * \return the description of the FNR1 field of DSTARITH00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH00_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH00_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * + * \return the content of the FNR1 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH00_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH00 register. + * + * \param[in] reg is the value of the DSTARITH00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH00_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH01 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH01 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH01_OFFSET 0x7cUL + +/** Reset value of the DSTARITH01 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH01_DT \ + (ATON_STRSWITCH_DSTARITH01_EN0_DT << ATON_STRSWITCH_DSTARITH01_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH01_LINK0_DT << ATON_STRSWITCH_DSTARITH01_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH01_FNR0_DT << ATON_STRSWITCH_DSTARITH01_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH01_EN1_DT << ATON_STRSWITCH_DSTARITH01_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH01_LINK1_DT << ATON_STRSWITCH_DSTARITH01_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH01_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH01_FNR1_DT << ATON_STRSWITCH_DSTARITH01_FNR1_LSB) + + + +/** Description of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_DESC "Connection to input port 1 of Arithmetic Accelerator 0" + +/** Address of the DSTARITH01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH01_OFFSET) + +/** Get the content of the DSTARITH01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH01_ADDR(UNIT))) + +/** Set the content of the DSTARITH01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH01_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH01 register. + * + * \return the description of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_DESC; +} + + +/** + * Get the offset of the DSTARITH01 register. + * + * \return the offset of DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH01_OFFSET; +} + + +/** + * Get the address of the DSTARITH01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH01 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH01_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH01 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH01_GET(instance); +} + + +/** + * Write the content of the DSTARITH01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH01 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH01_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH01_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH01 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN0_LSB, ATON_STRSWITCH_DSTARITH01_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN0_LSB, ATON_STRSWITCH_DSTARITH01_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH01 register. + * + * \return the description of the EN0 field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the EN0 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH01 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK0_LSB, ATON_STRSWITCH_DSTARITH01_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK0_LSB, ATON_STRSWITCH_DSTARITH01_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH01 register. + * + * \return the description of the LINK0 field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the LINK0 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH01 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR0_LSB, ATON_STRSWITCH_DSTARITH01_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR0_LSB, ATON_STRSWITCH_DSTARITH01_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH01 register. + * + * \return the description of the FNR0 field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the FNR0 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH01 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN1_LSB, ATON_STRSWITCH_DSTARITH01_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN1_LSB, ATON_STRSWITCH_DSTARITH01_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH01 register. + * + * \return the description of the EN1 field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the EN1 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH01 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK1_LSB, ATON_STRSWITCH_DSTARITH01_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK1_LSB, ATON_STRSWITCH_DSTARITH01_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH01 register. + * + * \return the description of the LINK1 field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the LINK1 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH01 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH01_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH01_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH01 register. + * + * \return the description of the TICKTYPE field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH01 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH01 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH01_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR1_LSB, ATON_STRSWITCH_DSTARITH01_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH01 register. */ +#define ATON_STRSWITCH_DSTARITH01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR1_LSB, ATON_STRSWITCH_DSTARITH01_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH01 register. + * + * \return the description of the FNR1 field of DSTARITH01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH01_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH01_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * + * \return the content of the FNR1 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH01_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH01 register. + * + * \param[in] reg is the value of the DSTARITH01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH01_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH10 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH10 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH10_OFFSET 0x80UL + +/** Reset value of the DSTARITH10 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH10_DT \ + (ATON_STRSWITCH_DSTARITH10_EN0_DT << ATON_STRSWITCH_DSTARITH10_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH10_LINK0_DT << ATON_STRSWITCH_DSTARITH10_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH10_FNR0_DT << ATON_STRSWITCH_DSTARITH10_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH10_EN1_DT << ATON_STRSWITCH_DSTARITH10_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH10_LINK1_DT << ATON_STRSWITCH_DSTARITH10_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH10_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH10_FNR1_DT << ATON_STRSWITCH_DSTARITH10_FNR1_LSB) + + + +/** Description of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_DESC "Connection to input port 0 of Arithmetic Accelerator 1" + +/** Address of the DSTARITH10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH10_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH10_OFFSET) + +/** Get the content of the DSTARITH10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH10_ADDR(UNIT))) + +/** Set the content of the DSTARITH10 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH10_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH10 register. + * + * \return the description of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_DESC; +} + + +/** + * Get the offset of the DSTARITH10 register. + * + * \return the offset of DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH10_OFFSET; +} + + +/** + * Get the address of the DSTARITH10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH10 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH10 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH10_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH10 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH10 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH10_GET(instance); +} + + +/** + * Write the content of the DSTARITH10 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH10 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH10_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH10_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH10 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN0_LSB, ATON_STRSWITCH_DSTARITH10_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN0_LSB, ATON_STRSWITCH_DSTARITH10_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH10 register. + * + * \return the description of the EN0 field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the EN0 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH10 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK0_LSB, ATON_STRSWITCH_DSTARITH10_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK0_LSB, ATON_STRSWITCH_DSTARITH10_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH10 register. + * + * \return the description of the LINK0 field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the LINK0 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH10 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR0_LSB, ATON_STRSWITCH_DSTARITH10_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR0_LSB, ATON_STRSWITCH_DSTARITH10_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH10 register. + * + * \return the description of the FNR0 field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the FNR0 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH10 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN1_LSB, ATON_STRSWITCH_DSTARITH10_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN1_LSB, ATON_STRSWITCH_DSTARITH10_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH10 register. + * + * \return the description of the EN1 field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the EN1 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH10 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK1_LSB, ATON_STRSWITCH_DSTARITH10_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK1_LSB, ATON_STRSWITCH_DSTARITH10_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH10 register. + * + * \return the description of the LINK1 field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the LINK1 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH10 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH10_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH10_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH10 register. + * + * \return the description of the TICKTYPE field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH10 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH10 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH10 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH10_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR1_LSB, ATON_STRSWITCH_DSTARITH10_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH10 register. */ +#define ATON_STRSWITCH_DSTARITH10_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR1_LSB, ATON_STRSWITCH_DSTARITH10_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH10 register. + * + * \return the description of the FNR1 field of DSTARITH10 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH10_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH10_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * + * \return the content of the FNR1 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH10_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH10 register. + * + * \param[in] reg is the value of the DSTARITH10 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH10 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH10_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH11 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH11 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH11_OFFSET 0x84UL + +/** Reset value of the DSTARITH11 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH11_DT \ + (ATON_STRSWITCH_DSTARITH11_EN0_DT << ATON_STRSWITCH_DSTARITH11_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH11_LINK0_DT << ATON_STRSWITCH_DSTARITH11_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH11_FNR0_DT << ATON_STRSWITCH_DSTARITH11_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH11_EN1_DT << ATON_STRSWITCH_DSTARITH11_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH11_LINK1_DT << ATON_STRSWITCH_DSTARITH11_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH11_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH11_FNR1_DT << ATON_STRSWITCH_DSTARITH11_FNR1_LSB) + + + +/** Description of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_DESC "Connection to input port 1 of Arithmetic Accelerator 1" + +/** Address of the DSTARITH11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH11_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH11_OFFSET) + +/** Get the content of the DSTARITH11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH11_ADDR(UNIT))) + +/** Set the content of the DSTARITH11 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH11_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH11 register. + * + * \return the description of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_DESC; +} + + +/** + * Get the offset of the DSTARITH11 register. + * + * \return the offset of DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH11_OFFSET; +} + + +/** + * Get the address of the DSTARITH11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH11 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH11 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH11_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH11 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH11 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH11_GET(instance); +} + + +/** + * Write the content of the DSTARITH11 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH11 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH11_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH11_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH11 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN0_LSB, ATON_STRSWITCH_DSTARITH11_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN0_LSB, ATON_STRSWITCH_DSTARITH11_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH11 register. + * + * \return the description of the EN0 field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the EN0 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH11 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK0_LSB, ATON_STRSWITCH_DSTARITH11_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK0_LSB, ATON_STRSWITCH_DSTARITH11_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH11 register. + * + * \return the description of the LINK0 field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the LINK0 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH11 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR0_LSB, ATON_STRSWITCH_DSTARITH11_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR0_LSB, ATON_STRSWITCH_DSTARITH11_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH11 register. + * + * \return the description of the FNR0 field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the FNR0 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH11 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN1_LSB, ATON_STRSWITCH_DSTARITH11_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN1_LSB, ATON_STRSWITCH_DSTARITH11_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH11 register. + * + * \return the description of the EN1 field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the EN1 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH11 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK1_LSB, ATON_STRSWITCH_DSTARITH11_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK1_LSB, ATON_STRSWITCH_DSTARITH11_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH11 register. + * + * \return the description of the LINK1 field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the LINK1 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH11 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH11_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH11_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH11 register. + * + * \return the description of the TICKTYPE field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH11 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH11 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH11 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH11_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR1_LSB, ATON_STRSWITCH_DSTARITH11_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH11 register. */ +#define ATON_STRSWITCH_DSTARITH11_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR1_LSB, ATON_STRSWITCH_DSTARITH11_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH11 register. + * + * \return the description of the FNR1 field of DSTARITH11 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH11_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH11_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * + * \return the content of the FNR1 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH11_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH11 register. + * + * \param[in] reg is the value of the DSTARITH11 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH11 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH11_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH20 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH20 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH20_OFFSET 0x88UL + +/** Reset value of the DSTARITH20 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH20_DT \ + (ATON_STRSWITCH_DSTARITH20_EN0_DT << ATON_STRSWITCH_DSTARITH20_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH20_LINK0_DT << ATON_STRSWITCH_DSTARITH20_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH20_FNR0_DT << ATON_STRSWITCH_DSTARITH20_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH20_EN1_DT << ATON_STRSWITCH_DSTARITH20_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH20_LINK1_DT << ATON_STRSWITCH_DSTARITH20_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH20_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH20_FNR1_DT << ATON_STRSWITCH_DSTARITH20_FNR1_LSB) + + + +/** Description of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_DESC "Connection to input port 0 of Arithmetic Accelerator 2" + +/** Address of the DSTARITH20 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH20_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH20_OFFSET) + +/** Get the content of the DSTARITH20 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH20_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH20_ADDR(UNIT))) + +/** Set the content of the DSTARITH20 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH20_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH20_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH20 register. + * + * \return the description of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_DESC; +} + + +/** + * Get the offset of the DSTARITH20 register. + * + * \return the offset of DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH20_OFFSET; +} + + +/** + * Get the address of the DSTARITH20 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH20 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH20 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH20_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH20 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH20 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH20 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH20_GET(instance); +} + + +/** + * Write the content of the DSTARITH20 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH20 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH20_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH20_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH20 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN0_LSB, ATON_STRSWITCH_DSTARITH20_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN0_LSB, ATON_STRSWITCH_DSTARITH20_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH20 register. + * + * \return the description of the EN0 field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the EN0 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH20 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK0_LSB, ATON_STRSWITCH_DSTARITH20_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK0_LSB, ATON_STRSWITCH_DSTARITH20_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH20 register. + * + * \return the description of the LINK0 field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the LINK0 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH20 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR0_LSB, ATON_STRSWITCH_DSTARITH20_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR0_LSB, ATON_STRSWITCH_DSTARITH20_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH20 register. + * + * \return the description of the FNR0 field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the FNR0 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH20 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN1_LSB, ATON_STRSWITCH_DSTARITH20_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN1_LSB, ATON_STRSWITCH_DSTARITH20_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH20 register. + * + * \return the description of the EN1 field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the EN1 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH20 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK1_LSB, ATON_STRSWITCH_DSTARITH20_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK1_LSB, ATON_STRSWITCH_DSTARITH20_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH20 register. + * + * \return the description of the LINK1 field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the LINK1 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH20 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH20_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH20_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH20 register. + * + * \return the description of the TICKTYPE field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH20 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH20 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH20 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH20_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR1_LSB, ATON_STRSWITCH_DSTARITH20_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH20 register. */ +#define ATON_STRSWITCH_DSTARITH20_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR1_LSB, ATON_STRSWITCH_DSTARITH20_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH20 register. + * + * \return the description of the FNR1 field of DSTARITH20 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH20_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH20_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * + * \return the content of the FNR1 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH20_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH20 register. + * + * \param[in] reg is the value of the DSTARITH20 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH20 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH20_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH21 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH21 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH21_OFFSET 0x8cUL + +/** Reset value of the DSTARITH21 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH21_DT \ + (ATON_STRSWITCH_DSTARITH21_EN0_DT << ATON_STRSWITCH_DSTARITH21_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH21_LINK0_DT << ATON_STRSWITCH_DSTARITH21_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH21_FNR0_DT << ATON_STRSWITCH_DSTARITH21_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH21_EN1_DT << ATON_STRSWITCH_DSTARITH21_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH21_LINK1_DT << ATON_STRSWITCH_DSTARITH21_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH21_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH21_FNR1_DT << ATON_STRSWITCH_DSTARITH21_FNR1_LSB) + + + +/** Description of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_DESC "Connection to input port 1 of Arithmetic Accelerator 2" + +/** Address of the DSTARITH21 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH21_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH21_OFFSET) + +/** Get the content of the DSTARITH21 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH21_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH21_ADDR(UNIT))) + +/** Set the content of the DSTARITH21 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH21_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH21_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH21 register. + * + * \return the description of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_DESC; +} + + +/** + * Get the offset of the DSTARITH21 register. + * + * \return the offset of DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH21_OFFSET; +} + + +/** + * Get the address of the DSTARITH21 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH21 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH21 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH21_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH21 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH21 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH21 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH21_GET(instance); +} + + +/** + * Write the content of the DSTARITH21 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH21 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH21_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH21_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH21 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN0_LSB, ATON_STRSWITCH_DSTARITH21_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN0_LSB, ATON_STRSWITCH_DSTARITH21_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH21 register. + * + * \return the description of the EN0 field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the EN0 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH21 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK0_LSB, ATON_STRSWITCH_DSTARITH21_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK0_LSB, ATON_STRSWITCH_DSTARITH21_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH21 register. + * + * \return the description of the LINK0 field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the LINK0 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH21 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR0_LSB, ATON_STRSWITCH_DSTARITH21_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR0_LSB, ATON_STRSWITCH_DSTARITH21_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH21 register. + * + * \return the description of the FNR0 field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the FNR0 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH21 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN1_LSB, ATON_STRSWITCH_DSTARITH21_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN1_LSB, ATON_STRSWITCH_DSTARITH21_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH21 register. + * + * \return the description of the EN1 field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the EN1 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH21 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK1_LSB, ATON_STRSWITCH_DSTARITH21_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK1_LSB, ATON_STRSWITCH_DSTARITH21_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH21 register. + * + * \return the description of the LINK1 field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the LINK1 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH21 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH21_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH21_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH21 register. + * + * \return the description of the TICKTYPE field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH21 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH21 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH21 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH21_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR1_LSB, ATON_STRSWITCH_DSTARITH21_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH21 register. */ +#define ATON_STRSWITCH_DSTARITH21_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR1_LSB, ATON_STRSWITCH_DSTARITH21_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH21 register. + * + * \return the description of the FNR1 field of DSTARITH21 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH21_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH21_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * + * \return the content of the FNR1 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH21_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH21 register. + * + * \param[in] reg is the value of the DSTARITH21 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH21 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH21_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH30 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH30 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH30_OFFSET 0x90UL + +/** Reset value of the DSTARITH30 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH30_DT \ + (ATON_STRSWITCH_DSTARITH30_EN0_DT << ATON_STRSWITCH_DSTARITH30_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH30_LINK0_DT << ATON_STRSWITCH_DSTARITH30_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH30_FNR0_DT << ATON_STRSWITCH_DSTARITH30_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH30_EN1_DT << ATON_STRSWITCH_DSTARITH30_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH30_LINK1_DT << ATON_STRSWITCH_DSTARITH30_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH30_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH30_FNR1_DT << ATON_STRSWITCH_DSTARITH30_FNR1_LSB) + + + +/** Description of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_DESC "Connection to input port 0 of Arithmetic Accelerator 3" + +/** Address of the DSTARITH30 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH30_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH30_OFFSET) + +/** Get the content of the DSTARITH30 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH30_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH30_ADDR(UNIT))) + +/** Set the content of the DSTARITH30 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH30_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH30_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH30 register. + * + * \return the description of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_DESC; +} + + +/** + * Get the offset of the DSTARITH30 register. + * + * \return the offset of DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH30_OFFSET; +} + + +/** + * Get the address of the DSTARITH30 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH30 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH30 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH30_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH30 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH30 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH30 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH30_GET(instance); +} + + +/** + * Write the content of the DSTARITH30 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH30 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH30_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH30_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH30 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN0_LSB, ATON_STRSWITCH_DSTARITH30_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN0_LSB, ATON_STRSWITCH_DSTARITH30_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH30 register. + * + * \return the description of the EN0 field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the EN0 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH30 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK0_LSB, ATON_STRSWITCH_DSTARITH30_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK0_LSB, ATON_STRSWITCH_DSTARITH30_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH30 register. + * + * \return the description of the LINK0 field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the LINK0 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH30 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR0_LSB, ATON_STRSWITCH_DSTARITH30_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR0_LSB, ATON_STRSWITCH_DSTARITH30_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH30 register. + * + * \return the description of the FNR0 field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the FNR0 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH30 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN1_LSB, ATON_STRSWITCH_DSTARITH30_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN1_LSB, ATON_STRSWITCH_DSTARITH30_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH30 register. + * + * \return the description of the EN1 field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the EN1 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH30 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK1_LSB, ATON_STRSWITCH_DSTARITH30_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK1_LSB, ATON_STRSWITCH_DSTARITH30_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH30 register. + * + * \return the description of the LINK1 field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the LINK1 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH30 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH30_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH30_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH30 register. + * + * \return the description of the TICKTYPE field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH30 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH30 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH30 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH30_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR1_LSB, ATON_STRSWITCH_DSTARITH30_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH30 register. */ +#define ATON_STRSWITCH_DSTARITH30_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR1_LSB, ATON_STRSWITCH_DSTARITH30_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH30 register. + * + * \return the description of the FNR1 field of DSTARITH30 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH30_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH30_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * + * \return the content of the FNR1 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH30_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH30 register. + * + * \param[in] reg is the value of the DSTARITH30 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH30 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH30_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTARITH31 register of one of the STRSWITCH Units **************************************************** */ + +/** Offset of the DSTARITH31 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH31_OFFSET 0x94UL + +/** Reset value of the DSTARITH31 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTARITH31_DT \ + (ATON_STRSWITCH_DSTARITH31_EN0_DT << ATON_STRSWITCH_DSTARITH31_EN0_LSB) | \ + (ATON_STRSWITCH_DSTARITH31_LINK0_DT << ATON_STRSWITCH_DSTARITH31_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTARITH31_FNR0_DT << ATON_STRSWITCH_DSTARITH31_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTARITH31_EN1_DT << ATON_STRSWITCH_DSTARITH31_EN1_LSB) | \ + (ATON_STRSWITCH_DSTARITH31_LINK1_DT << ATON_STRSWITCH_DSTARITH31_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTARITH31_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTARITH31_FNR1_DT << ATON_STRSWITCH_DSTARITH31_FNR1_LSB) + + + +/** Description of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_DESC "Connection to input port 1 of Arithmetic Accelerator 3" + +/** Address of the DSTARITH31 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH31_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH31_OFFSET) + +/** Get the content of the DSTARITH31 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH31_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH31_ADDR(UNIT))) + +/** Set the content of the DSTARITH31 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTARITH31_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH31_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTARITH31 register. + * + * \return the description of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_DESC; +} + + +/** + * Get the offset of the DSTARITH31 register. + * + * \return the offset of DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_GetOffset(void) +{ + return ATON_STRSWITCH_DSTARITH31_OFFSET; +} + + +/** + * Get the address of the DSTARITH31 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH31 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTARITH31 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH31_ADDR(instance); +} + + +/** + * Read the content of the DSTARITH31 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH31 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTARITH31 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTARITH31_GET(instance); +} + + +/** + * Write the content of the DSTARITH31 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH31 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTARITH31_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTARITH31_SET(instance, data); +} + + +/* ---------------------------------------------------------- EN0 field of the DSTARITH31 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_EN0_P 0 + +/** Read the content of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN0_LSB, ATON_STRSWITCH_DSTARITH31_EN0_W) + +/** Modify the content of the EN0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN0_LSB, ATON_STRSWITCH_DSTARITH31_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTARITH31 register. + * + * \return the description of the EN0 field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the EN0 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_EN0(reg, data); +} + + +/* --------------------------------------------------------- LINK0 field of the DSTARITH31 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK0_LSB, ATON_STRSWITCH_DSTARITH31_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK0_LSB, ATON_STRSWITCH_DSTARITH31_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTARITH31 register. + * + * \return the description of the LINK0 field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the LINK0 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTARITH31 register ---------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR0_LSB, ATON_STRSWITCH_DSTARITH31_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR0_LSB, ATON_STRSWITCH_DSTARITH31_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTARITH31 register. + * + * \return the description of the FNR0 field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the FNR0 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_FNR0(reg, data); +} + + +/* ---------------------------------------------------------- EN1 field of the DSTARITH31 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_EN1_P 0 + +/** Read the content of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN1_LSB, ATON_STRSWITCH_DSTARITH31_EN1_W) + +/** Modify the content of the EN1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN1_LSB, ATON_STRSWITCH_DSTARITH31_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTARITH31 register. + * + * \return the description of the EN1 field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the EN1 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_EN1(reg, data); +} + + +/* --------------------------------------------------------- LINK1 field of the DSTARITH31 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK1_LSB, ATON_STRSWITCH_DSTARITH31_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK1_LSB, ATON_STRSWITCH_DSTARITH31_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTARITH31 register. + * + * \return the description of the LINK1 field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the LINK1 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTARITH31 register -------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH31_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH31_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTARITH31 register. + * + * \return the description of the TICKTYPE field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the TICKTYPE field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTARITH31 register ---------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTARITH31 register is secured or not. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTARITH31 register is privileged or not. */ +#define ATON_STRSWITCH_DSTARITH31_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR1_LSB, ATON_STRSWITCH_DSTARITH31_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTARITH31 register. */ +#define ATON_STRSWITCH_DSTARITH31_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR1_LSB, ATON_STRSWITCH_DSTARITH31_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTARITH31 register. + * + * \return the description of the FNR1 field of DSTARITH31 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTARITH31_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTARITH31_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * + * \return the content of the FNR1 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTARITH31_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTARITH31 register. + * + * \param[in] reg is the value of the DSTARITH31 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTARITH31 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTARITH31_SET_FNR1(reg, data); +} + + +/* **************************************************** DSTPOOL0 register of one of the STRSWITCH Units ***************************************************** */ + +/** Offset of the DSTPOOL0 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTPOOL0_OFFSET 0x98UL + +/** Reset value of the DSTPOOL0 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTPOOL0_DT \ + (ATON_STRSWITCH_DSTPOOL0_EN0_DT << ATON_STRSWITCH_DSTPOOL0_EN0_LSB) | \ + (ATON_STRSWITCH_DSTPOOL0_LINK0_DT << ATON_STRSWITCH_DSTPOOL0_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTPOOL0_FNR0_DT << ATON_STRSWITCH_DSTPOOL0_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTPOOL0_EN1_DT << ATON_STRSWITCH_DSTPOOL0_EN1_LSB) | \ + (ATON_STRSWITCH_DSTPOOL0_LINK1_DT << ATON_STRSWITCH_DSTPOOL0_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DT << ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTPOOL0_FNR1_DT << ATON_STRSWITCH_DSTPOOL0_FNR1_LSB) + + + +/** Description of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_DESC "Connection to input port of Pooling Accelerator 0" + +/** Address of the DSTPOOL0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTPOOL0_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTPOOL0_OFFSET) + +/** Get the content of the DSTPOOL0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTPOOL0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL0_ADDR(UNIT))) + +/** Set the content of the DSTPOOL0 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTPOOL0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTPOOL0 register. + * + * \return the description of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_DESC; +} + + +/** + * Get the offset of the DSTPOOL0 register. + * + * \return the offset of DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_GetOffset(void) +{ + return ATON_STRSWITCH_DSTPOOL0_OFFSET; +} + + +/** + * Get the address of the DSTPOOL0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTPOOL0 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTPOOL0_ADDR(instance); +} + + +/** + * Read the content of the DSTPOOL0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTPOOL0 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTPOOL0_GET(instance); +} + + +/** + * Write the content of the DSTPOOL0 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTPOOL0_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTPOOL0_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN0 field of the DSTPOOL0 register ----------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_EN0_P 0 + +/** Read the content of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN0_LSB, ATON_STRSWITCH_DSTPOOL0_EN0_W) + +/** Modify the content of the EN0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN0_LSB, ATON_STRSWITCH_DSTPOOL0_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTPOOL0 register. + * + * \return the description of the EN0 field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the EN0 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_EN0(reg, data); +} + + +/* ---------------------------------------------------------- LINK0 field of the DSTPOOL0 register ---------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK0_LSB, ATON_STRSWITCH_DSTPOOL0_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK0_LSB, ATON_STRSWITCH_DSTPOOL0_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTPOOL0 register. + * + * \return the description of the LINK0 field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the LINK0 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_LINK0(reg, data); +} + + +/* ---------------------------------------------------------- FNR0 field of the DSTPOOL0 register ----------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR0_LSB, ATON_STRSWITCH_DSTPOOL0_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR0_LSB, ATON_STRSWITCH_DSTPOOL0_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTPOOL0 register. + * + * \return the description of the FNR0 field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the FNR0 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_FNR0(reg, data); +} + + +/* ----------------------------------------------------------- EN1 field of the DSTPOOL0 register ----------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_EN1_P 0 + +/** Read the content of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN1_LSB, ATON_STRSWITCH_DSTPOOL0_EN1_W) + +/** Modify the content of the EN1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN1_LSB, ATON_STRSWITCH_DSTPOOL0_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTPOOL0 register. + * + * \return the description of the EN1 field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the EN1 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_EN1(reg, data); +} + + +/* ---------------------------------------------------------- LINK1 field of the DSTPOOL0 register ---------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK1_LSB, ATON_STRSWITCH_DSTPOOL0_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK1_LSB, ATON_STRSWITCH_DSTPOOL0_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTPOOL0 register. + * + * \return the description of the LINK1 field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the LINK1 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_LINK1(reg, data); +} + + +/* -------------------------------------------------------- TICKTYPE field of the DSTPOOL0 register --------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTPOOL0 register. + * + * \return the description of the TICKTYPE field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the TICKTYPE field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_TICKTYPE(reg, data); +} + + +/* ---------------------------------------------------------- FNR1 field of the DSTPOOL0 register ----------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTPOOL0 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTPOOL0 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL0_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR1_LSB, ATON_STRSWITCH_DSTPOOL0_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTPOOL0 register. */ +#define ATON_STRSWITCH_DSTPOOL0_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR1_LSB, ATON_STRSWITCH_DSTPOOL0_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTPOOL0 register. + * + * \return the description of the FNR1 field of DSTPOOL0 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * + * \return the content of the FNR1 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL0_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTPOOL0 register. + * + * \param[in] reg is the value of the DSTPOOL0 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTPOOL0 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL0_SET_FNR1(reg, data); +} + + +/* **************************************************** DSTPOOL1 register of one of the STRSWITCH Units ***************************************************** */ + +/** Offset of the DSTPOOL1 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTPOOL1_OFFSET 0x9cUL + +/** Reset value of the DSTPOOL1 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTPOOL1_DT \ + (ATON_STRSWITCH_DSTPOOL1_EN0_DT << ATON_STRSWITCH_DSTPOOL1_EN0_LSB) | \ + (ATON_STRSWITCH_DSTPOOL1_LINK0_DT << ATON_STRSWITCH_DSTPOOL1_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTPOOL1_FNR0_DT << ATON_STRSWITCH_DSTPOOL1_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTPOOL1_EN1_DT << ATON_STRSWITCH_DSTPOOL1_EN1_LSB) | \ + (ATON_STRSWITCH_DSTPOOL1_LINK1_DT << ATON_STRSWITCH_DSTPOOL1_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DT << ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTPOOL1_FNR1_DT << ATON_STRSWITCH_DSTPOOL1_FNR1_LSB) + + + +/** Description of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_DESC "Connection to input port of Pooling Accelerator 1" + +/** Address of the DSTPOOL1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTPOOL1_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTPOOL1_OFFSET) + +/** Get the content of the DSTPOOL1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTPOOL1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL1_ADDR(UNIT))) + +/** Set the content of the DSTPOOL1 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTPOOL1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTPOOL1 register. + * + * \return the description of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_DESC; +} + + +/** + * Get the offset of the DSTPOOL1 register. + * + * \return the offset of DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_GetOffset(void) +{ + return ATON_STRSWITCH_DSTPOOL1_OFFSET; +} + + +/** + * Get the address of the DSTPOOL1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTPOOL1 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTPOOL1_ADDR(instance); +} + + +/** + * Read the content of the DSTPOOL1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTPOOL1 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTPOOL1_GET(instance); +} + + +/** + * Write the content of the DSTPOOL1 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTPOOL1_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTPOOL1_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN0 field of the DSTPOOL1 register ----------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_EN0_P 0 + +/** Read the content of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN0_LSB, ATON_STRSWITCH_DSTPOOL1_EN0_W) + +/** Modify the content of the EN0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN0_LSB, ATON_STRSWITCH_DSTPOOL1_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTPOOL1 register. + * + * \return the description of the EN0 field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the EN0 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_EN0(reg, data); +} + + +/* ---------------------------------------------------------- LINK0 field of the DSTPOOL1 register ---------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK0_LSB, ATON_STRSWITCH_DSTPOOL1_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK0_LSB, ATON_STRSWITCH_DSTPOOL1_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTPOOL1 register. + * + * \return the description of the LINK0 field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the LINK0 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_LINK0(reg, data); +} + + +/* ---------------------------------------------------------- FNR0 field of the DSTPOOL1 register ----------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR0_LSB, ATON_STRSWITCH_DSTPOOL1_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR0_LSB, ATON_STRSWITCH_DSTPOOL1_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTPOOL1 register. + * + * \return the description of the FNR0 field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the FNR0 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_FNR0(reg, data); +} + + +/* ----------------------------------------------------------- EN1 field of the DSTPOOL1 register ----------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_EN1_P 0 + +/** Read the content of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN1_LSB, ATON_STRSWITCH_DSTPOOL1_EN1_W) + +/** Modify the content of the EN1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN1_LSB, ATON_STRSWITCH_DSTPOOL1_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTPOOL1 register. + * + * \return the description of the EN1 field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the EN1 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_EN1(reg, data); +} + + +/* ---------------------------------------------------------- LINK1 field of the DSTPOOL1 register ---------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK1_LSB, ATON_STRSWITCH_DSTPOOL1_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK1_LSB, ATON_STRSWITCH_DSTPOOL1_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTPOOL1 register. + * + * \return the description of the LINK1 field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the LINK1 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_LINK1(reg, data); +} + + +/* -------------------------------------------------------- TICKTYPE field of the DSTPOOL1 register --------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTPOOL1 register. + * + * \return the description of the TICKTYPE field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the TICKTYPE field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_TICKTYPE(reg, data); +} + + +/* ---------------------------------------------------------- FNR1 field of the DSTPOOL1 register ----------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTPOOL1 register is secured or not. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTPOOL1 register is privileged or not. */ +#define ATON_STRSWITCH_DSTPOOL1_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR1_LSB, ATON_STRSWITCH_DSTPOOL1_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTPOOL1 register. */ +#define ATON_STRSWITCH_DSTPOOL1_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR1_LSB, ATON_STRSWITCH_DSTPOOL1_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTPOOL1 register. + * + * \return the description of the FNR1 field of DSTPOOL1 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * + * \return the content of the FNR1 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTPOOL1_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTPOOL1 register. + * + * \param[in] reg is the value of the DSTPOOL1 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTPOOL1 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTPOOL1_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTRECBUF00 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTRECBUF00 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTRECBUF00_OFFSET 0xa0UL + +/** Reset value of the DSTRECBUF00 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTRECBUF00_DT \ + (ATON_STRSWITCH_DSTRECBUF00_EN0_DT << ATON_STRSWITCH_DSTRECBUF00_EN0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF00_LINK0_DT << ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF00_FNR0_DT << ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF00_EN1_DT << ATON_STRSWITCH_DSTRECBUF00_EN1_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF00_LINK1_DT << ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DT << ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF00_FNR1_DT << ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB) + + + +/** Description of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_DESC "Connection to input port 0 of Reconfigurable Buffer 0" + +/** Address of the DSTRECBUF00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTRECBUF00_OFFSET) + +/** Get the content of the DSTRECBUF00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF00_ADDR(UNIT))) + +/** Set the content of the DSTRECBUF00 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF00_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTRECBUF00 register. + * + * \return the description of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_DESC; +} + + +/** + * Get the offset of the DSTRECBUF00 register. + * + * \return the offset of DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_GetOffset(void) +{ + return ATON_STRSWITCH_DSTRECBUF00_OFFSET; +} + + +/** + * Get the address of the DSTRECBUF00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF00 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTRECBUF00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTRECBUF00_ADDR(instance); +} + + +/** + * Read the content of the DSTRECBUF00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF00 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTRECBUF00 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET(instance); +} + + +/** + * Write the content of the DSTRECBUF00 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF00 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTRECBUF00_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTRECBUF00_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTRECBUF00 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN0_P 0 + +/** Read the content of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN0_LSB, ATON_STRSWITCH_DSTRECBUF00_EN0_W) + +/** Modify the content of the EN0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN0_LSB, ATON_STRSWITCH_DSTRECBUF00_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTRECBUF00 register. + * + * \return the description of the EN0 field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the EN0 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTRECBUF00 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTRECBUF00 register. + * + * \return the description of the LINK0 field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the LINK0 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTRECBUF00 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTRECBUF00 register. + * + * \return the description of the FNR0 field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the FNR0 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTRECBUF00 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_EN1_P 0 + +/** Read the content of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN1_LSB, ATON_STRSWITCH_DSTRECBUF00_EN1_W) + +/** Modify the content of the EN1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN1_LSB, ATON_STRSWITCH_DSTRECBUF00_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTRECBUF00 register. + * + * \return the description of the EN1 field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the EN1 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTRECBUF00 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTRECBUF00 register. + * + * \return the description of the LINK1 field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the LINK1 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTRECBUF00 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTRECBUF00 register. + * + * \return the description of the TICKTYPE field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the TICKTYPE field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTRECBUF00 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTRECBUF00 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTRECBUF00 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF00_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTRECBUF00 register. */ +#define ATON_STRSWITCH_DSTRECBUF00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTRECBUF00 register. + * + * \return the description of the FNR1 field of DSTRECBUF00 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * + * \return the content of the FNR1 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF00_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTRECBUF00 register. + * + * \param[in] reg is the value of the DSTRECBUF00 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTRECBUF00 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF00_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTRECBUF01 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTRECBUF01 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTRECBUF01_OFFSET 0xa4UL + +/** Reset value of the DSTRECBUF01 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTRECBUF01_DT \ + (ATON_STRSWITCH_DSTRECBUF01_EN0_DT << ATON_STRSWITCH_DSTRECBUF01_EN0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF01_LINK0_DT << ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF01_FNR0_DT << ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF01_EN1_DT << ATON_STRSWITCH_DSTRECBUF01_EN1_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF01_LINK1_DT << ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DT << ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF01_FNR1_DT << ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB) + + + +/** Description of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_DESC "Connection to input port 1 of Reconfigurable Buffer 0" + +/** Address of the DSTRECBUF01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTRECBUF01_OFFSET) + +/** Get the content of the DSTRECBUF01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF01_ADDR(UNIT))) + +/** Set the content of the DSTRECBUF01 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF01_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTRECBUF01 register. + * + * \return the description of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_DESC; +} + + +/** + * Get the offset of the DSTRECBUF01 register. + * + * \return the offset of DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_GetOffset(void) +{ + return ATON_STRSWITCH_DSTRECBUF01_OFFSET; +} + + +/** + * Get the address of the DSTRECBUF01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF01 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTRECBUF01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTRECBUF01_ADDR(instance); +} + + +/** + * Read the content of the DSTRECBUF01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF01 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTRECBUF01 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET(instance); +} + + +/** + * Write the content of the DSTRECBUF01 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF01 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTRECBUF01_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTRECBUF01_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTRECBUF01 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN0_P 0 + +/** Read the content of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN0_LSB, ATON_STRSWITCH_DSTRECBUF01_EN0_W) + +/** Modify the content of the EN0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN0_LSB, ATON_STRSWITCH_DSTRECBUF01_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTRECBUF01 register. + * + * \return the description of the EN0 field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the EN0 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTRECBUF01 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTRECBUF01 register. + * + * \return the description of the LINK0 field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the LINK0 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTRECBUF01 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTRECBUF01 register. + * + * \return the description of the FNR0 field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the FNR0 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTRECBUF01 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_EN1_P 0 + +/** Read the content of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN1_LSB, ATON_STRSWITCH_DSTRECBUF01_EN1_W) + +/** Modify the content of the EN1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN1_LSB, ATON_STRSWITCH_DSTRECBUF01_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTRECBUF01 register. + * + * \return the description of the EN1 field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the EN1 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTRECBUF01 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTRECBUF01 register. + * + * \return the description of the LINK1 field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the LINK1 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTRECBUF01 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTRECBUF01 register. + * + * \return the description of the TICKTYPE field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the TICKTYPE field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTRECBUF01 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTRECBUF01 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTRECBUF01 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF01_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTRECBUF01 register. */ +#define ATON_STRSWITCH_DSTRECBUF01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTRECBUF01 register. + * + * \return the description of the FNR1 field of DSTRECBUF01 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * + * \return the content of the FNR1 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF01_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTRECBUF01 register. + * + * \param[in] reg is the value of the DSTRECBUF01 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTRECBUF01 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF01_SET_FNR1(reg, data); +} + + +/* *************************************************** DSTRECBUF02 register of one of the STRSWITCH Units *************************************************** */ + +/** Offset of the DSTRECBUF02 register from the base address of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTRECBUF02_OFFSET 0xa8UL + +/** Reset value of the DSTRECBUF02 register of the STRSWITCH Unit. */ +#define ATON_STRSWITCH_DSTRECBUF02_DT \ + (ATON_STRSWITCH_DSTRECBUF02_EN0_DT << ATON_STRSWITCH_DSTRECBUF02_EN0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF02_LINK0_DT << ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF02_FNR0_DT << ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF02_EN1_DT << ATON_STRSWITCH_DSTRECBUF02_EN1_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF02_LINK1_DT << ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DT << ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB) | \ + (ATON_STRSWITCH_DSTRECBUF02_FNR1_DT << ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB) + + + +/** Description of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_DESC "Connection to input port 2 of Reconfigurable Buffer 0" + +/** Address of the DSTRECBUF02 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF02_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTRECBUF02_OFFSET) + +/** Get the content of the DSTRECBUF02 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF02_ADDR(UNIT))) + +/** Set the content of the DSTRECBUF02 register of one of the STRSWITCH Units. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF02_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DSTRECBUF02 register. + * + * \return the description of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_GetDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_DESC; +} + + +/** + * Get the offset of the DSTRECBUF02 register. + * + * \return the offset of DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_GetOffset(void) +{ + return ATON_STRSWITCH_DSTRECBUF02_OFFSET; +} + + +/** + * Get the address of the DSTRECBUF02 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF02 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of DSTRECBUF02 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_GetAddr(uint32_t instance) +{ + return ATON_STRSWITCH_DSTRECBUF02_ADDR(instance); +} + + +/** + * Read the content of the DSTRECBUF02 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF02 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of DSTRECBUF02 register belonging to Unit having index \e instance among the STRSWITCH Units + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get(uint32_t instance) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET(instance); +} + + +/** + * Write the content of the DSTRECBUF02 register. + * + * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF02 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_STRSWITCH_DSTRECBUF02_Set(uint32_t instance, uint32_t data) +{ + ATON_STRSWITCH_DSTRECBUF02_SET(instance, data); +} + + +/* --------------------------------------------------------- EN0 field of the DSTRECBUF02 register ---------------------------------------------------------- */ + +/** Description of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_DESC "Enable context 0" + +/** Offset of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_LSB 0UL + +/** Size in bits of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_W (1UL) + +/** Mask for retrieving the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_DT 0x0UL + +/** Access rights of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_AC "RW" + +/** Check whether access to the EN0 field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_S 0 + +/** Check whether access to the EN0 field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN0_P 0 + +/** Read the content of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN0_LSB, ATON_STRSWITCH_DSTRECBUF02_EN0_W) + +/** Modify the content of the EN0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN0_LSB, ATON_STRSWITCH_DSTRECBUF02_EN0_W, DATA) + + +/** + * Get the description of the EN0 field of DSTRECBUF02 register. + * + * \return the description of the EN0 field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_EN0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_EN0_DESC; +} + + +/** + * Read the content of the EN0 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the EN0 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_EN0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_EN0(reg); +} + + +/** + * Write the content of the EN0 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN0 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_EN0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_EN0(reg, data); +} + + +/* -------------------------------------------------------- LINK0 field of the DSTRECBUF02 register --------------------------------------------------------- */ + +/** Description of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_DESC "Source port of context 0" + +/** Offset of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB 1UL + +/** Size in bits of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_W (5UL) + +/** Mask for retrieving the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) + +/** Reset value of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_DT 0x0UL + +/** Access rights of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_AC "RW" + +/** Check whether access to the LINK0 field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_S 0 + +/** Check whether access to the LINK0 field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK0_P 0 + +/** Read the content of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK0_W) + +/** Modify the content of the LINK0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK0_W, DATA) + + +/** + * Get the description of the LINK0 field of DSTRECBUF02 register. + * + * \return the description of the LINK0 field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_LINK0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_LINK0_DESC; +} + + +/** + * Read the content of the LINK0 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the LINK0 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_LINK0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_LINK0(reg); +} + + +/** + * Write the content of the LINK0 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK0 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_LINK0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_LINK0(reg, data); +} + + +/* --------------------------------------------------------- FNR0 field of the DSTRECBUF02 register --------------------------------------------------------- */ + +/** Description of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_DESC "Number of ticks for context 0" + +/** Offset of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB 8UL + +/** Size in bits of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_W (8UL) + +/** Mask for retrieving the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_DT 0x0UL + +/** Access rights of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_AC "RW" + +/** Check whether access to the FNR0 field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_S 0 + +/** Check whether access to the FNR0 field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR0_P 0 + +/** Read the content of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR0_W) + +/** Modify the content of the FNR0 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR0_W, DATA) + + +/** + * Get the description of the FNR0 field of DSTRECBUF02 register. + * + * \return the description of the FNR0 field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_FNR0_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_FNR0_DESC; +} + + +/** + * Read the content of the FNR0 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the FNR0 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_FNR0(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_FNR0(reg); +} + + +/** + * Write the content of the FNR0 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR0 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_FNR0(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_FNR0(reg, data); +} + + +/* --------------------------------------------------------- EN1 field of the DSTRECBUF02 register ---------------------------------------------------------- */ + +/** Description of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_DESC "Enable context 1" + +/** Offset of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_LSB 16UL + +/** Size in bits of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_W (1UL) + +/** Mask for retrieving the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_DT 0x0UL + +/** Access rights of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_AC "RW" + +/** Check whether access to the EN1 field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_S 0 + +/** Check whether access to the EN1 field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_EN1_P 0 + +/** Read the content of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN1_LSB, ATON_STRSWITCH_DSTRECBUF02_EN1_W) + +/** Modify the content of the EN1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN1_LSB, ATON_STRSWITCH_DSTRECBUF02_EN1_W, DATA) + + +/** + * Get the description of the EN1 field of DSTRECBUF02 register. + * + * \return the description of the EN1 field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_EN1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_EN1_DESC; +} + + +/** + * Read the content of the EN1 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the EN1 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_EN1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_EN1(reg); +} + + +/** + * Write the content of the EN1 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN1 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_EN1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_EN1(reg, data); +} + + +/* -------------------------------------------------------- LINK1 field of the DSTRECBUF02 register --------------------------------------------------------- */ + +/** Description of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_DESC "Source port of context 1" + +/** Offset of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB 17UL + +/** Size in bits of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_W (5UL) + +/** Mask for retrieving the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) + +/** Reset value of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_DT 0x0UL + +/** Access rights of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_AC "RW" + +/** Check whether access to the LINK1 field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_S 0 + +/** Check whether access to the LINK1 field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_LINK1_P 0 + +/** Read the content of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK1_W) + +/** Modify the content of the LINK1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK1_W, DATA) + + +/** + * Get the description of the LINK1 field of DSTRECBUF02 register. + * + * \return the description of the LINK1 field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_LINK1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_LINK1_DESC; +} + + +/** + * Read the content of the LINK1 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the LINK1 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_LINK1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_LINK1(reg); +} + + +/** + * Write the content of the LINK1 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 5-bit value that must be written to the field + * + * \return the new content of the LINK1 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_LINK1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_LINK1(reg, data); +} + + +/* ------------------------------------------------------- TICKTYPE field of the DSTRECBUF02 register ------------------------------------------------------- */ + +/** Description of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" + +/** Offset of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB 23UL + +/** Size in bits of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_W (1UL) + +/** Mask for retrieving the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) + +/** Reset value of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DT 0x0UL + +/** Access rights of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_AC "RW" + +/** Check whether access to the TICKTYPE field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_S 0 + +/** Check whether access to the TICKTYPE field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_P 0 + +/** Read the content of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_W) + +/** Modify the content of the TICKTYPE field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_W, DATA) + + +/** + * Get the description of the TICKTYPE field of DSTRECBUF02 register. + * + * \return the description of the TICKTYPE field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DESC; +} + + +/** + * Read the content of the TICKTYPE field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the TICKTYPE field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_TICKTYPE(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_TICKTYPE(reg); +} + + +/** + * Write the content of the TICKTYPE field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the TICKTYPE field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_TICKTYPE(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_TICKTYPE(reg, data); +} + + +/* --------------------------------------------------------- FNR1 field of the DSTRECBUF02 register --------------------------------------------------------- */ + +/** Description of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_DESC "Number of ticks for context 1" + +/** Offset of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB 24UL + +/** Size in bits of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_W (8UL) + +/** Mask for retrieving the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_DT 0x0UL + +/** Access rights of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_AC "RW" + +/** Check whether access to the FNR1 field of the DSTRECBUF02 register is secured or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_S 0 + +/** Check whether access to the FNR1 field of the DSTRECBUF02 register is privileged or not. */ +#define ATON_STRSWITCH_DSTRECBUF02_FNR1_P 0 + +/** Read the content of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR1_W) + +/** Modify the content of the FNR1 field of the DSTRECBUF02 register. */ +#define ATON_STRSWITCH_DSTRECBUF02_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR1_W, DATA) + + +/** + * Get the description of the FNR1 field of DSTRECBUF02 register. + * + * \return the description of the FNR1 field of DSTRECBUF02 register + */ + +static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_FNR1_GetdDesc(void) +{ + return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_FNR1_DESC; +} + + +/** + * Read the content of the FNR1 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * + * \return the content of the FNR1 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_FNR1(uint32_t reg) +{ + return ATON_STRSWITCH_DSTRECBUF02_GET_FNR1(reg); +} + + +/** + * Write the content of the FNR1 field of the DSTRECBUF02 register. + * + * \param[in] reg is the value of the DSTRECBUF02 register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FNR1 field belonging to DSTRECBUF02 register + */ + +static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_FNR1(uint32_t reg, uint32_t data) +{ + return ATON_STRSWITCH_DSTRECBUF02_SET_FNR1(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* CONVACC Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of CONVACC Unit instances. */ +#define ATON_CONVACC_NUM 4 + +/** + * \name Structures, macros and functions of the CONVACC Units + */ +/*@{*/ + +/** + * Registers of the CONVACC Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e KFORMAT register (Kernel format). */ + uint32_t KFORMAT; + + /** \e SAMPLE register (Data sampling). */ + uint32_t SAMPLE; + + /** \e DFORMAT register (Data format). */ + uint32_t DFORMAT; + + /** \e FFORMAT register (Feature Data input dimensions). */ + uint32_t FFORMAT; + + /** \e FHCROP register (Horizontal feature data cropping). */ + uint32_t FHCROP; + + /** \e FVCROP register (Vertical feature data cropping). */ + uint32_t FVCROP; + + /** \e KFILT register (Kernel filter). */ + uint32_t KFILT; + + /** \e AFILT register (Accumulator filter). */ + uint32_t AFILT; + + /** \e ZFRAME register (Zero Frame). */ + uint32_t ZFRAME; + + /** \e ITER register (Iteration Control). */ + uint32_t ITER; + + /** \e FSUB register (Feature data subtract). */ + uint32_t FSUB; + + /** \e ZFBIAS register (Zero Frame Bias). */ + uint32_t ZFBIAS; + +} ATON_CONVACC_t; + + +/** Return the pointer to one of the CONVACC Units. */ +#define ATON_CONVACC(UNIT) ((ATON_CONVACC_t *)(intptr_t)ATON_CONVACC_BASE(UNIT)) + + +/** Name of one of the CONVACC Units. */ +#define ATON_CONVACC_NAME(UNIT) \ + (((UNIT) == 0) ? "CONVACC0" : \ + (((UNIT) == 1) ? "CONVACC1" : \ + (((UNIT) == 2) ? "CONVACC2" : \ + (((UNIT) == 3) ? "CONVACC3" : "")))) + + +/** Version of the CONVACC Units. */ +#define ATON_CONVACC_VERSION "5.1" + + +/** Description of one of the CONVACC Units. */ +#define ATON_CONVACC_DESC(UNIT) \ + (((UNIT) == 0) ? "Convolutional Accelerator 0" : \ + (((UNIT) == 1) ? "Convolutional Accelerator 1" : \ + (((UNIT) == 2) ? "Convolutional Accelerator 2" : \ + (((UNIT) == 3) ? "Convolutional Accelerator 3" : "")))) + + +/** Base address of one of the CONVACC Units. */ +#define ATON_CONVACC_BASE(UNIT) \ + (ATON_BASE + 0xf000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the CONVACC Units. */ +#define ATON_CONVACC_SIZE 0x1000UL + + +/** + * Get the name of one of the CONVACC Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 4<\em>) + * + * \return the name of Unit having index \e instance among the CONVACC Units + */ + +static inline const int8_t *ATON_CONVACC_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"CONVACC0"; + break; + + case 1: + str = (const int8_t *)"CONVACC1"; + break; + + case 2: + str = (const int8_t *)"CONVACC2"; + break; + + case 3: + str = (const int8_t *)"CONVACC3"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the CONVACC Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 4<\em>) + * + * \return the description of Unit having index \e instance among the CONVACC Units + */ + +static inline const int8_t *ATON_CONVACC_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Convolutional Accelerator 0"; + break; + + case 1: + str = (const int8_t *)"Convolutional Accelerator 1"; + break; + + case 2: + str = (const int8_t *)"Convolutional Accelerator 2"; + break; + + case 3: + str = (const int8_t *)"Convolutional Accelerator 3"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the CONVACC Units. + * + * \return the version of the CONVACC Units + */ + +static inline const int8_t *ATON_CONVACC_GetVersion(void) +{ + return (const int8_t *)ATON_CONVACC_VERSION; +} + + +/** + * Get the base address of one of the CONVACC Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 4<\em>) + * + * \return the base address of Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_GetBase(uint32_t instance) +{ + return ATON_CONVACC_BASE(instance); +} + + +/** + * Get the size in bytes of the CONVACC Units. + * + * \return the size in bytes of the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_GetSize(void) +{ + return ATON_CONVACC_SIZE; +} + + +/* ******************************************************* CTRL register of one of the CONVACC Units ******************************************************** */ + +/** Offset of the CTRL register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the CONVACC Unit. */ +#define ATON_CONVACC_CTRL_DT \ + (ATON_CONVACC_CTRL_EN_DT << ATON_CONVACC_CTRL_EN_LSB) | \ + (ATON_CONVACC_CTRL_CLR_DT << ATON_CONVACC_CTRL_CLR_LSB) | \ + (ATON_CONVACC_CTRL_NOSUM_DT << ATON_CONVACC_CTRL_NOSUM_LSB) | \ + (ATON_CONVACC_CTRL_KT1_DT << ATON_CONVACC_CTRL_KT1_LSB) | \ + (ATON_CONVACC_CTRL_NO1SUM_DT << ATON_CONVACC_CTRL_NO1SUM_LSB) | \ + (ATON_CONVACC_CTRL_SIMD_DT << ATON_CONVACC_CTRL_SIMD_LSB) | \ + (ATON_CONVACC_CTRL_AFILTMODE_DT << ATON_CONVACC_CTRL_AFILTMODE_LSB) | \ + (ATON_CONVACC_CTRL_GEN1SUM_DT << ATON_CONVACC_CTRL_GEN1SUM_LSB) | \ + (ATON_CONVACC_CTRL_FC_DT << ATON_CONVACC_CTRL_FC_LSB) | \ + (ATON_CONVACC_CTRL_FC_TSIZE_DT << ATON_CONVACC_CTRL_FC_TSIZE_LSB) | \ + (ATON_CONVACC_CTRL_FC_VSIZE_DT << ATON_CONVACC_CTRL_FC_VSIZE_LSB) | \ + (ATON_CONVACC_CTRL_FUNSIGNED_DT << ATON_CONVACC_CTRL_FUNSIGNED_LSB) | \ + (ATON_CONVACC_CTRL_KUNSIGNED_DT << ATON_CONVACC_CTRL_KUNSIGNED_LSB) | \ + (ATON_CONVACC_CTRL_KSETEN_DT << ATON_CONVACC_CTRL_KSETEN_LSB) | \ + (ATON_CONVACC_CTRL_FSTAT_DT << ATON_CONVACC_CTRL_FSTAT_LSB) | \ + (ATON_CONVACC_CTRL_FSTATLOADED_DT << ATON_CONVACC_CTRL_FSTATLOADED_LSB) | \ + (ATON_CONVACC_CTRL_FSTATCLEAR_DT << ATON_CONVACC_CTRL_FSTATCLEAR_LSB) | \ + (ATON_CONVACC_CTRL_FSTATOVERF_DT << ATON_CONVACC_CTRL_FSTATOVERF_LSB) | \ + (ATON_CONVACC_CTRL_DEEPMODE_DT << ATON_CONVACC_CTRL_DEEPMODE_LSB) | \ + (ATON_CONVACC_CTRL_DSS2MODE_DT << ATON_CONVACC_CTRL_DSS2MODE_LSB) | \ + (ATON_CONVACC_CTRL_CONFCLR_DT << ATON_CONVACC_CTRL_CONFCLR_LSB) | \ + (ATON_CONVACC_CTRL_ILL_DT << ATON_CONVACC_CTRL_ILL_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_CONVACC_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the CONVACC Units. */ +#define ATON_CONVACC_CTRL_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the CONVACC Units. */ +#define ATON_CONVACC_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the CONVACC Units. */ +#define ATON_CONVACC_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_GetOffset(void) +{ + return ATON_CONVACC_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the CTRL register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_CTRL_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get(uint32_t instance) +{ + return ATON_CONVACC_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the CTRL register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_EN_DESC "Enable the Convolution Accelerator" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_EN_LSB, ATON_CONVACC_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_EN_LSB, ATON_CONVACC_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_EN(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_CLR_LSB, ATON_CONVACC_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_CLR_LSB, ATON_CONVACC_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_CLR(reg, data); +} + + +/* ------------------------------------------------------------ NOSUM field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NOSUM_DESC "Do not sum and synchronize with stream link input 2" + +/** Offset of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NOSUM_LSB 2UL + +/** Size in bits of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NOSUM_W (1UL) + +/** Mask for retrieving the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NOSUM_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NOSUM_DT 0x0UL + +/** Access rights of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NOSUM_AC "RW" + +/** Check whether access to the NOSUM field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_NOSUM_S 0 + +/** Check whether access to the NOSUM field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_NOSUM_P 0 + +/** Read the content of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_NOSUM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_NOSUM_LSB, ATON_CONVACC_CTRL_NOSUM_W) + +/** Modify the content of the NOSUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_NOSUM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_NOSUM_LSB, ATON_CONVACC_CTRL_NOSUM_W, DATA) + + +/** + * Get the description of the NOSUM field of CTRL register. + * + * \return the description of the NOSUM field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_NOSUM_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_NOSUM_DESC; +} + + +/** + * Read the content of the NOSUM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the NOSUM field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_NOSUM(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_NOSUM(reg); +} + + +/** + * Write the content of the NOSUM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the NOSUM field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_NOSUM(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_NOSUM(reg, data); +} + + +/* ------------------------------------------------------------- KT1 field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KT1_DESC "Load kernel from T1 buffer" + +/** Offset of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KT1_LSB 3UL + +/** Size in bits of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KT1_W (1UL) + +/** Mask for retrieving the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KT1_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KT1_DT 0x0UL + +/** Access rights of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KT1_AC "RW" + +/** Check whether access to the KT1 field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_KT1_S 0 + +/** Check whether access to the KT1 field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_KT1_P 0 + +/** Read the content of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_KT1(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_KT1_LSB, ATON_CONVACC_CTRL_KT1_W) + +/** Modify the content of the KT1 field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_KT1(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_KT1_LSB, ATON_CONVACC_CTRL_KT1_W, DATA) + + +/** + * Get the description of the KT1 field of CTRL register. + * + * \return the description of the KT1 field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_KT1_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_KT1_DESC; +} + + +/** + * Read the content of the KT1 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the KT1 field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_KT1(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_KT1(reg); +} + + +/** + * Write the content of the KT1 field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the KT1 field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_KT1(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_KT1(reg, data); +} + + +/* ----------------------------------------------------------- NO1SUM field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NO1SUM_DESC "No sum and synchronization with stream link input 2 for the first frame" + +/** Offset of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NO1SUM_LSB 4UL + +/** Size in bits of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NO1SUM_W (1UL) + +/** Mask for retrieving the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NO1SUM_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NO1SUM_DT 0x0UL + +/** Access rights of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_NO1SUM_AC "RW" + +/** Check whether access to the NO1SUM field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_NO1SUM_S 0 + +/** Check whether access to the NO1SUM field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_NO1SUM_P 0 + +/** Read the content of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_NO1SUM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_NO1SUM_LSB, ATON_CONVACC_CTRL_NO1SUM_W) + +/** Modify the content of the NO1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_NO1SUM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_NO1SUM_LSB, ATON_CONVACC_CTRL_NO1SUM_W, DATA) + + +/** + * Get the description of the NO1SUM field of CTRL register. + * + * \return the description of the NO1SUM field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_NO1SUM_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_NO1SUM_DESC; +} + + +/** + * Read the content of the NO1SUM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the NO1SUM field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_NO1SUM(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_NO1SUM(reg); +} + + +/** + * Write the content of the NO1SUM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the NO1SUM field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_NO1SUM(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_NO1SUM(reg, data); +} + + +/* ------------------------------------------------------------ SIMD field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SIMD_DESC "Enable 8x8bit (1) or 16x8bit (2) SIMD mode" + +/** Offset of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SIMD_LSB 5UL + +/** Size in bits of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SIMD_W (2UL) + +/** Mask for retrieving the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SIMD_MASK ATON_FIELD_MASK(5UL, 2UL) + +/** Reset value of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SIMD_DT 0x0UL + +/** Access rights of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SIMD_AC "RW" + +/** Check whether access to the SIMD field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_SIMD_S 0 + +/** Check whether access to the SIMD field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_SIMD_P 0 + +/** Read the content of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_SIMD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_SIMD_LSB, ATON_CONVACC_CTRL_SIMD_W) + +/** Modify the content of the SIMD field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_SIMD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_SIMD_LSB, ATON_CONVACC_CTRL_SIMD_W, DATA) + + +/** + * Get the description of the SIMD field of CTRL register. + * + * \return the description of the SIMD field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_SIMD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_SIMD_DESC; +} + + +/** + * Read the content of the SIMD field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SIMD field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_SIMD(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_SIMD(reg); +} + + +/** + * Write the content of the SIMD field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the SIMD field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_SIMD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_SIMD(reg, data); +} + + +/* ---------------------------------------------------------- AFILTMODE field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_AFILTMODE_DESC "Accumulator port filter mode" + +/** Offset of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_AFILTMODE_LSB 8UL + +/** Size in bits of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_AFILTMODE_W (2UL) + +/** Mask for retrieving the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_AFILTMODE_MASK ATON_FIELD_MASK(8UL, 2UL) + +/** Reset value of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_AFILTMODE_DT 0x0UL + +/** Access rights of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_AFILTMODE_AC "RW" + +/** Check whether access to the AFILTMODE field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_AFILTMODE_S 0 + +/** Check whether access to the AFILTMODE field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_AFILTMODE_P 0 + +/** Read the content of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_AFILTMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_AFILTMODE_LSB, ATON_CONVACC_CTRL_AFILTMODE_W) + +/** Modify the content of the AFILTMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_AFILTMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_AFILTMODE_LSB, ATON_CONVACC_CTRL_AFILTMODE_W, DATA) + + +/** + * Get the description of the AFILTMODE field of CTRL register. + * + * \return the description of the AFILTMODE field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_AFILTMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_AFILTMODE_DESC; +} + + +/** + * Read the content of the AFILTMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the AFILTMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_AFILTMODE(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_AFILTMODE(reg); +} + + +/** + * Write the content of the AFILTMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the AFILTMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_AFILTMODE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_AFILTMODE(reg, data); +} + + +/* ----------------------------------------------------------- GEN1SUM field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GEN1SUM_DESC "Generate first accumulator input frame internally" + +/** Offset of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GEN1SUM_LSB 10UL + +/** Size in bits of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GEN1SUM_W (1UL) + +/** Mask for retrieving the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GEN1SUM_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GEN1SUM_DT 0x0UL + +/** Access rights of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GEN1SUM_AC "RW" + +/** Check whether access to the GEN1SUM field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_GEN1SUM_S 0 + +/** Check whether access to the GEN1SUM field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_GEN1SUM_P 0 + +/** Read the content of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_GEN1SUM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_GEN1SUM_LSB, ATON_CONVACC_CTRL_GEN1SUM_W) + +/** Modify the content of the GEN1SUM field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_GEN1SUM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_GEN1SUM_LSB, ATON_CONVACC_CTRL_GEN1SUM_W, DATA) + + +/** + * Get the description of the GEN1SUM field of CTRL register. + * + * \return the description of the GEN1SUM field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_GEN1SUM_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_GEN1SUM_DESC; +} + + +/** + * Read the content of the GEN1SUM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the GEN1SUM field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_GEN1SUM(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_GEN1SUM(reg); +} + + +/** + * Write the content of the GEN1SUM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the GEN1SUM field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_GEN1SUM(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_GEN1SUM(reg, data); +} + + +/* ------------------------------------------------------------- FC field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_DESC "Run accelerator in fully connected mode" + +/** Offset of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_LSB 11UL + +/** Size in bits of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_W (1UL) + +/** Mask for retrieving the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_DT 0x0UL + +/** Access rights of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_AC "RW" + +/** Check whether access to the FC field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FC_S 0 + +/** Check whether access to the FC field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FC_P 0 + +/** Read the content of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FC(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FC_LSB, ATON_CONVACC_CTRL_FC_W) + +/** Modify the content of the FC field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FC(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FC_LSB, ATON_CONVACC_CTRL_FC_W, DATA) + + +/** + * Get the description of the FC field of CTRL register. + * + * \return the description of the FC field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FC_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FC_DESC; +} + + +/** + * Read the content of the FC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FC field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FC(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FC(reg); +} + + +/** + * Write the content of the FC field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FC field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FC(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FC(reg, data); +} + + +/* ---------------------------------------------------------- FC_TSIZE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_DESC "FC decode table size" + +/** Offset of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_LSB 12UL + +/** Size in bits of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_W (4UL) + +/** Mask for retrieving the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_DT 0x0UL + +/** Access rights of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_AC "RW" + +/** Check whether access to the FC_TSIZE field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_S 0 + +/** Check whether access to the FC_TSIZE field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FC_TSIZE_P 0 + +/** Read the content of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FC_TSIZE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FC_TSIZE_LSB, ATON_CONVACC_CTRL_FC_TSIZE_W) + +/** Modify the content of the FC_TSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FC_TSIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FC_TSIZE_LSB, ATON_CONVACC_CTRL_FC_TSIZE_W, DATA) + + +/** + * Get the description of the FC_TSIZE field of CTRL register. + * + * \return the description of the FC_TSIZE field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FC_TSIZE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FC_TSIZE_DESC; +} + + +/** + * Read the content of the FC_TSIZE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FC_TSIZE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FC_TSIZE(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FC_TSIZE(reg); +} + + +/** + * Write the content of the FC_TSIZE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the FC_TSIZE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FC_TSIZE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FC_TSIZE(reg, data); +} + + +/* ---------------------------------------------------------- FC_VSIZE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_DESC "FC vector size" + +/** Offset of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_LSB 16UL + +/** Size in bits of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_W (4UL) + +/** Mask for retrieving the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_MASK ATON_FIELD_MASK(16UL, 4UL) + +/** Reset value of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_DT 0x0UL + +/** Access rights of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_AC "RW" + +/** Check whether access to the FC_VSIZE field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_S 0 + +/** Check whether access to the FC_VSIZE field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FC_VSIZE_P 0 + +/** Read the content of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FC_VSIZE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FC_VSIZE_LSB, ATON_CONVACC_CTRL_FC_VSIZE_W) + +/** Modify the content of the FC_VSIZE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FC_VSIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FC_VSIZE_LSB, ATON_CONVACC_CTRL_FC_VSIZE_W, DATA) + + +/** + * Get the description of the FC_VSIZE field of CTRL register. + * + * \return the description of the FC_VSIZE field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FC_VSIZE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FC_VSIZE_DESC; +} + + +/** + * Read the content of the FC_VSIZE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FC_VSIZE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FC_VSIZE(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FC_VSIZE(reg); +} + + +/** + * Write the content of the FC_VSIZE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the FC_VSIZE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FC_VSIZE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FC_VSIZE(reg, data); +} + + +/* ---------------------------------------------------------- FUNSIGNED field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_DESC "Feature data unsigned" + +/** Offset of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_LSB 20UL + +/** Size in bits of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_W (1UL) + +/** Mask for retrieving the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_DT 0x0UL + +/** Access rights of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_AC "RW" + +/** Check whether access to the FUNSIGNED field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_S 0 + +/** Check whether access to the FUNSIGNED field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FUNSIGNED_P 0 + +/** Read the content of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FUNSIGNED(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FUNSIGNED_LSB, ATON_CONVACC_CTRL_FUNSIGNED_W) + +/** Modify the content of the FUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FUNSIGNED(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FUNSIGNED_LSB, ATON_CONVACC_CTRL_FUNSIGNED_W, DATA) + + +/** + * Get the description of the FUNSIGNED field of CTRL register. + * + * \return the description of the FUNSIGNED field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FUNSIGNED_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FUNSIGNED_DESC; +} + + +/** + * Read the content of the FUNSIGNED field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FUNSIGNED field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FUNSIGNED(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FUNSIGNED(reg); +} + + +/** + * Write the content of the FUNSIGNED field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FUNSIGNED field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FUNSIGNED(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FUNSIGNED(reg, data); +} + + +/* ---------------------------------------------------------- KUNSIGNED field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_DESC "Kernel data unsigned" + +/** Offset of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_LSB 21UL + +/** Size in bits of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_W (1UL) + +/** Mask for retrieving the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_MASK ATON_FIELD_MASK(21UL, 1UL) + +/** Reset value of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_DT 0x0UL + +/** Access rights of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_AC "RW" + +/** Check whether access to the KUNSIGNED field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_S 0 + +/** Check whether access to the KUNSIGNED field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_KUNSIGNED_P 0 + +/** Read the content of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_KUNSIGNED(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_KUNSIGNED_LSB, ATON_CONVACC_CTRL_KUNSIGNED_W) + +/** Modify the content of the KUNSIGNED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_KUNSIGNED(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_KUNSIGNED_LSB, ATON_CONVACC_CTRL_KUNSIGNED_W, DATA) + + +/** + * Get the description of the KUNSIGNED field of CTRL register. + * + * \return the description of the KUNSIGNED field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_KUNSIGNED_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_KUNSIGNED_DESC; +} + + +/** + * Read the content of the KUNSIGNED field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the KUNSIGNED field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_KUNSIGNED(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_KUNSIGNED(reg); +} + + +/** + * Write the content of the KUNSIGNED field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the KUNSIGNED field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_KUNSIGNED(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_KUNSIGNED(reg, data); +} + + +/* ----------------------------------------------------------- KSETEN field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KSETEN_DESC "Enable kernel set 0 (bit 0) or 1 (bit 1) if KT1 is 1, otherwise select byte 1 (0), byte 2 (1), byte 3 (2) or all bytes (Deep1x1 mode only) (3) of kernel stream in SIMD mode " + +/** Offset of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KSETEN_LSB 22UL + +/** Size in bits of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KSETEN_W (2UL) + +/** Mask for retrieving the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KSETEN_MASK ATON_FIELD_MASK(22UL, 2UL) + +/** Reset value of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KSETEN_DT 0x0UL + +/** Access rights of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_KSETEN_AC "RW" + +/** Check whether access to the KSETEN field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_KSETEN_S 0 + +/** Check whether access to the KSETEN field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_KSETEN_P 0 + +/** Read the content of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_KSETEN(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_KSETEN_LSB, ATON_CONVACC_CTRL_KSETEN_W) + +/** Modify the content of the KSETEN field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_KSETEN(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_KSETEN_LSB, ATON_CONVACC_CTRL_KSETEN_W, DATA) + + +/** + * Get the description of the KSETEN field of CTRL register. + * + * \return the description of the KSETEN field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_KSETEN_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_KSETEN_DESC; +} + + +/** + * Read the content of the KSETEN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the KSETEN field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_KSETEN(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_KSETEN(reg); +} + + +/** + * Write the content of the KSETEN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the KSETEN field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_KSETEN(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_KSETEN(reg, data); +} + + +/* ------------------------------------------------------------ FSTAT field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTAT_DESC "Feature data stationary" + +/** Offset of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTAT_LSB 24UL + +/** Size in bits of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTAT_W (1UL) + +/** Mask for retrieving the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTAT_MASK ATON_FIELD_MASK(24UL, 1UL) + +/** Reset value of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTAT_DT 0x0UL + +/** Access rights of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTAT_AC "RW" + +/** Check whether access to the FSTAT field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FSTAT_S 0 + +/** Check whether access to the FSTAT field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FSTAT_P 0 + +/** Read the content of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FSTAT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTAT_LSB, ATON_CONVACC_CTRL_FSTAT_W) + +/** Modify the content of the FSTAT field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FSTAT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FSTAT_LSB, ATON_CONVACC_CTRL_FSTAT_W, DATA) + + +/** + * Get the description of the FSTAT field of CTRL register. + * + * \return the description of the FSTAT field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FSTAT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FSTAT_DESC; +} + + +/** + * Read the content of the FSTAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSTAT field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FSTAT(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FSTAT(reg); +} + + +/** + * Write the content of the FSTAT field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSTAT field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FSTAT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FSTAT(reg, data); +} + + +/* --------------------------------------------------------- FSTATLOADED field of the CTRL register --------------------------------------------------------- */ + +/** Description of the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_DESC "Feature data stationary loaded" + +/** Offset of the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_LSB 25UL + +/** Size in bits of the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_W (1UL) + +/** Mask for retrieving the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_MASK ATON_FIELD_MASK(25UL, 1UL) + +/** Reset value of the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_DT 0x0UL + +/** Access rights of the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_AC "R" + +/** Check whether access to the FSTATLOADED field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_S 0 + +/** Check whether access to the FSTATLOADED field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FSTATLOADED_P 0 + +/** Read the content of the FSTATLOADED field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FSTATLOADED(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTATLOADED_LSB, ATON_CONVACC_CTRL_FSTATLOADED_W) + + +/** + * Get the description of the FSTATLOADED field of CTRL register. + * + * \return the description of the FSTATLOADED field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FSTATLOADED_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FSTATLOADED_DESC; +} + + +/** + * Read the content of the FSTATLOADED field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSTATLOADED field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FSTATLOADED(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FSTATLOADED(reg); +} + + +/* --------------------------------------------------------- FSTATCLEAR field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_DESC "Feature data stationary clear" + +/** Offset of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_LSB 26UL + +/** Size in bits of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_W (1UL) + +/** Mask for retrieving the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_MASK ATON_FIELD_MASK(26UL, 1UL) + +/** Reset value of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_DT 0x0UL + +/** Access rights of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_AC "RW" + +/** Check whether access to the FSTATCLEAR field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_S 0 + +/** Check whether access to the FSTATCLEAR field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FSTATCLEAR_P 0 + +/** Read the content of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FSTATCLEAR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTATCLEAR_LSB, ATON_CONVACC_CTRL_FSTATCLEAR_W) + +/** Modify the content of the FSTATCLEAR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FSTATCLEAR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FSTATCLEAR_LSB, ATON_CONVACC_CTRL_FSTATCLEAR_W, DATA) + + +/** + * Get the description of the FSTATCLEAR field of CTRL register. + * + * \return the description of the FSTATCLEAR field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FSTATCLEAR_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FSTATCLEAR_DESC; +} + + +/** + * Read the content of the FSTATCLEAR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSTATCLEAR field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FSTATCLEAR(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FSTATCLEAR(reg); +} + + +/** + * Write the content of the FSTATCLEAR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSTATCLEAR field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FSTATCLEAR(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FSTATCLEAR(reg, data); +} + + +/* --------------------------------------------------------- FSTATOVERF field of the CTRL register ---------------------------------------------------------- */ + +/** Description of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_DESC "Feature data stationary overflow" + +/** Offset of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_LSB 27UL + +/** Size in bits of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_W (1UL) + +/** Mask for retrieving the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_MASK ATON_FIELD_MASK(27UL, 1UL) + +/** Reset value of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_DT 0x0UL + +/** Access rights of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_AC "RW" + +/** Check whether access to the FSTATOVERF field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_S 0 + +/** Check whether access to the FSTATOVERF field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_FSTATOVERF_P 0 + +/** Read the content of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_FSTATOVERF(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTATOVERF_LSB, ATON_CONVACC_CTRL_FSTATOVERF_W) + +/** Modify the content of the FSTATOVERF field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_FSTATOVERF(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FSTATOVERF_LSB, ATON_CONVACC_CTRL_FSTATOVERF_W, DATA) + + +/** + * Get the description of the FSTATOVERF field of CTRL register. + * + * \return the description of the FSTATOVERF field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_FSTATOVERF_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_FSTATOVERF_DESC; +} + + +/** + * Read the content of the FSTATOVERF field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the FSTATOVERF field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_FSTATOVERF(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_FSTATOVERF(reg); +} + + +/** + * Write the content of the FSTATOVERF field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSTATOVERF field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_FSTATOVERF(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_FSTATOVERF(reg, data); +} + + +/* ---------------------------------------------------------- DEEPMODE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DEEPMODE_DESC "Deep1x1 optimized mode" + +/** Offset of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DEEPMODE_LSB 28UL + +/** Size in bits of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DEEPMODE_W (1UL) + +/** Mask for retrieving the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DEEPMODE_MASK ATON_FIELD_MASK(28UL, 1UL) + +/** Reset value of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DEEPMODE_DT 0x0UL + +/** Access rights of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DEEPMODE_AC "RW" + +/** Check whether access to the DEEPMODE field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_DEEPMODE_S 0 + +/** Check whether access to the DEEPMODE field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_DEEPMODE_P 0 + +/** Read the content of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_DEEPMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_DEEPMODE_LSB, ATON_CONVACC_CTRL_DEEPMODE_W) + +/** Modify the content of the DEEPMODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_DEEPMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_DEEPMODE_LSB, ATON_CONVACC_CTRL_DEEPMODE_W, DATA) + + +/** + * Get the description of the DEEPMODE field of CTRL register. + * + * \return the description of the DEEPMODE field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_DEEPMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_DEEPMODE_DESC; +} + + +/** + * Read the content of the DEEPMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DEEPMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_DEEPMODE(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_DEEPMODE(reg); +} + + +/** + * Write the content of the DEEPMODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DEEPMODE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_DEEPMODE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_DEEPMODE(reg, data); +} + + +/* ---------------------------------------------------------- DSS2MODE field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DSS2MODE_DESC "DSS2 (depth separable stride 2) optimized mode" + +/** Offset of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DSS2MODE_LSB 29UL + +/** Size in bits of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DSS2MODE_W (1UL) + +/** Mask for retrieving the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DSS2MODE_MASK ATON_FIELD_MASK(29UL, 1UL) + +/** Reset value of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DSS2MODE_DT 0x0UL + +/** Access rights of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_DSS2MODE_AC "RW" + +/** Check whether access to the DSS2MODE field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_DSS2MODE_S 0 + +/** Check whether access to the DSS2MODE field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_DSS2MODE_P 0 + +/** Read the content of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_DSS2MODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_DSS2MODE_LSB, ATON_CONVACC_CTRL_DSS2MODE_W) + +/** Modify the content of the DSS2MODE field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_DSS2MODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_DSS2MODE_LSB, ATON_CONVACC_CTRL_DSS2MODE_W, DATA) + + +/** + * Get the description of the DSS2MODE field of CTRL register. + * + * \return the description of the DSS2MODE field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_DSS2MODE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_DSS2MODE_DESC; +} + + +/** + * Read the content of the DSS2MODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DSS2MODE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_DSS2MODE(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_DSS2MODE(reg); +} + + +/** + * Write the content of the DSS2MODE field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DSS2MODE field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_DSS2MODE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_DSS2MODE(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CONFCLR_DESC "Clear Configuration registers (auto cleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_CONFCLR_LSB, ATON_CONVACC_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_CONVACC_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_CONFCLR_LSB, ATON_CONVACC_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_CTRL_SET_CONFCLR(reg, data); +} + + +/* ------------------------------------------------------------- ILL field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_ILL_DESC "Illegal configuration" + +/** Offset of the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_ILL_LSB 31UL + +/** Size in bits of the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_ILL_W (1UL) + +/** Mask for retrieving the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_ILL_MASK ATON_FIELD_MASK(31UL, 1UL) + +/** Reset value of the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_ILL_DT 0x0UL + +/** Access rights of the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_ILL_AC "R" + +/** Check whether access to the ILL field of the CTRL register is secured or not. */ +#define ATON_CONVACC_CTRL_ILL_S 0 + +/** Check whether access to the ILL field of the CTRL register is privileged or not. */ +#define ATON_CONVACC_CTRL_ILL_P 0 + +/** Read the content of the ILL field of the CTRL register. */ +#define ATON_CONVACC_CTRL_GET_ILL(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_ILL_LSB, ATON_CONVACC_CTRL_ILL_W) + + +/** + * Get the description of the ILL field of CTRL register. + * + * \return the description of the ILL field of CTRL register + */ + +static inline const int8_t *ATON_CONVACC_CTRL_ILL_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_CTRL_ILL_DESC; +} + + +/** + * Read the content of the ILL field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ILL field belonging to CTRL register + */ + +static inline uint32_t ATON_CONVACC_CTRL_Get_ILL(uint32_t reg) +{ + return ATON_CONVACC_CTRL_GET_ILL(reg); +} + + +/* ****************************************************** VERSION register of one of the CONVACC Units ****************************************************** */ + +/** Offset of the VERSION register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the CONVACC Unit. */ +#define ATON_CONVACC_VERSION_DT \ + (ATON_CONVACC_VERSION_TYPE_DT << ATON_CONVACC_VERSION_TYPE_LSB) | \ + (ATON_CONVACC_VERSION_MINOR_DT << ATON_CONVACC_VERSION_MINOR_LSB) | \ + (ATON_CONVACC_VERSION_MAJOR_DT << ATON_CONVACC_VERSION_MAJOR_LSB) | \ + (ATON_CONVACC_VERSION_NRCLUSTER_DT << ATON_CONVACC_VERSION_NRCLUSTER_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_CONVACC_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the CONVACC Units. */ +#define ATON_CONVACC_VERSION_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the CONVACC Units. */ +#define ATON_CONVACC_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_CONVACC_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_CONVACC_VERSION_GetOffset(void) +{ + return ATON_CONVACC_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the VERSION register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_VERSION_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_VERSION_Get(uint32_t instance) +{ + return ATON_CONVACC_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_TYPE_DT 0x17UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_CONVACC_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_CONVACC_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_CONVACC_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_TYPE_LSB, ATON_CONVACC_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_CONVACC_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_CONVACC_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_CONVACC_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MINOR_DT 0x1UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_CONVACC_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_CONVACC_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_MINOR_LSB, ATON_CONVACC_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_CONVACC_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_CONVACC_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_CONVACC_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MAJOR_DT 0x5UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_CONVACC_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_CONVACC_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_CONVACC_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_MAJOR_LSB, ATON_CONVACC_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_CONVACC_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_CONVACC_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_CONVACC_VERSION_GET_MAJOR(reg); +} + + +/* -------------------------------------------------------- NRCLUSTER field of the VERSION register --------------------------------------------------------- */ + +/** Description of the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_DESC "Number of MAC clusters" + +/** Offset of the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_LSB 16UL + +/** Size in bits of the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_W (4UL) + +/** Mask for retrieving the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_MASK ATON_FIELD_MASK(16UL, 4UL) + +/** Reset value of the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_DT 0x6UL + +/** Access rights of the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_AC "R" + +/** Check whether access to the NRCLUSTER field of the VERSION register is secured or not. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_S 0 + +/** Check whether access to the NRCLUSTER field of the VERSION register is privileged or not. */ +#define ATON_CONVACC_VERSION_NRCLUSTER_P 0 + +/** Read the content of the NRCLUSTER field of the VERSION register. */ +#define ATON_CONVACC_VERSION_GET_NRCLUSTER(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_NRCLUSTER_LSB, ATON_CONVACC_VERSION_NRCLUSTER_W) + + +/** + * Get the description of the NRCLUSTER field of VERSION register. + * + * \return the description of the NRCLUSTER field of VERSION register + */ + +static inline const int8_t *ATON_CONVACC_VERSION_NRCLUSTER_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_VERSION_NRCLUSTER_DESC; +} + + +/** + * Read the content of the NRCLUSTER field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the NRCLUSTER field belonging to VERSION register + */ + +static inline uint32_t ATON_CONVACC_VERSION_Get_NRCLUSTER(uint32_t reg) +{ + return ATON_CONVACC_VERSION_GET_NRCLUSTER(reg); +} + + +/* ****************************************************** KFORMAT register of one of the CONVACC Units ****************************************************** */ + +/** Offset of the KFORMAT register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_KFORMAT_OFFSET 0x8UL + +/** Reset value of the KFORMAT register of the CONVACC Unit. */ +#define ATON_CONVACC_KFORMAT_DT \ + (ATON_CONVACC_KFORMAT_WIDTH_DT << ATON_CONVACC_KFORMAT_WIDTH_LSB) | \ + (ATON_CONVACC_KFORMAT_HEIGHT_DT << ATON_CONVACC_KFORMAT_HEIGHT_LSB) | \ + (ATON_CONVACC_KFORMAT_BTCDEPTH_DT << ATON_CONVACC_KFORMAT_BTCDEPTH_LSB) | \ + (ATON_CONVACC_KFORMAT_NR_DT << ATON_CONVACC_KFORMAT_NR_LSB) + + + +/** Description of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_DESC "Kernel format" + +/** Address of the KFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_KFORMAT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_KFORMAT_OFFSET) + +/** Get the content of the KFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_KFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFORMAT_ADDR(UNIT))) + +/** Set the content of the KFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_KFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFORMAT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KFORMAT register. + * + * \return the description of KFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_KFORMAT_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFORMAT_DESC; +} + + +/** + * Get the offset of the KFORMAT register. + * + * \return the offset of KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_GetOffset(void) +{ + return ATON_CONVACC_KFORMAT_OFFSET; +} + + +/** + * Get the address of the KFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFORMAT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of KFORMAT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_KFORMAT_ADDR(instance); +} + + +/** + * Read the content of the KFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFORMAT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of KFORMAT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Get(uint32_t instance) +{ + return ATON_CONVACC_KFORMAT_GET(instance); +} + + +/** + * Write the content of the KFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFORMAT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_KFORMAT_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_KFORMAT_SET(instance, data); +} + + +/* ---------------------------------------------------------- WIDTH field of the KFORMAT register ----------------------------------------------------------- */ + +/** Description of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_WIDTH_DESC "Kernel width" + +/** Offset of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_WIDTH_LSB 0UL + +/** Size in bits of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_WIDTH_W (8UL) + +/** Mask for retrieving the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_WIDTH_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_WIDTH_DT 0x3UL + +/** Access rights of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_WIDTH_AC "RW" + +/** Check whether access to the WIDTH field of the KFORMAT register is secured or not. */ +#define ATON_CONVACC_KFORMAT_WIDTH_S 0 + +/** Check whether access to the WIDTH field of the KFORMAT register is privileged or not. */ +#define ATON_CONVACC_KFORMAT_WIDTH_P 0 + +/** Read the content of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_GET_WIDTH(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_WIDTH_LSB, ATON_CONVACC_KFORMAT_WIDTH_W) + +/** Modify the content of the WIDTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_SET_WIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_WIDTH_LSB, ATON_CONVACC_KFORMAT_WIDTH_W, DATA) + + +/** + * Get the description of the WIDTH field of KFORMAT register. + * + * \return the description of the WIDTH field of KFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_KFORMAT_WIDTH_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFORMAT_WIDTH_DESC; +} + + +/** + * Read the content of the WIDTH field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * + * \return the content of the WIDTH field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Get_WIDTH(uint32_t reg) +{ + return ATON_CONVACC_KFORMAT_GET_WIDTH(reg); +} + + +/** + * Write the content of the WIDTH field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the WIDTH field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Set_WIDTH(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFORMAT_SET_WIDTH(reg, data); +} + + +/* ---------------------------------------------------------- HEIGHT field of the KFORMAT register ---------------------------------------------------------- */ + +/** Description of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_DESC "Kernel height" + +/** Offset of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_LSB 8UL + +/** Size in bits of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_W (8UL) + +/** Mask for retrieving the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_DT 0x3UL + +/** Access rights of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_AC "RW" + +/** Check whether access to the HEIGHT field of the KFORMAT register is secured or not. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_S 0 + +/** Check whether access to the HEIGHT field of the KFORMAT register is privileged or not. */ +#define ATON_CONVACC_KFORMAT_HEIGHT_P 0 + +/** Read the content of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_GET_HEIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_HEIGHT_LSB, ATON_CONVACC_KFORMAT_HEIGHT_W) + +/** Modify the content of the HEIGHT field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_SET_HEIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_HEIGHT_LSB, ATON_CONVACC_KFORMAT_HEIGHT_W, DATA) + + +/** + * Get the description of the HEIGHT field of KFORMAT register. + * + * \return the description of the HEIGHT field of KFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_KFORMAT_HEIGHT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFORMAT_HEIGHT_DESC; +} + + +/** + * Read the content of the HEIGHT field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * + * \return the content of the HEIGHT field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Get_HEIGHT(uint32_t reg) +{ + return ATON_CONVACC_KFORMAT_GET_HEIGHT(reg); +} + + +/** + * Write the content of the HEIGHT field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the HEIGHT field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Set_HEIGHT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFORMAT_SET_HEIGHT(reg, data); +} + + +/* --------------------------------------------------------- BTCDEPTH field of the KFORMAT register --------------------------------------------------------- */ + +/** Description of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_DESC "Batch Depth" + +/** Offset of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_LSB 16UL + +/** Size in bits of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_W (8UL) + +/** Mask for retrieving the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_DT 0x1UL + +/** Access rights of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_AC "RW" + +/** Check whether access to the BTCDEPTH field of the KFORMAT register is secured or not. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_S 0 + +/** Check whether access to the BTCDEPTH field of the KFORMAT register is privileged or not. */ +#define ATON_CONVACC_KFORMAT_BTCDEPTH_P 0 + +/** Read the content of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_GET_BTCDEPTH(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_BTCDEPTH_LSB, ATON_CONVACC_KFORMAT_BTCDEPTH_W) + +/** Modify the content of the BTCDEPTH field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_SET_BTCDEPTH(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_BTCDEPTH_LSB, ATON_CONVACC_KFORMAT_BTCDEPTH_W, DATA) + + +/** + * Get the description of the BTCDEPTH field of KFORMAT register. + * + * \return the description of the BTCDEPTH field of KFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_KFORMAT_BTCDEPTH_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFORMAT_BTCDEPTH_DESC; +} + + +/** + * Read the content of the BTCDEPTH field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * + * \return the content of the BTCDEPTH field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Get_BTCDEPTH(uint32_t reg) +{ + return ATON_CONVACC_KFORMAT_GET_BTCDEPTH(reg); +} + + +/** + * Write the content of the BTCDEPTH field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the BTCDEPTH field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Set_BTCDEPTH(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFORMAT_SET_BTCDEPTH(reg, data); +} + + +/* ------------------------------------------------------------ NR field of the KFORMAT register ------------------------------------------------------------ */ + +/** Description of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_NR_DESC "Total number of parallel kernels" + +/** Offset of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_NR_LSB 24UL + +/** Size in bits of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_NR_W (8UL) + +/** Mask for retrieving the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_NR_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_NR_DT 0x1UL + +/** Access rights of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_NR_AC "RW" + +/** Check whether access to the NR field of the KFORMAT register is secured or not. */ +#define ATON_CONVACC_KFORMAT_NR_S 0 + +/** Check whether access to the NR field of the KFORMAT register is privileged or not. */ +#define ATON_CONVACC_KFORMAT_NR_P 0 + +/** Read the content of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_GET_NR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_NR_LSB, ATON_CONVACC_KFORMAT_NR_W) + +/** Modify the content of the NR field of the KFORMAT register. */ +#define ATON_CONVACC_KFORMAT_SET_NR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_NR_LSB, ATON_CONVACC_KFORMAT_NR_W, DATA) + + +/** + * Get the description of the NR field of KFORMAT register. + * + * \return the description of the NR field of KFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_KFORMAT_NR_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFORMAT_NR_DESC; +} + + +/** + * Read the content of the NR field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * + * \return the content of the NR field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Get_NR(uint32_t reg) +{ + return ATON_CONVACC_KFORMAT_GET_NR(reg); +} + + +/** + * Write the content of the NR field of the KFORMAT register. + * + * \param[in] reg is the value of the KFORMAT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the NR field belonging to KFORMAT register + */ + +static inline uint32_t ATON_CONVACC_KFORMAT_Set_NR(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFORMAT_SET_NR(reg, data); +} + + +/* ****************************************************** SAMPLE register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the SAMPLE register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_SAMPLE_OFFSET 0xcUL + +/** Reset value of the SAMPLE register of the CONVACC Unit. */ +#define ATON_CONVACC_SAMPLE_DT \ + (ATON_CONVACC_SAMPLE_LPAD_DT << ATON_CONVACC_SAMPLE_LPAD_LSB) | \ + (ATON_CONVACC_SAMPLE_RPAD_DT << ATON_CONVACC_SAMPLE_RPAD_LSB) | \ + (ATON_CONVACC_SAMPLE_TPAD_DT << ATON_CONVACC_SAMPLE_TPAD_LSB) | \ + (ATON_CONVACC_SAMPLE_BPAD_DT << ATON_CONVACC_SAMPLE_BPAD_LSB) | \ + (ATON_CONVACC_SAMPLE_HSTRD_DT << ATON_CONVACC_SAMPLE_HSTRD_LSB) | \ + (ATON_CONVACC_SAMPLE_VSTRD_DT << ATON_CONVACC_SAMPLE_VSTRD_LSB) | \ + (ATON_CONVACC_SAMPLE_FSTATCNT_DT << ATON_CONVACC_SAMPLE_FSTATCNT_LSB) + + + +/** Description of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_DESC "Data sampling" + +/** Address of the SAMPLE register of one of the CONVACC Units. */ +#define ATON_CONVACC_SAMPLE_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_SAMPLE_OFFSET) + +/** Get the content of the SAMPLE register of one of the CONVACC Units. */ +#define ATON_CONVACC_SAMPLE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_SAMPLE_ADDR(UNIT))) + +/** Set the content of the SAMPLE register of one of the CONVACC Units. */ +#define ATON_CONVACC_SAMPLE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_SAMPLE_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of SAMPLE register. + * + * \return the description of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_DESC; +} + + +/** + * Get the offset of the SAMPLE register. + * + * \return the offset of SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_GetOffset(void) +{ + return ATON_CONVACC_SAMPLE_OFFSET; +} + + +/** + * Get the address of the SAMPLE register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the SAMPLE register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of SAMPLE register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_SAMPLE_ADDR(instance); +} + + +/** + * Read the content of the SAMPLE register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the SAMPLE register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of SAMPLE register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get(uint32_t instance) +{ + return ATON_CONVACC_SAMPLE_GET(instance); +} + + +/** + * Write the content of the SAMPLE register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the SAMPLE register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_SAMPLE_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_SAMPLE_SET(instance, data); +} + + +/* ----------------------------------------------------------- LPAD field of the SAMPLE register ------------------------------------------------------------ */ + +/** Description of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_LPAD_DESC "Number of vertical left dummy columns" + +/** Offset of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_LPAD_LSB 0UL + +/** Size in bits of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_LPAD_W (2UL) + +/** Mask for retrieving the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_LPAD_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_LPAD_DT 0x0UL + +/** Access rights of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_LPAD_AC "RW" + +/** Check whether access to the LPAD field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_LPAD_S 0 + +/** Check whether access to the LPAD field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_LPAD_P 0 + +/** Read the content of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_LPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_LPAD_LSB, ATON_CONVACC_SAMPLE_LPAD_W) + +/** Modify the content of the LPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_LPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_LPAD_LSB, ATON_CONVACC_SAMPLE_LPAD_W, DATA) + + +/** + * Get the description of the LPAD field of SAMPLE register. + * + * \return the description of the LPAD field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_LPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_LPAD_DESC; +} + + +/** + * Read the content of the LPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the LPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_LPAD(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_LPAD(reg); +} + + +/** + * Write the content of the LPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the LPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_LPAD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_LPAD(reg, data); +} + + +/* ----------------------------------------------------------- RPAD field of the SAMPLE register ------------------------------------------------------------ */ + +/** Description of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_RPAD_DESC "Number of vertical right dummy columns" + +/** Offset of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_RPAD_LSB 2UL + +/** Size in bits of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_RPAD_W (2UL) + +/** Mask for retrieving the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_RPAD_MASK ATON_FIELD_MASK(2UL, 2UL) + +/** Reset value of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_RPAD_DT 0x0UL + +/** Access rights of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_RPAD_AC "RW" + +/** Check whether access to the RPAD field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_RPAD_S 0 + +/** Check whether access to the RPAD field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_RPAD_P 0 + +/** Read the content of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_RPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_RPAD_LSB, ATON_CONVACC_SAMPLE_RPAD_W) + +/** Modify the content of the RPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_RPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_RPAD_LSB, ATON_CONVACC_SAMPLE_RPAD_W, DATA) + + +/** + * Get the description of the RPAD field of SAMPLE register. + * + * \return the description of the RPAD field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_RPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_RPAD_DESC; +} + + +/** + * Read the content of the RPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the RPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_RPAD(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_RPAD(reg); +} + + +/** + * Write the content of the RPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the RPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_RPAD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_RPAD(reg, data); +} + + +/* ----------------------------------------------------------- TPAD field of the SAMPLE register ------------------------------------------------------------ */ + +/** Description of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_TPAD_DESC "Number of horizontal top dummy lines" + +/** Offset of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_TPAD_LSB 4UL + +/** Size in bits of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_TPAD_W (2UL) + +/** Mask for retrieving the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_TPAD_MASK ATON_FIELD_MASK(4UL, 2UL) + +/** Reset value of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_TPAD_DT 0x0UL + +/** Access rights of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_TPAD_AC "RW" + +/** Check whether access to the TPAD field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_TPAD_S 0 + +/** Check whether access to the TPAD field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_TPAD_P 0 + +/** Read the content of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_TPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_TPAD_LSB, ATON_CONVACC_SAMPLE_TPAD_W) + +/** Modify the content of the TPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_TPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_TPAD_LSB, ATON_CONVACC_SAMPLE_TPAD_W, DATA) + + +/** + * Get the description of the TPAD field of SAMPLE register. + * + * \return the description of the TPAD field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_TPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_TPAD_DESC; +} + + +/** + * Read the content of the TPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the TPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_TPAD(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_TPAD(reg); +} + + +/** + * Write the content of the TPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the TPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_TPAD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_TPAD(reg, data); +} + + +/* ----------------------------------------------------------- BPAD field of the SAMPLE register ------------------------------------------------------------ */ + +/** Description of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_BPAD_DESC "Number of horizontal bottom dummy lines" + +/** Offset of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_BPAD_LSB 6UL + +/** Size in bits of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_BPAD_W (2UL) + +/** Mask for retrieving the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_BPAD_MASK ATON_FIELD_MASK(6UL, 2UL) + +/** Reset value of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_BPAD_DT 0x0UL + +/** Access rights of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_BPAD_AC "RW" + +/** Check whether access to the BPAD field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_BPAD_S 0 + +/** Check whether access to the BPAD field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_BPAD_P 0 + +/** Read the content of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_BPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_BPAD_LSB, ATON_CONVACC_SAMPLE_BPAD_W) + +/** Modify the content of the BPAD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_BPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_BPAD_LSB, ATON_CONVACC_SAMPLE_BPAD_W, DATA) + + +/** + * Get the description of the BPAD field of SAMPLE register. + * + * \return the description of the BPAD field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_BPAD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_BPAD_DESC; +} + + +/** + * Read the content of the BPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the BPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_BPAD(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_BPAD(reg); +} + + +/** + * Write the content of the BPAD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the BPAD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_BPAD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_BPAD(reg, data); +} + + +/* ----------------------------------------------------------- HSTRD field of the SAMPLE register ----------------------------------------------------------- */ + +/** Description of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_HSTRD_DESC "Horizontal stride" + +/** Offset of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_HSTRD_LSB 8UL + +/** Size in bits of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_HSTRD_W (3UL) + +/** Mask for retrieving the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_HSTRD_MASK ATON_FIELD_MASK(8UL, 3UL) + +/** Reset value of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_HSTRD_DT 0x1UL + +/** Access rights of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_HSTRD_AC "RW" + +/** Check whether access to the HSTRD field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_HSTRD_S 0 + +/** Check whether access to the HSTRD field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_HSTRD_P 0 + +/** Read the content of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_HSTRD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_HSTRD_LSB, ATON_CONVACC_SAMPLE_HSTRD_W) + +/** Modify the content of the HSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_HSTRD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_HSTRD_LSB, ATON_CONVACC_SAMPLE_HSTRD_W, DATA) + + +/** + * Get the description of the HSTRD field of SAMPLE register. + * + * \return the description of the HSTRD field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_HSTRD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_HSTRD_DESC; +} + + +/** + * Read the content of the HSTRD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the HSTRD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_HSTRD(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_HSTRD(reg); +} + + +/** + * Write the content of the HSTRD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the HSTRD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_HSTRD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_HSTRD(reg, data); +} + + +/* ----------------------------------------------------------- VSTRD field of the SAMPLE register ----------------------------------------------------------- */ + +/** Description of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_VSTRD_DESC "Vertical stride" + +/** Offset of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_VSTRD_LSB 12UL + +/** Size in bits of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_VSTRD_W (3UL) + +/** Mask for retrieving the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_VSTRD_MASK ATON_FIELD_MASK(12UL, 3UL) + +/** Reset value of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_VSTRD_DT 0x1UL + +/** Access rights of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_VSTRD_AC "RW" + +/** Check whether access to the VSTRD field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_VSTRD_S 0 + +/** Check whether access to the VSTRD field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_VSTRD_P 0 + +/** Read the content of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_VSTRD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_VSTRD_LSB, ATON_CONVACC_SAMPLE_VSTRD_W) + +/** Modify the content of the VSTRD field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_VSTRD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_VSTRD_LSB, ATON_CONVACC_SAMPLE_VSTRD_W, DATA) + + +/** + * Get the description of the VSTRD field of SAMPLE register. + * + * \return the description of the VSTRD field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_VSTRD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_VSTRD_DESC; +} + + +/** + * Read the content of the VSTRD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the VSTRD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_VSTRD(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_VSTRD(reg); +} + + +/** + * Write the content of the VSTRD field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the VSTRD field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_VSTRD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_VSTRD(reg, data); +} + + +/* --------------------------------------------------------- FSTATCNT field of the SAMPLE register ---------------------------------------------------------- */ + +/** Description of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_DESC "Number of frames before next reload of feature stationary frame" + +/** Offset of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_LSB 16UL + +/** Size in bits of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_W (16UL) + +/** Mask for retrieving the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_DT 0x0UL + +/** Access rights of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_AC "RW" + +/** Check whether access to the FSTATCNT field of the SAMPLE register is secured or not. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_S 0 + +/** Check whether access to the FSTATCNT field of the SAMPLE register is privileged or not. */ +#define ATON_CONVACC_SAMPLE_FSTATCNT_P 0 + +/** Read the content of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_GET_FSTATCNT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_FSTATCNT_LSB, ATON_CONVACC_SAMPLE_FSTATCNT_W) + +/** Modify the content of the FSTATCNT field of the SAMPLE register. */ +#define ATON_CONVACC_SAMPLE_SET_FSTATCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_FSTATCNT_LSB, ATON_CONVACC_SAMPLE_FSTATCNT_W, DATA) + + +/** + * Get the description of the FSTATCNT field of SAMPLE register. + * + * \return the description of the FSTATCNT field of SAMPLE register + */ + +static inline const int8_t *ATON_CONVACC_SAMPLE_FSTATCNT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_SAMPLE_FSTATCNT_DESC; +} + + +/** + * Read the content of the FSTATCNT field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * + * \return the content of the FSTATCNT field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Get_FSTATCNT(uint32_t reg) +{ + return ATON_CONVACC_SAMPLE_GET_FSTATCNT(reg); +} + + +/** + * Write the content of the FSTATCNT field of the SAMPLE register. + * + * \param[in] reg is the value of the SAMPLE register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FSTATCNT field belonging to SAMPLE register + */ + +static inline uint32_t ATON_CONVACC_SAMPLE_Set_FSTATCNT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_SAMPLE_SET_FSTATCNT(reg, data); +} + + +/* ****************************************************** DFORMAT register of one of the CONVACC Units ****************************************************** */ + +/** Offset of the DFORMAT register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_DFORMAT_OFFSET 0x10UL + +/** Reset value of the DFORMAT register of the CONVACC Unit. */ +#define ATON_CONVACC_DFORMAT_DT \ + (ATON_CONVACC_DFORMAT_INSHIFT_DT << ATON_CONVACC_DFORMAT_INSHIFT_LSB) | \ + (ATON_CONVACC_DFORMAT_FRNDMODE_DT << ATON_CONVACC_DFORMAT_FRNDMODE_LSB) | \ + (ATON_CONVACC_DFORMAT_OUTSHIFT_DT << ATON_CONVACC_DFORMAT_OUTSHIFT_LSB) | \ + (ATON_CONVACC_DFORMAT_ORNDMODE_DT << ATON_CONVACC_DFORMAT_ORNDMODE_LSB) | \ + (ATON_CONVACC_DFORMAT_ROUND_DT << ATON_CONVACC_DFORMAT_ROUND_LSB) | \ + (ATON_CONVACC_DFORMAT_SAT_DT << ATON_CONVACC_DFORMAT_SAT_LSB) | \ + (ATON_CONVACC_DFORMAT_RAW_DT << ATON_CONVACC_DFORMAT_RAW_LSB) | \ + (ATON_CONVACC_DFORMAT_OBYTES_DT << ATON_CONVACC_DFORMAT_OBYTES_LSB) | \ + (ATON_CONVACC_DFORMAT_FBYTES_DT << ATON_CONVACC_DFORMAT_FBYTES_LSB) | \ + (ATON_CONVACC_DFORMAT_FSHIFT_DT << ATON_CONVACC_DFORMAT_FSHIFT_LSB) | \ + (ATON_CONVACC_DFORMAT_FROUND_DT << ATON_CONVACC_DFORMAT_FROUND_LSB) | \ + (ATON_CONVACC_DFORMAT_FSAT_DT << ATON_CONVACC_DFORMAT_FSAT_LSB) + + + +/** Description of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_DESC "Data format" + +/** Address of the DFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_DFORMAT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_DFORMAT_OFFSET) + +/** Get the content of the DFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_DFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_DFORMAT_ADDR(UNIT))) + +/** Set the content of the DFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_DFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_DFORMAT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DFORMAT register. + * + * \return the description of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_DESC; +} + + +/** + * Get the offset of the DFORMAT register. + * + * \return the offset of DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_GetOffset(void) +{ + return ATON_CONVACC_DFORMAT_OFFSET; +} + + +/** + * Get the address of the DFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the DFORMAT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of DFORMAT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_DFORMAT_ADDR(instance); +} + + +/** + * Read the content of the DFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the DFORMAT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of DFORMAT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get(uint32_t instance) +{ + return ATON_CONVACC_DFORMAT_GET(instance); +} + + +/** + * Write the content of the DFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the DFORMAT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_DFORMAT_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_DFORMAT_SET(instance, data); +} + + +/* --------------------------------------------------------- INSHIFT field of the DFORMAT register ---------------------------------------------------------- */ + +/** Description of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_DESC "Accumulator data input signed left shift" + +/** Offset of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_LSB 0UL + +/** Size in bits of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_W (6UL) + +/** Mask for retrieving the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_MASK ATON_FIELD_MASK(0UL, 6UL) + +/** Reset value of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_DT 0x8UL + +/** Access rights of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_AC "RW" + +/** Check whether access to the INSHIFT field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_S 0 + +/** Check whether access to the INSHIFT field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_INSHIFT_P 0 + +/** Read the content of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_INSHIFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_INSHIFT_LSB, ATON_CONVACC_DFORMAT_INSHIFT_W) + +/** Modify the content of the INSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_INSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_INSHIFT_LSB, ATON_CONVACC_DFORMAT_INSHIFT_W, DATA) + + +/** + * Get the description of the INSHIFT field of DFORMAT register. + * + * \return the description of the INSHIFT field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_INSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_INSHIFT_DESC; +} + + +/** + * Read the content of the INSHIFT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the INSHIFT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_INSHIFT(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_INSHIFT(reg); +} + + +/** + * Write the content of the INSHIFT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the INSHIFT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_INSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_INSHIFT(reg, data); +} + + +/* --------------------------------------------------------- FRNDMODE field of the DFORMAT register --------------------------------------------------------- */ + +/** Description of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_DESC "Input feature rounding mode. For more information see section: Rounding and Saturation" + +/** Offset of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_LSB 6UL + +/** Size in bits of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_W (2UL) + +/** Mask for retrieving the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_MASK ATON_FIELD_MASK(6UL, 2UL) + +/** Reset value of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_DT 0x0UL + +/** Access rights of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_AC "RW" + +/** Check whether access to the FRNDMODE field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_S 0 + +/** Check whether access to the FRNDMODE field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_FRNDMODE_P 0 + +/** Read the content of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_FRNDMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FRNDMODE_LSB, ATON_CONVACC_DFORMAT_FRNDMODE_W) + +/** Modify the content of the FRNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_FRNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FRNDMODE_LSB, ATON_CONVACC_DFORMAT_FRNDMODE_W, DATA) + + +/** + * Get the description of the FRNDMODE field of DFORMAT register. + * + * \return the description of the FRNDMODE field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_FRNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_FRNDMODE_DESC; +} + + +/** + * Read the content of the FRNDMODE field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the FRNDMODE field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_FRNDMODE(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_FRNDMODE(reg); +} + + +/** + * Write the content of the FRNDMODE field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FRNDMODE field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_FRNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_FRNDMODE(reg, data); +} + + +/* --------------------------------------------------------- OUTSHIFT field of the DFORMAT register --------------------------------------------------------- */ + +/** Description of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_DESC "Result data output signed right shift" + +/** Offset of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_LSB 8UL + +/** Size in bits of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_W (6UL) + +/** Mask for retrieving the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_MASK ATON_FIELD_MASK(8UL, 6UL) + +/** Reset value of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_DT 0x8UL + +/** Access rights of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_AC "RW" + +/** Check whether access to the OUTSHIFT field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_S 0 + +/** Check whether access to the OUTSHIFT field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_OUTSHIFT_P 0 + +/** Read the content of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_OUTSHIFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_OUTSHIFT_LSB, ATON_CONVACC_DFORMAT_OUTSHIFT_W) + +/** Modify the content of the OUTSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_OUTSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_OUTSHIFT_LSB, ATON_CONVACC_DFORMAT_OUTSHIFT_W, DATA) + + +/** + * Get the description of the OUTSHIFT field of DFORMAT register. + * + * \return the description of the OUTSHIFT field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_OUTSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_OUTSHIFT_DESC; +} + + +/** + * Read the content of the OUTSHIFT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the OUTSHIFT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_OUTSHIFT(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_OUTSHIFT(reg); +} + + +/** + * Write the content of the OUTSHIFT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the OUTSHIFT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_OUTSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_OUTSHIFT(reg, data); +} + + +/* --------------------------------------------------------- ORNDMODE field of the DFORMAT register --------------------------------------------------------- */ + +/** Description of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_DESC "Output data rounding mode. For more information see section: Rounding and Saturation" + +/** Offset of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_LSB 14UL + +/** Size in bits of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_W (2UL) + +/** Mask for retrieving the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_DT 0x0UL + +/** Access rights of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_AC "RW" + +/** Check whether access to the ORNDMODE field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_S 0 + +/** Check whether access to the ORNDMODE field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_ORNDMODE_P 0 + +/** Read the content of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_ORNDMODE_LSB, ATON_CONVACC_DFORMAT_ORNDMODE_W) + +/** Modify the content of the ORNDMODE field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_ORNDMODE_LSB, ATON_CONVACC_DFORMAT_ORNDMODE_W, DATA) + + +/** + * Get the description of the ORNDMODE field of DFORMAT register. + * + * \return the description of the ORNDMODE field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_ORNDMODE_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_ORNDMODE_DESC; +} + + +/** + * Read the content of the ORNDMODE field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the ORNDMODE field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_ORNDMODE(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_ORNDMODE(reg); +} + + +/** + * Write the content of the ORNDMODE field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ORNDMODE field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_ORNDMODE(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_ORNDMODE(reg, data); +} + + +/* ---------------------------------------------------------- ROUND field of the DFORMAT register ----------------------------------------------------------- */ + +/** Description of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ROUND_DESC "Output data rounding after right shift" + +/** Offset of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ROUND_LSB 16UL + +/** Size in bits of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ROUND_W (1UL) + +/** Mask for retrieving the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ROUND_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ROUND_DT 0x0UL + +/** Access rights of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_ROUND_AC "RW" + +/** Check whether access to the ROUND field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_ROUND_S 0 + +/** Check whether access to the ROUND field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_ROUND_P 0 + +/** Read the content of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_ROUND_LSB, ATON_CONVACC_DFORMAT_ROUND_W) + +/** Modify the content of the ROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_ROUND_LSB, ATON_CONVACC_DFORMAT_ROUND_W, DATA) + + +/** + * Get the description of the ROUND field of DFORMAT register. + * + * \return the description of the ROUND field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_ROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_ROUND_DESC; +} + + +/** + * Read the content of the ROUND field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the ROUND field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_ROUND(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_ROUND(reg); +} + + +/** + * Write the content of the ROUND field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUND field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_ROUND(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_ROUND(reg, data); +} + + +/* ----------------------------------------------------------- SAT field of the DFORMAT register ------------------------------------------------------------ */ + +/** Description of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SAT_DESC "Output saturation" + +/** Offset of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SAT_LSB 17UL + +/** Size in bits of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SAT_W (1UL) + +/** Mask for retrieving the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SAT_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SAT_DT 0x0UL + +/** Access rights of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SAT_AC "RW" + +/** Check whether access to the SAT field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_SAT_S 0 + +/** Check whether access to the SAT field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_SAT_P 0 + +/** Read the content of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_SAT_LSB, ATON_CONVACC_DFORMAT_SAT_W) + +/** Modify the content of the SAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_SAT_LSB, ATON_CONVACC_DFORMAT_SAT_W, DATA) + + +/** + * Get the description of the SAT field of DFORMAT register. + * + * \return the description of the SAT field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_SAT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_SAT_DESC; +} + + +/** + * Read the content of the SAT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the SAT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_SAT(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_SAT(reg); +} + + +/** + * Write the content of the SAT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SAT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_SAT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_SAT(reg, data); +} + + +/* ----------------------------------------------------------- RAW field of the DFORMAT register ------------------------------------------------------------ */ + +/** Description of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_RAW_DESC "Use RAW file output format" + +/** Offset of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_RAW_LSB 18UL + +/** Size in bits of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_RAW_W (1UL) + +/** Mask for retrieving the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_RAW_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_RAW_DT 0x0UL + +/** Access rights of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_RAW_AC "RW" + +/** Check whether access to the RAW field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_RAW_S 0 + +/** Check whether access to the RAW field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_RAW_P 0 + +/** Read the content of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_RAW(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_RAW_LSB, ATON_CONVACC_DFORMAT_RAW_W) + +/** Modify the content of the RAW field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_RAW(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_RAW_LSB, ATON_CONVACC_DFORMAT_RAW_W, DATA) + + +/** + * Get the description of the RAW field of DFORMAT register. + * + * \return the description of the RAW field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_RAW_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_RAW_DESC; +} + + +/** + * Read the content of the RAW field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the RAW field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_RAW(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_RAW(reg); +} + + +/** + * Write the content of the RAW field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAW field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_RAW(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_RAW(reg, data); +} + + +/* ---------------------------------------------------------- OBYTES field of the DFORMAT register ---------------------------------------------------------- */ + +/** Description of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OBYTES_DESC "Output data width in bytes" + +/** Offset of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OBYTES_LSB 20UL + +/** Size in bits of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OBYTES_W (2UL) + +/** Mask for retrieving the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OBYTES_MASK ATON_FIELD_MASK(20UL, 2UL) + +/** Reset value of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OBYTES_DT 0x3UL + +/** Access rights of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_OBYTES_AC "RW" + +/** Check whether access to the OBYTES field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_OBYTES_S 0 + +/** Check whether access to the OBYTES field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_OBYTES_P 0 + +/** Read the content of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_OBYTES_LSB, ATON_CONVACC_DFORMAT_OBYTES_W) + +/** Modify the content of the OBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_OBYTES_LSB, ATON_CONVACC_DFORMAT_OBYTES_W, DATA) + + +/** + * Get the description of the OBYTES field of DFORMAT register. + * + * \return the description of the OBYTES field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_OBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_OBYTES_DESC; +} + + +/** + * Read the content of the OBYTES field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the OBYTES field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_OBYTES(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_OBYTES(reg); +} + + +/** + * Write the content of the OBYTES field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the OBYTES field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_OBYTES(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_OBYTES(reg, data); +} + + +/* ---------------------------------------------------------- FBYTES field of the DFORMAT register ---------------------------------------------------------- */ + +/** Description of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FBYTES_DESC "Input data width in bytes" + +/** Offset of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FBYTES_LSB 22UL + +/** Size in bits of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FBYTES_W (2UL) + +/** Mask for retrieving the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FBYTES_MASK ATON_FIELD_MASK(22UL, 2UL) + +/** Reset value of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FBYTES_DT 0x2UL + +/** Access rights of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FBYTES_AC "RW" + +/** Check whether access to the FBYTES field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_FBYTES_S 0 + +/** Check whether access to the FBYTES field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_FBYTES_P 0 + +/** Read the content of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_FBYTES(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FBYTES_LSB, ATON_CONVACC_DFORMAT_FBYTES_W) + +/** Modify the content of the FBYTES field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_FBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FBYTES_LSB, ATON_CONVACC_DFORMAT_FBYTES_W, DATA) + + +/** + * Get the description of the FBYTES field of DFORMAT register. + * + * \return the description of the FBYTES field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_FBYTES_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_FBYTES_DESC; +} + + +/** + * Read the content of the FBYTES field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the FBYTES field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_FBYTES(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_FBYTES(reg); +} + + +/** + * Write the content of the FBYTES field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the FBYTES field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_FBYTES(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_FBYTES(reg, data); +} + + +/* ---------------------------------------------------------- FSHIFT field of the DFORMAT register ---------------------------------------------------------- */ + +/** Description of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_DESC "Input feature data shift. Range 39:0. No shift 16" + +/** Offset of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_LSB 24UL + +/** Size in bits of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_W (6UL) + +/** Mask for retrieving the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_MASK ATON_FIELD_MASK(24UL, 6UL) + +/** Reset value of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_DT 0x10UL + +/** Access rights of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_AC "RW" + +/** Check whether access to the FSHIFT field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_S 0 + +/** Check whether access to the FSHIFT field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_FSHIFT_P 0 + +/** Read the content of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_FSHIFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FSHIFT_LSB, ATON_CONVACC_DFORMAT_FSHIFT_W) + +/** Modify the content of the FSHIFT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_FSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FSHIFT_LSB, ATON_CONVACC_DFORMAT_FSHIFT_W, DATA) + + +/** + * Get the description of the FSHIFT field of DFORMAT register. + * + * \return the description of the FSHIFT field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_FSHIFT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_FSHIFT_DESC; +} + + +/** + * Read the content of the FSHIFT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the FSHIFT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_FSHIFT(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_FSHIFT(reg); +} + + +/** + * Write the content of the FSHIFT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 6-bit value that must be written to the field + * + * \return the new content of the FSHIFT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_FSHIFT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_FSHIFT(reg, data); +} + + +/* ---------------------------------------------------------- FROUND field of the DFORMAT register ---------------------------------------------------------- */ + +/** Description of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FROUND_DESC "Input feature data rounding" + +/** Offset of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FROUND_LSB 30UL + +/** Size in bits of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FROUND_W (1UL) + +/** Mask for retrieving the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FROUND_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FROUND_DT 0x0UL + +/** Access rights of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FROUND_AC "RW" + +/** Check whether access to the FROUND field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_FROUND_S 0 + +/** Check whether access to the FROUND field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_FROUND_P 0 + +/** Read the content of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_FROUND(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FROUND_LSB, ATON_CONVACC_DFORMAT_FROUND_W) + +/** Modify the content of the FROUND field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_FROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FROUND_LSB, ATON_CONVACC_DFORMAT_FROUND_W, DATA) + + +/** + * Get the description of the FROUND field of DFORMAT register. + * + * \return the description of the FROUND field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_FROUND_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_FROUND_DESC; +} + + +/** + * Read the content of the FROUND field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the FROUND field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_FROUND(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_FROUND(reg); +} + + +/** + * Write the content of the FROUND field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FROUND field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_FROUND(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_FROUND(reg, data); +} + + +/* ----------------------------------------------------------- FSAT field of the DFORMAT register ----------------------------------------------------------- */ + +/** Description of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSAT_DESC "Input feature data saturation" + +/** Offset of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSAT_LSB 31UL + +/** Size in bits of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSAT_W (1UL) + +/** Mask for retrieving the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSAT_MASK ATON_FIELD_MASK(31UL, 1UL) + +/** Reset value of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSAT_DT 0x0UL + +/** Access rights of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_FSAT_AC "RW" + +/** Check whether access to the FSAT field of the DFORMAT register is secured or not. */ +#define ATON_CONVACC_DFORMAT_FSAT_S 0 + +/** Check whether access to the FSAT field of the DFORMAT register is privileged or not. */ +#define ATON_CONVACC_DFORMAT_FSAT_P 0 + +/** Read the content of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_GET_FSAT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FSAT_LSB, ATON_CONVACC_DFORMAT_FSAT_W) + +/** Modify the content of the FSAT field of the DFORMAT register. */ +#define ATON_CONVACC_DFORMAT_SET_FSAT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FSAT_LSB, ATON_CONVACC_DFORMAT_FSAT_W, DATA) + + +/** + * Get the description of the FSAT field of DFORMAT register. + * + * \return the description of the FSAT field of DFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_DFORMAT_FSAT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_DFORMAT_FSAT_DESC; +} + + +/** + * Read the content of the FSAT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the FSAT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Get_FSAT(uint32_t reg) +{ + return ATON_CONVACC_DFORMAT_GET_FSAT(reg); +} + + +/** + * Write the content of the FSAT field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the FSAT field belonging to DFORMAT register + */ + +static inline uint32_t ATON_CONVACC_DFORMAT_Set_FSAT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_DFORMAT_SET_FSAT(reg, data); +} + + +/* ****************************************************** FFORMAT register of one of the CONVACC Units ****************************************************** */ + +/** Offset of the FFORMAT register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_FFORMAT_OFFSET 0x14UL + +/** Reset value of the FFORMAT register of the CONVACC Unit. */ +#define ATON_CONVACC_FFORMAT_DT \ + (ATON_CONVACC_FFORMAT_WIDTH_DT << ATON_CONVACC_FFORMAT_WIDTH_LSB) | \ + (ATON_CONVACC_FFORMAT_HEIGHT_DT << ATON_CONVACC_FFORMAT_HEIGHT_LSB) + + + +/** Description of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_DESC "Feature Data input dimensions" + +/** Address of the FFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_FFORMAT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FFORMAT_OFFSET) + +/** Get the content of the FFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_FFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FFORMAT_ADDR(UNIT))) + +/** Set the content of the FFORMAT register of one of the CONVACC Units. */ +#define ATON_CONVACC_FFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FFORMAT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FFORMAT register. + * + * \return the description of FFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_FFORMAT_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FFORMAT_DESC; +} + + +/** + * Get the offset of the FFORMAT register. + * + * \return the offset of FFORMAT register + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_GetOffset(void) +{ + return ATON_CONVACC_FFORMAT_OFFSET; +} + + +/** + * Get the address of the FFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FFORMAT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of FFORMAT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_FFORMAT_ADDR(instance); +} + + +/** + * Read the content of the FFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FFORMAT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of FFORMAT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_Get(uint32_t instance) +{ + return ATON_CONVACC_FFORMAT_GET(instance); +} + + +/** + * Write the content of the FFORMAT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FFORMAT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_FFORMAT_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_FFORMAT_SET(instance, data); +} + + +/* ---------------------------------------------------------- WIDTH field of the FFORMAT register ----------------------------------------------------------- */ + +/** Description of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_WIDTH_DESC "Feature data width (automatically updated for raster scan data streams)" + +/** Offset of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_WIDTH_LSB 0UL + +/** Size in bits of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_WIDTH_W (16UL) + +/** Mask for retrieving the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_WIDTH_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_WIDTH_DT 0xffffUL + +/** Access rights of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_WIDTH_AC "RW" + +/** Check whether access to the WIDTH field of the FFORMAT register is secured or not. */ +#define ATON_CONVACC_FFORMAT_WIDTH_S 0 + +/** Check whether access to the WIDTH field of the FFORMAT register is privileged or not. */ +#define ATON_CONVACC_FFORMAT_WIDTH_P 0 + +/** Read the content of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_GET_WIDTH(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FFORMAT_WIDTH_LSB, ATON_CONVACC_FFORMAT_WIDTH_W) + +/** Modify the content of the WIDTH field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_SET_WIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FFORMAT_WIDTH_LSB, ATON_CONVACC_FFORMAT_WIDTH_W, DATA) + + +/** + * Get the description of the WIDTH field of FFORMAT register. + * + * \return the description of the WIDTH field of FFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_FFORMAT_WIDTH_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FFORMAT_WIDTH_DESC; +} + + +/** + * Read the content of the WIDTH field of the FFORMAT register. + * + * \param[in] reg is the value of the FFORMAT register + * + * \return the content of the WIDTH field belonging to FFORMAT register + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_Get_WIDTH(uint32_t reg) +{ + return ATON_CONVACC_FFORMAT_GET_WIDTH(reg); +} + + +/** + * Write the content of the WIDTH field of the FFORMAT register. + * + * \param[in] reg is the value of the FFORMAT register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the WIDTH field belonging to FFORMAT register + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_Set_WIDTH(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FFORMAT_SET_WIDTH(reg, data); +} + + +/* ---------------------------------------------------------- HEIGHT field of the FFORMAT register ---------------------------------------------------------- */ + +/** Description of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_DESC "Feature data height (automatically updated for raster scan data streams)" + +/** Offset of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_LSB 16UL + +/** Size in bits of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_W (16UL) + +/** Mask for retrieving the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_DT 0xffffUL + +/** Access rights of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_AC "RW" + +/** Check whether access to the HEIGHT field of the FFORMAT register is secured or not. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_S 0 + +/** Check whether access to the HEIGHT field of the FFORMAT register is privileged or not. */ +#define ATON_CONVACC_FFORMAT_HEIGHT_P 0 + +/** Read the content of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_GET_HEIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FFORMAT_HEIGHT_LSB, ATON_CONVACC_FFORMAT_HEIGHT_W) + +/** Modify the content of the HEIGHT field of the FFORMAT register. */ +#define ATON_CONVACC_FFORMAT_SET_HEIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FFORMAT_HEIGHT_LSB, ATON_CONVACC_FFORMAT_HEIGHT_W, DATA) + + +/** + * Get the description of the HEIGHT field of FFORMAT register. + * + * \return the description of the HEIGHT field of FFORMAT register + */ + +static inline const int8_t *ATON_CONVACC_FFORMAT_HEIGHT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FFORMAT_HEIGHT_DESC; +} + + +/** + * Read the content of the HEIGHT field of the FFORMAT register. + * + * \param[in] reg is the value of the FFORMAT register + * + * \return the content of the HEIGHT field belonging to FFORMAT register + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_Get_HEIGHT(uint32_t reg) +{ + return ATON_CONVACC_FFORMAT_GET_HEIGHT(reg); +} + + +/** + * Write the content of the HEIGHT field of the FFORMAT register. + * + * \param[in] reg is the value of the FFORMAT register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the HEIGHT field belonging to FFORMAT register + */ + +static inline uint32_t ATON_CONVACC_FFORMAT_Set_HEIGHT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FFORMAT_SET_HEIGHT(reg, data); +} + + +/* ****************************************************** FHCROP register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the FHCROP register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_FHCROP_OFFSET 0x18UL + +/** Reset value of the FHCROP register of the CONVACC Unit. */ +#define ATON_CONVACC_FHCROP_DT \ + (ATON_CONVACC_FHCROP_LEFT_DT << ATON_CONVACC_FHCROP_LEFT_LSB) | \ + (ATON_CONVACC_FHCROP_RIGHT_DT << ATON_CONVACC_FHCROP_RIGHT_LSB) + + + +/** Description of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_DESC "Horizontal feature data cropping" + +/** Address of the FHCROP register of one of the CONVACC Units. */ +#define ATON_CONVACC_FHCROP_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FHCROP_OFFSET) + +/** Get the content of the FHCROP register of one of the CONVACC Units. */ +#define ATON_CONVACC_FHCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FHCROP_ADDR(UNIT))) + +/** Set the content of the FHCROP register of one of the CONVACC Units. */ +#define ATON_CONVACC_FHCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FHCROP_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FHCROP register. + * + * \return the description of FHCROP register + */ + +static inline const int8_t *ATON_CONVACC_FHCROP_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FHCROP_DESC; +} + + +/** + * Get the offset of the FHCROP register. + * + * \return the offset of FHCROP register + */ + +static inline uint32_t ATON_CONVACC_FHCROP_GetOffset(void) +{ + return ATON_CONVACC_FHCROP_OFFSET; +} + + +/** + * Get the address of the FHCROP register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FHCROP register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of FHCROP register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FHCROP_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_FHCROP_ADDR(instance); +} + + +/** + * Read the content of the FHCROP register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FHCROP register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of FHCROP register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FHCROP_Get(uint32_t instance) +{ + return ATON_CONVACC_FHCROP_GET(instance); +} + + +/** + * Write the content of the FHCROP register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FHCROP register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_FHCROP_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_FHCROP_SET(instance, data); +} + + +/* ----------------------------------------------------------- LEFT field of the FHCROP register ------------------------------------------------------------ */ + +/** Description of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_LEFT_DESC "Left feature data boundary" + +/** Offset of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_LEFT_LSB 0UL + +/** Size in bits of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_LEFT_W (16UL) + +/** Mask for retrieving the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_LEFT_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_LEFT_DT 0x0UL + +/** Access rights of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_LEFT_AC "RW" + +/** Check whether access to the LEFT field of the FHCROP register is secured or not. */ +#define ATON_CONVACC_FHCROP_LEFT_S 0 + +/** Check whether access to the LEFT field of the FHCROP register is privileged or not. */ +#define ATON_CONVACC_FHCROP_LEFT_P 0 + +/** Read the content of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_GET_LEFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FHCROP_LEFT_LSB, ATON_CONVACC_FHCROP_LEFT_W) + +/** Modify the content of the LEFT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_SET_LEFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FHCROP_LEFT_LSB, ATON_CONVACC_FHCROP_LEFT_W, DATA) + + +/** + * Get the description of the LEFT field of FHCROP register. + * + * \return the description of the LEFT field of FHCROP register + */ + +static inline const int8_t *ATON_CONVACC_FHCROP_LEFT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FHCROP_LEFT_DESC; +} + + +/** + * Read the content of the LEFT field of the FHCROP register. + * + * \param[in] reg is the value of the FHCROP register + * + * \return the content of the LEFT field belonging to FHCROP register + */ + +static inline uint32_t ATON_CONVACC_FHCROP_Get_LEFT(uint32_t reg) +{ + return ATON_CONVACC_FHCROP_GET_LEFT(reg); +} + + +/** + * Write the content of the LEFT field of the FHCROP register. + * + * \param[in] reg is the value of the FHCROP register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the LEFT field belonging to FHCROP register + */ + +static inline uint32_t ATON_CONVACC_FHCROP_Set_LEFT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FHCROP_SET_LEFT(reg, data); +} + + +/* ----------------------------------------------------------- RIGHT field of the FHCROP register ----------------------------------------------------------- */ + +/** Description of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_RIGHT_DESC "Right feature data boundary" + +/** Offset of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_RIGHT_LSB 16UL + +/** Size in bits of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_RIGHT_W (16UL) + +/** Mask for retrieving the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_RIGHT_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_RIGHT_DT 0xffffUL + +/** Access rights of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_RIGHT_AC "RW" + +/** Check whether access to the RIGHT field of the FHCROP register is secured or not. */ +#define ATON_CONVACC_FHCROP_RIGHT_S 0 + +/** Check whether access to the RIGHT field of the FHCROP register is privileged or not. */ +#define ATON_CONVACC_FHCROP_RIGHT_P 0 + +/** Read the content of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_GET_RIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FHCROP_RIGHT_LSB, ATON_CONVACC_FHCROP_RIGHT_W) + +/** Modify the content of the RIGHT field of the FHCROP register. */ +#define ATON_CONVACC_FHCROP_SET_RIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FHCROP_RIGHT_LSB, ATON_CONVACC_FHCROP_RIGHT_W, DATA) + + +/** + * Get the description of the RIGHT field of FHCROP register. + * + * \return the description of the RIGHT field of FHCROP register + */ + +static inline const int8_t *ATON_CONVACC_FHCROP_RIGHT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FHCROP_RIGHT_DESC; +} + + +/** + * Read the content of the RIGHT field of the FHCROP register. + * + * \param[in] reg is the value of the FHCROP register + * + * \return the content of the RIGHT field belonging to FHCROP register + */ + +static inline uint32_t ATON_CONVACC_FHCROP_Get_RIGHT(uint32_t reg) +{ + return ATON_CONVACC_FHCROP_GET_RIGHT(reg); +} + + +/** + * Write the content of the RIGHT field of the FHCROP register. + * + * \param[in] reg is the value of the FHCROP register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the RIGHT field belonging to FHCROP register + */ + +static inline uint32_t ATON_CONVACC_FHCROP_Set_RIGHT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FHCROP_SET_RIGHT(reg, data); +} + + +/* ****************************************************** FVCROP register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the FVCROP register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_FVCROP_OFFSET 0x1cUL + +/** Reset value of the FVCROP register of the CONVACC Unit. */ +#define ATON_CONVACC_FVCROP_DT \ + (ATON_CONVACC_FVCROP_TOP_DT << ATON_CONVACC_FVCROP_TOP_LSB) | \ + (ATON_CONVACC_FVCROP_BOTTOM_DT << ATON_CONVACC_FVCROP_BOTTOM_LSB) + + + +/** Description of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_DESC "Vertical feature data cropping" + +/** Address of the FVCROP register of one of the CONVACC Units. */ +#define ATON_CONVACC_FVCROP_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FVCROP_OFFSET) + +/** Get the content of the FVCROP register of one of the CONVACC Units. */ +#define ATON_CONVACC_FVCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FVCROP_ADDR(UNIT))) + +/** Set the content of the FVCROP register of one of the CONVACC Units. */ +#define ATON_CONVACC_FVCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FVCROP_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FVCROP register. + * + * \return the description of FVCROP register + */ + +static inline const int8_t *ATON_CONVACC_FVCROP_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FVCROP_DESC; +} + + +/** + * Get the offset of the FVCROP register. + * + * \return the offset of FVCROP register + */ + +static inline uint32_t ATON_CONVACC_FVCROP_GetOffset(void) +{ + return ATON_CONVACC_FVCROP_OFFSET; +} + + +/** + * Get the address of the FVCROP register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FVCROP register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of FVCROP register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FVCROP_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_FVCROP_ADDR(instance); +} + + +/** + * Read the content of the FVCROP register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FVCROP register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of FVCROP register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FVCROP_Get(uint32_t instance) +{ + return ATON_CONVACC_FVCROP_GET(instance); +} + + +/** + * Write the content of the FVCROP register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FVCROP register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_FVCROP_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_FVCROP_SET(instance, data); +} + + +/* ------------------------------------------------------------ TOP field of the FVCROP register ------------------------------------------------------------ */ + +/** Description of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_TOP_DESC "Top feature data boundary" + +/** Offset of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_TOP_LSB 0UL + +/** Size in bits of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_TOP_W (16UL) + +/** Mask for retrieving the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_TOP_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_TOP_DT 0x0UL + +/** Access rights of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_TOP_AC "RW" + +/** Check whether access to the TOP field of the FVCROP register is secured or not. */ +#define ATON_CONVACC_FVCROP_TOP_S 0 + +/** Check whether access to the TOP field of the FVCROP register is privileged or not. */ +#define ATON_CONVACC_FVCROP_TOP_P 0 + +/** Read the content of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_GET_TOP(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FVCROP_TOP_LSB, ATON_CONVACC_FVCROP_TOP_W) + +/** Modify the content of the TOP field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_SET_TOP(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FVCROP_TOP_LSB, ATON_CONVACC_FVCROP_TOP_W, DATA) + + +/** + * Get the description of the TOP field of FVCROP register. + * + * \return the description of the TOP field of FVCROP register + */ + +static inline const int8_t *ATON_CONVACC_FVCROP_TOP_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FVCROP_TOP_DESC; +} + + +/** + * Read the content of the TOP field of the FVCROP register. + * + * \param[in] reg is the value of the FVCROP register + * + * \return the content of the TOP field belonging to FVCROP register + */ + +static inline uint32_t ATON_CONVACC_FVCROP_Get_TOP(uint32_t reg) +{ + return ATON_CONVACC_FVCROP_GET_TOP(reg); +} + + +/** + * Write the content of the TOP field of the FVCROP register. + * + * \param[in] reg is the value of the FVCROP register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the TOP field belonging to FVCROP register + */ + +static inline uint32_t ATON_CONVACC_FVCROP_Set_TOP(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FVCROP_SET_TOP(reg, data); +} + + +/* ---------------------------------------------------------- BOTTOM field of the FVCROP register ----------------------------------------------------------- */ + +/** Description of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_BOTTOM_DESC "Bottom feature data boundary" + +/** Offset of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_BOTTOM_LSB 16UL + +/** Size in bits of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_BOTTOM_W (16UL) + +/** Mask for retrieving the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_BOTTOM_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_BOTTOM_DT 0xffffUL + +/** Access rights of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_BOTTOM_AC "RW" + +/** Check whether access to the BOTTOM field of the FVCROP register is secured or not. */ +#define ATON_CONVACC_FVCROP_BOTTOM_S 0 + +/** Check whether access to the BOTTOM field of the FVCROP register is privileged or not. */ +#define ATON_CONVACC_FVCROP_BOTTOM_P 0 + +/** Read the content of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_GET_BOTTOM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FVCROP_BOTTOM_LSB, ATON_CONVACC_FVCROP_BOTTOM_W) + +/** Modify the content of the BOTTOM field of the FVCROP register. */ +#define ATON_CONVACC_FVCROP_SET_BOTTOM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FVCROP_BOTTOM_LSB, ATON_CONVACC_FVCROP_BOTTOM_W, DATA) + + +/** + * Get the description of the BOTTOM field of FVCROP register. + * + * \return the description of the BOTTOM field of FVCROP register + */ + +static inline const int8_t *ATON_CONVACC_FVCROP_BOTTOM_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FVCROP_BOTTOM_DESC; +} + + +/** + * Read the content of the BOTTOM field of the FVCROP register. + * + * \param[in] reg is the value of the FVCROP register + * + * \return the content of the BOTTOM field belonging to FVCROP register + */ + +static inline uint32_t ATON_CONVACC_FVCROP_Get_BOTTOM(uint32_t reg) +{ + return ATON_CONVACC_FVCROP_GET_BOTTOM(reg); +} + + +/** + * Write the content of the BOTTOM field of the FVCROP register. + * + * \param[in] reg is the value of the FVCROP register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the BOTTOM field belonging to FVCROP register + */ + +static inline uint32_t ATON_CONVACC_FVCROP_Set_BOTTOM(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FVCROP_SET_BOTTOM(reg, data); +} + + +/* ******************************************************* KFILT register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the KFILT register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_KFILT_OFFSET 0x20UL + +/** Reset value of the KFILT register of the CONVACC Unit. */ +#define ATON_CONVACC_KFILT_DT \ + (ATON_CONVACC_KFILT_TOT_DT << ATON_CONVACC_KFILT_TOT_LSB) | \ + (ATON_CONVACC_KFILT_FIRST_DT << ATON_CONVACC_KFILT_FIRST_LSB) | \ + (ATON_CONVACC_KFILT_LAST_DT << ATON_CONVACC_KFILT_LAST_LSB) | \ + (ATON_CONVACC_KFILT_IDX_DT << ATON_CONVACC_KFILT_IDX_LSB) + + + +/** Description of the KFILT register. */ +#define ATON_CONVACC_KFILT_DESC "Kernel filter" + +/** Address of the KFILT register of one of the CONVACC Units. */ +#define ATON_CONVACC_KFILT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_KFILT_OFFSET) + +/** Get the content of the KFILT register of one of the CONVACC Units. */ +#define ATON_CONVACC_KFILT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFILT_ADDR(UNIT))) + +/** Set the content of the KFILT register of one of the CONVACC Units. */ +#define ATON_CONVACC_KFILT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFILT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of KFILT register. + * + * \return the description of KFILT register + */ + +static inline const int8_t *ATON_CONVACC_KFILT_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFILT_DESC; +} + + +/** + * Get the offset of the KFILT register. + * + * \return the offset of KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_GetOffset(void) +{ + return ATON_CONVACC_KFILT_OFFSET; +} + + +/** + * Get the address of the KFILT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFILT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of KFILT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_KFILT_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_KFILT_ADDR(instance); +} + + +/** + * Read the content of the KFILT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFILT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of KFILT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_KFILT_Get(uint32_t instance) +{ + return ATON_CONVACC_KFILT_GET(instance); +} + + +/** + * Write the content of the KFILT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFILT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_KFILT_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_KFILT_SET(instance, data); +} + + +/* ------------------------------------------------------------ TOT field of the KFILT register ------------------------------------------------------------- */ + +/** Description of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_TOT_DESC "Total number of kernels" + +/** Offset of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_TOT_LSB 0UL + +/** Size in bits of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_TOT_W (8UL) + +/** Mask for retrieving the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_TOT_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_TOT_DT 0x1UL + +/** Access rights of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_TOT_AC "RW" + +/** Check whether access to the TOT field of the KFILT register is secured or not. */ +#define ATON_CONVACC_KFILT_TOT_S 0 + +/** Check whether access to the TOT field of the KFILT register is privileged or not. */ +#define ATON_CONVACC_KFILT_TOT_P 0 + +/** Read the content of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_GET_TOT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_TOT_LSB, ATON_CONVACC_KFILT_TOT_W) + +/** Modify the content of the TOT field of the KFILT register. */ +#define ATON_CONVACC_KFILT_SET_TOT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFILT_TOT_LSB, ATON_CONVACC_KFILT_TOT_W, DATA) + + +/** + * Get the description of the TOT field of KFILT register. + * + * \return the description of the TOT field of KFILT register + */ + +static inline const int8_t *ATON_CONVACC_KFILT_TOT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFILT_TOT_DESC; +} + + +/** + * Read the content of the TOT field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * + * \return the content of the TOT field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Get_TOT(uint32_t reg) +{ + return ATON_CONVACC_KFILT_GET_TOT(reg); +} + + +/** + * Write the content of the TOT field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the TOT field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Set_TOT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFILT_SET_TOT(reg, data); +} + + +/* ----------------------------------------------------------- FIRST field of the KFILT register ------------------------------------------------------------ */ + +/** Description of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_FIRST_DESC "First kernel" + +/** Offset of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_FIRST_LSB 8UL + +/** Size in bits of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_FIRST_W (8UL) + +/** Mask for retrieving the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_FIRST_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_FIRST_DT 0x0UL + +/** Access rights of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_FIRST_AC "RW" + +/** Check whether access to the FIRST field of the KFILT register is secured or not. */ +#define ATON_CONVACC_KFILT_FIRST_S 0 + +/** Check whether access to the FIRST field of the KFILT register is privileged or not. */ +#define ATON_CONVACC_KFILT_FIRST_P 0 + +/** Read the content of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_GET_FIRST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_FIRST_LSB, ATON_CONVACC_KFILT_FIRST_W) + +/** Modify the content of the FIRST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_SET_FIRST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFILT_FIRST_LSB, ATON_CONVACC_KFILT_FIRST_W, DATA) + + +/** + * Get the description of the FIRST field of KFILT register. + * + * \return the description of the FIRST field of KFILT register + */ + +static inline const int8_t *ATON_CONVACC_KFILT_FIRST_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFILT_FIRST_DESC; +} + + +/** + * Read the content of the FIRST field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * + * \return the content of the FIRST field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Get_FIRST(uint32_t reg) +{ + return ATON_CONVACC_KFILT_GET_FIRST(reg); +} + + +/** + * Write the content of the FIRST field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FIRST field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Set_FIRST(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFILT_SET_FIRST(reg, data); +} + + +/* ------------------------------------------------------------ LAST field of the KFILT register ------------------------------------------------------------ */ + +/** Description of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_LAST_DESC "Last kernel" + +/** Offset of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_LAST_LSB 16UL + +/** Size in bits of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_LAST_W (8UL) + +/** Mask for retrieving the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_LAST_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_LAST_DT 0x0UL + +/** Access rights of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_LAST_AC "RW" + +/** Check whether access to the LAST field of the KFILT register is secured or not. */ +#define ATON_CONVACC_KFILT_LAST_S 0 + +/** Check whether access to the LAST field of the KFILT register is privileged or not. */ +#define ATON_CONVACC_KFILT_LAST_P 0 + +/** Read the content of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_GET_LAST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_LAST_LSB, ATON_CONVACC_KFILT_LAST_W) + +/** Modify the content of the LAST field of the KFILT register. */ +#define ATON_CONVACC_KFILT_SET_LAST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFILT_LAST_LSB, ATON_CONVACC_KFILT_LAST_W, DATA) + + +/** + * Get the description of the LAST field of KFILT register. + * + * \return the description of the LAST field of KFILT register + */ + +static inline const int8_t *ATON_CONVACC_KFILT_LAST_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFILT_LAST_DESC; +} + + +/** + * Read the content of the LAST field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * + * \return the content of the LAST field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Get_LAST(uint32_t reg) +{ + return ATON_CONVACC_KFILT_GET_LAST(reg); +} + + +/** + * Write the content of the LAST field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the LAST field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Set_LAST(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_KFILT_SET_LAST(reg, data); +} + + +/* ------------------------------------------------------------ IDX field of the KFILT register ------------------------------------------------------------- */ + +/** Description of the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_IDX_DESC "Current kernel" + +/** Offset of the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_IDX_LSB 24UL + +/** Size in bits of the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_IDX_W (8UL) + +/** Mask for retrieving the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_IDX_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_IDX_DT 0x0UL + +/** Access rights of the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_IDX_AC "R" + +/** Check whether access to the IDX field of the KFILT register is secured or not. */ +#define ATON_CONVACC_KFILT_IDX_S 0 + +/** Check whether access to the IDX field of the KFILT register is privileged or not. */ +#define ATON_CONVACC_KFILT_IDX_P 0 + +/** Read the content of the IDX field of the KFILT register. */ +#define ATON_CONVACC_KFILT_GET_IDX(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_IDX_LSB, ATON_CONVACC_KFILT_IDX_W) + + +/** + * Get the description of the IDX field of KFILT register. + * + * \return the description of the IDX field of KFILT register + */ + +static inline const int8_t *ATON_CONVACC_KFILT_IDX_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_KFILT_IDX_DESC; +} + + +/** + * Read the content of the IDX field of the KFILT register. + * + * \param[in] reg is the value of the KFILT register + * + * \return the content of the IDX field belonging to KFILT register + */ + +static inline uint32_t ATON_CONVACC_KFILT_Get_IDX(uint32_t reg) +{ + return ATON_CONVACC_KFILT_GET_IDX(reg); +} + + +/* ******************************************************* AFILT register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the AFILT register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_AFILT_OFFSET 0x24UL + +/** Reset value of the AFILT register of the CONVACC Unit. */ +#define ATON_CONVACC_AFILT_DT \ + (ATON_CONVACC_AFILT_TOT_DT << ATON_CONVACC_AFILT_TOT_LSB) | \ + (ATON_CONVACC_AFILT_FIRST_DT << ATON_CONVACC_AFILT_FIRST_LSB) | \ + (ATON_CONVACC_AFILT_LAST_DT << ATON_CONVACC_AFILT_LAST_LSB) | \ + (ATON_CONVACC_AFILT_IDX_DT << ATON_CONVACC_AFILT_IDX_LSB) + + + +/** Description of the AFILT register. */ +#define ATON_CONVACC_AFILT_DESC "Accumulator filter" + +/** Address of the AFILT register of one of the CONVACC Units. */ +#define ATON_CONVACC_AFILT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_AFILT_OFFSET) + +/** Get the content of the AFILT register of one of the CONVACC Units. */ +#define ATON_CONVACC_AFILT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_AFILT_ADDR(UNIT))) + +/** Set the content of the AFILT register of one of the CONVACC Units. */ +#define ATON_CONVACC_AFILT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_AFILT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of AFILT register. + * + * \return the description of AFILT register + */ + +static inline const int8_t *ATON_CONVACC_AFILT_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_AFILT_DESC; +} + + +/** + * Get the offset of the AFILT register. + * + * \return the offset of AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_GetOffset(void) +{ + return ATON_CONVACC_AFILT_OFFSET; +} + + +/** + * Get the address of the AFILT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the AFILT register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of AFILT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_AFILT_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_AFILT_ADDR(instance); +} + + +/** + * Read the content of the AFILT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the AFILT register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of AFILT register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_AFILT_Get(uint32_t instance) +{ + return ATON_CONVACC_AFILT_GET(instance); +} + + +/** + * Write the content of the AFILT register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the AFILT register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_AFILT_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_AFILT_SET(instance, data); +} + + +/* ------------------------------------------------------------ TOT field of the AFILT register ------------------------------------------------------------- */ + +/** Description of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_TOT_DESC "Total number of accumulation tensors" + +/** Offset of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_TOT_LSB 0UL + +/** Size in bits of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_TOT_W (8UL) + +/** Mask for retrieving the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_TOT_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_TOT_DT 0x1UL + +/** Access rights of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_TOT_AC "RW" + +/** Check whether access to the TOT field of the AFILT register is secured or not. */ +#define ATON_CONVACC_AFILT_TOT_S 0 + +/** Check whether access to the TOT field of the AFILT register is privileged or not. */ +#define ATON_CONVACC_AFILT_TOT_P 0 + +/** Read the content of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_GET_TOT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_TOT_LSB, ATON_CONVACC_AFILT_TOT_W) + +/** Modify the content of the TOT field of the AFILT register. */ +#define ATON_CONVACC_AFILT_SET_TOT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_AFILT_TOT_LSB, ATON_CONVACC_AFILT_TOT_W, DATA) + + +/** + * Get the description of the TOT field of AFILT register. + * + * \return the description of the TOT field of AFILT register + */ + +static inline const int8_t *ATON_CONVACC_AFILT_TOT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_AFILT_TOT_DESC; +} + + +/** + * Read the content of the TOT field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * + * \return the content of the TOT field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Get_TOT(uint32_t reg) +{ + return ATON_CONVACC_AFILT_GET_TOT(reg); +} + + +/** + * Write the content of the TOT field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the TOT field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Set_TOT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_AFILT_SET_TOT(reg, data); +} + + +/* ----------------------------------------------------------- FIRST field of the AFILT register ------------------------------------------------------------ */ + +/** Description of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_FIRST_DESC "First accumulation tensor" + +/** Offset of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_FIRST_LSB 8UL + +/** Size in bits of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_FIRST_W (8UL) + +/** Mask for retrieving the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_FIRST_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_FIRST_DT 0x0UL + +/** Access rights of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_FIRST_AC "RW" + +/** Check whether access to the FIRST field of the AFILT register is secured or not. */ +#define ATON_CONVACC_AFILT_FIRST_S 0 + +/** Check whether access to the FIRST field of the AFILT register is privileged or not. */ +#define ATON_CONVACC_AFILT_FIRST_P 0 + +/** Read the content of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_GET_FIRST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_FIRST_LSB, ATON_CONVACC_AFILT_FIRST_W) + +/** Modify the content of the FIRST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_SET_FIRST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_AFILT_FIRST_LSB, ATON_CONVACC_AFILT_FIRST_W, DATA) + + +/** + * Get the description of the FIRST field of AFILT register. + * + * \return the description of the FIRST field of AFILT register + */ + +static inline const int8_t *ATON_CONVACC_AFILT_FIRST_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_AFILT_FIRST_DESC; +} + + +/** + * Read the content of the FIRST field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * + * \return the content of the FIRST field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Get_FIRST(uint32_t reg) +{ + return ATON_CONVACC_AFILT_GET_FIRST(reg); +} + + +/** + * Write the content of the FIRST field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the FIRST field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Set_FIRST(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_AFILT_SET_FIRST(reg, data); +} + + +/* ------------------------------------------------------------ LAST field of the AFILT register ------------------------------------------------------------ */ + +/** Description of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_LAST_DESC "Last accumulation tensor" + +/** Offset of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_LAST_LSB 16UL + +/** Size in bits of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_LAST_W (8UL) + +/** Mask for retrieving the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_LAST_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_LAST_DT 0x0UL + +/** Access rights of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_LAST_AC "RW" + +/** Check whether access to the LAST field of the AFILT register is secured or not. */ +#define ATON_CONVACC_AFILT_LAST_S 0 + +/** Check whether access to the LAST field of the AFILT register is privileged or not. */ +#define ATON_CONVACC_AFILT_LAST_P 0 + +/** Read the content of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_GET_LAST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_LAST_LSB, ATON_CONVACC_AFILT_LAST_W) + +/** Modify the content of the LAST field of the AFILT register. */ +#define ATON_CONVACC_AFILT_SET_LAST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_AFILT_LAST_LSB, ATON_CONVACC_AFILT_LAST_W, DATA) + + +/** + * Get the description of the LAST field of AFILT register. + * + * \return the description of the LAST field of AFILT register + */ + +static inline const int8_t *ATON_CONVACC_AFILT_LAST_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_AFILT_LAST_DESC; +} + + +/** + * Read the content of the LAST field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * + * \return the content of the LAST field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Get_LAST(uint32_t reg) +{ + return ATON_CONVACC_AFILT_GET_LAST(reg); +} + + +/** + * Write the content of the LAST field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the LAST field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Set_LAST(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_AFILT_SET_LAST(reg, data); +} + + +/* ------------------------------------------------------------ IDX field of the AFILT register ------------------------------------------------------------- */ + +/** Description of the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_IDX_DESC "Current accumulation tensor" + +/** Offset of the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_IDX_LSB 24UL + +/** Size in bits of the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_IDX_W (8UL) + +/** Mask for retrieving the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_IDX_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_IDX_DT 0x0UL + +/** Access rights of the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_IDX_AC "R" + +/** Check whether access to the IDX field of the AFILT register is secured or not. */ +#define ATON_CONVACC_AFILT_IDX_S 0 + +/** Check whether access to the IDX field of the AFILT register is privileged or not. */ +#define ATON_CONVACC_AFILT_IDX_P 0 + +/** Read the content of the IDX field of the AFILT register. */ +#define ATON_CONVACC_AFILT_GET_IDX(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_IDX_LSB, ATON_CONVACC_AFILT_IDX_W) + + +/** + * Get the description of the IDX field of AFILT register. + * + * \return the description of the IDX field of AFILT register + */ + +static inline const int8_t *ATON_CONVACC_AFILT_IDX_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_AFILT_IDX_DESC; +} + + +/** + * Read the content of the IDX field of the AFILT register. + * + * \param[in] reg is the value of the AFILT register + * + * \return the content of the IDX field belonging to AFILT register + */ + +static inline uint32_t ATON_CONVACC_AFILT_Get_IDX(uint32_t reg) +{ + return ATON_CONVACC_AFILT_GET_IDX(reg); +} + + +/* ****************************************************** ZFRAME register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the ZFRAME register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_ZFRAME_OFFSET 0x28UL + +/** Reset value of the ZFRAME register of the CONVACC Unit. */ +#define ATON_CONVACC_ZFRAME_DT \ + (ATON_CONVACC_ZFRAME_LEFT_DT << ATON_CONVACC_ZFRAME_LEFT_LSB) | \ + (ATON_CONVACC_ZFRAME_RIGHT_DT << ATON_CONVACC_ZFRAME_RIGHT_LSB) | \ + (ATON_CONVACC_ZFRAME_TOP_DT << ATON_CONVACC_ZFRAME_TOP_LSB) | \ + (ATON_CONVACC_ZFRAME_BOTTOM_DT << ATON_CONVACC_ZFRAME_BOTTOM_LSB) + + + +/** Description of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_DESC "Zero Frame" + +/** Address of the ZFRAME register of one of the CONVACC Units. */ +#define ATON_CONVACC_ZFRAME_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_ZFRAME_OFFSET) + +/** Get the content of the ZFRAME register of one of the CONVACC Units. */ +#define ATON_CONVACC_ZFRAME_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFRAME_ADDR(UNIT))) + +/** Set the content of the ZFRAME register of one of the CONVACC Units. */ +#define ATON_CONVACC_ZFRAME_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFRAME_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ZFRAME register. + * + * \return the description of ZFRAME register + */ + +static inline const int8_t *ATON_CONVACC_ZFRAME_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFRAME_DESC; +} + + +/** + * Get the offset of the ZFRAME register. + * + * \return the offset of ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_GetOffset(void) +{ + return ATON_CONVACC_ZFRAME_OFFSET; +} + + +/** + * Get the address of the ZFRAME register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFRAME register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of ZFRAME register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_ZFRAME_ADDR(instance); +} + + +/** + * Read the content of the ZFRAME register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFRAME register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of ZFRAME register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Get(uint32_t instance) +{ + return ATON_CONVACC_ZFRAME_GET(instance); +} + + +/** + * Write the content of the ZFRAME register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFRAME register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_ZFRAME_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_ZFRAME_SET(instance, data); +} + + +/* ----------------------------------------------------------- LEFT field of the ZFRAME register ------------------------------------------------------------ */ + +/** Description of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_LEFT_DESC "Width of left zero frame" + +/** Offset of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_LEFT_LSB 0UL + +/** Size in bits of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_LEFT_W (8UL) + +/** Mask for retrieving the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_LEFT_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_LEFT_DT 0x0UL + +/** Access rights of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_LEFT_AC "RW" + +/** Check whether access to the LEFT field of the ZFRAME register is secured or not. */ +#define ATON_CONVACC_ZFRAME_LEFT_S 0 + +/** Check whether access to the LEFT field of the ZFRAME register is privileged or not. */ +#define ATON_CONVACC_ZFRAME_LEFT_P 0 + +/** Read the content of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_GET_LEFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_LEFT_LSB, ATON_CONVACC_ZFRAME_LEFT_W) + +/** Modify the content of the LEFT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_SET_LEFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_LEFT_LSB, ATON_CONVACC_ZFRAME_LEFT_W, DATA) + + +/** + * Get the description of the LEFT field of ZFRAME register. + * + * \return the description of the LEFT field of ZFRAME register + */ + +static inline const int8_t *ATON_CONVACC_ZFRAME_LEFT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFRAME_LEFT_DESC; +} + + +/** + * Read the content of the LEFT field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * + * \return the content of the LEFT field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Get_LEFT(uint32_t reg) +{ + return ATON_CONVACC_ZFRAME_GET_LEFT(reg); +} + + +/** + * Write the content of the LEFT field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the LEFT field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Set_LEFT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ZFRAME_SET_LEFT(reg, data); +} + + +/* ----------------------------------------------------------- RIGHT field of the ZFRAME register ----------------------------------------------------------- */ + +/** Description of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_RIGHT_DESC "Width of right zero frame" + +/** Offset of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_RIGHT_LSB 8UL + +/** Size in bits of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_RIGHT_W (8UL) + +/** Mask for retrieving the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_RIGHT_MASK ATON_FIELD_MASK(8UL, 8UL) + +/** Reset value of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_RIGHT_DT 0x0UL + +/** Access rights of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_RIGHT_AC "RW" + +/** Check whether access to the RIGHT field of the ZFRAME register is secured or not. */ +#define ATON_CONVACC_ZFRAME_RIGHT_S 0 + +/** Check whether access to the RIGHT field of the ZFRAME register is privileged or not. */ +#define ATON_CONVACC_ZFRAME_RIGHT_P 0 + +/** Read the content of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_GET_RIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_RIGHT_LSB, ATON_CONVACC_ZFRAME_RIGHT_W) + +/** Modify the content of the RIGHT field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_SET_RIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_RIGHT_LSB, ATON_CONVACC_ZFRAME_RIGHT_W, DATA) + + +/** + * Get the description of the RIGHT field of ZFRAME register. + * + * \return the description of the RIGHT field of ZFRAME register + */ + +static inline const int8_t *ATON_CONVACC_ZFRAME_RIGHT_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFRAME_RIGHT_DESC; +} + + +/** + * Read the content of the RIGHT field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * + * \return the content of the RIGHT field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Get_RIGHT(uint32_t reg) +{ + return ATON_CONVACC_ZFRAME_GET_RIGHT(reg); +} + + +/** + * Write the content of the RIGHT field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the RIGHT field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Set_RIGHT(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ZFRAME_SET_RIGHT(reg, data); +} + + +/* ------------------------------------------------------------ TOP field of the ZFRAME register ------------------------------------------------------------ */ + +/** Description of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_TOP_DESC "Width of top zero frame" + +/** Offset of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_TOP_LSB 16UL + +/** Size in bits of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_TOP_W (8UL) + +/** Mask for retrieving the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_TOP_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_TOP_DT 0x0UL + +/** Access rights of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_TOP_AC "RW" + +/** Check whether access to the TOP field of the ZFRAME register is secured or not. */ +#define ATON_CONVACC_ZFRAME_TOP_S 0 + +/** Check whether access to the TOP field of the ZFRAME register is privileged or not. */ +#define ATON_CONVACC_ZFRAME_TOP_P 0 + +/** Read the content of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_GET_TOP(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_TOP_LSB, ATON_CONVACC_ZFRAME_TOP_W) + +/** Modify the content of the TOP field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_SET_TOP(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_TOP_LSB, ATON_CONVACC_ZFRAME_TOP_W, DATA) + + +/** + * Get the description of the TOP field of ZFRAME register. + * + * \return the description of the TOP field of ZFRAME register + */ + +static inline const int8_t *ATON_CONVACC_ZFRAME_TOP_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFRAME_TOP_DESC; +} + + +/** + * Read the content of the TOP field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * + * \return the content of the TOP field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Get_TOP(uint32_t reg) +{ + return ATON_CONVACC_ZFRAME_GET_TOP(reg); +} + + +/** + * Write the content of the TOP field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the TOP field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Set_TOP(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ZFRAME_SET_TOP(reg, data); +} + + +/* ---------------------------------------------------------- BOTTOM field of the ZFRAME register ----------------------------------------------------------- */ + +/** Description of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_DESC "Width of bottom zero frame" + +/** Offset of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_LSB 24UL + +/** Size in bits of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_W (8UL) + +/** Mask for retrieving the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_MASK ATON_FIELD_MASK(24UL, 8UL) + +/** Reset value of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_DT 0x0UL + +/** Access rights of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_AC "RW" + +/** Check whether access to the BOTTOM field of the ZFRAME register is secured or not. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_S 0 + +/** Check whether access to the BOTTOM field of the ZFRAME register is privileged or not. */ +#define ATON_CONVACC_ZFRAME_BOTTOM_P 0 + +/** Read the content of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_GET_BOTTOM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_BOTTOM_LSB, ATON_CONVACC_ZFRAME_BOTTOM_W) + +/** Modify the content of the BOTTOM field of the ZFRAME register. */ +#define ATON_CONVACC_ZFRAME_SET_BOTTOM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_BOTTOM_LSB, ATON_CONVACC_ZFRAME_BOTTOM_W, DATA) + + +/** + * Get the description of the BOTTOM field of ZFRAME register. + * + * \return the description of the BOTTOM field of ZFRAME register + */ + +static inline const int8_t *ATON_CONVACC_ZFRAME_BOTTOM_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFRAME_BOTTOM_DESC; +} + + +/** + * Read the content of the BOTTOM field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * + * \return the content of the BOTTOM field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Get_BOTTOM(uint32_t reg) +{ + return ATON_CONVACC_ZFRAME_GET_BOTTOM(reg); +} + + +/** + * Write the content of the BOTTOM field of the ZFRAME register. + * + * \param[in] reg is the value of the ZFRAME register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the BOTTOM field belonging to ZFRAME register + */ + +static inline uint32_t ATON_CONVACC_ZFRAME_Set_BOTTOM(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ZFRAME_SET_BOTTOM(reg, data); +} + + +/* ******************************************************* ITER register of one of the CONVACC Units ******************************************************** */ + +/** Offset of the ITER register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_ITER_OFFSET 0x2cUL + +/** Reset value of the ITER register of the CONVACC Unit. */ +#define ATON_CONVACC_ITER_DT \ + (ATON_CONVACC_ITER_PERIOD_DT << ATON_CONVACC_ITER_PERIOD_LSB) | \ + (ATON_CONVACC_ITER_NUMBER_DT << ATON_CONVACC_ITER_NUMBER_LSB) | \ + (ATON_CONVACC_ITER_OFFSET_DT << ATON_CONVACC_ITER_OFFSET_LSB) | \ + (ATON_CONVACC_ITER_IDX_DT << ATON_CONVACC_ITER_IDX_LSB) + + + +/** Description of the ITER register. */ +#define ATON_CONVACC_ITER_DESC "Iteration Control" + +/** Address of the ITER register of one of the CONVACC Units. */ +#define ATON_CONVACC_ITER_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_ITER_OFFSET) + +/** Get the content of the ITER register of one of the CONVACC Units. */ +#define ATON_CONVACC_ITER_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ITER_ADDR(UNIT))) + +/** Set the content of the ITER register of one of the CONVACC Units. */ +#define ATON_CONVACC_ITER_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ITER_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ITER register. + * + * \return the description of ITER register + */ + +static inline const int8_t *ATON_CONVACC_ITER_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ITER_DESC; +} + + +/** + * Get the offset of the ITER register. + * + * \return the offset of ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_GetOffset(void) +{ + return ATON_CONVACC_ITER_OFFSET; +} + + +/** + * Get the address of the ITER register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ITER register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of ITER register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_ITER_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_ITER_ADDR(instance); +} + + +/** + * Read the content of the ITER register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ITER register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of ITER register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_ITER_Get(uint32_t instance) +{ + return ATON_CONVACC_ITER_GET(instance); +} + + +/** + * Write the content of the ITER register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ITER register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_ITER_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_ITER_SET(instance, data); +} + + +/* ----------------------------------------------------------- PERIOD field of the ITER register ------------------------------------------------------------ */ + +/** Description of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_PERIOD_DESC "Iteration period" + +/** Offset of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_PERIOD_LSB 0UL + +/** Size in bits of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_PERIOD_W (16UL) + +/** Mask for retrieving the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_PERIOD_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_PERIOD_DT 0x0UL + +/** Access rights of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_PERIOD_AC "RW" + +/** Check whether access to the PERIOD field of the ITER register is secured or not. */ +#define ATON_CONVACC_ITER_PERIOD_S 0 + +/** Check whether access to the PERIOD field of the ITER register is privileged or not. */ +#define ATON_CONVACC_ITER_PERIOD_P 0 + +/** Read the content of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_GET_PERIOD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_PERIOD_LSB, ATON_CONVACC_ITER_PERIOD_W) + +/** Modify the content of the PERIOD field of the ITER register. */ +#define ATON_CONVACC_ITER_SET_PERIOD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ITER_PERIOD_LSB, ATON_CONVACC_ITER_PERIOD_W, DATA) + + +/** + * Get the description of the PERIOD field of ITER register. + * + * \return the description of the PERIOD field of ITER register + */ + +static inline const int8_t *ATON_CONVACC_ITER_PERIOD_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ITER_PERIOD_DESC; +} + + +/** + * Read the content of the PERIOD field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * + * \return the content of the PERIOD field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Get_PERIOD(uint32_t reg) +{ + return ATON_CONVACC_ITER_GET_PERIOD(reg); +} + + +/** + * Write the content of the PERIOD field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the PERIOD field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Set_PERIOD(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ITER_SET_PERIOD(reg, data); +} + + +/* ----------------------------------------------------------- NUMBER field of the ITER register ------------------------------------------------------------ */ + +/** Description of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_NUMBER_DESC "Number of iterations" + +/** Offset of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_NUMBER_LSB 16UL + +/** Size in bits of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_NUMBER_W (4UL) + +/** Mask for retrieving the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_NUMBER_MASK ATON_FIELD_MASK(16UL, 4UL) + +/** Reset value of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_NUMBER_DT 0x0UL + +/** Access rights of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_NUMBER_AC "RW" + +/** Check whether access to the NUMBER field of the ITER register is secured or not. */ +#define ATON_CONVACC_ITER_NUMBER_S 0 + +/** Check whether access to the NUMBER field of the ITER register is privileged or not. */ +#define ATON_CONVACC_ITER_NUMBER_P 0 + +/** Read the content of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_GET_NUMBER(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_NUMBER_LSB, ATON_CONVACC_ITER_NUMBER_W) + +/** Modify the content of the NUMBER field of the ITER register. */ +#define ATON_CONVACC_ITER_SET_NUMBER(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ITER_NUMBER_LSB, ATON_CONVACC_ITER_NUMBER_W, DATA) + + +/** + * Get the description of the NUMBER field of ITER register. + * + * \return the description of the NUMBER field of ITER register + */ + +static inline const int8_t *ATON_CONVACC_ITER_NUMBER_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ITER_NUMBER_DESC; +} + + +/** + * Read the content of the NUMBER field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * + * \return the content of the NUMBER field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Get_NUMBER(uint32_t reg) +{ + return ATON_CONVACC_ITER_GET_NUMBER(reg); +} + + +/** + * Write the content of the NUMBER field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the NUMBER field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Set_NUMBER(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ITER_SET_NUMBER(reg, data); +} + + +/* ----------------------------------------------------------- OFFSET field of the ITER register ------------------------------------------------------------ */ + +/** Description of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_OFFSET_DESC "Vertical offset per iteration" + +/** Offset of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_OFFSET_LSB 20UL + +/** Size in bits of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_OFFSET_W (2UL) + +/** Mask for retrieving the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_OFFSET_MASK ATON_FIELD_MASK(20UL, 2UL) + +/** Reset value of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_OFFSET_DT 0x0UL + +/** Access rights of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_OFFSET_AC "RW" + +/** Check whether access to the OFFSET field of the ITER register is secured or not. */ +#define ATON_CONVACC_ITER_OFFSET_S 0 + +/** Check whether access to the OFFSET field of the ITER register is privileged or not. */ +#define ATON_CONVACC_ITER_OFFSET_P 0 + +/** Read the content of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_GET_OFFSET(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_OFFSET_LSB, ATON_CONVACC_ITER_OFFSET_W) + +/** Modify the content of the OFFSET field of the ITER register. */ +#define ATON_CONVACC_ITER_SET_OFFSET(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ITER_OFFSET_LSB, ATON_CONVACC_ITER_OFFSET_W, DATA) + + +/** + * Get the description of the OFFSET field of ITER register. + * + * \return the description of the OFFSET field of ITER register + */ + +static inline const int8_t *ATON_CONVACC_ITER_OFFSET_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ITER_OFFSET_DESC; +} + + +/** + * Read the content of the OFFSET field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * + * \return the content of the OFFSET field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Get_OFFSET(uint32_t reg) +{ + return ATON_CONVACC_ITER_GET_OFFSET(reg); +} + + +/** + * Write the content of the OFFSET field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the OFFSET field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Set_OFFSET(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ITER_SET_OFFSET(reg, data); +} + + +/* ------------------------------------------------------------- IDX field of the ITER register ------------------------------------------------------------- */ + +/** Description of the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_IDX_DESC "Current iteration index" + +/** Offset of the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_IDX_LSB 24UL + +/** Size in bits of the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_IDX_W (4UL) + +/** Mask for retrieving the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_IDX_MASK ATON_FIELD_MASK(24UL, 4UL) + +/** Reset value of the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_IDX_DT 0x0UL + +/** Access rights of the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_IDX_AC "R" + +/** Check whether access to the IDX field of the ITER register is secured or not. */ +#define ATON_CONVACC_ITER_IDX_S 0 + +/** Check whether access to the IDX field of the ITER register is privileged or not. */ +#define ATON_CONVACC_ITER_IDX_P 0 + +/** Read the content of the IDX field of the ITER register. */ +#define ATON_CONVACC_ITER_GET_IDX(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_IDX_LSB, ATON_CONVACC_ITER_IDX_W) + + +/** + * Get the description of the IDX field of ITER register. + * + * \return the description of the IDX field of ITER register + */ + +static inline const int8_t *ATON_CONVACC_ITER_IDX_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ITER_IDX_DESC; +} + + +/** + * Read the content of the IDX field of the ITER register. + * + * \param[in] reg is the value of the ITER register + * + * \return the content of the IDX field belonging to ITER register + */ + +static inline uint32_t ATON_CONVACC_ITER_Get_IDX(uint32_t reg) +{ + return ATON_CONVACC_ITER_GET_IDX(reg); +} + + +/* ******************************************************* FSUB register of one of the CONVACC Units ******************************************************** */ + +/** Offset of the FSUB register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_FSUB_OFFSET 0x30UL + +/** Reset value of the FSUB register of the CONVACC Unit. */ +#define ATON_CONVACC_FSUB_DT \ + (ATON_CONVACC_FSUB_FSUB_DT << ATON_CONVACC_FSUB_FSUB_LSB) + + + +/** Description of the FSUB register. */ +#define ATON_CONVACC_FSUB_DESC "Feature data subtract" + +/** Address of the FSUB register of one of the CONVACC Units. */ +#define ATON_CONVACC_FSUB_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FSUB_OFFSET) + +/** Get the content of the FSUB register of one of the CONVACC Units. */ +#define ATON_CONVACC_FSUB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FSUB_ADDR(UNIT))) + +/** Set the content of the FSUB register of one of the CONVACC Units. */ +#define ATON_CONVACC_FSUB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FSUB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FSUB register. + * + * \return the description of FSUB register + */ + +static inline const int8_t *ATON_CONVACC_FSUB_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FSUB_DESC; +} + + +/** + * Get the offset of the FSUB register. + * + * \return the offset of FSUB register + */ + +static inline uint32_t ATON_CONVACC_FSUB_GetOffset(void) +{ + return ATON_CONVACC_FSUB_OFFSET; +} + + +/** + * Get the address of the FSUB register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FSUB register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of FSUB register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FSUB_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_FSUB_ADDR(instance); +} + + +/** + * Read the content of the FSUB register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FSUB register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of FSUB register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_FSUB_Get(uint32_t instance) +{ + return ATON_CONVACC_FSUB_GET(instance); +} + + +/** + * Write the content of the FSUB register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FSUB register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_FSUB_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_FSUB_SET(instance, data); +} + + +/* ------------------------------------------------------------ FSUB field of the FSUB register ------------------------------------------------------------- */ + +/** Description of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_FSUB_DESC "Feature data subtract value" + +/** Offset of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_FSUB_LSB 0UL + +/** Size in bits of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_FSUB_W (24UL) + +/** Mask for retrieving the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_FSUB_MASK ATON_FIELD_MASK(0UL, 24UL) + +/** Reset value of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_FSUB_DT 0x0UL + +/** Access rights of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_FSUB_AC "RW" + +/** Check whether access to the FSUB field of the FSUB register is secured or not. */ +#define ATON_CONVACC_FSUB_FSUB_S 0 + +/** Check whether access to the FSUB field of the FSUB register is privileged or not. */ +#define ATON_CONVACC_FSUB_FSUB_P 0 + +/** Read the content of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_GET_FSUB(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FSUB_FSUB_LSB, ATON_CONVACC_FSUB_FSUB_W) + +/** Modify the content of the FSUB field of the FSUB register. */ +#define ATON_CONVACC_FSUB_SET_FSUB(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FSUB_FSUB_LSB, ATON_CONVACC_FSUB_FSUB_W, DATA) + + +/** + * Get the description of the FSUB field of FSUB register. + * + * \return the description of the FSUB field of FSUB register + */ + +static inline const int8_t *ATON_CONVACC_FSUB_FSUB_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_FSUB_FSUB_DESC; +} + + +/** + * Read the content of the FSUB field of the FSUB register. + * + * \param[in] reg is the value of the FSUB register + * + * \return the content of the FSUB field belonging to FSUB register + */ + +static inline uint32_t ATON_CONVACC_FSUB_Get_FSUB(uint32_t reg) +{ + return ATON_CONVACC_FSUB_GET_FSUB(reg); +} + + +/** + * Write the content of the FSUB field of the FSUB register. + * + * \param[in] reg is the value of the FSUB register + * \param[in] data is 24-bit value that must be written to the field + * + * \return the new content of the FSUB field belonging to FSUB register + */ + +static inline uint32_t ATON_CONVACC_FSUB_Set_FSUB(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_FSUB_SET_FSUB(reg, data); +} + + +/* ****************************************************** ZFBIAS register of one of the CONVACC Units ******************************************************* */ + +/** Offset of the ZFBIAS register from the base address of the CONVACC Unit. */ +#define ATON_CONVACC_ZFBIAS_OFFSET 0x34UL + +/** Reset value of the ZFBIAS register of the CONVACC Unit. */ +#define ATON_CONVACC_ZFBIAS_DT \ + (ATON_CONVACC_ZFBIAS_ZFBIAS_DT << ATON_CONVACC_ZFBIAS_ZFBIAS_LSB) + + + +/** Description of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_DESC "Zero Frame Bias" + +/** Address of the ZFBIAS register of one of the CONVACC Units. */ +#define ATON_CONVACC_ZFBIAS_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_ZFBIAS_OFFSET) + +/** Get the content of the ZFBIAS register of one of the CONVACC Units. */ +#define ATON_CONVACC_ZFBIAS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFBIAS_ADDR(UNIT))) + +/** Set the content of the ZFBIAS register of one of the CONVACC Units. */ +#define ATON_CONVACC_ZFBIAS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFBIAS_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ZFBIAS register. + * + * \return the description of ZFBIAS register + */ + +static inline const int8_t *ATON_CONVACC_ZFBIAS_GetDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFBIAS_DESC; +} + + +/** + * Get the offset of the ZFBIAS register. + * + * \return the offset of ZFBIAS register + */ + +static inline uint32_t ATON_CONVACC_ZFBIAS_GetOffset(void) +{ + return ATON_CONVACC_ZFBIAS_OFFSET; +} + + +/** + * Get the address of the ZFBIAS register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFBIAS register whose address must be returned + * (it must be instance \< 4<\em>) + * + * \return the address of ZFBIAS register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_ZFBIAS_GetAddr(uint32_t instance) +{ + return ATON_CONVACC_ZFBIAS_ADDR(instance); +} + + +/** + * Read the content of the ZFBIAS register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFBIAS register whose content must be retrieved + * (it must be instance \< 4<\em>) + * + * \return the content of ZFBIAS register belonging to Unit having index \e instance among the CONVACC Units + */ + +static inline uint32_t ATON_CONVACC_ZFBIAS_Get(uint32_t instance) +{ + return ATON_CONVACC_ZFBIAS_GET(instance); +} + + +/** + * Write the content of the ZFBIAS register. + * + * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFBIAS register whose content must be modified + * (it must be instance \< 4<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_CONVACC_ZFBIAS_Set(uint32_t instance, uint32_t data) +{ + ATON_CONVACC_ZFBIAS_SET(instance, data); +} + + +/* ---------------------------------------------------------- ZFBIAS field of the ZFBIAS register ----------------------------------------------------------- */ + +/** Description of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_DESC "Bias added to zero frames" + +/** Offset of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_LSB 0UL + +/** Size in bits of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_W (16UL) + +/** Mask for retrieving the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_DT 0x0UL + +/** Access rights of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_AC "RW" + +/** Check whether access to the ZFBIAS field of the ZFBIAS register is secured or not. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_S 0 + +/** Check whether access to the ZFBIAS field of the ZFBIAS register is privileged or not. */ +#define ATON_CONVACC_ZFBIAS_ZFBIAS_P 0 + +/** Read the content of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_GET_ZFBIAS(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFBIAS_ZFBIAS_LSB, ATON_CONVACC_ZFBIAS_ZFBIAS_W) + +/** Modify the content of the ZFBIAS field of the ZFBIAS register. */ +#define ATON_CONVACC_ZFBIAS_SET_ZFBIAS(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFBIAS_ZFBIAS_LSB, ATON_CONVACC_ZFBIAS_ZFBIAS_W, DATA) + + +/** + * Get the description of the ZFBIAS field of ZFBIAS register. + * + * \return the description of the ZFBIAS field of ZFBIAS register + */ + +static inline const int8_t *ATON_CONVACC_ZFBIAS_ZFBIAS_GetdDesc(void) +{ + return (const int8_t *)ATON_CONVACC_ZFBIAS_ZFBIAS_DESC; +} + + +/** + * Read the content of the ZFBIAS field of the ZFBIAS register. + * + * \param[in] reg is the value of the ZFBIAS register + * + * \return the content of the ZFBIAS field belonging to ZFBIAS register + */ + +static inline uint32_t ATON_CONVACC_ZFBIAS_Get_ZFBIAS(uint32_t reg) +{ + return ATON_CONVACC_ZFBIAS_GET_ZFBIAS(reg); +} + + +/** + * Write the content of the ZFBIAS field of the ZFBIAS register. + * + * \param[in] reg is the value of the ZFBIAS register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the ZFBIAS field belonging to ZFBIAS register + */ + +static inline uint32_t ATON_CONVACC_ZFBIAS_Set_ZFBIAS(uint32_t reg, uint32_t data) +{ + return ATON_CONVACC_ZFBIAS_SET_ZFBIAS(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* DECUN Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of DECUN Unit instances. */ +#define ATON_DECUN_NUM 2 + +/** + * \name Structures, macros and functions of the DECUN Units + */ +/*@{*/ + +/** + * Registers of the DECUN Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e BFORMAT register (Number of Codebooks and Codevectors). */ + uint32_t BFORMAT; + + /** \e DFORMAT register (CV data format). */ + uint32_t DFORMAT; + + /** \e FFORMAT register (Number of batches). */ + uint32_t FFORMAT; + +} ATON_DECUN_t; + + +/** Return the pointer to one of the DECUN Units. */ +#define ATON_DECUN(UNIT) ((ATON_DECUN_t *)(intptr_t)ATON_DECUN_BASE(UNIT)) + + +/** Name of one of the DECUN Units. */ +#define ATON_DECUN_NAME(UNIT) \ + (((UNIT) == 0) ? "DECUN0" : \ + (((UNIT) == 1) ? "DECUN1" : "")) + + +/** Version of the DECUN Units. */ +#define ATON_DECUN_VERSION "1.10" + + +/** Description of one of the DECUN Units. */ +#define ATON_DECUN_DESC(UNIT) \ + (((UNIT) == 0) ? "Decompression Unit 0" : \ + (((UNIT) == 1) ? "Decompression Unit 1" : "")) + + +/** Base address of one of the DECUN Units. */ +#define ATON_DECUN_BASE(UNIT) \ + (ATON_BASE + 0x13000UL + ((UNIT) * 0x1000UL)) + +/** Size in bytes of the DECUN Units. */ +#define ATON_DECUN_SIZE 0x1000UL + + +/** + * Get the name of one of the DECUN Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) + * + * \return the name of Unit having index \e instance among the DECUN Units + */ + +static inline const int8_t *ATON_DECUN_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"DECUN0"; + break; + + case 1: + str = (const int8_t *)"DECUN1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the DECUN Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) + * + * \return the description of Unit having index \e instance among the DECUN Units + */ + +static inline const int8_t *ATON_DECUN_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Decompression Unit 0"; + break; + + case 1: + str = (const int8_t *)"Decompression Unit 1"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the DECUN Units. + * + * \return the version of the DECUN Units + */ + +static inline const int8_t *ATON_DECUN_GetVersion(void) +{ + return (const int8_t *)ATON_DECUN_VERSION; +} + + +/** + * Get the base address of one of the DECUN Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) + * + * \return the base address of Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_GetBase(uint32_t instance) +{ + return ATON_DECUN_BASE(instance); +} + + +/** + * Get the size in bytes of the DECUN Units. + * + * \return the size in bytes of the DECUN Units + */ + +static inline uint32_t ATON_DECUN_GetSize(void) +{ + return ATON_DECUN_SIZE; +} + + +/* ******************************************************** CTRL register of one of the DECUN Units ********************************************************* */ + +/** Offset of the CTRL register from the base address of the DECUN Unit. */ +#define ATON_DECUN_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the DECUN Unit. */ +#define ATON_DECUN_CTRL_DT \ + (ATON_DECUN_CTRL_EN_DT << ATON_DECUN_CTRL_EN_LSB) | \ + (ATON_DECUN_CTRL_CLR_DT << ATON_DECUN_CTRL_CLR_LSB) | \ + (ATON_DECUN_CTRL_DUALIN_DT << ATON_DECUN_CTRL_DUALIN_LSB) | \ + (ATON_DECUN_CTRL_OW_DT << ATON_DECUN_CTRL_OW_LSB) | \ + (ATON_DECUN_CTRL_PAGEADDR_DT << ATON_DECUN_CTRL_PAGEADDR_LSB) | \ + (ATON_DECUN_CTRL_CONFCLR_DT << ATON_DECUN_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_DECUN_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the DECUN Units. */ +#define ATON_DECUN_CTRL_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the DECUN Units. */ +#define ATON_DECUN_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the DECUN Units. */ +#define ATON_DECUN_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_GetOffset(void) +{ + return ATON_DECUN_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the CTRL register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_CTRL_GetAddr(uint32_t instance) +{ + return ATON_DECUN_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_CTRL_Get(uint32_t instance) +{ + return ATON_DECUN_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the CTRL register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DECUN_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_DECUN_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_EN_DESC "Enable the Decompression Unit" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_DECUN_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_DECUN_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_EN_LSB, ATON_DECUN_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_DECUN_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_EN_LSB, ATON_DECUN_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Get_EN(uint32_t reg) +{ + return ATON_DECUN_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_DECUN_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_DECUN_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_CLR_LSB, ATON_DECUN_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_CLR_LSB, ATON_DECUN_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_DECUN_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- DUALIN field of the CTRL register ------------------------------------------------------------ */ + +/** Description of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_DUALIN_DESC "Disable the kernel writing stream link" + +/** Offset of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_DUALIN_LSB 2UL + +/** Size in bits of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_DUALIN_W (1UL) + +/** Mask for retrieving the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_DUALIN_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_DUALIN_DT 0x0UL + +/** Access rights of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_DUALIN_AC "RW" + +/** Check whether access to the DUALIN field of the CTRL register is secured or not. */ +#define ATON_DECUN_CTRL_DUALIN_S 0 + +/** Check whether access to the DUALIN field of the CTRL register is privileged or not. */ +#define ATON_DECUN_CTRL_DUALIN_P 0 + +/** Read the content of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_GET_DUALIN(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_DUALIN_LSB, ATON_DECUN_CTRL_DUALIN_W) + +/** Modify the content of the DUALIN field of the CTRL register. */ +#define ATON_DECUN_CTRL_SET_DUALIN(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_DUALIN_LSB, ATON_DECUN_CTRL_DUALIN_W, DATA) + + +/** + * Get the description of the DUALIN field of CTRL register. + * + * \return the description of the DUALIN field of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_DUALIN_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_DUALIN_DESC; +} + + +/** + * Read the content of the DUALIN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the DUALIN field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Get_DUALIN(uint32_t reg) +{ + return ATON_DECUN_CTRL_GET_DUALIN(reg); +} + + +/** + * Write the content of the DUALIN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the DUALIN field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Set_DUALIN(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_CTRL_SET_DUALIN(reg, data); +} + + +/* ------------------------------------------------------------- OW field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_OW_DESC "Enable of CBs overwriting" + +/** Offset of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_OW_LSB 3UL + +/** Size in bits of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_OW_W (1UL) + +/** Mask for retrieving the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_OW_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_OW_DT 0x0UL + +/** Access rights of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_OW_AC "RW" + +/** Check whether access to the OW field of the CTRL register is secured or not. */ +#define ATON_DECUN_CTRL_OW_S 0 + +/** Check whether access to the OW field of the CTRL register is privileged or not. */ +#define ATON_DECUN_CTRL_OW_P 0 + +/** Read the content of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_GET_OW(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_OW_LSB, ATON_DECUN_CTRL_OW_W) + +/** Modify the content of the OW field of the CTRL register. */ +#define ATON_DECUN_CTRL_SET_OW(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_OW_LSB, ATON_DECUN_CTRL_OW_W, DATA) + + +/** + * Get the description of the OW field of CTRL register. + * + * \return the description of the OW field of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_OW_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_OW_DESC; +} + + +/** + * Read the content of the OW field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the OW field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Get_OW(uint32_t reg) +{ + return ATON_DECUN_CTRL_GET_OW(reg); +} + + +/** + * Write the content of the OW field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OW field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Set_OW(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_CTRL_SET_OW(reg, data); +} + + +/* ---------------------------------------------------------- PAGEADDR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_PAGEADDR_DESC "Choose the Page to w/r in the memory from the bus" + +/** Offset of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_PAGEADDR_LSB 4UL + +/** Size in bits of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_PAGEADDR_W (2UL) + +/** Mask for retrieving the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_PAGEADDR_MASK ATON_FIELD_MASK(4UL, 2UL) + +/** Reset value of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_PAGEADDR_DT 0x0UL + +/** Access rights of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_PAGEADDR_AC "RW" + +/** Check whether access to the PAGEADDR field of the CTRL register is secured or not. */ +#define ATON_DECUN_CTRL_PAGEADDR_S 0 + +/** Check whether access to the PAGEADDR field of the CTRL register is privileged or not. */ +#define ATON_DECUN_CTRL_PAGEADDR_P 0 + +/** Read the content of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_GET_PAGEADDR(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_PAGEADDR_LSB, ATON_DECUN_CTRL_PAGEADDR_W) + +/** Modify the content of the PAGEADDR field of the CTRL register. */ +#define ATON_DECUN_CTRL_SET_PAGEADDR(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_PAGEADDR_LSB, ATON_DECUN_CTRL_PAGEADDR_W, DATA) + + +/** + * Get the description of the PAGEADDR field of CTRL register. + * + * \return the description of the PAGEADDR field of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_PAGEADDR_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_PAGEADDR_DESC; +} + + +/** + * Read the content of the PAGEADDR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the PAGEADDR field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Get_PAGEADDR(uint32_t reg) +{ + return ATON_DECUN_CTRL_GET_PAGEADDR(reg); +} + + +/** + * Write the content of the PAGEADDR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the PAGEADDR field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Set_PAGEADDR(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_CTRL_SET_PAGEADDR(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_DECUN_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_DECUN_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_CONFCLR_LSB, ATON_DECUN_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_DECUN_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_CONFCLR_LSB, ATON_DECUN_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_DECUN_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_DECUN_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DECUN_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_CTRL_SET_CONFCLR(reg, data); +} + + +/* ******************************************************* VERSION register of one of the DECUN Units ******************************************************* */ + +/** Offset of the VERSION register from the base address of the DECUN Unit. */ +#define ATON_DECUN_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the DECUN Unit. */ +#define ATON_DECUN_VERSION_DT \ + (ATON_DECUN_VERSION_TYPE_DT << ATON_DECUN_VERSION_TYPE_LSB) | \ + (ATON_DECUN_VERSION_MINOR_DT << ATON_DECUN_VERSION_MINOR_LSB) | \ + (ATON_DECUN_VERSION_MAJOR_DT << ATON_DECUN_VERSION_MAJOR_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_DECUN_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the DECUN Units. */ +#define ATON_DECUN_VERSION_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the DECUN Units. */ +#define ATON_DECUN_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_DECUN_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_DECUN_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_DECUN_VERSION_GetOffset(void) +{ + return ATON_DECUN_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the VERSION register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_VERSION_GetAddr(uint32_t instance) +{ + return ATON_DECUN_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_VERSION_Get(uint32_t instance) +{ + return ATON_DECUN_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_TYPE_DT 0x19UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_DECUN_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_DECUN_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_DECUN_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_DECUN_VERSION_TYPE_LSB, ATON_DECUN_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_DECUN_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_DECUN_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_DECUN_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MINOR_DT 0xaUL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_DECUN_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_DECUN_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_DECUN_VERSION_MINOR_LSB, ATON_DECUN_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_DECUN_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_DECUN_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_DECUN_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_DECUN_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_DECUN_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_DECUN_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_DECUN_VERSION_MAJOR_LSB, ATON_DECUN_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_DECUN_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_DECUN_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_DECUN_VERSION_GET_MAJOR(reg); +} + + +/* ******************************************************* BFORMAT register of one of the DECUN Units ******************************************************* */ + +/** Offset of the BFORMAT register from the base address of the DECUN Unit. */ +#define ATON_DECUN_BFORMAT_OFFSET 0x8UL + +/** Reset value of the BFORMAT register of the DECUN Unit. */ +#define ATON_DECUN_BFORMAT_DT \ + (ATON_DECUN_BFORMAT_CVS_DT << ATON_DECUN_BFORMAT_CVS_LSB) | \ + (ATON_DECUN_BFORMAT_CWS_DT << ATON_DECUN_BFORMAT_CWS_LSB) | \ + (ATON_DECUN_BFORMAT_OSAM_DT << ATON_DECUN_BFORMAT_OSAM_LSB) + + + +/** Description of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_DESC "Number of Codebooks and Codevectors" + +/** Address of the BFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_BFORMAT_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_BFORMAT_OFFSET) + +/** Get the content of the BFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_BFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_BFORMAT_ADDR(UNIT))) + +/** Set the content of the BFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_BFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_BFORMAT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of BFORMAT register. + * + * \return the description of BFORMAT register + */ + +static inline const int8_t *ATON_DECUN_BFORMAT_GetDesc(void) +{ + return (const int8_t *)ATON_DECUN_BFORMAT_DESC; +} + + +/** + * Get the offset of the BFORMAT register. + * + * \return the offset of BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_GetOffset(void) +{ + return ATON_DECUN_BFORMAT_OFFSET; +} + + +/** + * Get the address of the BFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the BFORMAT register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of BFORMAT register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_BFORMAT_GetAddr(uint32_t instance) +{ + return ATON_DECUN_BFORMAT_ADDR(instance); +} + + +/** + * Read the content of the BFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the BFORMAT register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of BFORMAT register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Get(uint32_t instance) +{ + return ATON_DECUN_BFORMAT_GET(instance); +} + + +/** + * Write the content of the BFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the BFORMAT register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DECUN_BFORMAT_Set(uint32_t instance, uint32_t data) +{ + ATON_DECUN_BFORMAT_SET(instance, data); +} + + +/* ----------------------------------------------------------- CVS field of the BFORMAT register ------------------------------------------------------------ */ + +/** Description of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CVS_DESC "Number of Codevectors per Codebook" + +/** Offset of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CVS_LSB 0UL + +/** Size in bits of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CVS_W (8UL) + +/** Mask for retrieving the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CVS_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CVS_DT 0x0UL + +/** Access rights of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CVS_AC "RW" + +/** Check whether access to the CVS field of the BFORMAT register is secured or not. */ +#define ATON_DECUN_BFORMAT_CVS_S 0 + +/** Check whether access to the CVS field of the BFORMAT register is privileged or not. */ +#define ATON_DECUN_BFORMAT_CVS_P 0 + +/** Read the content of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_GET_CVS(REG) ATON_GET_FIELD(REG, ATON_DECUN_BFORMAT_CVS_LSB, ATON_DECUN_BFORMAT_CVS_W) + +/** Modify the content of the CVS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_SET_CVS(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_BFORMAT_CVS_LSB, ATON_DECUN_BFORMAT_CVS_W, DATA) + + +/** + * Get the description of the CVS field of BFORMAT register. + * + * \return the description of the CVS field of BFORMAT register + */ + +static inline const int8_t *ATON_DECUN_BFORMAT_CVS_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_BFORMAT_CVS_DESC; +} + + +/** + * Read the content of the CVS field of the BFORMAT register. + * + * \param[in] reg is the value of the BFORMAT register + * + * \return the content of the CVS field belonging to BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Get_CVS(uint32_t reg) +{ + return ATON_DECUN_BFORMAT_GET_CVS(reg); +} + + +/** + * Write the content of the CVS field of the BFORMAT register. + * + * \param[in] reg is the value of the BFORMAT register + * \param[in] data is 8-bit value that must be written to the field + * + * \return the new content of the CVS field belonging to BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Set_CVS(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_BFORMAT_SET_CVS(reg, data); +} + + +/* ----------------------------------------------------------- CWS field of the BFORMAT register ------------------------------------------------------------ */ + +/** Description of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CWS_DESC "Number of Codewords per Codevectors" + +/** Offset of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CWS_LSB 8UL + +/** Size in bits of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CWS_W (3UL) + +/** Mask for retrieving the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CWS_MASK ATON_FIELD_MASK(8UL, 3UL) + +/** Reset value of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CWS_DT 0x0UL + +/** Access rights of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_CWS_AC "RW" + +/** Check whether access to the CWS field of the BFORMAT register is secured or not. */ +#define ATON_DECUN_BFORMAT_CWS_S 0 + +/** Check whether access to the CWS field of the BFORMAT register is privileged or not. */ +#define ATON_DECUN_BFORMAT_CWS_P 0 + +/** Read the content of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_GET_CWS(REG) ATON_GET_FIELD(REG, ATON_DECUN_BFORMAT_CWS_LSB, ATON_DECUN_BFORMAT_CWS_W) + +/** Modify the content of the CWS field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_SET_CWS(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_BFORMAT_CWS_LSB, ATON_DECUN_BFORMAT_CWS_W, DATA) + + +/** + * Get the description of the CWS field of BFORMAT register. + * + * \return the description of the CWS field of BFORMAT register + */ + +static inline const int8_t *ATON_DECUN_BFORMAT_CWS_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_BFORMAT_CWS_DESC; +} + + +/** + * Read the content of the CWS field of the BFORMAT register. + * + * \param[in] reg is the value of the BFORMAT register + * + * \return the content of the CWS field belonging to BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Get_CWS(uint32_t reg) +{ + return ATON_DECUN_BFORMAT_GET_CWS(reg); +} + + +/** + * Write the content of the CWS field of the BFORMAT register. + * + * \param[in] reg is the value of the BFORMAT register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the CWS field belonging to BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Set_CWS(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_BFORMAT_SET_CWS(reg, data); +} + + +/* ----------------------------------------------------------- OSAM field of the BFORMAT register ----------------------------------------------------------- */ + +/** Description of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_OSAM_DESC "Number of read Codewords from the last CV" + +/** Offset of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_OSAM_LSB 12UL + +/** Size in bits of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_OSAM_W (3UL) + +/** Mask for retrieving the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_OSAM_MASK ATON_FIELD_MASK(12UL, 3UL) + +/** Reset value of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_OSAM_DT 0x0UL + +/** Access rights of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_OSAM_AC "RW" + +/** Check whether access to the OSAM field of the BFORMAT register is secured or not. */ +#define ATON_DECUN_BFORMAT_OSAM_S 0 + +/** Check whether access to the OSAM field of the BFORMAT register is privileged or not. */ +#define ATON_DECUN_BFORMAT_OSAM_P 0 + +/** Read the content of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_GET_OSAM(REG) ATON_GET_FIELD(REG, ATON_DECUN_BFORMAT_OSAM_LSB, ATON_DECUN_BFORMAT_OSAM_W) + +/** Modify the content of the OSAM field of the BFORMAT register. */ +#define ATON_DECUN_BFORMAT_SET_OSAM(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_BFORMAT_OSAM_LSB, ATON_DECUN_BFORMAT_OSAM_W, DATA) + + +/** + * Get the description of the OSAM field of BFORMAT register. + * + * \return the description of the OSAM field of BFORMAT register + */ + +static inline const int8_t *ATON_DECUN_BFORMAT_OSAM_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_BFORMAT_OSAM_DESC; +} + + +/** + * Read the content of the OSAM field of the BFORMAT register. + * + * \param[in] reg is the value of the BFORMAT register + * + * \return the content of the OSAM field belonging to BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Get_OSAM(uint32_t reg) +{ + return ATON_DECUN_BFORMAT_GET_OSAM(reg); +} + + +/** + * Write the content of the OSAM field of the BFORMAT register. + * + * \param[in] reg is the value of the BFORMAT register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the OSAM field belonging to BFORMAT register + */ + +static inline uint32_t ATON_DECUN_BFORMAT_Set_OSAM(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_BFORMAT_SET_OSAM(reg, data); +} + + +/* ******************************************************* DFORMAT register of one of the DECUN Units ******************************************************* */ + +/** Offset of the DFORMAT register from the base address of the DECUN Unit. */ +#define ATON_DECUN_DFORMAT_OFFSET 0xcUL + +/** Reset value of the DFORMAT register of the DECUN Unit. */ +#define ATON_DECUN_DFORMAT_DT \ + (ATON_DECUN_DFORMAT_CV8_DT << ATON_DECUN_DFORMAT_CV8_LSB) | \ + (ATON_DECUN_DFORMAT_RAWLINE_DT << ATON_DECUN_DFORMAT_RAWLINE_LSB) + + + +/** Description of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_DESC "CV data format" + +/** Address of the DFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_DFORMAT_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_DFORMAT_OFFSET) + +/** Get the content of the DFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_DFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_DFORMAT_ADDR(UNIT))) + +/** Set the content of the DFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_DFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_DFORMAT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of DFORMAT register. + * + * \return the description of DFORMAT register + */ + +static inline const int8_t *ATON_DECUN_DFORMAT_GetDesc(void) +{ + return (const int8_t *)ATON_DECUN_DFORMAT_DESC; +} + + +/** + * Get the offset of the DFORMAT register. + * + * \return the offset of DFORMAT register + */ + +static inline uint32_t ATON_DECUN_DFORMAT_GetOffset(void) +{ + return ATON_DECUN_DFORMAT_OFFSET; +} + + +/** + * Get the address of the DFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the DFORMAT register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of DFORMAT register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_DFORMAT_GetAddr(uint32_t instance) +{ + return ATON_DECUN_DFORMAT_ADDR(instance); +} + + +/** + * Read the content of the DFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the DFORMAT register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of DFORMAT register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_DFORMAT_Get(uint32_t instance) +{ + return ATON_DECUN_DFORMAT_GET(instance); +} + + +/** + * Write the content of the DFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the DFORMAT register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DECUN_DFORMAT_Set(uint32_t instance, uint32_t data) +{ + ATON_DECUN_DFORMAT_SET(instance, data); +} + + +/* ----------------------------------------------------------- CV8 field of the DFORMAT register ------------------------------------------------------------ */ + +/** Description of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_CV8_DESC "CodeVector data format" + +/** Offset of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_CV8_LSB 0UL + +/** Size in bits of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_CV8_W (1UL) + +/** Mask for retrieving the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_CV8_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_CV8_DT 0x0UL + +/** Access rights of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_CV8_AC "RW" + +/** Check whether access to the CV8 field of the DFORMAT register is secured or not. */ +#define ATON_DECUN_DFORMAT_CV8_S 0 + +/** Check whether access to the CV8 field of the DFORMAT register is privileged or not. */ +#define ATON_DECUN_DFORMAT_CV8_P 0 + +/** Read the content of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_GET_CV8(REG) ATON_GET_FIELD(REG, ATON_DECUN_DFORMAT_CV8_LSB, ATON_DECUN_DFORMAT_CV8_W) + +/** Modify the content of the CV8 field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_SET_CV8(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_DFORMAT_CV8_LSB, ATON_DECUN_DFORMAT_CV8_W, DATA) + + +/** + * Get the description of the CV8 field of DFORMAT register. + * + * \return the description of the CV8 field of DFORMAT register + */ + +static inline const int8_t *ATON_DECUN_DFORMAT_CV8_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_DFORMAT_CV8_DESC; +} + + +/** + * Read the content of the CV8 field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the CV8 field belonging to DFORMAT register + */ + +static inline uint32_t ATON_DECUN_DFORMAT_Get_CV8(uint32_t reg) +{ + return ATON_DECUN_DFORMAT_GET_CV8(reg); +} + + +/** + * Write the content of the CV8 field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CV8 field belonging to DFORMAT register + */ + +static inline uint32_t ATON_DECUN_DFORMAT_Set_CV8(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_DFORMAT_SET_CV8(reg, data); +} + + +/* --------------------------------------------------------- RAWLINE field of the DFORMAT register ---------------------------------------------------------- */ + +/** Description of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_RAWLINE_DESC "Raw linetype output" + +/** Offset of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_RAWLINE_LSB 1UL + +/** Size in bits of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_RAWLINE_W (1UL) + +/** Mask for retrieving the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_RAWLINE_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_RAWLINE_DT 0x0UL + +/** Access rights of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_RAWLINE_AC "RW" + +/** Check whether access to the RAWLINE field of the DFORMAT register is secured or not. */ +#define ATON_DECUN_DFORMAT_RAWLINE_S 0 + +/** Check whether access to the RAWLINE field of the DFORMAT register is privileged or not. */ +#define ATON_DECUN_DFORMAT_RAWLINE_P 0 + +/** Read the content of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_GET_RAWLINE(REG) ATON_GET_FIELD(REG, ATON_DECUN_DFORMAT_RAWLINE_LSB, ATON_DECUN_DFORMAT_RAWLINE_W) + +/** Modify the content of the RAWLINE field of the DFORMAT register. */ +#define ATON_DECUN_DFORMAT_SET_RAWLINE(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_DFORMAT_RAWLINE_LSB, ATON_DECUN_DFORMAT_RAWLINE_W, DATA) + + +/** + * Get the description of the RAWLINE field of DFORMAT register. + * + * \return the description of the RAWLINE field of DFORMAT register + */ + +static inline const int8_t *ATON_DECUN_DFORMAT_RAWLINE_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_DFORMAT_RAWLINE_DESC; +} + + +/** + * Read the content of the RAWLINE field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * + * \return the content of the RAWLINE field belonging to DFORMAT register + */ + +static inline uint32_t ATON_DECUN_DFORMAT_Get_RAWLINE(uint32_t reg) +{ + return ATON_DECUN_DFORMAT_GET_RAWLINE(reg); +} + + +/** + * Write the content of the RAWLINE field of the DFORMAT register. + * + * \param[in] reg is the value of the DFORMAT register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the RAWLINE field belonging to DFORMAT register + */ + +static inline uint32_t ATON_DECUN_DFORMAT_Set_RAWLINE(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_DFORMAT_SET_RAWLINE(reg, data); +} + + +/* ******************************************************* FFORMAT register of one of the DECUN Units ******************************************************* */ + +/** Offset of the FFORMAT register from the base address of the DECUN Unit. */ +#define ATON_DECUN_FFORMAT_OFFSET 0x10UL + +/** Reset value of the FFORMAT register of the DECUN Unit. */ +#define ATON_DECUN_FFORMAT_DT \ + (ATON_DECUN_FFORMAT_BN_DT << ATON_DECUN_FFORMAT_BN_LSB) + + + +/** Description of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_DESC "Number of batches" + +/** Address of the FFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_FFORMAT_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_FFORMAT_OFFSET) + +/** Get the content of the FFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_FFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_FFORMAT_ADDR(UNIT))) + +/** Set the content of the FFORMAT register of one of the DECUN Units. */ +#define ATON_DECUN_FFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_FFORMAT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FFORMAT register. + * + * \return the description of FFORMAT register + */ + +static inline const int8_t *ATON_DECUN_FFORMAT_GetDesc(void) +{ + return (const int8_t *)ATON_DECUN_FFORMAT_DESC; +} + + +/** + * Get the offset of the FFORMAT register. + * + * \return the offset of FFORMAT register + */ + +static inline uint32_t ATON_DECUN_FFORMAT_GetOffset(void) +{ + return ATON_DECUN_FFORMAT_OFFSET; +} + + +/** + * Get the address of the FFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the FFORMAT register whose address must be returned + * (it must be instance \< 2<\em>) + * + * \return the address of FFORMAT register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_FFORMAT_GetAddr(uint32_t instance) +{ + return ATON_DECUN_FFORMAT_ADDR(instance); +} + + +/** + * Read the content of the FFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the FFORMAT register whose content must be retrieved + * (it must be instance \< 2<\em>) + * + * \return the content of FFORMAT register belonging to Unit having index \e instance among the DECUN Units + */ + +static inline uint32_t ATON_DECUN_FFORMAT_Get(uint32_t instance) +{ + return ATON_DECUN_FFORMAT_GET(instance); +} + + +/** + * Write the content of the FFORMAT register. + * + * \param[in] instance is the index of the Unit (among the DECUN Units) containing the FFORMAT register whose content must be modified + * (it must be instance \< 2<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DECUN_FFORMAT_Set(uint32_t instance, uint32_t data) +{ + ATON_DECUN_FFORMAT_SET(instance, data); +} + + +/* ------------------------------------------------------------ BN field of the FFORMAT register ------------------------------------------------------------ */ + +/** Description of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_BN_DESC "Number of batches" + +/** Offset of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_BN_LSB 0UL + +/** Size in bits of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_BN_W (10UL) + +/** Mask for retrieving the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_BN_MASK ATON_FIELD_MASK(0UL, 10UL) + +/** Reset value of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_BN_DT 0x0UL + +/** Access rights of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_BN_AC "RW" + +/** Check whether access to the BN field of the FFORMAT register is secured or not. */ +#define ATON_DECUN_FFORMAT_BN_S 0 + +/** Check whether access to the BN field of the FFORMAT register is privileged or not. */ +#define ATON_DECUN_FFORMAT_BN_P 0 + +/** Read the content of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_GET_BN(REG) ATON_GET_FIELD(REG, ATON_DECUN_FFORMAT_BN_LSB, ATON_DECUN_FFORMAT_BN_W) + +/** Modify the content of the BN field of the FFORMAT register. */ +#define ATON_DECUN_FFORMAT_SET_BN(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_FFORMAT_BN_LSB, ATON_DECUN_FFORMAT_BN_W, DATA) + + +/** + * Get the description of the BN field of FFORMAT register. + * + * \return the description of the BN field of FFORMAT register + */ + +static inline const int8_t *ATON_DECUN_FFORMAT_BN_GetdDesc(void) +{ + return (const int8_t *)ATON_DECUN_FFORMAT_BN_DESC; +} + + +/** + * Read the content of the BN field of the FFORMAT register. + * + * \param[in] reg is the value of the FFORMAT register + * + * \return the content of the BN field belonging to FFORMAT register + */ + +static inline uint32_t ATON_DECUN_FFORMAT_Get_BN(uint32_t reg) +{ + return ATON_DECUN_FFORMAT_GET_BN(reg); +} + + +/** + * Write the content of the BN field of the FFORMAT register. + * + * \param[in] reg is the value of the FFORMAT register + * \param[in] data is 10-bit value that must be written to the field + * + * \return the new content of the BN field belonging to FFORMAT register + */ + +static inline uint32_t ATON_DECUN_FFORMAT_Set_BN(uint32_t reg, uint32_t data) +{ + return ATON_DECUN_FFORMAT_SET_BN(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* RECBUF Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of RECBUF Unit instances. */ +#define ATON_RECBUF_NUM 1 + +/** + * \name Structures, macros and functions of the RECBUF Units + */ +/*@{*/ + +/** + * Registers of the RECBUF Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e FORMAT0 register (Number of Input used channels and linetype for Input Stream 0). */ + uint32_t FORMAT0; + + /** \e FORMAT1 register (Number of Input/Output used channels and linetype for Output Stream 1). */ + uint32_t FORMAT1; + + /** \e FORMAT2 register (Number of Input/Output used channels and linetype for Output Stream 2). */ + uint32_t FORMAT2; + +} ATON_RECBUF_t; + + +/** Return the pointer to one of the RECBUF Units. */ +#define ATON_RECBUF(UNIT) ((ATON_RECBUF_t *)(intptr_t)ATON_RECBUF_BASE(UNIT)) + + +/** Name of one of the RECBUF Units. */ +#define ATON_RECBUF_NAME(UNIT) \ + (((UNIT) == 0) ? "RECBUF0" : "") + + +/** Version of the RECBUF Units. */ +#define ATON_RECBUF_VERSION "3.2" + + +/** Description of one of the RECBUF Units. */ +#define ATON_RECBUF_DESC(UNIT) \ + (((UNIT) == 0) ? "Reconfigurable Buffer 0" : "") + + +/** Base address of one of the RECBUF Units. */ +#define ATON_RECBUF_BASE(UNIT) \ + (ATON_BASE + 0x1d000UL + ((UNIT) * 0x0UL)) + +/** Size in bytes of the RECBUF Units. */ +#define ATON_RECBUF_SIZE 0x1000UL + + +/** + * Get the name of one of the RECBUF Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) + * + * \return the name of Unit having index \e instance among the RECBUF Units + */ + +static inline const int8_t *ATON_RECBUF_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"RECBUF0"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the RECBUF Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) + * + * \return the description of Unit having index \e instance among the RECBUF Units + */ + +static inline const int8_t *ATON_RECBUF_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Reconfigurable Buffer 0"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the RECBUF Units. + * + * \return the version of the RECBUF Units + */ + +static inline const int8_t *ATON_RECBUF_GetVersion(void) +{ + return (const int8_t *)ATON_RECBUF_VERSION; +} + + +/** + * Get the base address of one of the RECBUF Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) + * + * \return the base address of Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_GetBase(uint32_t instance) +{ + return ATON_RECBUF_BASE(instance); +} + + +/** + * Get the size in bytes of the RECBUF Units. + * + * \return the size in bytes of the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_GetSize(void) +{ + return ATON_RECBUF_SIZE; +} + + +/* ******************************************************** CTRL register of one of the RECBUF Units ******************************************************** */ + +/** Offset of the CTRL register from the base address of the RECBUF Unit. */ +#define ATON_RECBUF_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the RECBUF Unit. */ +#define ATON_RECBUF_CTRL_DT \ + (ATON_RECBUF_CTRL_EN_DT << ATON_RECBUF_CTRL_EN_LSB) | \ + (ATON_RECBUF_CTRL_CLR_DT << ATON_RECBUF_CTRL_CLR_LSB) | \ + (ATON_RECBUF_CTRL_CONFCLR_DT << ATON_RECBUF_CTRL_CONFCLR_LSB) | \ + (ATON_RECBUF_CTRL_ILL_DT << ATON_RECBUF_CTRL_ILL_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_RECBUF_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the RECBUF Units. */ +#define ATON_RECBUF_CTRL_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the RECBUF Units. */ +#define ATON_RECBUF_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the RECBUF Units. */ +#define ATON_RECBUF_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_RECBUF_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_RECBUF_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_GetOffset(void) +{ + return ATON_RECBUF_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the CTRL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_CTRL_GetAddr(uint32_t instance) +{ + return ATON_RECBUF_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_CTRL_Get(uint32_t instance) +{ + return ATON_RECBUF_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the CTRL register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_RECBUF_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_RECBUF_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_EN_DESC "Enable the Interrupt Controller" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_RECBUF_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_RECBUF_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_EN_LSB, ATON_RECBUF_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_RECBUF_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_EN_LSB, ATON_RECBUF_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_RECBUF_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Get_EN(uint32_t reg) +{ + return ATON_RECBUF_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_RECBUF_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_RECBUF_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_CLR_LSB, ATON_RECBUF_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_CLR_LSB, ATON_RECBUF_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_RECBUF_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_RECBUF_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_RECBUF_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_RECBUF_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_CONFCLR_LSB, ATON_RECBUF_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_RECBUF_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_CONFCLR_LSB, ATON_RECBUF_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_RECBUF_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_RECBUF_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_CTRL_SET_CONFCLR(reg, data); +} + + +/* ------------------------------------------------------------- ILL field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_ILL_DESC "Illegal Configuration register" + +/** Offset of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_ILL_LSB 31UL + +/** Size in bits of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_ILL_W (1UL) + +/** Mask for retrieving the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_ILL_MASK ATON_FIELD_MASK(31UL, 1UL) + +/** Reset value of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_ILL_DT 0x0UL + +/** Access rights of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_ILL_AC "RW" + +/** Check whether access to the ILL field of the CTRL register is secured or not. */ +#define ATON_RECBUF_CTRL_ILL_S 0 + +/** Check whether access to the ILL field of the CTRL register is privileged or not. */ +#define ATON_RECBUF_CTRL_ILL_P 0 + +/** Read the content of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_GET_ILL(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_ILL_LSB, ATON_RECBUF_CTRL_ILL_W) + +/** Modify the content of the ILL field of the CTRL register. */ +#define ATON_RECBUF_CTRL_SET_ILL(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_ILL_LSB, ATON_RECBUF_CTRL_ILL_W, DATA) + + +/** + * Get the description of the ILL field of CTRL register. + * + * \return the description of the ILL field of CTRL register + */ + +static inline const int8_t *ATON_RECBUF_CTRL_ILL_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_CTRL_ILL_DESC; +} + + +/** + * Read the content of the ILL field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the ILL field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Get_ILL(uint32_t reg) +{ + return ATON_RECBUF_CTRL_GET_ILL(reg); +} + + +/** + * Write the content of the ILL field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ILL field belonging to CTRL register + */ + +static inline uint32_t ATON_RECBUF_CTRL_Set_ILL(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_CTRL_SET_ILL(reg, data); +} + + +/* ****************************************************** VERSION register of one of the RECBUF Units ******************************************************* */ + +/** Offset of the VERSION register from the base address of the RECBUF Unit. */ +#define ATON_RECBUF_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the RECBUF Unit. */ +#define ATON_RECBUF_VERSION_DT \ + (ATON_RECBUF_VERSION_TYPE_DT << ATON_RECBUF_VERSION_TYPE_LSB) | \ + (ATON_RECBUF_VERSION_MINOR_DT << ATON_RECBUF_VERSION_MINOR_LSB) | \ + (ATON_RECBUF_VERSION_MAJOR_DT << ATON_RECBUF_VERSION_MAJOR_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_RECBUF_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the RECBUF Units. */ +#define ATON_RECBUF_VERSION_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the RECBUF Units. */ +#define ATON_RECBUF_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_RECBUF_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_RECBUF_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_RECBUF_VERSION_GetOffset(void) +{ + return ATON_RECBUF_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the VERSION register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_VERSION_GetAddr(uint32_t instance) +{ + return ATON_RECBUF_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_VERSION_Get(uint32_t instance) +{ + return ATON_RECBUF_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_TYPE_DT 0x20UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_RECBUF_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_RECBUF_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_RECBUF_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_RECBUF_VERSION_TYPE_LSB, ATON_RECBUF_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_RECBUF_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_RECBUF_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_RECBUF_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MINOR_DT 0x2UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_RECBUF_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_RECBUF_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_VERSION_MINOR_LSB, ATON_RECBUF_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_RECBUF_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_RECBUF_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_RECBUF_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MAJOR_DT 0x3UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_RECBUF_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_RECBUF_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_RECBUF_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_VERSION_MAJOR_LSB, ATON_RECBUF_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_RECBUF_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_RECBUF_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_RECBUF_VERSION_GET_MAJOR(reg); +} + + +/* ****************************************************** FORMAT0 register of one of the RECBUF Units ******************************************************* */ + +/** Offset of the FORMAT0 register from the base address of the RECBUF Unit. */ +#define ATON_RECBUF_FORMAT0_OFFSET 0x8UL + +/** Reset value of the FORMAT0 register of the RECBUF Unit. */ +#define ATON_RECBUF_FORMAT0_DT \ + (ATON_RECBUF_FORMAT0_ACTCHIN_DT << ATON_RECBUF_FORMAT0_ACTCHIN_LSB) | \ + (ATON_RECBUF_FORMAT0_MEMBMARK_DT << ATON_RECBUF_FORMAT0_MEMBMARK_LSB) + + + +/** Description of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_DESC "Number of Input used channels and linetype for Input Stream 0" + +/** Address of the FORMAT0 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT0_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_FORMAT0_OFFSET) + +/** Get the content of the FORMAT0 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT0_ADDR(UNIT))) + +/** Set the content of the FORMAT0 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FORMAT0 register. + * + * \return the description of FORMAT0 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT0_GetDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT0_DESC; +} + + +/** + * Get the offset of the FORMAT0 register. + * + * \return the offset of FORMAT0 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_GetOffset(void) +{ + return ATON_RECBUF_FORMAT0_OFFSET; +} + + +/** + * Get the address of the FORMAT0 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of FORMAT0 register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_GetAddr(uint32_t instance) +{ + return ATON_RECBUF_FORMAT0_ADDR(instance); +} + + +/** + * Read the content of the FORMAT0 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of FORMAT0 register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_Get(uint32_t instance) +{ + return ATON_RECBUF_FORMAT0_GET(instance); +} + + +/** + * Write the content of the FORMAT0 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_RECBUF_FORMAT0_Set(uint32_t instance, uint32_t data) +{ + ATON_RECBUF_FORMAT0_SET(instance, data); +} + + +/* --------------------------------------------------------- ACTCHIN field of the FORMAT0 register ---------------------------------------------------------- */ + +/** Description of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_DESC "Number of Active Input Channels" + +/** Offset of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_LSB 0UL + +/** Size in bits of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_W (2UL) + +/** Mask for retrieving the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_DT 0x0UL + +/** Access rights of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_AC "RW" + +/** Check whether access to the ACTCHIN field of the FORMAT0 register is secured or not. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_S 0 + +/** Check whether access to the ACTCHIN field of the FORMAT0 register is privileged or not. */ +#define ATON_RECBUF_FORMAT0_ACTCHIN_P 0 + +/** Read the content of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_GET_ACTCHIN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT0_ACTCHIN_LSB, ATON_RECBUF_FORMAT0_ACTCHIN_W) + +/** Modify the content of the ACTCHIN field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_SET_ACTCHIN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT0_ACTCHIN_LSB, ATON_RECBUF_FORMAT0_ACTCHIN_W, DATA) + + +/** + * Get the description of the ACTCHIN field of FORMAT0 register. + * + * \return the description of the ACTCHIN field of FORMAT0 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT0_ACTCHIN_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT0_ACTCHIN_DESC; +} + + +/** + * Read the content of the ACTCHIN field of the FORMAT0 register. + * + * \param[in] reg is the value of the FORMAT0 register + * + * \return the content of the ACTCHIN field belonging to FORMAT0 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_Get_ACTCHIN(uint32_t reg) +{ + return ATON_RECBUF_FORMAT0_GET_ACTCHIN(reg); +} + + +/** + * Write the content of the ACTCHIN field of the FORMAT0 register. + * + * \param[in] reg is the value of the FORMAT0 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ACTCHIN field belonging to FORMAT0 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_Set_ACTCHIN(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_FORMAT0_SET_ACTCHIN(reg, data); +} + + +/* --------------------------------------------------------- MEMBMARK field of the FORMAT0 register --------------------------------------------------------- */ + +/** Description of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_DESC "Bookmark for the RAM Partitioning for Input Stream 0" + +/** Offset of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_LSB 4UL + +/** Size in bits of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_W (10UL) + +/** Mask for retrieving the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_MASK ATON_FIELD_MASK(4UL, 10UL) + +/** Reset value of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_DT 0x0UL + +/** Access rights of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_AC "RW" + +/** Check whether access to the MEMBMARK field of the FORMAT0 register is secured or not. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_S 0 + +/** Check whether access to the MEMBMARK field of the FORMAT0 register is privileged or not. */ +#define ATON_RECBUF_FORMAT0_MEMBMARK_P 0 + +/** Read the content of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_GET_MEMBMARK(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT0_MEMBMARK_LSB, ATON_RECBUF_FORMAT0_MEMBMARK_W) + +/** Modify the content of the MEMBMARK field of the FORMAT0 register. */ +#define ATON_RECBUF_FORMAT0_SET_MEMBMARK(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT0_MEMBMARK_LSB, ATON_RECBUF_FORMAT0_MEMBMARK_W, DATA) + + +/** + * Get the description of the MEMBMARK field of FORMAT0 register. + * + * \return the description of the MEMBMARK field of FORMAT0 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT0_MEMBMARK_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT0_MEMBMARK_DESC; +} + + +/** + * Read the content of the MEMBMARK field of the FORMAT0 register. + * + * \param[in] reg is the value of the FORMAT0 register + * + * \return the content of the MEMBMARK field belonging to FORMAT0 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_Get_MEMBMARK(uint32_t reg) +{ + return ATON_RECBUF_FORMAT0_GET_MEMBMARK(reg); +} + + +/** + * Write the content of the MEMBMARK field of the FORMAT0 register. + * + * \param[in] reg is the value of the FORMAT0 register + * \param[in] data is 10-bit value that must be written to the field + * + * \return the new content of the MEMBMARK field belonging to FORMAT0 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT0_Set_MEMBMARK(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_FORMAT0_SET_MEMBMARK(reg, data); +} + + +/* ****************************************************** FORMAT1 register of one of the RECBUF Units ******************************************************* */ + +/** Offset of the FORMAT1 register from the base address of the RECBUF Unit. */ +#define ATON_RECBUF_FORMAT1_OFFSET 0xcUL + +/** Reset value of the FORMAT1 register of the RECBUF Unit. */ +#define ATON_RECBUF_FORMAT1_DT \ + (ATON_RECBUF_FORMAT1_ACTCHIN_DT << ATON_RECBUF_FORMAT1_ACTCHIN_LSB) | \ + (ATON_RECBUF_FORMAT1_MEMBMARK_DT << ATON_RECBUF_FORMAT1_MEMBMARK_LSB) + + + +/** Description of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_DESC "Number of Input/Output used channels and linetype for Output Stream 1" + +/** Address of the FORMAT1 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT1_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_FORMAT1_OFFSET) + +/** Get the content of the FORMAT1 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT1_ADDR(UNIT))) + +/** Set the content of the FORMAT1 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FORMAT1 register. + * + * \return the description of FORMAT1 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT1_GetDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT1_DESC; +} + + +/** + * Get the offset of the FORMAT1 register. + * + * \return the offset of FORMAT1 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_GetOffset(void) +{ + return ATON_RECBUF_FORMAT1_OFFSET; +} + + +/** + * Get the address of the FORMAT1 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of FORMAT1 register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_GetAddr(uint32_t instance) +{ + return ATON_RECBUF_FORMAT1_ADDR(instance); +} + + +/** + * Read the content of the FORMAT1 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of FORMAT1 register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_Get(uint32_t instance) +{ + return ATON_RECBUF_FORMAT1_GET(instance); +} + + +/** + * Write the content of the FORMAT1 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_RECBUF_FORMAT1_Set(uint32_t instance, uint32_t data) +{ + ATON_RECBUF_FORMAT1_SET(instance, data); +} + + +/* --------------------------------------------------------- ACTCHIN field of the FORMAT1 register ---------------------------------------------------------- */ + +/** Description of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_DESC "Number of Active Input Channels" + +/** Offset of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_LSB 0UL + +/** Size in bits of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_W (2UL) + +/** Mask for retrieving the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_DT 0x0UL + +/** Access rights of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_AC "RW" + +/** Check whether access to the ACTCHIN field of the FORMAT1 register is secured or not. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_S 0 + +/** Check whether access to the ACTCHIN field of the FORMAT1 register is privileged or not. */ +#define ATON_RECBUF_FORMAT1_ACTCHIN_P 0 + +/** Read the content of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_GET_ACTCHIN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT1_ACTCHIN_LSB, ATON_RECBUF_FORMAT1_ACTCHIN_W) + +/** Modify the content of the ACTCHIN field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_SET_ACTCHIN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT1_ACTCHIN_LSB, ATON_RECBUF_FORMAT1_ACTCHIN_W, DATA) + + +/** + * Get the description of the ACTCHIN field of FORMAT1 register. + * + * \return the description of the ACTCHIN field of FORMAT1 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT1_ACTCHIN_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT1_ACTCHIN_DESC; +} + + +/** + * Read the content of the ACTCHIN field of the FORMAT1 register. + * + * \param[in] reg is the value of the FORMAT1 register + * + * \return the content of the ACTCHIN field belonging to FORMAT1 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_Get_ACTCHIN(uint32_t reg) +{ + return ATON_RECBUF_FORMAT1_GET_ACTCHIN(reg); +} + + +/** + * Write the content of the ACTCHIN field of the FORMAT1 register. + * + * \param[in] reg is the value of the FORMAT1 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ACTCHIN field belonging to FORMAT1 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_Set_ACTCHIN(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_FORMAT1_SET_ACTCHIN(reg, data); +} + + +/* --------------------------------------------------------- MEMBMARK field of the FORMAT1 register --------------------------------------------------------- */ + +/** Description of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_DESC "Bookmark for the RAM Partitioning for Input Stream 0" + +/** Offset of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_LSB 4UL + +/** Size in bits of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_W (10UL) + +/** Mask for retrieving the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_MASK ATON_FIELD_MASK(4UL, 10UL) + +/** Reset value of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_DT 0x0UL + +/** Access rights of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_AC "RW" + +/** Check whether access to the MEMBMARK field of the FORMAT1 register is secured or not. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_S 0 + +/** Check whether access to the MEMBMARK field of the FORMAT1 register is privileged or not. */ +#define ATON_RECBUF_FORMAT1_MEMBMARK_P 0 + +/** Read the content of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_GET_MEMBMARK(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT1_MEMBMARK_LSB, ATON_RECBUF_FORMAT1_MEMBMARK_W) + +/** Modify the content of the MEMBMARK field of the FORMAT1 register. */ +#define ATON_RECBUF_FORMAT1_SET_MEMBMARK(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT1_MEMBMARK_LSB, ATON_RECBUF_FORMAT1_MEMBMARK_W, DATA) + + +/** + * Get the description of the MEMBMARK field of FORMAT1 register. + * + * \return the description of the MEMBMARK field of FORMAT1 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT1_MEMBMARK_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT1_MEMBMARK_DESC; +} + + +/** + * Read the content of the MEMBMARK field of the FORMAT1 register. + * + * \param[in] reg is the value of the FORMAT1 register + * + * \return the content of the MEMBMARK field belonging to FORMAT1 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_Get_MEMBMARK(uint32_t reg) +{ + return ATON_RECBUF_FORMAT1_GET_MEMBMARK(reg); +} + + +/** + * Write the content of the MEMBMARK field of the FORMAT1 register. + * + * \param[in] reg is the value of the FORMAT1 register + * \param[in] data is 10-bit value that must be written to the field + * + * \return the new content of the MEMBMARK field belonging to FORMAT1 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT1_Set_MEMBMARK(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_FORMAT1_SET_MEMBMARK(reg, data); +} + + +/* ****************************************************** FORMAT2 register of one of the RECBUF Units ******************************************************* */ + +/** Offset of the FORMAT2 register from the base address of the RECBUF Unit. */ +#define ATON_RECBUF_FORMAT2_OFFSET 0x10UL + +/** Reset value of the FORMAT2 register of the RECBUF Unit. */ +#define ATON_RECBUF_FORMAT2_DT \ + (ATON_RECBUF_FORMAT2_ACTCHIN_DT << ATON_RECBUF_FORMAT2_ACTCHIN_LSB) | \ + (ATON_RECBUF_FORMAT2_MEMBMARK_DT << ATON_RECBUF_FORMAT2_MEMBMARK_LSB) + + + +/** Description of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_DESC "Number of Input/Output used channels and linetype for Output Stream 2" + +/** Address of the FORMAT2 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT2_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_FORMAT2_OFFSET) + +/** Get the content of the FORMAT2 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT2_ADDR(UNIT))) + +/** Set the content of the FORMAT2 register of one of the RECBUF Units. */ +#define ATON_RECBUF_FORMAT2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of FORMAT2 register. + * + * \return the description of FORMAT2 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT2_GetDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT2_DESC; +} + + +/** + * Get the offset of the FORMAT2 register. + * + * \return the offset of FORMAT2 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_GetOffset(void) +{ + return ATON_RECBUF_FORMAT2_OFFSET; +} + + +/** + * Get the address of the FORMAT2 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT2 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of FORMAT2 register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_GetAddr(uint32_t instance) +{ + return ATON_RECBUF_FORMAT2_ADDR(instance); +} + + +/** + * Read the content of the FORMAT2 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT2 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of FORMAT2 register belonging to Unit having index \e instance among the RECBUF Units + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_Get(uint32_t instance) +{ + return ATON_RECBUF_FORMAT2_GET(instance); +} + + +/** + * Write the content of the FORMAT2 register. + * + * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT2 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_RECBUF_FORMAT2_Set(uint32_t instance, uint32_t data) +{ + ATON_RECBUF_FORMAT2_SET(instance, data); +} + + +/* --------------------------------------------------------- ACTCHIN field of the FORMAT2 register ---------------------------------------------------------- */ + +/** Description of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_DESC "Number of Active Input Channels" + +/** Offset of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_LSB 0UL + +/** Size in bits of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_W (2UL) + +/** Mask for retrieving the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_MASK ATON_FIELD_MASK(0UL, 2UL) + +/** Reset value of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_DT 0x0UL + +/** Access rights of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_AC "RW" + +/** Check whether access to the ACTCHIN field of the FORMAT2 register is secured or not. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_S 0 + +/** Check whether access to the ACTCHIN field of the FORMAT2 register is privileged or not. */ +#define ATON_RECBUF_FORMAT2_ACTCHIN_P 0 + +/** Read the content of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_GET_ACTCHIN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT2_ACTCHIN_LSB, ATON_RECBUF_FORMAT2_ACTCHIN_W) + +/** Modify the content of the ACTCHIN field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_SET_ACTCHIN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT2_ACTCHIN_LSB, ATON_RECBUF_FORMAT2_ACTCHIN_W, DATA) + + +/** + * Get the description of the ACTCHIN field of FORMAT2 register. + * + * \return the description of the ACTCHIN field of FORMAT2 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT2_ACTCHIN_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT2_ACTCHIN_DESC; +} + + +/** + * Read the content of the ACTCHIN field of the FORMAT2 register. + * + * \param[in] reg is the value of the FORMAT2 register + * + * \return the content of the ACTCHIN field belonging to FORMAT2 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_Get_ACTCHIN(uint32_t reg) +{ + return ATON_RECBUF_FORMAT2_GET_ACTCHIN(reg); +} + + +/** + * Write the content of the ACTCHIN field of the FORMAT2 register. + * + * \param[in] reg is the value of the FORMAT2 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the ACTCHIN field belonging to FORMAT2 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_Set_ACTCHIN(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_FORMAT2_SET_ACTCHIN(reg, data); +} + + +/* --------------------------------------------------------- MEMBMARK field of the FORMAT2 register --------------------------------------------------------- */ + +/** Description of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_DESC "Bookmark for the RAM Partitioning for Input Stream 0" + +/** Offset of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_LSB 4UL + +/** Size in bits of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_W (10UL) + +/** Mask for retrieving the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_MASK ATON_FIELD_MASK(4UL, 10UL) + +/** Reset value of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_DT 0x0UL + +/** Access rights of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_AC "RW" + +/** Check whether access to the MEMBMARK field of the FORMAT2 register is secured or not. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_S 0 + +/** Check whether access to the MEMBMARK field of the FORMAT2 register is privileged or not. */ +#define ATON_RECBUF_FORMAT2_MEMBMARK_P 0 + +/** Read the content of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_GET_MEMBMARK(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT2_MEMBMARK_LSB, ATON_RECBUF_FORMAT2_MEMBMARK_W) + +/** Modify the content of the MEMBMARK field of the FORMAT2 register. */ +#define ATON_RECBUF_FORMAT2_SET_MEMBMARK(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT2_MEMBMARK_LSB, ATON_RECBUF_FORMAT2_MEMBMARK_W, DATA) + + +/** + * Get the description of the MEMBMARK field of FORMAT2 register. + * + * \return the description of the MEMBMARK field of FORMAT2 register + */ + +static inline const int8_t *ATON_RECBUF_FORMAT2_MEMBMARK_GetdDesc(void) +{ + return (const int8_t *)ATON_RECBUF_FORMAT2_MEMBMARK_DESC; +} + + +/** + * Read the content of the MEMBMARK field of the FORMAT2 register. + * + * \param[in] reg is the value of the FORMAT2 register + * + * \return the content of the MEMBMARK field belonging to FORMAT2 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_Get_MEMBMARK(uint32_t reg) +{ + return ATON_RECBUF_FORMAT2_GET_MEMBMARK(reg); +} + + +/** + * Write the content of the MEMBMARK field of the FORMAT2 register. + * + * \param[in] reg is the value of the FORMAT2 register + * \param[in] data is 10-bit value that must be written to the field + * + * \return the new content of the MEMBMARK field belonging to FORMAT2 register + */ + +static inline uint32_t ATON_RECBUF_FORMAT2_Set_MEMBMARK(uint32_t reg, uint32_t data) +{ + return ATON_RECBUF_FORMAT2_SET_MEMBMARK(reg, data); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* EPOCHCTRL Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of EPOCHCTRL Unit instances. */ +#define ATON_EPOCHCTRL_NUM 1 + +/** + * \name Structures, macros and functions of the EPOCHCTRL Units + */ +/*@{*/ + +/** + * Registers of the EPOCHCTRL Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e ADDR register (Blob fetch address). */ + uint32_t ADDR; + + /** \e IRQ register (Interrupt status register). */ + uint32_t IRQ; + + /** \e ENCR_LSB register (Encryption ID LSB (RO when CTRL.RUNNING)). */ + uint32_t ENCR_LSB; + + /** \e ENCR_MSB register (Encryption ID MSB (RO when CTRL.RUNNING)). */ + uint32_t ENCR_MSB; + + /** \e CID_CACHE register (Compartment ID / Cache register (RO when CTRL.RUNNING)). */ + uint32_t CID_CACHE; + + /** \e LABEL register (Label register). */ + uint32_t LABEL; + + /** \e BC register (Blob opcode counter). */ + uint32_t BC; + + /** \e ACC register (Accumulator). */ + uint32_t ACC; + +} ATON_EPOCHCTRL_t; + + +/** Return the pointer to one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL(UNIT) ((ATON_EPOCHCTRL_t *)(intptr_t)ATON_EPOCHCTRL_BASE(UNIT)) + + +/** Name of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_NAME(UNIT) \ + (((UNIT) == 0) ? "EPOCHCTRL0" : "") + + +/** Version of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_VERSION "1.1" + + +/** Description of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_DESC(UNIT) \ + (((UNIT) == 0) ? "Epoch Controller 0" : "") + + +/** Base address of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_BASE(UNIT) \ + (ATON_BASE + 0x1e000UL + ((UNIT) * 0x0UL)) + +/** Size in bytes of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_SIZE 0x1000UL + + +/** + * Get the name of one of the EPOCHCTRL Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) + * + * \return the name of Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline const int8_t *ATON_EPOCHCTRL_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"EPOCHCTRL0"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the EPOCHCTRL Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) + * + * \return the description of Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline const int8_t *ATON_EPOCHCTRL_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Epoch Controller 0"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the EPOCHCTRL Units. + * + * \return the version of the EPOCHCTRL Units + */ + +static inline const int8_t *ATON_EPOCHCTRL_GetVersion(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION; +} + + +/** + * Get the base address of one of the EPOCHCTRL Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) + * + * \return the base address of Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_GetBase(uint32_t instance) +{ + return ATON_EPOCHCTRL_BASE(instance); +} + + +/** + * Get the size in bytes of the EPOCHCTRL Units. + * + * \return the size in bytes of the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_GetSize(void) +{ + return ATON_EPOCHCTRL_SIZE; +} + + +/* ****************************************************** CTRL register of one of the EPOCHCTRL Units ******************************************************* */ + +/** Offset of the CTRL register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_CTRL_DT \ + (ATON_EPOCHCTRL_CTRL_EN_DT << ATON_EPOCHCTRL_CTRL_EN_LSB) | \ + (ATON_EPOCHCTRL_CTRL_CLR_DT << ATON_EPOCHCTRL_CTRL_CLR_LSB) | \ + (ATON_EPOCHCTRL_CTRL_AUTOCLR_DT << ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB) | \ + (ATON_EPOCHCTRL_CTRL_SM_DT << ATON_EPOCHCTRL_CTRL_SM_LSB) | \ + (ATON_EPOCHCTRL_CTRL_CONFCLR_DT << ATON_EPOCHCTRL_CTRL_CONFCLR_LSB) | \ + (ATON_EPOCHCTRL_CTRL_RUNNING_DT << ATON_EPOCHCTRL_CTRL_RUNNING_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_CTRL_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_GetOffset(void) +{ + return ATON_EPOCHCTRL_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CTRL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CTRL register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_EPOCHCTRL_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_EPOCHCTRL_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_EN_DESC "Enables the Epoch Controller" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_EPOCHCTRL_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_EPOCHCTRL_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_EN_LSB, ATON_EPOCHCTRL_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_EN_LSB, ATON_EPOCHCTRL_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_EN(uint32_t reg) +{ + return ATON_EPOCHCTRL_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CLR_DESC "Clears all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_EPOCHCTRL_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_EPOCHCTRL_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CLR_LSB, ATON_EPOCHCTRL_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CLR_LSB, ATON_EPOCHCTRL_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_EPOCHCTRL_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- AUTOCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_DESC "Autoclear on stop (RO when CTRL.RUNNING)" + +/** Offset of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB 2UL + +/** Size in bits of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_W (1UL) + +/** Mask for retrieving the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_DT 0x0UL + +/** Access rights of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_AC "RW" + +/** Check whether access to the AUTOCLR field of the CTRL register is secured or not. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_S 0 + +/** Check whether access to the AUTOCLR field of the CTRL register is privileged or not. */ +#define ATON_EPOCHCTRL_CTRL_AUTOCLR_P 0 + +/** Read the content of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_GET_AUTOCLR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB, ATON_EPOCHCTRL_CTRL_AUTOCLR_W) + +/** Modify the content of the AUTOCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SET_AUTOCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB, ATON_EPOCHCTRL_CTRL_AUTOCLR_W, DATA) + + +/** + * Get the description of the AUTOCLR field of CTRL register. + * + * \return the description of the AUTOCLR field of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_AUTOCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_AUTOCLR_DESC; +} + + +/** + * Read the content of the AUTOCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the AUTOCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_AUTOCLR(uint32_t reg) +{ + return ATON_EPOCHCTRL_CTRL_GET_AUTOCLR(reg); +} + + +/** + * Write the content of the AUTOCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the AUTOCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_AUTOCLR(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CTRL_SET_AUTOCLR(reg, data); +} + + +/* ------------------------------------------------------------- SM field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SM_DESC "Step mode (RO when CTRL.RUNNING)" + +/** Offset of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SM_LSB 3UL + +/** Size in bits of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SM_W (1UL) + +/** Mask for retrieving the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SM_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SM_DT 0x0UL + +/** Access rights of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SM_AC "RW" + +/** Check whether access to the SM field of the CTRL register is secured or not. */ +#define ATON_EPOCHCTRL_CTRL_SM_S 0 + +/** Check whether access to the SM field of the CTRL register is privileged or not. */ +#define ATON_EPOCHCTRL_CTRL_SM_P 0 + +/** Read the content of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_GET_SM(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_SM_LSB, ATON_EPOCHCTRL_CTRL_SM_W) + +/** Modify the content of the SM field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SET_SM(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_SM_LSB, ATON_EPOCHCTRL_CTRL_SM_W, DATA) + + +/** + * Get the description of the SM field of CTRL register. + * + * \return the description of the SM field of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_SM_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_SM_DESC; +} + + +/** + * Read the content of the SM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the SM field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_SM(uint32_t reg) +{ + return ATON_EPOCHCTRL_CTRL_GET_SM(reg); +} + + +/** + * Write the content of the SM field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SM field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_SM(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CTRL_SET_SM(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared) (RO when CTRL.RUNNING)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_EPOCHCTRL_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CONFCLR_LSB, ATON_EPOCHCTRL_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CONFCLR_LSB, ATON_EPOCHCTRL_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_EPOCHCTRL_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CTRL_SET_CONFCLR(reg, data); +} + + +/* ----------------------------------------------------------- RUNNING field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_DESC "Running condition" + +/** Offset of the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_LSB 31UL + +/** Size in bits of the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_W (1UL) + +/** Mask for retrieving the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_MASK ATON_FIELD_MASK(31UL, 1UL) + +/** Reset value of the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_DT 0x0UL + +/** Access rights of the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_AC "R" + +/** Check whether access to the RUNNING field of the CTRL register is secured or not. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_S 0 + +/** Check whether access to the RUNNING field of the CTRL register is privileged or not. */ +#define ATON_EPOCHCTRL_CTRL_RUNNING_P 0 + +/** Read the content of the RUNNING field of the CTRL register. */ +#define ATON_EPOCHCTRL_CTRL_GET_RUNNING(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_RUNNING_LSB, ATON_EPOCHCTRL_CTRL_RUNNING_W) + + +/** + * Get the description of the RUNNING field of CTRL register. + * + * \return the description of the RUNNING field of CTRL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CTRL_RUNNING_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CTRL_RUNNING_DESC; +} + + +/** + * Read the content of the RUNNING field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the RUNNING field belonging to CTRL register + */ + +static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_RUNNING(uint32_t reg) +{ + return ATON_EPOCHCTRL_CTRL_GET_RUNNING(reg); +} + + +/* ***************************************************** VERSION register of one of the EPOCHCTRL Units ***************************************************** */ + +/** Offset of the VERSION register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_VERSION_DT \ + (ATON_EPOCHCTRL_VERSION_TYPE_DT << ATON_EPOCHCTRL_VERSION_TYPE_LSB) | \ + (ATON_EPOCHCTRL_VERSION_MINOR_DT << ATON_EPOCHCTRL_VERSION_MINOR_LSB) | \ + (ATON_EPOCHCTRL_VERSION_MAJOR_DT << ATON_EPOCHCTRL_VERSION_MAJOR_LSB) | \ + (ATON_EPOCHCTRL_VERSION_I_IRQ_DT << ATON_EPOCHCTRL_VERSION_I_IRQ_LSB) | \ + (ATON_EPOCHCTRL_VERSION_ENCR_DT << ATON_EPOCHCTRL_VERSION_ENCR_LSB) | \ + (ATON_EPOCHCTRL_VERSION_CACHE_DT << ATON_EPOCHCTRL_VERSION_CACHE_LSB) | \ + (ATON_EPOCHCTRL_VERSION_CID_DT << ATON_EPOCHCTRL_VERSION_CID_LSB) | \ + (ATON_EPOCHCTRL_VERSION_EXTSYNC_DT << ATON_EPOCHCTRL_VERSION_EXTSYNC_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_VERSION_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_GetOffset(void) +{ + return ATON_EPOCHCTRL_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the VERSION register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_DT 0x21UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_TYPE_LSB, ATON_EPOCHCTRL_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_DT 0x1UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_MINOR_LSB, ATON_EPOCHCTRL_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_MAJOR_LSB, ATON_EPOCHCTRL_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- I_IRQ field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_DESC "Number of interrupt monitored" + +/** Offset of the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_LSB 16UL + +/** Size in bits of the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_W (8UL) + +/** Mask for retrieving the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_MASK ATON_FIELD_MASK(16UL, 8UL) + +/** Reset value of the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_DT 0x4UL + +/** Access rights of the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_AC "R" + +/** Check whether access to the I_IRQ field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_S 0 + +/** Check whether access to the I_IRQ field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_I_IRQ_P 0 + +/** Read the content of the I_IRQ field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_I_IRQ(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_I_IRQ_LSB, ATON_EPOCHCTRL_VERSION_I_IRQ_W) + + +/** + * Get the description of the I_IRQ field of VERSION register. + * + * \return the description of the I_IRQ field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_I_IRQ_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_I_IRQ_DESC; +} + + +/** + * Read the content of the I_IRQ field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the I_IRQ field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_I_IRQ(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_I_IRQ(reg); +} + + +/* ----------------------------------------------------------- ENCR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_DESC "Encription support" + +/** Offset of the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_LSB 24UL + +/** Size in bits of the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_W (1UL) + +/** Mask for retrieving the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_MASK ATON_FIELD_MASK(24UL, 1UL) + +/** Reset value of the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_DT 0x1UL + +/** Access rights of the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_AC "R" + +/** Check whether access to the ENCR field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_S 0 + +/** Check whether access to the ENCR field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_ENCR_P 0 + +/** Read the content of the ENCR field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_ENCR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_ENCR_LSB, ATON_EPOCHCTRL_VERSION_ENCR_W) + + +/** + * Get the description of the ENCR field of VERSION register. + * + * \return the description of the ENCR field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_ENCR_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_ENCR_DESC; +} + + +/** + * Read the content of the ENCR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the ENCR field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_ENCR(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_ENCR(reg); +} + + +/* ---------------------------------------------------------- CACHE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_DESC "Cache support" + +/** Offset of the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_LSB 25UL + +/** Size in bits of the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_W (1UL) + +/** Mask for retrieving the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_MASK ATON_FIELD_MASK(25UL, 1UL) + +/** Reset value of the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_DT 0x1UL + +/** Access rights of the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_AC "R" + +/** Check whether access to the CACHE field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_S 0 + +/** Check whether access to the CACHE field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_CACHE_P 0 + +/** Read the content of the CACHE field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_CACHE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_CACHE_LSB, ATON_EPOCHCTRL_VERSION_CACHE_W) + + +/** + * Get the description of the CACHE field of VERSION register. + * + * \return the description of the CACHE field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_CACHE_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_CACHE_DESC; +} + + +/** + * Read the content of the CACHE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the CACHE field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_CACHE(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_CACHE(reg); +} + + +/* ----------------------------------------------------------- CID field of the VERSION register ------------------------------------------------------------ */ + +/** Description of the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CID_DESC "Compartment ID support" + +/** Offset of the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CID_LSB 26UL + +/** Size in bits of the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CID_W (1UL) + +/** Mask for retrieving the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CID_MASK ATON_FIELD_MASK(26UL, 1UL) + +/** Reset value of the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CID_DT 0x1UL + +/** Access rights of the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_CID_AC "R" + +/** Check whether access to the CID field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_CID_S 0 + +/** Check whether access to the CID field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_CID_P 0 + +/** Read the content of the CID field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_CID(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_CID_LSB, ATON_EPOCHCTRL_VERSION_CID_W) + + +/** + * Get the description of the CID field of VERSION register. + * + * \return the description of the CID field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_CID_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_CID_DESC; +} + + +/** + * Read the content of the CID field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the CID field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_CID(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_CID(reg); +} + + +/* --------------------------------------------------------- EXTSYNC field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_DESC "External triggers support" + +/** Offset of the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_LSB 27UL + +/** Size in bits of the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_W (1UL) + +/** Mask for retrieving the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_MASK ATON_FIELD_MASK(27UL, 1UL) + +/** Reset value of the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_DT 0x1UL + +/** Access rights of the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_AC "R" + +/** Check whether access to the EXTSYNC field of the VERSION register is secured or not. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_S 0 + +/** Check whether access to the EXTSYNC field of the VERSION register is privileged or not. */ +#define ATON_EPOCHCTRL_VERSION_EXTSYNC_P 0 + +/** Read the content of the EXTSYNC field of the VERSION register. */ +#define ATON_EPOCHCTRL_VERSION_GET_EXTSYNC(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_EXTSYNC_LSB, ATON_EPOCHCTRL_VERSION_EXTSYNC_W) + + +/** + * Get the description of the EXTSYNC field of VERSION register. + * + * \return the description of the EXTSYNC field of VERSION register + */ + +static inline const int8_t *ATON_EPOCHCTRL_VERSION_EXTSYNC_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_VERSION_EXTSYNC_DESC; +} + + +/** + * Read the content of the EXTSYNC field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the EXTSYNC field belonging to VERSION register + */ + +static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_EXTSYNC(uint32_t reg) +{ + return ATON_EPOCHCTRL_VERSION_GET_EXTSYNC(reg); +} + + +/* ****************************************************** ADDR register of one of the EPOCHCTRL Units ******************************************************* */ + +/** Offset of the ADDR register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ADDR_OFFSET 0x8UL + +/** Reset value of the ADDR register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ADDR_DT \ + (ATON_EPOCHCTRL_ADDR_REG_DT << ATON_EPOCHCTRL_ADDR_REG_LSB) + + + +/** Description of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_DESC "Blob fetch address" + +/** Address of the ADDR register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ADDR_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ADDR_OFFSET) + +/** Get the content of the ADDR register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ADDR_ADDR(UNIT))) + +/** Set the content of the ADDR register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ADDR_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ADDR register. + * + * \return the description of ADDR register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ADDR_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ADDR_DESC; +} + + +/** + * Get the offset of the ADDR register. + * + * \return the offset of ADDR register + */ + +static inline uint32_t ATON_EPOCHCTRL_ADDR_GetOffset(void) +{ + return ATON_EPOCHCTRL_ADDR_OFFSET; +} + + +/** + * Get the address of the ADDR register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ADDR register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of ADDR register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ADDR_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_ADDR_ADDR(instance); +} + + +/** + * Read the content of the ADDR register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ADDR register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of ADDR register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ADDR_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_ADDR_GET(instance); +} + + +/** + * Write the content of the ADDR register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ADDR register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_EPOCHCTRL_ADDR_Set(uint32_t instance, uint32_t data) +{ + ATON_EPOCHCTRL_ADDR_SET(instance, data); +} + + +/* ------------------------------------------------------------- REG field of the ADDR register ------------------------------------------------------------- */ + +/** Description of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_REG_DESC "Blob fetch address. Must be 64 bit aligned (values not 64 bits aligned will be refused) (RO when CTRL.RUNNING)" + +/** Offset of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_REG_LSB 0UL + +/** Size in bits of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_REG_W (32UL) + +/** Mask for retrieving the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_REG_DT 0x0UL + +/** Access rights of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_REG_AC "RW" + +/** Check whether access to the REG field of the ADDR register is secured or not. */ +#define ATON_EPOCHCTRL_ADDR_REG_S 0 + +/** Check whether access to the REG field of the ADDR register is privileged or not. */ +#define ATON_EPOCHCTRL_ADDR_REG_P 0 + +/** Read the content of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ADDR_REG_LSB, ATON_EPOCHCTRL_ADDR_REG_W) + +/** Modify the content of the REG field of the ADDR register. */ +#define ATON_EPOCHCTRL_ADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ADDR_REG_LSB, ATON_EPOCHCTRL_ADDR_REG_W, DATA) + + +/** + * Get the description of the REG field of ADDR register. + * + * \return the description of the REG field of ADDR register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ADDR_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ADDR_REG_DESC; +} + + +/** + * Read the content of the REG field of the ADDR register. + * + * \param[in] reg is the value of the ADDR register + * + * \return the content of the REG field belonging to ADDR register + */ + +static inline uint32_t ATON_EPOCHCTRL_ADDR_Get_REG(uint32_t reg) +{ + return ATON_EPOCHCTRL_ADDR_GET_REG(reg); +} + + +/** + * Write the content of the REG field of the ADDR register. + * + * \param[in] reg is the value of the ADDR register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the REG field belonging to ADDR register + */ + +static inline uint32_t ATON_EPOCHCTRL_ADDR_Set_REG(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_ADDR_SET_REG(reg, data); +} + + +/* ******************************************************* IRQ register of one of the EPOCHCTRL Units ******************************************************* */ + +/** Offset of the IRQ register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_IRQ_OFFSET 0xcUL + +/** Reset value of the IRQ register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_IRQ_DT \ + (ATON_EPOCHCTRL_IRQ_IRQ_DT << ATON_EPOCHCTRL_IRQ_IRQ_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DT << ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_CONF_DT << ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_START_DT << ATON_EPOCHCTRL_IRQ_ERR_START_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DT << ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DT << ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_SRC_DT << ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB) | \ + (ATON_EPOCHCTRL_IRQ_ERR_EVT_DT << ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB) | \ + (ATON_EPOCHCTRL_IRQ_SM_DT << ATON_EPOCHCTRL_IRQ_SM_LSB) + + + +/** Description of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_DESC "Interrupt status register" + +/** Address of the IRQ register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_IRQ_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_IRQ_OFFSET) + +/** Get the content of the IRQ register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_IRQ_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_IRQ_ADDR(UNIT))) + +/** Set the content of the IRQ register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_IRQ_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_IRQ_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of IRQ register. + * + * \return the description of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_DESC; +} + + +/** + * Get the offset of the IRQ register. + * + * \return the offset of IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_GetOffset(void) +{ + return ATON_EPOCHCTRL_IRQ_OFFSET; +} + + +/** + * Get the address of the IRQ register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the IRQ register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of IRQ register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_IRQ_ADDR(instance); +} + + +/** + * Read the content of the IRQ register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the IRQ register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of IRQ register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_IRQ_GET(instance); +} + + +/** + * Write the content of the IRQ register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the IRQ register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_EPOCHCTRL_IRQ_Set(uint32_t instance, uint32_t data) +{ + ATON_EPOCHCTRL_IRQ_SET(instance, data); +} + + +/* ------------------------------------------------------------- IRQ field of the IRQ register -------------------------------------------------------------- */ + +/** Description of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_DESC "Interrupt status (write 1 to acknowledge)" + +/** Offset of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_LSB 0UL + +/** Size in bits of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_W (1UL) + +/** Mask for retrieving the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_DT 0x0UL + +/** Access rights of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_AC "RW" + +/** Check whether access to the IRQ field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_S 0 + +/** Check whether access to the IRQ field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_IRQ_P 0 + +/** Read the content of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_IRQ(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_IRQ_LSB, ATON_EPOCHCTRL_IRQ_IRQ_W) + +/** Modify the content of the IRQ field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_IRQ(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_IRQ_LSB, ATON_EPOCHCTRL_IRQ_IRQ_W, DATA) + + +/** + * Get the description of the IRQ field of IRQ register. + * + * \return the description of the IRQ field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_IRQ_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_IRQ_DESC; +} + + +/** + * Read the content of the IRQ field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the IRQ field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_IRQ(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_IRQ(reg); +} + + +/** + * Write the content of the IRQ field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the IRQ field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_IRQ(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_IRQ(reg, data); +} + + +/* --------------------------------------------------------- ERR_BUSPORT field of the IRQ register ---------------------------------------------------------- */ + +/** Description of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DESC "Error on busport IF interrupt status (write 1 to acknowledge)" + +/** Offset of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB 1UL + +/** Size in bits of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_W (1UL) + +/** Mask for retrieving the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DT 0x0UL + +/** Access rights of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_AC "RW" + +/** Check whether access to the ERR_BUSPORT field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_S 0 + +/** Check whether access to the ERR_BUSPORT field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_P 0 + +/** Read the content of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_BUSPORT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_W) + +/** Modify the content of the ERR_BUSPORT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_BUSPORT(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_W, DATA) + + +/** + * Get the description of the ERR_BUSPORT field of IRQ register. + * + * \return the description of the ERR_BUSPORT field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DESC; +} + + +/** + * Read the content of the ERR_BUSPORT field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_BUSPORT field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_BUSPORT(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_BUSPORT(reg); +} + + +/** + * Write the content of the ERR_BUSPORT field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_BUSPORT field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_BUSPORT(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_BUSPORT(reg, data); +} + + +/* ----------------------------------------------------------- ERR_CONF field of the IRQ register ----------------------------------------------------------- */ + +/** Description of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_DESC "Error on configuration IF interrupt status (write 1 to acknowledge)" + +/** Offset of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB 2UL + +/** Size in bits of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_W (1UL) + +/** Mask for retrieving the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_MASK ATON_FIELD_MASK(2UL, 1UL) + +/** Reset value of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_DT 0x0UL + +/** Access rights of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_AC "RW" + +/** Check whether access to the ERR_CONF field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_S 0 + +/** Check whether access to the ERR_CONF field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_CONF_P 0 + +/** Read the content of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_CONF(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB, ATON_EPOCHCTRL_IRQ_ERR_CONF_W) + +/** Modify the content of the ERR_CONF field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_CONF(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB, ATON_EPOCHCTRL_IRQ_ERR_CONF_W, DATA) + + +/** + * Get the description of the ERR_CONF field of IRQ register. + * + * \return the description of the ERR_CONF field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_CONF_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_CONF_DESC; +} + + +/** + * Read the content of the ERR_CONF field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_CONF field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_CONF(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_CONF(reg); +} + + +/** + * Write the content of the ERR_CONF field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_CONF field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_CONF(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_CONF(reg, data); +} + + +/* ---------------------------------------------------------- ERR_START field of the IRQ register ----------------------------------------------------------- */ + +/** Description of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_DESC "Error on start (wrong blob ID) interrupt status (write 1 to acknowledge)" + +/** Offset of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_LSB 3UL + +/** Size in bits of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_W (1UL) + +/** Mask for retrieving the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_DT 0x0UL + +/** Access rights of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_AC "RW" + +/** Check whether access to the ERR_START field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_S 0 + +/** Check whether access to the ERR_START field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_START_P 0 + +/** Read the content of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_START(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_START_LSB, ATON_EPOCHCTRL_IRQ_ERR_START_W) + +/** Modify the content of the ERR_START field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_START(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_START_LSB, ATON_EPOCHCTRL_IRQ_ERR_START_W, DATA) + + +/** + * Get the description of the ERR_START field of IRQ register. + * + * \return the description of the ERR_START field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_START_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_START_DESC; +} + + +/** + * Read the content of the ERR_START field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_START field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_START(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_START(reg); +} + + +/** + * Write the content of the ERR_START field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_START field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_START(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_START(reg, data); +} + + +/* --------------------------------------------------------- ERR_TIMEOUT field of the IRQ register ---------------------------------------------------------- */ + +/** Description of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DESC "Error on timeout interrupt status (write 1 to acknowledge)" + +/** Offset of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB 4UL + +/** Size in bits of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_W (1UL) + +/** Mask for retrieving the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DT 0x0UL + +/** Access rights of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_AC "RW" + +/** Check whether access to the ERR_TIMEOUT field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_S 0 + +/** Check whether access to the ERR_TIMEOUT field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_P 0 + +/** Read the content of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_TIMEOUT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_W) + +/** Modify the content of the ERR_TIMEOUT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_TIMEOUT(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_W, DATA) + + +/** + * Get the description of the ERR_TIMEOUT field of IRQ register. + * + * \return the description of the ERR_TIMEOUT field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DESC; +} + + +/** + * Read the content of the ERR_TIMEOUT field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_TIMEOUT field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_TIMEOUT(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_TIMEOUT(reg); +} + + +/** + * Write the content of the ERR_TIMEOUT field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_TIMEOUT field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_TIMEOUT(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_TIMEOUT(reg, data); +} + + +/* ---------------------------------------------------------- ERR_UNKOP field of the IRQ register ----------------------------------------------------------- */ + +/** Description of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DESC "Error on unknown opcode intwerrupt status (write 1 to acknowledge)" + +/** Offset of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB 5UL + +/** Size in bits of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_W (1UL) + +/** Mask for retrieving the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DT 0x0UL + +/** Access rights of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_AC "RW" + +/** Check whether access to the ERR_UNKOP field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_S 0 + +/** Check whether access to the ERR_UNKOP field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_P 0 + +/** Read the content of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_UNKOP(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_W) + +/** Modify the content of the ERR_UNKOP field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_UNKOP(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_W, DATA) + + +/** + * Get the description of the ERR_UNKOP field of IRQ register. + * + * \return the description of the ERR_UNKOP field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_UNKOP_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DESC; +} + + +/** + * Read the content of the ERR_UNKOP field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_UNKOP field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_UNKOP(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_UNKOP(reg); +} + + +/** + * Write the content of the ERR_UNKOP field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_UNKOP field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_UNKOP(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_UNKOP(reg, data); +} + + +/* ----------------------------------------------------------- ERR_SRC field of the IRQ register ------------------------------------------------------------ */ + +/** Description of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_DESC "Error on not supported source selection in WFI or WFT opcode" + +/** Offset of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB 6UL + +/** Size in bits of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_W (1UL) + +/** Mask for retrieving the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_MASK ATON_FIELD_MASK(6UL, 1UL) + +/** Reset value of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_DT 0x0UL + +/** Access rights of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_AC "RW" + +/** Check whether access to the ERR_SRC field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_S 0 + +/** Check whether access to the ERR_SRC field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_SRC_P 0 + +/** Read the content of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_SRC(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB, ATON_EPOCHCTRL_IRQ_ERR_SRC_W) + +/** Modify the content of the ERR_SRC field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_SRC(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB, ATON_EPOCHCTRL_IRQ_ERR_SRC_W, DATA) + + +/** + * Get the description of the ERR_SRC field of IRQ register. + * + * \return the description of the ERR_SRC field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_SRC_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_SRC_DESC; +} + + +/** + * Read the content of the ERR_SRC field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_SRC field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_SRC(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_SRC(reg); +} + + +/** + * Write the content of the ERR_SRC field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_SRC field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_SRC(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_SRC(reg, data); +} + + +/* ----------------------------------------------------------- ERR_EVT field of the IRQ register ------------------------------------------------------------ */ + +/** Description of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_DESC "Error on too big number of events to wait in WFT opcode" + +/** Offset of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB 7UL + +/** Size in bits of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_W (1UL) + +/** Mask for retrieving the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_MASK ATON_FIELD_MASK(7UL, 1UL) + +/** Reset value of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_DT 0x0UL + +/** Access rights of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_AC "RW" + +/** Check whether access to the ERR_EVT field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_S 0 + +/** Check whether access to the ERR_EVT field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_ERR_EVT_P 0 + +/** Read the content of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_ERR_EVT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB, ATON_EPOCHCTRL_IRQ_ERR_EVT_W) + +/** Modify the content of the ERR_EVT field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_ERR_EVT(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB, ATON_EPOCHCTRL_IRQ_ERR_EVT_W, DATA) + + +/** + * Get the description of the ERR_EVT field of IRQ register. + * + * \return the description of the ERR_EVT field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_EVT_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_EVT_DESC; +} + + +/** + * Read the content of the ERR_EVT field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the ERR_EVT field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_EVT(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_ERR_EVT(reg); +} + + +/** + * Write the content of the ERR_EVT field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ERR_EVT field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_EVT(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_ERR_EVT(reg, data); +} + + +/* -------------------------------------------------------------- SM field of the IRQ register -------------------------------------------------------------- */ + +/** Description of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SM_DESC "Step mode trigger (write 1 to trigger, write 0 has no effect). Read 1 if the opcode is executing" + +/** Offset of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SM_LSB 16UL + +/** Size in bits of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SM_W (1UL) + +/** Mask for retrieving the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SM_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SM_DT 0x0UL + +/** Access rights of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SM_AC "RW" + +/** Check whether access to the SM field of the IRQ register is secured or not. */ +#define ATON_EPOCHCTRL_IRQ_SM_S 0 + +/** Check whether access to the SM field of the IRQ register is privileged or not. */ +#define ATON_EPOCHCTRL_IRQ_SM_P 0 + +/** Read the content of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_GET_SM(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_SM_LSB, ATON_EPOCHCTRL_IRQ_SM_W) + +/** Modify the content of the SM field of the IRQ register. */ +#define ATON_EPOCHCTRL_IRQ_SET_SM(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_SM_LSB, ATON_EPOCHCTRL_IRQ_SM_W, DATA) + + +/** + * Get the description of the SM field of IRQ register. + * + * \return the description of the SM field of IRQ register + */ + +static inline const int8_t *ATON_EPOCHCTRL_IRQ_SM_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_IRQ_SM_DESC; +} + + +/** + * Read the content of the SM field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * + * \return the content of the SM field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_SM(uint32_t reg) +{ + return ATON_EPOCHCTRL_IRQ_GET_SM(reg); +} + + +/** + * Write the content of the SM field of the IRQ register. + * + * \param[in] reg is the value of the IRQ register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SM field belonging to IRQ register + */ + +static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_SM(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_IRQ_SET_SM(reg, data); +} + + +/* **************************************************** ENCR_LSB register of one of the EPOCHCTRL Units ***************************************************** */ + +/** Offset of the ENCR_LSB register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ENCR_LSB_OFFSET 0x10UL + +/** Reset value of the ENCR_LSB register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ENCR_LSB_DT \ + (ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DT << ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB) + + + +/** Description of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" + +/** Address of the ENCR_LSB register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ENCR_LSB_OFFSET) + +/** Get the content of the ENCR_LSB register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ENCR_LSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_LSB_ADDR(UNIT))) + +/** Set the content of the ENCR_LSB register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ENCR_LSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_LSB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ENCR_LSB register. + * + * \return the description of ENCR_LSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_LSB_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_LSB_DESC; +} + + +/** + * Get the offset of the ENCR_LSB register. + * + * \return the offset of ENCR_LSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_GetOffset(void) +{ + return ATON_EPOCHCTRL_ENCR_LSB_OFFSET; +} + + +/** + * Get the address of the ENCR_LSB register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_LSB register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of ENCR_LSB register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_ENCR_LSB_ADDR(instance); +} + + +/** + * Read the content of the ENCR_LSB register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_LSB register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of ENCR_LSB register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_ENCR_LSB_GET(instance); +} + + +/** + * Write the content of the ENCR_LSB register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_LSB register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_EPOCHCTRL_ENCR_LSB_Set(uint32_t instance, uint32_t data) +{ + ATON_EPOCHCTRL_ENCR_LSB_SET(instance, data); +} + + +/* --------------------------------------------------------- ID_LSB field of the ENCR_LSB register ---------------------------------------------------------- */ + +/** Description of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" + +/** Offset of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB 0UL + +/** Size in bits of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_W (32UL) + +/** Mask for retrieving the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DT 0x0UL + +/** Access rights of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_AC "RW" + +/** Check whether access to the ID_LSB field of the ENCR_LSB register is secured or not. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_S 0 + +/** Check whether access to the ID_LSB field of the ENCR_LSB register is privileged or not. */ +#define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_P 0 + +/** Read the content of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_GET_ID_LSB(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_W) + +/** Modify the content of the ID_LSB field of the ENCR_LSB register. */ +#define ATON_EPOCHCTRL_ENCR_LSB_SET_ID_LSB(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_W, DATA) + + +/** + * Get the description of the ID_LSB field of ENCR_LSB register. + * + * \return the description of the ID_LSB field of ENCR_LSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DESC; +} + + +/** + * Read the content of the ID_LSB field of the ENCR_LSB register. + * + * \param[in] reg is the value of the ENCR_LSB register + * + * \return the content of the ID_LSB field belonging to ENCR_LSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_Get_ID_LSB(uint32_t reg) +{ + return ATON_EPOCHCTRL_ENCR_LSB_GET_ID_LSB(reg); +} + + +/** + * Write the content of the ID_LSB field of the ENCR_LSB register. + * + * \param[in] reg is the value of the ENCR_LSB register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the ID_LSB field belonging to ENCR_LSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_Set_ID_LSB(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_ENCR_LSB_SET_ID_LSB(reg, data); +} + + +/* **************************************************** ENCR_MSB register of one of the EPOCHCTRL Units ***************************************************** */ + +/** Offset of the ENCR_MSB register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ENCR_MSB_OFFSET 0x14UL + +/** Reset value of the ENCR_MSB register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ENCR_MSB_DT \ + (ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DT << ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB) | \ + (ATON_EPOCHCTRL_ENCR_MSB_EN_DT << ATON_EPOCHCTRL_ENCR_MSB_EN_LSB) | \ + (ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DT << ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB) | \ + (ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DT << ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB) + + + +/** Description of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" + +/** Address of the ENCR_MSB register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ENCR_MSB_OFFSET) + +/** Get the content of the ENCR_MSB register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ENCR_MSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_MSB_ADDR(UNIT))) + +/** Set the content of the ENCR_MSB register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ENCR_MSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_MSB_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of ENCR_MSB register. + * + * \return the description of ENCR_MSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_DESC; +} + + +/** + * Get the offset of the ENCR_MSB register. + * + * \return the offset of ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_GetOffset(void) +{ + return ATON_EPOCHCTRL_ENCR_MSB_OFFSET; +} + + +/** + * Get the address of the ENCR_MSB register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_MSB register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of ENCR_MSB register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_ENCR_MSB_ADDR(instance); +} + + +/** + * Read the content of the ENCR_MSB register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_MSB register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of ENCR_MSB register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_ENCR_MSB_GET(instance); +} + + +/** + * Write the content of the ENCR_MSB register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_MSB register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_EPOCHCTRL_ENCR_MSB_Set(uint32_t instance, uint32_t data) +{ + ATON_EPOCHCTRL_ENCR_MSB_SET(instance, data); +} + + +/* --------------------------------------------------------- ID_MSB field of the ENCR_MSB register ---------------------------------------------------------- */ + +/** Description of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" + +/** Offset of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB 0UL + +/** Size in bits of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_W (11UL) + +/** Mask for retrieving the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_MASK ATON_FIELD_MASK(0UL, 11UL) + +/** Reset value of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DT 0x0UL + +/** Access rights of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_AC "RW" + +/** Check whether access to the ID_MSB field of the ENCR_MSB register is secured or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_S 0 + +/** Check whether access to the ID_MSB field of the ENCR_MSB register is privileged or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_P 0 + +/** Read the content of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_GET_ID_MSB(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_W) + +/** Modify the content of the ID_MSB field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_SET_ID_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_W, DATA) + + +/** + * Get the description of the ID_MSB field of ENCR_MSB register. + * + * \return the description of the ID_MSB field of ENCR_MSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DESC; +} + + +/** + * Read the content of the ID_MSB field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the ID_MSB field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_ID_MSB(uint32_t reg) +{ + return ATON_EPOCHCTRL_ENCR_MSB_GET_ID_MSB(reg); +} + + +/** + * Write the content of the ID_MSB field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 11-bit value that must be written to the field + * + * \return the new content of the ID_MSB field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_ID_MSB(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_ENCR_MSB_SET_ID_MSB(reg, data); +} + + +/* ----------------------------------------------------------- EN field of the ENCR_MSB register ------------------------------------------------------------ */ + +/** Description of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_DESC "Encryption enable (RO when CTRL.RUNNING)" + +/** Offset of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_LSB 12UL + +/** Size in bits of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_W (1UL) + +/** Mask for retrieving the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_MASK ATON_FIELD_MASK(12UL, 1UL) + +/** Reset value of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_DT 0x0UL + +/** Access rights of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_AC "RW" + +/** Check whether access to the EN field of the ENCR_MSB register is secured or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_S 0 + +/** Check whether access to the EN field of the ENCR_MSB register is privileged or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_EN_P 0 + +/** Read the content of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_GET_EN(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_EN_LSB, ATON_EPOCHCTRL_ENCR_MSB_EN_W) + +/** Modify the content of the EN field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_EN_LSB, ATON_EPOCHCTRL_ENCR_MSB_EN_W, DATA) + + +/** + * Get the description of the EN field of ENCR_MSB register. + * + * \return the description of the EN field of ENCR_MSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_EN_DESC; +} + + +/** + * Read the content of the EN field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the EN field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_EN(uint32_t reg) +{ + return ATON_EPOCHCTRL_ENCR_MSB_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_ENCR_MSB_SET_EN(reg, data); +} + + +/* --------------------------------------------------------- ROUNDS field of the ENCR_MSB register ---------------------------------------------------------- */ + +/** Description of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DESC "Encryption number of rounds: 0->12, 1->9 (RO when CTRL.RUNNING)" + +/** Offset of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB 13UL + +/** Size in bits of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_W (1UL) + +/** Mask for retrieving the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_MASK ATON_FIELD_MASK(13UL, 1UL) + +/** Reset value of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DT 0x0UL + +/** Access rights of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_AC "RW" + +/** Check whether access to the ROUNDS field of the ENCR_MSB register is secured or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_S 0 + +/** Check whether access to the ROUNDS field of the ENCR_MSB register is privileged or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_P 0 + +/** Read the content of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_GET_ROUNDS(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_W) + +/** Modify the content of the ROUNDS field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_SET_ROUNDS(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_W, DATA) + + +/** + * Get the description of the ROUNDS field of ENCR_MSB register. + * + * \return the description of the ROUNDS field of ENCR_MSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DESC; +} + + +/** + * Read the content of the ROUNDS field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the ROUNDS field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_ROUNDS(uint32_t reg) +{ + return ATON_EPOCHCTRL_ENCR_MSB_GET_ROUNDS(reg); +} + + +/** + * Write the content of the ROUNDS field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ROUNDS field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_ROUNDS(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_ENCR_MSB_SET_ROUNDS(reg, data); +} + + +/* --------------------------------------------------------- KEY_SEL field of the ENCR_MSB register --------------------------------------------------------- */ + +/** Description of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DESC "Encryption key selection (RO when CTRL.RUNNING)" + +/** Offset of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB 14UL + +/** Size in bits of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_W (2UL) + +/** Mask for retrieving the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DT 0x0UL + +/** Access rights of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_AC "RW" + +/** Check whether access to the KEY_SEL field of the ENCR_MSB register is secured or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_S 0 + +/** Check whether access to the KEY_SEL field of the ENCR_MSB register is privileged or not. */ +#define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_P 0 + +/** Read the content of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_GET_KEY_SEL(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_W) + +/** Modify the content of the KEY_SEL field of the ENCR_MSB register. */ +#define ATON_EPOCHCTRL_ENCR_MSB_SET_KEY_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_W, DATA) + + +/** + * Get the description of the KEY_SEL field of ENCR_MSB register. + * + * \return the description of the KEY_SEL field of ENCR_MSB register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DESC; +} + + +/** + * Read the content of the KEY_SEL field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * + * \return the content of the KEY_SEL field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_KEY_SEL(uint32_t reg) +{ + return ATON_EPOCHCTRL_ENCR_MSB_GET_KEY_SEL(reg); +} + + +/** + * Write the content of the KEY_SEL field of the ENCR_MSB register. + * + * \param[in] reg is the value of the ENCR_MSB register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the KEY_SEL field belonging to ENCR_MSB register + */ + +static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_KEY_SEL(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_ENCR_MSB_SET_KEY_SEL(reg, data); +} + + +/* **************************************************** CID_CACHE register of one of the EPOCHCTRL Units **************************************************** */ + +/** Offset of the CID_CACHE register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_CID_CACHE_OFFSET 0x18UL + +/** Reset value of the CID_CACHE register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_CID_CACHE_DT \ + (ATON_EPOCHCTRL_CID_CACHE_CID_DT << ATON_EPOCHCTRL_CID_CACHE_CID_LSB) | \ + (ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DT << ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB) | \ + (ATON_EPOCHCTRL_CID_CACHE_ALLOC_DT << ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB) | \ + (ATON_EPOCHCTRL_CID_CACHE_PFETCH_DT << ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB) | \ + (ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DT << ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB) + + + +/** Description of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_DESC "Compartment ID / Cache register (RO when CTRL.RUNNING)" + +/** Address of the CID_CACHE register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_CID_CACHE_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_CID_CACHE_OFFSET) + +/** Get the content of the CID_CACHE register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_CID_CACHE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CID_CACHE_ADDR(UNIT))) + +/** Set the content of the CID_CACHE register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_CID_CACHE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CID_CACHE_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CID_CACHE register. + * + * \return the description of CID_CACHE register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_DESC; +} + + +/** + * Get the offset of the CID_CACHE register. + * + * \return the offset of CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_GetOffset(void) +{ + return ATON_EPOCHCTRL_CID_CACHE_OFFSET; +} + + +/** + * Get the address of the CID_CACHE register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CID_CACHE register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CID_CACHE register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_CID_CACHE_ADDR(instance); +} + + +/** + * Read the content of the CID_CACHE register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CID_CACHE register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CID_CACHE register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_CID_CACHE_GET(instance); +} + + +/** + * Write the content of the CID_CACHE register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CID_CACHE register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_EPOCHCTRL_CID_CACHE_Set(uint32_t instance, uint32_t data) +{ + ATON_EPOCHCTRL_CID_CACHE_SET(instance, data); +} + + +/* ---------------------------------------------------------- CID field of the CID_CACHE register ----------------------------------------------------------- */ + +/** Description of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_DESC "Compartment ID (RO when CTRL.RUNNING)" + +/** Offset of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_LSB 0UL + +/** Size in bits of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_W (3UL) + +/** Mask for retrieving the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_MASK ATON_FIELD_MASK(0UL, 3UL) + +/** Reset value of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_DT 0x0UL + +/** Access rights of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_AC "RW" + +/** Check whether access to the CID field of the CID_CACHE register is secured or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_S 0 + +/** Check whether access to the CID field of the CID_CACHE register is privileged or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_CID_P 0 + +/** Read the content of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_GET_CID(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CID_LSB, ATON_EPOCHCTRL_CID_CACHE_CID_W) + +/** Modify the content of the CID field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_SET_CID(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CID_LSB, ATON_EPOCHCTRL_CID_CACHE_CID_W, DATA) + + +/** + * Get the description of the CID field of CID_CACHE register. + * + * \return the description of the CID field of CID_CACHE register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_CID_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_CID_DESC; +} + + +/** + * Read the content of the CID field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the CID field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_CID(uint32_t reg) +{ + return ATON_EPOCHCTRL_CID_CACHE_GET_CID(reg); +} + + +/** + * Write the content of the CID field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 3-bit value that must be written to the field + * + * \return the new content of the CID field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_CID(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CID_CACHE_SET_CID(reg, data); +} + + +/* ------------------------------------------------------- CACHEABLE field of the CID_CACHE register -------------------------------------------------------- */ + +/** Description of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DESC "Cacheable (RO when CTRL.RUNNING)" + +/** Offset of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB 3UL + +/** Size in bits of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_W (1UL) + +/** Mask for retrieving the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_MASK ATON_FIELD_MASK(3UL, 1UL) + +/** Reset value of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DT 0x0UL + +/** Access rights of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_AC "RW" + +/** Check whether access to the CACHEABLE field of the CID_CACHE register is secured or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_S 0 + +/** Check whether access to the CACHEABLE field of the CID_CACHE register is privileged or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_P 0 + +/** Read the content of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_GET_CACHEABLE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_W) + +/** Modify the content of the CACHEABLE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_SET_CACHEABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_W, DATA) + + +/** + * Get the description of the CACHEABLE field of CID_CACHE register. + * + * \return the description of the CACHEABLE field of CID_CACHE register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DESC; +} + + +/** + * Read the content of the CACHEABLE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the CACHEABLE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_CACHEABLE(uint32_t reg) +{ + return ATON_EPOCHCTRL_CID_CACHE_GET_CACHEABLE(reg); +} + + +/** + * Write the content of the CACHEABLE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CACHEABLE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_CACHEABLE(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CID_CACHE_SET_CACHEABLE(reg, data); +} + + +/* --------------------------------------------------------- ALLOC field of the CID_CACHE register ---------------------------------------------------------- */ + +/** Description of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_DESC "Allocate (RO when CTRL.RUNNING)" + +/** Offset of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB 4UL + +/** Size in bits of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_W (1UL) + +/** Mask for retrieving the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_MASK ATON_FIELD_MASK(4UL, 1UL) + +/** Reset value of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_DT 0x0UL + +/** Access rights of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_AC "RW" + +/** Check whether access to the ALLOC field of the CID_CACHE register is secured or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_S 0 + +/** Check whether access to the ALLOC field of the CID_CACHE register is privileged or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_ALLOC_P 0 + +/** Read the content of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_GET_ALLOC(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB, ATON_EPOCHCTRL_CID_CACHE_ALLOC_W) + +/** Modify the content of the ALLOC field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_SET_ALLOC(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB, ATON_EPOCHCTRL_CID_CACHE_ALLOC_W, DATA) + + +/** + * Get the description of the ALLOC field of CID_CACHE register. + * + * \return the description of the ALLOC field of CID_CACHE register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_ALLOC_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_ALLOC_DESC; +} + + +/** + * Read the content of the ALLOC field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the ALLOC field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_ALLOC(uint32_t reg) +{ + return ATON_EPOCHCTRL_CID_CACHE_GET_ALLOC(reg); +} + + +/** + * Write the content of the ALLOC field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the ALLOC field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_ALLOC(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CID_CACHE_SET_ALLOC(reg, data); +} + + +/* --------------------------------------------------------- PFETCH field of the CID_CACHE register --------------------------------------------------------- */ + +/** Description of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_DESC "Prefetch (RO when CTRL.RUNNING)" + +/** Offset of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB 5UL + +/** Size in bits of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_W (1UL) + +/** Mask for retrieving the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_MASK ATON_FIELD_MASK(5UL, 1UL) + +/** Reset value of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_DT 0x0UL + +/** Access rights of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_AC "RW" + +/** Check whether access to the PFETCH field of the CID_CACHE register is secured or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_S 0 + +/** Check whether access to the PFETCH field of the CID_CACHE register is privileged or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_PFETCH_P 0 + +/** Read the content of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_GET_PFETCH(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB, ATON_EPOCHCTRL_CID_CACHE_PFETCH_W) + +/** Modify the content of the PFETCH field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_SET_PFETCH(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB, ATON_EPOCHCTRL_CID_CACHE_PFETCH_W, DATA) + + +/** + * Get the description of the PFETCH field of CID_CACHE register. + * + * \return the description of the PFETCH field of CID_CACHE register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_PFETCH_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_PFETCH_DESC; +} + + +/** + * Read the content of the PFETCH field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the PFETCH field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_PFETCH(uint32_t reg) +{ + return ATON_EPOCHCTRL_CID_CACHE_GET_PFETCH(reg); +} + + +/** + * Write the content of the PFETCH field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the PFETCH field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_PFETCH(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CID_CACHE_SET_PFETCH(reg, data); +} + + +/* -------------------------------------------------------- LINESIZE field of the CID_CACHE register -------------------------------------------------------- */ + +/** Description of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DESC "Line size: 0 -> 64B, 1 -> 128B, 2 -> 256B, 3 -> 512B (RO when CTRL.RUNNING)" + +/** Offset of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB 6UL + +/** Size in bits of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_W (2UL) + +/** Mask for retrieving the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_MASK ATON_FIELD_MASK(6UL, 2UL) + +/** Reset value of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DT 0x0UL + +/** Access rights of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_AC "RW" + +/** Check whether access to the LINESIZE field of the CID_CACHE register is secured or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_S 0 + +/** Check whether access to the LINESIZE field of the CID_CACHE register is privileged or not. */ +#define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_P 0 + +/** Read the content of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_GET_LINESIZE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_W) + +/** Modify the content of the LINESIZE field of the CID_CACHE register. */ +#define ATON_EPOCHCTRL_CID_CACHE_SET_LINESIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_W, DATA) + + +/** + * Get the description of the LINESIZE field of CID_CACHE register. + * + * \return the description of the LINESIZE field of CID_CACHE register + */ + +static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_LINESIZE_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DESC; +} + + +/** + * Read the content of the LINESIZE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * + * \return the content of the LINESIZE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_LINESIZE(uint32_t reg) +{ + return ATON_EPOCHCTRL_CID_CACHE_GET_LINESIZE(reg); +} + + +/** + * Write the content of the LINESIZE field of the CID_CACHE register. + * + * \param[in] reg is the value of the CID_CACHE register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the LINESIZE field belonging to CID_CACHE register + */ + +static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_LINESIZE(uint32_t reg, uint32_t data) +{ + return ATON_EPOCHCTRL_CID_CACHE_SET_LINESIZE(reg, data); +} + + +/* ****************************************************** LABEL register of one of the EPOCHCTRL Units ****************************************************** */ + +/** Offset of the LABEL register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_LABEL_OFFSET 0x1cUL + +/** Reset value of the LABEL register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_LABEL_DT \ + (ATON_EPOCHCTRL_LABEL_REG_DT << ATON_EPOCHCTRL_LABEL_REG_LSB) + + + +/** Description of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_DESC "Label register" + +/** Address of the LABEL register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_LABEL_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_LABEL_OFFSET) + +/** Get the content of the LABEL register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_LABEL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_LABEL_ADDR(UNIT))) + + +/** + * Get the description of LABEL register. + * + * \return the description of LABEL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_LABEL_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_LABEL_DESC; +} + + +/** + * Get the offset of the LABEL register. + * + * \return the offset of LABEL register + */ + +static inline uint32_t ATON_EPOCHCTRL_LABEL_GetOffset(void) +{ + return ATON_EPOCHCTRL_LABEL_OFFSET; +} + + +/** + * Get the address of the LABEL register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the LABEL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of LABEL register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_LABEL_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_LABEL_ADDR(instance); +} + + +/** + * Read the content of the LABEL register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the LABEL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of LABEL register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_LABEL_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_LABEL_GET(instance); +} + + +/* ------------------------------------------------------------ REG field of the LABEL register ------------------------------------------------------------- */ + +/** Description of the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_REG_DESC "Label value" + +/** Offset of the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_REG_LSB 0UL + +/** Size in bits of the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_REG_W (27UL) + +/** Mask for retrieving the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_REG_MASK ATON_FIELD_MASK(0UL, 27UL) + +/** Reset value of the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_REG_DT 0x0UL + +/** Access rights of the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_REG_AC "R" + +/** Check whether access to the REG field of the LABEL register is secured or not. */ +#define ATON_EPOCHCTRL_LABEL_REG_S 0 + +/** Check whether access to the REG field of the LABEL register is privileged or not. */ +#define ATON_EPOCHCTRL_LABEL_REG_P 0 + +/** Read the content of the REG field of the LABEL register. */ +#define ATON_EPOCHCTRL_LABEL_GET_REG(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_LABEL_REG_LSB, ATON_EPOCHCTRL_LABEL_REG_W) + + +/** + * Get the description of the REG field of LABEL register. + * + * \return the description of the REG field of LABEL register + */ + +static inline const int8_t *ATON_EPOCHCTRL_LABEL_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_LABEL_REG_DESC; +} + + +/** + * Read the content of the REG field of the LABEL register. + * + * \param[in] reg is the value of the LABEL register + * + * \return the content of the REG field belonging to LABEL register + */ + +static inline uint32_t ATON_EPOCHCTRL_LABEL_Get_REG(uint32_t reg) +{ + return ATON_EPOCHCTRL_LABEL_GET_REG(reg); +} + + +/* ******************************************************* BC register of one of the EPOCHCTRL Units ******************************************************** */ + +/** Offset of the BC register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_BC_OFFSET 0x20UL + +/** Reset value of the BC register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_BC_DT \ + (ATON_EPOCHCTRL_BC_CNT_DT << ATON_EPOCHCTRL_BC_CNT_LSB) + + + +/** Description of the BC register. */ +#define ATON_EPOCHCTRL_BC_DESC "Blob opcode counter" + +/** Address of the BC register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_BC_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_BC_OFFSET) + +/** Get the content of the BC register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_BC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_BC_ADDR(UNIT))) + + +/** + * Get the description of BC register. + * + * \return the description of BC register + */ + +static inline const int8_t *ATON_EPOCHCTRL_BC_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_BC_DESC; +} + + +/** + * Get the offset of the BC register. + * + * \return the offset of BC register + */ + +static inline uint32_t ATON_EPOCHCTRL_BC_GetOffset(void) +{ + return ATON_EPOCHCTRL_BC_OFFSET; +} + + +/** + * Get the address of the BC register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the BC register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of BC register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_BC_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_BC_ADDR(instance); +} + + +/** + * Read the content of the BC register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the BC register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of BC register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_BC_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_BC_GET(instance); +} + + +/* -------------------------------------------------------------- CNT field of the BC register -------------------------------------------------------------- */ + +/** Description of the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_CNT_DESC "Blob opcode counter" + +/** Offset of the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_CNT_LSB 0UL + +/** Size in bits of the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_CNT_W (16UL) + +/** Mask for retrieving the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_CNT_MASK ATON_FIELD_MASK(0UL, 16UL) + +/** Reset value of the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_CNT_DT 0x0UL + +/** Access rights of the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_CNT_AC "R" + +/** Check whether access to the CNT field of the BC register is secured or not. */ +#define ATON_EPOCHCTRL_BC_CNT_S 0 + +/** Check whether access to the CNT field of the BC register is privileged or not. */ +#define ATON_EPOCHCTRL_BC_CNT_P 0 + +/** Read the content of the CNT field of the BC register. */ +#define ATON_EPOCHCTRL_BC_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_BC_CNT_LSB, ATON_EPOCHCTRL_BC_CNT_W) + + +/** + * Get the description of the CNT field of BC register. + * + * \return the description of the CNT field of BC register + */ + +static inline const int8_t *ATON_EPOCHCTRL_BC_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_BC_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the BC register. + * + * \param[in] reg is the value of the BC register + * + * \return the content of the CNT field belonging to BC register + */ + +static inline uint32_t ATON_EPOCHCTRL_BC_Get_CNT(uint32_t reg) +{ + return ATON_EPOCHCTRL_BC_GET_CNT(reg); +} + + +/* ******************************************************* ACC register of one of the EPOCHCTRL Units ******************************************************* */ + +/** Offset of the ACC register from the base address of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ACC_OFFSET 0x24UL + +/** Reset value of the ACC register of the EPOCHCTRL Unit. */ +#define ATON_EPOCHCTRL_ACC_DT \ + (ATON_EPOCHCTRL_ACC_REG_DT << ATON_EPOCHCTRL_ACC_REG_LSB) + + + +/** Description of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_DESC "Accumulator" + +/** Address of the ACC register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ACC_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ACC_OFFSET) + +/** Get the content of the ACC register of one of the EPOCHCTRL Units. */ +#define ATON_EPOCHCTRL_ACC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ACC_ADDR(UNIT))) + + +/** + * Get the description of ACC register. + * + * \return the description of ACC register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ACC_GetDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ACC_DESC; +} + + +/** + * Get the offset of the ACC register. + * + * \return the offset of ACC register + */ + +static inline uint32_t ATON_EPOCHCTRL_ACC_GetOffset(void) +{ + return ATON_EPOCHCTRL_ACC_OFFSET; +} + + +/** + * Get the address of the ACC register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ACC register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of ACC register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ACC_GetAddr(uint32_t instance) +{ + return ATON_EPOCHCTRL_ACC_ADDR(instance); +} + + +/** + * Read the content of the ACC register. + * + * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ACC register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of ACC register belonging to Unit having index \e instance among the EPOCHCTRL Units + */ + +static inline uint32_t ATON_EPOCHCTRL_ACC_Get(uint32_t instance) +{ + return ATON_EPOCHCTRL_ACC_GET(instance); +} + + +/* ------------------------------------------------------------- REG field of the ACC register -------------------------------------------------------------- */ + +/** Description of the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_REG_DESC "Accumulator value" + +/** Offset of the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_REG_LSB 0UL + +/** Size in bits of the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_REG_W (32UL) + +/** Mask for retrieving the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_REG_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_REG_DT 0x0UL + +/** Access rights of the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_REG_AC "R" + +/** Check whether access to the REG field of the ACC register is secured or not. */ +#define ATON_EPOCHCTRL_ACC_REG_S 0 + +/** Check whether access to the REG field of the ACC register is privileged or not. */ +#define ATON_EPOCHCTRL_ACC_REG_P 0 + +/** Read the content of the REG field of the ACC register. */ +#define ATON_EPOCHCTRL_ACC_GET_REG(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ACC_REG_LSB, ATON_EPOCHCTRL_ACC_REG_W) + + +/** + * Get the description of the REG field of ACC register. + * + * \return the description of the REG field of ACC register + */ + +static inline const int8_t *ATON_EPOCHCTRL_ACC_REG_GetdDesc(void) +{ + return (const int8_t *)ATON_EPOCHCTRL_ACC_REG_DESC; +} + + +/** + * Read the content of the REG field of the ACC register. + * + * \param[in] reg is the value of the ACC register + * + * \return the content of the REG field belonging to ACC register + */ + +static inline uint32_t ATON_EPOCHCTRL_ACC_Get_REG(uint32_t reg) +{ + return ATON_EPOCHCTRL_ACC_GET_REG(reg); +} + + +/*@}*/ + + +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ +/* */ +/* DEBUG_TRACE Units */ +/* */ +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ + +/** Number of DEBUG_TRACE Unit instances. */ +#define ATON_DEBUG_TRACE_NUM 1 + +/** + * \name Structures, macros and functions of the DEBUG_TRACE Units + */ +/*@{*/ + +/** + * Registers of the DEBUG_TRACE Units + */ + +typedef volatile struct +{ + /** \e CTRL register (Control register). */ + uint32_t CTRL; + + /** \e VERSION register (Version register). */ + uint32_t VERSION; + + /** \e LOW_ILINK_STATES register (Monitor Input Link 1). */ + uint32_t LOW_ILINK_STATES; + + /** \e HIGH_ILINK_STATES register (Monitor Input Link 2). */ + uint32_t HIGH_ILINK_STATES; + + /** \e LOW_OLINK_STATES register (Monitor Output Link 1). */ + uint32_t LOW_OLINK_STATES; + + /** \e HIGH_OLINK_STATES register (Monitor Output Link 2). */ + uint32_t HIGH_OLINK_STATES; + + // ...other registers that cannot be defined in this structure... + +} ATON_DEBUG_TRACE_t; + + +/** Return the pointer to one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE(UNIT) ((ATON_DEBUG_TRACE_t *)(intptr_t)ATON_DEBUG_TRACE_BASE(UNIT)) + + +/** Name of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_NAME(UNIT) \ + (((UNIT) == 0) ? "DEBUG_TRACE0" : "") + + +/** Version of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_VERSION "1.1" + + +/** Description of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_DESC(UNIT) \ + (((UNIT) == 0) ? "Debug Trace 0" : "") + + +/** Base address of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_BASE(UNIT) \ + (ATON_BASE + 0x1f000UL + ((UNIT) * 0x0UL)) + +/** Size in bytes of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_SIZE 0x1000UL + + +/** + * Get the name of one of the DEBUG_TRACE Units. + * + * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) + * + * \return the name of Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline const int8_t *ATON_DEBUG_TRACE_GetName(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"DEBUG_TRACE0"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the description of one of the DEBUG_TRACE Units. + * + * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) + * + * \return the description of Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline const int8_t *ATON_DEBUG_TRACE_GetDesc(uint32_t instance) +{ + const int8_t *str = NULL; + + switch (instance) + { + case 0: + str = (const int8_t *)"Debug Trace 0"; + break; + + default: + break; + } + + return str; +} + + +/** + * Get the version of the DEBUG_TRACE Units. + * + * \return the version of the DEBUG_TRACE Units + */ + +static inline const int8_t *ATON_DEBUG_TRACE_GetVersion(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION; +} + + +/** + * Get the base address of one of the DEBUG_TRACE Units. + * + * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) + * + * \return the base address of Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_GetBase(uint32_t instance) +{ + return ATON_DEBUG_TRACE_BASE(instance); +} + + +/** + * Get the size in bytes of the DEBUG_TRACE Units. + * + * \return the size in bytes of the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_GetSize(void) +{ + return ATON_DEBUG_TRACE_SIZE; +} + + +/* ***************************************************** CTRL register of one of the DEBUG_TRACE Units ****************************************************** */ + +/** Offset of the CTRL register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_CTRL_OFFSET 0x0UL + +/** Reset value of the CTRL register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_CTRL_DT \ + (ATON_DEBUG_TRACE_CTRL_EN_DT << ATON_DEBUG_TRACE_CTRL_EN_LSB) | \ + (ATON_DEBUG_TRACE_CTRL_CLR_DT << ATON_DEBUG_TRACE_CTRL_CLR_LSB) | \ + (ATON_DEBUG_TRACE_CTRL_CONFCLR_DT << ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB) + + + +/** Description of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_DESC "Control register" + +/** Address of the CTRL register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_CTRL_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_CTRL_OFFSET) + +/** Get the content of the CTRL register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_CTRL_ADDR(UNIT))) + +/** Set the content of the CTRL register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_CTRL_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of CTRL register. + * + * \return the description of CTRL register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_CTRL_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_CTRL_DESC; +} + + +/** + * Get the offset of the CTRL register. + * + * \return the offset of CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_GetOffset(void) +{ + return ATON_DEBUG_TRACE_CTRL_OFFSET; +} + + +/** + * Get the address of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the CTRL register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of CTRL register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_CTRL_ADDR(instance); +} + + +/** + * Read the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the CTRL register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of CTRL register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_CTRL_GET(instance); +} + + +/** + * Write the content of the CTRL register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the CTRL register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_CTRL_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_CTRL_SET(instance, data); +} + + +/* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ + +/** Description of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_EN_DESC "Enable the Debug Trace Unit" + +/** Offset of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_EN_LSB 0UL + +/** Size in bits of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_EN_W (1UL) + +/** Mask for retrieving the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_EN_DT 0x0UL + +/** Access rights of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_EN_AC "RW" + +/** Check whether access to the EN field of the CTRL register is secured or not. */ +#define ATON_DEBUG_TRACE_CTRL_EN_S 0 + +/** Check whether access to the EN field of the CTRL register is privileged or not. */ +#define ATON_DEBUG_TRACE_CTRL_EN_P 0 + +/** Read the content of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_EN_LSB, ATON_DEBUG_TRACE_CTRL_EN_W) + +/** Modify the content of the EN field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_EN_LSB, ATON_DEBUG_TRACE_CTRL_EN_W, DATA) + + +/** + * Get the description of the EN field of CTRL register. + * + * \return the description of the EN field of CTRL register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_CTRL_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_CTRL_EN_DESC; +} + + +/** + * Read the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_CTRL_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_CTRL_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ + +/** Description of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_DESC "Clear all pipeline registers" + +/** Offset of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_LSB 1UL + +/** Size in bits of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_W (1UL) + +/** Mask for retrieving the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) + +/** Reset value of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_DT 0x0UL + +/** Access rights of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_AC "RW" + +/** Check whether access to the CLR field of the CTRL register is secured or not. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_S 0 + +/** Check whether access to the CLR field of the CTRL register is privileged or not. */ +#define ATON_DEBUG_TRACE_CTRL_CLR_P 0 + +/** Read the content of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CLR_LSB, ATON_DEBUG_TRACE_CTRL_CLR_W) + +/** Modify the content of the CLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CLR_LSB, ATON_DEBUG_TRACE_CTRL_CLR_W, DATA) + + +/** + * Get the description of the CLR field of CTRL register. + * + * \return the description of the CLR field of CTRL register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_CTRL_CLR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_CTRL_CLR_DESC; +} + + +/** + * Read the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get_CLR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_CTRL_GET_CLR(reg); +} + + +/** + * Write the content of the CLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Set_CLR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_CTRL_SET_CLR(reg, data); +} + + +/* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ + +/** Description of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_DESC "Clear Configuration registers (auto cleared)" + +/** Offset of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB 30UL + +/** Size in bits of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_W (1UL) + +/** Mask for retrieving the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) + +/** Reset value of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_DT 0x0UL + +/** Access rights of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_AC "RW" + +/** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_S 0 + +/** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ +#define ATON_DEBUG_TRACE_CTRL_CONFCLR_P 0 + +/** Read the content of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB, ATON_DEBUG_TRACE_CTRL_CONFCLR_W) + +/** Modify the content of the CONFCLR field of the CTRL register. */ +#define ATON_DEBUG_TRACE_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB, ATON_DEBUG_TRACE_CTRL_CONFCLR_W, DATA) + + +/** + * Get the description of the CONFCLR field of CTRL register. + * + * \return the description of the CONFCLR field of CTRL register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_CTRL_CONFCLR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_CTRL_CONFCLR_DESC; +} + + +/** + * Read the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * + * \return the content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get_CONFCLR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_CTRL_GET_CONFCLR(reg); +} + + +/** + * Write the content of the CONFCLR field of the CTRL register. + * + * \param[in] reg is the value of the CTRL register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CONFCLR field belonging to CTRL register + */ + +static inline uint32_t ATON_DEBUG_TRACE_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_CTRL_SET_CONFCLR(reg, data); +} + + +/* **************************************************** VERSION register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the VERSION register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_VERSION_OFFSET 0x4UL + +/** Reset value of the VERSION register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_VERSION_DT \ + (ATON_DEBUG_TRACE_VERSION_TYPE_DT << ATON_DEBUG_TRACE_VERSION_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_VERSION_MINOR_DT << ATON_DEBUG_TRACE_VERSION_MINOR_LSB) | \ + (ATON_DEBUG_TRACE_VERSION_MAJOR_DT << ATON_DEBUG_TRACE_VERSION_MAJOR_LSB) | \ + (ATON_DEBUG_TRACE_VERSION_NRSIG_DT << ATON_DEBUG_TRACE_VERSION_NRSIG_LSB) | \ + (ATON_DEBUG_TRACE_VERSION_NRTRIG_DT << ATON_DEBUG_TRACE_VERSION_NRTRIG_LSB) + + + +/** Description of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_DESC "Version register" + +/** Address of the VERSION register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_VERSION_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_VERSION_OFFSET) + +/** Get the content of the VERSION register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_VERSION_ADDR(UNIT))) + + +/** + * Get the description of VERSION register. + * + * \return the description of VERSION register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_VERSION_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION_DESC; +} + + +/** + * Get the offset of the VERSION register. + * + * \return the offset of VERSION register + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_GetOffset(void) +{ + return ATON_DEBUG_TRACE_VERSION_OFFSET; +} + + +/** + * Get the address of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the VERSION register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of VERSION register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_VERSION_ADDR(instance); +} + + +/** + * Read the content of the VERSION register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the VERSION register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of VERSION register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_VERSION_GET(instance); +} + + +/* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_DESC "Block type" + +/** Offset of the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_LSB 0UL + +/** Size in bits of the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_W (8UL) + +/** Mask for retrieving the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) + +/** Reset value of the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_DT 0x22UL + +/** Access rights of the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_AC "R" + +/** Check whether access to the TYPE field of the VERSION register is secured or not. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_S 0 + +/** Check whether access to the TYPE field of the VERSION register is privileged or not. */ +#define ATON_DEBUG_TRACE_VERSION_TYPE_P 0 + +/** Read the content of the TYPE field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_TYPE_LSB, ATON_DEBUG_TRACE_VERSION_TYPE_W) + + +/** + * Get the description of the TYPE field of VERSION register. + * + * \return the description of the TYPE field of VERSION register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_VERSION_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION_TYPE_DESC; +} + + +/** + * Read the content of the TYPE field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the TYPE field belonging to VERSION register + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_VERSION_GET_TYPE(reg); +} + + +/* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_DESC "Block minor version" + +/** Offset of the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_LSB 8UL + +/** Size in bits of the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_W (4UL) + +/** Mask for retrieving the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) + +/** Reset value of the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_DT 0x1UL + +/** Access rights of the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_AC "R" + +/** Check whether access to the MINOR field of the VERSION register is secured or not. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_S 0 + +/** Check whether access to the MINOR field of the VERSION register is privileged or not. */ +#define ATON_DEBUG_TRACE_VERSION_MINOR_P 0 + +/** Read the content of the MINOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_MINOR_LSB, ATON_DEBUG_TRACE_VERSION_MINOR_W) + + +/** + * Get the description of the MINOR field of VERSION register. + * + * \return the description of the MINOR field of VERSION register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_VERSION_MINOR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION_MINOR_DESC; +} + + +/** + * Read the content of the MINOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MINOR field belonging to VERSION register + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_MINOR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_VERSION_GET_MINOR(reg); +} + + +/* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_DESC "Block major version" + +/** Offset of the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_LSB 12UL + +/** Size in bits of the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_W (4UL) + +/** Mask for retrieving the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) + +/** Reset value of the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_DT 0x1UL + +/** Access rights of the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_AC "R" + +/** Check whether access to the MAJOR field of the VERSION register is secured or not. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_S 0 + +/** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ +#define ATON_DEBUG_TRACE_VERSION_MAJOR_P 0 + +/** Read the content of the MAJOR field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_MAJOR_LSB, ATON_DEBUG_TRACE_VERSION_MAJOR_W) + + +/** + * Get the description of the MAJOR field of VERSION register. + * + * \return the description of the MAJOR field of VERSION register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_VERSION_MAJOR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION_MAJOR_DESC; +} + + +/** + * Read the content of the MAJOR field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the MAJOR field belonging to VERSION register + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_MAJOR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_VERSION_GET_MAJOR(reg); +} + + +/* ---------------------------------------------------------- NRSIG field of the VERSION register ----------------------------------------------------------- */ + +/** Description of the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_DESC "Number of observable signals" + +/** Offset of the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_LSB 16UL + +/** Size in bits of the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_W (10UL) + +/** Mask for retrieving the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_MASK ATON_FIELD_MASK(16UL, 10UL) + +/** Reset value of the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_DT 0x1ffUL + +/** Access rights of the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_AC "R" + +/** Check whether access to the NRSIG field of the VERSION register is secured or not. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_S 0 + +/** Check whether access to the NRSIG field of the VERSION register is privileged or not. */ +#define ATON_DEBUG_TRACE_VERSION_NRSIG_P 0 + +/** Read the content of the NRSIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_GET_NRSIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_NRSIG_LSB, ATON_DEBUG_TRACE_VERSION_NRSIG_W) + + +/** + * Get the description of the NRSIG field of VERSION register. + * + * \return the description of the NRSIG field of VERSION register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_VERSION_NRSIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION_NRSIG_DESC; +} + + +/** + * Read the content of the NRSIG field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the NRSIG field belonging to VERSION register + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_NRSIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_VERSION_GET_NRSIG(reg); +} + + +/* ---------------------------------------------------------- NRTRIG field of the VERSION register ---------------------------------------------------------- */ + +/** Description of the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_DESC "Number of trigger events supported" + +/** Offset of the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_LSB 26UL + +/** Size in bits of the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_W (6UL) + +/** Mask for retrieving the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_MASK ATON_FIELD_MASK(26UL, 6UL) + +/** Reset value of the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_DT 0x8UL + +/** Access rights of the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_AC "R" + +/** Check whether access to the NRTRIG field of the VERSION register is secured or not. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_S 0 + +/** Check whether access to the NRTRIG field of the VERSION register is privileged or not. */ +#define ATON_DEBUG_TRACE_VERSION_NRTRIG_P 0 + +/** Read the content of the NRTRIG field of the VERSION register. */ +#define ATON_DEBUG_TRACE_VERSION_GET_NRTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_NRTRIG_LSB, ATON_DEBUG_TRACE_VERSION_NRTRIG_W) + + +/** + * Get the description of the NRTRIG field of VERSION register. + * + * \return the description of the NRTRIG field of VERSION register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_VERSION_NRTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_VERSION_NRTRIG_DESC; +} + + +/** + * Read the content of the NRTRIG field of the VERSION register. + * + * \param[in] reg is the value of the VERSION register + * + * \return the content of the NRTRIG field belonging to VERSION register + */ + +static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_NRTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_VERSION_GET_NRTRIG(reg); +} + + +/* *********************************************** LOW_ILINK_STATES register of one of the DEBUG_TRACE Units ************************************************ */ + +/** Offset of the LOW_ILINK_STATES register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_OFFSET 0x8UL + +/** Reset value of the LOW_ILINK_STATES register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_DT \ + (ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_LSB) + + + +/** Description of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_DESC "Monitor Input Link 1" + +/** Address of the LOW_ILINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_LOW_ILINK_STATES_OFFSET) + +/** Get the content of the LOW_ILINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_LOW_ILINK_STATES_ADDR(UNIT))) + + +/** + * Get the description of LOW_ILINK_STATES register. + * + * \return the description of LOW_ILINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_LOW_ILINK_STATES_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_LOW_ILINK_STATES_DESC; +} + + +/** + * Get the offset of the LOW_ILINK_STATES register. + * + * \return the offset of LOW_ILINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_GetOffset(void) +{ + return ATON_DEBUG_TRACE_LOW_ILINK_STATES_OFFSET; +} + + +/** + * Get the address of the LOW_ILINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_ILINK_STATES register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of LOW_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_LOW_ILINK_STATES_ADDR(instance); +} + + +/** + * Read the content of the LOW_ILINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_ILINK_STATES register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of LOW_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET(instance); +} + + +/* ----------------------------------------------------- STALLS field of the LOW_ILINK_STATES register ------------------------------------------------------ */ + +/** Description of the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DESC "Monitor Stream Switch input link stalls 0-31" + +/** Offset of the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_LSB 0UL + +/** Size in bits of the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_W (32UL) + +/** Mask for retrieving the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DT 0x0UL + +/** Access rights of the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_AC "R" + +/** Check whether access to the STALLS field of the LOW_ILINK_STATES register is secured or not. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_S 0 + +/** Check whether access to the STALLS field of the LOW_ILINK_STATES register is privileged or not. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_P 0 + +/** Read the content of the STALLS field of the LOW_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_W) + + +/** + * Get the description of the STALLS field of LOW_ILINK_STATES register. + * + * \return the description of the STALLS field of LOW_ILINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DESC; +} + + +/** + * Read the content of the STALLS field of the LOW_ILINK_STATES register. + * + * \param[in] reg is the value of the LOW_ILINK_STATES register + * + * \return the content of the STALLS field belonging to LOW_ILINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_Get_STALLS(uint32_t reg) +{ + return ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET_STALLS(reg); +} + + +/* *********************************************** HIGH_ILINK_STATES register of one of the DEBUG_TRACE Units *********************************************** */ + +/** Offset of the HIGH_ILINK_STATES register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_OFFSET 0xcUL + +/** Reset value of the HIGH_ILINK_STATES register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_DT \ + (ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_LSB) + + + +/** Description of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_DESC "Monitor Input Link 2" + +/** Address of the HIGH_ILINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_HIGH_ILINK_STATES_OFFSET) + +/** Get the content of the HIGH_ILINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_HIGH_ILINK_STATES_ADDR(UNIT))) + + +/** + * Get the description of HIGH_ILINK_STATES register. + * + * \return the description of HIGH_ILINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_HIGH_ILINK_STATES_DESC; +} + + +/** + * Get the offset of the HIGH_ILINK_STATES register. + * + * \return the offset of HIGH_ILINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GetOffset(void) +{ + return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_OFFSET; +} + + +/** + * Get the address of the HIGH_ILINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_ILINK_STATES register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of HIGH_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_ADDR(instance); +} + + +/** + * Read the content of the HIGH_ILINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_ILINK_STATES register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of HIGH_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET(instance); +} + + +/* ----------------------------------------------------- STALLS field of the HIGH_ILINK_STATES register ----------------------------------------------------- */ + +/** Description of the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DESC "Monitor Stream Switch input link stalls 32-63" + +/** Offset of the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_LSB 0UL + +/** Size in bits of the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_W (32UL) + +/** Mask for retrieving the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DT 0x0UL + +/** Access rights of the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_AC "R" + +/** Check whether access to the STALLS field of the HIGH_ILINK_STATES register is secured or not. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_S 0 + +/** Check whether access to the STALLS field of the HIGH_ILINK_STATES register is privileged or not. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_P 0 + +/** Read the content of the STALLS field of the HIGH_ILINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_W) + + +/** + * Get the description of the STALLS field of HIGH_ILINK_STATES register. + * + * \return the description of the STALLS field of HIGH_ILINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DESC; +} + + +/** + * Read the content of the STALLS field of the HIGH_ILINK_STATES register. + * + * \param[in] reg is the value of the HIGH_ILINK_STATES register + * + * \return the content of the STALLS field belonging to HIGH_ILINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_Get_STALLS(uint32_t reg) +{ + return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET_STALLS(reg); +} + + +/* *********************************************** LOW_OLINK_STATES register of one of the DEBUG_TRACE Units ************************************************ */ + +/** Offset of the LOW_OLINK_STATES register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_OFFSET 0x10UL + +/** Reset value of the LOW_OLINK_STATES register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_DT \ + (ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_LSB) + + + +/** Description of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_DESC "Monitor Output Link 1" + +/** Address of the LOW_OLINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_LOW_OLINK_STATES_OFFSET) + +/** Get the content of the LOW_OLINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_LOW_OLINK_STATES_ADDR(UNIT))) + + +/** + * Get the description of LOW_OLINK_STATES register. + * + * \return the description of LOW_OLINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_LOW_OLINK_STATES_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_LOW_OLINK_STATES_DESC; +} + + +/** + * Get the offset of the LOW_OLINK_STATES register. + * + * \return the offset of LOW_OLINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_GetOffset(void) +{ + return ATON_DEBUG_TRACE_LOW_OLINK_STATES_OFFSET; +} + + +/** + * Get the address of the LOW_OLINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_OLINK_STATES register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of LOW_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_LOW_OLINK_STATES_ADDR(instance); +} + + +/** + * Read the content of the LOW_OLINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_OLINK_STATES register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of LOW_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET(instance); +} + + +/* ----------------------------------------------------- STALLS field of the LOW_OLINK_STATES register ------------------------------------------------------ */ + +/** Description of the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DESC "Monitor Stream Switch output link stalls 0-31" + +/** Offset of the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_LSB 0UL + +/** Size in bits of the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_W (32UL) + +/** Mask for retrieving the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DT 0x0UL + +/** Access rights of the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_AC "R" + +/** Check whether access to the STALLS field of the LOW_OLINK_STATES register is secured or not. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_S 0 + +/** Check whether access to the STALLS field of the LOW_OLINK_STATES register is privileged or not. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_P 0 + +/** Read the content of the STALLS field of the LOW_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_W) + + +/** + * Get the description of the STALLS field of LOW_OLINK_STATES register. + * + * \return the description of the STALLS field of LOW_OLINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DESC; +} + + +/** + * Read the content of the STALLS field of the LOW_OLINK_STATES register. + * + * \param[in] reg is the value of the LOW_OLINK_STATES register + * + * \return the content of the STALLS field belonging to LOW_OLINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_Get_STALLS(uint32_t reg) +{ + return ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET_STALLS(reg); +} + + +/* *********************************************** HIGH_OLINK_STATES register of one of the DEBUG_TRACE Units *********************************************** */ + +/** Offset of the HIGH_OLINK_STATES register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_OFFSET 0x14UL + +/** Reset value of the HIGH_OLINK_STATES register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_DT \ + (ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_LSB) + + + +/** Description of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_DESC "Monitor Output Link 2" + +/** Address of the HIGH_OLINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_HIGH_OLINK_STATES_OFFSET) + +/** Get the content of the HIGH_OLINK_STATES register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_HIGH_OLINK_STATES_ADDR(UNIT))) + + +/** + * Get the description of HIGH_OLINK_STATES register. + * + * \return the description of HIGH_OLINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_HIGH_OLINK_STATES_DESC; +} + + +/** + * Get the offset of the HIGH_OLINK_STATES register. + * + * \return the offset of HIGH_OLINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GetOffset(void) +{ + return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_OFFSET; +} + + +/** + * Get the address of the HIGH_OLINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_OLINK_STATES register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of HIGH_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_ADDR(instance); +} + + +/** + * Read the content of the HIGH_OLINK_STATES register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_OLINK_STATES register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of HIGH_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET(instance); +} + + +/* ----------------------------------------------------- STALLS field of the HIGH_OLINK_STATES register ----------------------------------------------------- */ + +/** Description of the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DESC "Monitor Stream Switch output link stalls 32-63" + +/** Offset of the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_LSB 0UL + +/** Size in bits of the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_W (32UL) + +/** Mask for retrieving the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DT 0x0UL + +/** Access rights of the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_AC "R" + +/** Check whether access to the STALLS field of the HIGH_OLINK_STATES register is secured or not. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_S 0 + +/** Check whether access to the STALLS field of the HIGH_OLINK_STATES register is privileged or not. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_P 0 + +/** Read the content of the STALLS field of the HIGH_OLINK_STATES register. */ +#define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_W) + + +/** + * Get the description of the STALLS field of HIGH_OLINK_STATES register. + * + * \return the description of the STALLS field of HIGH_OLINK_STATES register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DESC; +} + + +/** + * Read the content of the STALLS field of the HIGH_OLINK_STATES register. + * + * \param[in] reg is the value of the HIGH_OLINK_STATES register + * + * \return the content of the STALLS field belonging to HIGH_OLINK_STATES register + */ + +static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_Get_STALLS(uint32_t reg) +{ + return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET_STALLS(reg); +} + + +/* **************************************************** TRIG_0 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_0 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_0_OFFSET 0x1cUL + +/** Reset value of the TRIG_0 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_0_DT \ + (ATON_DEBUG_TRACE_TRIG_0_EN_DT << ATON_DEBUG_TRACE_TRIG_0_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_0_SEL_DT << ATON_DEBUG_TRACE_TRIG_0_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_0_OVR_DT << ATON_DEBUG_TRACE_TRIG_0_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_0_FILTER_DT << ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB) + + + +/** Description of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_DESC "Trigger Generation register 1" + +/** Address of the TRIG_0 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_0_OFFSET) + +/** Get the content of the TRIG_0 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT))) + +/** Set the content of the TRIG_0 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_0 register. + * + * \return the description of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_DESC; +} + + +/** + * Get the offset of the TRIG_0 register. + * + * \return the offset of TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_0_OFFSET; +} + + +/** + * Get the address of the TRIG_0 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_0_ADDR(instance); +} + + +/** + * Read the content of the TRIG_0 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET(instance); +} + + +/** + * Write the content of the TRIG_0 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_0_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_0_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_0 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_S 0 + +/** Check whether access to the EN field of the TRIG_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_EN_P 0 + +/** Read the content of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EN_LSB, ATON_DEBUG_TRACE_TRIG_0_EN_W) + +/** Modify the content of the EN field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EN_LSB, ATON_DEBUG_TRACE_TRIG_0_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_0 register. + * + * \return the description of the EN field of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * + * \return the content of the EN field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_0_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_0 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SEL_LSB, ATON_DEBUG_TRACE_TRIG_0_SEL_W) + +/** Modify the content of the SEL field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SEL_LSB, ATON_DEBUG_TRACE_TRIG_0_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_0 register. + * + * \return the description of the SEL field of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * + * \return the content of the SEL field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_0_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_0 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_0 register. + * + * \return the description of the SWTRIG field of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * + * \return the content of the SWTRIG field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_0_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_0 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_OVR_LSB, ATON_DEBUG_TRACE_TRIG_0_OVR_W) + +/** Modify the content of the OVR field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_OVR_LSB, ATON_DEBUG_TRACE_TRIG_0_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_0 register. + * + * \return the description of the OVR field of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * + * \return the content of the OVR field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_0_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_0 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_0 register. + * + * \return the description of the EVENT_TYPE field of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_0_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_0 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_0_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_0_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_0 register. */ +#define ATON_DEBUG_TRACE_TRIG_0_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_0_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_0 register. + * + * \return the description of the FILTER field of TRIG_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * + * \return the content of the FILTER field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_0_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_0 register. + * + * \param[in] reg is the value of the TRIG_0 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_0_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_1 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_1 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_1_OFFSET 0x20UL + +/** Reset value of the TRIG_1 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_1_DT \ + (ATON_DEBUG_TRACE_TRIG_1_EN_DT << ATON_DEBUG_TRACE_TRIG_1_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_1_SEL_DT << ATON_DEBUG_TRACE_TRIG_1_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_1_OVR_DT << ATON_DEBUG_TRACE_TRIG_1_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_1_FILTER_DT << ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB) + + + +/** Description of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_DESC "Trigger Generation register 2" + +/** Address of the TRIG_1 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_1_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_1_OFFSET) + +/** Get the content of the TRIG_1 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_1_ADDR(UNIT))) + +/** Set the content of the TRIG_1 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_1 register. + * + * \return the description of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_DESC; +} + + +/** + * Get the offset of the TRIG_1 register. + * + * \return the offset of TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_1_OFFSET; +} + + +/** + * Get the address of the TRIG_1 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_1_ADDR(instance); +} + + +/** + * Read the content of the TRIG_1 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET(instance); +} + + +/** + * Write the content of the TRIG_1 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_1_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_1_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_1 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_S 0 + +/** Check whether access to the EN field of the TRIG_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_EN_P 0 + +/** Read the content of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EN_LSB, ATON_DEBUG_TRACE_TRIG_1_EN_W) + +/** Modify the content of the EN field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EN_LSB, ATON_DEBUG_TRACE_TRIG_1_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_1 register. + * + * \return the description of the EN field of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * + * \return the content of the EN field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_1_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_1 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SEL_LSB, ATON_DEBUG_TRACE_TRIG_1_SEL_W) + +/** Modify the content of the SEL field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SEL_LSB, ATON_DEBUG_TRACE_TRIG_1_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_1 register. + * + * \return the description of the SEL field of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * + * \return the content of the SEL field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_1_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_1 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_1 register. + * + * \return the description of the SWTRIG field of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * + * \return the content of the SWTRIG field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_1_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_1 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_OVR_LSB, ATON_DEBUG_TRACE_TRIG_1_OVR_W) + +/** Modify the content of the OVR field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_OVR_LSB, ATON_DEBUG_TRACE_TRIG_1_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_1 register. + * + * \return the description of the OVR field of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * + * \return the content of the OVR field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_1_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_1 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_1 register. + * + * \return the description of the EVENT_TYPE field of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_1_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_1 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_1_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_1_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_1 register. */ +#define ATON_DEBUG_TRACE_TRIG_1_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_1_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_1 register. + * + * \return the description of the FILTER field of TRIG_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * + * \return the content of the FILTER field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_1_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_1 register. + * + * \param[in] reg is the value of the TRIG_1 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_1_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_2 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_2 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_2_OFFSET 0x24UL + +/** Reset value of the TRIG_2 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_2_DT \ + (ATON_DEBUG_TRACE_TRIG_2_EN_DT << ATON_DEBUG_TRACE_TRIG_2_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_2_SEL_DT << ATON_DEBUG_TRACE_TRIG_2_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_2_OVR_DT << ATON_DEBUG_TRACE_TRIG_2_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_2_FILTER_DT << ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB) + + + +/** Description of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_DESC "Trigger Generation register 3" + +/** Address of the TRIG_2 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_2_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_2_OFFSET) + +/** Get the content of the TRIG_2 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_2_ADDR(UNIT))) + +/** Set the content of the TRIG_2 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_2 register. + * + * \return the description of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_DESC; +} + + +/** + * Get the offset of the TRIG_2 register. + * + * \return the offset of TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_2_OFFSET; +} + + +/** + * Get the address of the TRIG_2 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_2 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_2_ADDR(instance); +} + + +/** + * Read the content of the TRIG_2 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_2 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET(instance); +} + + +/** + * Write the content of the TRIG_2 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_2 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_2_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_2_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_2 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_S 0 + +/** Check whether access to the EN field of the TRIG_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_EN_P 0 + +/** Read the content of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EN_LSB, ATON_DEBUG_TRACE_TRIG_2_EN_W) + +/** Modify the content of the EN field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EN_LSB, ATON_DEBUG_TRACE_TRIG_2_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_2 register. + * + * \return the description of the EN field of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * + * \return the content of the EN field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_2_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_2 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SEL_LSB, ATON_DEBUG_TRACE_TRIG_2_SEL_W) + +/** Modify the content of the SEL field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SEL_LSB, ATON_DEBUG_TRACE_TRIG_2_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_2 register. + * + * \return the description of the SEL field of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * + * \return the content of the SEL field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_2_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_2 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_2 register. + * + * \return the description of the SWTRIG field of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * + * \return the content of the SWTRIG field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_2_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_2 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_OVR_LSB, ATON_DEBUG_TRACE_TRIG_2_OVR_W) + +/** Modify the content of the OVR field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_OVR_LSB, ATON_DEBUG_TRACE_TRIG_2_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_2 register. + * + * \return the description of the OVR field of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * + * \return the content of the OVR field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_2_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_2 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_2 register. + * + * \return the description of the EVENT_TYPE field of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_2_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_2 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_2_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_2_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_2 register. */ +#define ATON_DEBUG_TRACE_TRIG_2_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_2_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_2 register. + * + * \return the description of the FILTER field of TRIG_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * + * \return the content of the FILTER field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_2_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_2 register. + * + * \param[in] reg is the value of the TRIG_2 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_2_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_3 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_3 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_3_OFFSET 0x28UL + +/** Reset value of the TRIG_3 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_3_DT \ + (ATON_DEBUG_TRACE_TRIG_3_EN_DT << ATON_DEBUG_TRACE_TRIG_3_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_3_SEL_DT << ATON_DEBUG_TRACE_TRIG_3_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_3_OVR_DT << ATON_DEBUG_TRACE_TRIG_3_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_3_FILTER_DT << ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB) + + + +/** Description of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_DESC "Trigger Generation register 4" + +/** Address of the TRIG_3 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_3_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_3_OFFSET) + +/** Get the content of the TRIG_3 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_3_ADDR(UNIT))) + +/** Set the content of the TRIG_3 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_3_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_3 register. + * + * \return the description of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_DESC; +} + + +/** + * Get the offset of the TRIG_3 register. + * + * \return the offset of TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_3_OFFSET; +} + + +/** + * Get the address of the TRIG_3 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_3 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_3_ADDR(instance); +} + + +/** + * Read the content of the TRIG_3 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_3 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET(instance); +} + + +/** + * Write the content of the TRIG_3 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_3 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_3_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_3_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_3 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_S 0 + +/** Check whether access to the EN field of the TRIG_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_EN_P 0 + +/** Read the content of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EN_LSB, ATON_DEBUG_TRACE_TRIG_3_EN_W) + +/** Modify the content of the EN field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EN_LSB, ATON_DEBUG_TRACE_TRIG_3_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_3 register. + * + * \return the description of the EN field of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * + * \return the content of the EN field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_3_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_3 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SEL_LSB, ATON_DEBUG_TRACE_TRIG_3_SEL_W) + +/** Modify the content of the SEL field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SEL_LSB, ATON_DEBUG_TRACE_TRIG_3_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_3 register. + * + * \return the description of the SEL field of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * + * \return the content of the SEL field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_3_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_3 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_3 register. + * + * \return the description of the SWTRIG field of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * + * \return the content of the SWTRIG field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_3_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_3 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_OVR_LSB, ATON_DEBUG_TRACE_TRIG_3_OVR_W) + +/** Modify the content of the OVR field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_OVR_LSB, ATON_DEBUG_TRACE_TRIG_3_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_3 register. + * + * \return the description of the OVR field of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * + * \return the content of the OVR field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_3_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_3 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_3 register. + * + * \return the description of the EVENT_TYPE field of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_3_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_3 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_3_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_3_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_3 register. */ +#define ATON_DEBUG_TRACE_TRIG_3_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_3_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_3 register. + * + * \return the description of the FILTER field of TRIG_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * + * \return the content of the FILTER field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_3_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_3 register. + * + * \param[in] reg is the value of the TRIG_3 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_3_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_4 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_4 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_4_OFFSET 0x2cUL + +/** Reset value of the TRIG_4 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_4_DT \ + (ATON_DEBUG_TRACE_TRIG_4_EN_DT << ATON_DEBUG_TRACE_TRIG_4_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_4_SEL_DT << ATON_DEBUG_TRACE_TRIG_4_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_4_OVR_DT << ATON_DEBUG_TRACE_TRIG_4_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_4_FILTER_DT << ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB) + + + +/** Description of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_DESC "Trigger Generation register 5" + +/** Address of the TRIG_4 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_4_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_4_OFFSET) + +/** Get the content of the TRIG_4 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_4_ADDR(UNIT))) + +/** Set the content of the TRIG_4 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_4_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_4 register. + * + * \return the description of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_DESC; +} + + +/** + * Get the offset of the TRIG_4 register. + * + * \return the offset of TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_4_OFFSET; +} + + +/** + * Get the address of the TRIG_4 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_4 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_4_ADDR(instance); +} + + +/** + * Read the content of the TRIG_4 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_4 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET(instance); +} + + +/** + * Write the content of the TRIG_4 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_4 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_4_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_4_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_4 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_S 0 + +/** Check whether access to the EN field of the TRIG_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_EN_P 0 + +/** Read the content of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EN_LSB, ATON_DEBUG_TRACE_TRIG_4_EN_W) + +/** Modify the content of the EN field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EN_LSB, ATON_DEBUG_TRACE_TRIG_4_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_4 register. + * + * \return the description of the EN field of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * + * \return the content of the EN field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_4_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_4 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SEL_LSB, ATON_DEBUG_TRACE_TRIG_4_SEL_W) + +/** Modify the content of the SEL field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SEL_LSB, ATON_DEBUG_TRACE_TRIG_4_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_4 register. + * + * \return the description of the SEL field of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * + * \return the content of the SEL field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_4_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_4 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_4 register. + * + * \return the description of the SWTRIG field of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * + * \return the content of the SWTRIG field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_4_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_4 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_OVR_LSB, ATON_DEBUG_TRACE_TRIG_4_OVR_W) + +/** Modify the content of the OVR field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_OVR_LSB, ATON_DEBUG_TRACE_TRIG_4_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_4 register. + * + * \return the description of the OVR field of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * + * \return the content of the OVR field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_4_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_4 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_4 register. + * + * \return the description of the EVENT_TYPE field of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_4_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_4 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_4_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_4_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_4 register. */ +#define ATON_DEBUG_TRACE_TRIG_4_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_4_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_4 register. + * + * \return the description of the FILTER field of TRIG_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * + * \return the content of the FILTER field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_4_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_4 register. + * + * \param[in] reg is the value of the TRIG_4 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_4_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_5 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_5 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_5_OFFSET 0x30UL + +/** Reset value of the TRIG_5 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_5_DT \ + (ATON_DEBUG_TRACE_TRIG_5_EN_DT << ATON_DEBUG_TRACE_TRIG_5_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_5_SEL_DT << ATON_DEBUG_TRACE_TRIG_5_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_5_OVR_DT << ATON_DEBUG_TRACE_TRIG_5_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_5_FILTER_DT << ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB) + + + +/** Description of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_DESC "Trigger Generation register 6" + +/** Address of the TRIG_5 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_5_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_5_OFFSET) + +/** Get the content of the TRIG_5 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_5_ADDR(UNIT))) + +/** Set the content of the TRIG_5 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_5_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_5 register. + * + * \return the description of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_DESC; +} + + +/** + * Get the offset of the TRIG_5 register. + * + * \return the offset of TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_5_OFFSET; +} + + +/** + * Get the address of the TRIG_5 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_5 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_5_ADDR(instance); +} + + +/** + * Read the content of the TRIG_5 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_5 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET(instance); +} + + +/** + * Write the content of the TRIG_5 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_5 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_5_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_5_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_5 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_S 0 + +/** Check whether access to the EN field of the TRIG_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_EN_P 0 + +/** Read the content of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EN_LSB, ATON_DEBUG_TRACE_TRIG_5_EN_W) + +/** Modify the content of the EN field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EN_LSB, ATON_DEBUG_TRACE_TRIG_5_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_5 register. + * + * \return the description of the EN field of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * + * \return the content of the EN field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_5_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_5 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SEL_LSB, ATON_DEBUG_TRACE_TRIG_5_SEL_W) + +/** Modify the content of the SEL field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SEL_LSB, ATON_DEBUG_TRACE_TRIG_5_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_5 register. + * + * \return the description of the SEL field of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * + * \return the content of the SEL field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_5_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_5 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_5 register. + * + * \return the description of the SWTRIG field of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * + * \return the content of the SWTRIG field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_5_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_5 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_OVR_LSB, ATON_DEBUG_TRACE_TRIG_5_OVR_W) + +/** Modify the content of the OVR field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_OVR_LSB, ATON_DEBUG_TRACE_TRIG_5_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_5 register. + * + * \return the description of the OVR field of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * + * \return the content of the OVR field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_5_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_5 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_5 register. + * + * \return the description of the EVENT_TYPE field of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_5_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_5 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_5_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_5_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_5 register. */ +#define ATON_DEBUG_TRACE_TRIG_5_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_5_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_5 register. + * + * \return the description of the FILTER field of TRIG_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * + * \return the content of the FILTER field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_5_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_5 register. + * + * \param[in] reg is the value of the TRIG_5 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_5_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_6 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_6 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_6_OFFSET 0x34UL + +/** Reset value of the TRIG_6 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_6_DT \ + (ATON_DEBUG_TRACE_TRIG_6_EN_DT << ATON_DEBUG_TRACE_TRIG_6_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_6_SEL_DT << ATON_DEBUG_TRACE_TRIG_6_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_6_OVR_DT << ATON_DEBUG_TRACE_TRIG_6_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_6_FILTER_DT << ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB) + + + +/** Description of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_DESC "Trigger Generation register 7" + +/** Address of the TRIG_6 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_6_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_6_OFFSET) + +/** Get the content of the TRIG_6 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_6_ADDR(UNIT))) + +/** Set the content of the TRIG_6 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_6_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_6 register. + * + * \return the description of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_DESC; +} + + +/** + * Get the offset of the TRIG_6 register. + * + * \return the offset of TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_6_OFFSET; +} + + +/** + * Get the address of the TRIG_6 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_6 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_6_ADDR(instance); +} + + +/** + * Read the content of the TRIG_6 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_6 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET(instance); +} + + +/** + * Write the content of the TRIG_6 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_6 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_6_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_6_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_6 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_S 0 + +/** Check whether access to the EN field of the TRIG_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_EN_P 0 + +/** Read the content of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EN_LSB, ATON_DEBUG_TRACE_TRIG_6_EN_W) + +/** Modify the content of the EN field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EN_LSB, ATON_DEBUG_TRACE_TRIG_6_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_6 register. + * + * \return the description of the EN field of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * + * \return the content of the EN field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_6_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_6 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SEL_LSB, ATON_DEBUG_TRACE_TRIG_6_SEL_W) + +/** Modify the content of the SEL field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SEL_LSB, ATON_DEBUG_TRACE_TRIG_6_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_6 register. + * + * \return the description of the SEL field of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * + * \return the content of the SEL field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_6_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_6 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_6 register. + * + * \return the description of the SWTRIG field of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * + * \return the content of the SWTRIG field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_6_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_6 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_OVR_LSB, ATON_DEBUG_TRACE_TRIG_6_OVR_W) + +/** Modify the content of the OVR field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_OVR_LSB, ATON_DEBUG_TRACE_TRIG_6_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_6 register. + * + * \return the description of the OVR field of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * + * \return the content of the OVR field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_6_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_6 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_6 register. + * + * \return the description of the EVENT_TYPE field of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_6_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_6 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_6_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_6_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_6 register. */ +#define ATON_DEBUG_TRACE_TRIG_6_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_6_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_6 register. + * + * \return the description of the FILTER field of TRIG_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * + * \return the content of the FILTER field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_6_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_6 register. + * + * \param[in] reg is the value of the TRIG_6 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_6_SET_FILTER(reg, data); +} + + +/* **************************************************** TRIG_7 register of one of the DEBUG_TRACE Units ***************************************************** */ + +/** Offset of the TRIG_7 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_7_OFFSET 0x38UL + +/** Reset value of the TRIG_7 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_TRIG_7_DT \ + (ATON_DEBUG_TRACE_TRIG_7_EN_DT << ATON_DEBUG_TRACE_TRIG_7_EN_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_7_SEL_DT << ATON_DEBUG_TRACE_TRIG_7_SEL_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_7_OVR_DT << ATON_DEBUG_TRACE_TRIG_7_OVR_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_TRIG_7_FILTER_DT << ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB) + + + +/** Description of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_DESC "Trigger Generation register 8" + +/** Address of the TRIG_7 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_7_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_7_OFFSET) + +/** Get the content of the TRIG_7 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_7_ADDR(UNIT))) + +/** Set the content of the TRIG_7 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_7_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of TRIG_7 register. + * + * \return the description of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_DESC; +} + + +/** + * Get the offset of the TRIG_7 register. + * + * \return the offset of TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_GetOffset(void) +{ + return ATON_DEBUG_TRACE_TRIG_7_OFFSET; +} + + +/** + * Get the address of the TRIG_7 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_7 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of TRIG_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_7_ADDR(instance); +} + + +/** + * Read the content of the TRIG_7 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_7 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of TRIG_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET(instance); +} + + +/** + * Write the content of the TRIG_7 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_7 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_TRIG_7_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_TRIG_7_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the TRIG_7 register ------------------------------------------------------------- */ + +/** Description of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_DESC "Enable trigger generation" + +/** Offset of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_LSB 0UL + +/** Size in bits of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_W (1UL) + +/** Mask for retrieving the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_DT 0x0UL + +/** Access rights of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_AC "RW" + +/** Check whether access to the EN field of the TRIG_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_S 0 + +/** Check whether access to the EN field of the TRIG_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_EN_P 0 + +/** Read the content of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EN_LSB, ATON_DEBUG_TRACE_TRIG_7_EN_W) + +/** Modify the content of the EN field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EN_LSB, ATON_DEBUG_TRACE_TRIG_7_EN_W, DATA) + + +/** + * Get the description of the EN field of TRIG_7 register. + * + * \return the description of the EN field of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_EN_DESC; +} + + +/** + * Read the content of the EN field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * + * \return the content of the EN field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_7_SET_EN(reg, data); +} + + +/* ------------------------------------------------------------ SEL field of the TRIG_7 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_LSB 1UL + +/** Size in bits of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_W (9UL) + +/** Mask for retrieving the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) + +/** Reset value of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_DT 0x0UL + +/** Access rights of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_AC "RW" + +/** Check whether access to the SEL field of the TRIG_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_S 0 + +/** Check whether access to the SEL field of the TRIG_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_SEL_P 0 + +/** Read the content of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SEL_LSB, ATON_DEBUG_TRACE_TRIG_7_SEL_W) + +/** Modify the content of the SEL field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SEL_LSB, ATON_DEBUG_TRACE_TRIG_7_SEL_W, DATA) + + +/** + * Get the description of the SEL field of TRIG_7 register. + * + * \return the description of the SEL field of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * + * \return the content of the SEL field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * \param[in] data is 9-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_7_SET_SEL(reg, data); +} + + +/* ---------------------------------------------------------- SWTRIG field of the TRIG_7 register ----------------------------------------------------------- */ + +/** Description of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DESC "SW generated trigger (autocleared)" + +/** Offset of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB 10UL + +/** Size in bits of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_W (1UL) + +/** Mask for retrieving the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) + +/** Reset value of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DT 0x0UL + +/** Access rights of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_AC "RW" + +/** Check whether access to the SWTRIG field of the TRIG_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_S 0 + +/** Check whether access to the SWTRIG field of the TRIG_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_P 0 + +/** Read the content of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_W) + +/** Modify the content of the SWTRIG field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_W, DATA) + + +/** + * Get the description of the SWTRIG field of TRIG_7 register. + * + * \return the description of the SWTRIG field of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_SWTRIG_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DESC; +} + + +/** + * Read the content of the SWTRIG field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * + * \return the content of the SWTRIG field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_SWTRIG(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET_SWTRIG(reg); +} + + +/** + * Write the content of the SWTRIG field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the SWTRIG field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_SWTRIG(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_7_SET_SWTRIG(reg, data); +} + + +/* ------------------------------------------------------------ OVR field of the TRIG_7 register ------------------------------------------------------------ */ + +/** Description of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_DESC "Multiple events detected within 10 clock periods" + +/** Offset of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_LSB 11UL + +/** Size in bits of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_W (1UL) + +/** Mask for retrieving the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) + +/** Reset value of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_DT 0x0UL + +/** Access rights of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_AC "RW" + +/** Check whether access to the OVR field of the TRIG_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_S 0 + +/** Check whether access to the OVR field of the TRIG_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_OVR_P 0 + +/** Read the content of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_OVR_LSB, ATON_DEBUG_TRACE_TRIG_7_OVR_W) + +/** Modify the content of the OVR field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_OVR_LSB, ATON_DEBUG_TRACE_TRIG_7_OVR_W, DATA) + + +/** + * Get the description of the OVR field of TRIG_7 register. + * + * \return the description of the OVR field of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_OVR_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_OVR_DESC; +} + + +/** + * Read the content of the OVR field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * + * \return the content of the OVR field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_OVR(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET_OVR(reg); +} + + +/** + * Write the content of the OVR field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the OVR field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_OVR(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_7_SET_OVR(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the TRIG_7 register --------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the TRIG_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the TRIG_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of TRIG_7 register. + * + * \return the description of the EVENT_TYPE field of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * + * \return the content of the EVENT_TYPE field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_7_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- FILTER field of the TRIG_7 register ----------------------------------------------------------- */ + +/** Description of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_DESC "Number of events to detect before sending a trigger" + +/** Offset of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB 16UL + +/** Size in bits of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_W (16UL) + +/** Mask for retrieving the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) + +/** Reset value of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_DT 0x1UL + +/** Access rights of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_AC "RW" + +/** Check whether access to the FILTER field of the TRIG_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_S 0 + +/** Check whether access to the FILTER field of the TRIG_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_TRIG_7_FILTER_P 0 + +/** Read the content of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_7_FILTER_W) + +/** Modify the content of the FILTER field of the TRIG_7 register. */ +#define ATON_DEBUG_TRACE_TRIG_7_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_7_FILTER_W, DATA) + + +/** + * Get the description of the FILTER field of TRIG_7 register. + * + * \return the description of the FILTER field of TRIG_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_FILTER_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_FILTER_DESC; +} + + +/** + * Read the content of the FILTER field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * + * \return the content of the FILTER field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_FILTER(uint32_t reg) +{ + return ATON_DEBUG_TRACE_TRIG_7_GET_FILTER(reg); +} + + +/** + * Write the content of the FILTER field of the TRIG_7 register. + * + * \param[in] reg is the value of the TRIG_7 register + * \param[in] data is 16-bit value that must be written to the field + * + * \return the new content of the FILTER field belonging to TRIG_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_FILTER(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_TRIG_7_SET_FILTER(reg, data); +} + + +/* **************************************************** EVENT_0 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_0 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_0_OFFSET 0x40UL + +/** Reset value of the EVENT_0 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_0_DT \ + (ATON_DEBUG_TRACE_EVENT_0_EN_DT << ATON_DEBUG_TRACE_EVENT_0_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_SEL_DT << ATON_DEBUG_TRACE_EVENT_0_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_WRAP_DT << ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_DESC "Observer register 1" + +/** Address of the EVENT_0 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_0_OFFSET) + +/** Get the content of the EVENT_0 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT))) + +/** Set the content of the EVENT_0 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_0 register. + * + * \return the description of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_DESC; +} + + +/** + * Get the offset of the EVENT_0 register. + * + * \return the offset of EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_0_OFFSET; +} + + +/** + * Get the address of the EVENT_0 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_0_ADDR(instance); +} + + +/** + * Read the content of the EVENT_0 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET(instance); +} + + +/** + * Write the content of the EVENT_0 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_0_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_0_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_0 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_S 0 + +/** Check whether access to the EN field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_EN_P 0 + +/** Read the content of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_EN_W) + +/** Modify the content of the EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_0 register. + * + * \return the description of the EN field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the EN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_0 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_SEL_W) + +/** Modify the content of the SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_0 register. + * + * \return the description of the SEL field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the SEL field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_0 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_0 register. + * + * \return the description of the EVENT_TYPE field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_0 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_0_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_0_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_0 register. + * + * \return the description of the WRAP field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the WRAP field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_0 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_0 register. + * + * \return the description of the CNT_DOWN field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_0 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_0 register. + * + * \return the description of the INT_DISABLE field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_0 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_0 register. + * + * \return the description of the START_EVENT_EN field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_0 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_0 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_0 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_0 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_0 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_0 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_0 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_0 register. */ +#define ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_0 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_0 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_0 register. + * + * \param[in] reg is the value of the EVENT_0 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_0 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_1 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_1 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_1_OFFSET 0x44UL + +/** Reset value of the EVENT_1 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_1_DT \ + (ATON_DEBUG_TRACE_EVENT_1_EN_DT << ATON_DEBUG_TRACE_EVENT_1_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_SEL_DT << ATON_DEBUG_TRACE_EVENT_1_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_WRAP_DT << ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_DESC "Observer register 2" + +/** Address of the EVENT_1 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_1_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_1_OFFSET) + +/** Get the content of the EVENT_1 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_ADDR(UNIT))) + +/** Set the content of the EVENT_1 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_1 register. + * + * \return the description of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_DESC; +} + + +/** + * Get the offset of the EVENT_1 register. + * + * \return the offset of EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_1_OFFSET; +} + + +/** + * Get the address of the EVENT_1 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_1_ADDR(instance); +} + + +/** + * Read the content of the EVENT_1 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET(instance); +} + + +/** + * Write the content of the EVENT_1 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_1_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_1_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_1 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_S 0 + +/** Check whether access to the EN field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_EN_P 0 + +/** Read the content of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_EN_W) + +/** Modify the content of the EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_1 register. + * + * \return the description of the EN field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the EN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_1 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_SEL_W) + +/** Modify the content of the SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_1 register. + * + * \return the description of the SEL field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the SEL field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_1 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_1 register. + * + * \return the description of the EVENT_TYPE field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_1 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_1_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_1_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_1 register. + * + * \return the description of the WRAP field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the WRAP field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_1 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_1 register. + * + * \return the description of the CNT_DOWN field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_1 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_1 register. + * + * \return the description of the INT_DISABLE field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_1 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_1 register. + * + * \return the description of the START_EVENT_EN field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_1 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_1 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_1 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_1 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_1 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_1 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_1 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_1 register. */ +#define ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_1 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_1 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_1 register. + * + * \param[in] reg is the value of the EVENT_1 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_1 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_2 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_2 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_2_OFFSET 0x48UL + +/** Reset value of the EVENT_2 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_2_DT \ + (ATON_DEBUG_TRACE_EVENT_2_EN_DT << ATON_DEBUG_TRACE_EVENT_2_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_SEL_DT << ATON_DEBUG_TRACE_EVENT_2_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_WRAP_DT << ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_DESC "Observer register 3" + +/** Address of the EVENT_2 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_2_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_2_OFFSET) + +/** Get the content of the EVENT_2 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_ADDR(UNIT))) + +/** Set the content of the EVENT_2 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_2 register. + * + * \return the description of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_DESC; +} + + +/** + * Get the offset of the EVENT_2 register. + * + * \return the offset of EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_2_OFFSET; +} + + +/** + * Get the address of the EVENT_2 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_2_ADDR(instance); +} + + +/** + * Read the content of the EVENT_2 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET(instance); +} + + +/** + * Write the content of the EVENT_2 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_2_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_2_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_2 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_S 0 + +/** Check whether access to the EN field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_EN_P 0 + +/** Read the content of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_EN_W) + +/** Modify the content of the EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_2 register. + * + * \return the description of the EN field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the EN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_2 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_SEL_W) + +/** Modify the content of the SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_2 register. + * + * \return the description of the SEL field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the SEL field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_2 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_2 register. + * + * \return the description of the EVENT_TYPE field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_2 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_2_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_2_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_2 register. + * + * \return the description of the WRAP field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the WRAP field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_2 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_2 register. + * + * \return the description of the CNT_DOWN field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_2 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_2 register. + * + * \return the description of the INT_DISABLE field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_2 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_2 register. + * + * \return the description of the START_EVENT_EN field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_2 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_2 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_2 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_2 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_2 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_2 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_2 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_2 register. */ +#define ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_2 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_2 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_2 register. + * + * \param[in] reg is the value of the EVENT_2 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_2 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_3 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_3 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_3_OFFSET 0x4cUL + +/** Reset value of the EVENT_3 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_3_DT \ + (ATON_DEBUG_TRACE_EVENT_3_EN_DT << ATON_DEBUG_TRACE_EVENT_3_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_SEL_DT << ATON_DEBUG_TRACE_EVENT_3_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_WRAP_DT << ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_DESC "Observer register 4" + +/** Address of the EVENT_3 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_3_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_3_OFFSET) + +/** Get the content of the EVENT_3 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_ADDR(UNIT))) + +/** Set the content of the EVENT_3 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_3 register. + * + * \return the description of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_DESC; +} + + +/** + * Get the offset of the EVENT_3 register. + * + * \return the offset of EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_3_OFFSET; +} + + +/** + * Get the address of the EVENT_3 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_3_ADDR(instance); +} + + +/** + * Read the content of the EVENT_3 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET(instance); +} + + +/** + * Write the content of the EVENT_3 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_3_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_3_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_3 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_S 0 + +/** Check whether access to the EN field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_EN_P 0 + +/** Read the content of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_EN_W) + +/** Modify the content of the EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_3 register. + * + * \return the description of the EN field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the EN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_3 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_SEL_W) + +/** Modify the content of the SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_3 register. + * + * \return the description of the SEL field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the SEL field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_3 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_3 register. + * + * \return the description of the EVENT_TYPE field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_3 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_3_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_3_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_3 register. + * + * \return the description of the WRAP field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the WRAP field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_3 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_3 register. + * + * \return the description of the CNT_DOWN field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_3 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_3 register. + * + * \return the description of the INT_DISABLE field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_3 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_3 register. + * + * \return the description of the START_EVENT_EN field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_3 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_3 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_3 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_3 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_3 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_3 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_3 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_3 register. */ +#define ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_3 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_3 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_3 register. + * + * \param[in] reg is the value of the EVENT_3 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_3 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_4 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_4 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_4_OFFSET 0x50UL + +/** Reset value of the EVENT_4 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_4_DT \ + (ATON_DEBUG_TRACE_EVENT_4_EN_DT << ATON_DEBUG_TRACE_EVENT_4_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_SEL_DT << ATON_DEBUG_TRACE_EVENT_4_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_WRAP_DT << ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_DESC "Observer register 5" + +/** Address of the EVENT_4 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_4_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_4_OFFSET) + +/** Get the content of the EVENT_4 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_ADDR(UNIT))) + +/** Set the content of the EVENT_4 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_4 register. + * + * \return the description of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_DESC; +} + + +/** + * Get the offset of the EVENT_4 register. + * + * \return the offset of EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_4_OFFSET; +} + + +/** + * Get the address of the EVENT_4 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_4_ADDR(instance); +} + + +/** + * Read the content of the EVENT_4 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET(instance); +} + + +/** + * Write the content of the EVENT_4 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_4_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_4_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_4 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_S 0 + +/** Check whether access to the EN field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_EN_P 0 + +/** Read the content of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_EN_W) + +/** Modify the content of the EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_4 register. + * + * \return the description of the EN field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the EN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_4 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_SEL_W) + +/** Modify the content of the SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_4 register. + * + * \return the description of the SEL field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the SEL field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_4 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_4 register. + * + * \return the description of the EVENT_TYPE field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_4 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_4_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_4_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_4 register. + * + * \return the description of the WRAP field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the WRAP field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_4 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_4 register. + * + * \return the description of the CNT_DOWN field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_4 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_4 register. + * + * \return the description of the INT_DISABLE field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_4 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_4 register. + * + * \return the description of the START_EVENT_EN field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_4 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_4 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_4 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_4 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_4 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_4 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_4 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_4 register. */ +#define ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_4 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_4 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_4 register. + * + * \param[in] reg is the value of the EVENT_4 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_4 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_5 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_5 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_5_OFFSET 0x54UL + +/** Reset value of the EVENT_5 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_5_DT \ + (ATON_DEBUG_TRACE_EVENT_5_EN_DT << ATON_DEBUG_TRACE_EVENT_5_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_SEL_DT << ATON_DEBUG_TRACE_EVENT_5_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_WRAP_DT << ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_DESC "Observer register 6" + +/** Address of the EVENT_5 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_5_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_5_OFFSET) + +/** Get the content of the EVENT_5 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_ADDR(UNIT))) + +/** Set the content of the EVENT_5 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_5 register. + * + * \return the description of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_DESC; +} + + +/** + * Get the offset of the EVENT_5 register. + * + * \return the offset of EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_5_OFFSET; +} + + +/** + * Get the address of the EVENT_5 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_5_ADDR(instance); +} + + +/** + * Read the content of the EVENT_5 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET(instance); +} + + +/** + * Write the content of the EVENT_5 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_5_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_5_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_5 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_S 0 + +/** Check whether access to the EN field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_EN_P 0 + +/** Read the content of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_EN_W) + +/** Modify the content of the EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_5 register. + * + * \return the description of the EN field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the EN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_5 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_SEL_W) + +/** Modify the content of the SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_5 register. + * + * \return the description of the SEL field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the SEL field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_5 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_5 register. + * + * \return the description of the EVENT_TYPE field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_5 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_5_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_5_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_5 register. + * + * \return the description of the WRAP field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the WRAP field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_5 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_5 register. + * + * \return the description of the CNT_DOWN field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_5 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_5 register. + * + * \return the description of the INT_DISABLE field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_5 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_5 register. + * + * \return the description of the START_EVENT_EN field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_5 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_5 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_5 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_5 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_5 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_5 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_5 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_5 register. */ +#define ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_5 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_5 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_5 register. + * + * \param[in] reg is the value of the EVENT_5 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_5 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_6 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_6 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_6_OFFSET 0x58UL + +/** Reset value of the EVENT_6 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_6_DT \ + (ATON_DEBUG_TRACE_EVENT_6_EN_DT << ATON_DEBUG_TRACE_EVENT_6_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_SEL_DT << ATON_DEBUG_TRACE_EVENT_6_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_WRAP_DT << ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_DESC "Observer register 7" + +/** Address of the EVENT_6 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_6_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_6_OFFSET) + +/** Get the content of the EVENT_6 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_ADDR(UNIT))) + +/** Set the content of the EVENT_6 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_6 register. + * + * \return the description of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_DESC; +} + + +/** + * Get the offset of the EVENT_6 register. + * + * \return the offset of EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_6_OFFSET; +} + + +/** + * Get the address of the EVENT_6 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_6_ADDR(instance); +} + + +/** + * Read the content of the EVENT_6 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET(instance); +} + + +/** + * Write the content of the EVENT_6 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_6_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_6_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_6 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_S 0 + +/** Check whether access to the EN field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_EN_P 0 + +/** Read the content of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_EN_W) + +/** Modify the content of the EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_6 register. + * + * \return the description of the EN field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the EN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_6 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_SEL_W) + +/** Modify the content of the SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_6 register. + * + * \return the description of the SEL field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the SEL field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_6 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_6 register. + * + * \return the description of the EVENT_TYPE field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_6 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_6_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_6_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_6 register. + * + * \return the description of the WRAP field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the WRAP field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_6 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_6 register. + * + * \return the description of the CNT_DOWN field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_6 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_6 register. + * + * \return the description of the INT_DISABLE field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_6 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_6 register. + * + * \return the description of the START_EVENT_EN field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_6 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_6 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_6 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_6 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_6 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_6 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_6 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_6 register. */ +#define ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_6 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_6 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_6 register. + * + * \param[in] reg is the value of the EVENT_6 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_6 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_7 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_7 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_7_OFFSET 0x5cUL + +/** Reset value of the EVENT_7 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_7_DT \ + (ATON_DEBUG_TRACE_EVENT_7_EN_DT << ATON_DEBUG_TRACE_EVENT_7_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_SEL_DT << ATON_DEBUG_TRACE_EVENT_7_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_WRAP_DT << ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_DESC "Observer register 8" + +/** Address of the EVENT_7 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_7_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_7_OFFSET) + +/** Get the content of the EVENT_7 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_ADDR(UNIT))) + +/** Set the content of the EVENT_7 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_7 register. + * + * \return the description of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_DESC; +} + + +/** + * Get the offset of the EVENT_7 register. + * + * \return the offset of EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_7_OFFSET; +} + + +/** + * Get the address of the EVENT_7 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_7_ADDR(instance); +} + + +/** + * Read the content of the EVENT_7 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET(instance); +} + + +/** + * Write the content of the EVENT_7 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_7_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_7_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_7 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_S 0 + +/** Check whether access to the EN field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_EN_P 0 + +/** Read the content of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_EN_W) + +/** Modify the content of the EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_7 register. + * + * \return the description of the EN field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the EN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_7 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_SEL_W) + +/** Modify the content of the SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_7 register. + * + * \return the description of the SEL field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the SEL field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_7 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_7 register. + * + * \return the description of the EVENT_TYPE field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_7 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_7_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_7_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_7 register. + * + * \return the description of the WRAP field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the WRAP field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_7 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_7 register. + * + * \return the description of the CNT_DOWN field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_7 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_7 register. + * + * \return the description of the INT_DISABLE field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_7 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_7 register. + * + * \return the description of the START_EVENT_EN field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_7 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_7 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_7 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_7 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_7 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_7 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_7 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_7 register. */ +#define ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_7 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_7 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_7 register. + * + * \param[in] reg is the value of the EVENT_7 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_7 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_8 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_8 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_8_OFFSET 0x60UL + +/** Reset value of the EVENT_8 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_8_DT \ + (ATON_DEBUG_TRACE_EVENT_8_EN_DT << ATON_DEBUG_TRACE_EVENT_8_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_SEL_DT << ATON_DEBUG_TRACE_EVENT_8_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_WRAP_DT << ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_DESC "Observer register 9" + +/** Address of the EVENT_8 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_8_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_8_OFFSET) + +/** Get the content of the EVENT_8 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_ADDR(UNIT))) + +/** Set the content of the EVENT_8 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_8 register. + * + * \return the description of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_DESC; +} + + +/** + * Get the offset of the EVENT_8 register. + * + * \return the offset of EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_8_OFFSET; +} + + +/** + * Get the address of the EVENT_8 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_8 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_8_ADDR(instance); +} + + +/** + * Read the content of the EVENT_8 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_8 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET(instance); +} + + +/** + * Write the content of the EVENT_8 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_8_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_8_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_8 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_S 0 + +/** Check whether access to the EN field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_EN_P 0 + +/** Read the content of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_EN_W) + +/** Modify the content of the EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_8 register. + * + * \return the description of the EN field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the EN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_8 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_SEL_W) + +/** Modify the content of the SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_8 register. + * + * \return the description of the SEL field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the SEL field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_8 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_8 register. + * + * \return the description of the EVENT_TYPE field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_8 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_8_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_8_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_8 register. + * + * \return the description of the WRAP field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the WRAP field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_8 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_8 register. + * + * \return the description of the CNT_DOWN field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_8 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_8 register. + * + * \return the description of the INT_DISABLE field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_8 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_8 register. + * + * \return the description of the START_EVENT_EN field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_8 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_8 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_8 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_8 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_8 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_8 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_8 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_8 register. */ +#define ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_8 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_8 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_8 register. + * + * \param[in] reg is the value of the EVENT_8 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_8 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_SEL(reg, data); +} + + +/* **************************************************** EVENT_9 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_9 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_9_OFFSET 0x64UL + +/** Reset value of the EVENT_9 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_9_DT \ + (ATON_DEBUG_TRACE_EVENT_9_EN_DT << ATON_DEBUG_TRACE_EVENT_9_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_SEL_DT << ATON_DEBUG_TRACE_EVENT_9_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_WRAP_DT << ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_DESC "Observer register 10" + +/** Address of the EVENT_9 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_9_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_9_OFFSET) + +/** Get the content of the EVENT_9 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_ADDR(UNIT))) + +/** Set the content of the EVENT_9 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_9 register. + * + * \return the description of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_DESC; +} + + +/** + * Get the offset of the EVENT_9 register. + * + * \return the offset of EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_9_OFFSET; +} + + +/** + * Get the address of the EVENT_9 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_9 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_9_ADDR(instance); +} + + +/** + * Read the content of the EVENT_9 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_9 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET(instance); +} + + +/** + * Write the content of the EVENT_9 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_9_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_9_SET(instance, data); +} + + +/* ------------------------------------------------------------ EN field of the EVENT_9 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_S 0 + +/** Check whether access to the EN field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_EN_P 0 + +/** Read the content of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_EN_W) + +/** Modify the content of the EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_9 register. + * + * \return the description of the EN field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the EN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_9 register ------------------------------------------------------------ */ + +/** Description of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_SEL_W) + +/** Modify the content of the SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_9 register. + * + * \return the description of the SEL field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the SEL field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_SEL(reg, data); +} + + +/* -------------------------------------------------------- EVENT_TYPE field of the EVENT_9 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_9 register. + * + * \return the description of the EVENT_TYPE field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_EVENT_TYPE(reg, data); +} + + +/* ----------------------------------------------------------- WRAP field of the EVENT_9 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_9_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_9_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_9 register. + * + * \return the description of the WRAP field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the WRAP field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_WRAP(reg, data); +} + + +/* --------------------------------------------------------- CNT_DOWN field of the EVENT_9 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_9 register. + * + * \return the description of the CNT_DOWN field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_9 register -------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_9 register. + * + * \return the description of the INT_DISABLE field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_INT_DISABLE(reg, data); +} + + +/* ------------------------------------------------------ START_EVENT_EN field of the EVENT_9 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_9 register. + * + * \return the description of the START_EVENT_EN field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_9 register ------------------------------------------------------- */ + +/** Description of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_9 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_9 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_9 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_SEL(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_9 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_9 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_9 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_9 register. */ +#define ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_9 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_9 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_9 register. + * + * \param[in] reg is the value of the EVENT_9 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_9 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_SEL(reg, data); +} + + +/* *************************************************** EVENT_10 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_10 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_10_OFFSET 0x68UL + +/** Reset value of the EVENT_10 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_10_DT \ + (ATON_DEBUG_TRACE_EVENT_10_EN_DT << ATON_DEBUG_TRACE_EVENT_10_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_SEL_DT << ATON_DEBUG_TRACE_EVENT_10_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_WRAP_DT << ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_DESC "Observer register 11" + +/** Address of the EVENT_10 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_10_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_10_OFFSET) + +/** Get the content of the EVENT_10 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_ADDR(UNIT))) + +/** Set the content of the EVENT_10 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_10 register. + * + * \return the description of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_DESC; +} + + +/** + * Get the offset of the EVENT_10 register. + * + * \return the offset of EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_10_OFFSET; +} + + +/** + * Get the address of the EVENT_10 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_10 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_10_ADDR(instance); +} + + +/** + * Read the content of the EVENT_10 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_10 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET(instance); +} + + +/** + * Write the content of the EVENT_10 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_10_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_10_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN field of the EVENT_10 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_S 0 + +/** Check whether access to the EN field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_EN_P 0 + +/** Read the content of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_EN_W) + +/** Modify the content of the EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_10 register. + * + * \return the description of the EN field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the EN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_10 register ----------------------------------------------------------- */ + +/** Description of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_SEL_W) + +/** Modify the content of the SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_10 register. + * + * \return the description of the SEL field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the SEL field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_SEL(reg, data); +} + + +/* ------------------------------------------------------- EVENT_TYPE field of the EVENT_10 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_10 register. + * + * \return the description of the EVENT_TYPE field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- WRAP field of the EVENT_10 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_10_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_10_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_10 register. + * + * \return the description of the WRAP field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the WRAP field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_WRAP(reg, data); +} + + +/* -------------------------------------------------------- CNT_DOWN field of the EVENT_10 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_10 register. + * + * \return the description of the CNT_DOWN field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_10 register ------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_10 register. + * + * \return the description of the INT_DISABLE field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_INT_DISABLE(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_EN field of the EVENT_10 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_10 register. + * + * \return the description of the START_EVENT_EN field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_10 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_10 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_10 register ----------------------------------------------------- */ + +/** Description of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_10 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_SEL(reg, data); +} + + +/* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_10 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_10 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_10 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_10 register. */ +#define ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_10 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_10 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_10 register. + * + * \param[in] reg is the value of the EVENT_10 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_10 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_SEL(reg, data); +} + + +/* *************************************************** EVENT_11 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_11 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_11_OFFSET 0x6cUL + +/** Reset value of the EVENT_11 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_11_DT \ + (ATON_DEBUG_TRACE_EVENT_11_EN_DT << ATON_DEBUG_TRACE_EVENT_11_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_SEL_DT << ATON_DEBUG_TRACE_EVENT_11_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_WRAP_DT << ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_DESC "Observer register 12" + +/** Address of the EVENT_11 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_11_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_11_OFFSET) + +/** Get the content of the EVENT_11 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_ADDR(UNIT))) + +/** Set the content of the EVENT_11 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_11 register. + * + * \return the description of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_DESC; +} + + +/** + * Get the offset of the EVENT_11 register. + * + * \return the offset of EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_11_OFFSET; +} + + +/** + * Get the address of the EVENT_11 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_11 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_11_ADDR(instance); +} + + +/** + * Read the content of the EVENT_11 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_11 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET(instance); +} + + +/** + * Write the content of the EVENT_11 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_11_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_11_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN field of the EVENT_11 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_S 0 + +/** Check whether access to the EN field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_EN_P 0 + +/** Read the content of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_EN_W) + +/** Modify the content of the EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_11 register. + * + * \return the description of the EN field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the EN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_11 register ----------------------------------------------------------- */ + +/** Description of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_SEL_W) + +/** Modify the content of the SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_11 register. + * + * \return the description of the SEL field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the SEL field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_SEL(reg, data); +} + + +/* ------------------------------------------------------- EVENT_TYPE field of the EVENT_11 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_11 register. + * + * \return the description of the EVENT_TYPE field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- WRAP field of the EVENT_11 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_11_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_11_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_11 register. + * + * \return the description of the WRAP field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the WRAP field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_WRAP(reg, data); +} + + +/* -------------------------------------------------------- CNT_DOWN field of the EVENT_11 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_11 register. + * + * \return the description of the CNT_DOWN field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_11 register ------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_11 register. + * + * \return the description of the INT_DISABLE field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_INT_DISABLE(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_EN field of the EVENT_11 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_11 register. + * + * \return the description of the START_EVENT_EN field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_11 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_11 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_11 register ----------------------------------------------------- */ + +/** Description of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_11 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_SEL(reg, data); +} + + +/* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_11 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_11 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_11 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_11 register. */ +#define ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_11 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_11 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_11 register. + * + * \param[in] reg is the value of the EVENT_11 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_11 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_SEL(reg, data); +} + + +/* *************************************************** EVENT_12 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_12 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_12_OFFSET 0x70UL + +/** Reset value of the EVENT_12 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_12_DT \ + (ATON_DEBUG_TRACE_EVENT_12_EN_DT << ATON_DEBUG_TRACE_EVENT_12_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_SEL_DT << ATON_DEBUG_TRACE_EVENT_12_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_WRAP_DT << ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_DESC "Observer register 13" + +/** Address of the EVENT_12 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_12_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_12_OFFSET) + +/** Get the content of the EVENT_12 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_ADDR(UNIT))) + +/** Set the content of the EVENT_12 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_12 register. + * + * \return the description of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_DESC; +} + + +/** + * Get the offset of the EVENT_12 register. + * + * \return the offset of EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_12_OFFSET; +} + + +/** + * Get the address of the EVENT_12 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_12 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_12_ADDR(instance); +} + + +/** + * Read the content of the EVENT_12 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_12 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET(instance); +} + + +/** + * Write the content of the EVENT_12 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_12_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_12_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN field of the EVENT_12 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_S 0 + +/** Check whether access to the EN field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_EN_P 0 + +/** Read the content of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_EN_W) + +/** Modify the content of the EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_12 register. + * + * \return the description of the EN field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the EN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_12 register ----------------------------------------------------------- */ + +/** Description of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_SEL_W) + +/** Modify the content of the SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_12 register. + * + * \return the description of the SEL field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the SEL field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_SEL(reg, data); +} + + +/* ------------------------------------------------------- EVENT_TYPE field of the EVENT_12 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_12 register. + * + * \return the description of the EVENT_TYPE field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- WRAP field of the EVENT_12 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_12_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_12_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_12 register. + * + * \return the description of the WRAP field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the WRAP field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_WRAP(reg, data); +} + + +/* -------------------------------------------------------- CNT_DOWN field of the EVENT_12 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_12 register. + * + * \return the description of the CNT_DOWN field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_12 register ------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_12 register. + * + * \return the description of the INT_DISABLE field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_INT_DISABLE(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_EN field of the EVENT_12 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_12 register. + * + * \return the description of the START_EVENT_EN field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_12 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_12 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_12 register ----------------------------------------------------- */ + +/** Description of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_12 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_SEL(reg, data); +} + + +/* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_12 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_12 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_12 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_12 register. */ +#define ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_12 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_12 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_12 register. + * + * \param[in] reg is the value of the EVENT_12 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_12 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_SEL(reg, data); +} + + +/* *************************************************** EVENT_13 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_13 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_13_OFFSET 0x74UL + +/** Reset value of the EVENT_13 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_13_DT \ + (ATON_DEBUG_TRACE_EVENT_13_EN_DT << ATON_DEBUG_TRACE_EVENT_13_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_SEL_DT << ATON_DEBUG_TRACE_EVENT_13_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_WRAP_DT << ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_DESC "Observer register 14" + +/** Address of the EVENT_13 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_13_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_13_OFFSET) + +/** Get the content of the EVENT_13 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_ADDR(UNIT))) + +/** Set the content of the EVENT_13 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_13 register. + * + * \return the description of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_DESC; +} + + +/** + * Get the offset of the EVENT_13 register. + * + * \return the offset of EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_13_OFFSET; +} + + +/** + * Get the address of the EVENT_13 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_13 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_13_ADDR(instance); +} + + +/** + * Read the content of the EVENT_13 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_13 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET(instance); +} + + +/** + * Write the content of the EVENT_13 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_13_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_13_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN field of the EVENT_13 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_S 0 + +/** Check whether access to the EN field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_EN_P 0 + +/** Read the content of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_EN_W) + +/** Modify the content of the EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_13 register. + * + * \return the description of the EN field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the EN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_13 register ----------------------------------------------------------- */ + +/** Description of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_SEL_W) + +/** Modify the content of the SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_13 register. + * + * \return the description of the SEL field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the SEL field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_SEL(reg, data); +} + + +/* ------------------------------------------------------- EVENT_TYPE field of the EVENT_13 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_13 register. + * + * \return the description of the EVENT_TYPE field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- WRAP field of the EVENT_13 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_13_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_13_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_13 register. + * + * \return the description of the WRAP field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the WRAP field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_WRAP(reg, data); +} + + +/* -------------------------------------------------------- CNT_DOWN field of the EVENT_13 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_13 register. + * + * \return the description of the CNT_DOWN field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_13 register ------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_13 register. + * + * \return the description of the INT_DISABLE field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_INT_DISABLE(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_EN field of the EVENT_13 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_13 register. + * + * \return the description of the START_EVENT_EN field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_13 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_13 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_13 register ----------------------------------------------------- */ + +/** Description of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_13 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_SEL(reg, data); +} + + +/* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_13 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_13 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_13 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_13 register. */ +#define ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_13 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_13 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_13 register. + * + * \param[in] reg is the value of the EVENT_13 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_13 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_SEL(reg, data); +} + + +/* *************************************************** EVENT_14 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_14 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_14_OFFSET 0x78UL + +/** Reset value of the EVENT_14 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_14_DT \ + (ATON_DEBUG_TRACE_EVENT_14_EN_DT << ATON_DEBUG_TRACE_EVENT_14_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_SEL_DT << ATON_DEBUG_TRACE_EVENT_14_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_WRAP_DT << ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_DESC "Observer register 15" + +/** Address of the EVENT_14 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_14_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_14_OFFSET) + +/** Get the content of the EVENT_14 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_ADDR(UNIT))) + +/** Set the content of the EVENT_14 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_14 register. + * + * \return the description of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_DESC; +} + + +/** + * Get the offset of the EVENT_14 register. + * + * \return the offset of EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_14_OFFSET; +} + + +/** + * Get the address of the EVENT_14 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_14 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_14_ADDR(instance); +} + + +/** + * Read the content of the EVENT_14 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_14 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET(instance); +} + + +/** + * Write the content of the EVENT_14 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_14_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_14_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN field of the EVENT_14 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_S 0 + +/** Check whether access to the EN field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_EN_P 0 + +/** Read the content of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_EN_W) + +/** Modify the content of the EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_14 register. + * + * \return the description of the EN field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the EN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_14 register ----------------------------------------------------------- */ + +/** Description of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_SEL_W) + +/** Modify the content of the SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_14 register. + * + * \return the description of the SEL field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the SEL field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_SEL(reg, data); +} + + +/* ------------------------------------------------------- EVENT_TYPE field of the EVENT_14 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_14 register. + * + * \return the description of the EVENT_TYPE field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- WRAP field of the EVENT_14 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_14_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_14_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_14 register. + * + * \return the description of the WRAP field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the WRAP field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_WRAP(reg, data); +} + + +/* -------------------------------------------------------- CNT_DOWN field of the EVENT_14 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_14 register. + * + * \return the description of the CNT_DOWN field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_14 register ------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_14 register. + * + * \return the description of the INT_DISABLE field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_INT_DISABLE(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_EN field of the EVENT_14 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_14 register. + * + * \return the description of the START_EVENT_EN field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_14 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_14 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_14 register ----------------------------------------------------- */ + +/** Description of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_14 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_SEL(reg, data); +} + + +/* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_14 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_14 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_14 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_14 register. */ +#define ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_14 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_14 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_14 register. + * + * \param[in] reg is the value of the EVENT_14 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_14 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_SEL(reg, data); +} + + +/* *************************************************** EVENT_15 register of one of the DEBUG_TRACE Units **************************************************** */ + +/** Offset of the EVENT_15 register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_15_OFFSET 0x7cUL + +/** Reset value of the EVENT_15 register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_15_DT \ + (ATON_DEBUG_TRACE_EVENT_15_EN_DT << ATON_DEBUG_TRACE_EVENT_15_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_SEL_DT << ATON_DEBUG_TRACE_EVENT_15_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_WRAP_DT << ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB) | \ + (ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB) + + + +/** Description of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_DESC "Observer register 16" + +/** Address of the EVENT_15 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_15_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_15_OFFSET) + +/** Get the content of the EVENT_15 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_ADDR(UNIT))) + +/** Set the content of the EVENT_15 register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_15 register. + * + * \return the description of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_DESC; +} + + +/** + * Get the offset of the EVENT_15 register. + * + * \return the offset of EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_15_OFFSET; +} + + +/** + * Get the address of the EVENT_15 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15 register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_15 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_15_ADDR(instance); +} + + +/** + * Read the content of the EVENT_15 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15 register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_15 register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET(instance); +} + + +/** + * Write the content of the EVENT_15 register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15 register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_15_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_15_SET(instance, data); +} + + +/* ----------------------------------------------------------- EN field of the EVENT_15 register ------------------------------------------------------------ */ + +/** Description of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_DESC "Enable observer" + +/** Offset of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_LSB 0UL + +/** Size in bits of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_W (1UL) + +/** Mask for retrieving the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_MASK ATON_FIELD_MASK(0UL, 1UL) + +/** Reset value of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_DT 0x0UL + +/** Access rights of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_AC "RW" + +/** Check whether access to the EN field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_S 0 + +/** Check whether access to the EN field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_EN_P 0 + +/** Read the content of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_EN_W) + +/** Modify the content of the EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_EN_W, DATA) + + +/** + * Get the description of the EN field of EVENT_15 register. + * + * \return the description of the EN field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_EN_DESC; +} + + +/** + * Read the content of the EN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the EN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_EN(reg); +} + + +/** + * Write the content of the EN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the EN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_EN(reg, data); +} + + +/* ----------------------------------------------------------- SEL field of the EVENT_15 register ----------------------------------------------------------- */ + +/** Description of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_DESC "Select signal to be monitored" + +/** Offset of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_LSB 1UL + +/** Size in bits of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_W (13UL) + +/** Mask for retrieving the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) + +/** Reset value of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_DT 0x0UL + +/** Access rights of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_AC "RW" + +/** Check whether access to the SEL field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_S 0 + +/** Check whether access to the SEL field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_SEL_P 0 + +/** Read the content of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_SEL_W) + +/** Modify the content of the SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_SEL_W, DATA) + + +/** + * Get the description of the SEL field of EVENT_15 register. + * + * \return the description of the SEL field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_SEL_DESC; +} + + +/** + * Read the content of the SEL field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the SEL field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_SEL(reg); +} + + +/** + * Write the content of the SEL field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 13-bit value that must be written to the field + * + * \return the new content of the SEL field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_SEL(reg, data); +} + + +/* ------------------------------------------------------- EVENT_TYPE field of the EVENT_15 register -------------------------------------------------------- */ + +/** Description of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" + +/** Offset of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB 14UL + +/** Size in bits of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_W (2UL) + +/** Mask for retrieving the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) + +/** Reset value of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DT 0x0UL + +/** Access rights of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_AC "RW" + +/** Check whether access to the EVENT_TYPE field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_S 0 + +/** Check whether access to the EVENT_TYPE field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_P 0 + +/** Read the content of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_W) + +/** Modify the content of the EVENT_TYPE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_W, DATA) + + +/** + * Get the description of the EVENT_TYPE field of EVENT_15 register. + * + * \return the description of the EVENT_TYPE field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DESC; +} + + +/** + * Read the content of the EVENT_TYPE field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the EVENT_TYPE field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_EVENT_TYPE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_EVENT_TYPE(reg); +} + + +/** + * Write the content of the EVENT_TYPE field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 2-bit value that must be written to the field + * + * \return the new content of the EVENT_TYPE field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_EVENT_TYPE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_EVENT_TYPE(reg, data); +} + + +/* ---------------------------------------------------------- WRAP field of the EVENT_15 register ----------------------------------------------------------- */ + +/** Description of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" + +/** Offset of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB 16UL + +/** Size in bits of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_W (1UL) + +/** Mask for retrieving the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) + +/** Reset value of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_DT 0x0UL + +/** Access rights of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_AC "RW" + +/** Check whether access to the WRAP field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_S 0 + +/** Check whether access to the WRAP field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_WRAP_P 0 + +/** Read the content of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_15_WRAP_W) + +/** Modify the content of the WRAP field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_15_WRAP_W, DATA) + + +/** + * Get the description of the WRAP field of EVENT_15 register. + * + * \return the description of the WRAP field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_WRAP_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_WRAP_DESC; +} + + +/** + * Read the content of the WRAP field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the WRAP field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_WRAP(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_WRAP(reg); +} + + +/** + * Write the content of the WRAP field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the WRAP field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_WRAP(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_WRAP(reg, data); +} + + +/* -------------------------------------------------------- CNT_DOWN field of the EVENT_15 register --------------------------------------------------------- */ + +/** Description of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" + +/** Offset of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB 17UL + +/** Size in bits of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_W (1UL) + +/** Mask for retrieving the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) + +/** Reset value of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DT 0x0UL + +/** Access rights of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_AC "RW" + +/** Check whether access to the CNT_DOWN field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_S 0 + +/** Check whether access to the CNT_DOWN field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_P 0 + +/** Read the content of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_W) + +/** Modify the content of the CNT_DOWN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_W, DATA) + + +/** + * Get the description of the CNT_DOWN field of EVENT_15 register. + * + * \return the description of the CNT_DOWN field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DESC; +} + + +/** + * Read the content of the CNT_DOWN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the CNT_DOWN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_CNT_DOWN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_CNT_DOWN(reg); +} + + +/** + * Write the content of the CNT_DOWN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the CNT_DOWN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_CNT_DOWN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_CNT_DOWN(reg, data); +} + + +/* ------------------------------------------------------- INT_DISABLE field of the EVENT_15 register ------------------------------------------------------- */ + +/** Description of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DESC "Mask interrupt for the related observer" + +/** Offset of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB 18UL + +/** Size in bits of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_W (1UL) + +/** Mask for retrieving the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) + +/** Reset value of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DT 0x0UL + +/** Access rights of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_AC "RW" + +/** Check whether access to the INT_DISABLE field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_S 0 + +/** Check whether access to the INT_DISABLE field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_P 0 + +/** Read the content of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_W) + +/** Modify the content of the INT_DISABLE field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_W, DATA) + + +/** + * Get the description of the INT_DISABLE field of EVENT_15 register. + * + * \return the description of the INT_DISABLE field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DESC; +} + + +/** + * Read the content of the INT_DISABLE field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the INT_DISABLE field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_INT_DISABLE(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_INT_DISABLE(reg); +} + + +/** + * Write the content of the INT_DISABLE field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the INT_DISABLE field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_INT_DISABLE(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_INT_DISABLE(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_EN field of the EVENT_15 register ------------------------------------------------------ */ + +/** Description of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" + +/** Offset of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB 19UL + +/** Size in bits of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_W (1UL) + +/** Mask for retrieving the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) + +/** Reset value of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DT 0x0UL + +/** Access rights of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_AC "RW" + +/** Check whether access to the START_EVENT_EN field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_S 0 + +/** Check whether access to the START_EVENT_EN field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_P 0 + +/** Read the content of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_W) + +/** Modify the content of the START_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_W, DATA) + + +/** + * Get the description of the START_EVENT_EN field of EVENT_15 register. + * + * \return the description of the START_EVENT_EN field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DESC; +} + + +/** + * Read the content of the START_EVENT_EN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the START_EVENT_EN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_START_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_EN(reg); +} + + +/** + * Write the content of the START_EVENT_EN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the START_EVENT_EN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_START_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_EN(reg, data); +} + + +/* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_15 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" + +/** Offset of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB 20UL + +/** Size in bits of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_W (1UL) + +/** Mask for retrieving the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) + +/** Reset value of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DT 0x0UL + +/** Access rights of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_AC "RW" + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_S 0 + +/** Check whether access to the STOP_EVENT_EN field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_P 0 + +/** Read the content of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_W) + +/** Modify the content of the STOP_EVENT_EN field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_W, DATA) + + +/** + * Get the description of the STOP_EVENT_EN field of EVENT_15 register. + * + * \return the description of the STOP_EVENT_EN field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DESC; +} + + +/** + * Read the content of the STOP_EVENT_EN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the STOP_EVENT_EN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_STOP_EVENT_EN(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_EN(reg); +} + + +/** + * Write the content of the STOP_EVENT_EN field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 1-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_EN field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_EN(reg, data); +} + + +/* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_15 register ----------------------------------------------------- */ + +/** Description of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" + +/** Offset of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB 21UL + +/** Size in bits of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_W (4UL) + +/** Mask for retrieving the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) + +/** Reset value of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DT 0x0UL + +/** Access rights of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_AC "RW" + +/** Check whether access to the START_EVENT_SEL field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_S 0 + +/** Check whether access to the START_EVENT_SEL field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_P 0 + +/** Read the content of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_W) + +/** Modify the content of the START_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_W, DATA) + + +/** + * Get the description of the START_EVENT_SEL field of EVENT_15 register. + * + * \return the description of the START_EVENT_SEL field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DESC; +} + + +/** + * Read the content of the START_EVENT_SEL field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the START_EVENT_SEL field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_START_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_SEL(reg); +} + + +/** + * Write the content of the START_EVENT_SEL field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the START_EVENT_SEL field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_SEL(reg, data); +} + + +/* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_15 register ------------------------------------------------------ */ + +/** Description of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" + +/** Offset of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB 25UL + +/** Size in bits of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_W (4UL) + +/** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) + +/** Reset value of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DT 0x0UL + +/** Access rights of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_AC "RW" + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_15 register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_S 0 + +/** Check whether access to the STOP_EVENT_SEL field of the EVENT_15 register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_P 0 + +/** Read the content of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_W) + +/** Modify the content of the STOP_EVENT_SEL field of the EVENT_15 register. */ +#define ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_W, DATA) + + +/** + * Get the description of the STOP_EVENT_SEL field of EVENT_15 register. + * + * \return the description of the STOP_EVENT_SEL field of EVENT_15 register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DESC; +} + + +/** + * Read the content of the STOP_EVENT_SEL field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * + * \return the content of the STOP_EVENT_SEL field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_STOP_EVENT_SEL(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_SEL(reg); +} + + +/** + * Write the content of the STOP_EVENT_SEL field of the EVENT_15 register. + * + * \param[in] reg is the value of the EVENT_15 register + * \param[in] data is 4-bit value that must be written to the field + * + * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_15 register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_SEL(reg, data); +} + + +/* ************************************************** EVENT_0_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_0_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_OFFSET 0x84UL + +/** Reset value of the EVENT_0_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB) + + + +/** Description of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_DESC "Observer counter register 1" + +/** Address of the EVENT_0_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_0_CNT_OFFSET) + +/** Get the content of the EVENT_0_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_0_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_0_CNT register. + * + * \return the description of EVENT_0_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_0_CNT register. + * + * \return the offset of EVENT_0_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_0_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_0_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_0_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_0_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_0_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_0_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_0_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_0_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_0_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_0_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_0_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_0_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_0_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_0_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_0_CNT register. + * + * \return the description of the CNT field of EVENT_0_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_0_CNT register. + * + * \param[in] reg is the value of the EVENT_0_CNT register + * + * \return the content of the CNT field belonging to EVENT_0_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_0_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_0_CNT register. + * + * \param[in] reg is the value of the EVENT_0_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_0_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_0_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_1_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_1_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_OFFSET 0x88UL + +/** Reset value of the EVENT_1_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB) + + + +/** Description of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_DESC "Observer counter register 2" + +/** Address of the EVENT_1_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_1_CNT_OFFSET) + +/** Get the content of the EVENT_1_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_1_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_1_CNT register. + * + * \return the description of EVENT_1_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_1_CNT register. + * + * \return the offset of EVENT_1_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_1_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_1_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_1_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_1_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_1_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_1_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_1_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_1_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_1_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_1_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_1_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_1_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_1_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_1_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_1_CNT register. + * + * \return the description of the CNT field of EVENT_1_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_1_CNT register. + * + * \param[in] reg is the value of the EVENT_1_CNT register + * + * \return the content of the CNT field belonging to EVENT_1_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_1_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_1_CNT register. + * + * \param[in] reg is the value of the EVENT_1_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_1_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_1_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_2_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_2_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_OFFSET 0x8cUL + +/** Reset value of the EVENT_2_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB) + + + +/** Description of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_DESC "Observer counter register 3" + +/** Address of the EVENT_2_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_2_CNT_OFFSET) + +/** Get the content of the EVENT_2_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_2_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_2_CNT register. + * + * \return the description of EVENT_2_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_2_CNT register. + * + * \return the offset of EVENT_2_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_2_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_2_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_2_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_2_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_2_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_2_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_2_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_2_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_2_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_2_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_2_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_2_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_2_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_2_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_2_CNT register. + * + * \return the description of the CNT field of EVENT_2_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_2_CNT register. + * + * \param[in] reg is the value of the EVENT_2_CNT register + * + * \return the content of the CNT field belonging to EVENT_2_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_2_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_2_CNT register. + * + * \param[in] reg is the value of the EVENT_2_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_2_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_2_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_3_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_3_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_OFFSET 0x90UL + +/** Reset value of the EVENT_3_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB) + + + +/** Description of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_DESC "Observer counter register 4" + +/** Address of the EVENT_3_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_3_CNT_OFFSET) + +/** Get the content of the EVENT_3_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_3_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_3_CNT register. + * + * \return the description of EVENT_3_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_3_CNT register. + * + * \return the offset of EVENT_3_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_3_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_3_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_3_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_3_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_3_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_3_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_3_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_3_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_3_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_3_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_3_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_3_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_3_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_3_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_3_CNT register. + * + * \return the description of the CNT field of EVENT_3_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_3_CNT register. + * + * \param[in] reg is the value of the EVENT_3_CNT register + * + * \return the content of the CNT field belonging to EVENT_3_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_3_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_3_CNT register. + * + * \param[in] reg is the value of the EVENT_3_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_3_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_3_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_4_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_4_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_OFFSET 0x94UL + +/** Reset value of the EVENT_4_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB) + + + +/** Description of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_DESC "Observer counter register 5" + +/** Address of the EVENT_4_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_4_CNT_OFFSET) + +/** Get the content of the EVENT_4_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_4_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_4_CNT register. + * + * \return the description of EVENT_4_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_4_CNT register. + * + * \return the offset of EVENT_4_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_4_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_4_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_4_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_4_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_4_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_4_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_4_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_4_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_4_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_4_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_4_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_4_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_4_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_4_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_4_CNT register. + * + * \return the description of the CNT field of EVENT_4_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_4_CNT register. + * + * \param[in] reg is the value of the EVENT_4_CNT register + * + * \return the content of the CNT field belonging to EVENT_4_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_4_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_4_CNT register. + * + * \param[in] reg is the value of the EVENT_4_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_4_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_4_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_5_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_5_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_OFFSET 0x98UL + +/** Reset value of the EVENT_5_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB) + + + +/** Description of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_DESC "Observer counter register 6" + +/** Address of the EVENT_5_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_5_CNT_OFFSET) + +/** Get the content of the EVENT_5_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_5_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_5_CNT register. + * + * \return the description of EVENT_5_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_5_CNT register. + * + * \return the offset of EVENT_5_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_5_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_5_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_5_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_5_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_5_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_5_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_5_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_5_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_5_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_5_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_5_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_5_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_5_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_5_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_5_CNT register. + * + * \return the description of the CNT field of EVENT_5_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_5_CNT register. + * + * \param[in] reg is the value of the EVENT_5_CNT register + * + * \return the content of the CNT field belonging to EVENT_5_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_5_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_5_CNT register. + * + * \param[in] reg is the value of the EVENT_5_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_5_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_5_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_6_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_6_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_OFFSET 0x9cUL + +/** Reset value of the EVENT_6_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB) + + + +/** Description of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_DESC "Observer counter register 7" + +/** Address of the EVENT_6_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_6_CNT_OFFSET) + +/** Get the content of the EVENT_6_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_6_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_6_CNT register. + * + * \return the description of EVENT_6_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_6_CNT register. + * + * \return the offset of EVENT_6_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_6_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_6_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_6_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_6_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_6_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_6_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_6_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_6_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_6_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_6_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_6_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_6_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_6_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_6_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_6_CNT register. + * + * \return the description of the CNT field of EVENT_6_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_6_CNT register. + * + * \param[in] reg is the value of the EVENT_6_CNT register + * + * \return the content of the CNT field belonging to EVENT_6_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_6_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_6_CNT register. + * + * \param[in] reg is the value of the EVENT_6_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_6_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_6_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_7_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_7_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_OFFSET 0xa0UL + +/** Reset value of the EVENT_7_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB) + + + +/** Description of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_DESC "Observer counter register 8" + +/** Address of the EVENT_7_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_7_CNT_OFFSET) + +/** Get the content of the EVENT_7_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_7_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_7_CNT register. + * + * \return the description of EVENT_7_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_7_CNT register. + * + * \return the offset of EVENT_7_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_7_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_7_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_7_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_7_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_7_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_7_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_7_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_7_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_7_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_7_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_7_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_7_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_7_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_7_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_7_CNT register. + * + * \return the description of the CNT field of EVENT_7_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_7_CNT register. + * + * \param[in] reg is the value of the EVENT_7_CNT register + * + * \return the content of the CNT field belonging to EVENT_7_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_7_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_7_CNT register. + * + * \param[in] reg is the value of the EVENT_7_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_7_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_7_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_8_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_8_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_OFFSET 0xa4UL + +/** Reset value of the EVENT_8_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB) + + + +/** Description of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_DESC "Observer counter register 9" + +/** Address of the EVENT_8_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_8_CNT_OFFSET) + +/** Get the content of the EVENT_8_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_8_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_8_CNT register. + * + * \return the description of EVENT_8_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_8_CNT register. + * + * \return the offset of EVENT_8_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_8_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_8_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_8_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_8_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_8_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_8_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_8_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_8_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_8_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_8_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_8_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_8_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_8_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_8_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_8_CNT register. + * + * \return the description of the CNT field of EVENT_8_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_8_CNT register. + * + * \param[in] reg is the value of the EVENT_8_CNT register + * + * \return the content of the CNT field belonging to EVENT_8_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_8_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_8_CNT register. + * + * \param[in] reg is the value of the EVENT_8_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_8_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_8_CNT_SET_CNT(reg, data); +} + + +/* ************************************************** EVENT_9_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_9_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_OFFSET 0xa8UL + +/** Reset value of the EVENT_9_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB) + + + +/** Description of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_DESC "Observer counter register 10" + +/** Address of the EVENT_9_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_9_CNT_OFFSET) + +/** Get the content of the EVENT_9_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_9_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_9_CNT register. + * + * \return the description of EVENT_9_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_9_CNT register. + * + * \return the offset of EVENT_9_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_9_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_9_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_9_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_9_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_9_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_9_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_9_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_9_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_9_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_9_CNT register ---------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_9_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_9_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_9_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_9_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_9_CNT register. + * + * \return the description of the CNT field of EVENT_9_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_9_CNT register. + * + * \param[in] reg is the value of the EVENT_9_CNT register + * + * \return the content of the CNT field belonging to EVENT_9_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_9_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_9_CNT register. + * + * \param[in] reg is the value of the EVENT_9_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_9_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_9_CNT_SET_CNT(reg, data); +} + + +/* ************************************************* EVENT_10_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_10_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_OFFSET 0xacUL + +/** Reset value of the EVENT_10_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB) + + + +/** Description of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_DESC "Observer counter register 11" + +/** Address of the EVENT_10_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_10_CNT_OFFSET) + +/** Get the content of the EVENT_10_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_10_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_10_CNT register. + * + * \return the description of EVENT_10_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_10_CNT register. + * + * \return the offset of EVENT_10_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_10_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_10_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_10_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_10_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_10_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_10_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_10_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_10_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_10_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_10_CNT register --------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_10_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_10_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_10_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_10_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_10_CNT register. + * + * \return the description of the CNT field of EVENT_10_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_10_CNT register. + * + * \param[in] reg is the value of the EVENT_10_CNT register + * + * \return the content of the CNT field belonging to EVENT_10_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_10_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_10_CNT register. + * + * \param[in] reg is the value of the EVENT_10_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_10_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_10_CNT_SET_CNT(reg, data); +} + + +/* ************************************************* EVENT_11_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_11_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_OFFSET 0xb0UL + +/** Reset value of the EVENT_11_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB) + + + +/** Description of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_DESC "Observer counter register 12" + +/** Address of the EVENT_11_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_11_CNT_OFFSET) + +/** Get the content of the EVENT_11_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_11_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_11_CNT register. + * + * \return the description of EVENT_11_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_11_CNT register. + * + * \return the offset of EVENT_11_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_11_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_11_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_11_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_11_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_11_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_11_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_11_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_11_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_11_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_11_CNT register --------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_11_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_11_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_11_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_11_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_11_CNT register. + * + * \return the description of the CNT field of EVENT_11_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_11_CNT register. + * + * \param[in] reg is the value of the EVENT_11_CNT register + * + * \return the content of the CNT field belonging to EVENT_11_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_11_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_11_CNT register. + * + * \param[in] reg is the value of the EVENT_11_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_11_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_11_CNT_SET_CNT(reg, data); +} + + +/* ************************************************* EVENT_12_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_12_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_OFFSET 0xb4UL + +/** Reset value of the EVENT_12_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB) + + + +/** Description of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_DESC "Observer counter register 13" + +/** Address of the EVENT_12_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_12_CNT_OFFSET) + +/** Get the content of the EVENT_12_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_12_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_12_CNT register. + * + * \return the description of EVENT_12_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_12_CNT register. + * + * \return the offset of EVENT_12_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_12_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_12_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_12_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_12_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_12_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_12_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_12_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_12_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_12_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_12_CNT register --------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_12_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_12_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_12_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_12_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_12_CNT register. + * + * \return the description of the CNT field of EVENT_12_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_12_CNT register. + * + * \param[in] reg is the value of the EVENT_12_CNT register + * + * \return the content of the CNT field belonging to EVENT_12_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_12_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_12_CNT register. + * + * \param[in] reg is the value of the EVENT_12_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_12_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_12_CNT_SET_CNT(reg, data); +} + + +/* ************************************************* EVENT_13_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_13_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_OFFSET 0xb8UL + +/** Reset value of the EVENT_13_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB) + + + +/** Description of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_DESC "Observer counter register 14" + +/** Address of the EVENT_13_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_13_CNT_OFFSET) + +/** Get the content of the EVENT_13_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_13_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_13_CNT register. + * + * \return the description of EVENT_13_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_13_CNT register. + * + * \return the offset of EVENT_13_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_13_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_13_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_13_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_13_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_13_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_13_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_13_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_13_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_13_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_13_CNT register --------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_13_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_13_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_13_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_13_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_13_CNT register. + * + * \return the description of the CNT field of EVENT_13_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_13_CNT register. + * + * \param[in] reg is the value of the EVENT_13_CNT register + * + * \return the content of the CNT field belonging to EVENT_13_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_13_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_13_CNT register. + * + * \param[in] reg is the value of the EVENT_13_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_13_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_13_CNT_SET_CNT(reg, data); +} + + +/* ************************************************* EVENT_14_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_14_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_OFFSET 0xbcUL + +/** Reset value of the EVENT_14_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB) + + + +/** Description of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_DESC "Observer counter register 15" + +/** Address of the EVENT_14_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_14_CNT_OFFSET) + +/** Get the content of the EVENT_14_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_14_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_14_CNT register. + * + * \return the description of EVENT_14_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_14_CNT register. + * + * \return the offset of EVENT_14_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_14_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_14_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_14_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_14_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_14_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_14_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_14_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_14_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_14_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_14_CNT register --------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_14_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_14_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_14_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_14_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_14_CNT register. + * + * \return the description of the CNT field of EVENT_14_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_14_CNT register. + * + * \param[in] reg is the value of the EVENT_14_CNT register + * + * \return the content of the CNT field belonging to EVENT_14_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_14_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_14_CNT register. + * + * \param[in] reg is the value of the EVENT_14_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_14_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_14_CNT_SET_CNT(reg, data); +} + + +/* ************************************************* EVENT_15_CNT register of one of the DEBUG_TRACE Units ************************************************** */ + +/** Offset of the EVENT_15_CNT register from the base address of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_OFFSET 0xc0UL + +/** Reset value of the EVENT_15_CNT register of the DEBUG_TRACE Unit. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DT \ + (ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB) + + + +/** Description of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_DESC "Observer counter register 16" + +/** Address of the EVENT_15_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_15_CNT_OFFSET) + +/** Get the content of the EVENT_15_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(UNIT))) + +/** Set the content of the EVENT_15_CNT register of one of the DEBUG_TRACE Units. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(UNIT)) = (DATA); } while (0); + + +/** + * Get the description of EVENT_15_CNT register. + * + * \return the description of EVENT_15_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_CNT_GetDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_CNT_DESC; +} + + +/** + * Get the offset of the EVENT_15_CNT register. + * + * \return the offset of EVENT_15_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_GetOffset(void) +{ + return ATON_DEBUG_TRACE_EVENT_15_CNT_OFFSET; +} + + +/** + * Get the address of the EVENT_15_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15_CNT register whose address must be returned + * (it must be instance \< 1<\em>) + * + * \return the address of EVENT_15_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_GetAddr(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(instance); +} + + +/** + * Read the content of the EVENT_15_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15_CNT register whose content must be retrieved + * (it must be instance \< 1<\em>) + * + * \return the content of EVENT_15_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_Get(uint32_t instance) +{ + return ATON_DEBUG_TRACE_EVENT_15_CNT_GET(instance); +} + + +/** + * Write the content of the EVENT_15_CNT register. + * + * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15_CNT register whose content must be modified + * (it must be instance \< 1<\em>) + * \param[in] data is 32-bit value that must be written to the register + */ + +static inline void ATON_DEBUG_TRACE_EVENT_15_CNT_Set(uint32_t instance, uint32_t data) +{ + ATON_DEBUG_TRACE_EVENT_15_CNT_SET(instance, data); +} + + +/* --------------------------------------------------------- CNT field of the EVENT_15_CNT register --------------------------------------------------------- */ + +/** Description of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DESC "Event counter" + +/** Offset of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB 0UL + +/** Size in bits of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_W (32UL) + +/** Mask for retrieving the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) + +/** Reset value of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DT 0x0UL + +/** Access rights of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_AC "RW" + +/** Check whether access to the CNT field of the EVENT_15_CNT register is secured or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_S 0 + +/** Check whether access to the CNT field of the EVENT_15_CNT register is privileged or not. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_P 0 + +/** Read the content of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_W) + +/** Modify the content of the CNT field of the EVENT_15_CNT register. */ +#define ATON_DEBUG_TRACE_EVENT_15_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_W, DATA) + + +/** + * Get the description of the CNT field of EVENT_15_CNT register. + * + * \return the description of the CNT field of EVENT_15_CNT register + */ + +static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_GetdDesc(void) +{ + return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DESC; +} + + +/** + * Read the content of the CNT field of the EVENT_15_CNT register. + * + * \param[in] reg is the value of the EVENT_15_CNT register + * + * \return the content of the CNT field belonging to EVENT_15_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_Get_CNT(uint32_t reg) +{ + return ATON_DEBUG_TRACE_EVENT_15_CNT_GET_CNT(reg); +} + + +/** + * Write the content of the CNT field of the EVENT_15_CNT register. + * + * \param[in] reg is the value of the EVENT_15_CNT register + * \param[in] data is 32-bit value that must be written to the field + * + * \return the new content of the CNT field belonging to EVENT_15_CNT register + */ + +static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_Set_CNT(uint32_t reg, uint32_t data) +{ + return ATON_DEBUG_TRACE_EVENT_15_CNT_SET_CNT(reg, data); +} + + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif // #ifndef ATON_H diff --git a/lib/stai/libstai/include/ai_common_config.h b/lib/stai/libstai/include/ai_common_config.h new file mode 100644 index 000000000..f809d5be2 --- /dev/null +++ b/lib/stai/libstai/include/ai_common_config.h @@ -0,0 +1,31 @@ +/** + ****************************************************************************** + * @file ai_common_config.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform common compile configuration defines + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_COMMON_CONFIG_H +#define AI_COMMON_CONFIG_H + +/*! + * @defgroup layers Layers Compilation Config Definitions + * @brief definition + * + */ + +#define HAS_PROFILE_FLOAT +#define HAS_PROFILE_FIXED + + +#endif /*AI_COMMON_CONFIG_H*/ diff --git a/lib/stai/libstai/include/ai_datatypes.h b/lib/stai/libstai/include/ai_datatypes.h new file mode 100644 index 000000000..42104186f --- /dev/null +++ b/lib/stai/libstai/include/ai_datatypes.h @@ -0,0 +1,71 @@ + +#ifndef AI_DATATYPES_H +#define AI_DATATYPES_H +/** + ****************************************************************************** + * @file ai_datatypes.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include +#include "ai_platform.h" +#include "ai_platform_interface.h" + +/*! + * @defgroup datatypes Platform Interface Datatypes + * @brief Data structures used by AI platform to implement neural networks + * + */ + +/** Count Variable Number of Arguments (up to 64 elements) *******************/ +#define AI_NUMARGS(...) \ + PP_NARG_(__VA_ARGS__,PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N +#define PP_RSEQ_N() \ + 63,62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 + + +/*****************************************************************************/ +#define AI_PTR_ALIGN(ptr, alignment) \ + ((((ai_uptr)(ptr))+((ai_uptr)(alignment)-1))&(~((ai_uptr)(alignment)-1))) + + +/*! + * @typedef ai_offset + * @ingroup ai_datatypes_internal + * @brief Generic index offset type + */ +typedef int32_t ai_offset; + + +AI_API_DECLARE_BEGIN + +AI_API_DECLARE_END + +#endif /* AI_DATATYPES_H */ diff --git a/lib/stai/libstai/include/ai_datatypes_defines.h b/lib/stai/libstai/include/ai_datatypes_defines.h new file mode 100644 index 000000000..96962b4d3 --- /dev/null +++ b/lib/stai/libstai/include/ai_datatypes_defines.h @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file ai_datatypes_defines.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_DATATYPES_DEFINES_H +#define AI_DATATYPES_DEFINES_H + +#include "ai_platform.h" +#include "core_assert.h" + + +/*! + * @defgroup datatypes_defines Internal Datatypes Defines Header + * @brief Data structures used internally to implement neural networks + * + */ + +/* define to track datatypes used by codegen */ +#define AI_INTERNAL_API /* AI_INTERNAL_API */ + +#define AI_CONST const +#define AI_STATIC static +#define AI_STATIC_CONST static const + +/******************************************************************************/ +/* NOP operation used by codegen */ +#define AI_NOP /* NOP */ + +#define AI_WRAP_FUNC(fn_) do { fn_ } while (0); + +#define AI_CAT(a, ...) AI_PRIMITIVE_CAT(a, __VA_ARGS__) +#define AI_PRIMITIVE_CAT(a, ...) a ## __VA_ARGS__ + +/******************************************************************************/ +#define AI_ASSERT(expr) \ + CORE_ASSERT(expr) + + +/******************************************************************************/ +#define AI_NO_PACKED_STRUCTS + +/* Macro for defining packed structures (compiler dependent). + * This just reduces memory requirements, but is not required. + */ +#if defined(AI_NO_PACKED_STRUCTS) + /* Disable struct packing */ + #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ + #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ + #define AI_PACKED /* AI_PACKED */ +#elif defined(__GNUC__) || defined(__clang__) + /* For GCC and clang */ + #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ + #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ + #define AI_PACKED __attribute__((packed)) +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) || defined(__CC_ARM) + /* For IAR ARM and Keil MDK-ARM compilers */ + #define AI_PACKED_STRUCT_START _Pragma("pack(push, 1)") + #define AI_PACKED_STRUCT_END _Pragma("pack(pop)") + #define AI_PACKED /* AI_PACKED */ +#elif defined(_MSC_VER) && (_MSC_VER >= 1500) + /* For Microsoft Visual C++ */ + #define AI_PACKED_STRUCT_START __pragma(pack(push, 1)) + #define AI_PACKED_STRUCT_END __pragma(pack(pop)) + #define AI_PACKED /* AI_PACKED */ +#else + /* Unknown compiler */ + #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ + #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ + #define AI_PACKED /* AI_PACKED */ +#endif /* AI_NO_PACKED_STRUCTS */ + +/******************************************************************************/ +#define AI_STRINGIFY_ARG(contents) # contents +#define AI_STRINGIFY(macro_or_string) AI_STRINGIFY_ARG (macro_or_string) + +/******************************************************************************/ +#if defined(_MSC_VER) + #define AI_DECLARE_STATIC static __inline + // #define AI_FORCE_INLINE static __forceinline + #define AI_FORCE_INLINE static __inline + #define AI_HINT_INLINE static __inline + #define AI_ALIGNED_TYPE(type, x) type __declspec(align(x)) + #define AI_INTERFACE_ENTRY __declspec(dllexport) +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define AI_DECLARE_STATIC static inline + // #define AI_FORCE_INLINE static _Pragma("inline=forced") // TODO: check this definition! + #define AI_FORCE_INLINE static inline + #define AI_HINT_INLINE static inline + #define AI_ALIGNED_TYPE(type, x) type + #define AI_INTERFACE_ENTRY /* AI_INTERFACE_ENTRY */ +#elif defined(__GNUC__) + #define AI_DECLARE_STATIC static __inline + #define AI_FORCE_INLINE static __inline + #define AI_HINT_INLINE static __inline + #define AI_ALIGNED_TYPE(type, x) type __attribute__ ((aligned(x))) + #define AI_INTERFACE_ENTRY /* AI_INTERFACE_ENTRY */ +#else /* _MSC_VER */ + #define AI_DECLARE_STATIC static __inline + // #define AI_FORCE_INLINE static __forceinline + #define AI_FORCE_INLINE static __inline + #define AI_HINT_INLINE static __inline + #define AI_ALIGNED_TYPE(type, x) type __attribute__ ((aligned(x))) + #define AI_INTERFACE_ENTRY __attribute__((visibility("default"))) +#endif /* _MSC_VER */ + +/******************************************************************************/ +#define AI_ALIGN_MASKED(value, mask) ( ((value)+(mask))&(~(mask)) ) + +#define AI_GET_VERSION_STRING(major, minor, micro) \ + AI_STRINGIFY_ARG(major) "." \ + AI_STRINGIFY_ARG(minor) "." \ + AI_STRINGIFY_ARG(micro) \ + + +#define AI_PACK_TENSORS_PTR(...) \ + AI_PACK(__VA_ARGS__) + +#define AI_PACK_INFO(size_) (ai_tensor_info[1]) { { \ + .buffer = (ai_buffer[size_])AI_STRUCT_INIT, \ + .state = (ai_tensor_state[size_])AI_STRUCT_INIT, \ +} } + +#define AI_CR "\r\n" + +#if (defined HAS_AI_DEBUG || defined HAS_DEBUG_LIB) +#include +#define AI_DEBUG(...) __VA_ARGS__ +#define AI_DEBUG_PRINT(fmt, ...) { printf(fmt, ##__VA_ARGS__); } +#else +#define AI_DEBUG(...) AI_WRAP_FUNC(/*AI_DEBUG*/) +#define AI_DEBUG_PRINT(fmt, ...) AI_WRAP_FUNC(/*AI_DEBUG_PRINT*/) +#endif + +#define AI_FLAG_SET(mask, flag) (mask) |= (flag) +#define AI_FLAG_UNSET(mask, flag) (mask) &= (~(flag)) +#define AI_FLAG_IS_SET(mask, flag) ((flag)==((mask)&(flag))) + +#endif /*AI_DATATYPES_DEFINES_H*/ diff --git a/lib/stai/libstai/include/ai_datatypes_format.h b/lib/stai/libstai/include/ai_datatypes_format.h new file mode 100644 index 000000000..86682160e --- /dev/null +++ b/lib/stai/libstai/include/ai_datatypes_format.h @@ -0,0 +1,514 @@ +/** + ****************************************************************************** + * @file ai_datatypes_format.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private format handling routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_DATATYPES_FORMAT_H +#define AI_DATATYPES_FORMAT_H + +#include "ai_platform.h" +#include "ai_datatypes_defines.h" + + +/*! + * @defgroup ai_datatypes_format Definiton and Macro of array and buffer formats + * @brief Type definition and implementation of internal @ref ai_array and + * @ref ai_buffer formats. + * @details The library handles 2 different kind of formats: an internal format + * that is part of the @ref ai_array struct that is a packed 32bit representation + * of the format attributes, and a public format (used in public APIs) associated + * with @ref ai_buffer struct , defined as enum in @ref ai_platform.h, + * that is just an enum type. Converters are provided in this header file to + * convert from one format representation to another. + * Some MSB bits are reserved in both formats to code some bit flag useful to + * declare some special attribute. Three flags are actually implemented in both + * formats: the @ref AI_BUFFER_FMT_FLAG_CONST and @ref AI_FMT_FLAG_CONST used + * to tag read-only memory buffers, @ref AI_BUFFER_FMT_FLAG_STATIC and + * @ref AI_FMT_FLAG_STATIC to mark statically allocated memory buffers and + * @ref AI_FMT_FLAG_SCRATCH_BUFFER to tag temporary scratch buffers. + * All the formats are declared in a proper tuple organize table header named + * @ref format_lists.h that enumerates all the formats available for the library. + * A new format could be added easily by adding a new FMY_ENTRY() as required. + * The preprocessor automatically generates the code for the handling of the + * format according to this tuples entry. A rational for the methodology could + * be found here: + * - https://codecraft.co/2012/10/29/how-enums-spread-disease-and-how-to-cure-it/ + * + * The 32bits internal format fields are organized as follows: + * + * MSB LSB + * 31 25 24 23 21 17 14 7 0 + * /---------------------------------------------------------------------------/ + * / ATTR. FLAGS |COMPLEX | SIGN | LDIV | TYPE | PMASK | BITS | FBITS / + * /---------------------------------------------------------------------------/ + * Where: + * - FLAGS: is the reserved bits to store additional format attributes (e.g. + * I/O / STATIC flags. etc.) + * - COMPLEX: 1 bit mark the format as complex type + * - SIGN : 1 bit mark the format as signed type + * - LDIV : 2 bits is a log2 value that is used to compute elements size + * with some special format such as the compressed ones. It is a shift + * factor usually set to zero + * - TYPE : 4 bits mark the format "family" type. Actually 5 families are coded, + * @ref AI_FMT_FLOAT (float types) + * @ref AI_FMT_Q (fixed-point types in Qm.n format) + * @ref AI_FMT_BOOL (boolean type) + * @ref AI_FMT_LUT_FLOAT (compressed float lookup formats) + * @ref AI_FMT_LUT_Q (compressed Qmn lookup formats) + * - PMASK 3 bits padding mask used to set the optional dimension for padding + * to handle special aligned formats/ E.g. a 1 bit format + * Usually this is set to 0x0 + * - BITS 7 bits set the total number of bits of the element, padding bits + * excluded. The bits are thus = sign bit + fractional bits + integer bits + * The number of integer bits could thus be known using the @ref + * AI_FMT_GET_IBITS() macro. + * - FBITS 7 bits set the number of fractional bits in the format + * + * + * A reference code snippet for usage is the test unit that uses this header: + * + * \include test/test_lcut_formats.cpp + * + */ + +/*! + * Format bitfields definition. NOTE: 7 MSB are masked off + * for (optional) atributes setting using flags. see @ref AI_FMT_FLAG_CONST that + * is used for marking a data as constant readonly + */ + +/* 1 bit field to identify floating point values*/ +#define _FMT_COMPLEX_MASK (0x1) +#define _FMT_COMPLEX_BITS (24) + +/*! 1 bit sign info */ +#define _FMT_SIGN_MASK (0x1) +#define _FMT_SIGN_BITS (23) + +/*! fractional bits field (i.e. for Q formats see @ref AI_FMT_Q) */ +#define _FMT_FBITS_MASK (0x7F) +#define _FMT_FBITS_BITS (0) +#define _FMT_FBITS_BIAS ((_FMT_FBITS_MASK+1) >> 1) + +/*! TOTAL number of bits (fractional+integer+sign) (excluded padding ones) */ +#define _FMT_BITS_MASK (0x7F) +#define _FMT_BITS_BITS (7) +#define _FMT_BITS_BIAS (0) + +/*! Padding bits for handling formats not aligned to multiples of 8 bits */ +#define _FMT_PMASK_MASK (0x7) +#define _FMT_PMASK_BITS (14) + +/*! bits reserved for identifying the family format, e.g. float, fixed-point..*/ +#define _FMT_TYPE_MASK (0xF) +#define _FMT_TYPE_BITS (17) + +#define _FMT_LDIV_MASK (0x3) +#define _FMT_LDIV_BITS (21) + + +/******************************************************************************/ +#define AI_FMT_OBJ(fmt_) ((ai_array_format)(fmt_)) + +/*! + * Only 25 LSB bits are used for storing actual format bits. 7 bits are reserved + * for format attributes, see @ref AI_FMT_FLAG_CONST flag + */ +#define AI_FMT_FLAG_BITS (25) +#define AI_FMT_MASK ((0x1<> AI_FMT_FLAG_BITS ) + +#define AI_FMT_SAME(fmt1_, fmt2_) \ + ( AI_FMT_GET(fmt1_) == AI_FMT_GET(fmt2_) ) + +#define _FMT_SET(val, mask, bits) AI_FMT_OBJ(((val)&(mask))<<(bits)) +#define _FMT_GET(fmt, mask, bits) ((AI_FMT_OBJ(fmt)>>(bits))&(mask)) + +#define AI_FMT_SET_COMPLEX(val) _FMT_SET(val, _FMT_COMPLEX_MASK, _FMT_COMPLEX_BITS) +#define AI_FMT_GET_COMPLEX(fmt) _FMT_GET(fmt, _FMT_COMPLEX_MASK, _FMT_COMPLEX_BITS) +#define AI_FMT_SET_SIGN(val) _FMT_SET(val, _FMT_SIGN_MASK, _FMT_SIGN_BITS) +#define AI_FMT_GET_SIGN(fmt) _FMT_GET(fmt, _FMT_SIGN_MASK, _FMT_SIGN_BITS) +#define AI_FMT_SET_PMASK(val) _FMT_SET(val, _FMT_PMASK_MASK, _FMT_PMASK_BITS) +#define AI_FMT_GET_PMASK(fmt) _FMT_GET(fmt, _FMT_PMASK_MASK, _FMT_PMASK_BITS) +#define AI_FMT_SET_TYPE(val) _FMT_SET(val, _FMT_TYPE_MASK, _FMT_TYPE_BITS) +#define AI_FMT_GET_TYPE(fmt) _FMT_GET(fmt, _FMT_TYPE_MASK, _FMT_TYPE_BITS) +#define AI_FMT_SET_LDIV(val) _FMT_SET(val, _FMT_LDIV_MASK, _FMT_LDIV_BITS) +#define AI_FMT_GET_LDIV(fmt) _FMT_GET(fmt, _FMT_LDIV_MASK, _FMT_LDIV_BITS) + + +#define AI_FMT_SET_BITS(val) \ + _FMT_SET((val) + _FMT_BITS_BIAS, _FMT_BITS_MASK, _FMT_BITS_BITS) +#define AI_FMT_GET_BITS(fmt) \ + ((ai_i8)_FMT_GET(fmt, _FMT_BITS_MASK, _FMT_BITS_BITS) - _FMT_BITS_BIAS) +#define AI_FMT_SET_FBITS(val) \ + _FMT_SET((val) + _FMT_FBITS_BIAS, _FMT_FBITS_MASK, _FMT_FBITS_BITS) +#define AI_FMT_GET_FBITS(fmt) \ + ((ai_i8)_FMT_GET(fmt, _FMT_FBITS_MASK, _FMT_FBITS_BITS) - _FMT_FBITS_BIAS) + +/*! + * The total number of bits for a given format is supposed to be the sum of the + * bits + padding bits. This means that the number of integer bits is derived + * as follow: int_bits = bits - fbits (fractional bits) - 1 (for the sign) + */ +#define AI_FMT_GET_BITS_SIZE(fmt_) \ + AI_FMT_GET_BITS(fmt_) + +/*! Macro used to compute the integer bits for a format */ +#define AI_FMT_GET_IBITS(fmt_) \ + ((ai_i16)AI_FMT_GET_BITS(fmt_)-AI_FMT_GET_FBITS(fmt_)-AI_FMT_GET_SIGN(fmt_)) + +/*! ai_buffer format handlers section *****************************************/ + +#define AI_BUFFER_FMT_MASK_Q(fmt_) \ + ( AI_BUFFER_FMT_OBJ(fmt_) & 0xFFFFC000 ) + +#define AI_BUFFER_FMT_GET_Q(fmt_) \ + ( AI_BUFFER_FMT_MASK_Q(fmt_) | AI_BUFFER_FMT_SET_FBITS(0) | \ + AI_BUFFER_FMT_SET_FBITS(0) ) + +#define AI_BUFFER_FMT_SET_Q(bits_, fbits_) \ + AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, bits_, fbits_) + +#define AI_BUFFER_FMT_IS_Q(fmt_) \ + ( (AI_BUFFER_FMT_TYPE_Q==AI_BUFFER_FMT_GET_TYPE(fmt_)) && \ + (1==AI_BUFFER_FMT_GET_SIGN(fmt_)) ) + +#define AI_BUFFER_FMT_SET_UQ(bits_, fbits_) \ + AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, bits_, fbits_) + +#define AI_BUFFER_FMT_IS_UQ(fmt_) \ + ( (AI_BUFFER_FMT_TYPE_Q==AI_BUFFER_FMT_GET_TYPE(fmt_)) && \ + (0==AI_BUFFER_FMT_GET_SIGN(fmt_)) ) + +/*! Q ai_array format handlers ************************************************/ +#define AI_ARRAY_FMT_Q(bits_, fbits_) \ + ( AI_FMT_MASK_Q(AI_ARRAY_FORMAT_Q) | AI_FMT_SET_BITS(bits_) | AI_FMT_SET_FBITS(fbits_) ) + +#define AI_ARRAY_FMT_SET_Q(bits_, fbits_) \ + AI_ARRAY_FMT_Q(bits_, fbits_) + +#define AI_ARRAY_FMT_IS_Q(fmt_) \ + ( AI_FMT_GET(AI_FMT_MASK_Q(AI_ARRAY_FORMAT_Q))==AI_FMT_GET(AI_FMT_MASK_Q(fmt_)) ) + +#define AI_ARRAY_FMT_UQ(bits_, fbits_) \ + ( AI_FMT_MASK_Q(AI_ARRAY_FORMAT_UQ) | AI_FMT_SET_BITS(bits_) | AI_FMT_SET_FBITS(fbits_) ) + +#define AI_ARRAY_FMT_SET_UQ(bits_, fbits_) \ + AI_ARRAY_FMT_UQ(bits_, fbits_) + +#define AI_ARRAY_FMT_IS_UQ(fmt_) \ + ( AI_FMT_GET(AI_FMT_MASK_Q(AI_ARRAY_FORMAT_UQ))==AI_FMT_GET(AI_FMT_MASK_Q(fmt_)) ) + +AI_DEPRECATED +/* Alias for AI_ARRAY_FMT_SET_Q */ +#define AI_ARRAY_FMT_SET_SQ(bits_, fbits_) \ + AI_ARRAY_FMT_SET_Q(bits_, fbits_) + +AI_DEPRECATED +/* Alias for AI_ARRAY_FMT_IS_Q */ +#define AI_ARRAY_FMT_IS_SQ(fmt_) \ + AI_ARRAY_FMT_IS_Q(fmt_) + +/*! ai_array section **********************************************************/ +#define AI_ARRAY_FMT_ENTRY(name_) \ + AI_CONCAT(AI_ARRAY_FORMAT_, name_) + +#define AI_ARRAY_FMT_NAME(fmt_) \ + ai_array_fmt_name(fmt_) + +#define AI_ARRAY_FMT_VALID(fmt_) \ + ai_array_fmt_valid(fmt_) + +#define AI_ARRAY_FMT_EXPORTED(fmt_) \ + ai_array_fmt_exported(fmt_) + +#define AI_ARRAY_FMT_GET_FORMATS(formats_) \ + ai_array_fmt_get_formats(formats_) + +#define AI_ARRAY_TO_BUFFER_FMT(fmt_) \ + ai_array_to_buffer_fmt(fmt_) + +#define AI_ARRAY_GET_BYTE_SIZE(fmt_, count_) \ + ai_array_get_byte_size(fmt_, count_) + +#define AI_ARRAY_GET_DATA_BYTE_SIZE(fmt_, count_) \ + ai_array_get_data_byte_size(fmt_, count_) + +#define AI_ARRAY_GET_ELEMS_FROM_SIZE(fmt_, size_) \ + ai_array_get_elems_from_size(fmt_, size_) + + +/* Compile sanity checks for formats field consistency */ +#if (AI_FMT_MASK != AI_BUFFER_FMT_MASK) +#error "AI_FMT_MASK != AI_BUFFER_FMT_MASK" +#endif +#if (AI_FMT_NONE != AI_BUFFER_FMT_TYPE_NONE) +#error "AI_FMT_NONE != AI_BUFFER_FMT_TYPE_NONE" +#endif +#if (AI_FMT_FLOAT != AI_BUFFER_FMT_TYPE_FLOAT) +#error "AI_FMT_FLOAT != AI_BUFFER_FMT_TYPE_FLOAT" +#endif +#if (AI_FMT_Q != AI_BUFFER_FMT_TYPE_Q) +#error "AI_FMT_Q != AI_BUFFER_FMT_TYPE_Q" +#endif +#if (AI_FMT_BOOL != AI_BUFFER_FMT_TYPE_BOOL) +#error "AI_FMT_BOOL != AI_BUFFER_FMT_TYPE_BOOL" +#endif +#if (AI_FMT_FLAG_CONST != AI_BUFFER_FMT_FLAG_CONST) +#error "AI_FMT_FLAG_CONST != AI_BUFFER_FMT_FLAG_CONST" +#endif +#if (AI_FMT_FLAG_STATIC != AI_BUFFER_FMT_FLAG_STATIC) +#error "AI_FMT_FLAG_STATIC != AI_BUFFER_FMT_FLAG_STATIC" +#endif +#if (AI_FMT_FLAG_IS_IO != AI_BUFFER_FMT_FLAG_IS_IO) +#error "AI_FMT_FLAG_IS_IO != AI_BUFFER_FMT_FLAG_IS_IO" +#endif +#if (AI_FMT_FLAG_STATIC != AI_BUFFER_FMT_FLAG_PERSISTENT) +#error "AI_FMT_FLAG_STATIC != AI_BUFFER_FMT_FLAG_PERSISTENT" +#endif + + +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_array_format + * @ingroup ai_datatypes_format + * @brief Generic Data Format Specifier for @ref ai_array (32bits packed info) + */ +typedef int32_t ai_array_format; + +/*! + * @enum internal data format enums + * @ingroup ai_datatypes_format + * @brief Generic Data Format Specifier (32bits packed info) + */ +typedef enum { +#define FMT_ENTRY(exp_, name_, type_id_, sign_bit_, complex_bit_, \ + pmask_, bits_, fbits_, ldiv_bits_) \ + AI_ARRAY_FMT_ENTRY(name_) = (AI_FMT_SET_COMPLEX(complex_bit_) | \ + AI_FMT_SET_SIGN(sign_bit_) | \ + AI_FMT_SET_BITS(bits_) | \ + AI_FMT_SET_FBITS(fbits_) | \ + AI_FMT_SET_PMASK(pmask_) | \ + AI_FMT_SET_TYPE(type_id_) | \ + AI_FMT_SET_LDIV(ldiv_bits_)), +#include "formats_list.h" +} ai_array_format_entry; + +/*! + * @brief Get a human readable string from the format ID value + * @ingroup ai_datatypes_format + * @param[in] type the @ref ai_array_format to print out + * @return a string with a human readable name of the format + */ +AI_INTERNAL_API +const char* ai_array_fmt_name(const ai_array_format type); + +/*! + * @brief Check if @ref ai_array_format is a exportable to an @ref ai_buffer_format + * @ingroup ai_datatypes_format + * @param[in] type the ai_array_format to check + * @return true if the format is exported, false otherwise + */ +AI_INTERNAL_API +ai_bool ai_array_fmt_exported(const ai_array_format type); + +/*! + * @brief Check if @ref ai_array_format is a valid format present in the list of + * supported formats + * @ingroup ai_datatypes_format + * @param[in] type the ai_array_format to check + * @return true if the format is valid, false otherwise + */ +AI_INTERNAL_API +ai_bool ai_array_fmt_valid(const ai_array_format type); + +/*! + * @brief Get the complete list of supported @ref ai_array_format formats + * @ingroup ai_datatypes_format + * @param[out] formats a pointer to an array withj all supported formats listed + * @return the number of supported formats + */ +AI_INTERNAL_API +ai_size ai_array_fmt_get_formats(const ai_array_format** formats); + +/*! ai_buffer section ********************************************************* + * Only 25 LSB bits are used for storing actual format bits. 7 bits are reserved + * for format atrtributes, see @ref AI_FMT_FLAG_CONST flag + */ + +#define AI_BUFFER_FMT_ENTRY(name_) \ + AI_CONCAT(AI_BUFFER_FORMAT_, name_) + +#define AI_BUFFER_FMT_NAME(type_) \ + ai_buffer_fmt_name(type_) + +#define AI_BUFFER_FMT_VALID(type_) \ + ai_buffer_fmt_valid(type_) + +#define AI_BUFFER_FMT_GET_FORMATS(formats_) \ + ai_buffer_fmt_get_formats(formats_) + +#define AI_BUFFER_TO_ARRAY_FMT(fmt_) \ + ai_buffer_to_array_fmt(fmt_) + +#define AI_BUFFER_GET_BITS_SIZE(fmt) \ + AI_ARRAY_GET_BITS_SIZE(AI_BUFFER_TO_ARRAY_FMT(fmt)) + + +/*! + * @brief Get a human readable string from the format ID value + * @ingroup ai_datatypes_format + * @param[in] type the @ref ai_buffer_format to print out + * @return a string with a human readable name of the format + */ +AI_INTERNAL_API +const char* ai_buffer_fmt_name( + const ai_buffer_format type); + +/*! + * @brief Check if @ref ai_buffer_format is a valid format present in the list + * of supported formats + * @ingroup ai_datatypes_format + * @param[in] type the @ref ai_buffer_format to check + * @return true if the format is valid, false otherwise + */ +AI_INTERNAL_API +ai_bool ai_buffer_fmt_valid( + const ai_buffer_format type); + +/*! + * @brief Get the complete list of supported @ref ai_buffer_format formats + * @ingroup ai_datatypes_format + * @param[out] formats a pointer to an array with all supported formats listed + * @return the number of supported formats + */ +AI_INTERNAL_API +ai_size ai_buffer_fmt_get_formats( + const ai_buffer_format** formats); + +/*! Conversions section *******************************************************/ +/*! + * @brief Convert from ai_array_format to ai_buffer_format. + * @ingroup ai_datatypes_format + * @param fmt the input ai_array_format to convert + * @return the converted format as a ai_buffer_format + */ +AI_INTERNAL_API +ai_buffer_format ai_array_to_buffer_fmt( + const ai_array_format fmt); + +/*! + * @brief Convert from ai_buffer_format to ai_array_format. + * @ingroup ai_datatypes_format + * @param fmt the input ai_buffer_format to convert + * @return the converted format as a ai_array_format + */ +AI_INTERNAL_API +ai_array_format ai_buffer_to_array_fmt( + const ai_buffer_format fmt); + +/** helpers section ***********************************************************/ +/*! + * @brief Computes the size in bytes given an ai_array_format and number of + * array elements. + * @details This routine computes from the number of elements of the array its + * size in bytes. If the array is referred by a tensor structure, it is the task + * of the latter to handle per-dimension padding (e.g. to align odd rows in a + * 4-bit matrix. At array level the padding elements MUST be included in the + * number of elements. + * @ingroup ai_datatypes_format + * @param[in] fmt the input array format as an ai_array_format + * @param[in] count the number of elements stored in the data array + * @return the size in bytes of the array given the specific format and number + * of elements (including padding elements) + */ +AI_INTERNAL_API +ai_size ai_array_get_byte_size( + const ai_array_format fmt, const ai_size count); + +/*! + * @brief Computes the size in bytes given an ai_array_format and number of + * array elements of the data fields (e.g. LUT table size excluded). + * @details This routine computes from the number of elements of the array its + * size in bytes. If the array is referred by a tensor structure, it is the task + * of the latter to handle per-dimension padding (e.g. to align odd rows in a + * 4-bit matrix. At array level the padding elements MUST be included in the + * number of elements. + * @ingroup ai_datatypes_format + * @param[in] fmt the input array format as an ai_array_format + * @param[in] count the number of elements stored in the data array + * @return the size in bytes of the array given the specific format and number + * of elements (including padding elements) + */ +AI_INTERNAL_API +ai_size ai_array_get_data_byte_size( + const ai_array_format fmt, const ai_size count); + +/*! + * @brief Computes the number of elements from ai_array_format and + * the size in byte of the array. + * @ingroup ai_datatypes_format + * @param fmt the input array format as an ai_array_format + * @param size the size in bytes of the array + * @return the number of elements that could be stored given the format + */ +AI_INTERNAL_API +ai_size ai_array_get_elems_from_size( + const ai_array_format fmt, const ai_size byte_size); + +AI_API_DECLARE_END + +#endif /*AI_DATATYPES_FORMAT_H*/ diff --git a/lib/stai/libstai/include/ai_datatypes_internal.h b/lib/stai/libstai/include/ai_datatypes_internal.h new file mode 100644 index 000000000..e4a9e3197 --- /dev/null +++ b/lib/stai/libstai/include/ai_datatypes_internal.h @@ -0,0 +1,417 @@ +/** + ****************************************************************************** + * @file ai_datatypes_internal.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_DATATYPES_INTERNAL_H +#define AI_DATATYPES_INTERNAL_H + +#include "ai_datatypes.h" +#include "ai_datatypes_defines.h" + +/*! + * @defgroup datatypes_internal Internal Datatypes + * @brief Data structures used internally to implement neural networks + * + * The layers are defined as structs; a generic layer type defines the basic + * layer parameters and type-specific parameters are handled by specializations + * implemented as a C union. The layers keep also a pointer to the parent + * network and the next layer in the network. + * The input, output and parameters are tensor with an hard-coded maximum + * dimension of 4. Tensors are floating point arrays with a notion of size. + * The network is a linked list of layers, and thus it stores only the pointer + * to the first layer. + */ + +/*! + * @section Offsets + * @ingroup datatypes_internal + * Macros to handle (byte) stride addressing on tensors. The `AI_PTR` macro + * is used to always cast a pointer to byte array. The macros `AI_OFFSET_X` are + * used to compute (byte) offsets of respectively adjacents row elements, col + * elements, channel elements and `channel_in` elements. + * @{ + */ + +/*! AI_STORAGE_KLASS SECTION ************************************/ +#define AI_STORAGE_KLASS_TYPE(s_) \ + ( (s_)->type ) + +#define AI_STORAGE_KLASS_SIZE(s_) \ + ( (s_)->size ) + +#define AI_STORAGE_KLASS_DATA(s_, type_) \ + ( (type_*)((s_)->data) ) + +#define AI_STORAGE_KLASS_COPY(dst_, dst_type_, src_, src_type_) \ +{ \ + AI_ASSERT(AI_STORAGE_KLASS_SIZE(src_)>=AI_STORAGE_KLASS_SIZE(dst_)) \ + AI_STORAGE_KLASS_SIZE(dst_) = AI_STORAGE_KLASS_SIZE(src_); \ + for (ai_size i=0; i AI_SHAPE_DEPTH) \ + ? AI_SHAPE_ELEM((shape_), AI_SHAPE_DEPTH) : 1) +#define AI_SHAPE_E(shape_) ((AI_SHAPE_SIZE((shape_)) > AI_SHAPE_EXTENSION) \ + ? AI_SHAPE_ELEM((shape_), AI_SHAPE_EXTENSION) : 1) +#define AI_SHAPE_T(shape_) AI_SHAPE_ELEM((shape_), AI_SHAPE_TIME) + +#define AI_CONV_SHAPE_H AI_SHAPE_W +#define AI_CONV_SHAPE_W AI_SHAPE_CH +#define AI_CONV_SHAPE_CH AI_SHAPE_H +#define AI_CONV_SHAPE_IN_CH AI_SHAPE_IN_CH + +/*! AI_STRIDES SECTION ***********************************/ +#define AI_STRIDE_2D_H(stride_) \ + AI_STRIDE_ELEM((stride_), AI_SHAPE_2D_HEIGHT) + +#define AI_STRIDE_2D_W(stride_) \ + AI_STRIDE_ELEM((stride_), AI_SHAPE_2D_WIDTH) + +#define AI_STRIDE_ELEM(stride_, pos_) \ + AI_STORAGE_KLASS_DATA(stride_, ai_stride_dimension)[pos_] + +#define AI_STRIDE_GET_ELEM(stride_, pos_) \ + (((pos_) < AI_STRIDE_SIZE(stride_)) ? AI_STRIDE_ELEM(stride_, pos_) : 0) + +#define AI_STRIDE_SET_ELEM(stride_, pos_, val_) \ + if ((pos_) < AI_STRIDE_SIZE(stride_)) AI_STRIDE_ELEM(stride_, pos_) = (val_); + +#define AI_STRIDE_TYPE(stride_) \ + AI_STORAGE_KLASS_TYPE(stride_) + +#define AI_STRIDE_SIZE(stride_) \ + AI_STORAGE_KLASS_SIZE(stride_) + +#define AI_STRIDE_CLONE(dst_, src_) \ + AI_STORAGE_KLASS_COPY(dst_, ai_stride_dimension, src_, ai_stride_dimension) + +#define AI_STRIDE_BCAST_CLONE(dst_, src_) \ +{ \ + for (ai_size i=0; i= 5) ? AI_STRIDE_ELEM((stride), AI_SHAPE_DEPTH) : 0) +#define AI_STRIDE_E(stride) ((AI_STRIDE_SIZE((stride)) == 6) ? AI_STRIDE_ELEM((stride), AI_SHAPE_EXTENSION) : 0) +#define AI_STRIDE_T(stride) AI_STRIDE_ELEM((stride), AI_SHAPE_TIME) + +#define AI_STRIDE_SET_H(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_HEIGHT, val) +#define AI_STRIDE_SET_W(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_WIDTH, val) +#define AI_STRIDE_SET_CH(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_CHANNEL, val) +#define AI_STRIDE_SET_IN_CH(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_IN_CHANNEL, val) +#define AI_STRIDE_SET_D(stride, val) if (AI_STRIDE_SIZE((stride)) >= 5) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_DEPTH, val) +#define AI_STRIDE_SET_E(stride, val) if (AI_STRIDE_SIZE((stride)) == 6) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_EXTENSION, val) + +/*! AI_TENSORS SECTION ***********************************/ +#define AI_TENSOR_KLASS(tensor_) \ + ((tensor_) ? (tensor_)->klass : NULL) + +#define AI_TENSOR_SHAPE(tensor_) \ + (&((tensor_)->shape)) + +#define AI_TENSOR_STRIDE(tensor_) \ + (&((tensor_)->stride)) + +#define AI_TENSOR_INFO(tensor_) \ + (&((tensor_)->info)) + +#define AI_TENSOR_ARRAY(tensor_) \ + ((tensor_) ? (tensor_)->data : NULL) + +#define AI_TENSOR_ID(tensor_) \ + ((tensor_) ? AI_TENSOR_INFO(tensor_)->id : 0) + +#define AI_TENSOR_FLAGS(tensor_) \ + ((tensor_) ? AI_TENSOR_INFO(tensor_)->flags : 0) + +#define AI_TENSOR_DATA_SIZE(tensor_) \ + ((tensor_) ? AI_TENSOR_INFO(tensor_)->data_size : 0) + +/*! AI_OFFSETS SECTION ***********************************/ +//#define AI_OFFSET_BATCH(b, stride) ((ai_ptr_offset)(b) * AI_STRIDE_BATCH(stride)) +#define AI_OFFSET_H(y, stride) ((ai_ptr_offset)(y) * AI_STRIDE_H(stride)) +#define AI_OFFSET_W(x, stride) ((ai_ptr_offset)(x) * AI_STRIDE_W(stride)) +#define AI_OFFSET_CH(ch, stride) ((ai_ptr_offset)(ch) * AI_STRIDE_CH(stride)) +#define AI_OFFSET_IN_CH(in_ch, stride) ((ai_ptr_offset)(in_ch) * \ + AI_STRIDE_IN_CH(stride)) +#define AI_OFFSET_D(d, stride) ((ai_ptr_offset)(d) * AI_STRIDE_D(stride)) +#define AI_OFFSET_E(e, stride) ((ai_ptr_offset)(e) * AI_STRIDE_E(stride)) + +#define AI_OFFSET_5D(y, x, d, e, ch, stride) ( \ + AI_OFFSET_H((y), (stride)) + AI_OFFSET_W((x), (stride)) + \ + AI_OFFSET_D((d), (stride)) + AI_OFFSET_E((e), (stride)) + \ + AI_OFFSET_CH((ch), (stride)) ) + +#define AI_OFFSET(y, x, ch, z, stride) ( \ + AI_OFFSET_H((y), (stride)) + AI_OFFSET_W((x), (stride)) + \ + AI_OFFSET_CH((ch), (stride)) + \ + ((AI_STRIDE_SIZE((stride)) == 4) ? AI_OFFSET_IN_CH((z), (stride)) : AI_OFFSET_D((z), (stride))) ) + +/*! @} */ + +#define AI_GET_CONV_OUT_SIZE(in_size, filt_size, pad_l, pad_r, filt_stride) \ + ((((in_size) - (filt_size) + (pad_l) + (pad_r)) / (filt_stride)) + 1) + + +/** Tensors datatypes defines handlers ****************************************/ +#define AI_TENSOR_SIZE(tensor_) \ + get_tensor_size(tensor_, true) + +#define AI_TENSOR_SIZE_UNPAD(tensor_) \ + get_tensor_size(tensor_, false) + +#define AI_TENSOR_BYTE_SIZE(tensor_) \ + get_tensor_byte_size(tensor_) + + +/******************************************************************************/ +#define AI_PLATFORM_VERSION_INIT(major_, minor_, micro_) \ + { .major = (major_), .minor = (minor_), .micro = (micro_), .reserved = 0x0 } + + +/** Integer tensor info extraction ********************************************/ +#define AI_INTQ_INFO_LIST_SCALE_ARRAY(list_, type_) \ + ( ((list_) && (list_)->info) \ + ? ((type_*)((list_)->info->scale)) : NULL ) + +#define AI_INTQ_INFO_LIST_ZEROPOINT_ARRAY(list_, type_) \ + ( ((list_) && (list_)->info) \ + ? ((type_*)((list_)->info->zeropoint)) : NULL ) + +#define AI_KLASS_GET_INTQ_INFO_LIST(tensor_) \ + ((ai_intq_info_list*)((tensor_)->klass)) + + +AI_API_DECLARE_BEGIN + +/*! + * @brief Check whether 2 shapes have identical dimensions. + * @ingroup datatypes_internal + * @param shape0 the 1st tensor shape to compare + * @param shape1 the 2nd tensor shape to compare + * @return true if shape0 and shape1 have same dimensions. false otherwise + */ +AI_DECLARE_STATIC +ai_bool ai_shape_is_same( + const ai_shape* shape0, const ai_shape* shape1) +{ + AI_ASSERT(shape0 && shape1) + if (AI_SHAPE_SIZE(shape0) != AI_SHAPE_SIZE(shape1)) + return false; + ai_size dim = AI_SHAPE_SIZE(shape0); + while ( dim>0 ) { + dim--; + if ( AI_SHAPE_ELEM(shape0, dim)!=AI_SHAPE_ELEM(shape1, dim) ) + return false; + } + return true; +} + + +/*! + * @brief Check whether the shapes is 1*1*1... for a scalar value content. + * @ingroup datatypes_internal + * @param shape the tensor shape to evaluate + * @return true if shape0 is scalar false otherwise + */ +AI_DECLARE_STATIC +ai_bool ai_shape_is_scalar( + const ai_shape* shape0) +{ + ai_size dim = AI_SHAPE_SIZE(shape0); + while (dim>0) { + dim--; + if (AI_SHAPE_ELEM(shape0, dim) != 1) + return false; + } + return true; +} + + +/*! + * @brief Check if shape0 is a subshape of shape1 + * @ingroup datatypes_internal + * @param shape0 the 1st tensor shape to compare + * @param shape1 the 2nd tensor shape to compare + * @return true if shape0 is a subshape of shape1 (all shape0 dimensions are +* smallers or equal of the shape1 ones). false otherwise + */ +AI_DECLARE_STATIC +ai_bool ai_shape_is_subshape( + const ai_shape* shape0, const ai_shape* shape1) +{ + AI_ASSERT(shape0 && shape1) + AI_ASSERT(AI_SHAPE_SIZE(shape0)==AI_SHAPE_SIZE(shape1)) + ai_size dim = AI_SHAPE_SIZE(shape0); + while (dim) { + dim--; + if ( AI_SHAPE_ELEM(shape0, dim)>AI_SHAPE_ELEM(shape1, dim) ) + return false; + } + return true; +} + +/*! + * @brief Computes the total size of a tensor given its dimensions. + * @ingroup datatypes_internal + * @param shape the tensor shape + */ +AI_DECLARE_STATIC +ai_size ai_shape_get_size(const ai_shape* shape) +{ + AI_ASSERT(shape) + ai_size dim = AI_SHAPE_SIZE(shape); + AI_ASSERT(dim > 0) + ai_size size = 1; + while (dim>0) { + dim--; + size *= AI_SHAPE_ELEM(shape, dim); + } + return size; +} + +/*! + * @brief Computes the size of the input image discarding the channels. + * @ingroup datatypes_internal + * @param shape the tensor shape + */ +AI_DECLARE_STATIC +ai_size ai_shape_get_npixels(const ai_shape* shape) +{ + AI_ASSERT(shape) + const ai_size npixels = AI_SHAPE_W(shape) * AI_SHAPE_H(shape); + return npixels; +} + +/** APIs Section *************************************************************/ +/*! + * @brief Get packed version from major, minor, micro representaion. + * @ingroup datatypes_internal + * @param major major version value + * @param minor minor version value + * @param micro micro version value + * @return a packed version info obtained serializing input values + */ +AI_INTERNAL_API +ai_version ai_version_get(const ai_u8 major, const ai_u8 minor, const ai_u8 micro); + +/*! + * @brief Get un-packed version from packed version representaion. + * @ingroup datatypes_internal + * @param version a packed varsion info + * @return struct with de-serialized major, minor, micro values + */ +AI_INTERNAL_API +ai_platform_version ai_platform_version_get(const ai_version version); + +/*! + * @brief Map from ai_buffer data struct to ai_array data struct. + * @ingroup datatypes_internal + * @param buf a pointer to the ai_buffer to be mapped to ai_array + * @return an initialized @ref ai_array struct representing same data + */ +AI_INTERNAL_API +ai_array ai_from_buffer_to_array(const ai_buffer* buf); + +/*! + * @brief Map from ai_array data struct to ai_buffer data struct. + * @ingroup datatypes_internal + * @param array a pointer to the ai_array to be mapped to ai_buffer + * @return an initialized @ref ai_buffer struct representing same data + */ +AI_INTERNAL_API +ai_buffer ai_from_array_to_buffer(const ai_array* array); + +/*! + * @brief get the total number of elements of a n-dimensional tensor. + * @ingroup datatypes_internal + * @param t a pointer to an @ref ai_tensor + * @param with_padding when true it considers also padded elements + * @return the number of elements of the tensor (with/without padded ones) + */ +AI_INTERNAL_API +ai_size get_tensor_size(const ai_tensor* t, const ai_bool with_padding); + +/*! + * @brief get the total size in bytes of elements of a n-dimensional tensor (excluding padded ones). + * @ingroup datatypes_internal + * @param t a pointer to an @ref ai_tensor + * @return the total size in bytes of elements of the tensor (excluding padded ones) + */ +AI_INTERNAL_API +ai_size get_tensor_byte_size(const ai_tensor* t); + + +AI_API_DECLARE_END + +#endif /*AI_DATATYPES_INTERNAL_H*/ diff --git a/lib/stai/libstai/include/ai_layer_custom_interface.h b/lib/stai/libstai/include/ai_layer_custom_interface.h new file mode 100644 index 000000000..f066701f1 --- /dev/null +++ b/lib/stai/libstai/include/ai_layer_custom_interface.h @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file ai_layer_custom_interface.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform custom layers interface APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LAYER_CUSTOM_INTERFACE_H +#define AI_LAYER_CUSTOM_INTERFACE_H + +#include "ai_platform.h" +#include "ai_platform_interface.h" + +#include "layers_custom.h" + +#define INTQ_SCALE_FLOAT (AI_BUFFER_META_FLAG_SCALE_FLOAT) +#define INTQ_ZEROPOINT_U8 (AI_BUFFER_META_FLAG_ZEROPOINT_U8) +#define INTQ_ZEROPOINT_S8 (AI_BUFFER_META_FLAG_ZEROPOINT_S8) +#define INTQ_ZEROPOINT_U16 (AI_BUFFER_META_FLAG_ZEROPOINT_U16) +#define INTQ_ZEROPOINT_S16 (AI_BUFFER_META_FLAG_ZEROPOINT_S16) + +#define AI_TENSOR_HEIGHT (3) +#define AI_TENSOR_WIDTH (2) +#define AI_TENSOR_CHANNEL (1) +#define AI_TENSOR_IN_CHANNEL (0) + + +AI_API_DECLARE_BEGIN + +typedef enum { + TYPE_NONE = 0x0, + TYPE_FLOAT, + TYPE_BOOL, + TYPE_INTEGER, + TYPE_SIGNED, + TYPE_UNSIGNED, +} ai_tensor_type; + +typedef struct { + ai_tensor_type type; + ai_i8 bits; + ai_i8 fbits; +} ai_tensor_format; + +typedef struct { + ai_u16 flags; /*!< optional flags to store intq info attributes */ + ai_u16 size; /*!< number of elements in the the intq_info list */ + ai_float* scale; /*!< array of scales factors */ + union { + ai_u8* zeropoint_u8; /*!< array of zeropoints as unsigned */ + ai_i8* zeropoint_s8; /*!< array of zeropoints as signed */ + }; +} ai_tensor_intq_info; + + +/**************************************************************************** + ** Layer Custom Interface APIs + ****************************************************************************/ +/*! + * @brief acquire the custom layer from its handle + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return a pointer to ai_layer_custom if found and valid, else NULL + */ +AI_INTERFACE_TYPE +ai_layer_custom* ai_layer_custom_get( + ai_layer* layer); + +/*! + * @brief release the custom layer provided its handle + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer to release + */ +AI_INTERFACE_TYPE +void ai_layer_custom_release( + ai_layer* layer); + +/*! + * @brief get the number of inputs tensors of a custom layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return the number of input tensors of the layer. 0 if no input tensors or error + */ +AI_INTERFACE_TYPE +ai_size ai_layer_get_tensor_in_size( + const ai_layer* layer); + +/*! + * @brief get the number of outputs tensors of a custom layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return the number of outputs tensors of the layer. 0 if no outputs tensors or error + */ +AI_INTERFACE_TYPE +ai_size ai_layer_get_tensor_out_size( + const ai_layer* layer); + + +/*! + * @brief get the number of weights tensors of a custom layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return the number of weights tensors of the layer. 0 if no weights tensors or error + */ +AI_INTERFACE_TYPE +ai_size ai_layer_get_tensor_weights_size( + const ai_layer* layer); + + +/*! + * @brief get the n-th (at index pos) input tensor pointer from a layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the layer + * @param pos the index position in the tensor list + * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL + */ +AI_INTERFACE_TYPE +ai_tensor* ai_layer_get_tensor_in( + const ai_layer* layer, const ai_u16 pos); + +/*! + * @brief get the n-th (at index pos) output tensor pointer from a layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the layer + * @param pos the index position in the tensor list + * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL + */ +AI_INTERFACE_TYPE +ai_tensor* ai_layer_get_tensor_out( + const ai_layer* layer, const ai_u16 pos); + + +/*! + * @brief get the n-th (at index pos) weight tensor pointer from a layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the layer + * @param pos the index position in the tensor list + * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL + */ +AI_INTERFACE_TYPE +ai_tensor* ai_layer_get_tensor_weights( + const ai_layer* layer, const ai_u16 pos); + + +/**** Layer Tensors APIs ***************************************************/ +/*! + * @brief check if the tensor has integer quantization informations @ref ai_tensor_intq_info + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return true if tensot has integer quantization informations, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_tensor_has_intq( + const ai_tensor* t); + +/*! + * @brief get the tensor integer quantization informations @ref ai_tensor_intq_info + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the integer quantization informations as a struct @ref ai_tensor_intq_info + */ +AI_INTERFACE_TYPE +ai_tensor_intq_info ai_tensor_get_intq( + const ai_tensor* t); + +/*! + * @brief get the format of the tensor see @ref ai_tensor_format + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the tensor format + */ +AI_INTERFACE_TYPE +ai_tensor_format ai_tensor_get_format( + const ai_tensor* t); + +/**** Shapes Getters ****/ +/*! + * @brief get the dimensionality of the tensor shapes + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the dimensionality of the tensor shape + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_shape_size( + const ai_tensor* t); + +/*! + * @brief get the value of the shape dimensionality pos + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the value of the shape dimensionality at pos of the tensor + */ +AI_INTERFACE_TYPE +ai_shape_dimension ai_tensor_get_shape( + const ai_tensor* t, const ai_u16 pos); + +/**** Strides Getters ****/ +/*! + * @brief get the dimensionality of the tensor strides + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the dimensionality of the tensor strides @ref ai_stride + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_stride_size( + const ai_tensor* t); + +/*! + * @brief get the value of the stride dimensionality pos + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the value of the stride dimensionality at pos of the tensor + */ +AI_INTERFACE_TYPE +ai_stride_dimension ai_tensor_get_stride( + const ai_tensor* t, const ai_u16 pos); + +/**** Data Storage Getters ****/ +/*! + * @brief get tensor storage data buffer pointer + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return a pointer to the tensor data buffer, set to NULL if error + */ +AI_INTERFACE_TYPE +ai_any_ptr ai_tensor_get_data( + const ai_tensor* t); + +/*! + * @brief get number of tensor elements + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the number of tensor elements or 0 if error + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_data_size( + const ai_tensor* t); + +/*! + * @brief get the size in bytes of the tensor data buffer + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the size in bytes of the tensor data buffer. 0 if error + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_data_byte_size( + const ai_tensor* t); + + +AI_API_DECLARE_END + +#endif /*AI_LAYER_CUSTOM_INTERFACE_H*/ diff --git a/lib/stai/libstai/include/ai_lite.h b/lib/stai/libstai/include/ai_lite.h new file mode 100644 index 000000000..1ad075e6a --- /dev/null +++ b/lib/stai/libstai/include/ai_lite.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file ai_lite.h + * @author STMicroelectronics + * @brief Definitions and implementations of runtime-lite public APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LITE_H +#define AI_LITE_H + +#include "ai_platform.h" +#include "stai.h" + +#define LITE_API_ENTRY \ + /* LITE_API_ENTRY */ + +#define LITE_GRAPH_INIT(_inputs, _outputs, _activations, _weights, _cb, _cb_cookie) { \ + .inputs = (stai_ptr*)(_inputs), \ + .outputs = (stai_ptr*)(_outputs), \ + .activations = (stai_ptr*)(_activations), \ + .weights = (const stai_ptr*)(_weights), \ + .cb = (_cb), \ + .cb_cookie = (_cb_cookie), \ +} + + +STAI_API_DECLARE_BEGIN + +typedef enum { + LITE_OK = 0x0, + LITE_KO_INPUTS = (0x1 << 0), + LITE_KO_OUTPUTS = (0x1 << 1), + LITE_KO_WEIGHTS = (0x1 << 2), + LITE_KO_ACTIVATIONS = (0x1 << 3), + LITE_KO_GRAPH = (0x1 << 4), + LITE_KO_API = (0x1 << 5), +} lite_result; + + +typedef struct { + stai_ptr* inputs; + stai_ptr* outputs; + stai_ptr* activations; + const stai_ptr* weights; + const stai_event_cb cb; + void* cb_cookie; +} lite_graph; + + +STAI_API_DECLARE_END + +#endif /* AI_LITE_H */ diff --git a/lib/stai/libstai/include/ai_lite_inspect.h b/lib/stai/libstai/include/ai_lite_inspect.h new file mode 100644 index 000000000..68036dc40 --- /dev/null +++ b/lib/stai/libstai/include/ai_lite_inspect.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file ai_lite_inspect.h + * @author STMicroelectronics + * @brief Definitions and implementations of runtime-lite inspection routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LITE_INSPECT_H +#define AI_LITE_INSPECT_H +#include "ai_platform.h" + +// #define HAS_LITE_INSPECT + +#ifdef HAS_LITE_INSPECT +#include "stai_debug.h" + +#define LITE_INSPECT_CB(flags, node_id, data_ptr, data_size, data_fmt, data_id, data_pos) { \ + if (graph->cb) { \ + graph->cb((const void*)(graph->cb_cookie), \ + (const stai_flags)(flags), \ + (const int32_t)(node_id), (const void*)(data_ptr), (const int32_t)(data_size), \ + (const int32_t)(data_fmt), (const int32_t)(data_id), (const int32_t)(data_pos)); \ + } \ +} + +#else + +#define LITE_INSPECT_CB(flags, node_id, data_ptr, data_size, data_fmt, data_id, data_pos) { \ + do { /* LITE_INSPECT_CB() */ } while (0); \ +} + +#endif /* HAS_LITE_INSPECT */ + +#endif /* AI_LITE_INSPECT_H */ diff --git a/lib/stai/libstai/include/ai_lite_interface.h b/lib/stai/libstai/include/ai_lite_interface.h new file mode 100644 index 000000000..82fd300f2 --- /dev/null +++ b/lib/stai/libstai/include/ai_lite_interface.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file ai_lite_interface.h + * @author STMicroelectronics + * @brief Definitions and implementations of runtime-lite codegen APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LITE_INTERFACE_H +#define AI_LITE_INTERFACE_H + +#include "ai_lite.h" +#include "core_assert.h" + + +/*****************************************************************************/ +/* Generic Codegen Section */ +// #ifdef HAS_LOG +#if 0 +#include "core_log.h" + +#define LITE_GRAPH_START(_graph_name) \ + AI_LOG_DEBUG("[LITE GRAPH START] : " _graph_name) + +#define LITE_GRAPH_END(_graph_name) \ + AI_LOG_DEBUG("[LITE GRAPH END] : " _graph_name) + +#else + +#define LITE_GRAPH_START(_graph_name) \ + /* LITE_GRAPH_START() */ + +#define LITE_GRAPH_END(_graph_name) \ + /* LITE_GRAPH_END() */ + +#endif /* HAS_LOG */ + +#define LITE_ASSERT(expr) \ + CORE_ASSERT(expr) + + +/*****************************************************************************/ +#if defined(_MSC_VER) + #define LITE_DECLARE_STATIC static __inline + #define LITE_HINT_INLINE static __inline + #define LITE_FORCE_INLINE static __inline +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define LITE_DECLARE_STATIC static inline + #define LITE_HINT_INLINE static inline + #define LITE_FORCE_INLINE static inline +#elif defined(__GNUC__) + #define LITE_DECLARE_STATIC static __inline + #define LITE_HINT_INLINE static __inline + #define LITE_FORCE_INLINE static __inline +#else + #define LITE_DECLARE_STATIC static __inline + #define LITE_HINT_INLINE static __inline + #define LITE_FORCE_INLINE static __inline +#endif /* _MSC_VER */ + +#define LITE_API_ENTRY /* LITE_API_ENTRY */ + +#define LITE_PACK(...) \ + __VA_ARGS__ + +#define LITE_UNUSED(_elem) \ + ((void)(_elem)); + + +/*****************************************************************************/ +/* Arrays Section */ + +#define LITE_ARRAY_VALUES(...) \ + { LITE_PACK(__VA_ARGS__) } + +#define LITE_ARRAY_DATA(_array, _type) \ + ((_type*)(_array)->data) + +#define LITE_ARRAY_DATA_START(_array, _type) \ + ((_type*)(_array)->data_start) + +/*****************************************************************************/ +/* Tensors Section */ + +#define LITE_TENSOR_ARRAY(_tensor, _pos) \ + (((_tensor)->data) + (_pos)) + +/*****************************************************************************/ +/* Tensors List Section */ + +#define LITE_TENSOR_LIST(_chain, _pos) \ + (&(_chain)->chain[_pos]) + +#define LITE_TENSOR_IN(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 0)->tensor[_pos]) + +#define LITE_TENSOR_OUT(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 1)->tensor[_pos]) + +#define LITE_TENSOR_WEIGHTS(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 2)->tensor[_pos]) + +#define LITE_TENSOR_SCRATCHS(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 3)->tensor[_pos]) + +/*****************************************************************************/ +#define LITE_LAYER_ACQUIRE(name_, cast_type_, ptr_) \ + LITE_ASSERT(ptr_) \ + AI_CONCAT(ai_layer_, cast_type_)* name_ = \ + (AI_CONCAT(ai_layer_, cast_type_)*)(ptr_); + +#define LITE_LAYER_RELEASE(name_, cast_type_) \ + /* LITE_LAYER_RELEASE() */ + + +#endif /* AI_LITE_INTERFACE_H */ diff --git a/lib/stai/libstai/include/ai_lite_math_helpers.h b/lib/stai/libstai/include/ai_lite_math_helpers.h new file mode 100644 index 000000000..af5701476 --- /dev/null +++ b/lib/stai/libstai/include/ai_lite_math_helpers.h @@ -0,0 +1,272 @@ +#ifndef AI_LITE_MATH_HELPERS_H +#define AI_LITE_MATH_HELPERS_H +/** + ****************************************************************************** + * @file ai_lite_math_helpers.h + * @author STMicroelectronics + * @brief Math helpers routines header file for lite APIs. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include +#include +#include + +#include "ai_platform.h" +#include "ai_platform_interface.h" +#include "ai_datatypes_defines.h" + +#define AI_FLOAT_TOLERANCE (6.19209290e-5F) /* Used for small calculation + noise issues */ +#define AI_FLOAT_EPSILON (1.19209290e-7F) +#define AI_I8_EPSILON (0.00787401F) /* 1/(2^7 - 1) */ +#define AI_I16_EPSILON (3.051851e-5F) /* 1/(2^15 - 1) */ + +#define AI_FLT_MAX (3.40282346638528859812e+38f) + +#define AI_MIN(x,y) ( ((x)<(y)) ? (x) : (y) ) +#define AI_MAX(x,y) ( ((x)>(y)) ? (x) : (y) ) +#define AI_SIGN(x) (((x)>0) ? 1 : -1) +#define AI_CLAMP(x, min, max) AI_MIN(AI_MAX(x,min), max) +#define AI_ABS(x) fabsf(x) +#define AI_ABS_DIFF(x, y) ( ((x)>(y)) ? ((x)-(y)) : ((y)-(x)) ) +#define AI_NEG(x) ( -1 * (x) ) +#define AI_NOT(x) ( ((x)==true) ? false : true) +#define AI_RECIPROCAL(x) ( 1.0f / (x) ) +#define AI_CEIL(x) ceilf(x) +#define AI_FLOOR(x) floorf(x) +#define AI_FLOOR_DIV(x, y) AI_FLOOR((x)/(y)) /* floor division: x // y */ +#define AI_FLOOR_MOD(x, y) fmodf(x, y) +#define AI_ROUND(x) roundf(x) +#define AI_POW(x,y) powf(x, y) + +#define AI_SQUARED_DIFF(x, y) (((x)-(y)) * ((x)-(y))) + +#define AI_FLOAT_NEGATIVE_HALF (-0.5f + AI_FLOAT_EPSILON) +#define AI_FLOAT_POSITIVE_HALF (0.5f) + + +#define AI_MATH_ACOS(x) acosf(x) +#define AI_MATH_ACOSH(x) acoshf(x) +#define AI_MATH_ASIN(x) asinf(x) +#define AI_MATH_ASINH(x) asinhf(x) +#define AI_MATH_ATAN(x) atanf(x) +#define AI_MATH_ATANH(x) atanhf(x) +#define AI_MATH_COS(x) cosf(x) +#define AI_MATH_COSH(x) coshf(x) +#define AI_MATH_ERF(x) erff(x) +#define AI_MATH_EXP(x) expf(x) +#define AI_MATH_LOG(x) logf(x) +#define AI_MATH_POW(x, e) powf((x), (e)) +#define AI_MATH_RSQRT(x) (1.0f / AI_MATH_SQRT(x)) +#define AI_MATH_SIN(x) sinf(x) +#define AI_MATH_SINH(x) sinhf(x) +#define AI_MATH_SQRT(x) ai_math_sqrt(x) +#define AI_MATH_TAN(x) tanf(x) +#define AI_MATH_TANH(x) tanhf(x) +#define AI_MATH_SQUARE(x) AI_MATH_POW(x, 2.0f) + +#define AI_MATH_ACOS(x) acosf(x) +#define AI_MATH_ACOSH(x) acoshf(x) +#define AI_MATH_ASIN(x) asinf(x) +#define AI_MATH_ASINH(x) asinhf(x) +#define AI_MATH_ATAN(x) atanf(x) +#define AI_MATH_ATANH(x) atanhf(x) +#define AI_MATH_COS(x) cosf(x) +#define AI_MATH_COSH(x) coshf(x) +#define AI_MATH_ERF(x) erff(x) +#define AI_MATH_EXP(x) expf(x) +#define AI_MATH_LOG(x) logf(x) +#define AI_MATH_POW(x, e) powf((x), (e)) +#define AI_MATH_RSQRT(x) (1.0f / AI_MATH_SQRT(x)) +#define AI_MATH_SIN(x) sinf(x) +#define AI_MATH_SINH(x) sinhf(x) +#define AI_MATH_SQRT(x) ai_math_sqrt(x) +#define AI_MATH_TAN(x) tanf(x) +#define AI_MATH_TANH(x) tanhf(x) +#define AI_MATH_SQUARE(x) AI_MATH_POW(x, 2.0f) +#define AI_MATH_RELU_TEST(x, thr, min, max) \ + (((x)<=(thr)) ? (min) : (max)) + +#define AI_MATH_CLIP_LINEAR_REMAP(x, alpha, beta) \ + (AI_MAX(0, AI_MIN(1, ((x) * (alpha) + (beta))))) + +#define AI_MATH_RELU_GENERIC(x, thr, alpha, max) \ + AI_MATH_RELU_TEST(x, max, AI_MATH_RELU_GENERIC_NO_MAX(x, thr, alpha), max) + +#define AI_MATH_RELU_GENERIC_NO_MAX(x, thr, alpha) \ + AI_MATH_RELU_TEST(x, thr, ((alpha)*((x)-(thr))), x) + +#define AI_MATH_RELU_THRESHOLDED(x, thr) \ + AI_MATH_RELU_TEST(x, thr, 0, (x)) + +#define AI_MATH_LEAKY_RELU(x, neg_slope, pos_slope) \ + AI_MATH_RELU_TEST(x, 0, (x)*(neg_slope), (x)*(pos_slope)) +// ( ((x)>0) ? (x)*(pos_slope) : (x)*(neg_slope) ) + +#define AI_MATH_PRELU(x, slope) \ + AI_MATH_RELU_TEST(x, 0, (x)*(slope), (x)) +// AI_MATH_LEAKY_RELU(x, slope, 1) + +#define AI_MATH_RELU(x) \ + AI_MATH_RELU_TEST(x, 0, 0, x) +// AI_MAX(x, 0) + +#define AI_MATH_ELU(x, alpha) \ + (AI_MAX(0.0f, (x)) + AI_MIN(0.0f, (alpha) * (AI_MATH_EXP(x)-1.0f))) + +#define AI_MATH_SELU(x, alpha, scale) \ + ((scale)*AI_MATH_ELU(x, alpha)) + +#define AI_MATH_SCALED_TANH(x, alpha, beta) \ + ((alpha)*AI_MATH_TANH((beta)*(x))) + +#define AI_MATH_SIGMOID(x) \ + (1.0f / (1.0f + AI_MATH_EXP(-(x)))) + +#define AI_MATH_LOGISTIC(x)\ + (x < 0) ? (1.0f -(1.0f / (1.0f + AI_MATH_EXP(-AI_ABS(x))))) :\ + (1.0f / (1.0f + AI_MATH_EXP(-AI_ABS(x)))) + +#define AI_MATH_HARD_SIGMOID(x, alpha, beta) \ + AI_MATH_CLIP_LINEAR_REMAP(x, alpha, beta) + +#define AI_MATH_GELU_NO_APPROXIMATE(x) \ + ((x / 2.0f) * (1.0f + AI_MATH_ERF(x/AI_MATH_SQRT(2.0f)))) + +#define AI_MATH_GELU_APPROXIMATE(x) \ + ((x / 2.0f) * (1.0f + AI_MATH_TANH(AI_MATH_SQRT(2.0f/PI)*(x + 0.044715f * AI_MATH_POW(x, 3.0f))))) + +#define AI_MATH_GELU(x, approximate) \ + (((bool)approximate) ? AI_MATH_GELU_APPROXIMATE(x) : AI_MATH_GELU_NO_APPROXIMATE(x)) + + + + +/* Formula with higher accuracy */ +#define AI_MATH_SWISH(x) \ + ((x) * AI_MATH_SIGMOID(x)) + +#define AI_MATH_HARD_SWISH(x) \ + ((x) * AI_MATH_CLIP_LINEAR_REMAP(x, 1.0f/6, 0.5f)) + +#define AI_MATH_SOFT_PLUS(x) \ + AI_MATH_LOG(1.0f + AI_MATH_EXP(x)) + +#define AI_MATH_SOFT_SIGN(x) \ + ((x) / (1.0f + AI_ABS(x))) + +/*! + * @brief Round float x to the nearest integer (breaking +- 0.5 ties to the nearest even integer) + */ +static inline ai_i32 ai_round_f2i_t2e(ai_float x) +{ + x += x >= 0.0f ? 0.5f : -0.5f; + ai_i32 i32_x = (ai_i32)x; + + if (((ai_float)i32_x == x) && ((i32_x & 0x1) != 0)) { + ai_i32 to_nearest_even = i32_x < 0 ? 1 : -1; + i32_x += to_nearest_even; + } + return i32_x; +} + +static inline ai_u32 ai_round_f2u_t2e(ai_float x) +{ + x += 0.5f; + ai_u32 u32_x = (ai_u32)x; + + if (((ai_float)u32_x) == x && ((u32_x & 0x1) != 0)) { + u32_x -= 1; + } + return u32_x; +} + + +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_vec4_float + * @ingroup ai_datatypes_internal + * @brief 32bit X 4 float (optimization for embedded MCU) + */ +typedef struct { + ai_float a1; + ai_float a2; + ai_float a3; + ai_float a4; +} ai_vec4_float; + + +#define AI_VEC4_FLOAT(ptr_) \ + _get_vec4_float((ai_handle)(ptr_)) + + +AI_DECLARE_STATIC +ai_vec4_float _get_vec4_float(const ai_handle fptr) +{ + return *((const ai_vec4_float*)fptr); +} + +/*****************************************************************************/ +typedef struct { + ai_u16 numRows; /**< number of rows of the matrix. */ + ai_u16 numCols; /**< number of columns of the matrix. */ + ai_float *pData; /**< points to the data of the matrix. */ +} ai_matrix_f32; + +/*! + * @brief general 2D matrix initialization + * @ingroup ai_lite_math_helpers + * @param S pointer to S matrix + * @param nRows number of rows of S matrix + * @param nColumns number of columns of S matrix + * @param pData pointer to S matrix data + */ +AI_INTERFACE_ENTRY +void st_mat_init_f32(ai_matrix_f32* S, + const uint16_t nRows, + const uint16_t nColumns, + float* pData); + + +/*! + * @brief general 2D matrix multiplication on float values + * @ingroup ai_lite_math_helpers + * @param pSrcA pointer to A matrix + * @param pSrcB pointer to B matrix + * @param pSrcC pointer to C matrix/array + * @param alpha multiplier of A*B product + * @param beta multiplier of C + * @param tA flag for A transpose + * @param tB flag for B transpose + * @param pDstY matrix result + * @return ARM_MATH_SUCCESS in case of success, ARM_MATH_SIZE_MISMATCH else + */ +AI_INTERFACE_ENTRY +uint32_t st_mat_gemm_f32(const ai_matrix_f32* pSrcA, + const ai_matrix_f32* pSrcB, + const ai_matrix_f32* pSrcC, + const float alpha, const float beta, + const int8_t tA, const int8_t tB, + ai_matrix_f32 * pDstY); + +/*! + * @brief platform optimized square root on a float value + * @ingroup ai_lite_math_helpers + * @param x input value + * @return square root of the value + */ +AI_INTERFACE_ENTRY +float ai_math_sqrt(const float x); + +#endif /*AI_LITE_MATH_HELPERS_H*/ diff --git a/lib/stai/libstai/include/ai_math_helpers.h b/lib/stai/libstai/include/ai_math_helpers.h new file mode 100644 index 000000000..72916ce5c --- /dev/null +++ b/lib/stai/libstai/include/ai_math_helpers.h @@ -0,0 +1,572 @@ +#ifndef AI_MATH_HELPERS_H +#define AI_MATH_HELPERS_H +/** + ****************************************************************************** + * @file ai_math_helpers.h + * @author AST Embedded Analytics Research Platform + * @brief Math helpers routines header file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include "ai_lite_math_helpers.h" + +//#if defined(HAS_X86) || defined(__CC_ARM) || defined(CM4) || defined(CM7) +#define _AI_CONV_2D_LOOP_UNROLLING_OPTIM +//#endif + +#define STM32_DOT_INLINE_OPTIM + +/* Modes for element wise integer optimized implementation */ +#define AI_ELTWISE_NO_SCALAR (0) +#define AI_ELTWISE_SCALAR1 (1) +#define AI_ELTWISE_SCALAR2 (2) +#define AI_ELTWISE_SCALAR_CH1 (3) +#define AI_ELTWISE_SCALAR_CH2 (4) + + +AI_API_DECLARE_BEGIN + +#if defined(STM32_DOT_INLINE_OPTIM) + +AI_DECLARE_STATIC +void __ai_math_dot_array( + ai_float* out, + const ai_float* data0, + const ai_float* data1, + ai_size data_size) +{ + ai_register ai_float sum = 0.0f; /* Temporary result storage */ + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + +#if defined(_AI_CONV_2D_LOOP_UNROLLING_OPTIM) + /* First part of the processing with loop unrolling. Compute 16 outputs at a time. + ** a second loop below computes the remaining 1 to 15 samples. */ + while (data_size >= 16u) { + ai_register ai_vec4_float ch_in_f = AI_VEC4_FLOAT(data1); + ai_register ai_vec4_float weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + + ch_in_f = AI_VEC4_FLOAT(data1); + weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + + ch_in_f = AI_VEC4_FLOAT(data1); + weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + + ch_in_f = AI_VEC4_FLOAT(data1); + weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + data_size -= 16u; + } + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (data_size >= 4u) { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer */ + sum += (*data0++) * (*data1++); + sum += (*data0++) * (*data1++); + sum += (*data0++) * (*data1++); + sum += (*data0++) * (*data1++); + + /* Decrement the loop counter */ + data_size -= 4u; + } +#endif + while (data_size > 0u) { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += (*data0++) * (*data1++); + + /* Decrement the loop counter */ + data_size--; + } + + /* Directly accumulate the result back in the destination buffer */ + *out += sum; +} + + +#undef AI_MATH_DOT_ARRAY +#define AI_MATH_DOT_ARRAY(dst, src0, src1, size) \ + { __ai_math_dot_array(dst, src0, src1, size); } + +#else /* STM32_DOT_INLINE_OPTIM */ + +#undef AI_MATH_DOT_ARRAY +#define AI_MATH_DOT_ARRAY(dst, src0, src1, size) \ + { ai_math_dot_array(dst, src0, src1, size); } + +#endif + + +/*! + * @defgroup math_helpers Math helpers + * @brief Common math functions + * + * Math functions are mapped to the underlying platform through those utility + * functions. On x86 and ARM v7 they are mapped to the float math functions in + * the C99 standard library; on MCUs they are mapped to the ARM DSP functions. + */ + +/*! + * @brief platform optimized dot product of float vectors + * + * Computes the dot product between vectors and adds the result to out. + * @ingroup math_helpers + * @param out scalar result of the dot product + * @param data0 the first float vector + * @param data1 the second float vector + * @param data_size the size of both vectors + */ +AI_INTERFACE_ENTRY +void ai_math_dot_array( + ai_float* out, + const ai_float* data0, + const ai_float* data1, + const ai_size data_size); +/*! + * @brief ErfInv a float value + * @ingroup math_helpers + * @param x input value + * @return square root of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_erfinv(const ai_float x); + +/*! + * @brief platform optimized exponential on a float value + * @ingroup math_helpers + * @param x input value + * @return exponential of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_exp(const ai_float x); + +/*! + * @brief platform logical not + * @ingroup math_helpers + * @param x input value + * @return not of the value + */ +AI_INTERFACE_ENTRY ai_bool ai_logical_not(const ai_bool x); + +/*! + * @brief platform optimized pow on a float value + * @ingroup math_helpers + * @param x input value + * @param e input value + * @return pow of the value ^ e + */ +AI_INTERFACE_ENTRY ai_float ai_math_pow(const ai_float x, const ai_float e); + +/*! + * @brief platform optimized tangent on a float value + * @ingroup math_helpers + * @param x input value + * @return hyperbolic tangent of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_tanh(const ai_float x); + +/*! + * @brief platform optimized relu on a float value + * @ingroup math_helpers + * @param x input value + * @return relu of the value ( x if x>0 else 0) + */ +AI_INTERFACE_ENTRY ai_float ai_math_relu(const ai_float x); + +/*! + * @brief platform optimized parametric relu on a float value + * @ingroup math_helpers + * @param x input value + * @param slope input value + * @return parametric relu of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_prelu(const ai_float x, const ai_float slope); + +/*! + * @brief platform optimized parametric sigmoid on a float value + * @ingroup math_helpers + * @param x input value + * @return sigmoid of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_sigmoid(const ai_float x); + +/*! + * @brief platform optimized parametric hard sigmoid on a float value + * @ingroup math_helpers + * @param x input value + * @return hard sigmoid of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_hard_sigmoid(const ai_float x); // const ai_float alpha, const ai_float beta); + +/*! + * @brief platform optimized parametric swish on a float value + * @ingroup math_helpers + * @param x input value + * @return swish of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_swish(const ai_float x); + +/*! + * @brief platform optimized parametric hard_swish on a float value + * @ingroup math_helpers + * @param x input value + * @return hard_swish of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_hard_swish(const ai_float x); + +/*! + * @brief platform optimized parametric gelu on a float value + * @ingroup math_helpers + * @param x input value + * @param aaproximate input value + * @return gelu of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_gelu(const ai_float x, const ai_bool approximate); + +/*! + * @brief platform optimized parametric sign function on a float value + * @ingroup math_helpers + * @param x input value + * @return sign of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_sign(const ai_float x); + +/*! + * @brief optimized parametric rectified linear unit on a float value + * @ingroup math_helpers + * @param x input value + * @param slope parameter value + * @return x if x is positive and x*slope otherwise + */ +AI_INTERFACE_ENTRY ai_float ai_fast_prelu(const ai_float x, const ai_float slope); + +AI_INTERFACE_ENTRY void ai_div(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_div_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_bitshift_right(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_right_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_right_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_right_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_floor_div(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_floor_div_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_floor_mod(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_floor_mod_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_mod(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_max(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_max_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_min(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_min_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_mul(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_mul_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_pow(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_pow_buffer(ai_handle out, const ai_handle b, const ai_handle e, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_sub(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_sub_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_sum(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_sum_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_and(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_and_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_or(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_or_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_xor(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_xor_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_greater(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_greater_or_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_less(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_less_or_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_not_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_squared_diff(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_squared_diff_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_atan2(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_atan2_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_API_DECLARE_END + +#endif /* AI_MATH_HELPERS_H */ diff --git a/lib/stai/libstai/include/ai_platform.h b/lib/stai/libstai/include/ai_platform.h new file mode 100644 index 000000000..b49f04ab9 --- /dev/null +++ b/lib/stai/libstai/include/ai_platform.h @@ -0,0 +1,985 @@ +/** + ****************************************************************************** + * @file ai_platform.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_PLATFORM_H +#define AI_PLATFORM_H + +#include +#include + +#define __STDC_FORMAT_MACROS 1 +#include + +#ifndef AI_PLATFORM_API_MAJOR +#define AI_PLATFORM_API_MAJOR (1) +#endif +#ifndef AI_PLATFORM_API_MINOR +#define AI_PLATFORM_API_MINOR (2) +#endif +#ifndef AI_PLATFORM_API_MICRO +#define AI_PLATFORM_API_MICRO (0) +#endif + +#define AI_PLATFORM_API_VERSION \ + AI_VERSION(AI_PLATFORM_API_MAJOR, \ + AI_PLATFORM_API_MINOR, \ + AI_PLATFORM_API_MICRO) + + +#ifndef AI_TOOLS_API_VERSION_MAJOR +#define AI_TOOLS_API_VERSION_MAJOR (1) +#endif +#ifndef AI_TOOLS_API_VERSION_MINOR +#define AI_TOOLS_API_VERSION_MINOR (5) +#endif +#ifndef AI_TOOLS_API_VERSION_MICRO +#define AI_TOOLS_API_VERSION_MICRO (0) +#endif + +/*****************************************************************************/ +#define AI_TOOLS_API_VERSION \ + AI_VERSION(AI_TOOLS_API_VERSION_MAJOR, \ + AI_TOOLS_API_VERSION_MINOR, \ + AI_TOOLS_API_VERSION_MICRO) + +#define AI_TOOLS_API_VERSION_1_3 \ + AI_VERSION(1, 3, 0) + +#define AI_TOOLS_API_VERSION_1_4 \ + AI_VERSION(1, 4, 0) + +#define AI_TOOLS_API_VERSION_1_5 \ + AI_VERSION(1, 5, 0) + +/*****************************************************************************/ +#ifdef __cplusplus +#define AI_API_DECLARE_BEGIN extern "C" { +#define AI_API_DECLARE_END } +#define ai_register /* register */ +#else +#include +#define AI_API_DECLARE_BEGIN /* AI_API_DECLARE_BEGIN */ +#define AI_API_DECLARE_END /* AI_API_DECLARE_END */ +#define ai_register register +#endif + +/*****************************************************************************/ +#define AI_FLAG_NONE (0x0) + +/*****************************************************************************/ +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_flags + * @ingroup ai_platform + * @brief bitmask for flags management + */ +typedef uint32_t ai_flags; + +/*****************************************************************************/ +#define AI_CONCAT_ARG(a, b) a ## b +#define AI_CONCAT(a, b) AI_CONCAT_ARG(a, b) + +/*! AI_CAST SECTION ***********************************/ +#define AI_CAST(type_, expr_) ((type_)(expr_)) + +/*****************************************************************************/ +#define AI_MAGIC_SIGNATURE \ + (0xa1facade) + +#define AI_PACK(...) \ + __VA_ARGS__ + +/*****************************************************************************/ +#define AI_SHAPE_BCWH (0x01u) + +/*! + * @typedef ai_shape_dimension + * @ingroup ai_platform + * @brief shape dimension type to be used in shape related structs @ref ai_buffer_shape + */ +typedef uint32_t ai_shape_dimension; + +/*****************************************************************************/ +#if defined(_MSC_VER) + #define AI_API_ENTRY __declspec(dllexport) + #define AI_ALIGNED(x) /* AI_ALIGNED(x) */ +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define AI_API_ENTRY /* AI_API_ENTRY */ + #define AI_ALIGNED(x) AI_CONCAT(AI_ALIGNED_,x) + #define AI_ALIGNED_1 _Pragma("data_alignment = 1") + #define AI_ALIGNED_2 _Pragma("data_alignment = 2") + #define AI_ALIGNED_4 _Pragma("data_alignment = 4") + #define AI_ALIGNED_8 _Pragma("data_alignment = 8") + #define AI_ALIGNED_16 _Pragma("data_alignment = 16") + #define AI_ALIGNED_32 _Pragma("data_alignment = 32") +#elif defined(__CC_ARM) + #define AI_API_ENTRY __attribute__((visibility("default"))) + #define AI_ALIGNED(x) __attribute__((aligned (x))) + /* Keil disallows anonymous union initialization by default */ + #pragma anon_unions +#elif defined(__GNUC__) + //#define AI_API_ENTRY __attribute__((visibility("default"))) + #define AI_API_ENTRY /* AI_API_ENTRY */ + #define AI_ALIGNED(x) __attribute__((aligned(x))) +#else + /* Dynamic libraries are not supported by the compiler */ + #define AI_API_ENTRY /* AI_API_ENTRY */ + #define AI_ALIGNED(x) /* AI_ALIGNED(x) */ +#endif + +#define AI_HANDLE_PTR(ptr_) ((ai_handle)(ptr_)) +#define AI_HANDLE_NULL AI_HANDLE_PTR(NULL) + +#define AI_HANDLE_FUNC_PTR(func) ((ai_handle_func)(func)) + +#define AI_UNUSED(x) (void)(x); + +#define AI_DEPRECATED /* AI_DEPRECATED */ + +#define AI_LEGACY /* AI_LEGACY */ + +#define AI_MAGIC_MARKER (0xA1FACADE) + + +#if defined(__cplusplus) + #define AI_STRUCT_INIT {} + #define AI_C_ARRAY_INIT {} +#else + #define AI_STRUCT_INIT {0} + #define AI_C_ARRAY_INIT {0} +#endif + +#define AI_ERROR_FMT AIU32_FMT + +#define AI_IS_UNSIGNED(type) \ + ((((type)0) - 1) > 0) + +#define AI_CUSTOM_SIZE(type) \ + (ai_custom_type_signature)((AI_IS_UNSIGNED(type)) \ + ? (0x80|(sizeof(type)&0x7f)) : (sizeof(type)&0x7f)) + +/*! network buffers struct handlers *******************************************/ +#ifdef __cplusplus + +#define AI_NETWORK_PARAMS_INIT(params_, activations_) \ +{ \ + {{ params_, activations_ }} \ +} + +#define AI_NETWORK_BUFFERS_INIT(weights_buffers_, activations_buffers_) \ +{ \ + AI_MAGIC_SIGNATURE, AI_PACK(weights_buffers_), AI_PACK(activations_buffers_) \ +} + +#else + +#define AI_NETWORK_PARAMS_INIT(params_, activations_) \ +{ \ + .params = params_, \ + .activations = activations_ \ +} + +#define AI_NETWORK_BUFFERS_INIT(weights_buffers_, activations_buffers_) \ +{ \ + .map_signature = AI_MAGIC_SIGNATURE, \ + .map_weights = AI_PACK(weights_buffers_), \ + .map_activations = AI_PACK(activations_buffers_) \ +} + +#endif // __cplusplus + + +/*! binary padded bits macro helpers *****************************************/ +#define AI_PBITS_MASK \ + (0x1F) + +#define AI_PBITS_SHIFTS \ + (5) + +#define AI_PBITS_PADDED_BYTES_COUNT(bits_) \ + (((ai_u32)(bits_) + 7) >> 3) + +#define AI_PBITS_PADDED_WORDS_COUNT(bits_) \ + (((ai_size)(bits_) + AI_PBITS_MASK) >> AI_PBITS_SHIFTS) + +#define AI_PBITS_GET_WORD(word_ptr_, bits_) \ + (((ai_pbits*)(word_ptr_)) + ((bits_) >> AI_PBITS_SHIFTS)) + +#define AI_PAD_CHANNELS(format_, channels_) \ + ((AI_BUFFER_FMT_GET_BITS(format_)==1) ? (AI_PBITS_PADDED_WORDS_COUNT(channels_) << AI_PBITS_SHIFTS) : (channels_)) + + +/*! ai_intq_info struct handlers *********************************************/ +#define INTQ_CONST const +// #define INTQ_CONST + +#define AI_INTQ_INFO_LIST(list_) \ + ((list_)->info) + +#define AI_INTQ_INFO_LIST_FLAGS(list_) \ + ((list_) ? (list_)->flags : 0) + +#define AI_INTQ_INFO_LIST_SIZE(list_) \ + ((list_) ? (list_)->size : 0) + +#define AI_HAS_INTQ_INFO_LIST(list_) \ + ((list_) ? (((list_)->info) && ((list_)->size>0)) : false) + +#define AI_INTQ_INFO_LIST_SCALE(list_, type_, pos_) \ + (((list_) && (list_)->info && ((pos_)<(list_)->size)) \ + ? ((type_*)((list_)->info->scale))[(pos_)] : 1.0f) + +#define AI_INTQ_INFO_LIST_ZEROPOINT(list_, type_, pos_) \ + (((list_) && (list_)->info && ((pos_)<(list_)->size)) \ + ? ((type_*)((list_)->info->zeropoint))[(pos_)] : 0) + +/*! ai_buffer format handlers ************************************************/ + +/*! + * @enum buffer format definition + * @ingroup ai_platform + * + * 32 bit signed format list. + */ +typedef int32_t ai_buffer_format; + +/*! ai_buffer_meta flags & macros ********************************************/ +#define AI_BUFFER_META_HAS_INTQ_INFO (0x1U << 0) +#define AI_BUFFER_META_FLAG_SCALE_FLOAT (0x1U << 0) +#define AI_BUFFER_META_FLAG_ZEROPOINT_U8 (0x1U << 1) +#define AI_BUFFER_META_FLAG_ZEROPOINT_S8 (0x1U << 2) +#define AI_BUFFER_META_FLAG_ZEROPOINT_U16 (0x1U << 3) +#define AI_BUFFER_META_FLAG_ZEROPOINT_S16 (0x1U << 4) + +/*! ai_buffer format variable flags & macros *********************************/ +#define AI_BUFFER_FMT_MASK (0x01FFFFFF) +#define AI_BUFFER_FMT_TYPE_NONE (0x0) +#define AI_BUFFER_FMT_TYPE_FLOAT (0x1) +#define AI_BUFFER_FMT_TYPE_Q (0x2) +#define AI_BUFFER_FMT_TYPE_BOOL (0x3) + +#define AI_BUFFER_FMT_FLAG_CONST (0x1U<<30) +#define AI_BUFFER_FMT_FLAG_STATIC (0x1U<<29) +#define AI_BUFFER_FMT_FLAG_IS_IO (0x1U<<27) +#define AI_BUFFER_FMT_FLAG_PERSISTENT (0x1U<<29) + + +#define AI_BUFFER_FMT_PACK(value_, mask_, bits_) \ + ( ((value_) & (mask_)) << (bits_) ) + +#define AI_BUFFER_FMT_UNPACK(fmt_, mask_, bits_) \ + ( (AI_BUFFER_FMT_OBJ(fmt_) >> (bits_)) & (mask_) ) + +#define AI_BUFFER_FMT_OBJ(fmt_) \ + ((ai_buffer_format)(fmt_)) + +#define AI_BUFFER_FMT_GET_FLOAT(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0x1, 24) + +#define AI_BUFFER_FMT_GET_SIGN(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0x1, 23) + +#define AI_BUFFER_FMT_GET_TYPE(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0xF, 17) + +#define AI_BUFFER_FMT_GET_BITS(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0x7F, 7) + +#define AI_BUFFER_FMT_SET_BITS(bits_) \ + AI_BUFFER_FMT_PACK((bits_), 0x7F, 7) + +#define AI_BUFFER_FMT_GET_FBITS(fmt_) \ + ( (ai_i8)AI_BUFFER_FMT_UNPACK(fmt_, 0x7F, 0) - 64 ) + +#define AI_BUFFER_FMT_SET_FBITS(fbits_) \ + AI_BUFFER_FMT_PACK((fbits_)+64, 0x7F, 0) + +#define AI_BUFFER_FMT_SET(type_id_, sign_bit_, float_bit_, bits_, fbits_) \ + AI_BUFFER_FMT_OBJ( \ + AI_BUFFER_FMT_PACK(0, 0x1, 24) | \ + AI_BUFFER_FMT_PACK(sign_bit_, 0x1, 23) | \ + AI_BUFFER_FMT_PACK(0, 0x3, 21) | \ + AI_BUFFER_FMT_PACK(type_id_, 0xF, 17) | \ + AI_BUFFER_FMT_PACK(0, 0x7, 14) | \ + AI_BUFFER_FMT_SET_BITS(bits_) | \ + AI_BUFFER_FMT_SET_FBITS(fbits_) \ + ) + +#define AI_BUFFER_FMT_SET_COMPLEX(type_id_, sign_bit_, bits_, fbits_) \ + AI_BUFFER_FMT_OBJ( \ + AI_BUFFER_FMT_PACK(1, 0x1, 24) | \ + AI_BUFFER_FMT_PACK(sign_bit_, 0x1, 23) | \ + AI_BUFFER_FMT_PACK(0, 0x3, 21) | \ + AI_BUFFER_FMT_PACK(type_id_, 0xF, 17) | \ + AI_BUFFER_FMT_PACK(0, 0x7, 14) | \ + AI_BUFFER_FMT_SET_BITS(bits_) | \ + AI_BUFFER_FMT_SET_FBITS(fbits_) \ + ) + +#define AI_BUFFER_FMT_SAME(fmt1_, fmt2_) \ + ( AI_BUFFER_FMT_GET(fmt1_) == AI_BUFFER_FMT_GET(fmt2_) ) + +#define AI_BUFFER_FMT_GET(fmt_) \ + (AI_BUFFER_FMT_OBJ(fmt_) & AI_BUFFER_FMT_MASK) + +#define AI_BUFFER_FORMAT(buf_) \ + AI_BUFFER_FMT_GET((buf_)->format) + + +/*! + * @define shape type index + * @ingroup ai_platform + * @brief positional ID for generic shapes C structs + */ +#define AI_SHAPE_EXTENSION (0x5) +#define AI_SHAPE_DEPTH (0x4) +#define AI_SHAPE_HEIGHT (0x3) +#define AI_SHAPE_WIDTH (0x2) +#define AI_SHAPE_CHANNEL (0x1) +#define AI_SHAPE_IN_CHANNEL (0x0) +#define AI_SHAPE_BATCH (0x0) +#define AI_SHAPE_TIME (0x0) + + +AI_DEPRECATED +#define AI_BUFFER_WIDTH(buf_) \ + ((buf_)->shape.data[AI_SHAPE_WIDTH]) + +AI_DEPRECATED +#define AI_BUFFER_HEIGHT(buf_) \ + ((buf_)->shape.data[AI_SHAPE_HEIGHT]) + +AI_DEPRECATED +#define AI_BUFFER_CHANNELS(buf_) \ + ((buf_)->shape.data[AI_SHAPE_CHANNEL]) + +AI_DEPRECATED +#define AI_BUFFER_N_BATCHES(buf_) \ + ((buf_)->shape.data[AI_SHAPE_BATCH]) + +#define AI_BUFFER_DATA(buf_, type_) \ + ((type_*)((buf_)->data)) + +#define AI_BUFFER_META_INFO(buf_) \ + ((buf_)->meta_info) + +#define AI_BUFFER_META_INFO_INTQ(meta_) \ + ((meta_) && ((meta_)->flags & AI_BUFFER_META_HAS_INTQ_INFO)) \ + ? ((meta_)->intq_info) : NULL + +#define AI_BUFFER_META_INFO_INTQ_GET_SIZE(meta_) \ + ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ + ? AI_INTQ_INFO_LIST_SIZE(AI_BUFFER_META_INFO_INTQ(meta_)) \ + : 0 ) + +#define AI_BUFFER_META_INFO_INTQ_GET_SCALE(meta_, pos_) \ + ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ + ? AI_INTQ_INFO_LIST_SCALE(AI_BUFFER_META_INFO_INTQ(meta_), ai_float, pos_) \ + : 0 ) + +#define AI_BUFFER_META_INFO_INTQ_GET_ZEROPOINT(meta_, pos_) \ + ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ + ? ((AI_INTQ_INFO_LIST_FLAGS(AI_BUFFER_META_INFO_INTQ(meta_))&AI_BUFFER_META_FLAG_ZEROPOINT_U8) \ + ? AI_INTQ_INFO_LIST_ZEROPOINT(AI_BUFFER_META_INFO_INTQ(meta_), ai_u8, pos_) \ + : AI_INTQ_INFO_LIST_ZEROPOINT(AI_BUFFER_META_INFO_INTQ(meta_), ai_i8, pos_) ) \ + : 0 ) + +#define AI_BUFFER_META_INFO_INIT(flags_, intq_info_) { \ + .flags = (flags_), \ + .intq_info = AI_PACK(intq_info_) \ +} + +#define AI_BUFFER_SIZE(buf_) \ + ai_buffer_get_size(buf_, true) + +#define AI_BUFFER_SIZE_UNPAD(buf_) \ + ai_buffer_get_size(buf_, false) + +#define AI_BUFFER_BYTE_SIZE(count_, fmt_) \ + ai_buffer_get_byte_size(count_, fmt_) + +#define AI_BUFFER_FLAGS(buf_) \ + ((buf_) ? (buf_)->flags : 0x0) + +#define AI_BUFFER_SHAPE_INIT(type_, size_, ...) \ +{ \ + .type = (type_), \ + .size = (size_), \ + .data = (ai_shape_dimension[]){ __VA_ARGS__ } \ +} + +#define AI_BUFFER_SHAPE_INIT_FROM_ARRAY(type_, size_, array_ptr_) \ +{ \ + .type = (type_), \ + .size = (size_), \ + .data = (ai_shape_dimension*)(array_ptr_) \ +} + +#define AI_BUFFER_SHAPE_SIZE(buf_) \ + ((buf_) ? (buf_)->shape.size : 0) + +#define AI_BUFFER_SHAPE_TYPE(buf_) \ + ((buf_) ? (buf_)->shape.type : 0) + +#if defined(HAS_AI_ASSERT) && defined(AI_ASSERT) + +#define AI_BUFFER_SET_SHAPE_ELEM(buf_, pos_, value_) { \ + AI_ASSERT(buf_) \ + (buf_)->shape.data[pos_] = (value_); \ +} + +#define AI_BUFFER_SHAPE_ELEM(buf_, pos_) \ + (((pos_)shape.data[pos_] : 0) + +#else + +#define AI_BUFFER_SET_SHAPE_ELEM(buf_, pos_, value_) { \ + (buf_)->shape.data[pos_] = (value_); \ +} + +#define AI_BUFFER_SHAPE_ELEM(buf_, pos_) \ + (buf_)->shape.data[pos_] + +#endif + + +AI_DEPRECATED +#define AI_BUFFER_OBJ_INIT(format_, h_, w_, ch_, n_batches_, data_) \ +{ .format = (ai_buffer_format)(format_), \ + .data = (ai_handle)(data_), \ + .meta_info = NULL, \ + .flags = AI_FLAG_NONE, \ + .size = (h_) * (w_) * AI_PAD_CHANNELS(format_, ch_), \ + .shape = AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, (n_batches_), (ch_), (w_), (h_)), \ +} + +/* 7.1 new macro API */ +#define AI_BUFFER_INIT(flags_, format_, shape_, size_, meta_info_, data_) \ +{ .format = (ai_buffer_format)(format_), \ + .data = (ai_handle)(data_), \ + .meta_info = (meta_info_), \ + .flags = (flags_), \ + .size = (size_), \ + .shape = AI_PACK(shape_) \ +} + +/* 7.1 new macro API */ +#define AI_BUFFER_INIT_STATIC(type_, flags_, format_, shape_, size_, meta_info_, ...) \ +{ .format = (ai_buffer_format)(format_), \ + .data = (ai_handle)((type_[]){__VA_ARGS__}), \ + .meta_info = (meta_info_), \ + .flags = (flags_), \ + .size = (size_), \ + .shape = AI_PACK(shape_) \ +} + +/*****************************************************************************/ +#define AI_NETWORK_BUFFERS_FIELD_DECLARE \ + ai_signature map_signature; /*! structure signature (required!) */ \ + ai_buffer_array map_weights; /*! info about weights array buffers (required!) */ \ + ai_buffer_array map_activations; /*! info about activations array buffers (required!) */ + +#define AI_NETWORK_PARAMS_FIELDS_DECLARE \ +union { \ + struct { \ + ai_buffer params; /*! info about params buffer(required!) */ \ + ai_buffer activations; /*! info about activations buffer (required!) */ \ + }; \ + struct { \ + AI_NETWORK_BUFFERS_FIELD_DECLARE \ + }; \ +}; + +/*****************************************************************************/ +#define AI_BUFFER_ARRAY_OBJ_INIT(flags_, size_, buffer_array_) \ +{ \ + .flags = (ai_u16)(flags_), \ + .size = (ai_u16)(size_), \ + .buffer = (ai_buffer*)(buffer_array_) \ +} + +#define AI_BUFFER_ARRAY_OBJ_INIT_STATIC(flags_, size_, ...) \ +{ \ + .flags = (ai_u16)(flags_), \ + .size = (ai_u16)(size_), \ + .buffer = (ai_buffer*)((ai_buffer[]){__VA_ARGS__}) \ +} + +#define AI_BUFFER_ARRAY_SANE(buf_array_) \ + ai_buffer_array_sane(buf_array_) + +#define AI_BUFFER_ARRAY_FLAGS(buf_array_) \ + ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? (buf_array_)->flags : AI_FLAG_NONE) + +#define AI_BUFFER_ARRAY_SIZE(buf_array_) \ + ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? (buf_array_)->size : 0) + +#define AI_BUFFER_ARRAY_ITEM(buf_array_, pos_) \ + ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? ((buf_array_)->buffer + (pos_)) : NULL) + +#define AI_BUFFER_ARRAY_ITEM_SET_ADDRESS(buf_array_, pos_, address_) \ + ai_buffer_array_item_set_address(buf_array_, pos_, address_) + + +/*! + * @enum buffer formats enum list + * @ingroup ai_platform + * + * List of supported ai_buffer format types. + */ +enum { + AI_BUFFER_FORMAT_NONE = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_NONE, 0, 0, 0, 0), + AI_BUFFER_FORMAT_FLOAT = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_FLOAT, 1, 0, 32, 0), + + AI_BUFFER_FORMAT_U1 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 1, 0), + AI_BUFFER_FORMAT_U8 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 8, 0), + AI_BUFFER_FORMAT_U16 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 16, 0), + AI_BUFFER_FORMAT_U32 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 32, 0), + + AI_BUFFER_FORMAT_S1 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 1, 0), + AI_BUFFER_FORMAT_S8 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 8, 0), + AI_BUFFER_FORMAT_S16 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 16, 0), + AI_BUFFER_FORMAT_S32 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 32, 0), + + AI_BUFFER_FORMAT_Q = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 0, 0), + AI_BUFFER_FORMAT_Q7 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 8, 7), + AI_BUFFER_FORMAT_Q15 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 16, 15), + + AI_BUFFER_FORMAT_UQ = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 0, 0), + AI_BUFFER_FORMAT_UQ7 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 8, 7), + AI_BUFFER_FORMAT_UQ15 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 16, 15), + + AI_BUFFER_FORMAT_BOOL = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_BOOL, 0, 0, 8, 0), +}; + +/*****************************************************************************/ +#define AI_ERROR_INIT(type_, code_) { \ + .type = AI_ERROR_##type_, \ + .code = AI_ERROR_CODE_##code_ \ +} + +/* printf formats */ +#define SSIZET_FMT "%" PRIu32 +#define AII32_FMT "%" PRId32 +#define AIU32_FMT "%" PRIu32 +#define AII64_FMT "%" PRId64 +#define AIU64_FMT "%" PRIu64 + + +#define AI_VERSION(major_, minor_, micro_) \ + (((major_)<<24) | ((minor_)<<16) | ((micro_)<<8)) + + +typedef uint8_t ai_custom_type_signature; + +typedef void* ai_handle; +typedef const void* ai_handle_const; + +typedef float ai_float; +typedef double ai_double; + +typedef bool ai_bool; + +typedef char ai_char; + +typedef uint32_t ai_size; +typedef int16_t ai_short_size; + +typedef uintptr_t ai_uptr; + +typedef unsigned int ai_uint; +typedef uint8_t ai_u8; +typedef uint16_t ai_u16; +typedef uint32_t ai_u32; +typedef uint64_t ai_u64; + +typedef int ai_int; +typedef int8_t ai_i8; +typedef int16_t ai_i16; +typedef int32_t ai_i32; +typedef int64_t ai_i64; + +typedef uint64_t ai_macc; + +typedef int32_t ai_pbits; + +typedef uint32_t ai_signature; + +typedef void (*ai_handle_func)(ai_handle); + +/*****************************************************************************/ +/*! + * @struct ai_error + * @ingroup ai_platform + * @brief Structure encoding details about the last error. + */ +typedef struct ai_error_ { + ai_u32 type : 8; /*!< Error type represented by @ref ai_error_type */ + ai_u32 code : 24; /*!< Error code represented by @ref ai_error_code */ +} ai_error; + +/*****************************************************************************/ +/*! + * @struct ai_intq_info + * @ingroup ai_platform + * @brief an element of the ai_intq_info_list entry. It reports an array for the + * scale and zeropoint values for each buffer. Optional flags are also present + */ +typedef struct ai_intq_info_ { + INTQ_CONST ai_float* scale; + INTQ_CONST ai_handle zeropoint; +} ai_intq_info; + +/*! + * @struct ai_intq_info_list + * @ingroup ai_platform + * @brief list reporting meta info for quantized networks integer support + * when size > 1 it means a per channel out quantization + */ +typedef struct ai_intq_info_list_ { + ai_u16 flags; /*!< optional flags to store intq info attributes */ + ai_u16 size; /*!< number of elements in the the intq_info list */ + INTQ_CONST ai_intq_info* info; /*!< pointer to an array of metainfo + * associated to the intq_info list */ +} ai_intq_info_list; + +/*****************************************************************************/ +/*! + * @struct ai_buffer_meta_info + * @ingroup ai_platform + * @brief Optional meta attributes associated with the I/O buffer. + * This datastruct is used also for network querying, where the data field may + * may be NULL. + */ +typedef struct ai_buffer_meta_info_ { + ai_u32 flags; /*!< meta info flags */ + ai_intq_info_list* intq_info; /*!< meta info related to integer format */ +} ai_buffer_meta_info; + +/*! + * @struct ai_buffer_shape + * @ingroup ai_platform + * @brief Memory buffer shape datatype definition. + */ +typedef struct ai_buffer_shape_ { + ai_u32 type : 8; /*!< shape type: reserved for compatibility */ + ai_u32 size : 24; /*!< size: shape cardinality */ + ai_shape_dimension* data; /*!< pointer to shape tuple array */ +} ai_buffer_shape; + +/*! + * @struct ai_buffer + * @ingroup ai_platform + * @brief Memory buffer storing data (optional) with a shape, size and type. + * This datastruct is used also for network querying, where the data field may + * may be NULL. + */ +typedef struct ai_buffer_ { + ai_buffer_format format; /*!< buffer format */ + ai_handle data; /*!< pointer to buffer data */ + ai_buffer_meta_info* meta_info; /*!< pointer to buffer metadata info */ + /* New 7.1 fields */ + ai_flags flags; /*!< shape optional flags */ + ai_size size; /*!< number of elements of the buffer (including optional padding) */ + ai_buffer_shape shape; /*!< n-dimensional shape info */ +} ai_buffer; + +/*! + * @struct ai_buffer_array + * @ingroup ai_platform + * @brief Array of @ref ai_buffer. + */ +typedef struct ai_buffer_array_ { + ai_u16 flags; /*!< buffer array flags */ + ai_u16 size; /*!< buffer array size */ + ai_buffer* buffer; /*!< buffer array buffers pointer */ +} ai_buffer_array; + +/* enums section */ + +/*! + * @enum ai_error_type + * @ingroup ai_platform + * + * Generic enum to list network error types. + */ +typedef enum { + AI_ERROR_NONE = 0x00, /*!< No error */ + AI_ERROR_TOOL_PLATFORM_API_MISMATCH = 0x01, + AI_ERROR_TYPES_MISMATCH = 0x02, + AI_ERROR_INVALID_HANDLE = 0x10, + AI_ERROR_INVALID_STATE = 0x11, + AI_ERROR_INVALID_INPUT = 0x12, + AI_ERROR_INVALID_OUTPUT = 0x13, + AI_ERROR_INVALID_PARAM = 0x14, + AI_ERROR_INVALID_SIGNATURE = 0x15, + AI_ERROR_INVALID_SIZE = 0x16, + AI_ERROR_INVALID_VALUE = 0x17, + AI_ERROR_INIT_FAILED = 0x30, + AI_ERROR_ALLOCATION_FAILED = 0x31, + AI_ERROR_DEALLOCATION_FAILED = 0x32, + AI_ERROR_CREATE_FAILED = 0x33, +} ai_error_type; + +/*! + * @enum ai_error_code + * @ingroup ai_platform + * + * Generic enum to list network error codes. + */ +typedef enum { + AI_ERROR_CODE_NONE = 0x0000, /*!< No error */ + AI_ERROR_CODE_NETWORK = 0x0010, + AI_ERROR_CODE_NETWORK_PARAMS = 0x0011, + AI_ERROR_CODE_NETWORK_WEIGHTS = 0x0012, + AI_ERROR_CODE_NETWORK_ACTIVATIONS = 0x0013, + AI_ERROR_CODE_LAYER = 0x0014, + AI_ERROR_CODE_TENSOR = 0x0015, + AI_ERROR_CODE_ARRAY = 0x0016, + AI_ERROR_CODE_INVALID_PTR = 0x0017, + AI_ERROR_CODE_INVALID_SIZE = 0x0018, + AI_ERROR_CODE_INVALID_FORMAT = 0x0019, + AI_ERROR_CODE_OUT_OF_RANGE = 0x0020, + AI_ERROR_CODE_INVALID_BATCH = 0x0021, + AI_ERROR_CODE_MISSED_INIT = 0x0030, + AI_ERROR_CODE_IN_USE = 0x0040, + AI_ERROR_CODE_LOCK = 0x0041, +} ai_error_code; + +/*! + * @struct ai_platform_version + * @ingroup ai_platform + * @brief Datastruct storing platform version info + */ +typedef struct ai_platform_version_ { + ai_u8 major; + ai_u8 minor; + ai_u8 micro; + ai_u8 reserved; +} ai_platform_version; + +/*! + * @struct ai_network_params + * @ingroup ai_platform + * + * Datastructure to pass parameters during network initialization. + */ +typedef struct ai_network_params_ { + AI_NETWORK_PARAMS_FIELDS_DECLARE +} ai_network_params; + +/*! + * @struct ai_network_buffers + * @ingroup ai_platform + * + * Datastructure to pass network buffers during network initialization. + */ +typedef struct ai_network_buffers_ { + AI_NETWORK_BUFFERS_FIELD_DECLARE +} ai_network_buffers; + +/*! + * @struct ai_network_report + * @ingroup ai_platform + * + * Datastructure to query a network report with some relevant network detail. + */ +typedef struct ai_network_report_ { + const char* model_name; + const char* model_signature; + const char* model_datetime; + + const char* compile_datetime; + + const char* runtime_revision; + ai_platform_version runtime_version; + + const char* tool_revision; + ai_platform_version tool_version; + ai_platform_version tool_api_version; + + ai_platform_version api_version; + ai_platform_version interface_api_version; + + ai_macc n_macc; + + ai_u16 n_inputs; + ai_u16 n_outputs; + ai_buffer* inputs; + ai_buffer* outputs; + + AI_NETWORK_PARAMS_FIELDS_DECLARE + + ai_u32 n_nodes; + + ai_signature signature; +} ai_network_report; + +/*! + * @enum ai_scatter_nd_reduction + * @ingroup ai_platform + * @brief reduction operation in scatter_nd layer + */ +typedef enum { + AI_SCATTER_ND_NONE = 0x0, + AI_SCATTER_ND_OPERATION +} ai_scatter_nd_reduction; + +/*! + * @enum ai_upsample_mode + * @ingroup ai_platform + * @brief allowed mode in upsample layer + */ +typedef enum { + AI_UPSAMPLE_ZEROS = 0x0, + AI_UPSAMPLE_NEAREST, + AI_UPSAMPLE_BILINEAR, + AI_UPSAMPLE_TRILINEAR +} ai_upsample_mode; + +/*! + * @enum ai_resize_mode + * @ingroup ai_platform + * @brief allowed mode in resize layer + */ +typedef enum { + AI_RESIZE_ZEROS = 0x0, + AI_RESIZE_NEAREST, + AI_RESIZE_LINEAR, + AI_RESIZE_CUBIC +} ai_resize_mode; + +/*! + * @enum ai_coord_transf_mode + * @ingroup ai_platform + * @brief coordinate_transformation_mode in resize layer + */ +typedef enum { + AI_HALF_PIXEL = 0x0, + AI_PYTORCH_HALF_PIXEL, + AI_ALIGN_CORNERS, + AI_ASYMMETRIC, + AI_TF_HALF_PIXEL_FOR_NN, + AI_TF_CROP_AND_RESIZE +} ai_coord_transf_mode; + +typedef enum { + AI_ROUND_PREFER_FLOOR = 0x0, + AI_ROUND_PREFER_CEIL, + AI_ROUND_FLOOR, + AI_ROUND_CEIL +} ai_nearest_mode; + +typedef enum { + AI_PAD_CONSTANT = 0x0, + AI_PAD_REFLECT, + AI_PAD_EDGE, + AI_PAD_8BIT_CH1ST_CONSTANT, +} ai_pad_mode; + +#define OUTPUT_PADDING_FLAG (1 << 0) +#define CHANNEL_FIRST_FLAG (1 << 1) +/* Padding pattern supported: */ +/* 0 = (1, 1, 1,1), 1 = (0, 0, 2, 2) */ +#define CHANNEL_PADDING_PATTERN (1 << 2) +/* Carefull when changing those definitions + bit0 shall always select output padding (Valid vs Same) + bit1 shall always select Channel first /channel lst format + bit2 shall always select padding pattern (1, 1, 1, 1) (stride1) or (0, 0, 2, 2) (stride2) +*/ +typedef enum { + AI_LAYER_FORMAT_CHANNEL_LAST_VALID = 0x0, + AI_LAYER_FORMAT_CHANNEL_LAST_SAME = 0x1, + AI_LAYER_FORMAT_CHANNEL_FIRST_VALID = 0x2, + AI_LAYER_FORMAT_CHANNEL_FIRST_SAME = 0x3, + AI_LAYER_FORMAT_CHANNEL_FIRST_SAME2 = 0x7, +} ai_layer_format_type; + +/*! ai_platform public APIs **************************************************/ + +/*! + * @brief get the total number of elements of an ai_buffer. + * @ingroup ai_platform + * @param buffer a pointer to an @ref ai_buffer + * @param with_padding when true it considers also padded elements + * @return the number of elements of the buffer (with/without padded ones) + */ +AI_API_ENTRY +ai_size ai_buffer_get_size(const ai_buffer* buffer, const ai_bool with_padding); + +/*! + * @brief get the size in bytes of an ai_buffer (given the number of elements and format). + * @ingroup ai_platform + * @param count the number of elements composing the buffer + * @param fmt the format of the ai_buffer + * @return the size in bytes of the buffer + */ +AI_API_ENTRY +ai_size ai_buffer_get_byte_size(const ai_size count, const ai_buffer_format fmt); + +/*! + * @brief get total size in bytes of a buffer array. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return the total size in bytes of all the buffer arrays + */ +AI_API_ENTRY +ai_bool ai_buffer_array_is_empty(const ai_buffer_array* barray); + +/*! + * @brief get total size in bytes of a buffer array. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return the total size in bytes of all the buffer arrays + */ +AI_API_ENTRY +ai_bool ai_buffer_array_is_valid(const ai_buffer_array* barray); + +/*! + * @brief check if a buffer array is valid - i.e. not empty. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return true if the array is consistent and not empty, false otherwise + */ +AI_API_ENTRY +ai_bool ai_buffer_array_sane(const ai_buffer_array* barray); + +/*! + * @brief get total size in bytes of a buffer array. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return the total size in bytes of all the buffer arrays + */ +AI_API_ENTRY +ai_size ai_buffer_array_get_byte_size(const ai_buffer_array* barray); + +/*! + * @brief set the address of buffer array item @pos + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @param pos the index of the element in the array + * @param address the address to set + * @return true if successful, false otherwise + */ +AI_API_ENTRY +ai_bool ai_buffer_array_item_set_address( + ai_buffer_array* barray, const ai_u32 pos, ai_handle address); + +AI_API_DECLARE_END + +#endif /*AI_PLATFORM_H*/ diff --git a/lib/stai/libstai/include/ai_platform_interface.h b/lib/stai/libstai/include/ai_platform_interface.h new file mode 100644 index 000000000..369e42531 --- /dev/null +++ b/lib/stai/libstai/include/ai_platform_interface.h @@ -0,0 +1,1144 @@ +/** + ****************************************************************************** + * @file ai_platform_interface.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform interface APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_PLATFORM_INTERFACE_H +#define AI_PLATFORM_INTERFACE_H + +#include "ai_platform.h" +#include "datatypes_network.h" +#include "ai_datatypes.h" +#include "ai_datatypes_defines.h" +#include "ai_datatypes_format.h" + +#include "stai.h" + +/*****************************************************************************/ +#define AI_INTERFACE_TYPE /* AI_INTERFACE_TYPE */ + + +/*****************************************************************************/ +/*! + * @defgroup datatypes_interface Interface Datatypes + * @brief Data structures and defines used to implement neural networks + */ + +#define AI_MAGIC_LEGACY_TOKEN (0xA1C00103) + +#define AI_MAGIC_CONTEXT_TOKEN (0xA1C00100) /*!< Network Context Magic Token */ + +#define AI_MAGIC_INSPECTOR_TOKEN (0xB1C00100) /*!< Inspector Magic Token */ + + +/*****************************************************************************/ +#define AI_ERROR_TRAP(net_, type_, code_) \ + ai_platform_network_set_error(AI_CONTEXT_OBJ(net_), AI_CONCAT(AI_ERROR_,type_), \ + AI_CONCAT(AI_ERROR_CODE_,code_)) + +/*! AI_PTR HANDLERS SECTION ************************************/ + +#define AI_PTR(ptr_) AI_CAST(ai_ptr, ptr_) +#define AI_PTR_CONST(ptr_) AI_CAST(ai_ptr_const, ptr_) + +/*! STATIC ARRAYS ALLOCATOR SECTION ************************************/ +#define AI_PACK_STORAGE_ARRAY(type_, dim_, ...) \ + (type_[dim_]) { AI_PACK(__VA_ARGS__) } + +/*! AI_STORAGE_KLASS SECTION ************************************/ +#define AI_STORAGE_KLASS_PACK(type_, dim_, ...) \ + AI_PACK_STORAGE_ARRAY(type_, dim_, __VA_ARGS__) + +#define AI_STORAGE_KLASS_INIT(type_, size_, data_) \ +{ \ + .type = (type_), \ + .size = (size_), \ + .data = (ai_handle)(data_), \ +} + +/*! + * @enum ai_storage_klass_type + * @ingroup ai_platform_interface + * @brief @ref ai_storage_class types enum + */ +typedef enum { + AI_STORAGE_KLASS_NONE = 0x00, + AI_STORAGE_KLASS_SHAPE = 0x01, + AI_STORAGE_KLASS_STRIDE = 0x02, +} ai_storage_klass_type; + +/*! + * @struct ai_storage_klass + * @ingroup ai_platform_interface + * @brief Generic "Template" klass for generic storage arrays containers + * from this klass several typed containers are derived (see e.g. @ref ai_shape) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_storage_klass_s { + ai_u32 type : 8; + ai_u32 size : 24; + ai_handle data; +} ai_storage_klass; +AI_PACKED_STRUCT_END + +/*! AI_SHAPES SECTION ************************************/ +#define AI_SHAPE_MAX_DIMENSION (6) + + +#define AI_SHAPE_2D_INIT(w_, h_) \ + { .data = { (w_), (h_) } } + +#define AI_SHAPE_INIT(dim_, ...) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_SHAPE, \ + dim_, \ + AI_STORAGE_KLASS_PACK(ai_shape_dimension, dim_, ## __VA_ARGS__)) + +#define AI_SHAPE_INIT_FROM_BUFFER(dim_, buffer_) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_SHAPE, \ + dim_, \ + buffer_) + +#define AI_SHAPE_ALLOCATE_STATIC(num_dim_) \ + AI_SHAPE_INIT((num_dim_), 0) + + +typedef ai_u8 ai_shape_idx; + +/*! + * @struct ai_shape + * @ingroup ai_platform_interface + * @brief Dimensions for generic 4D tensors + */ +typedef ai_storage_klass ai_shape; + + +/*! AI_STRIDES HANDLERS SECTION ************************************/ +#define AI_STRIDE_INIT(dim_, ...) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_STRIDE, \ + dim_, \ + AI_STORAGE_KLASS_PACK(ai_stride_dimension, dim_, ## __VA_ARGS__)) + + +#define AI_STRIDE_INIT_FROM_BUFFER(dim_, buffer_) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_STRIDE, \ + dim_, \ + buffer_) + +#define AI_STRIDE_ALLOCATE_STATIC(num_dims_) \ + AI_STRIDE_INIT((num_dims_), 0) + + +/*! + * @struct ai_stride + * @ingroup ai_platform_interface + * @brief Stride dimensions for generic 4D tensors (in number of elements) + */ +typedef ai_storage_klass ai_stride; + +/*! BASIC_TYPES HANDLERS SECTION ************************************/ +#define AI_SIZE(value_) \ + AI_CAST(ai_size, value_) + +/*! AI_KLASS_OBJ HANDLERS SECTION ************************************/ +#define AI_KLASS_OBJ(obj_) \ + AI_CAST(ai_klass_obj, obj_) + +/*! GENERIC HANDLERS SECTION ************************************/ +#define AI_OBJ_DATA(obj_, type_) \ + AI_CAST(type_, (obj_)->data) + +/*! AI_BUFFER HANDLERS SECTION ************************************/ +#define AI_BUFFER_OBJ(ptr_) \ + AI_CAST(ai_buffer*, ptr_) + +/*! AI_ARRAY HANDLERS SECTION ************************************/ +#define AI_ARRAY_OBJ(ptr_) \ + AI_CAST(ai_array*, ptr_) + +#define AI_ARRAY_OBJ_INIT_STATIC(type_, format_, size_, ...) { \ + .format = AI_FMT_OBJ(format_), \ + .size = (ai_array_size)(size_), \ + .data = (ai_ptr)((type_[]){ __VA_ARGS__ }), \ + .data_start = AI_PTR(0), \ +} + +#define AI_ARRAY_OBJ_INIT(format_, data_, data_start_, size_) { \ + .format = AI_FMT_OBJ(format_), \ + .size = AI_CAST(ai_array_size, size_), \ + .data = AI_PTR(data_), \ + .data_start = AI_PTR(data_start_) } + +#define AI_ARRAY_OBJ_DECLARE_STATIC(name_, type_, format_, attr_, size_, ...) \ + AI_ALIGNED(4) \ + attr_ ai_array name_ = AI_ARRAY_OBJ_INIT_STATIC(type_, format_, size_, __VA_ARGS__); + + +#define AI_ARRAY_OBJ_DECLARE(name_, format_, data_, data_start_, size_, attr_) \ + AI_ALIGNED(4) \ + attr_ ai_array name_ = AI_ARRAY_OBJ_INIT(format_, data_, data_start_, size_); + + +/********************************* ai_array macros ***************************/ +#define AI_PACK_ARRAYS(...) \ + (ai_array[]) { AI_PACK(__VA_ARGS__) } + +#define AI_ARRAY_LIST_OBJ_INIT(arrays_ptr_) \ + ((ai_array*)(arrays_ptr_)) + +#define AI_ARRAY_LIST_FLAGS(list_) \ + ((list_) ? (list_)->flags : 0x0) + +#define AI_ARRAY_LIST_SIZE(list_) \ + ((list_) ? (list_)->size : 0) + +#define AI_ARRAY_LIST_DATA(list_, pos_) \ + ((list_) ? &((list_)->data[pos_]) : NULL) + + +/********************************* ai_tensor macros **************************/ +#define AI_TENSOR_OBJ(obj_) \ + AI_CAST(ai_tensor*, obj_) + +#define AI_TENSOR_INFO_OBJ_INIT(id_, flags_, data_size_) { \ + .id = (id_), \ + .flags = (flags_), \ + .data_size = (data_size_) \ +} + +#define AI_TENSOR_OBJ_INIT(id_, flags_, shape_, stride_, arrays_size_, arrays_ptr_, klass_obj_) { \ + .klass = (ai_klass_obj)(klass_obj_), \ + .info = AI_TENSOR_INFO_OBJ_INIT(id_, flags_, arrays_size_), \ + .shape = shape_, \ + .stride = stride_, \ + .data = AI_ARRAY_LIST_OBJ_INIT(AI_PACK(arrays_ptr_)), \ +} + +#define AI_TENSOR_OBJ_DECLARE(name_, attr_, id_, flags_, shape_, stride_, \ + arrays_size_, arrays_ptr_, klass_obj_) \ + AI_ALIGNED(4) \ + attr_ ai_tensor name_ = AI_TENSOR_OBJ_INIT(id_, flags_, AI_PACK(shape_), AI_PACK(stride_), \ + arrays_size_, AI_PACK(arrays_ptr_), AI_PACK(klass_obj_)); + + +/********************************* TENSOR STATE MACROS ***********************/ +#define AI_TENSOR_STATE_OBJ_INIT(end_ptr_ , curr_ptr_, stride_, size_) \ + { (end_ptr_), (curr_ptr_), (stride_), (size_) } + +/********************************* TENSOR LIST MACROS ************************/ +#if (AI_TOOLS_API_VERSION <= AI_TOOLS_API_VERSION_1_3) +#pragma message ("Including deprecated AI_TENSOR_LIST_ENTRY, AI_TENSOR_LIST_EMPTY, AI_TENSOR_LIST_IO_ENTRY") + +AI_DEPRECATED +#define AI_TENSOR_LIST_EMPTY \ + AI_TENSOR_LIST_OBJ_EMPTY + +AI_DEPRECATED +#define AI_TENSOR_LIST_ENTRY(...) \ + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, AI_NUMARGS(__VA_ARGS__), __VA_ARGS__) + +AI_DEPRECATED +#define AI_TENSOR_LIST_IO_ENTRY(flags_, size_, ...) \ + AI_TENSOR_LIST_IO_OBJ_INIT(flags_, size_, __VA_ARGS__) + +#endif /* AI_TOOLS_API_VERSION_1_3 */ + +#define AI_TENSOR_LIST_OBJ_INIT(flags_, size_, ...) \ + { .size = (size_), .flags = (flags_), \ + .tensor = (ai_tensor*[]) { __VA_ARGS__ }, .info = NULL \ + } + +#define AI_TENSOR_LIST_OBJ_EMPTY \ + { .size = 0, .flags = AI_FLAG_NONE, \ + .tensor = (ai_tensor*[]) { NULL }, .info = NULL \ + } + +#define AI_TENSOR_LIST_OBJ_DECLARE(name_, attr_, flags_, size_, ...) \ + AI_ALIGNED(4) \ + attr_ ai_tensor_list name_ = AI_TENSOR_LIST_OBJ_INIT( \ + flags_, size_, __VA_ARGS__); + +/********************************* TENSOR LIST I/O MACROS ********************/ + +#define AI_TENSOR_LIST_IO_OBJ_INIT(flags_, size_, ...) \ + { .size = (size_), .flags = (flags_), \ + .tensor = (ai_tensor*[]) { __VA_ARGS__ }, \ + .info = (ai_tensor_list_info[1]) { { \ + .buffer = (ai_buffer[size_]){AI_STRUCT_INIT}, \ + .state = (ai_tensor_state[size_]){AI_STRUCT_INIT}, \ + .meta = (ai_buffer_meta_info[size_]){AI_STRUCT_INIT} \ + } } \ + } + +/********************************* TENSOR CHAIN MACROS ***********************/ +#define AI_TENSOR_CHAIN_OBJ_INIT(flags_, size_, ...) \ + { .size = (size_), .flags = (flags_), \ + .chain = (ai_tensor_list[]){ __VA_ARGS__ } } + +#define AI_TENSOR_CHAIN_OBJ_DECLARE(name_, attr_, size_, ...) \ + AI_ALIGNED(4) \ + attr_ ai_tensor_chain name_ = \ + AI_TENSOR_CHAIN_OBJ_INIT(AI_FLAG_NONE, size_, __VA_ARGS__); + + +/********************************* TENSOR CHAIN I/O MACROS *******************/ +#define AI_TENSOR_CHAIN_IO_OBJ_INIT(flags_, in_tensor_list_, out_tensor_list_) \ + { .chain = (ai_tensor_list[]){ in_tensor_list_, out_tensor_list_ }, \ + .size = 2, .flags = (flags_) } + +#define AI_TENSOR_CHAIN_IO_OBJ_DECLARE( \ + name_, attr_, flags_, in_tensor_list_, out_tensor_list_) \ + AI_ALIGNED(4) \ + attr_ ai_tensor_chain_io name_ = \ + AI_TENSOR_CHAIN_IO_OBJ_INIT(flags_, in_tensor_list_, out_tensor_list_); + +/******************************* NETWORK SECTION ****************************/ +#define AI_NETWORK_OBJ(obj_) \ + ((ai_network*)(obj_)) + + +#if (AI_TOOLS_API_VERSION < AI_TOOLS_API_VERSION_1_5) + +AI_DEPRECATED +#define AI_NETWORK_OBJ_INIT( \ + weights_buffer_, activations_buffer_, \ + in_tensor_list_ptr_, out_tensor_list_ptr_, \ + in_node_ptr_, signature_, klass_obj_) { \ + .magic = AI_MAGIC_CONTEXT_TOKEN, \ + .signature = signature_, \ + .tool_api_version = 0x0, \ + .error = AI_ERROR_INIT(NONE, NONE), \ + .flags = AI_FLAG_NONE, \ + .klass = AI_KLASS_OBJ(klass_obj_), \ + .n_batches = 0, \ + .batch_id = 0, \ + .buffers = AI_NETWORK_BUFFERS_INIT( \ + AI_BUFFER_ARRAY_OBJ_INIT_STATIC(AI_FLAG_NONE, 1, AI_PACK(weights_buffer_)), \ + AI_BUFFER_ARRAY_OBJ_INIT_STATIC(AI_FLAG_NONE, 1, AI_PACK(activations_buffer_))), \ + .tensors = AI_TENSOR_CHAIN_IO_OBJ_INIT(AI_FLAG_NONE, \ + AI_PACK(in_tensor_list_ptr_), \ + AI_PACK(out_tensor_list_ptr_)), \ + .input_node = AI_NODE_OBJ(in_node_ptr_), \ + .current_node = AI_NODE_OBJ(NULL), \ + .on_node_exec = NULL, \ + .data_exec = NULL, \ + .lite_cb = NULL, \ +} + +#else + +#define AI_NETWORK_OBJ_INIT( \ + weights_buffer_, activations_buffer_, \ + in_tensor_list_ptr_, out_tensor_list_ptr_, \ + in_node_ptr_, signature_, klass_obj_) { \ + .magic = AI_MAGIC_CONTEXT_TOKEN, \ + .signature = signature_, \ + .tool_api_version = 0x0, \ + .error = AI_ERROR_INIT(NONE, NONE), \ + .klass = AI_KLASS_OBJ(klass_obj_), \ + .flags = AI_FLAG_NONE, \ + .n_batches = 0, \ + .batch_id = 0, \ + .buffers = AI_NETWORK_BUFFERS_INIT(AI_PACK(weights_buffer_), \ + AI_PACK(activations_buffer_)), \ + .tensors = AI_TENSOR_CHAIN_IO_OBJ_INIT(AI_FLAG_NONE, \ + AI_PACK(in_tensor_list_ptr_), \ + AI_PACK(out_tensor_list_ptr_)), \ + .input_node = AI_NODE_OBJ(in_node_ptr_), \ + .current_node = AI_NODE_OBJ(NULL), \ + .on_node_exec = NULL, \ + .data_exec = NULL, \ + .lite_cb = NULL, \ +} + +#endif // AI_TOOLS_API_VERSION + + +#define AI_NETWORK_OBJ_DECLARE( \ + name_, attr_, \ + weights_buffer_, activations_buffer_, \ + in_tensor_list_ptr_, out_tensor_list_ptr_, \ + in_node_ptr_, signature_, klass_obj_) \ + AI_ALIGNED(4) \ + attr_ ai_network name_ = AI_NETWORK_OBJ_INIT( \ + AI_PACK(weights_buffer_), \ + AI_PACK(activations_buffer_), \ + AI_PACK(in_tensor_list_ptr_), \ + AI_PACK(out_tensor_list_ptr_), \ + (in_node_ptr_), (signature_), (klass_obj_)); + +#define AI_NETWORK_ACQUIRE_CTX(handle_) \ + AI_NETWORK_OBJ(ai_platform_context_acquire(handle_)) + +/******************************************************************************/ +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_version + * @ingroup ai_platform_interface + * @brief Packed representation for @ref ai_platform_version + */ +typedef uint32_t ai_version; + +/*! + * @typedef ai_klass_obj + * @ingroup ai_platform_interface + * @brief handler to (private) generic subclass derivatives implementation + */ +typedef void* ai_klass_obj; + +/*! + * @typedef ai_ptr + * @ingroup ai_platform_interface + * @brief Byte pointer data addressing + */ +typedef uint8_t* ai_ptr; + +/*! + * @typedef ai_ptr_const + * @ingroup ai_platform_interface + * @brief Constant byte pointer data addressing + */ +typedef const uint8_t* ai_ptr_const; + +/*! + * @typedef ai_ptr_offset + * @ingroup ai_platform_interface + * @brief byte offset for computing strides + */ +typedef int32_t ai_ptr_offset; + +/*! + * @typedef ai_magic + * @ingroup ai_platform_interface + * @brief magic field to mark internal datatstructures + */ +typedef uint32_t ai_magic; + +/*! + * @typedef ai_complex_f64 + * @ingroup ai_platform_interface + * @brief Definition of float complex number (i.e. two 32bits numbers) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + ai_float real; + ai_float imag; +} ai_complex_f64; +AI_PACKED_STRUCT_END + +/*! + * @typedef ai_complex_s64 + * @ingroup ai_platform_interface + * @brief Definition of signed integer complex number (i.e. two 32bits numbers) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + ai_i32 real; + ai_i32 imag; +} ai_complex_s64; +AI_PACKED_STRUCT_END + +/*! + * @typedef ai_complex_s32 + * @ingroup ai_platform_interface + * @brief Definition of signed integer complex number (i.e. two 16bits numbers) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + ai_i16 real; + ai_i16 imag; +} ai_complex_s32; +AI_PACKED_STRUCT_END + +/*! + * @typedef ai_complex_s16 + * @ingroup ai_platform_interface + * @brief Definition of signed integer complex number (i.e. two 8bits numbers) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + ai_i8 real; + ai_i8 imag; +} ai_complex_s16; +AI_PACKED_STRUCT_END + +/*! + * @typedef ai_any_ptr + * @ingroup ai_platform_interface + * @brief union for defining any pointer + */ +typedef union { + ai_handle handle; + ai_ptr ptr; + ai_float* float32; + ai_double* float64; + ai_u8* u8; + ai_i8* s8; + ai_u16* u16; + ai_i16* s16; + ai_u32* u32; + ai_i32* s32; + ai_u64* u64; + ai_i64* s64; + ai_complex_s16* complexs16; + ai_complex_s32* complexs32; + ai_complex_s64* complexs64; + ai_complex_f64* complexfloat64; +} ai_any_ptr; + +#define AI_ANY_PTR_INIT(ptr_) \ + { .handle = (ai_handle)(ptr_) } + +#define AI_CONTEXT_FIELDS \ + ai_magic magic; /*!< magic word to mark valid contexts datastructs*/ \ + ai_signature signature; /*!< 32bit signature for network consistency checks */ \ + ai_version tool_api_version; /*! Tools Codegen API version */ \ + ai_error error; /*!< track 1st error code in the network */ \ + ai_flags flags; /*!< bitflags mask to track some network state info */ + +#define AI_CONTEXT_OBJ(obj) ((ai_context*)(obj)) + +/*! + * @typedef ai_context + * @ingroup ai_platform_interface + * @brief Abstract internal context header exposed to codegen interface + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + AI_CONTEXT_FIELDS +} ai_context; +AI_PACKED_STRUCT_END + +/*! + * @enum ai_shape_2d_type + * @ingroup ai_platform_interface + * @brief Codes for the 2D tensor dimensions + */ +typedef enum { + AI_SHAPE_2D_MAX_DIMENSION = 0x2, + AI_SHAPE_2D_HEIGHT = 0x1, + AI_SHAPE_2D_WIDTH = 0x0, +} ai_shape_2d_type; + + +/*! + * @struct ai_shape_2d + * @ingroup ai_platform_interface + * @brief Dimensions for generic 2D tensors + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_shape_2d_s { + ai_shape_dimension data[AI_SHAPE_2D_MAX_DIMENSION]; /*!< 2D tensor dimensions */ +} ai_shape_2d; +AI_PACKED_STRUCT_END + + +/*! + * @struct ai_array + * @ingroup ai_platform_interface + * @brief Generic flattened array with size + * and (byte) stride of each item + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_array_s { + ai_array_format format; /*!< array format (see @ref ai_array_format) */ + ai_array_size size; /*!< number of elements in the array (NOT number + of bytes!). The size of the array could be + determine using @ref AI_ARRAY_GET_BYTE_SIZE + macro */ + ai_ptr data; /*!< pointer to data */ + ai_ptr data_start; /*!< pointer to parent's data start address */ +} ai_array; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor_info + * @ingroup ai_platform_interface + * @brief ai_tensor_info info structure for storing size of the array list, + * tensor dimensionality, etc. + * + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_info_s { + ai_u16 id; + ai_u8 flags; + ai_u8 data_size; +} ai_tensor_info; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor + * @ingroup ai_platform_interface + * @brief Generic tensor structure for storing parameters and activations + * + * The data is stored in a flattened array with an implicit order given by the + * reverse order in @ref ai_shape_dimension: + * in_channels, channels, width, height. + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_s { + ai_klass_obj klass; /*!< opaque pointer to klass context */ + ai_tensor_info info; /*!< tensor info metadata see @ref ai_tensor_info)*/ + ai_shape shape; /*!< tensor shape see @ref ai_shape */ + ai_stride stride; /*!< tensor stride see @ref ai_stride */ + ai_array* data; /*!< flattened array pointer to tensor data */ +} ai_tensor; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor_state + * @ingroup ai_platform_interface + * @brief state context for tensor management (used for I/O network tensors) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_state_s { + ai_ptr end_ptr; /*!< end address of the I/O tensor data buffer */ + ai_ptr curr_ptr; /*!< current address of the I/O tensor data buffer (for batching) */ + ai_ptr_offset stride; /*!< single batch buffer size (in bytes) */ + ai_size size; /*!< total size in bytes of the I/O tensor buffer */ +} ai_tensor_state; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor_list_info + * @ingroup ai_platform_interface + * @brief info metadata for tensor list management (used for I/O network tensors) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_list_info_s { + ai_tensor_state* state; /*!< I/O buffer internal pointers state */ + ai_buffer* buffer; /*!< I/O buffer pointer */ + ai_buffer_meta_info* meta; /*!< I/O buffer meta informations */ +} ai_tensor_list_info; +AI_PACKED_STRUCT_END + +/********************************* INTEGER QUANTIZATION DATATYPES ************/ + +#define AI_INTQ_INFO_OBJ_INIT(flags_, scale_ , zeropoint_) { \ + .scale = (scale_), \ + .zeropoint = (ai_handle)(zeropoint_), \ + .flags = (flags_), \ +} + + +#define AI_PACK_INTQ_INFO_LIST(...) \ + (ai_intq_info_list[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_INTQ_INFO(scale_, zp_) \ + (INTQ_CONST ai_intq_info[1]) { { \ + .scale = (INTQ_CONST ai_float*) AI_PACK(scale_), \ + .zeropoint = (ai_handle) AI_PACK(zp_) \ + } } + +#define AI_PACK_INTQ_SCALE(...) \ + (INTQ_CONST ai_float[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_INTQ_ZP(...) \ + (INTQ_CONST ai_i8[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_UINTQ_ZP(...) \ + (INTQ_CONST ai_u8[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_INTQ_ZP16(...) \ + (INTQ_CONST ai_i16[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_UINTQ_ZP16(...) \ + (INTQ_CONST ai_u16[]) { AI_PACK(__VA_ARGS__) } + +#define AI_INTQ_INFO_LIST_OBJ_INIT(flags_, size_, info_) \ +{ \ + .flags = (flags_), \ + .size = (size_), \ + .info = (info_), \ +} + +#define AI_INTQ_INFO_LIST_OBJ_EMPTY { 0 } + +#define AI_INTQ_INFO_LIST_OBJ_DECLARE(name_, attr_, flags_, size_, info_) \ + AI_ALIGNED(4) \ + attr_ ai_intq_info_list name_ = \ + AI_INTQ_INFO_LIST_OBJ_INIT(flags_, size_, AI_PACK(info_)); + +#define AI_INTQ_INFO_LIST_OBJ_DECLARE_EMPTY(name_, attr_) \ + AI_ALIGNED(4) \ + attr_ ai_intq_info_list name_ = AI_INTQ_INFO_LIST_OBJ_EMPTY; + +/********************************* TENSOR CHAINS DATATYPES *******************/ +/*! + * @enum ai_tensor_chain_type + * @ingroup ai_platform_interface + * @brief Enum for the different tensor chains supported in the library + */ +typedef enum { + AI_TENSOR_CHAIN_INPUT = 0x0, + AI_TENSOR_CHAIN_OUTPUT = 0x1, + AI_TENSOR_CHAIN_WEIGHTS = 0x2, + AI_TENSOR_CHAIN_SCRATCH = 0x3, + AI_TENSOR_CHAIN_SIZE +} ai_tensor_chain_type; + +/*! + * @struct ai_tensor_list + * @ingroup ai_platform_interface + * @brief list (in form of arrays) of internal nodes tensor pointers + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_list_s { + ai_u16 size; /*!< number of elements in the the tensor list */ + ai_u16 flags; /*!< optional flags to store tensor list attributes */ + ai_tensor** tensor; /*!< array of linked tensor pointer */ + ai_tensor_list_info* info; /*!< pointer to an array of metainfo associated to the tensors */ +} ai_tensor_list; +AI_PACKED_STRUCT_END + + +/*! + * @struct ai_tensor_chain + * @ingroup ai_platform_interface + * @brief tensor chain datastruct for internal network nodes + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_chain_s { + ai_u16 size; + ai_u16 flags; + ai_tensor_list* chain; /*!< pointer to a 4 sized array see @ref ai_tensor_chain_type */ +} ai_tensor_chain; +AI_PACKED_STRUCT_END + +/************************************** LAYER DATATYPES *******************/ + +/*! + * @struct ai_layer + * @ingroup ai_platform_interface + * @brief Structure encoding a generic opaque layer in the network + * + */ +typedef void ai_layer; + + +/************************************** OBSERVER DATATYPES *******************/ + +/* forward function */ +struct ai_node_s; + +/*! + * @struct ai_observer_node + * @ingroup ai_observer_interface + * @brief observer node data struct for internal network nodes + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_observer_node_s { + ai_u16 c_idx; /*!< node index (position in the execution list) */ + ai_u16 type; /*!< node type info @see ai_node datastruct */ + ai_u16 id; /*!< node id assigned by codegen tool to identify the model layer*/ + ai_u16 unused; /*!< unused field for alignment */ + const ai_tensor_chain* inner_tensors; /*!< pointer to the inner tensor if available */ + const ai_tensor_chain* tensors; /*!< pointer to a 4 sized array see @ref ai_tensor_chain_type */ +} ai_observer_node; +AI_PACKED_STRUCT_END + +#define AI_OBSERVER_NONE_EVT (0) /*!< No event */ +#define AI_OBSERVER_INIT_EVT (1 << 0) /*!< called at the end of the init function */ +#define AI_OBSERVER_PRE_EVT (1 << 1) /*!< before c-node execution */ +#define AI_OBSERVER_POST_EVT (1 << 2) /*!< after c-node execution */ + +#define AI_OBSERVER_FIRST_EVT (1 << 8) /*!< indicate the first c-node */ +#define AI_OBSERVER_LAST_EVT (1 << 9) /*!< indicate the last c-node */ + +#define AI_OBSERVER_REGISTERED (1 << 24) /*!< internal flag */ + +#define AI_OBSERVER_MASK_EVT (0xFF) /*!< mask for requested user event */ + +/* Client callback definition */ +typedef ai_u32 (*ai_observer_node_cb)( + const ai_handle cookie, + const ai_u32 flags, + const ai_observer_node *node); + +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_observer_exec_ctx_s { + ai_observer_node_cb on_node; /*!< registered user observer call-back function */ + ai_handle cookie; /*!< reference of the user context */ + ai_u32 flags; /*!< flags definition */ + ai_u16 c_idx; /*!< store/indicate the index of the current c_node */ + ai_u16 n_nodes; /*!< total number of c_node */ + struct ai_node_s *cur; /*!< pointer of the current node (pre or post) */ +} ai_observer_exec_ctx; +AI_PACKED_STRUCT_END + +typedef enum { + AI_NODE_EXEC_INIT = 0x0, + AI_NODE_EXEC_START = 0x1, + AI_NODE_EXEC_PRE = 0x2, + AI_NODE_EXEC_POST = 0x3, +} ai_node_exec_state; + +/* Internal/private definition of node execution callback */ +typedef ai_u32 (*ai_node_exec_cb)( + const ai_node_exec_state state, + struct ai_node_s *cur, + const ai_handle ctx); + + +/********************************* NETWORK DATATYPES *************************/ + +/*! + * @struct ai_network + * @ingroup layers + * @brief Structure encoding a sequential neural network + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + AI_CONTEXT_FIELDS + ai_klass_obj klass; /*!< opaque handler to specific network implementations */ + + ai_u16 n_batches; /*!< number of batches to process */ + ai_u16 batch_id; /*!< current batch to to process btw [0, n_batches)*/ + + // New 6.1 context storing explicitly network buffers. This allow also management of network persistent state now + ai_network_buffers buffers; /*!< network buffers datastruct */ + + ai_tensor_chain tensors; /*!< I/O tensor chain list see @ref ai_tensor_list */ + + struct ai_node_s* input_node; /*!< first node to execute */ + struct ai_node_s* current_node; /*!< current node to execute */ + + ai_node_exec_cb on_node_exec; /*!< registered call-back function called when + a node/operator is scheduled */ + ai_handle data_exec; /*!< private reference for the runtime context */ + ai_handle lite_cb; /*!< registered opaque call-back handler for lite APIs */ +} ai_network; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_network + * @ingroup layers + * @brief Structure encoding a sequential neural network + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + AI_CONTEXT_FIELDS + // ai_klass_obj klass; /*!< opaque handler to specific network implementations */ + + // ai_u16 n_batches; /*!< number of batches to process */ + // ai_u16 batch_id; /*!< current batch to to process btw [0, n_batches)*/ + + ai_buffer* _inputs; + ai_buffer* _outputs; + ai_buffer_array _map_weights; + ai_buffer_array _map_activations; + ai_u64* _ctx; +} ai_network_context; +AI_PACKED_STRUCT_END + +/*! + * @brief Get platform runtime lib revision version as string. + * @ingroup ai_platform_interface + * @return a string containing the revision of the runtime library + */ +AI_INTERFACE_TYPE +const char* ai_platform_runtime_get_revision(void); + +/*! + * @brief Get platform runtime lib version as datastruct. + * @ingroup ai_platform_interface + * @return a datastruct containing the version of the runtime library + */ +AI_INTERFACE_TYPE +ai_platform_version ai_platform_runtime_get_version(void); + +/*! + * @brief Get platform public APIs version as datastruct. + * @ingroup ai_platform_interface + * @return a datastruct containing the version of the public APIs + */ +AI_INTERFACE_TYPE +ai_platform_version ai_platform_api_get_version(void); + +/*! + * @brief Get platform interface private APIs version as datastruct. + * @ingroup ai_platform_interface + * @return a datastruct containing the version of the interface private APIs + */ +AI_INTERFACE_TYPE +ai_platform_version ai_platform_interface_api_get_version(void); + + +/**************************************************************************** + ** Context APIs + ****************************************************************************/ +/*! + * @brief Get platform context. + * @ingroup ai_platform_interface + * @return a valid context handle or NULL otherwise + */ +AI_INTERFACE_TYPE +ai_context* ai_platform_context_acquire(const ai_handle handle); + +/*! + * @brief Release platform context. + * @ingroup ai_platform_interface + * @return an opaque handle to the released object + */ +AI_INTERFACE_TYPE +ai_handle ai_platform_context_release(ai_context* ctx); + + +/**************************************************************************** + ** Platform Network Params APIs + ****************************************************************************/ +/*! + * @brief get the weights map from user provided network params info + * @ingroup ai_platform_interface + * @param params a pointer to ai_network_params struct + * @param map table pointer to the table map to initialize + * @param map_size the number of entries of the table to initialize + * @return true if initialization succeeded, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_get_weights_map( + ai_ptr* map, const ai_size map_size, const ai_network_params* params); + +/*! + * @brief get the activations map from user provided network params info + * @ingroup ai_platform_interface + * @param params a pointer to ai_network_params struct + * @param map table pointer to the table map to initialize + * @param map_size the number of entries of the table to initialize + * @return true if initialization succeeded, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_get_activations_map( + ai_ptr* map, const ai_size map_size, const ai_network_params* params); + +/*! + * @brief bind code generated weights and activations map arrays to ai_netwoek_params + * @ingroup ai_platform_interface + * @param[out] params the network params struct reporting binded params + * @param[in] map_weights pointer to the codegened weights map array to be bound + * @param[in] map_activations pointer to the codegened activation map array to be bound + * @return true if network parameters binding succeed, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_bind_network_params( + ai_network_params* params, + const ai_buffer_array* map_weights, const ai_buffer_array* map_activations); + +/**************************************************************************** + ** Platform Network APIs + ****************************************************************************/ +/*! + * @brief get **first** error tracked when using the network + * @ingroup ai_platform_interface + * @param network an opaque handler to the network context + * @return ai_error the FIRST error generated during network processing + */ +AI_INTERFACE_TYPE +ai_error ai_platform_network_get_error(ai_handle network); + + +/*! + * @brief Set specific error code of the network. if an error is already present + * keep it + * @ingroup ai_platform_interface + * @param net_ctx a pointer to the network context + * @param type error type as defined in @ref ai_error_type + * @param code error code as defined in @ref ai_error_code + * @return true if no previous errors where recorded, false if a previous error + * is present or context is invalid + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_network_set_error( + ai_context* net_ctx, const ai_error_type type, const ai_error_code code); + +/*! + * @brief Finalize network report datastruct with I/O buffer infos + * @ingroup ai_platform_interface + * @return bool if the report has been finalized correctly. false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_api_get_network_report( + ai_handle network, ai_network_report* r); + + +/*! + * @brief Get network inputs array pointer as a ai_buffer array pointer. + * @ingroup network + * @param network an opaque handler to the network context + * @param n_buffer optional parameter to return the number of inputs + * @return a ai_buffer pointer to the inputs arrays + */ +AI_INTERFACE_TYPE +ai_buffer* ai_platform_inputs_get(ai_handle network, ai_u16 *n_buffer); + +/*! + * @brief Get network outputs array pointer as a ai_buffer array pointer. + * @ingroup network + * @param network an opaque handler to the network context + * @param n_buffer optional parameter to return the number of outputs + * @return a ai_buffer pointer to the inputs arrays + */ +AI_INTERFACE_TYPE +ai_buffer* ai_platform_outputs_get(ai_handle network, ai_u16 *n_buffer); + + +/*! + * @brief create a network context with some error check + * @ingroup ai_platform_interface + * @param a pointer to an opaque handle of the network context + * @param an (optional) pointer to the network config buffer info + * @param net_ctx a pointer to the network context structure to initialize + * @param tool_major major version id of the tool used to generate the network + * @param tool_minor minor version id of the tool used to generate the network + * @param tool_micro micro version id of the tool used to generate the network + * @return the error during network creation or error none if ok + */ +AI_INTERFACE_TYPE +ai_error ai_platform_network_create( + ai_handle* network, const ai_buffer* network_config, + ai_context* net_ctx, + const ai_u8 tool_major, const ai_u8 tool_minor, const ai_u8 tool_micro); + +/*! + * @brief destroy a network context + * @ingroup ai_platform_interface + * @param network a pointer to an opaque handle of the network context + * @return AI_HANDLE_NULL if deallocation OK, same network handle if failed + */ +AI_INTERFACE_TYPE +ai_handle ai_platform_network_destroy(ai_handle network); + +/*! + * @brief initialize the network context + * @ingroup ai_platform_interface + * @param network a pointer to an opaque handle of the network context + * @return a valid network context, NULL if initialization failed + */ +AI_INTERFACE_TYPE +ai_context* ai_platform_network_init( + ai_handle network, const ai_network_params* params); + +/*! + * @brief post-initialize of the network context. + * @ingroup ai_platform_interface + * @param network a pointer to an opaque handle of the network context + * @return a valid network context, NULL if initialization failed + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_network_post_init(ai_handle network); + +/*! + * @brief main platform runtime execute of a network + * @ingroup ai_platform_interface + * @param network an opaque handler to the network context + * @param input a pointer to the input buffer data to process + * @param output a pointer to the output buffer + * @return the number of batches processed from the input. A result <=0 in case + * of error + */ +AI_INTERFACE_TYPE +ai_i32 ai_platform_network_process( + ai_handle network, const ai_buffer* input, ai_buffer* output); + + +/**************************************************************************** + ** ST.AI Wrapper APIs + ****************************************************************************/ +AI_INTERFACE_TYPE +void ai_platform_stai_handle_error( + ai_error* dst_error, + const stai_return_code code); + + +AI_INTERFACE_TYPE +ai_buffer* ai_platform_stai_bind_io( + ai_u16* n_buffer, + ai_buffer* dst_io_buffers, + const stai_ptr* src_io_buffers, + const stai_size src_io_buffers_size); + + +AI_INTERFACE_TYPE +ai_bool ai_platform_stai_update_io( + ai_i32* batch_id, + stai_ptr* dst_inputs, stai_ptr* dst_outputs, + const ai_buffer* src_inputs, const ai_buffer* src_outputs, + const ai_size n_inputs, const ai_size n_outputs); + +/**************************************************************************** + ** Observer APIs + ****************************************************************************/ + +/*! + * @brief Return the info of a requested c-node (defined by the + * c_idx field). Should be called after the initialization phase. + * @ingroup ai_platform_observer + * @param network a pointer to an opaque handle of the network context + * @param node_info a pointer to a reference of the node description + * @return true if the node_info->c_idx designates a valid index else + * false (network error is updated). + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_node_info( + ai_handle network, ai_observer_node *node_info); + +/*! + * @brief Register an observer context. Allows to register a client CB which + * will be called before or/and after the execution of a c-node with + * the references of the used tensors (see @ref ai_observer_node). + * @ingroup ai_platform_observer + * @param network a pointer to an opaque handle of the network context + * @param cb reference of the user callback function + * @param cookie reference of a user object/ctx + * @param flags indicate expected events (see AI_OBSERVER_XX_EVT flag definition) + * @return false if the registration has failed (network error is updated) else true + * of error. + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_register( + ai_handle network, + ai_observer_node_cb cb, + ai_handle cookie, + ai_u32 flags); + +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_register_s(ai_handle network, + ai_observer_exec_ctx *ctx); + +/*! + * @brief un-register the observer context. + * @ingroup ai_platform_observer + * @param network a pointer to an opaque handle of the network context + * @param ctx a pointer to a reference of the registered platform observer context + * @param cb reference of the registered user callback function + * @param cookie reference of the registered user object/ctx + * @return false if the un-registration has failed (network error is updated) else true + * of error. + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_unregister(ai_handle network, + ai_observer_node_cb cb, ai_handle cookie); + +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_unregister_s(ai_handle network, + ai_observer_exec_ctx *ctx); + +AI_API_DECLARE_END + +#endif /*AI_PLATFORM_INTERFACE_H*/ diff --git a/lib/stai/libstai/include/ai_reloc_network.h b/lib/stai/libstai/include/ai_reloc_network.h new file mode 100644 index 000000000..7cde30d37 --- /dev/null +++ b/lib/stai/libstai/include/ai_reloc_network.h @@ -0,0 +1,416 @@ +/** + ****************************************************************************** + * @file ai_reloc_network.h + * @author MCD/AIS Team + * @brief Relocatable network support + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019,2021 STMicroelectronics. + * All rights reserved.

+ * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __AI_RELOC_NETWORK_H__ +#define __AI_RELOC_NETWORK_H__ + +#include + +/* ----------------------------------------------------------------------------- + * AI RELOC definition + * ----------------------------------------------------------------------------- + */ + +/* + * v1.0 : initial version until v7.0 tools + * v2.0 : update the init fct to support fragmented activations/weights buffer + */ + +/* version of the AI RELOC runtime (bootstrap) */ +#define AI_RELOC_RT_VERSION_MAJOR 2 +#define AI_RELOC_RT_VERSION_MINOR 0 + +/* AI RT executing mode definitions */ +#define AI_RELOC_RT_LOAD_MODE_XIP (1 << 0) /* (default) only the data/bss section are + copied in RAM, code is executed in-place */ +#define AI_RELOC_RT_LOAD_MODE_COPY (1 << 1) /* code and data sections are copied in RAM */ + +/* AI RT error definitions */ +#define AI_RELOC_RT_ERR_NONE (0) +#define AI_RELOC_RT_ERR_INVALID_BIN (-1) /* Invalid binary object */ +#define AI_RELOC_RT_ERR_MEMORY (-2) /* RAM size is insufficient */ +#define AI_RELOC_RT_ERR_NOT_SUPPORTED (-3) /* feature/option not supported */ +#define AI_RELOC_RT_ERR_PARAM (-4) /* param not valid */ + +/* + * AI RELOC flags (32b) - part of the binary header + * + * b31..b24 : 8b - RT version major.minor (4b+4b) + * + * b23..b20 : 4b - fields reserved for post-process script + * + * Variant fields + * + * b19..b12 : 8b - compilation options: ARM tool-chain, FPU, FLOAT-ABI + * b19..b16: 4b - ARM tool-chain - 1000b: GNU Arm Embedded Tool-chain + * b15: 1b - reserved + * b14.b13: 2b - Floating-point ABI used - '00b':soft, '01b':softfp, '10b':hard + * b12: 1b - FPU is used + * b11..b0 : 12b - CPUID (Part Number fields of the @0xE000ED00 CPUID register) + */ + +/* CPUID/Cortex-mM definition */ +#define AI_RELOC_ARM_CORTEX_M0P (0xC60UL) +#define AI_RELOC_ARM_CORTEX_M3 (0xC23UL) +#define AI_RELOC_ARM_CORTEX_M4 (0xC24UL) +#define AI_RELOC_ARM_CORTEX_M7 (0xC27UL) +#define AI_RELOC_ARM_CORTEX_M33 (0xD21UL) +#define AI_RELOC_ARM_CORTEX_M55 (0xD22UL) + +/* Tool-chain definition (ONLY this tool-chain is currently supported)*/ +#define AI_RELOC_TOOLCHAIN_ARM_EMBEDDED (0x8UL) + +/* Floating-point ABI definition (in relation with the tool-chain) */ +#define AI_RELOC_TOOLCHAIN_FP_ABI_SOFT (0x0UL) +#define AI_RELOC_TOOLCHAIN_FP_ABI_SOFTFP (0x1UL) +#define AI_RELOC_TOOLCHAIN_FP_ABI_HARD (0x2UL) + +/* Getter/setter macros to read */ +#define AI_RELOC_RT_SET_FLAGS(_var) (((AI_RELOC_RT_VERSION_MAJOR << 4 |\ + AI_RELOC_RT_VERSION_MINOR << 0) << 24) |\ + ((_var) & 0xFFFFF) ) + +#define AI_RELOC_RT_GET_MAJOR(_flags) (int)(((_flags) >> 28) & 0xF) +#define AI_RELOC_RT_GET_MINOR(_flags) (int)(((_flags) >> 24) & 0xF) + +#define AI_RELOC_RT_GET_VARIANT(_flags) ((_flags) & 0xFFFFF) +#define AI_RELOC_RT_GET_POST_OPTIONS(_flags) ((_flags >> 20) & 0xF) +#define AI_RELOC_RT_GET_CPUID(_flags) ((_flags >> 0) & 0xFFF) +#define AI_RELOC_RT_GET_COPTS(_flags) ((_flags >> 12) & 0xF) +#define AI_RELOC_RT_FPU_USED(_flags) (((_flags) >> 12) & 1) + + +/* AI RELOC RT context definition */ +struct ai_reloc_rt_ctx { + volatile uint32_t state; /* current state */ + ai_handle network; /* real handle of the network instance */ + uint32_t ram_addr; /* loaded base address for the RAM sections */ + uint32_t rom_addr; /* loaded base address for the ROM sections */ + uint32_t ram_alloc_addr; /* base address of the allocated buffer (optional) */ + const char *c_name; /* c-name of model */ + const uint32_t act_size; /* requested RAM size for the activations */ + const uint32_t weights_size; /* size for the weights */ + ai_observer_exec_ctx obs_ctx; /* RT low-level context for the observer */ +}; + +#define AI_RELOC_RT_STATE_NOT_INITIALIZED (0) +#define AI_RELOC_RT_STATE_INITIALIZED (1 << 0) +#define AI_RELOC_RT_STATE_XIP_MODE (1 << 1) + + +#if defined(AI_NETWORK_RELOC) + +/* ----------------------------------------------------------------------------- + * This part is only used during the compilation of the network.c to + * generate the entry points (see linker and relocatable_pp.py files). + * ----------------------------------------------------------------------------- + */ + +#if !defined(C_NAME) + +#include + +#define C_NAME network +#define C_NAME_UP NETWORK + +#else + +#if !defined(C_INC_DATA_FILE) +#error C_INC_DATA_FILE should be defined +#endif + +#if !defined(C_NAME_UP) +#error C_NAME_UP should be defined (=str.upper(C_NAME)) +#endif + +#include C_INC_DATA_FILE + +#endif + +#if !defined(VARIANT) +/* Default variant definition */ +#define VARIANT ( (AI_RELOC_TOOLCHAIN_ARM_EMBEDDED << 16) | (AI_RELOC_TOOLCHAIN_FP_ABI_HARD << 13) |\ + (1UL << 12) | AI_RELOC_ARM_CORTEX_M4) +#endif + + +#if !defined(__GNUC__) +#error "AI_NETWORK_RELOC code generation is only supported with a GCC-based tool-chain" +#endif + +#define MAKE_FN_(_x, _e) ai_ ## _x ## _e +#define MAKE_DEF_(_x, _e) AI_ ## _x ## _e + +#define _DATA_WEIGHTS(name) MAKE_DEF_(name, _DATA_WEIGHTS) +#define _DATA_ACTIVATIONS(name) MAKE_DEF_(name, _DATA_ACTIVATIONS) + +#define _MODEL_NAME(name) MAKE_DEF_(name, _MODEL_NAME) +#define _ACT_SIZE(name) MAKE_DEF_(name, _DATA_ACTIVATIONS_SIZE) +#define _WEIGHTS_SIZE(name) MAKE_DEF_(name, _DATA_WEIGHTS_SIZE) + +#define _CREATE(name) MAKE_FN_(name, _create) +#define _INIT(name) MAKE_FN_(name, _init) +#define _RUN(name) MAKE_FN_(name, _run) +#define _REPORT(name) MAKE_FN_(name, _get_report) +#define _ERROR(name) MAKE_FN_(name, _get_error) +#define _DESTROY(name) MAKE_FN_(name, _destroy) +#define _FORWARD(name) MAKE_FN_(name, _forward) +#define _DATA_PARAMS_GET(name) MAKE_FN_(name, _data_params_get) + +static ai_bool ai_network_init_v2(ai_handle hdl, const ai_handle *weights, const ai_handle *activations) +{ + ai_network_params params; + ai_bool (*fct_)(ai_network_params* params) = _DATA_PARAMS_GET(C_NAME); + fct_(¶ms); + + for (int idx=0; idx < params.map_activations.size; idx++) + AI_BUFFER_ARRAY_ITEM_SET_ADDRESS(¶ms.map_activations, idx, activations[idx]); + + for (int idx=0; idx < params.map_weights.size; idx++) + AI_BUFFER_ARRAY_ITEM_SET_ADDRESS(¶ms.map_weights, idx, weights[idx]); + + return _INIT(C_NAME)(hdl, ¶ms); +} + +/* + * Entry table to handle the offset of network entry point and + * the RT context. + */ +struct ai_reloc_network_entries { + ai_error (*create)(ai_handle* network, const ai_buffer* network_config); + ai_bool (*init)(ai_handle network, const ai_network_params* params); + ai_bool (*init_v2)(ai_handle network, const ai_handle *weights, const ai_handle *act); + ai_i32 (*run)(ai_handle network, const ai_buffer* input, ai_buffer* output); + ai_bool (*report)(ai_handle network, ai_network_report* report); + ai_error (*error)(ai_handle network); + ai_handle (*destroy)(ai_handle network); + ai_i32 (*forward)(ai_handle network, const ai_buffer* input); + ai_bool (*plt_obs_register_s)(ai_handle network, ai_observer_exec_ctx *ctx); + ai_bool (*plt_obs_unregister_s)(ai_handle network, ai_observer_exec_ctx *ctx); + ai_bool (*plt_obs_node_info)(ai_handle network, ai_observer_node *node_info); + struct ai_reloc_rt_ctx *rt_ctx; +}; + +#define AI_RELOC_NETWORK()\ + static struct ai_reloc_rt_ctx __attribute__((used, section (".network_rt_ctx"), )) _network_rt_ctx = { 0, 0, 0, 0, 0, _MODEL_NAME(C_NAME_UP), _ACT_SIZE(C_NAME_UP), _WEIGHTS_SIZE(C_NAME_UP) }; \ + const struct ai_reloc_network_entries __attribute__((used, section (".network_rt_init"), visibility("default"))) _network_entries = { \ + .create = _CREATE(C_NAME), \ + .init = _INIT(C_NAME), \ + .init_v2 = ai_network_init_v2, \ + .run = _RUN(C_NAME), \ + .report = _REPORT(C_NAME), \ + .error = _ERROR(C_NAME), \ + .destroy = _DESTROY(C_NAME), \ + .forward = _FORWARD(C_NAME), \ + .plt_obs_register_s = ai_platform_observer_register_s, \ + .plt_obs_unregister_s = ai_platform_observer_unregister_s, \ + .plt_obs_node_info = ai_platform_observer_node_info, \ + .rt_ctx = &_network_rt_ctx,\ + }; \ + const uint32_t __attribute__((used, section (".network_rt_flags"), visibility("default"))) _network_flags = AI_RELOC_RT_SET_FLAGS(VARIANT);\ + + +#else + +#define AI_RELOC_NETWORK() + +#endif + + +AI_API_DECLARE_BEGIN + +typedef struct _ai_rel_network_info { + const char* c_name; /* c-name of the model */ + ai_u32 variant; /* 32-b word to handle the reloc rt version, + the used ARM Embedded compiler, + Cortex-Mx (CPUID) and if the FPU is requested */ + ai_size code_sz; /* size of the code (header + txt + rodata + data + got + rel sections) */ + ai_handle weights; /* address of the weights (= @ of the object + offset) */ + ai_size weights_sz; /* size (in bytes) of the weights */ + ai_size acts_sz; /* minimum requested RAM size (in bytes) for the activations buffer */ + ai_size rt_ram_xip; /* minimum requested RAM size to install it, XIP mode */ + ai_size rt_ram_copy; /* minimum requested RAM size to install it, COPY mode */ +} ai_rel_network_info; + + +/* ----------------------------------------------------------------------------- + * Public API declaration + * ----------------------------------------------------------------------------- + */ + +/*! + * @brief utility function to retrieve the dimensioning information + * to install the relocatable binary network + * + * @param obj address of the binary object + * @rt rt a pointer to the ai_rel_network_info struct where to + * store info. + * + * @return an error type/code pair indicating both the error type and code + * see @ref ai_error for struct definition + */ +AI_API_ENTRY +ai_error ai_rel_network_rt_get_info(const void* obj, ai_rel_network_info* rt); + +/*! + * @brief install and create an instance of the network + * + * @param obj address of the binary object + * @param ram_addr indicate the address of the RAM to install + * the different sections according the requested mode. + * @param ram_size indicate the size of the provided RAM + * @param mode indicate the expected executing mode + * - AI_RELOC_RT_LOAD_MODE_XIP: code is executed in place + * - AI_RELOC_RT_LOAD_MODE_COPY: code is copied in ram before. + * @param hdl a pointer to a ai_handle object to store the reference + * (opaque object) of the instance. + * + * @return an error type/code pair indicating both the error type and code + * see @ref ai_error for struct definition + * + * Note: If ram_size or ram_addr parameters are null, requested memory buffer + * is allocated with the AI_RELOC_MALLOC/AI_RELOC_FREE functions. + * _crc_cb can be the NULL pointers to have a default behavior. + */ +AI_API_ENTRY +ai_error ai_rel_network_load_and_create(const void* obj, ai_handle ram_addr, + ai_size ram_size, uint32_t mode, + ai_handle* hdl); + +/*! + * @brief initialize the instance of the network + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * @param weights array of weights buffers + * @param act array of activations buffers + * + * @return false if the handle is invalid, weights and act addresses are + * invalid, otherwise network instance is fully initialized. + * Note that ai_rel_network_get_error() can be used to have more details + * about the error. + */ +AI_API_ENTRY +ai_bool ai_rel_network_init(ai_handle hdl, const ai_handle *weights, + const ai_handle *act); + +/*! + * @brief retrieve the network information + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * @param report reference report object to store the informations + * + * @return false if the handle is invalid, report is NULL, + * otherwise network instance is fully initialized. + * + * Note: in case of error the error type could be queried by + * using @ref ai_rel_network_get_error + */ +AI_API_ENTRY +ai_bool ai_rel_network_get_report(ai_handle hdl, ai_network_report* report); + +/*! + * @brief return the last error + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * + * @return an error type/code pair indicating both the error type and code + * see @ref ai_error for struct definition + */ +AI_API_ENTRY +ai_error ai_rel_network_get_error(ai_handle hdl); + +/*! + * @brief run the network and return the predicted output + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * @param + * + * @return number of input batches processed (default 1) or <= 0 if it fails + * + * Note: in case of error the error type could be queried by + * using @ref ai_rel_network_get_error + */ +AI_API_ENTRY +ai_i32 ai_rel_network_run(ai_handle hdl, const ai_buffer* input, ai_buffer* output); + + +/*! + * @brief un-install and destroy the instantiated network + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * + * @return AI_HANDLE_NULL if network was destroyed correctly + */ +AI_API_ENTRY +ai_handle ai_rel_network_destroy(ai_handle hdl); + +/*! + * @brief register an observer context. Allows to register a client CB which + * will be called before or/and after the execution of a c-node with + * the references of the used tensors (see @ref ai_observer_node). + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * @param cb reference of the user callback function + * @param cookie reference of a user object/ctx + * @param flags indicate expected events (see AI_OBSERVER_XX_EVT flag definition) + * + * @return false if the registration has failed (network error is updated) + * else true (network error is updated). + */ +AI_API_ENTRY +ai_bool ai_rel_platform_observer_register(ai_handle hdl, + ai_observer_node_cb cb, ai_handle cookie, ai_u32 flags); + +/*! + * @brief un-register the observer context. + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * @param cb reference of the user callback function + * @param cookie reference of a user object/ctx + * + * @return false if the un-registration has failed (network error is updated) + * else true + * + * Note: in case of error the error type could be queried by + * using @ref ai_rel_network_get_error + */ +AI_API_ENTRY +ai_bool ai_rel_platform_observer_unregister(ai_handle hdl, + ai_observer_node_cb cb, ai_handle cookie); + + +/*! + * @brief return the info of a requested c-node (defined by the + * c_idx field). Should be called after the initialization phase. + * + * @param hdl network handle (@ref ai_rel_network_load_and_create()) + * @param node_info a pointer to a reference of the node description + * + * @return true if the node_info->c_idx designates a valid index else + * false + * + * Note: in case of error the error type could be queried by + * using @ref ai_rel_network_get_error + */ +AI_API_ENTRY +ai_bool ai_rel_platform_observer_node_info(ai_handle hdl, + ai_observer_node *node_info); + +AI_API_DECLARE_END + +#endif diff --git a/lib/stai/libstai/include/core_assert.h b/lib/stai/libstai/include/core_assert.h new file mode 100644 index 000000000..6eb71d920 --- /dev/null +++ b/lib/stai/libstai/include/core_assert.h @@ -0,0 +1,37 @@ +/** + ****************************************************************************** + * @file core_assert.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core assert routine + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_ASSERT_H +#define CORE_ASSERT_H + +#ifdef HAS_AI_ASSERT +// Override __FILE__ macro to disable full path asserts() +// Need to add during build also -Wbuiltin-macro-redefined options to avoid warnings +#undef __FILE__ +#define __FILE__ (__builtin_strrchr("/" __BASE_FILE__, '/') + 1) + +#include +#define CORE_ASSERT(expr) \ + assert(expr); /* CORE_ASSERT */ + +#else +#define CORE_ASSERT(expr) \ + (void)0; /* CORE_ASSERT */ + +#endif /* HAS_AI_ASSERT */ + +#endif /* CORE_ASSERT_H */ diff --git a/lib/stai/libstai/include/core_common.h b/lib/stai/libstai/include/core_common.h new file mode 100644 index 000000000..e7513f4b5 --- /dev/null +++ b/lib/stai/libstai/include/core_common.h @@ -0,0 +1,273 @@ +#ifndef CORE_COMMON_H +#define CORE_COMMON_H +/** + ****************************************************************************** + * @file core_common.h + * @author AST Embedded Analytics Research Platform + * @brief header file of common core datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include "ai_platform.h" +#include "ai_platform_interface.h" +#include "core_datatypes.h" + +/*! + * @defgroup core_common Common Core Library Routines + * @brief Common macros, datatypes and routines of core common module + * @details This module contains the definitons and handling of the @ref ai_node + * datastructures. An ai_node is a generic abstraction for a network node that + * could be either a fixed function layer or an operator. Ideally the platform + * interface defined in api module should handle an process generic nodes in the + * network, not relying on the fact that they are layers or operators datastructs + * Specific implementative details should be kept inside layers and operators + * modules. The core module implements additionally common routines used in the + * layers and operators modules. + */ + +/******************************************************************************/ +#ifdef HAS_AI_ASSERT + #define ASSERT_ARRAY_SANITY(a_) \ + AI_ASSERT((a_) && (a_)->size>0) + + #define ASSERT_ARRAY_DATA_SANITY(a_) \ + ASSERT_ARRAY_SANITY(a_) \ + AI_ASSERT((a_)->data && (a_)->data_start) + + #define ASSERT_TENSOR_SANITY(t_) \ + AI_ASSERT((t_) && (t_)->data) \ + AI_ASSERT(CORE_TENSOR_GET_SHAPE_SIZE(t_)>0) \ + ASSERT_ARRAY_SANITY((t_)->data) + + #define ASSERT_TENSOR_LIST_SANITY(tlist_) \ + AI_ASSERT((tlist_) && (GET_TENSOR_LIST_SIZE(tlist_)>0)) \ + + #define ASSERT_TENSOR_DATA_SANITY(t_) \ + ASSERT_TENSOR_SANITY(t_) \ + ASSERT_ARRAY_DATA_SANITY((t_)->data) + + #define ASSERT_NODE_SANITY(node_) \ + do { \ + AI_ASSERT(AI_NODE_OBJ(node_)->tensors && AI_NODE_OBJ(node_)->tensors->chain) \ + ASSERT_TENSOR_SANITY(GET_TENSOR_IN(AI_NODE_OBJ(node_)->tensors, 0)) \ + ASSERT_TENSOR_SANITY(GET_TENSOR_OUT(AI_NODE_OBJ(node_)->tensors, 0)) \ + } while (0); +#else + #define ASSERT_ARRAY_SANITY(a_) /* ASSERT_ARRAY_SANITY */ + #define ASSERT_ARRAY_DATA_SANITY(a_) /* ASSERT_ARRAY_DATA_SANITY */ + #define ASSERT_TENSOR_SANITY(t_) /* ASSERT_TENSOR_SANITY */ + #define ASSERT_TENSOR_LIST_SANITY(tlist_) /* ASSERT_TENSOR_LIST_SANITY */ + #define ASSERT_TENSOR_DATA_SANITY(t_) /* ASSERT_TENSOR_DATA_SANITY */ + #define ASSERT_NODE_SANITY(node_) /* ASSERT_NODE_SANITY */ +#endif /*HAS_AI_ASSERT*/ + + +#if defined(__GNUC__) || defined(__clang__) + /* Suppress unused function warnings */ + #define AI_UNUSED_FUNCTION __attribute__((unused)) + /* Manage false positives in address sanitizer */ + #define AI_NO_SANITIZE_ADDRESS __attribute__((no_sanitize_address)) +#else + #define AI_UNUSED_FUNCTION /* AI_UNUSED_FUNCTION */ + #define AI_NO_SANITIZE_ADDRESS /* AI_NO_SANITIZE_ADDRESS */ +#endif + + +/******************************************************************************/ +#define AI_NODE_TYPE(type_) \ + ((ai_node_type)((ai_u32)(type_)&0xFFFF)) + +#define AI_NODE_OBJ(obj_) \ + ((ai_node*)(obj_)) + +#define AI_NODE_FUNC(func_) \ + ((node_func)(func_)) + +#define AI_NODE_COMMON_FIELDS_DECLARE \ + ai_node_type type; /*!< node type id (see @ref ai_node_type) */ \ + ai_id_obj id; /*!< node object instance id (see @ref ai_id_obj) */ \ + ai_flags flags; /*!< node object flags */ \ + ai_klass_obj klass; /*!< opaque handler to specific layer implementations */ \ + ai_network* network; /*!< handle to global network context */ \ + struct ai_node_s* next; /*!< the next node object in the sequence */ \ + node_func forward; /*!< forward function for the node */ \ + AI_CONST ai_tensor_chain* tensors; /*!< pointer to node tensor chain */ + +#define AI_NODE_STATEFUL_FIELDS_DECLARE \ + AI_NODE_COMMON_FIELDS_DECLARE \ + ai_handle state; \ + node_func init; \ + node_func update; \ + node_func destroy; + +#define AI_NODE_COMMON_INIT(type_, id_, flags_, klass_, network_, next_, forward_) \ + .type = AI_NODE_TYPE(type_), \ + .id = AI_ID_OBJ(id_), \ + .flags = (flags_), \ + .klass = AI_KLASS_OBJ(klass_), \ + .network = AI_NETWORK_OBJ(network_), \ + .next = AI_NODE_OBJ(next_), \ + .forward = AI_NODE_FUNC(forward_) + +/*****************************************************************************/ +/** Network Tensors Chains / Lists Handlers **/ +/*****************************************************************************/ +#define AI_FOR_EACH_TENSOR_CHAIN_DO(tlist_ptr_, chain_) \ + ai_tensor_list* tlist_ptr_ = (chain_)->chain; \ + for (; tlist_ptr_<(((chain_)->chain)+((chain_)->size)); tlist_ptr_++) + +#define AI_FOR_EACH_TENSOR_LIST_DO(idx_, t_ptr_, tlist_ptr_) \ + ai_tensor* t_ptr_ = NULL; \ + for (ai_size idx_ = 0; (idx_ < GET_TENSOR_LIST_SIZE(tlist_ptr_)) && \ + ((t_ptr_ = GET_TENSOR_LIST_ITEM(tlist_ptr_, idx_)) != NULL); ++idx_) + + +#define GET_TENSOR_LIST_INFO(list_) \ + ((list_)->info) + +#define GET_TENSOR_LIST_META(list_, pos_) \ + (&(GET_TENSOR_LIST_INFO(list_)->meta[pos_])) + +#define GET_TENSOR_LIST_STATE(list_, pos_) \ + (&(GET_TENSOR_LIST_INFO(list_)->state[pos_])) + +#define GET_TENSOR_LIST_BUFFER(list_, pos_) \ + (&(GET_TENSOR_LIST_INFO(list_)->buffer[pos_])) + +#define GET_TENSOR_LIST_ITEM(list_, pos_) \ + ((NULL!=GET_TENSOR_LIST_ITEMS(list_)) \ + ? GET_TENSOR_LIST_ITEMS(list_)[(pos_)] : NULL) + +#define GET_TENSOR_LIST_ITEMS(list_) \ + ((list_)->tensor) + +#define GET_TENSOR_LIST_SIZE(list_) \ + ((NULL!=(list_)) ? (list_)->size : 0) + +#define GET_TENSOR_CHAIN_SIZE(chain_) \ + ((NULL!=(chain_)) ? (chain_)->size : 0) + +#define GET_TENSOR_LIST(chain_, type_) \ + ((AI_CONCAT(AI_TENSOR_CHAIN_, type_)<(chain_)->size) \ + ? &(chain_)->chain[AI_CONCAT(AI_TENSOR_CHAIN_, type_)] : NULL) + +#define GET_TENSOR_LIST_IN(chain_) \ + (GET_TENSOR_LIST(chain_, INPUT)) + +#define GET_TENSOR_LIST_OUT(chain_) \ + (GET_TENSOR_LIST(chain_, OUTPUT)) + +#define GET_TENSOR_LIST_WEIGTHS(chain_) \ + (GET_TENSOR_LIST(chain_, WEIGHTS)) + +#define GET_TENSOR_LIST_SCRATCH(chain_) \ + (GET_TENSOR_LIST(chain_, SCRATCH)) + +#define GET_TENSOR_IN(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_IN(chain_), (pos_))) + +#define GET_TENSOR_OUT(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_OUT(chain_), (pos_))) + +#define GET_TENSOR_WEIGHTS(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_WEIGTHS(chain_), (pos_))) + +#define GET_TENSOR_SCRATCH(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_SCRATCH(chain_), (pos_))) + +/******************************************************************************/ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_node_type + * @ingroup core_common + * @brief generic network node numeric type ID + * + */ +typedef uint16_t ai_node_type; + +/*! + * @typedef void (*node_func)(struct ai_node_s* node) + * @ingroup core_common + * @brief Callback signatures for all forward functions + */ +typedef void (*node_func)(struct ai_node_s* node); + +/*! + * @typedef ai_float (*func_nl_el)(const ai_float x) + * @ingroup core_common + * @brief Fuction pointer for generic elementwise transforms + * + * This function pointer abstracts a generic nonlinear function applied to a + * single element. See @ref ai_math_sqrt in @ref math_helpers as examples. + */ +typedef ai_float (*func_nl_el)(const ai_float x); + +/*! + * @struct ai_node + * @ingroup core_common + * @brief Structure encoding a generic node of the network + * + * The node struct includes information about the network it belong to, the + * next node in a sequential network and the forward function. The forward + * functions are implemented in the @ref layers module. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_node_s { + AI_NODE_COMMON_FIELDS_DECLARE +} ai_node; + +/*! + * @struct ai_node_stateful + * @ingroup core_common + * @brief Structure encoding a stateful node of the network + * + * The node struct includes information about the network it belong to, the + * next node in a sequential network and the init, update and forward functions. + * The node functions are implemented in the @ref layers module. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_node_stateful_s { + AI_NODE_STATEFUL_FIELDS_DECLARE +} ai_node_stateful; + +/*! + * @brief initialize core module + * @ingroup core_common + * @return false if initialization fails, false otherwise + */ +AI_INTERNAL_API +ai_bool core_init(void); + +/*! + * @brief get 1st error raised during processing + * @ingroup core_common + * @param[out] error the @ref ai_error recorded during processing + * @return the 1st error generated during processing. If no errors AI_ERROR_NONE + */ +AI_INTERNAL_API +ai_error core_get_error(ai_error* error); + +/*! + * @brief set error recorded during processing + * @ingroup core_common + * @param[out] error the @ref ai_error to set + * @param[in] type the specific error type to set + * @param[in] code the specific error code to set + * @return true if the error is set, false in case a precedent error was already + */ +AI_INTERNAL_API +ai_bool core_set_error( + ai_error* error, const ai_error_type type, const ai_error_code code); + +AI_API_DECLARE_END + +#endif /*CORE_COMMON_H*/ diff --git a/lib/stai/libstai/include/core_convert.h b/lib/stai/libstai/include/core_convert.h new file mode 100644 index 000000000..721549e09 --- /dev/null +++ b/lib/stai/libstai/include/core_convert.h @@ -0,0 +1,159 @@ +/** + ****************************************************************************** + * @file core_convert.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core utils routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_CONVERT_H +#define CORE_CONVERT_H + +#include "ai_platform.h" +#include "ai_platform_interface.h" + +#include "core_common.h" + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup core_convert Core Convert Routines + * @brief Implementation of core node format convertion routines + * (Q7 to float, ... etc.) + */ + + +/*! + * @brief Convert tensors from float to quantized or viceversa + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert(ai_node *pNode); + +/*! + * @brief Convert integer tensors between QM.N formats (8/16 bits) + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_fixed(ai_node *pNode); + +/*! + * @brief Convert integer tensors between signed and usigned (int8/uint8) formats + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_integer(ai_node *pNode); + +/*! + * @brief Convert float tensor to binary + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_if32os1(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is8os1(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to signed int 8 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is1os8(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to signed int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is1os16(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is1of32(ai_node *pNode); + + +/*! + * @brief Convert signed int 16 bit tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is16of32(ai_node *pNode); + + +/*! + * @brief Convert unsigned int 16 bit tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_iu16of32(ai_node *pNode); + + +/*! + * @brief Convert float tensor to signed int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_if32os16(ai_node *pNode); + + +/*! + * @brief Convert float tensor to unsigned int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_if32ou16(ai_node *pNode); + + +/*! + * @brief Convert signed int 16 bit tensor to unsigned int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is16ou16(ai_node *pNode); + + +/*! + * @brief Convert a shape struct into a stride struct + * @ingroup core_convert + * @param[in] in a pointer to a shape to convert + * @return a condverted stride datastruct + */ +AI_INTERNAL_API +void core_shape_to_stride(ai_stride* out, const ai_shape* in); + + +#endif /*CORE_CONVERT_H*/ diff --git a/lib/stai/libstai/include/core_datatypes.h b/lib/stai/libstai/include/core_datatypes.h new file mode 100644 index 000000000..998aa9106 --- /dev/null +++ b/lib/stai/libstai/include/core_datatypes.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file core_datatypes.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core module private defines and datatypes + * to public nor codegen tool + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_CORE_DATATYPES_H +#define AI_CORE_DATATYPES_H + +#include + +/*! + * @defgroup Core Module Datatypes + * @brief Data structures and defines used by core module + */ + +/*! + * @brief platform runtime core library version + */ +#ifndef AI_PLATFORM_RUNTIME_MAJOR +#define AI_PLATFORM_RUNTIME_MAJOR (10) +#endif +#ifndef AI_PLATFORM_RUNTIME_MINOR +#define AI_PLATFORM_RUNTIME_MINOR (1) +#endif +#ifndef AI_PLATFORM_RUNTIME_MICRO +#define AI_PLATFORM_RUNTIME_MICRO (0) +#endif + + +#define AI_ID_OBJ(id) \ + ((ai_id_obj)(id)) + +#define AI_C_ARRAY_COUNT(array_) \ + ( sizeof(array_) / sizeof((array_)[0]) ) + +#define AI_C_ARRAY_BYTE_SIZE(array_) \ + ( sizeof(array_) ) + + +/*! + * @typedef ai_id_obj + * @ingroup core_datatypes + * @brief numeric identifier for generic object instances (e.g. layers, + * operators, etc.) It is used by codegen tool to keep tracks of specific + * instances created + */ +typedef uint16_t ai_id_obj; + +#endif /*AI_CORE_DATATYPES_H*/ diff --git a/lib/stai/libstai/include/core_log.h b/lib/stai/libstai/include/core_log.h new file mode 100644 index 000000000..423e0c22b --- /dev/null +++ b/lib/stai/libstai/include/core_log.h @@ -0,0 +1,130 @@ +/** + ****************************************************************************** + * @file core_log.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core log interfaces + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_LOG_H +#define CORE_LOG_H + +#include "ai_platform.h" +#include "ai_datatypes_defines.h" + +/*! + * @defgroup core_log Logger core routines wrapper interface + * @brief Common macros, datatypes and routines of ai logger module + * @details This header defines the wrapping macros interfaces to handle the + * global logger module. These macro are defined when the macro HAS_LOG is + * defined, otherwise they are all set to NOP routines and no logger code is + * compiled at all. When the macro HAS_LOG is defined, only the log messages + * having an enum id >= the value of the macro are compiled. Thus to include in + * compilation only log messages up to the error level the value of HAS_LOG must + * be equal the the enum value of LOG_ERROR macro (i.e. 3). a value of 6 means + * to include all log messages up to the lower LOG_TRACE level. + */ + +#if defined HAS_LOG && (HAS_LOG>=0) +#include "ai_log.h" + #define AI_LOG_SECTION(...) \ + { __VA_ARGS__ } + + #define AI_LOG_ACQUIRE() \ + ai_log_acquire() + #define AI_LOG_SET_LEVEL(level_) \ + AI_WRAP_FUNC(ai_log_set_level(level_);) + #define AI_LOG_SET_QUIET(onoff_) \ + AI_WRAP_FUNC(ai_log_set_quiet(onoff_);) + #define AI_LOG_SET_LOCK_FN(fn_, udata_) \ + AI_WRAP_FUNC(ai_log_set_lock(fn_, udata_);) + #define AI_LOG_CHANNEL_PUSH(level_, fn_, udata_) \ + AI_WRAP_FUNC(ai_log_channel_push(level_, fn_, udata_);) + #define AI_LOG_CHANNEL_POP(fn_, udata_) \ + AI_WRAP_FUNC(ai_log_channel_pop(fn_, udata_);) + #ifdef LOG_USE_FILE + #define AI_LOG_SET_FILE_POINTER(fp_) \ + AI_WRAP_FUNC(ai_log_set_fp(fp_);) + #else + #define AI_LOG_SET_FILE_POINTER(fp_) \ + AI_WRAP_FUNC(/*AI_LOG_SET_FILE_POINTER()*/) + #endif +#else + #define AI_LOG_SECTION(...) AI_WRAP_FUNC(/*AI_LOG_SECTION()*/) + + #define AI_LOG_ACQUIRE() (NULL) + #define AI_LOG_SET_LEVEL(level_) AI_WRAP_FUNC(/*AI_LOG_SET_LEVEL()*/) + #define AI_LOG_SET_QUIET(onoff_) AI_WRAP_FUNC(/*AI_LOG_SET_QUIET()*/) + #define AI_LOG_SET_LOCK_FN(fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_SET_LOCK_FN()*/) + #define AI_LOG_CHANNEL_PUSH(level_, fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_CHANNEL_PUSH()*/) + #define AI_LOG_CHANNEL_POP(fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_CHANNEL_POP()*/) + #define AI_LOG_SET_FILE_POINTER(fp_) AI_WRAP_FUNC(/*AI_LOG_SET_FILE_POINTER()*/) +#endif + +#if defined HAS_LOG + #define AI_LOG_PRINT(level, fmt, ...) \ + AI_WRAP_FUNC(ai_log_print(level, fmt, ##__VA_ARGS__);) +#else + #define AI_LOG_PRINT(level, fmt, ...) \ + AI_WRAP_FUNC(/*AI_LOG_PRINT(...)*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_SUDO) + #define AI_LOG_SUDO(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_SUDO, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_SUDO(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_SUDO()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_TRACE) + #define AI_LOG_TRACE(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_TRACE, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_TRACE(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_TRACE()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_DEBUG) + #define AI_LOG_DEBUG(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_DEBUG, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_DEBUG(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_DEBUG()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_INFO) + #define AI_LOG_INFO(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_INFO, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_INFO(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_INFO()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_WARN) + #define AI_LOG_WARN(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_WARN, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_WARN(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_WARN()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_ERROR) + #define AI_LOG_ERROR(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_ERROR, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_ERROR(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_ERROR()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_FATAL) + #define AI_LOG_FATAL(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_FATAL, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_FATAL(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_FATAL()*/) +#endif + +#endif /*CORE_LOG_H*/ diff --git a/lib/stai/libstai/include/core_net_inspect.h b/lib/stai/libstai/include/core_net_inspect.h new file mode 100644 index 000000000..aab4a89bd --- /dev/null +++ b/lib/stai/libstai/include/core_net_inspect.h @@ -0,0 +1,92 @@ +/** + ****************************************************************************** + * @file core_net_inspect.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core network inspection APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_NET_INSPECT_H +#define CORE_NET_INSPECT_H + +#include "core_net_inspect_interface.h" + +#include "core_common.h" +#include "layers_common.h" + +/*! + * @defgroup core_net_inspect Core Network Inspection routines + * @brief Implementation of core network inspection routines that allows to + * inspect on a node basis a generated network model + * @details A network context @ref ai_network basically contains a chained list + * of nodes @ref ai_node that have an associated forward function. + * Each ai)network context and ai_node datastructs have as a required member + * field an opaque handler (i.e. a void pointer) to a klass object. + * This handler is intended to be used as a platform specific node context + * that implements specific target platform routines. + * The inspector module basically acts as a plugin that exploiting these features + * by temporary creating an hidden inspection context (see + * @ref ai_core_inspect_net_klass) associated to the network and + * linking it by re-routing the klass field to this inspection context. The + * inspection context saves as part of its state (by a stack push operation), the + * internal state of the network (all node / network klass pointers and actual + * forward functions). + * Thus, for each node it re-routes all node's forward functions to a dedicated + * inspection forward function (see @ref _forward_inspect_validate() routine) + * This routine is the core of the mechanism and it allows to inspect a network + * node by node. Some additional inspection could thus be done inside the + * _forward_inspect_validate() routine before and after the actual node + * forward function is called; + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup core_net_inspect Network Inspection Core + * @brief Implementation of the validation network routines + */ + +/*! + * @brief Initialize the network inspection context on a given network + * @ingroup core net inspect + * @param network opaque handler to the network instance + * @param cfg a pointer to the inspector configuration we want to use + * @return true if execution of the API is fine, false otherwise + */ +AI_API_ENTRY +ai_bool ai_network_inspect_init( + ai_handle network, const ai_inspect_config* cfg); + +/*! + * @brief Get a summary report from the inspected network + * @ingroup core net inspect + * @param network opaque handler to the network instance + * @param report a pointer to the report provided back by the inspection + * @return true if execution of the API is fine, false otherwise + */ +AI_API_ENTRY +ai_bool ai_network_inspect_get_report( + ai_handle network, ai_inspect_net_report* report); + +/*! + * @brief Destroy the network inspection context on a given network + * @ingroup core net inspect + * @param network opaque handler to the network instance + * @return true if execution of the API is fine, false otherwise + */ +AI_API_ENTRY +ai_bool ai_network_inspect_destroy(ai_handle network); + +AI_API_DECLARE_END + +#endif /* CORE_NET_INSPECT_H */ diff --git a/lib/stai/libstai/include/core_net_inspect_interface.h b/lib/stai/libstai/include/core_net_inspect_interface.h new file mode 100644 index 000000000..2ad03cdc5 --- /dev/null +++ b/lib/stai/libstai/include/core_net_inspect_interface.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file core_net_inspect_interface.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core network inspection interface APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_NET_INSPECT_INTERFACE_H +#define CORE_NET_INSPECT_INTERFACE_H + +#include "ai_platform.h" + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup core_validation Validation Core + * @brief Implementation of the validation network interface headers + */ + + +/*! + * @struct ai_inspect_node_info + * @brief network node inspection context: there is one of this datastruct + * for each node of the network + */ +typedef struct ai_inspect_node_info_s { + ai_u16 type; /*!< node type info @see ai_node datastruct */ + ai_u16 id; /*!< node id assigned by codegen tool to identify + the specific node instance */ + ai_u16 batch_id; /*!< current node batch processed */ + ai_u16 n_batches; /*!< total number of node batches to process */ + ai_float elapsed_ms; /*!< node performance analysys: time in + milliseconds to execute the node forward + function */ + ai_u16 in_size; /*!< number of node's input activation buffers */ + ai_u16 out_size; /*!< number of node's output activation buffers */ + ai_buffer* in; /*!< input node activation buffer see @ref ai_buffer */ + ai_buffer* out; /*!< output node activation buffer see @ref ai_buffer */ +} ai_inspect_node_info; + +/*! + * @struct ai_inspect_net_report + * @brief network inspection report context + */ +typedef struct ai_inspect_net_report_s { + ai_u32 id; /*!< id of the report */ + ai_signature signature; /*!< network identification checksum */ + ai_u32 num_inferences; /*!< total number of inferences processed + during the inspection */ + ai_u32 n_nodes; /*!< number of nodes in the network */ + ai_float elapsed_ms; /*!< network total time (in ms) for processing + num_inferences inferences */ + ai_inspect_node_info* node; /*!< pointer to the array of size n_nodes where + a single node report is reported. see @ref + ai_inspect_node_info datastruct */ +} ai_inspect_net_report; + +/*! + * @enum net inspector inspection mode + * @brief configuration flags to set net inspection mode + */ +typedef enum { + VALIDATION_INSPECT = (0x1<<0), /**< Network validation inspection mode */ + STORE_ALL_IO_ACTIVATIONS = (0x1<<7), /**< Store all I/O activations on snapshot datastruct */ +} ai_inspect_mode; + +typedef enum { + AI_NODE_EXEC_PRE_FORWARD_STAGE = 0x0, + AI_NODE_EXEC_POST_FORWARD_STAGE = 0x1, +} ai_node_exec_stage; + +/*! + * @brief function pointer to callback report + */ +typedef void (*ai_inspect_report_cb_func)( + const ai_handle cookie, + const ai_inspect_net_report* report); + +/*! + * @brief function pointer to node execute + */ +typedef void (*ai_inspect_exec_node_cb_func)( + const ai_handle cookie, + const ai_inspect_node_info* node_info, + const ai_node_exec_stage stage); + +/*! + * @struct ai_inspect_config + * @brief inspection config datastruct + */ +typedef struct ai_inspect_config_s { + ai_u8 validation_mode; /*!< validation mode flags + see @ref ai_inspect_mode */ + ai_u8 log_level; /*!< log class level see @ref LOG_SUDO */ + ai_bool log_quiet; /*!< log class quiet mode */ + ai_inspect_report_cb_func on_report_destroy; /*!< callback function + called when a report datastruct + is released from memory */ + ai_inspect_exec_node_cb_func on_exec_node; /*!< callback function + called when a node is executed (pre & post) */ + ai_handle cookie; +} ai_inspect_config; + + +AI_API_DECLARE_END + +#endif /* CORE_NET_INSPECT_INTERFACE_H */ diff --git a/lib/stai/libstai/include/core_private.h b/lib/stai/libstai/include/core_private.h new file mode 100644 index 000000000..4e5e0a132 --- /dev/null +++ b/lib/stai/libstai/include/core_private.h @@ -0,0 +1,365 @@ +/** + ****************************************************************************** + * @file core_private.h + * @author AST Embedded Analytics Research Platform + * @brief private header file of common private core private module defines + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_PRIVATE_H +#define CORE_PRIVATE_H + +#include "ai_datatypes_format.h" +#include "ai_datatypes_internal.h" +#include "ai_math_helpers.h" + +#include "core_assert.h" +#include "core_log.h" + +/*! + * @defgroup core_private Core Library Private macros and datatypes + * @brief Common macros, datatypes and routines for core private rounites + * @details This module contains the definitons and implementations of some + * internal routines and datatypes that are supposed to not be exposed as + * public headers. So usually this file should be include only on .c files or + * headers that are private as well + */ + +/*** Foreground Colors ****************************************************/ +#define CORE_COLOR_BLACK "\x1b[30m" +#define CORE_COLOR_RED "\x1b[31m" +#define CORE_COLOR_GREEN "\x1b[32m" +#define CORE_COLOR_YELLOW "\x1b[33m" +#define CORE_COLOR_BLUE "\x1b[94m" +#define CORE_COLOR_MAGENTA "\x1b[35m" +#define CORE_COLOR_CYAN "\x1b[36m" +#define CORE_COLOR_WHYTE "\x1b[37m" +#define CORE_COLOR_DEFAULT "\x1b[39m" +#define CORE_COLOR_LGRAY "\x1b[90m" +#define CORE_COLOR_LRED "\x1b[91m" +#define CORE_COLOR_LGREEN "\x1b[92m" +#define CORE_COLOR_LYELLOW "\x1b[93m" +#define CORE_COLOR_LBLUE "\x1b[94m" +#define CORE_COLOR_LMAGENTA "\x1b[95m" +#define CORE_COLOR_LCYAN "\x1b[96m" +#define CORE_COLOR_LWHITE "\x1b[97m" + +/*** Text Attributes Colors *********************************************/ +#define CORE_COLOR_OFF "\x1b[0m" +#define CORE_COLOR_BOLD "\x1b[1m" +#define CORE_COLOR_UNDERLINE "\x1b[4m" +#define CORE_COLOR_BLINK "\x1b[5m" +#define CORE_COLOR_BOLD_OFF "\x1b[21m" +#define CORE_COLOR_UNDERLINE_OFF "\x1b[24m" +#define CORE_COLOR_BLINK_OFF "\x1b[25m" + +/*** Background Colors ****************************************************/ +#define CORE_COLOR_BG_BLACK "\x1b[40m" +#define CORE_COLOR_BG_RED "\x1b[41m" +#define CORE_COLOR_BG_GREEN "\x1b[42m" +#define CORE_COLOR_BG_YELLOW "\x1b[43m" +#define CORE_COLOR_BG_BLUE "\x1b[44m" +#define CORE_COLOR_BG_MAGENTA "\x1b[45m" +#define CORE_COLOR_BG_CYAN "\x1b[46m" +#define CORE_COLOR_BG_WHITE "\x1b[47m" +#define CORE_COLOR_BG_DEFAULT "\x1b[49m" +#define CORE_COLOR_BG_LGRAY "\x1b[100m" +#define CORE_COLOR_BG_LRED "\x1b[101m" +#define CORE_COLOR_BG_LGREEN "\x1b[102m" +#define CORE_COLOR_BG_LYELLOW "\x1b[103m" +#define CORE_COLOR_BG_LBLUE "\x1b[104m" +#define CORE_COLOR_BG_LMAGENTA "\x1b[105m" +#define CORE_COLOR_BG_LCYAN "\x1b[106m" +#define CORE_COLOR_BG_LWHITE "\x1b[107m" + + +/*****************************************************************************/ +#define CORE_ADDRESS_RANGE_INIT(start_, end_) \ + core_address_range_init(start_, end_) + +#define CORE_GET_BUFFER_META_INFO(meta_info_, tensor_ptr_) \ + core_get_buffer_meta_info(meta_info_, tensor_ptr_) + +#define CORE_ADDRESS_RANGE_END(range_) \ + ( (ai_ptr)(((range_)->start)+((range_)->size)) ) + +#define CORE_ADDRESS_RANGE_OVERLAP(overlap_) \ + ( ((overlap_)->start) && (((overlap_)->size)>0) ) + +#define CORE_ADDRESS_RANGE_OVERLAP_PARTIAL(overlap_, ref_) \ + ( ((overlap_)->start) && (((overlap_)->size)<((ref_)->size)) ) + +#define CORE_MEMORY_OVERLAP_INIT(partial_, range_, chain_id_, tensor_id_) { \ + .partial = (partial_), .range = AI_PACK(range_), \ + .chain_id = (chain_id_), .tensor_id = (tensor_id_) \ +} + +#define CORE_OFFSET(offset_, max_) \ + ((ai_i32)(((offset_)<0) ? AI_MAX((max_) - (offset_), 0) : AI_MIN(offset_, max_))) + +/*****************************************************************************/ +/** Network Context Handlers **/ +/*****************************************************************************/ + +/*****************************************************************************/ +/** Network Tensors Handlers **/ +/*****************************************************************************/ +#define AI_TENSOR_HAS_INTQ_INFO \ + AI_BUFFER_META_HAS_INTQ_INFO + +#define CORE_TENSOR_GET_SHAPE_SIZE(tensor_) \ + ai_shape_get_size(AI_TENSOR_SHAPE(tensor_)) + + +#define CORE_ASSERT_SHAPE_MATCH(x, y) \ +do { \ + AI_ASSERT(AI_SHAPE_H(y) == 1 || AI_SHAPE_H(x)==1 || AI_SHAPE_H(y)==AI_SHAPE_H(x)) \ + AI_ASSERT(AI_SHAPE_W(y) == 1 || AI_SHAPE_W(x)==1 || AI_SHAPE_W(y)==AI_SHAPE_W(x)) \ + AI_ASSERT(AI_SHAPE_D(y) == 1 || AI_SHAPE_D(x)==1 || AI_SHAPE_D(y)==AI_SHAPE_D(x)) \ + AI_ASSERT(AI_SHAPE_E(y) == 1 || AI_SHAPE_E(x)==1 || AI_SHAPE_E(y)==AI_SHAPE_E(x)) \ + AI_ASSERT(AI_SHAPE_CH(y) == 1 || AI_SHAPE_CH(x)==1|| AI_SHAPE_CH(y)==AI_SHAPE_CH(x)) \ + AI_ASSERT(AI_SHAPE_IN_CH(y) == 1 || AI_SHAPE_IN_CH(x)==1|| AI_SHAPE_IN_CH(y)==AI_SHAPE_IN_CH(x)) \ +} while(0); + + +#define AI_TENSOR_ARRAY_BYTE_SIZE(t_) \ + AI_ARRAY_OBJ_BYTE_SIZE(AI_ARRAY_OBJ(t_->data)) + +#define AI_TENSOR_ARRAY_GET_DATA_ADDR(t_) \ + AI_HANDLE_PTR(AI_ARRAY_OBJ_DATA_START(t_->data, void)) + +#define AI_TENSOR_ARRAY_UPDATE_DATA_ADDR(t_, addr_) \ + { ai_array *arr_ = AI_ARRAY_OBJ(t_->data); \ + const uintptr_t off_ = (uintptr_t)arr_->data - (uintptr_t)arr_->data_start; \ + arr_->data_start = AI_PTR(addr_); \ + arr_->data = AI_PTR((uintptr_t)addr_ + off_); \ + } + +#define AI_TENSOR_INTEGER_GET_SIZE(t_) \ + ((t_->klass) ? (AI_KLASS_GET_INTQ_INFO_LIST(t_))->size : 0) + +#define AI_TENSOR_INTEGER_GET_SCALE(t_, idx_) \ + AI_INTQ_INFO_LIST_SCALE(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_float, idx_) + +#define AI_TENSOR_INTEGER_GET_ZEROPOINT_I8(t_, idx_) \ + AI_INTQ_INFO_LIST_ZEROPOINT(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_i8, idx_) + +#define AI_TENSOR_INTEGER_GET_ZEROPOINT_U8(t_, idx_) \ + AI_INTQ_INFO_LIST_ZEROPOINT(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_u8, idx_) + +#define AI_TENSOR_FMT_GET_SIGN(t_) \ + AI_BUFFER_FMT_GET_SIGN(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_FMT_GET_BITS(t_) \ + AI_BUFFER_FMT_GET_BITS(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_FMT_GET_FBITS(t_) \ + AI_BUFFER_FMT_GET_FBITS(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_FMT_GET_TYPE(t_) \ + AI_BUFFER_FMT_GET_TYPE(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_GET_FMT(t_) \ + AI_FMT_OBJ(AI_ARRAY_OBJ(t_->data)->format) + + +/*****************************************************************************/ +/** Network Buffers Handlers **/ +/*****************************************************************************/ +#define AI_FOR_EACH_BUFFER_ARRAY_ITEM(buffer_ptr_, buffer_array_ptr_, start_pos_, end_pos_) \ + ai_buffer* buffer_ptr_ = AI_BUFFER_ARRAY_ITEM(buffer_array_ptr_, \ + CORE_OFFSET(end_pos_, AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_))); \ + for ( ; buffer_ptr_ && AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_) && \ + (buffer_ptr_>=AI_BUFFER_ARRAY_ITEM(buffer_array_ptr_, \ + CORE_OFFSET(start_pos_, AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_)))); buffer_ptr_--) + +/*****************************************************************************/ +/** Network Arrays Handlers **/ +/*****************************************************************************/ +#define AI_ARRAY_OBJ_FMT(array_) \ + AI_FMT_OBJ(AI_ARRAY_OBJ(array_)->format) + +#define AI_ARRAY_OBJ_FMT_GET(array_) \ + AI_FMT_GET(AI_ARRAY_OBJ_FMT(array_)) + +#define AI_ARRAY_OBJ_SIZE(array_) \ + (AI_ARRAY_OBJ(array_)->size) + +#define AI_ARRAY_OBJ_BYTE_SIZE(array_) \ + AI_SIZE(AI_ARRAY_GET_BYTE_SIZE(AI_ARRAY_OBJ_FMT(array_), \ + AI_ARRAY_OBJ_SIZE(array_))) + +#define AI_ARRAY_OBJ_DATA_SIZE(array_) \ + AI_ARRAY_GET_DATA_BYTE_SIZE(AI_ARRAY_OBJ_FMT(array_), \ + AI_ARRAY_OBJ_SIZE(array_)) + +#define AI_ARRAY_OBJ_DATA(array_, type_) \ + AI_CAST(type_*, AI_ARRAY_OBJ(array_)->data) + +#define AI_ARRAY_OBJ_DATA_START(array_, type_) \ + AI_CAST(type_*, AI_ARRAY_OBJ(array_)->data_start) + +#define AI_ARRAY_OBJ_ELEM(array_, type_, pos_) \ + AI_ARRAY_OBJ_DATA(array_, type_)[(pos_)] + + +/*****************************************************************************/ +/** Network Tensors Chains / Lists Handlers **/ +/*****************************************************************************/ +#define SET_TENSOR_IN(chain_, pos_) \ + (GET_TENSOR_LIST_IN(chain_)->tensor[(pos_)]) + +#define SET_TENSOR_OUT(chain_, pos_) \ + (GET_TENSOR_LIST_OUT(chain_)->tensor[(pos_)]) + +#define AI_NODE_IO_GET(node_, in_, out_) \ + ASSERT_NODE_SANITY(node_) \ + ai_tensor* in_ = GET_TENSOR_IN((node_)->tensors, 0); \ + ai_tensor* out_ = GET_TENSOR_OUT((node_)->tensors, 0); \ + ASSERT_TENSOR_SANITY(in_) \ + ASSERT_TENSOR_SANITY(out_) + + +/*****************************************************************************/ +#define AI_BITS_TO_BYTES(bits_) \ + (((bits_)+0x7) >> 3) + +#define AI_BYTES_TO_BITS(bytes_) \ + ((bytes_) << 3) + + +/*****************************************************************************/ +/** Network Nodes Handlers **/ +/*****************************************************************************/ +#define AI_NODE_IS_FIRST(node) \ + (AI_NODE_OBJ(node)==AI_NODE_OBJ(AI_NODE_OBJ(node)->network->input_node)) + +#define AI_NODE_IS_LAST(node_) \ + ((AI_NODE_OBJ(node_)==AI_NODE_OBJ(node_)->next) || \ + (AI_NODE_OBJ(node_)->next==NULL)) + +#define AI_FOR_EACH_NODE_DO(node_, nodes_) \ + for (ai_node* node_ = AI_NODE_OBJ(nodes_); (node_); \ + node_ = ((AI_NODE_IS_LAST(node_)) ? NULL : (node_)->next)) + +/*****************************************************************************/ +typedef struct { + ai_ptr start; + ai_size size; +} ai_address_range; + +typedef struct { + ai_address_range range; + ai_u16 chain_id; + ai_u16 tensor_id; + ai_bool partial; +} ai_memory_overlap; + +/*****************************************************************************/ +AI_DECLARE_STATIC +ai_address_range core_address_range_init( + const ai_handle start, const ai_handle end) +{ + ai_address_range r; + + r.start = (ai_ptr)((startdata) + ai_bool ok; + + meta->flags = 0x0; + meta->intq_info = AI_KLASS_GET_INTQ_INFO_LIST(t); + ok = (meta->intq_info && (meta->intq_info->size>0)); + meta->flags |= (ok) ? AI_BUFFER_META_HAS_INTQ_INFO : 0x0; + return (ok) ? meta : NULL; +} + + +#if 0 +#include +#include + +AI_DECLARE_STATIC +void _dump_file_print( + const char* fname, const char* fmt, ...) +{ + static FILE* fp = NULL; + if (fname) { + if (!fp) { + fp = fopen(fname, "a"); + } + } + + if (fp) { + va_list args; + va_start(args, fmt); + vfprintf(fp, fmt, args); + va_end(args); + fflush(fp); + } +} + + +AI_DECLARE_STATIC +void _dump_bytearray( + const char* fname, + const ai_handle src, const ai_size src_size, const ai_u8 src_id, + const char* name) +{ + static FILE* fp = NULL; + if (fname && src && (src_size>0)) { + if (!fp) { + fp = fopen(fname, "a"); + } + } + + if (fp) { + switch (src_id) { + case 1: + { + const ai_float* src_value = (const ai_float*)src; + fprintf(fp, "ai_float %s[%u] = {%f", name, src_size, src_value[0]); + for (ai_size i=1; i the include directories are searched in the order + * specified in the compiler + * To enable the override, put the generated path before the API path + */ + +#include "ai_platform.h" + +AI_API_DECLARE_BEGIN + +#ifdef AI_OVERRIDE_CUSTOM_TYPES +#warning "Warning: Custom Types have been already defined!\n" +#endif + +#define AI_CUSTOM_TYPES_COUNT (3) + +#define AI_CUSTOM_TYPES_SIGNATURE_DECLARE(name) \ + const ai_custom_type_signature name[AI_CUSTOM_TYPES_COUNT+1] = { \ + AI_CUSTOM_TYPES_COUNT, \ + AI_CUSTOM_SIZE(ai_shape_dimension), \ + AI_CUSTOM_SIZE(ai_stride_dimension), \ + AI_CUSTOM_SIZE(ai_array_size), \ + }; + + +typedef ai_i32 ai_stride_dimension; +typedef ai_u32 ai_array_size; + + +AI_API_DECLARE_END + +#endif /* DATATYPES_NETWORK_H */ diff --git a/lib/stai/libstai/include/ec.h b/lib/stai/libstai/include/ec.h new file mode 100644 index 000000000..2a0172292 --- /dev/null +++ b/lib/stai/libstai/include/ec.h @@ -0,0 +1,40 @@ +/** + ****************************************************************************** + * @file ec.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of Epoch Controller Blobs. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __EC_H +#define __EC_H + +#include + +/** Magic number of the Epoch Controller binary file. */ +#define ECASM_BINARY_MAGIC 0xECBF0020 + +/** Magic number of the Epoch Controller program. */ +#define ECASM_PROGRAM_MAGIC 0xCA057A7A + +/** Type containing an Epoch Controller instruction. */ +typedef uint32_t ECInstr; + +/** Type containing an address of an Epoch Controller instruction. */ +typedef uint32_t ECAddr; + +/** Type used for each entry of the Epoch Controller binary file: magic number, number of elements, file and instruction + * offsets. */ +typedef uint32_t ECFileEntry; + +#endif // #ifndef __EC_H diff --git a/lib/stai/libstai/include/ecloader.h b/lib/stai/libstai/include/ecloader.h new file mode 100644 index 000000000..aed9e2709 --- /dev/null +++ b/lib/stai/libstai/include/ecloader.h @@ -0,0 +1,69 @@ +/** + ****************************************************************************** + * @file ecloader.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of Epoch Controller Blobs Loader. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __ECLOADER_H +#define __ECLOADER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "ec.h" + +#ifdef USE_FILES + + // return the size of a file. + extern long ec_file_size(const char *path); + + // copy a file to memory + extern bool ec_copy_file(const char *path, uint8_t *ptr); + +#endif /* #ifdef USE_FILES */ + + // copy to memory the Epoch Controller program contained in an Epoch Controller binary + extern bool ec_copy_program(const uint8_t *file_ptr, ECInstr *program, unsigned int *program_size); + + // copy to memory the relocation table contained in an Epoch Controller binary + extern bool ec_copy_reloc_table(const uint8_t *file_ptr, ECFileEntry *reloc_table, unsigned int *reloc_table_size); + + // get the pointer to the relocation table contained in an Epoch Controller binary + extern const ECFileEntry *ec_get_reloc_table_ptr(const uint8_t *file_ptr); + + // return the number of different relocations contained in an Epoch Controller binary + extern unsigned int ec_get_num_relocs(const ECFileEntry *reloc_table_ptr); + + // return the identifier of a relocation contained in an Epoch Controller binary + extern const char *ec_get_reloc_id(const ECFileEntry *reloc_table_ptr, unsigned int idx); + + // relocate all the values associated with a relocation specified by using an index + extern bool ec_reloc(const ECFileEntry *reloc_table_ptr, ECInstr *program, unsigned int idx, ECAddr base, + ECAddr *prev_base); + + // relocate all the values associated with a relocation specified by using an identifier + extern bool ec_reloc_by_id(const ECFileEntry *reloc_table_ptr, ECInstr *program, const char *id, ECAddr base, + ECAddr *prev_base); + +#ifdef __cplusplus +} +#endif + +#endif // #ifndef __ECLOADER_H diff --git a/lib/stai/libstai/include/formats_list.h b/lib/stai/libstai/include/formats_list.h new file mode 100644 index 000000000..a0317d3a1 --- /dev/null +++ b/lib/stai/libstai/include/formats_list.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file format_list.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* FMT_ENTRY( exp_(0/1 only), name_, type_id_, + * sign_bit_, complex_bit_, pmask_, bits_, fbits_, ldiv_bits_) + * Specifications (in order of the bit fields, little endian): + - name_ : it is the enum used to define both the ai_array_format and + ai_buffer_format. + - exp_ (1bit) : it is a boolean flag (0 or 1) indicating whether the format + is available as a public APIs ai_buffer format. in this case the field + exp_name_ indicates the enum name of the ai_buffer format + - (7 bits): reserved for flags + - sign_bit_ (1bit) : codes whether or not the format is of a signed type + - complex_bit_ (1bit) : codes if the format is of a complex type + - ldiv_bits (2 bits) : right shift value for computing the byte size of the + format + - type_id_ (4bits) : it is used to define the "family" of the format: + see @ref AI_FMT_Q as an example. Currently supported types are: + AI_FMT_Q (fixed point types), AI_FMT_FLOAT (floating point values), + AI_FMT_LUT_FLOAT or AI_FMT_LUT_Q (compressed formats) + - pmask_ (3bits) : padding mask bits for the format + - bits_ (7bits) : size in bits of the format (NB: integer+fractional bits) + - fbits_ (7bits) : number of fractional bits for the format + (for AI_FMT_Q only) + + */ + +/* Format none entry */ +FMT_ENTRY(1, NONE, AI_FMT_NONE, 0, 0, 0x0, 0, 0, 0) + +/* Floating point formats */ +FMT_ENTRY(1, FLOAT, AI_FMT_FLOAT, 1, 0, 0x0, 32, 0, 0) +FMT_ENTRY(0, FLOAT64, AI_FMT_FLOAT, 1, 0, 0x0, 64, 0, 0) +FMT_ENTRY(0, FLOAT16, AI_FMT_FLOAT, 1, 0, 0x0, 16, 0, 0) + +/* Integer formats (i.e. fractional bits = 0!) */ +FMT_ENTRY(1, U8, AI_FMT_Q, 0, 0, 0x0, 8, 0, 0) +FMT_ENTRY(1, U16, AI_FMT_Q, 0, 0, 0x0, 16, 0, 0) +FMT_ENTRY(1, U32, AI_FMT_Q, 0, 0, 0x0, 32, 0, 0) +FMT_ENTRY(0, U64, AI_FMT_Q, 0, 0, 0x0, 64, 0, 0) +FMT_ENTRY(1, U1, AI_FMT_Q, 0, 0, 0x0, 1, 0, 0) +FMT_ENTRY(0, U4, AI_FMT_Q, 0, 0, 0x0, 4, 0, 0) + +FMT_ENTRY(1, S8, AI_FMT_Q, 1, 0, 0x0, 8, 0, 0) +FMT_ENTRY(1, S16, AI_FMT_Q, 1, 0, 0x0, 16, 0, 0) +FMT_ENTRY(1, S32, AI_FMT_Q, 1, 0, 0x0, 32, 0, 0) +FMT_ENTRY(0, S64, AI_FMT_Q, 1, 0, 0x0, 64, 0, 0) +FMT_ENTRY(1, S1, AI_FMT_Q, 1, 0, 0x0, 1, 0, 0) +FMT_ENTRY(0, S4, AI_FMT_Q, 1, 0, 0x0, 4, 0, 0) + +/* Fixed-point formats including ARM CMSIS Q7, Q15, Q31 ones */ +FMT_ENTRY(1, Q, AI_FMT_Q, 1, 0, 0x0, 0, 0, 0) +FMT_ENTRY(1, Q7, AI_FMT_Q, 1, 0, 0x0, 8, 7, 0) +FMT_ENTRY(1, Q15, AI_FMT_Q, 1, 0, 0x0, 16, 15, 0) +FMT_ENTRY(0, Q31, AI_FMT_Q, 1, 0, 0x0, 32, 31, 0) + +FMT_ENTRY(1, UQ, AI_FMT_Q, 0, 0, 0x0, 0, 0, 0) +FMT_ENTRY(1, UQ7, AI_FMT_Q, 0, 0, 0x0, 8, 7, 0) +FMT_ENTRY(1, UQ15, AI_FMT_Q, 0, 0, 0x0, 16, 15, 0) +FMT_ENTRY(0, UQ31, AI_FMT_Q, 0, 0, 0x0, 32, 31, 0) + +/* Compressed formats */ +FMT_ENTRY(0, LUT4_FLOAT, AI_FMT_LUT_FLOAT, 1, 0, 0x0, 32, 0, 3) +FMT_ENTRY(0, LUT8_FLOAT, AI_FMT_LUT_FLOAT, 1, 0, 0x0, 32, 0, 2) +FMT_ENTRY(0, LUT4_Q15, AI_FMT_LUT_Q, 1, 0, 0x0, 16, 15, 2) +FMT_ENTRY(0, LUT8_Q15, AI_FMT_LUT_Q, 1, 0, 0x0, 16, 15, 1) +FMT_ENTRY(0, LUT4_UQ15, AI_FMT_LUT_Q, 0, 0, 0x0, 16, 15, 2) +FMT_ENTRY(0, LUT8_UQ15, AI_FMT_LUT_Q, 0, 0, 0x0, 16, 15, 1) + +/* Boolean format */ +FMT_ENTRY(1, BOOL, AI_FMT_BOOL, 0, 0, 0x0, 8, 0, 0) + +/* Complex formats */ +FMT_ENTRY(0, COMPLEX_FLOAT64, AI_FMT_FLOAT, 1, 1, 0x0, 64, 0, 0) +FMT_ENTRY(0, COMPLEX_S64, AI_FMT_Q, 1, 1, 0x0, 64, 0, 0) +FMT_ENTRY(0, COMPLEX_S32, AI_FMT_Q, 1, 1, 0x0, 32, 0, 0) +FMT_ENTRY(0, COMPLEX_S16, AI_FMT_Q, 1, 1, 0x0, 16, 0, 0) + +#undef FMT_ENTRY diff --git a/lib/stai/libstai/include/layers.h b/lib/stai/libstai/include/layers.h new file mode 100644 index 000000000..2c60b23d2 --- /dev/null +++ b/lib/stai/libstai/include/layers.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file layers.h + * @author STMicroelectronics + * @brief header file of AI platform layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_H +#define LAYERS_H + +#include "layers_common.h" +#include "layers_conv2d.h" +#include "layers_custom.h" +#include "layers_dense.h" +#include "layers_formats_converters.h" +#include "layers_generic.h" +#include "layers_lite_graph.h" +#include "layers_nl.h" +#include "layers_norm.h" +#include "layers_pad_dqnn.h" +#include "layers_pad_generic.h" +#include "layers_pool.h" +#include "layers_rnn.h" +#include "layers_sm.h" +#include "layers_ml.h" +#include "layers_ml_iforest.h" +#include "layers_ml_svc.h" +#include "layers_ml.h" +#include "layers_ml_linearclassifier.h" +#include "layers_ml_treeensembleclassifier.h" +#include "layers_ml_treeensembleregressor.h" +#include "layers_ml_svmregressor.h" + +#include "layers_conv2d_dqnn.h" +#include "layers_dense_dqnn.h" +#include "layers_pool_dqnn.h" +#include "layers_generic_dqnn.h" +#include "layers_upsample_generic.h" +#include "layers_upsample.h" +#include "layers_resize.h" +#include "layers_argminmax.h" +#include "layers_wrappers.h" +#include "ai_math_helpers.h" + + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_any_layer_ptr + * @ingroup layers + * @brief Generic union for typed layers pointers + */ +typedef struct { + ai_layer_type type; /*!< layer type id (see @ref ai_layer_type) */ + union { +#define LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) \ + AI_CONCAT(ai_layer_, struct_)* struct_; +#include "layers_list.h" + }; +} ai_any_layer_ptr; + + +AI_API_DECLARE_END + +#endif /*LAYERS_H*/ diff --git a/lib/stai/libstai/include/layers_argminmax.h b/lib/stai/libstai/include/layers_argminmax.h new file mode 100644 index 000000000..236242539 --- /dev/null +++ b/lib/stai/libstai/include/layers_argminmax.h @@ -0,0 +1,49 @@ + +/** + ****************************************************************************** + * @file layers_arminmax.h + * @author AIS + * @brief header file of AI platform generic layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_ARGMINMAX_H +#define LAYERS_ARGMINMAX_H + +#include "layers_generic.h" + + +AI_API_DECLARE_BEGIN + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmax_is8(ai_layer* layer); + +/*! + * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmin_is8(ai_layer* layer); + +AI_API_DECLARE_END + +#endif /*LAYERS_ARGMINMAX_H*/ diff --git a/lib/stai/libstai/include/layers_common.h b/lib/stai/libstai/include/layers_common.h new file mode 100644 index 000000000..d73163b2f --- /dev/null +++ b/lib/stai/libstai/include/layers_common.h @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file layers_common.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_COMMON_H +#define LAYERS_COMMON_H + +#ifdef USE_CYCLE_MEASUREMENTS + #include "layers_cycles_estimation.h" +#endif +#include "ai_platform.h" +#include "ai_common_config.h" + +#include "core_common.h" + +/* optimizations */ +#define AI_OPTIM_FUNC_MP_ARRAY_F32 (0) + + +#define AI_LAYER_OBJ(obj_) \ + ((ai_layer_base*)(obj_)) + +#define AI_LAYER_FUNC(func_) \ + ((layer_func)(func_)) + +#define AI_LAYER_TYPE(type_) \ + ( (ai_layer_type)((ai_u32)(type_)&0xFFFF) ) + +#define AI_LAYER_TYPE_ENTRY(type_) \ + AI_CONCAT(AI_CONCAT(AI_LAYER_, type_), _TYPE) + +#define AI_LAYER_TYPE_NAME(type_) \ + ai_layer_type_name(AI_LAYER_TYPE(type_)) + + +#if (AI_TOOLS_API_VERSION <= AI_TOOLS_API_VERSION_1_3) +#pragma message ("Including deprecated AI_LAYER_OBJ_INIT, AI_LAYER_OBJ_DECLARE") + +AI_DEPRECATED +#define AI_LAYER_OBJ_INIT(type_, id_, network_, \ + next_, forward_, ...) \ + { \ + AI_NODE_COMMON_INIT(AI_CONCAT(AI_LAYER_, type_), id_, 0x0, \ + NULL, network_, next_, forward_), \ + ## __VA_ARGS__ \ + } + +AI_DEPRECATED +#define AI_LAYER_OBJ_DECLARE(varname_, id_, type_, struct_, forward_func_, \ + network_, next_, attr_, ...) \ + AI_ALIGNED(4) \ + attr_ AI_CONCAT(ai_layer_, struct_) varname_ = \ + AI_LAYER_OBJ_INIT(type_, id_, network_, \ + next_, forward_func_, \ + ## __VA_ARGS__); + +#else + +#define AI_LAYER_OBJ_INIT(type_, id_, flags_, klass_, network_, \ + next_, forward_, tensors_, ...) \ + { \ + AI_NODE_COMMON_INIT(AI_CONCAT(AI_LAYER_, type_), id_, flags_, \ + klass_, network_, next_, forward_), \ + .tensors = (tensors_), \ + ## __VA_ARGS__ \ + } + +#define AI_LAYER_OBJ_DECLARE( \ + varname_, id_, \ + type_, flags_, klass_obj_, \ + struct_, forward_func_, \ + tensors_chain_, \ + network_, next_, attr_, ...) \ + AI_ALIGNED(4) \ + attr_ AI_CONCAT(ai_layer_, struct_) varname_ = \ + AI_LAYER_OBJ_INIT(type_, id_, flags_, klass_obj_, network_, \ + next_, forward_func_, tensors_chain_, ## __VA_ARGS__); + +#endif /* AI_TOOLS_API_VERSION_1_3 */ + +#ifdef HAS_AI_ASSERT + #define AI_LAYER_IO_GET(layer_, in_, out_) \ + ASSERT_LAYER_SANITY(layer_) \ + const ai_tensor* in_ = GET_TENSOR_IN((layer_)->tensors, 0); \ + ai_tensor* out_ = GET_TENSOR_OUT((layer_)->tensors, 0); \ + ASSERT_TENSOR_DATA_SANITY(in_) \ + ASSERT_TENSOR_DATA_SANITY(out_) + + #define AI_LAYER_TENSOR_LIST_IO_GET(layer_, tlist_in_, tlist_out_) \ + ASSERT_LAYER_SANITY(layer_) \ + const ai_tensor_list* tlist_in_ = GET_TENSOR_LIST_IN((layer_)->tensors); \ + ai_tensor_list* tlist_out_ = GET_TENSOR_LIST_OUT((layer_)->tensors); \ + ASSERT_TENSOR_LIST_SANITY(tlist_in_) \ + ASSERT_TENSOR_LIST_SANITY(tlist_out_) + + #define AI_LAYER_WEIGHTS_GET(layer_, weights_, bias_) \ + const ai_tensor* weights_ = GET_TENSOR_WEIGHTS((layer_)->tensors, 0); \ + const ai_tensor* bias_ = (GET_TENSOR_LIST_SIZE(GET_TENSOR_LIST_WEIGTHS((layer_)->tensors))>1) \ + ? GET_TENSOR_WEIGHTS((layer_)->tensors, 1) \ + : NULL; \ + ASSERT_TENSOR_DATA_SANITY(weights_) \ + if (bias_) { ASSERT_TENSOR_DATA_SANITY(bias_) } +#else + #define AI_LAYER_IO_GET(layer_, in_, out_) \ + const ai_tensor* in_ = GET_TENSOR_IN((layer_)->tensors, 0); \ + ai_tensor* out_ = GET_TENSOR_OUT((layer_)->tensors, 0); + + #define AI_LAYER_TENSOR_LIST_IO_GET(layer_, tlist_in_, tlist_out_) \ + const ai_tensor_list* tlist_in_ = GET_TENSOR_LIST_IN((layer_)->tensors); \ + ai_tensor_list* tlist_out_ = GET_TENSOR_LIST_OUT((layer_)->tensors); + + #define AI_LAYER_WEIGHTS_GET(layer_, weights_, bias_) \ + const ai_tensor* weights_ = GET_TENSOR_WEIGHTS((layer_)->tensors, 0); \ + const ai_tensor* bias_ = (GET_TENSOR_LIST_SIZE(GET_TENSOR_LIST_WEIGTHS((layer_)->tensors))>1) \ + ? GET_TENSOR_WEIGHTS((layer_)->tensors, 1) \ + : NULL; \ + +#endif /*HAS_AI_ASSERT*/ + + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup layers_common Layers Common + * @brief Implementation of the common layers datastructures + * This header enumerates the layers specific definition implemented in the + * library toghether with the macros and datatypes used to manipulate them. + */ + +/*! + * @typedef (*func_copy_tensor) + * @ingroup layers_common + * @brief Fuction pointer for generic tensor copy routines + * this function pointer abstracts a generic tensor copy routine. + */ +typedef ai_bool (*func_copy_tensor)(ai_tensor* dst, const ai_tensor* src); + +/*! + * @enum ai_layer_type + * @ingroup layers_common + * @brief ai_tools supported layers type id + */ +typedef enum { +#define LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) \ + AI_LAYER_TYPE_ENTRY(type_) = id_, +#include "layers_list.h" +} ai_layer_type; + +#define AI_LAYER_COMMON_FIELDS_DECLARE \ + AI_NODE_COMMON_FIELDS_DECLARE + +#define AI_LAYER_STATEFUL_FIELDS_DECLARE \ + AI_NODE_STATEFUL_FIELDS_DECLARE + + +/*! + * @typedef void (*layer_func)(struct ai_layer_* layer) + * @ingroup layers_common + * @brief Callback signatures for all layers forward functions + */ +typedef node_func layer_func; + +/*! + * @struct ai_layer_base + * @ingroup layers_common + * @brief Structure encoding a base layer in the network + * + */ +typedef ai_node ai_layer_base; + +/*! + * @struct ai_layer_stateful + * @ingroup layers_common + * @brief Structure encoding a stateful layer in the network + * + */ +typedef ai_node_stateful ai_layer_stateful; + +/*! + * @brief Check the custom network types against the internally compiled ones + * Helper function to check if the private APIs where compiled with a different + * `datatypes_network.h` than the one provided to the caller. + * @ingroup layers_common + * @param signatures list of type sizes signatures (first element is the number of types) + * @return false if there is a type size mismatch + */ +AI_INTERNAL_API +ai_bool ai_check_custom_types(const ai_custom_type_signature* signatures); + +/*! + * @brief Helper API to retrieve a human readable layer type from enum + * @ingroup layers_common + * @param type in type of layer + * @return string defining the type of the layer + */ +AI_INTERNAL_API +const char* ai_layer_type_name(const ai_layer_type type); + +/*! + * @brief Helper API to check if a node is a valid layer type + * @ingroup layers_common + * @param type in type of layer + * @return true if the layer is one of the ones listed in the enum, + * false otherwise + */ +AI_INTERNAL_API +ai_bool ai_layer_type_is_valid(const ai_layer_type type); + + +/*! + * @brief check scratch size computed with actual scratch buffer size + * @ingroup layers + * @param layer_type the layer type + * @param fmt buffers format + * @param filt_width filter width (when relevant) + * @param filt_height filter height (when relevant) + * @param n_channel_in the number of channels in + * @param n_channel_out the number of channels out + * @param is_pointwise is pointwise convulation (conv2d) + * @param is_rgb is rgb convolution (conv2d) + * @param is depthwise is depthwise convolution (conv2d) + * @param is_ch_wise has weights per channel + * @param is_sssa is signed + * @param p_tensor_scratch the scratch tensor + * @param p_function_name the name of the function + * @param line_nb the the line of the function + */ +AI_INTERNAL_API +void ai_layer_check_scratch_size( ai_layer_type layer_type, ai_array_format fmt, + ai_size filt_width, ai_size filt_height, + ai_u16 n_channel_in, ai_u16 n_channel_out, + ai_bool is_pointwise, ai_bool is_rgb, + ai_bool is_depthwise, ai_bool is_ch1st, ai_bool is_ch_wise, + ai_bool is_sssa, ai_u32 tensor_scratch_size_bytes, + const char *p_function_name, const int line_nb); + +#ifdef HAS_AI_ASSERT +#define CHECK_SCRATCH_BUFFER_SIZE( layer_type, fmt, \ + filt_width, filt_height, \ + n_channel_in, n_channel_out, \ + is_pointwise, is_rgb, \ + is_depthwise, is_ch1st, is_ch_wise, \ + is_sssa_ch, tensor_scratch_size_bytes) \ + ai_layer_check_scratch_size( layer_type, fmt, \ + filt_width, filt_height, \ + n_channel_in, n_channel_out, \ + is_pointwise, is_rgb, \ + is_depthwise, is_ch1st, is_ch_wise, \ + is_sssa_ch, tensor_scratch_size_bytes, \ + __FUNCTION__, __LINE__); +#else +#define CHECK_SCRATCH_BUFFER_SIZE( layer_type, fmt, \ + filt_width, filt_height, \ + n_channel_in, n_channel_out, \ + is_pointwise, is_rgb, \ + is_depthwise, is_ch1st, is_ch_wise, \ + is_sssa_ch, tensor_scratch_size_bytes) \ + AI_WRAP_FUNC(/*NULL*/) +#endif +#define IS_PW 1 +#define IS_RGB 1 +#define IS_DW 1 +#define IS_CH1ST 1 +#define IS_CH_WISE 1 +#define IS_SSSA_CH 1 + +#define NOT_PW 0 +#define NOT_RGB 0 +#define NOT_DW 0 +#define NOT_CH1ST 0 +#define NOT_CH_WISE 0 +#define NOT_SSSA_CH 0 + + +AI_API_DECLARE_END + +#endif /*LAYERS_COMMON_H*/ diff --git a/lib/stai/libstai/include/layers_conv2d.h b/lib/stai/libstai/include/layers_conv2d.h new file mode 100644 index 000000000..0cffe69fe --- /dev/null +++ b/lib/stai/libstai/include/layers_conv2d.h @@ -0,0 +1,741 @@ +/** + ****************************************************************************** + * @file layers_conv2d.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform conv2d layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_CONV2D_H +#define LAYERS_CONV2D_H + +#include "layers_nl.h" +#include "layers_pool.h" + + + + +#define AI_LAYER_CONV2D_FIELDS_DECLARE \ + AI_LAYER_COMMON_FIELDS_DECLARE \ + ai_u32 groups; /*!< groups for separable convolution */ \ + AI_CONST ai_array* nl_params; /*!< array pointer to non linear parameters */ \ + ai_handle nl_func; /*!< function pointer to non linear transform */ \ + ai_shape_2d filter_stride; /*!< filter stride, how much the filter moves */ \ + ai_shape_2d dilation; /*!< dilation value along axis of the filter */ \ + ai_shape filter_pad; /*!< filter pad 4d */ \ + ai_layer_format_type in_ch_format; /*!< Input format (Channel 1st vs Channel last */ \ + ai_layer_format_type out_ch_format; /*!< Output format (Channel 1st vs Channel last */ + + + +/*! + * @defgroup layers_conv2d Convolutive Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_dense + * @ingroup layers_conv2d + * @brief Dense (fully connected) layer + */ +typedef ai_layer_base ai_layer_dense; + +/*! + * @struct ai_layer_gemm + * @ingroup layers_conv2d + * @brief layer for General Matrix Multiplication + * + * Layer for General Matrix Multiplication (GEMM): + * \f{equation}{ Y = \alpha A \cdot B + \beta C \f} + * \f$\alpha\f$ and \f$\beta\f$ are paramaters, A and B are matrices, + * C is a matrix or an array. Size checks for A, B, C, and Y are performed and + * broadcast is applied on C if necessary. + * This is a sequential layer (see @ref ai_layer). + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gemm_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float alpha; /*!< alpha coefficient */ + ai_float beta; /*!< beta coefficient */ + ai_u8 tA; /*!< transpose A flag */ + ai_u8 tB; /*!< transpose B flag */ +} ai_layer_gemm; + +/*! + * @struct ai_layer_matmul + * @ingroup layers_conv2d + * @brief layer for General Matrix Multiplication + * + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_matmul_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float alpha; /*!< alpha coefficient */ + ai_float beta; /*!< beta coefficient */ + ai_u8 tA; /*!< transpose A flag */ + ai_u8 tB; /*!< transpose B flag */ +} ai_layer_matmul; + +/*! + * @struct ai_layer_conv2d + * @ingroup layers_conv2d + * @brief 2D convolutional layer with strides and pads + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_ { + AI_LAYER_CONV2D_FIELDS_DECLARE +} ai_layer_conv2d; + +/*! + * @struct ai_layer_conv2d_nl_pool + * @ingroup layers_conv2d + * @brief 2D convolutional layer + nl + pooling with strides and pads + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_nl_pool_ { + AI_LAYER_CONV2D_FIELDS_DECLARE + + ai_shape_2d pool_size; /*!< pooling size */ + ai_shape_2d pool_stride; /*!< pooling stride */ + ai_shape pool_pad; /*!< pooling pad */ + + ai_handle pool_func; /*!< function pointer to pooling transform */ +} ai_layer_conv2d_nl_pool; + + +/* +AI_INTERNAL_API +void ai_dict8_dot_array_f32(ai_handle out, ai_ptr_const data0, ai_ptr_const lut, + const ai_float* data1, const ai_size data_size); + +AI_INTERNAL_API +void ai_dict4_dot_array_f32(ai_handle out, ai_ptr_const data0, ai_ptr_const lut, + const ai_float* data1, const ai_size data_size); +*/ + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a floating point 32 2D convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32(ai_layer* layer); + +/*! + * @brief Computes the activations of a floating point 32 2D dw layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_if32of32wf32(ai_layer* layer); + +/*! + * @brief Computes the activations of a floating point 32 2D convolutional group layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32_group(ai_layer* layer); + +/*! + * @brief Computes the activations of a 2D floating point 32 pool fused convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32_nl_pool(ai_layer* layer); + +/*! + * @brief Computes the activations of a 2D floating point 32 pool fused dw layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_if32of32wf32_nl_pool(ai_layer* layer); + +/*! + * @brief Computes the activations of a 2D floating point 32 pool fused convolutional group layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32_group_nl_pool(ai_layer* layer); + +/*! + * @brief Computes the activations of a GEMM layer. + * @ingroup layers + * @param layer the layer including output and input tensors + */ +AI_INTERNAL_API +void forward_gemm(ai_layer* layer); + +/*! + * @brief Computes matmul layer, intended as numpy.matmul(A,B). + * @ingroup layers + * @param layer the layer including output and input tensors + */ +AI_INTERNAL_API +void forward_matmul(ai_layer* layer); + +/*! + * @brief Computes the activations of a dense (fully connected) layer. + * @ingroup layers_conv2d + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense(ai_layer* layer); + + +/*! + * @brief Computes the activations of a fixed point 2D convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a fixed point @ref ai_layer_conv2d_nl_pool + * layer. + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSSA per layer quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os8ws8_sssa_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme Optimized for HSP + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_hsp_1step_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme Optimized for HSP + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_hsp_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme Optimized for HSP + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_hsp_3step_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 1xN kernels + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_1xN_sssa8_ch(ai_layer *pLayer); + + + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels and input are + * channel first + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_ch1st_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme with depth multiplier > 1 + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_dm_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of int8 quantized DW layers. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_all_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer + * for SSSA per channel quantized scheme. Optimized for HSP + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_hsp_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer + * for SSSA per channel quantized scheme. Optimized for HSP + * 1Step version (nb input channel <= 4) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_hsp_1step_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer + * for SSSA per channel quantized scheme. Optimized for HSP + * 3 Step variant + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_hsp_3step_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_dilated_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) + * number of output channel is greater than 8 + * Kernels shall be 3x3 and stride is (1,1) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_3x3_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid or same padding) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid or same padding) + * Used for configuration supported by HSP and if HSP is available + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_hsp_1step_sssa8_ch(ai_layer *pLayer); + +AI_INTERNAL_API +void forward_conv2d_hsp_sssa8_ch(ai_layer *pLayer); + +AI_INTERNAL_API +void forward_conv2d_hsp_3step_sssa8_ch(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a int8 quantized Conv2d layer + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_all_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized RGB Conv2d layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_rgb_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels, + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels, + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_ch1st_sssa8_ch_nl_pool(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme with depth multiplier > 1 + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_dm_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of int8 quantized DW layers, with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_all_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer, + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_dilated_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) and pooling fused + * number of output channel is greater than 8 + * Kernels shall be 3x3 and stride is (1,1) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_3x3_sssa8_ch_nl_pool(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a int8 quantized non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid or same padding) and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized Conv2d layer and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_all_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSUA per layer quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSUA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for UAUA per layer quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for UAUA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_UAUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer. + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSSA per layer quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSSA per channel quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSSA_ch(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSUA per layer quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSUA per channel quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for UAUA per layer quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for UAUA per channel quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_UAUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer. + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer(ai_layer *pLayer); + + + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per layer quantized scheme Optimized for HSP + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_hsp_sssa8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per layer quantized scheme Optimized for HSP, 3Step loop (out_ch) + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_hsp_3step_sssa8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per channel quantized scheme: HSP variant + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSSA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSUA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSUA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for UAUA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for UAUA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_UAUA_ch(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_CONV2D_H*/ diff --git a/lib/stai/libstai/include/layers_conv2d_dqnn.h b/lib/stai/libstai/include/layers_conv2d_dqnn.h new file mode 100644 index 000000000..5b8f31005 --- /dev/null +++ b/lib/stai/libstai/include/layers_conv2d_dqnn.h @@ -0,0 +1,488 @@ +/** + ****************************************************************************** + * @file layers_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN conv datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_CONV2D_DQNN_H +#define LAYERS_CONV2D_DQNN_H + +#include "layers_common.h" +#include "layers_conv2d.h" + +/*! + * @defgroup layers_conv2d_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +#define AI_DQNN_PAD_1_KEY (1) +#define AI_DQNN_PAD_M1_KEY (-1) +#define AI_DQNN_PAD_0_KEY (0) +#define AI_DQNN_PAD_1_VALUE (0x0) +#define AI_DQNN_PAD_M1_VALUE (0xFFFFFFFF) +#define AI_DQNN_PAD_0_VALUE (0x2) + + +/*! + * @struct ai_layer_conv2d_dqnn + * @ingroup layers_conv2d_dqnn + * @brief conv2d_dqnn layer + * + * @ref forward_conv2d_is1os1ws1 + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_dqnn_ { + AI_LAYER_CONV2D_FIELDS_DECLARE + ai_i32 pad_value; +} ai_layer_conv2d_dqnn; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os1ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights - Optimized thanks to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os1ws1_bn_optim2(ai_layer *pLayer); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os8ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os8ws1_bn_optim1(ai_layer *pLayer); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1of32ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1of32ws1_bn_optim1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - Optimized thanks to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_optim2(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_optim1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad0(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Optimized thanks to + * Optim0 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad0_optim0(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with 0 padding (QKeras like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_pad0(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Optimized thanks + * to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad1_optim2(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_pad1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) - Optimized thanks + * to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_pad1_optim1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os1ws8(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - Optimized thanks to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os1ws8_optim2(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - quantized with DoReFa SotA quantizer + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_dorefa_is8os1ws8(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 16-bits quantized input, binary weights + and binary output + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is16os1ws1_bn_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 16-bits quantized input, binary weights + and 16-bits quantized output + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is16os16ws1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - Optimized thanks to Optim3 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_optim3(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad0(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Optimized thanks to + * Optim3 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad0_optim3(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad1(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Optimized thanks to + * Optim3 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad1_optim3(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os8ws1(ai_layer *pLayer); + +/** + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os16ws1_bn_pad0_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os16ws1_bn_pad1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os16ws1_bn_pad1_optim1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1ou16ws1_bn_pad0_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1ou16ws1_bn_pad1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsiged output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * @ingroup lite_conv2d_dqnn + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1ou16ws1_bn_pad1_optim1_fxp(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSSA per channel quantized RGB scheme using n_channel_in = 3 + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os8ws8_sssa_ch_rgb(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_bool out_ch_format, + ai_i16 *p_out_r_shift, + ai_i32 *p_out_factor); + +/*! + * @brief Computes the activations of a point-wise integer quantized convolution + for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_is8os8ws8_sssa_ch(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + ai_i16 *p_out_r_shift, + ai_i32 *p_out_factor, + ai_i32 AI_PWOverlay, + ai_i16 *bufferA, + ai_i32 scratch_size); + // st_nn_context_t context); + +/*! + * @brief Computes the activations of a depth-wise integer quantized convolution + for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_is8os8ws8_sssa_ch(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + ai_i16 *p_out_r_shift, + ai_i32 *p_out_factor); + + +AI_API_DECLARE_END + +#endif /*LAYERS_CONV2D_DQNN_H*/ diff --git a/lib/stai/libstai/include/layers_custom.h b/lib/stai/libstai/include/layers_custom.h new file mode 100644 index 000000000..5abde392c --- /dev/null +++ b/lib/stai/libstai/include/layers_custom.h @@ -0,0 +1,41 @@ +#ifndef LAYERS_CUSTOM_H +#define LAYERS_CUSTOM_H +/** + ****************************************************************************** + * @file layers_custom.h + * @author STMicroelectronics + * @brief header file of AI platform custom layers datatype + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include "layers_common.h" + +/*! + * @defgroup layers_custom Custom layer definitions + * @brief Definition of structures custom layers + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_custom + * @ingroup layers_custom + * @brief Custom layer wrapper + * + * The custom layer wrapper + */ +typedef ai_layer_stateful ai_layer_custom; + + +AI_API_DECLARE_END + +#endif /* LAYERS_CUSTOM_H */ diff --git a/lib/stai/libstai/include/layers_dense.h b/lib/stai/libstai/include/layers_dense.h new file mode 100644 index 000000000..75396251d --- /dev/null +++ b/lib/stai/libstai/include/layers_dense.h @@ -0,0 +1,105 @@ +#ifndef LAYERS_DENSE_H +#define LAYERS_DENSE_H +/** + ****************************************************************************** + * @file layers_dense.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform dense layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "layers_common.h" + + +/*! + * @defgroup layers Normalization Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @brief Computes the activations of a fixed point dense (fully connected) layer. + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer. + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSSA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSUA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSUA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for UAUA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for UAUA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_UAUA_ch(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_DENSE_H*/ + diff --git a/lib/stai/libstai/include/layers_dense_dqnn.h b/lib/stai/libstai/include/layers_dense_dqnn.h new file mode 100644 index 000000000..6ff4638df --- /dev/null +++ b/lib/stai/libstai/include/layers_dense_dqnn.h @@ -0,0 +1,394 @@ +/** + ****************************************************************************** + * @file layers_dense_dqnn.h + * @author AST Embedded Analytics Research Platform + * @brief header file of deeply quantized dense layers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_DENSE_DQNN_H +#define LAYERS_DENSE_DQNN_H + +#include "layers_common.h" + +/*! + * @defgroup layers_dense_dqnn Quantized Dense Layers definition. + * @brief Implements the kernels and the forward functions to implement + * dense layers with quantized inputs, weights, or outputs. + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_dense_dqnn + * @ingroup layers_dense_dqnn + * @brief Specific instance of deeply quantized dense layers. + */ +typedef ai_layer_base ai_layer_dense_dqnn; + +/*****************************************************************************/ +/* Forward Functions Section */ +/*****************************************************************************/ + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 8-bit signed output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os8ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 8-bit signed output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 32-bit floating point weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32wf32(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 32-bit floating point weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32wf32_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws8(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 8-bit signed weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws8_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * binary output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws8(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * binary output, and 8-bit signed weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws8_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 8-bit signed output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os8ws8(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 16-bit signed output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os16ws8(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * float output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8of32ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * float output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8of32ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 1-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 1-bit signed output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * binary weights and binary output. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os1ws1_bn_fxp(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 8-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os8ws1(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 16-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 1-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 1-bit signed output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 8-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os8ws1(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 16-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * f32 output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16of32ws1(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * f32 output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16of32ws1_bn(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 1-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 1-bit signed output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 8-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os8ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 16-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32of32ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32of32ws1_bn(ai_layer* layer); + +AI_API_DECLARE_END + +#endif /*LAYERS_DENSE_DQNN_H*/ diff --git a/lib/stai/libstai/include/layers_formats_converters.h b/lib/stai/libstai/include/layers_formats_converters.h new file mode 100644 index 000000000..99ab4df86 --- /dev/null +++ b/lib/stai/libstai/include/layers_formats_converters.h @@ -0,0 +1,57 @@ +/** + ****************************************************************************** + * @file layers_formats_converters.h + * @author AST Embedded Analytics Research Platform + * @brief header file of formats converters layers + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_FORMATS_CONVERTERS_H +#define LAYERS_FORMATS_CONVERTERS_H + +#include "layers_common.h" + +/*! + * @defgroup layers_formats_converters Formats Converters Layers Definition + * @brief this group implements formats converter layers (cast, etc.) + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_cast + * @ingroup layers_formats_converters + * @brief C Implementation of cast layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_cast_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_array_format to_format; /*!< cast output format */ +} ai_layer_cast; + + +/*****************************************************************************/ +/* Forward Functions Section */ +/*****************************************************************************/ + +/*! + * @brief forward function for cast layer. + * @ingroup layers_ + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_cast(ai_layer* layer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_FORMATS_CONVERTERS_H*/ diff --git a/lib/stai/libstai/include/layers_generic.h b/lib/stai/libstai/include/layers_generic.h new file mode 100644 index 000000000..6927b9249 --- /dev/null +++ b/lib/stai/libstai/include/layers_generic.h @@ -0,0 +1,809 @@ + +/** + ****************************************************************************** + * @file layers_generic.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform generic layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_GENERIC_H +#define LAYERS_GENERIC_H + +#include "layers_common.h" + +typedef enum { + KTfLiteNone = 0, + KTfLiteActRelu, + KTfLiteActRelu1, + KTfLiteActRelu6, + KTfLiteActTanh, + KTfLiteActSignBit, + KTfLiteActSigmoid +} ai_tflitefused_activation; + +/*! + * @defgroup layers_generic Generic Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_time_delay + * @ingroup layers_generic + * @brief TimeDelay layer with sparse kernel + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_time_delay_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* mask; /*!< sparse filter mask */ +} ai_layer_time_delay; + +/*! + * @struct ai_layer_split + * @ingroup layers_generic + * @brief Split layer definition + * + * This layer defines the params of a splitting layer. It is intended to be used + * by his associated forward function @ref forward_split + */ + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_split_ { + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_i32 outer_elems; + const ai_i32 outer_elems_stride; +} ai_layer_split; + + +/*! + * @struct ai_layer_topK + * @ingroup layers_generic + * @brief topK layer definition + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_topK_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i16 axis; + ai_i16 largest; +} ai_layer_topK; + +typedef AI_ALIGNED_TYPE(struct,4)ai_layer_svdf_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_size rank; + ai_tflitefused_activation activation; + +} ai_layer_svdf; + + +/*! + * @struct ai_layer_slice + * @ingroup layers_generic + * @brief Slice layer definition + * + * This layer defines the params of a slicing layer. It is intended to be used + * by his associated forward function @ref forward_slice + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_slice_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* axes; /*!< Axes that 'starts' and 'ends' apply to. It's optional*/ + AI_CONST ai_array* starts; /*!< Starting indices of corrisponding axis in axes*/ + AI_CONST ai_array* ends; /*!< Ending indices (exclusive) of corrisponding axis in axes*/ +} ai_layer_slice; + +/*! + * @struct ai_layer_gather + * @ingroup layers_generic + * @brief Gather layer definition + * + * This layer defines the params of a gathering layer. It is intended to be used + * by his associated forward function @ref forward_gather + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gather_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i16 axis; /*!< Which axis to gather on It's optional*/ + ai_tensor* indices; /*!< Indices of corrisponding axis in axes*/ + } ai_layer_gather; + +/*! + * @struct ai_layer_gather_nd + * @ingroup layers_generic + * @brief GatherND layer definition + * + * This layer defines the params of a gathering layer (ND). It is intended to be used + * by his associated forward function @ref forward_gather_nd + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gather_nd_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_tensor* indices; /*!< Indices of corrisponding slices of inputs*/ + } ai_layer_gather_nd; + +/*! + * @struct ai_layer_tile + * @ingroup layers generic + * @brief Tile layer definition + * + * This layer defines the param of an tile layer. It constructs a tensor by tiling a + * given tensor. It is intended to be used by its associated forward function + * @ref forward_upsample + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tile_{ + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* repeats; /*!< numbers of repeated copies along each dimension */ +} ai_layer_tile; + +/*! + * @struct ai_layer_shape + * @ingroup layers generic + * @brief Shape layer definition + * + * This layer defines the param of a shape layer. It returns the shape of the + * input tensor. It is intended to be used by its associated forward function + * @ref forward_shape + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_shape_{ + AI_LAYER_COMMON_FIELDS_DECLARE +} ai_layer_shape; + + +/*! + * @struct ai_layer_upsample + * @ingroup layers generic + * @brief Upsample layer definition + * + * This layer defines the param of an upsampling layer. It overloads its params + * to allow zeros upsampling, helpful traspose convolutions, for instance. + * It is intended to be used by its associated forward function @ref forward_upsample + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_upsample_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_upsample_mode mode; /*!< upsample mode */ + ai_bool center; /*!< center pixels */ + AI_CONST ai_array* scales; /*!< scale array along each dimension */ + ai_nearest_mode nearest_mode; /*!< used in nearest mode */ +} ai_layer_upsample; + +/*! + * @struct ai_layer_resize + * @ingroup layers generic + * @brief Resize layer definition + * + * This layer defines the param of a resize layer. + * It is intended to be used by its associated forward function @ref forward_resize + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_resize_{ + AI_LAYER_COMMON_FIELDS_DECLARE + + ai_coord_transf_mode coord_transf_mode; /*!< coordinate tranformation mode */ + ai_float cubic_coeff_a; /*!< the coefficient 'a' used in cubic interpolation */ + ai_bool exclude_outside; /*!< exclude outside pixels flag */ + ai_float extrapol_val; /*!< used in tf_crop_and_resize cas */ + ai_resize_mode mode; /*!< resize mode */ + ai_nearest_mode nearest_mode; /*!< used in nearest mode */ + AI_CONST ai_array* scales; /*!< scale array along each dimension */ + AI_CONST ai_array* roi; /*!< roi array, used in tf_crop_and_resize case */ +} ai_layer_resize; + +/*! + * @struct ai_layer_instanceNormalization + * @ingroup layers generic + * @brief instance normalization layer definition + * + * This layer defines the params of an instance normalization layer. + * It is intended to be used by its associated forward function @ref forward_instanceNormalization + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_instanceNormaization_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float eps; /*!< epsilon value, to avoid by zero division */ +} ai_layer_instanceNormalization; + +/*! + * @struct ai_layer_mode + * @ingroup layers generic + * @brief Pad layer definition + * + * This layer defines the param of an pad layer. It pad a tensor. + * It is intended to be used by its associated forward function @ref forward_pad + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pad_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_pad_mode mode; /*!< pad mode */ + ai_shape pads; /*!< Number of padding to add or remove at the beginning and end of each axis */ + const ai_array* value; /*!< Indicates the value to be filled */ +} ai_layer_pad; + +/*! + * @struct ai_layer_mode + * @ingroup layers generic + * @brief ConstantOfShape layer definition + * + * This layer defines the param of an constantofshape layer. It constantofshape a tensor. + * It is intended to be used by its associated forward function @ref forward_constantofshape + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_constantofshape_{ + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_array* value; /*!< Indicates the value to be filled */ +} ai_layer_constantofshape; +/*! + * @struct ai_layer_add + * @ingroup layers_generic + * @brief Add layer definition + * + * This layer defines the params of an add layer. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_add_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_u16 in_layers_count; /*!< number of input layers to concat */ + ai_u16 in_layer_curr; /*!< current layer to concat */ + ai_tensor** in_tensors; /*!< input tensors list (if NULL==no copy) */ + ai_tensor* out_tensor; /*!< output tensor (if NULL==no copy) */ + func_copy_tensor copy_to_out_tensor; /*!< pointer to copy tensor func + (NULL = no copy) */ + ai_layer_base* split_layer; /*!< pointer to associated split layer */ + ai_layer_base* next_layer; /*!< pointer to next layer to process */ +} ai_layer_add; + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_argminmax_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i16 axis; + ai_i16 select_last_index; +} ai_layer_argminmax; + +/*! + * @struct ai_layer_transpose + * @ingroup layers_generic + * @brief Transpose layer datastruct declaration. This defines the params of a + * transpose layer. It is intended to be used by his associated forward function + * @ref forward_transpose + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_transpose_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape out_mapping; /*!< transpose output mapping order. I.e. tt is a + permutation of the input tensor shape */ +} ai_layer_transpose; + +/*! + * @struct ai_layer_transpose_batch + * @ingroup layers_generic + * @brief Transpose batch layer datastruct declaration. This defines the params of a + * transpose layer. It is intended to be used by his associated forward function + * @ref forward_transpose_batch + */ +typedef ai_layer_base ai_layer_transpose_batch; + + +#define AI_TIME_DISTRIBUTED_AXIS (AI_SHAPE_HEIGHT) + +/*! + * @struct ai_layer_time_distributed + * @ingroup layers_generic + * @brief Time distributed layer datastruct declaration. This defines the params + * of a time distributed layer. It is intended to be used by his associated + * forward function @ref forward_time_distributed + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_time_distributed_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_layer_base* inner_layer; /*!< inner layer to process */ +} ai_layer_time_distributed; + +/*! + * @struct ai_layer_concat + * @ingroup layers_generic + * @brief Concatenation layer + * + * Concat Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_concat_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; /*!< which axis to concatenate on */ +} ai_layer_concat; + +/*! + * @struct ai_layer_pack + * @ingroup layers_generic + * @brief pack layer + * + * Pack Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pack_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; /*!< which axis to concatenate on */ +} ai_layer_pack; + +/*! + * @struct ai_layer_unpack + * @ingroup layers_generic + * @brief unpack layer + * + * Unpack Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_unpack_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; /*!< which axis to concatenate on */ +} ai_layer_unpack; + +typedef void (*func_binary)(ai_handle out,const ai_handle a, const ai_handle b); +typedef void (*func_buffer_binary)(ai_handle out,const ai_handle a, const ai_handle b, const ai_size loop); +typedef void (*func_buffer_binary_integer)(ai_handle out,const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle scale1, const ai_handle zp1, const ai_handle scale2, const ai_handle zp2, + const ai_handle scaleout, const ai_handle zpout, const ai_i32 scalar_op); + +/*! + * @struct ai_layer_eltwise + * @ingroup layers_generic + * @brief General element-wise transformation layer + * + * Elementwise Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_eltwise_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_binary operation; /*!< operation to apply elementwise */ + func_buffer_binary buffer_operation; /*!< operation to apply elementwise */ +} ai_layer_eltwise; + +/*! + * @struct ai_layer_eltwise_integer + * @ingroup layers_generic + * @brief General element-wise transformation layer for integer data + * + * Elementwise Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_eltwise_integer_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_binary operation; /*!< operation to apply elementwise */ + func_buffer_binary_integer buffer_operation; /*!< operation to apply elementwise */ +} ai_layer_eltwise_integer; + +/*! + * @struct ai_layer_scatter_nd + * @ingroup layers_generic + * @brief ScatterND layer definition + * + * This layer defines the params of a scattering layer (ND). It is intended to be used + * by his associated forward function @ref forward_scatter_nd + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_scatter_nd_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_tensor* indices; /*!< Indices of corrisponding slices of inputs*/ + ai_tensor* updates; /*!< Updates of corrisponding slices of inputs*/ + func_binary operation; /*!< operation to apply elementwise */ + ai_scatter_nd_reduction reduction; /*!< Reduction operation in ScatterND layer*/ +} ai_layer_scatter_nd; + +/*! + * @struct ai_layer_reduce + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_ { + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_array* neutral_value; /*!< Initialization value for operation */ + func_binary operation; /*!< operation to apply elementwise */ +} ai_layer_reduce; + +/*! + * @struct ai_layer_reduce_log_sum_exp + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_log_sum_exp_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; +} ai_layer_reduce_log_sum_exp; + +/*! + * @struct ai_layer_reduce l1 + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_l1_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* axes; +} ai_layer_reduce_l1; + + +/*! + * @struct ai_layer_reduce l2 + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_l2_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* axes; +} ai_layer_reduce_l2; + + +/*! + * @struct ai_layer_where + * @ingroup layers generic + * @brief Where layer definition + * + * This layer operates on 3 input tensors: condition, X and Y. + * It return elements, either from X or Y, depending on condition + * (with Numpy-style broadcasting support). + * @ref forward_where + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_where_ { + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_array *shapes_len; + ai_bool channel_first; +} ai_layer_where; + + +/*! + * @struct ai_layer_reverse + * @ingroup layers_reverse + * @brief Reverse layer + * + * The type of reverse function is handled by the specific forward function + * @ref forward_svm_regressor + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reverse_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i32 axis; /*!< selected axis to perform the operation */ +} ai_layer_reverse; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Dummy forward routine with no processing. + * @ingroup layers_generic + * @param generic layer handle + */ +AI_INTERNAL_API +void forward_nop(ai_layer* layer); + +/*! + * @brief Computes the activations of a TimeDelay layer. + * @ingroup layers_generic + * @param layer the time delay layer + */ +AI_INTERNAL_API +void forward_time_delay(ai_layer* layer); + +/*! + * @brief Split network computation in N parallel branches. + * @ingroup layers_generic + * @param layer the split layer + */ +AI_INTERNAL_API +void forward_split(ai_layer* layer); + +/*! + * @brief Add network computation from N parallel branches. + * @ingroup layers_generic + * @param layer the add layer + */ +AI_INTERNAL_API +void forward_add(ai_layer* layer); + +/*! + * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmax(ai_layer* layer); + +/*! + * @brief Compute the indices of the min elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmin(ai_layer* layer); + +/*! + * @brief Svdf layer. + * @ingroup layers_generic + * @param layer svdf layer + */ +AI_INTERNAL_API +void forward_svdf(ai_layer* layer); + +/*! + * @brief Transpose a tensor along a pivot and save transposed values into an output + * tensor + * @ingroup layers_generic + * @param layer the transpose layer + */ +AI_INTERNAL_API +void forward_transpose(ai_layer* layer); + +/*! + * @brief Transpose batch and save transposed values of a determinate batch into an output + * tensor + * @ingroup layers_generic + * @param layer the transpose batch layer + */ +AI_INTERNAL_API +void forward_transpose_batch(ai_layer* layer); + +/*! + * @brief TimeDistrubuted forward layer function. This forward function + * implements the timedistributed layer. + * @ingroup layers_generic + * @param layer the time distributed layer + */ +AI_INTERNAL_API +void forward_time_distributed(ai_layer* layer); + +/*! + * @brief Packing a list of tensors in a single tensor + * @ingroup layers generic + * @param layer the packing layer + */ +AI_INTERNAL_API +void forward_pack(ai_layer* layer); + +/*! + * @brief Unpacking a single of tensors in a list tensor + * @ingroup layers generic + * @param layer the unpacking layer + */ +AI_INTERNAL_API +void forward_unpack(ai_layer* layer); + +/*! + * @brief Concatenates a list of tensors into a single tensor. + * @ingroup layers_generic + * @param layer the concatenation layer + */ +AI_INTERNAL_API +void forward_concat(ai_layer* layer); + +/*! + * @brief Gather an input tensor + * @ingroup layers_generic + * @param layer the gathered layer + */ +AI_INTERNAL_API +void forward_gather(ai_layer* layer); + +/*! + * @brief GatherND an input tensor + * @ingroup layers_generic + * @param layer the gathered layer (ND) + */ +AI_INTERNAL_API +void forward_gather_nd(ai_layer* layer); + +/*! + * @brief GatherND channel first an input tensor + * @ingroup layers_generic + * @param layer the gathered layer (ND) + */ +AI_INTERNAL_API +void forward_gather_nd_channel_first(ai_layer* layer); + +/*! + * @brief ScatterND an input tensor + * @ingroup layers_generic + * @param layer the scattered layer (ND) + */ +AI_INTERNAL_API +void forward_scatter_nd(ai_layer* layer); + +/*! + * @brief Slice an input tensors + * @ingroup layers_generic + * @param layer the sliced layer + */ +AI_INTERNAL_API +void forward_slice(ai_layer* layer); + +/*! + * @brief Tile an input tensors + * @ingroup layers_generic + * @param layer the tiled layer + */ +AI_INTERNAL_API +void forward_tile(ai_layer* layer); + +/*! + * @brief Returns the shape of an input tensors + * @ingroup layers_generic + * @param layer the Shape layer + */ +AI_INTERNAL_API +void forward_shape(ai_layer* layer); + +/*! + * @brief TopK an input tensors + * @ingroup layers_generic + * @param layer the Topked layer + */ +AI_INTERNAL_API +void forward_topK(ai_layer* layer); + +/*! + * @brief Pad an input tensors + * @ingroup layers_generic + * @param layer the pad layer + */ +AI_INTERNAL_API +void forward_pad(ai_layer* layer); + +/*! + * @brief ConstantofShape an input tensors + * @ingroup layers_generic + * @param layer the constantofshape layer + */ +AI_INTERNAL_API +void forward_constantofshape(ai_layer* layer); + +/*! + * @brief Upsample an input tensors + * @ingroup layers_generic + * @param layer the upsampled layer + */ +AI_INTERNAL_API +void forward_upsample(ai_layer* layer); + +/*! + * @brief Resize an input tensors + * @ingroup layers_generic + * @param layer the resized layer + */ +AI_INTERNAL_API +void forward_resize(ai_layer* layer); + +/*! + * @brief Instance Normalization on an input tensors + * @ingroup layers_generic + * @param layer the instance normalization layer + */ +AI_INTERNAL_API +void forward_instanceNormalization(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the integer input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise_integer(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the signed integer input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise_integer_INT8(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the unsigned integer input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise_integer_UINT8(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce_log_sum_exp(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce_l1(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce_l2(ai_layer* layer); + + +/*! + * @brief Behave like numpy.where with Numpy-style broadcasting support + * @ingroup layers_generic + * @param layer the where layer + */ +AI_INTERNAL_API +void forward_where(ai_layer* layer); + +/*! + * @brief Apply an elementwise addition to the input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_add_integer(ai_layer* layer); + +/*! + * @brief Apply an elementwise addition to the input tensors + * with int8 I/O + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_add_integer_INT8(ai_layer* layer); + +/*! + * @brief Apply an elementwise addition to the input tensors + * with uint8 I/O + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_add_integer_UINT8(ai_layer* layer); + + +/*! + * @brief Reverse layer. + * @ingroup layers_generic + * @param layer reverse layer + */ +AI_INTERNAL_API +void forward_reverse(ai_layer *pLayer); + + +/*! + * @brief Upsample an input tensors with unsigned 8-bit integer input,. + * It is to be used also for other formats, since the function only + * performs memory copy. + * @ingroup layers_generic + * @param layer the upsampled layer + */ +AI_INTERNAL_API +void forward_upsample_generic(ai_layer* layer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_GENERIC_H*/ diff --git a/lib/stai/libstai/include/layers_generic_dqnn.h b/lib/stai/libstai/include/layers_generic_dqnn.h new file mode 100644 index 000000000..269176e71 --- /dev/null +++ b/lib/stai/libstai/include/layers_generic_dqnn.h @@ -0,0 +1,51 @@ +/** + ****************************************************************************** + * @file layers_generic_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_GENERIC_DQNN_H +#define LAYERS_GENERIC_DQNN_H + +#include "layers_common.h" +#include "layers_generic.h" + +/*! + * @defgroup layers_generic_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles concat with binary input, binary output and + * binary weights + * @ingroup layers_generic_dqnn + * @param layer concat layer + */ +AI_INTERNAL_API +void forward_concat_is1os1(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_GENERIC_DQNN_H*/ diff --git a/lib/stai/libstai/include/layers_list.h b/lib/stai/libstai/include/layers_list.h new file mode 100644 index 000000000..4c5632a7c --- /dev/null +++ b/lib/stai/libstai/include/layers_list.h @@ -0,0 +1,168 @@ +/** + ****************************************************************************** + * @file layers_list.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* No sentry. This is deliberate!! */ +/* Template: LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) + * Where: + * - type_ is the (enum) type name of the layer. to have the complete enum + * value you should use the macro @ref AI_LAYER_TYPE_ENTRY(type_) that adds + * the specific prefix and postfix tokens to the type_ + * - id_ is the numeric id of the layer + * - struct_ is the name of the datastruct of the layer without the ai_layer_ + * prefix + * - forward_func_ is the forward function name of the routine implementing + * actual layer processing + * - init_func_ is the init function name of the routine implementing + * actual layer initialization + * - destroy_func_ is the destroy function name of the routine implementing + * actual layer de-initialization + */ + +/* Layer IDs for stateless layers (bit 8 set) */ +#define LAYER_ID(id_) \ + (0x100 + (id_)) +/* Layer IDs for stateful layers (bits 7 and 8 set) */ +#define LAYER_STATEFUL_ID(id_) \ + (0x180 + (id_)) + +/*!< Base layer */ +LAYER_ENTRY(BASE, LAYER_ID(0), base, NULL, NULL, NULL) +/*!< Elementwise addition layer */ +LAYER_ENTRY(ADD, LAYER_ID(1), add, forward_add, NULL, NULL) + /*!< Batch normalization layer */ +LAYER_ENTRY(BN, LAYER_ID(2), bn, forward_bn, NULL, NULL) +/*!< 2D Convolutional layer */ +LAYER_ENTRY(CONV2D, LAYER_ID(3), conv2d, forward_conv2d, NULL, NULL) +/*!< Dense layer */ +LAYER_ENTRY(DENSE, LAYER_ID(4), dense, forward_dense, NULL, NULL) +/*!< Local Response Normalization layer */ +LAYER_ENTRY(LRN, LAYER_ID(6), lrn, forward_lrn, NULL, NULL) +/*!< Nonlinearity layer */ +LAYER_ENTRY(NL, LAYER_ID(7), nl, NULL, NULL, NULL) +/*!< Normalization layer */ +LAYER_ENTRY(NORM, LAYER_ID(8), norm, forward_norm, NULL, NULL) +/*!< Merged Conv2d / Pool layer */ +LAYER_ENTRY(OPTIMIZED_CONV2D, LAYER_ID(9), conv2d_nl_pool, forward_conv2d_nl_pool, NULL, NULL) +/*!< Transpose Tensor layer */ +LAYER_ENTRY(TRANSPOSE, LAYER_ID(10), transpose, forward_transpose, NULL, NULL) +/*!< Pooling layer */ +LAYER_ENTRY(POOL, LAYER_ID(11), pool, forward_pool, NULL, NULL) +/*!< Softmax layer */ +LAYER_ENTRY(SM, LAYER_ID(12), sm, forward_sm, NULL, NULL) +/*!< Split layer */ +LAYER_ENTRY(SPLIT, LAYER_ID(13), split, forward_split, NULL, NULL) +/*!< TimeDelay layer */ +LAYER_ENTRY(TIME_DELAY, LAYER_ID(14), time_delay, forward_time_delay, NULL, NULL) +/*!< TimeDistributed layer */ +LAYER_ENTRY(TIME_DISTRIBUTED, LAYER_ID(15), time_distributed, forward_time_distributed, NULL, NULL) +/*!< Concat Tensor layer */ +LAYER_ENTRY(CONCAT, LAYER_ID(16), concat, forward_concat, NULL, NULL) +/*!< GEMM layer */ +LAYER_ENTRY(GEMM, LAYER_ID(17), gemm, forward_gemm, NULL, NULL) +/*!< Upsample layer */ +LAYER_ENTRY(UPSAMPLE, LAYER_ID(18), upsample, forward_upsample, NULL, NULL) +/*!< Container layer for eltwise operations */ +LAYER_ENTRY(ELTWISE, LAYER_ID(19), eltwise, forward_eltwise, NULL, NULL) +/*!< Container layer for eltwise integer operations */ +LAYER_ENTRY(ELTWISE_INTEGER, LAYER_ID(20), eltwise_integer, NULL, NULL, NULL) +/*!< InstanceNormalization layer */ +LAYER_ENTRY(INSTANCENORMALIZATION, LAYER_ID(21), instanceNormalization, forward_instanceNormalization, NULL, NULL) +/*!< Pad layer */ +LAYER_ENTRY(PAD, LAYER_ID(22), pad, forward_pad, NULL, NULL) +/*!< Slice layer */ +LAYER_ENTRY(SLICE, LAYER_ID(23), slice, forward_slice, NULL, NULL) +/*!< Tile layer */ +LAYER_ENTRY(TILE, LAYER_ID(24), tile, forward_tile, NULL, NULL) +/*!< Container layer for reduce operations */ +LAYER_ENTRY(REDUCE, LAYER_ID(25), reduce, forward_reduce, NULL, NULL) +/*!< Recurrent Neural Network layer */ +LAYER_ENTRY(RNN, LAYER_ID(26), rnn, forward_rnn, NULL, NULL) +/*!< Resize layer */ +LAYER_ENTRY(RESIZE, LAYER_ID(27), resize, forward_resize, NULL, NULL) +/*!< Gather layer */ +LAYER_ENTRY(GATHER, LAYER_ID(28), gather, forward_gather, NULL, NULL) +/*!< Pack layer */ +LAYER_ENTRY(PACK, LAYER_ID(29), pack, forward_pack, NULL, NULL) +/*!< Unpack layer */ +LAYER_ENTRY(UNPACK, LAYER_ID(30), unpack, forward_unpack, NULL, NULL) +/*!< ArgMin & ArgMax layers */ +LAYER_ENTRY(ARGMINMAX, LAYER_ID(31), argminmax, NULL, NULL, NULL) +/*!< Cast Neural Network Layer */ +LAYER_ENTRY(CAST, LAYER_ID(33), cast, forward_cast, NULL, NULL) +/*!< iForest layer */ +LAYER_ENTRY(IFOREST, LAYER_ID(34), iforest, forward_iforest, NULL, NULL) +/*!< SVM Regressor layer */ +LAYER_ENTRY(SVMREG, LAYER_ID(35), svmreg, forward_svm_regressor, NULL, NULL) +/*!< ArrayFeatureExtractor layer */ +LAYER_ENTRY(ARRAYFEATUREEXTRACTOR, LAYER_ID(36), arrayfeatureextractor, forward_arrayfeatureextractor, NULL, NULL) +/*!< SVM Classifier (SVC) layer */ +LAYER_ENTRY(SVC, LAYER_ID(37), svc, forward_svc, NULL, NULL) +/*!< ZipMap layer */ +LAYER_ENTRY(ZIPMAP, LAYER_ID(38), zipmap, forward_zipmap, NULL, NULL) +/*!< Where layer */ +LAYER_ENTRY(WHERE, LAYER_ID(39), where, forward_where, NULL, NULL) +/*!< LinearClassifier layer */ +LAYER_ENTRY(LINEARCLASSIFIER, LAYER_ID(40), linearclassifier, forward_linearclassifier, NULL, NULL) +/*!< TreeEnsembleClassifier layer */ +LAYER_ENTRY(TREE_ENSEMBLE_CLASSIFIER, LAYER_ID(41), tree_ensemble_classifier, forward_tree_ensemble_classifier, NULL, NULL) +/*!< TopK layer */ +LAYER_ENTRY(TOPK, LAYER_ID(42), topK, forward_topK, NULL, NULL) +/*!< ReduceLogSumExp layer */ +LAYER_ENTRY(REDUCE_LOG_SUM_EXP, LAYER_ID(43), reduce_log_sum_exp, forward_reduce_log_sum_exp, NULL, NULL) +/*!< ReduceL1 layer */ +LAYER_ENTRY(REDUCE_L1, LAYER_ID(44), reduce_l1, forward_reduce_l1, NULL, NULL) +/*!< Runtime Lite Graph Wrapper layer */ +LAYER_ENTRY(LITE_GRAPH, LAYER_ID(45), lite_graph, NULL, NULL, NULL) +/*!< TreeEnsembleRegressor layer */ +LAYER_ENTRY(TREE_ENSEMBLE_REGRESSOR, LAYER_ID(46), tree_ensemble_regressor, forward_tree_ensemble_regressor, NULL, NULL) +/*!< GatherND layer */ +LAYER_ENTRY(GATHER_ND, LAYER_ID(67), gather_nd, forward_gather_nd, NULL, NULL) +/*!< MATMUL layer */ +LAYER_ENTRY(MATMUL, LAYER_ID(68), matmul, forward_dmatmul, NULL, NULL) +/*!< Deeply Quantized Dense Layers */ +LAYER_ENTRY(CONV2D_DQNN, LAYER_ID(48), conv2d_dqnn, forward_pw_is1os1ws1_bn, NULL, NULL) +LAYER_ENTRY(POOL_DQNN, LAYER_ID(49), pool_dqnn, forward_maxpool_is1os1, NULL, NULL) + +LAYER_ENTRY(DENSE_DQNN, LAYER_ID(50), dense_dqnn, forward_dense_is1os1ws1, NULL, NULL) +/*!< Reverse layer */ +LAYER_ENTRY(REVERSE, LAYER_ID(51), reverse, forward_reverse, NULL, NULL) +/*!< ScatterND layer */ +LAYER_ENTRY(SCATTER_ND, LAYER_ID(69), scatter_nd, forward_scatter_nd, NULL, NULL) + +/*!< TFLite wrapper */ +LAYER_ENTRY(TFLITE_WRAPPER, LAYER_ID(52), tflite_wrapper, NULL, NULL, NULL) + +/*****************************************************************************/ +/*!< Base Stateful Layer type */ +LAYER_ENTRY(STATEFUL, LAYER_STATEFUL_ID(0), stateful, NULL, NULL, NULL) +/*!< Long Short Time Memory layer */ +LAYER_ENTRY(LSTM, LAYER_STATEFUL_ID(1), lstm, forward_lstm, init_lstm, destroy_lstm) +/*!< Custom layer */ +LAYER_ENTRY(CUSTOM, LAYER_STATEFUL_ID(2), custom, NULL, NULL, NULL) +/*!< Gated Recurrent Unit layer */ +LAYER_ENTRY(GRU, LAYER_STATEFUL_ID(3), gru, forward_gru, init_gru, destroy_gru) + +/*!< Stateless Template layer declaration */ +/* LAYER_ENTRY(TEMPLATE, LAYER_ID(XX), template, forward_template, NULL, NULL) */ +/*!< Stateful Template layer declaration */ +/* LAYER_ENTRY(TEMPLATE, LAYER_STATEFUL_ID(XX), template, forward_template, init_template, destroy_template) */ + +#undef LAYER_ENTRY +#undef LAYER_ID +#undef LAYER_STATEFUL_ID diff --git a/lib/stai/libstai/include/layers_lite_graph.h b/lib/stai/libstai/include/layers_lite_graph.h new file mode 100644 index 000000000..c5ade8c7d --- /dev/null +++ b/lib/stai/libstai/include/layers_lite_graph.h @@ -0,0 +1,48 @@ +/** + ****************************************************************************** + * @file layers_lite_graph.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform lite graph layers wrapper interface + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_LITE_GRAPH_H +#define LAYERS_LITE_GRAPH_H + +#include "core_common.h" + +/*! + * @defgroup layers_lite_graph Lite Graph Wrapper Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_lite_graph + * @ingroup layers_lite_graph + * @brief Generic Lite Graph Layer Wrapper + * + * The type of lite graph is handled by the specific forward lite graph function. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lite_graph_ { + AI_NODE_COMMON_FIELDS_DECLARE + ai_handle* activations_map; /*!< array of pointers to shared activations memory pools */ + ai_handle* weights_map; /*!< array of pointers to shared weights memory pools */ +} ai_layer_lite_graph; + + +AI_API_DECLARE_END + +#endif /*LAYERS_LITE_GRAPH_H*/ diff --git a/lib/stai/libstai/include/layers_ml.h b/lib/stai/libstai/include/layers_ml.h new file mode 100644 index 000000000..792add9b0 --- /dev/null +++ b/lib/stai/libstai/include/layers_ml.h @@ -0,0 +1,89 @@ +/** + ****************************************************************************** + * @file layers_ml.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform ml layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_ML_H +#define LAYERS_ML_H + +#include "layers_common.h" + +/*! + * @defgroup layers_generic ML Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_ArrayFeatureExtractor + * @ingroup layers_ml + * @brief ai_layer_ArrayFeatureExtractor layer definition + * + * This layer select elements of the input tensor based on the indices passed. It is intended to be used + * by his associated forward function @ref forward_arrayfeatureextractor + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_arrayfeatureextractor_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_tensor* indices; /*!< Indices of corrisponding axis in axes*/ +} ai_layer_arrayfeatureextractor; + + +/*! + * @struct ai_layer_ZipMap + * @ingroup layers_ml + * @brief ai_layer_ZipMap layer definition + * + * This layer creates a map from the input and the attributes. + * The values are provided by the input tensor, while the keys are specified by the attributes. + * The user must provide keys in either classlabels_strings or classlabels_int64s (but not both). + * The columns of the tensor correspond one-by-one to the keys specified by the attributes. + * There must be as many columns as keys. + * It is intended to be used by his associated forward function @ref forward_zipmap. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_zipmap_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_bool has_classlabels_int; +} ai_layer_zipmap; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + + +/*! + * @brief select elements of the input tensor based on the indices passed. + * @ingroup layers_ml + * @param layer array feture extractor + */ +AI_INTERNAL_API +void forward_arrayfeatureextractor(ai_layer* layer); + + +/*! + * @brief creates a map from the inputs and the attributes + * @ingroup layers_ml + * @param layer zipmap + */ +AI_INTERNAL_API +void forward_zipmap(ai_layer* layer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_ML_H*/ diff --git a/lib/stai/libstai/include/layers_ml_iforest.h b/lib/stai/libstai/include/layers_ml_iforest.h new file mode 100644 index 000000000..90bf50945 --- /dev/null +++ b/lib/stai/libstai/include/layers_ml_iforest.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file layers_iforest.h + * @author AIS + * @brief header file of AI platform iForest layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_IFOREST_H +#define LAYERS_IFOREST_H + +#include "layers_common.h" + +/*! + * @defgroup layers_ml Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/* Allowed tests branch in the iTrees */ +typedef enum +{ + AI_IFOREST_BRANCH_LT_IDX = 0, + AI_IFOREST_BRANCH_LEQ_IDX, + AI_IFOREST_BRANCH_EQ_IDX, + AI_IFOREST_BRANCH_END, +} ai_iforest_branch_e; + + +/*! + * @struct ai_layer_iforest + * @ingroup layers_iforest + * @brief iForest layer + * + * The type of iforest function is handled by the specific forward function + * @ref forward_iforest + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_iforest_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float global_average_path_length; /*!< global average path length used to normalized average path length*/ + ai_float score_threshold; /*!< score threshold used to center the score around 0 */ +} ai_layer_iforest; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the iforest ML algorithm. + * @ingroup layers_iforest + * @param layer iforest layer + */ +AI_INTERNAL_API +void forward_iforest(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_IFOREST_H*/ diff --git a/lib/stai/libstai/include/layers_ml_linearclassifier.h b/lib/stai/libstai/include/layers_ml_linearclassifier.h new file mode 100644 index 000000000..6312e9e5e --- /dev/null +++ b/lib/stai/libstai/include/layers_ml_linearclassifier.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file layers_ml_linearclassifier.h + * @author SRA + * @brief header file of AI platform LinearClassifier datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_LINEARCLASSIFIER_H +#define LAYERS_LINEARCLASSIFIER_H + +#include "layers_common.h" +#include "layers_nl.h" + +/*! + * @defgroup layers_linearclassifier Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/*! + * @struct ai_layer_linearclassifier + * @ingroup layers_linearclassifier + * @brief Linearclassifier layer + * + * The type of svmreg function is handled by the specific forward function + * @ref forward_linearclassifier + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_linearclassifier_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_nl nl_func; /*!< function pointer to non linear transform */ \ + ai_bool multi_class; /*!< Indicates whether to do OvR or multinomial */ + ai_bool has_classlabels_int; /*!< if True, LinearClassifier returns classlabels int, else classlabels string */ + +} ai_layer_linearclassifier; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the LinearClassifier ML operator. + * @ingroup layers_linaerclassifier + * @param layer linear classifier layer + */ +AI_INTERNAL_API +void forward_linearclassifier(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_LINEARCLASSIFIER_H*/ diff --git a/lib/stai/libstai/include/layers_ml_svc.h b/lib/stai/libstai/include/layers_ml_svc.h new file mode 100644 index 000000000..8cc742f9a --- /dev/null +++ b/lib/stai/libstai/include/layers_ml_svc.h @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file layers_svc.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform SVM Classifier (SVC) datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_SVC_H +#define LAYERS_SVC_H + +#include "layers_common.h" + +/*! + * @defgroup layers_svc Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/* SVM classifier (SVC) kernel types */ +typedef enum ai_svc_kernel_e_ { + AI_SVC_KERNEL_LINEAR = 0, + AI_SVC_KERNEL_POLYNOMIAL, + AI_SVC_KERNEL_RBF, + AI_SVC_KERNEL_SIGMOID, + AI_SVC_KERNEL_UNSUPPORTED +} ai_svc_kernel_e; + + +/*! + * @struct ai_layer_svc + * @ingroup layers_svc + * @brief SVM Classifier (SVC) layer + * + * The type of svc function is handled by the specific forward function + * @ref forward_svc + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_svc_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float gamma; /*!< kernel coefficient for rbf, polynomial and sigmoid functions */ + ai_float coef0; /*!< term in polynomial and sigmoid functions */ + ai_u32 degree; /*!< polynomial function degree */ + ai_svc_kernel_e kernel_type; /*!< kernel type : see ai_svm_kernel_e */ + ai_bool proba_support; /*!< whether or not use the parameters learned in Platt scaling */ + ai_bool has_classlabels_int; /*!< if True, SVC returns classlabels int, else classlabels string */ +} ai_layer_svc; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the SVM Classifier ML operator. + * @ingroup layers_svc + * @param layer svm classifier layer + */ +AI_INTERNAL_API +void forward_svc(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_SVC_H*/ diff --git a/lib/stai/libstai/include/layers_ml_svmregressor.h b/lib/stai/libstai/include/layers_ml_svmregressor.h new file mode 100644 index 000000000..444d76e9b --- /dev/null +++ b/lib/stai/libstai/include/layers_ml_svmregressor.h @@ -0,0 +1,78 @@ +/** + ****************************************************************************** + * @file layers_svmregressor.h + * @author AIS + * @brief header file of AI platform SVM Regressor datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_SVMREGRESSOR_H +#define LAYERS_SVMREGRESSOR_H + +#include "layers_common.h" + +/*! + * @defgroup layers_svmreg Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/* SVM regressor kernel types */ +typedef enum ai_svm_kernel_e_ { + AI_SVMREG_KERNEL_LINEAR = 0, + AI_SVMREG_KERNEL_POLYNOMIAL, + AI_SVMREG_KERNEL_RBF, + AI_SVMREG_KERNEL_SIGMOID, + AI_SVMREG_KERNEL_UNSUPPORTED, +} ai_svm_kernel_e; + + +/*! + * @struct ai_layer_svmreg + * @ingroup layers_svmreg + * @brief SVM Regressor layer + * + * The type of svmreg function is handled by the specific forward function + * @ref forward_svm_regressor + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_svmreg_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float intercept; /*!< constant used in the decision function */ + ai_float gamma; /*!< kernel coefficient for rbf, polynomial and sigmoid functions */ + ai_float coef0; /*!< term in polynomial and sigmoid functions */ + ai_u32 degree; /*!< polynomial function degree */ + ai_svm_kernel_e kernel_type; /*!< kernel type : see ai_svm_kernel_e */ +} ai_layer_svmreg; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the SVM Regressor ML operator. + * @ingroup layers_svmreg + * @param layer svm regressor layer + */ +AI_INTERNAL_API +void forward_svm_regressor(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_SVMREGRESSOR_H*/ diff --git a/lib/stai/libstai/include/layers_ml_treeensembleclassifier.h b/lib/stai/libstai/include/layers_ml_treeensembleclassifier.h new file mode 100644 index 000000000..5853ea626 --- /dev/null +++ b/lib/stai/libstai/include/layers_ml_treeensembleclassifier.h @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file layers_ml_treeensembleclassifier.h + * @author AIS + * @brief header file of AI platform TreeEnsembleClassifier datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021-2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_TREE_ENSEMBLE_CLASSIFIER_H +#define LAYERS_TREE_ENSEMBLE_CLASSIFIER_H + +#include "layers_common.h" +#include "layers_nl.h" + + + +/*! + * @defgroup layers_ml_treensembleclassifier Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/* Error return codes */ +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_NO 0 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_WRONG_IDX_FMT -1 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNFOUND_LEAF -2 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNSUPPORTED_BRANCH -3 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNSUPPORTED_FEATURE -4 + +#define AI_TREE_ENSEMBLE_CLASSIFIER_DEPTH_MAX 10000 + + +/* Type of condition in the TreeEnsembleClassifier*/ +typedef enum +{ + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_LT_IDX = 0, + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_LEQ_IDX, + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_EQ_IDX, + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_END, +} ai_tree_ensenble_classifier_branch_e; + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tree_ensemble_classifier_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_nl nl_func; + uint8_t all_weights_are_positive; + ai_float nodes_values_scale; + ai_float nodes_values_offset; + ai_float class_weights_scale; + ai_float class_weights_offset; +} ai_layer_tree_ensemble_classifier; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the TreeEnsembleClassifier ML operator. + * @ingroup layers_svmreg + * @param layer tree ensemble classifier layer + */ +AI_INTERNAL_API +void forward_tree_ensemble_classifier(ai_layer *pLayer); + +AI_INTERNAL_API +ai_i32 decodeEstimator_LEQ_8Bits(const ai_float *pDataIn, + ai_float *pOutDataScores, + const ai_u8 *pFeatureIdxForEstimator, + const ai_float *pValuesForEstimator, + const ai_u8 *pTrueIdxForEstimator, + const ai_u8 *pFalseIdxForEstimator, + const ai_handle pClassWeightsForEstimator, + const ai_array_format classWeightsFormat, + const ai_u8 *pClassNodeIdsForEstimator, + const ai_u16 nbClassWithCurrentEstimator, + const ai_u8 *pClassIdsForEstimator); + +AI_INTERNAL_API +ai_i32 decodeEstimator_LEQ_16Bits(const ai_float *pDataIn, + ai_float *pOutDataScores, + const ai_u8 *pFeatureIdxForEstimator, + const ai_float *pValuesForEstimator, + const ai_u16 *pTrueIdxForEstimator, + const ai_u16 *pFalseIdxForEstimator, + ai_handle pClassWeightsForEstimator, + const ai_array_format classWeightsFormat, + const ai_u16 *pClassNodeIdsForEstimator, + const ai_u16 nbClassWithCurrentEstimator, + const ai_u16 *pClassIdsForEstimator); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_TREE_ENSEMBLE_CLASSIFIER_H*/ diff --git a/lib/stai/libstai/include/layers_ml_treeensembleregressor.h b/lib/stai/libstai/include/layers_ml_treeensembleregressor.h new file mode 100644 index 000000000..c4be1e631 --- /dev/null +++ b/lib/stai/libstai/include/layers_ml_treeensembleregressor.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file layers_svmregressor.h + * @author AIS + * @brief header file of AI platform SVM Regressor datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_TREE_ENSEMBLE_REGRESSOR_H +#define LAYERS_TREE_ENSEMBLE_REGRESSOR_H + +#include "layers_common.h" +#include "layers_ml_treeensembleclassifier.h" +#include "layers_nl.h" + +/*! + * @defgroup layers_svmreg Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tree_ensemble_regressor_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_nl nl_func; + uint8_t all_weights_are_positive; + ai_float nodes_values_offset; + ai_float nodes_values_scale; + ai_float target_weights_offset; + ai_float target_weights_scale; +} ai_layer_tree_ensemble_regressor; + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the TreeEnsembleRegressor ML operator. + * @ingroup layers_svmreg + * @param layer tree ensemble regressor layer + */ +AI_INTERNAL_API +void forward_tree_ensemble_regressor(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_SVMREGRESSOR_H*/ diff --git a/lib/stai/libstai/include/layers_nl.h b/lib/stai/libstai/include/layers_nl.h new file mode 100644 index 000000000..ca96e58e3 --- /dev/null +++ b/lib/stai/libstai/include/layers_nl.h @@ -0,0 +1,1130 @@ +/** + ****************************************************************************** + * @file layers_nl.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform nonlinearity layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_NL_H +#define LAYERS_NL_H + +#include "layers_common.h" +#include "lite_internal_apis.h" + +/*! + * @defgroup layers_nl Normalization Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_nl + * @ingroup layers_nl + * @brief Generic Nonlinearity layer + * + * The type of nonlinearity is handled by the specific forward function. + * It is a sequential layer. see @ref ai_layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_nl_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* nl_params; /*!< associated parameters array */ +} ai_layer_nl; + +/*! + * @struct ai_layer_sm + * @ingroup layers_nl + * @brief Softmax Nonlinearity layer + * + * It is a sequential layer. see @ref ai_layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_sm_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* nl_params; /*!< associated parameters array */ + ai_i16 axis; +} ai_layer_sm; + +/*! + * @typedef (*func_nl) + * @ingroup layers_nl + * @brief Fuction pointer for generic non linear transform + * this function pointer abstracts a generic non linear layer. + * see @ref nl_func_tanh_array_f32 and similar as examples. + */ +//typedef void (*func_nl)(ai_array *out, const ai_array *in, +// const ai_size size, const ai_handle params); +typedef void (*func_nl)(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Softmax pooling computed on a single float channel + * @ingroup layers_nl + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param channel_size number of elements of the input channel + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sm_channel_f32(ai_tensor *out, const ai_tensor *in, + const ai_size channel_size, const ai_handle params); + +/*! + * @brief Softmax normalization computed on an array of float channels + * @ingroup layers_nl + * @param out opaque handler to float output channel array + * @param in opaque handler to float input channel array + * @param in_size total size (number of elements) to process on the input + * @param channel_size number of elements of the input channel + * @param in_channel_step number of elements to move to next input element + * @param out_channel_step number of elements to move to next output element + */ +AI_INTERNAL_API +void nl_func_sm_array_f32(ai_tensor *out, ai_tensor *in, + const ai_size in_size, + const ai_size channel_size, + const ai_size in_channel_step, + const ai_size out_channel_step); + +/*! + * @brief Softmax zero pooling computed on a single float channel + * @ingroup layers_nl + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param channel_size number of elements of the input channel + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sm_zero_channel_f32(ai_tensor *out, const ai_tensor *in, + const ai_size channel_size, const ai_handle params); + +/*! + * @brief Probit non linearity + * @ingroup layers_nl + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param channel_size number of elements of the input channel + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_probit_f32(ai_tensor *out, const ai_tensor *in, + const ai_size channel_size, const ai_handle params); + + +/*! + * @brief Computes the tanh function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_tanh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the tanh function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_tanh_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + + +/*! + * @brief Computes the sigmoid function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sigmoid_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sigmoid function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sigmoid_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + + +/*! + * @brief Computes the hard sigmoid function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_hard_sigmoid_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); +/*! + * @brief Computes the logistic function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_logistic_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); +/*! + * @brief Computes the swish function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_swish_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hard swish function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_hard_swish_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the gelu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_gelu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the absolute value function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_abs_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_cos_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_acos_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hyperbolic cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_cosh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse hyperbolic cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_acosh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sin_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_asin_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hyperbolic sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sinh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse hyperbolic sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_asinh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the tangent function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_tan_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse tangent function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_atan_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse hyperbolic tangent function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_atanh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the error function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_erf_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the natural logarithm function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_log_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the reciprocal square root function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_rsqrt_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the squarefunction on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_square_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the floor function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_floor_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the ceil function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_ceil_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the rounding function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_round_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the exponential function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_exp_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sign negation function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_neg_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sign negation function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_not_array_bool(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + + +/*! + * @brief Computes the reciprocal function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_reciprocal_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the square root function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sqrt_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the soft plus function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + */ +AI_INTERNAL_API +void nl_func_soft_plus_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the soft sign function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_soft_sign_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sign function on a single float element. + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + */ +AI_INTERNAL_API +void nl_func_sign_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the clip function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_clip_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hardmax function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param axis direction of the max index to be searched + */ +AI_INTERNAL_API +void nl_func_hardmax_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_shape *shape, const ai_handle params); + +/*! + * @brief Computes the generic relu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_generic_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the thresholded relu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_thresholded_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the relu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the relu function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the relu function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +void nl_func_relu_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the clip function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +void nl_func_clip_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the activation function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to generated and used LUT + */ +void nl_func_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the elu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_elu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the max relu function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_max_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the selu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_selu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the prelu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param slope opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size size of the input data in bytes + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_prelu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the prelu function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +void nl_func_prelu_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/******************************************************************************/ +/** Forward Functions Section **/ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a ReLU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point ReLU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer-quantized ReLU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a clip integer-quantized nonlinear layer. + * @ingroup layers_nl + * @param pLayer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_clip_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a ReLU6 nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_thresholded(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point max ReLU layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_max_fixed(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a ELU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_elu(ai_layer* layer); + +/*! + * @brief Computes the activations of a SELU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_selu(ai_layer* layer); + +/*! + * @brief Computes the activations of a PRELU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_prelu(ai_layer* layer); + +/*! + * @brief Computes the activations of a binary tanh (sign) nonlinear layer. + * @ingroup layers + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sign(ai_layer* layer); + +/*! + * @brief Computes the activations of a clip nonlinear layer. + * @ingroup layers + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_clip(ai_layer* layer); + +/*! + * @brief Computes the activations of a sigmoid nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sigmoid(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point sigmoid nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sigmoid_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a hard sigmoid nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_hard_sigmoid(ai_layer* layer); + +/*! + * @brief Computes the activations of a swish nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_swish(ai_layer* layer); + +/*! + * @brief Computes the activations of a hard swish nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_hard_swish(ai_layer* layer); + +/*! + * @brief Computes the activations of a gelu nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_gelu(ai_layer* layer); + +/*! + * @brief Computes the activations of an exponential nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_exp(ai_layer* layer); + +/*! + * @brief Computes the activations of an square root nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sqrt(ai_layer* layer); + +/*! + * @brief Computes the activations of a soft plus nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_soft_plus(ai_layer* layer); + +/*! + * @brief Computes the activations of a soft sign nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_soft_sign(ai_layer* layer); + +/*! + * @brief Computes the activations of a cosine (cos) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_cos(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse cosine (acos) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_acos(ai_layer* layer); + +/*! + * @brief Computes the activations of a hyperbolic cosine (cosh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_cosh(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse hyperbolic cosine (acosh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_acosh(ai_layer* layer); + +/*! + * @brief Computes the activations of a sine (sin) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sin(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse sine (asin) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_asin(ai_layer* layer); + +/*! + * @brief Computes the activations of a hyperbolic sine (sinh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sinh(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse hyperbolic sine (asinh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_asinh(ai_layer* layer); + +/*! + * @brief Computes the activations of a tangent (tan) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_tan(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse tangent (atan) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_atan(ai_layer* layer); + +/*! + * @brief Computes the activations of a hyperbolic tangent (tanh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_tanh(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse hyperbolic tangent (atanh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_atanh(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point tanh nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_tanh_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a error function (erf) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_erf(ai_layer* layer); + +/*! + * @brief Computes the activations of a natural logarithm (log) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_log(ai_layer* layer); + +/*! + * @brief Computes the activations of a reciprocal square root (rsqrt) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_rsqrt(ai_layer* layer); + +/*! + * @brief Computes the activations of a square layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_square(ai_layer* layer); + +/*! + * @brief Computes the activations of an absolute value (abs) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_abs(ai_layer* layer); + +/*! + * @brief Computes the activations of a ceil layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_ceil(ai_layer* layer); + +/*! + * @brief Computes the activations of a floor layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_floor(ai_layer* layer); + +/*! + * @brief Computes the activations of a rounding layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_round(ai_layer* layer); + +/*! + * @brief Computes the activations of a sign negation (neg) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_neg(ai_layer* layer); +/*! + * @brief Computes the activations of a sign negation (not) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_not(ai_layer* layer); + + +/*! + * @brief Computes the activations of a reciprocal layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_reciprocal(ai_layer* layer); + +/*! + * @brief Hardmax on an input tensors + * @ingroup layers_generic + * @param layer the hardmax layer + */ +AI_INTERNAL_API +void forward_hardmax(ai_layer* layer); + +/*! + * @brief Computes the activations of a softmax nonlinear layer. + * @ingroup layers_nl + * @param layer the softmax (sm) layer + */ +AI_INTERNAL_API +void forward_sm(ai_layer* layer); + +/*! + * @brief Computes the activations of a softmax nonlinear layer (integer version). + * @ingroup layers_nl + * @param layer the softmax (sm) layer + */ +AI_INTERNAL_API +void forward_sm_integer(ai_layer* layer); + +/*! + * @brief Computes the activations of an integer quantized nonlinear layer. + * Non linear operation is function of used LUT defined through + * (pLayer->nl_params->data) + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_nl_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer quantized PReLu. + * Slope params are located like weights, not params because they are + * quantized + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_prelu_integer(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_NL_H*/ diff --git a/lib/stai/libstai/include/layers_norm.h b/lib/stai/libstai/include/layers_norm.h new file mode 100644 index 000000000..e78c962cc --- /dev/null +++ b/lib/stai/libstai/include/layers_norm.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file layers_norm.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform normalization layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_NORM_H +#define LAYERS_NORM_H + +#include "layers_common.h" + +/*! + * @defgroup layers_norm Normalization Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_bn + * @ingroup layers_norm + * @brief Batch normalization (scale with bias) layer + */ +typedef ai_layer_base ai_layer_bn; + +/*! + * @struct ai_layer_lrn + * @ingroup layers_norm + * @brief Local Response Normalization layer + * + * Divides each element by a scale factor computed + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lrn_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_u32 local_size; /*!< size of the normalization window */ + ai_float k; /*!< bias term */ + ai_float alpha; /*!< input scale */ + ai_float beta; /*!< scale exponent */ +} ai_layer_lrn; + +/*! + * @enum ai_norm_type_e + * @ingroup layers_norm + * @brief store the type of normalization algorithm to apply +*/ +typedef enum ai_norm_type_ { + NONE = 0, + L1 = 1, + L2 = 2, + MAX = 3, +} ai_norm_type_e; + +/*! + * @struct ai_layer_norm + * @ingroup layers_norm + * @brief Lp Normalization layer + * + * Normalizes the tensor along the 'axis' direction using the Lp norm. + * Optionally divides the result by the number of the elements. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_norm_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_idx axis; /*! normalization axis */ + ai_float exponent; /*!< normalization exponent p */ + ai_bool scale; /*!< multiplies by the pth root of the number of elements */ + ai_norm_type_e norm_type; +} ai_layer_norm; + + +/*! + * @brief Local response normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param pad amount of padding for the channels + */ +AI_INTERNAL_API +void func_lrn_array_f32(ai_handle out, const ai_handle in, + const ai_size in_size, const ai_size channel_size, + const ai_i32 pad, const ai_float k, + const ai_float alpha, const ai_float beta); + +/*! + * @brief Lp normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param exponent p exponent for the Lp normalization + * @param axis_stride stride (in array elements) of the normalization axis + * @param axis_size size of the normalization axis + * @param outer_size number of tensor slices (including the normalization axis) + * on which compute the normalization + */ +AI_INTERNAL_API +void func_norm_array_f32(ai_handle out, const ai_handle in, + const ai_float exponent, + const ai_float norm, + const ai_size axis_stride, + const ai_size axis_size, + const ai_size outer_size); + +/*! + * @brief Max normalization computed on float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param axis_stride stride (in array elements) of the normalization axis + * @param axis_size size of the normalization axis + * @param outer_size number of tensor slices (including the normalization axis) + */ +AI_INTERNAL_API +void func_norm_max_array_f32(ai_handle out, const ai_handle in, + const ai_float norm, + const ai_size axis_size, + const ai_size n_el); + +/*! + * @brief Fast L2 normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param axis_size size of the normalization axis + * @param n_el total number of elements in the tensor + */ +AI_INTERNAL_API +void func_norm_l2_fast_array_f32(ai_handle out, const ai_handle in, + const ai_float norm, + const ai_size axis_size, + const ai_size outer_size); + +/*! + * @brief Fast L1 normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param axis_size size of the normalization axis + * @param n_el total number of elements in the tensor + */ +AI_INTERNAL_API +void func_norm_l1_fast_array_f32(ai_handle out, const ai_handle in, + const ai_float norm, + const ai_size axis_size, + const ai_size n_el); + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a batchnorm (scale + bias) layer. + * @ingroup layers_norm + * @param layer the batch normalization (bn) layer + */ +AI_INTERNAL_API +void forward_bn(ai_layer* layer); + +/*! + * @brief Computes the activations of a batchnorm (scale + bias) layer with + * integer format + * @ingroup layers_norm + * @param layer the batch normalization (bn) layer + */ +AI_INTERNAL_API +void forward_bn_integer(ai_layer* layer); + +/*! + * @brief Computes the activations of a Local Response Normalization Layer. + * @ingroup layers_norm + * @param layer the local response normalization (lrn) layer + */ +AI_INTERNAL_API +void forward_lrn(ai_layer* layer); + +/*! + * @brief Computes the activations of a normalization layer. + * @ingroup layers_norm + * @param layer the normalization (norm) layer + */ +AI_INTERNAL_API +void forward_norm(ai_layer* layer); + +/*! + * @brief Batch Normalization with 16-bit input, 16-bit threshold and binary output. + * It is implemented using a threshold, and this is possible because the output is binary. + * @param layer the batch normalization layer + */ +AI_INTERNAL_API +void forward_bn_is16os1ws16(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_NORM_H*/ diff --git a/lib/stai/libstai/include/layers_pad_dqnn.h b/lib/stai/libstai/include/layers_pad_dqnn.h new file mode 100644 index 000000000..29354d23b --- /dev/null +++ b/lib/stai/libstai/include/layers_pad_dqnn.h @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file layers_pad_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN padding datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_PADDING_DQNN_H +#define LAYERS_PADDING_DQNN_H + +#include "layers_common.h" +#include "layers_generic.h" + +/*! + * @defgroup layers_generic_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + + +/*! + * @brief Handles padding with binary input and binary output + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_is1os1(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_PADDING_DQNN_H*/ diff --git a/lib/stai/libstai/include/layers_pad_generic.h b/lib/stai/libstai/include/layers_pad_generic.h new file mode 100644 index 000000000..6eeff1d67 --- /dev/null +++ b/lib/stai/libstai/include/layers_pad_generic.h @@ -0,0 +1,71 @@ +/** + ****************************************************************************** + * @file layers_pad_generic.h + * @author AIS + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_PADDING_DQNN_H +#define LAYERS_PADDING_DQNN_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles generic padding in constant mode + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_constant(ai_layer *pLayer); + +/*! + * @brief Handles generic padding in edge mode + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_edge(ai_layer *pLayer); + +/*! + * @brief Handles generic padding in reflect mode + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_reflect(ai_layer *pLayer); + + +/*! + * @brief Handles generic padding in constant mode Channel 1st 8bit + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_8bit_ch1st_3x3_constant(ai_layer* pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_PAD_GENERIC_H*/ diff --git a/lib/stai/libstai/include/layers_pool.h b/lib/stai/libstai/include/layers_pool.h new file mode 100644 index 000000000..e24c04195 --- /dev/null +++ b/lib/stai/libstai/include/layers_pool.h @@ -0,0 +1,413 @@ +/** + ****************************************************************************** + * @file layers_pool.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform pooling layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_POOL_H +#define LAYERS_POOL_H + +#include "layers_common.h" +#include "lite_maxpool_dqnn.h" +#include "lite_pool_f32.h" + +/*! + * @defgroup layers_pool Pooling Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_pool + * @ingroup layers_pool + * @brief Pooling layer + * + * The type of pooling function is handled by the specific forward function + * @ref forward_pool + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pool_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_2d pool_size; /*!< pooling size */ + ai_shape_2d pool_stride; /*!< pooling stride */ + ai_shape pool_pad; /*!< pooling pad, y,x border sizes */ + ai_u8 count_include_pad; /*!< include pad flag */ +} ai_layer_pool; + + + +/*! + * @brief Max Pooling on a 8/16 bits fixed point data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_fixed(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Max Pooling on a 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_integer(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Max Pooling on a signed 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_integer_INT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Max Pooling on a unsigned 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_integer_UINT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Average Pooling on a 8/16 bits fixed point data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_fixed(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + + /*! + * @brief Average Pooling on a 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_integer(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + + /*! + * @brief Average Pooling on a signed 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_integer_INT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + + /*! + * @brief Average Pooling on a unsigned 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_integer_UINT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a max pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point max pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with int8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_INT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with int8 I/O. Optimized for HSP + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_hsp_INT8(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with int8 I/O. Optimized for HSP: 2 Step variant for bigger tensors + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_hsp_2step_INT8(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with uint8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_UINT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with int16 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_INT16(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with uint16 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_UINT16(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an average pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap(ai_layer* layer); + + +/*! + * @brief Computes the activations of a fixed point average pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized average pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an average pooling layer. Optimized for HSP + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_hsp_INT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an average pooling layer. Optimized for HSP + * Variant for larger tensors + * @ingroup layers_pool + * @param layer the pooling (pool) layer, + */ +AI_INTERNAL_API +void forward_ap_hsp_2step_INT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized average pooling layer + * with int8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_integer_INT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized average pooling layer + * with uint8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_integer_UINT8(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_POOL_H*/ diff --git a/lib/stai/libstai/include/layers_pool_dqnn.h b/lib/stai/libstai/include/layers_pool_dqnn.h new file mode 100644 index 000000000..a5bcf6805 --- /dev/null +++ b/lib/stai/libstai/include/layers_pool_dqnn.h @@ -0,0 +1,68 @@ +/** + ****************************************************************************** + * @file layers_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN pool datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_POOL_DQNN_H +#define LAYERS_POOL_DQNN_H + +#include "layers_common.h" +#include "layers_pool.h" + +/*! + * @defgroup layers_pool_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + + +/*! + * @struct ai_layer_pool_dqnn + * @ingroup layers_pool_dqnn + * @brief pool_dqnn layer + * + * @ref forward_maxpool_is1os1 + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pool_dqnn_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_2d pool_size; /*!< pooling size */ + ai_shape_2d pool_stride; /*!< pooling stride */ + ai_shape pool_pad; /*!< pooling pad, y,x border sizes */ +// ai_u32 pad_value; /*!< pooling pad value */ +} ai_layer_pool_dqnn; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles max pooling with binary input and binary output + * @ingroup layers_pool_dqnn + * @param layer conv2d_pool layer + */ +AI_INTERNAL_API +void forward_maxpool_is1os1(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_POOL_DQNN_H*/ diff --git a/lib/stai/libstai/include/layers_resize.h b/lib/stai/libstai/include/layers_resize.h new file mode 100644 index 000000000..820158d44 --- /dev/null +++ b/lib/stai/libstai/include/layers_resize.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file layers_resize.h + * @author STMicroelectronics + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_RESIZE_H +#define LAYERS_RESIZE_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles generic resizing in nearest mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_if32of32(ai_layer* layer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_bilinear_if32of32(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_nearest_if32of32(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_bilinear_is16os16(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_nearest_is16os16(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_bilinear_is8os8(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_nearest_is8os8(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_PAD_GENERIC_H*/ diff --git a/lib/stai/libstai/include/layers_rnn.h b/lib/stai/libstai/include/layers_rnn.h new file mode 100644 index 000000000..c3e67974b --- /dev/null +++ b/lib/stai/libstai/include/layers_rnn.h @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file layers_rnn.h + * @author AST Embedded Analytics Research Platform + * @brief header file of RNN layers + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_RNN_H +#define LAYERS_RNN_H + +#include "layers_common.h" +#include "layers_nl.h" + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_lstm + * @ingroup layers + * @brief LSTM layer with generic nonlinearities and peephole connections + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lstm_ { + AI_LAYER_STATEFUL_FIELDS_DECLARE + ai_size n_units; /**< size of the hidden RNN state */ + func_nl activation_nl; /**< activation nonlinearity (input to cell) */ + func_nl recurrent_nl; /**< recurrent nonlinearity (hidden to cell) */ + func_nl out_nl; /**< output nonlinearity (cell to hidden) */ + ai_bool go_backwards; /**< process reversed input */ + ai_bool return_state; /**< return state */ + ai_bool reverse_seq; /**< reverse output sequence */ + ai_float cell_clip; /**< cell clip value */ +} ai_layer_lstm; + +/*! + * @struct ai_layer_gru + * @ingroup layers + * @brief Gated Recurrent Unit (GRU) layer with generic nonlinearities + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gru_ { + AI_LAYER_STATEFUL_FIELDS_DECLARE + ai_size n_units; /**< size of the hidden RNN state */ + func_nl activation_nl; /**< activation nonlinearity (input to cell) */ + func_nl recurrent_nl; /**< recurrent nonlinearity (hidden to cell) */ + ai_bool reset_after; + ai_bool return_state; + ai_bool go_backwards; /**< process reversed input */ + ai_bool reverse_seq; /**< reverse output sequence */ +} ai_layer_gru; + +/*! + * @struct ai_layer_rnn + * @ingroup layers + * @brief Simple Recurrent Neural Network (RNN) layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_rnn_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_size n_units; /**< size of the hidden RNN state */ + func_nl activation_nl; /**< activation nonlinearity (input to hidden) */ + ai_bool go_backwards; /**< process reversed input */ + ai_bool reverse_seq; /**< reverse output sequence */ + ai_bool return_state; +} ai_layer_rnn; + + +/*! + * @brief Allocate states for a stateful network. + * @ingroup layers + * + * Function used to allocate states of a stateful network. + */ +void _allocate_states(ai_float **states, ai_u32 size_in_bytes); + + +/*! + * @brief Deallocate states for a stateful network. + * @ingroup layers + * + * Function used to deallocate states of a stateful network. + */ +void _deallocate_states(ai_float **states); + + +/*! + * @brief Initialize a Long-Short Term Memory (LSTM) layer. + * @ingroup layers + * + * Function used to initialize lstm internal state + */ +AI_INTERNAL_API +void init_lstm(ai_layer * layer); + + +/*! + * @brief Destroy a Long-Short Term Memory (LSTM) layer state. + * @ingroup layers + * + * Function used to destroy lstm internal state + */ +AI_INTERNAL_API +void destroy_lstm(ai_layer * layer); + + +/*! + * @brief Computes the activations of a Long-Short Term Memory (LSTM) layer. + * @ingroup layers + * + * Implements a Long-Short Term Layer with peephole connections: + * \f{eqnarray*}{ + * i_t &=& \sigma_a(x_t W_{xi} + h_{t-1} W_{hi} + * + w_{ci} \odot c_{t-1} + b_i)\\ + * f_t &=& \sigma_a(x_t W_{xf} + h_{t-1} W_{hf} + * + w_{cf} \odot c_{t-1} + b_f)\\ + * c_t &=& f_t \odot c_{t - 1} + * + i_t \odot \sigma_r(x_t W_{xc} + h_{t-1} W_{hc} + b_c)\\ + * o_t &=& \sigma_a(x_t W_{xo} + h_{t-1} W_{ho} + w_{co} \odot c_t + b_o)\\ + * h_t &=& o_t \odot \sigma_o(c_t) + * \f} + * where \f$\sigma_a\f$ is the activation nonlinearity, \f$\sigma_r\f$ is the + * recurrent nonlinearity and \f$\sigma_o\f$ is the out nonlinearity. The + * \f$W_x\f$, \f$W_h\f$ and \f$W_c\f$ weights are sliced from the kernel, + * recurrent and peephole weights. + * + * @param layer the LSTM layer + */ +AI_INTERNAL_API +void forward_lstm(ai_layer * layer); + +AI_INTERNAL_API +void forward_lstm_is8os8ws8(ai_layer * layer); + + +/*! + * @brief Initialize a Gated Recurrent Unit (GRU) layer. + * @ingroup layers + * + * Function used to initialize gru internal state + */ +AI_INTERNAL_API +void init_gru(ai_layer * layer); + + +/*! + * @brief Destroy a Gated Recurrent Unit (GRU) layer state. + * @ingroup layers + * + * Function used to destroy gru internal state + */ +AI_INTERNAL_API +void destroy_gru(ai_layer * layer); + +/*! + * @brief Computes the activations of a Gated Recurrent Unit (GRU) layer. + * @ingroup layers + * + * Implements a Gated Recurrent Unit with the formula: + * \f{eqnarray*}{ + * r_t &=& \sigma_a(x_t W_{xr} + h_{t - 1} W_{hr} + b_r) \\ + * z_t &=& \sigma_a(x_t W_{xz} + h_{t - 1} W_{hz} + b_z) \\ + * c_t &=& \sigma_r(x_t W_{xc} + r_t \odot (h_{t - 1} W_{hc} + b_{hc}) + b_c) + * \qquad \textnormal{when reset after is true} \\ + * c_t &=& \sigma_r(x_t W_{xc} + (r_t \odot h_{t - 1}) W_{hc} + b_{hc} + b_c) + * \qquad \textnormal{when reset after is false (default)} \\ + * h_t &=& (1 - z_t) \odot h_{t - 1} + z_t \odot c_t + * \f} + * where \f$\sigma_a\f$ is the activation nonlinearity and \f$\sigma_r\f$ is + * the recurrent nonlinearity. The weights are sliced from the kernel and + * recurrent weights. + * + * @param layer the GRU layer + */ +AI_INTERNAL_API +void forward_gru(ai_layer * layer); + +/*! + * @brief Computes the activations of a Recurrent Neural Network (RNN) layer. + * @ingroup layers + * + * Implements a recurrent layer with the formula: + * \f{eqnarray*}{ + * h_t &=& \sigma_a(x_t W_{xr} + h_{t - 1} W_{hr} + b_r) + * \f} + * where \f$\sigma_a\f$ is the activation nonlinearity. The weights are sliced + * from the kernel and recurrent weights. + * + * @param layer the RNN layer + */ +AI_INTERNAL_API +void forward_rnn(ai_layer * layer); + +AI_API_DECLARE_END + +#endif /* LAYERS_RNN_H */ diff --git a/lib/stai/libstai/include/layers_sm.h b/lib/stai/libstai/include/layers_sm.h new file mode 100644 index 000000000..bf2b7ffdd --- /dev/null +++ b/lib/stai/libstai/include/layers_sm.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file layers_sm.h + * @author STMicroelectronics + * @brief header file of AI platform non softmax layer datatype + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_SM_H +#define LAYERS_SM_H + +#include "layers_common.h" + +/*! + * @defgroup layers SoftMax Layer Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @brief Softmax normalization computed on an array of fixed point channels + * @ingroup layers_sm + * @param out opaque handler to output channel array + * @param in opaque handler to input channel array + * @param in_size total size (number of elements) to process on the input + * @param channel_size number of elements of the input channel + * @param in_channel_step number of elements to move to next input element + * @param out_channel_step number of elements to move to next output element + */ +AI_INTERNAL_API +void sm_func_sm_array_fixed(ai_handle out, const ai_handle in, + const ai_size in_size, + const ai_size channel_size, + const ai_size in_channel_step, + const ai_size out_channel_step); + +/*! + * @brief Computes the activations of a fixed point softmax nonlinear layer. + * @ingroup layers_sm + * @param layer the softmax (sm) layer + */ +AI_INTERNAL_API +void forward_sm_fixed(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_SM_H*/ + diff --git a/lib/stai/libstai/include/layers_upsample.h b/lib/stai/libstai/include/layers_upsample.h new file mode 100644 index 000000000..ff906a188 --- /dev/null +++ b/lib/stai/libstai/include/layers_upsample.h @@ -0,0 +1,69 @@ +/** + ****************************************************************************** + * @file layers_upsample_generic.h + * @author STMicroelectronics + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_UPSAMPLE_H +#define LAYERS_UPSAMPLE_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + + +/*! + * @brief Handles upsampling in zeros mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_zeros_is8os8(ai_layer* layer); + +/*! + * @brief Handles upsampling in bilinear mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_bilinear_is8os8(ai_layer* layer); + +/*! + * @brief Handles upsampling in zeros mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_zeros_is16os16(ai_layer* layer); + +/*! + * @brief Handles upsampling in bilinear mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_bilinear_is16os16(ai_layer* layer); +AI_API_DECLARE_END + +#endif /*LAYERS_UPSAMPLE_H*/ diff --git a/lib/stai/libstai/include/layers_upsample_generic.h b/lib/stai/libstai/include/layers_upsample_generic.h new file mode 100644 index 000000000..7178d5181 --- /dev/null +++ b/lib/stai/libstai/include/layers_upsample_generic.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file layers_upsample_generic.h + * @author STMicroelectronics + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_UPSAMPLE_GENERIC_H +#define LAYERS_UPSAMPLE_GENERIC_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles generic upsampling in nearest mode + * @ingroup layers_generic + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_nearest(ai_layer *pLayer); + +/*! + * @brief Handles generic upsampling in zeros mode + * @ingroup layers_generic + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_zeros(ai_layer *pLayer); + +/*! + * @brief Handles generic upsampling in bilinear mode + * @ingroup layers_generic + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_bilinear(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_UPSAMPLE_GENERIC_H*/ diff --git a/lib/stai/libstai/include/layers_wrappers.h b/lib/stai/libstai/include/layers_wrappers.h new file mode 100644 index 000000000..dbcec9d5c --- /dev/null +++ b/lib/stai/libstai/include/layers_wrappers.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file layers_wrappers.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform generic layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef _LAYERS_WRAPPERS_H +#define _LAYERS_WRAPPERS_H + +#include "layers_common.h" + +/*! + * @defgroup layers_wrappers Runtime Wrapper Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_tflite_wrapper + * @ingroup layers_generic + * @brief TimeDelay layer with sparse kernel + */ + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tflite_wrapper_ { + AI_NODE_COMMON_FIELDS_DECLARE + const ai_array* init_data; +} ai_layer_tflite_wrapper; + +AI_API_DECLARE_END + +#endif /* _LAYERS_WRAPPERS_H */ + diff --git a/lib/stai/libstai/include/lite_argminmax.h b/lib/stai/libstai/include/lite_argminmax.h new file mode 100644 index 000000000..9a8e59f32 --- /dev/null +++ b/lib/stai/libstai/include/lite_argminmax.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file lite_argminmax.h + * @author AIS + * @brief header file of AI platform lite argmin argmax funcions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_ARGMINMAX_H +#define LITE_ARGMINMAX_H + +#include "ai_lite_interface.h" + + +void forward_lite_argmax_if32( const ai_float* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmin_if32( const ai_float* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmax_is8( const ai_i8* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmax_iu8( const ai_u8* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmin_is8( const ai_i8* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); + + +#endif /*LITE_ARGMINMAX_H*/ diff --git a/lib/stai/libstai/include/lite_bn_f32.h b/lib/stai/libstai/include/lite_bn_f32.h new file mode 100644 index 000000000..25399706b --- /dev/null +++ b/lib/stai/libstai/include/lite_bn_f32.h @@ -0,0 +1,42 @@ +/** + ****************************************************************************** + * @file lite_bnf32.h + * @author AIS + * @brief header file of AI platform lite batch normalization functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_BN_F32_H +#define LITE_BN_F32_H + + +#include "ai_lite_interface.h" + +/*! + * @brief Forward function for a batch normalization (BN) layer with + * signed float input, signed float output, and float parameters. + * @ingroup lite_bn_f32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param scale The pointer to BN scale param. + * @param bias The pointer to bias. + * @param n_elements The number of elements in the input tensor. + * @param n_channel_in The number of channel in the input tensor. + */ +LITE_API_ENTRY +void forward_lite_bn_if32of32wf32( + ai_float* output, const ai_float* input, + const ai_float* scale, const ai_float* bias, + const ai_u32 n_elements, const ai_u32 n_channel_in); + + +#endif /* LITE_BN_F32_H */ diff --git a/lib/stai/libstai/include/lite_bn_integer.h b/lib/stai/libstai/include/lite_bn_integer.h new file mode 100644 index 000000000..fd89fd566 --- /dev/null +++ b/lib/stai/libstai/include/lite_bn_integer.h @@ -0,0 +1,216 @@ +/** + ****************************************************************************** + * @file lite_bn_integer.h + * @author AIS + * @brief header file of AI platform lite integer batch normalization + * normalization functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_BN_INTEGER_H +#define LITE_BN_INTEGER_H + + +#include "ai_lite_interface.h" + +/** + * @brief Batch Normalization with 16-bit input, 16-bit threshold and binary output. + * It is implemented using a threshold, and this is possible because the output is binary. + * + * @param[in] pIn Input data pointer + * @param[out] pOut_32 Output data pointer + * @param[in] pThreshold Thresholds pointer (one per channel) + * @param[in] dim_x X dimension + * @param[in] dim_y Y dimension + * @param[in] channels_num Channels number + */ +LITE_API_ENTRY +void forward_lite_bn_is16os1ws16(const ai_i16 *pIn, + ai_u32 *pOut_32, + const ai_i16 *pThreshold, + const ai_i16 dim_x, + const ai_i16 dim_y, + const ai_i16 channels_num); + + + + + +/** + * @brief Batch Normalization with signed 8-bit input, output. + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_is8os8( const ai_i8 *p_in, + ai_i8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint, + ai_float out_scale, + const ai_i32 out_zeropoint, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/** + * @brief Batch Normalization with signed 8-bit input, output + * per channel quantization + * + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_is8os8_ch( const ai_i8 *p_in, + ai_i8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint, + ai_float out_scale, + const ai_i32 out_zeropoint, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/** + * @brief Batch Normalization with unsigned 8-bit input, output + * + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_iu8ou8( const ai_u8 *p_in, + ai_u8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint_32, + ai_float out_scale, + const ai_i32 out_zeropoint_32, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/** + * @brief Batch Normalization with unsigned 8-bit input, output + * per channel quantization + * + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_iu8ou8_ch( const ai_u8 *p_in, + ai_u8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint, + ai_float out_scale, + const ai_i32 out_zeropoint, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +#endif /* LITE_BN_INTEGER_H */ diff --git a/lib/stai/libstai/include/lite_conv2d.h b/lib/stai/libstai/include/lite_conv2d.h new file mode 100644 index 000000000..870e56e44 --- /dev/null +++ b/lib/stai/libstai/include/lite_conv2d.h @@ -0,0 +1,477 @@ +/** + ****************************************************************************** + * @file lite_conv2d.h + * @author AIS + * @brief header file of AI platform lite conv2d kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_H +#define LITE_CONV2D_H + +#include "ai_lite_interface.h" +#include "lite_internal_apis.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles 2D convolution with float input, float output and + * float weights + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_ptr_const pWeights_init, + const ai_ptr_const pBias_init, + ai_float *pWeights_prefetch, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_size filt_height_dilated, + const ai_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_size n_groups); + +/*! + * @brief Handles 2D depthwise convolution with float input, float output and + * float weights + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_dw_if32of32wf32(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_ptr_const pWeights_init, + const ai_ptr_const pBias_init, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_size filt_height_dilated, + const ai_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_size n_groups); + +/*! + * @brief Handles 2D grouped convolution with float input, float output and + * float weights + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32_group(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_ptr_const pWeights_init, + const ai_ptr_const pBias_init, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_size filt_height_dilated, + const ai_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_size n_groups); + +/*! + * @brief Handles dilated conv2d convolutions (valid padding) + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_dilated_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles conv2d convolutions (valid padding) with number of channels >= 8 + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_deep_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +/*! + * @brief Handles conv2d convolutions (valid padding) with number of channels >= 8 + * Special forward function for 3x3 kernels and Stride = 1 + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_deep_3x3_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles conv2d convolutions optimized by HSP HW + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_hsp_1step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +LITE_API_ENTRY +void +forward_lite_conv2d_hsp_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +LITE_API_ENTRY +void +forward_lite_conv2d_hsp_3step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + + +/*! + * @brief Handles conv2d convolutions with same padding or with number of channels < 8 + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles rgb conv2d convolutions + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_rgb_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel, + const ai_u16 padding, + const ai_u16 stride, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles 2D convolution with float input, float output and + * float weights with pool fused + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32_pool(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_float *pWeights_init, + const ai_float *pBias_init, + ai_float *pScratch_init, + ai_float *pWeights_prefetch, + const ai_short_size n_channel_in, + const ai_short_size n_channel_out, + const ai_short_size width_in, + const ai_short_size height_in, + const ai_short_size width_out, + const ai_short_size height_out, + const ai_short_size filt_width, + const ai_short_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_short_size filt_height_dilated, + const ai_short_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_short_size n_groups, + const ai_short_size width_conv_out, + const ai_short_size height_conv_out, + func_nl_lite nl_func_lite, + ai_ptr_const nl_params, + const ai_ptr_offset nl_params_step, + const ai_ptr_offset nl_params_size, + ai_handle pool_func, + const ai_short_size pool_width, + const ai_short_size pool_height, + const ai_short_size pool_stride_x, + const ai_short_size pool_stride_y, + const ai_short_size pool_pad_x, + const ai_short_size pool_pad_y); + +/*! + * @brief Handles 2D depthwise convolution with float input, float output and + * float weights with pool fused + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_dw_if32of32wf32_pool(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_float *pWeights_init, + const ai_float *pBias_init, + ai_float *pScratch_init, + const ai_short_size n_channel_in, + const ai_short_size n_channel_out, + const ai_short_size width_in, + const ai_short_size height_in, + const ai_short_size width_out, + const ai_short_size height_out, + const ai_short_size filt_width, + const ai_short_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_short_size filt_height_dilated, + const ai_short_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_short_size n_groups, + const ai_short_size width_conv_out, + const ai_short_size height_conv_out, + func_nl_lite nl_func_lite, + ai_ptr_const nl_params, + const ai_ptr_offset nl_params_step, + const ai_ptr_offset nl_params_size, + ai_handle pool_func, + const ai_short_size pool_width, + const ai_short_size pool_height, + const ai_short_size pool_stride_x, + const ai_short_size pool_stride_y, + const ai_short_size pool_pad_x, + const ai_short_size pool_pad_y); +/*! + * @brief Handles 2D grouped convolution with float input, float output and + * float weights with pool fused + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32_group_pool(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_float *pWeights_init, + const ai_float *pBias_init, + ai_float *pScratch_init, + const ai_short_size n_channel_in, + const ai_short_size n_channel_out, + const ai_short_size width_in, + const ai_short_size height_in, + const ai_short_size width_out, + const ai_short_size height_out, + const ai_short_size filt_width, + const ai_short_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_short_size filt_height_dilated, + const ai_short_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_short_size n_groups, + const ai_short_size width_conv_out, + const ai_short_size height_conv_out, + func_nl_lite nl_func_lite, + ai_ptr_const nl_params, + const ai_ptr_offset nl_params_step, + const ai_ptr_offset nl_params_size, + ai_handle pool_func, + const ai_short_size pool_width, + const ai_short_size pool_height, + const ai_short_size pool_stride_x, + const ai_short_size pool_stride_y, + const ai_short_size pool_pad_x, + const ai_short_size pool_pad_y); + +#endif /*LITE_CONV2D_H*/ diff --git a/lib/stai/libstai/include/lite_conv2d_dqnn.h b/lib/stai/libstai/include/lite_conv2d_dqnn.h new file mode 100644 index 000000000..435a865c4 --- /dev/null +++ b/lib/stai/libstai/include/lite_conv2d_dqnn.h @@ -0,0 +1,568 @@ +/** + ****************************************************************************** + * @file lite_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform lite dqnn conv kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_DQNN_H +#define LITE_CONV2D_DQNN_H + +#include "ai_lite_interface.h" + +# define AI_16_OVERFLOW_CHECK(val_) (val_ <= 32767) + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +AI_API_DECLARE_BEGIN + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad0(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * - Optimized thanks to Optim0 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad0_optim0(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os8ws1_bn_pad0(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad1(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim2 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad1_optim2(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 width_out, + const ai_u16 height_out, + const ai_u16 filt_width, + const ai_u16 filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_i32 *pThreshold, + const ai_u8 flatten_output); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os8ws1_bn_pad1(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale, + const ai_float *pOffset, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os8ws1_bn_pad1_optim1(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale, + const ai_float *pOffset, + const ai_i32 pad_value); + +/** + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os16ws1_bn_pad0_fxp(const ai_u32 *pDataIn_init, + ai_i16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os16ws1_bn_pad1_fxp(const ai_u32 *pDataIn_init, + ai_i16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os16ws1_bn_pad1_optim1_fxp(const ai_u32 *pDataIn_init, + ai_i16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + + +/** + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1ou16ws1_bn_pad1_fxp(const ai_u32 *pDataIn_init, + ai_u16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1ou16ws1_bn_pad0_fxp(const ai_u32 *pDataIn_init, + ai_u16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F. + * - Optimized thanks to Optim1 assumptions + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1ou16ws1_bn_pad1_optim1_fxp(const ai_u32 *pDataIn_init, + ai_u16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - Lite I/F + * @ingroup lite_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +LITE_API_ENTRY +void forward_lite_conv2d_is8os1ws8(const ai_i8 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i8 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i8 in_zeropoint); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - Lite I/F - Optimized thanks to Optim2 assumptions + * @ingroup lite_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +LITE_API_ENTRY +void forward_lite_conv2d_is8os1ws8_optim2(const ai_i8 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i8 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i8 in_zeropoint); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - quantized with DoReFa SotA quantizer, lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_dorefa_is8os1ws8(const ai_i8 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u8 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i8 in_zeropoint); + + +/*! + * @brief Handles 2D convolution with 8-bits quantized input, output and weights + * - quantized with with different quantization for channel + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is8os8ws8_sssa_ch(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_i32 scratch_size); + +/*! + * @brief Handles 2D convolution with 16-bits quantized inputs, binary outputs and binary weights - Lite I/F. + * Vanilla version. + * @ingroup lite_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +LITE_API_ENTRY +void forward_lite_conv2d_is16os1ws1_bn_fxp(const ai_i16 *pIn, + ai_u32 *pOut_32, + const ai_u32 *pWeights, + const ai_i32 *pThreshold, + ai_i8 *pBufferA, + const ai_i32 dim_kernel, + const ai_i16 dim_im_in_x, + const ai_i16 dim_im_in_y, + const ai_i16 dim_im_out_x, + const ai_i16 dim_im_out_y, + const ai_i16 ch_im_in, + const ai_i16 ch_im_out, + const ai_i16 dim_kernel_x, + const ai_i16 dim_kernel_y, + const ai_i16 padding_x, + const ai_i16 padding_y, + const ai_i16 stride_x, + const ai_i16 stride_y, + const ai_i16 dilation_x, + const ai_i16 dilation_y, + const ai_i16 in_zeropoint); + + +/** + * @brief Handles 2D convolution with 16-bits quantized inputs, 16-bits quantized outputs and binary weights - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is16os16ws1_fxp(const ai_i16 *pIn, + ai_i16 *pOut, + const ai_u32 *pWeights, + ai_i8 *pBufferA, + const ai_i16 dim_im_in_x, + const ai_i16 dim_im_in_y, + const ai_i16 dim_im_out_x, + const ai_i16 dim_im_out_y, + const ai_i16 ch_im_in, + const ai_i16 ch_im_out, + const ai_u32 dim_kernel, + const ai_i16 dim_kernel_x, + const ai_i16 dim_kernel_y, + const ai_i16 padding_x, + const ai_i16 padding_y, + const ai_i16 stride_x, + const ai_i16 stride_y, + const ai_i16 dilation_x, + const ai_i16 dilation_y, + const ai_i16 in_zeropoint); + +AI_API_DECLARE_END + +#endif /*LITE_CONV2D_DQNN_H*/ diff --git a/lib/stai/libstai/include/lite_conv2d_is16.h b/lib/stai/libstai/include/lite_conv2d_is16.h new file mode 100644 index 000000000..3529b460b --- /dev/null +++ b/lib/stai/libstai/include/lite_conv2d_is16.h @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file lite_dense_is16.h + * @author Giacomo Turati + * @brief header file of AI platform lite conv2d kernel (with signed int16 input) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_IS16_H +#define LITE_CONV2D_IS16_H + + +#include "stai.h" +#include "ai_lite_interface.h" + +/*! + * @brief Conv2d layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support signed integer 16 input and signed integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @param output Pointer to the output buffer + * @param input Pointer to the input buffer + * @param weights Pointer to the weights array + * @param n_channel_in Number of input channels + * @param n_channel_out Number of output channels, i.e.,the number of conv2d hidden filters + * @param width_in Input width + * @param height_in Input height + * @param width_out Output width + * @param height_out Output height + * @param filt_width Filters width + * @param filt_height Filters height + * @param filt_pad_x Filters pad width + * @param filt_pad_y Filters pad height + * @param stride_x Stride width + * @param stride_y Stride height + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + * @param signed_input Signed input flag + * @param signed_output Signed output flag +*/ +LITE_API_ENTRY +void forward_lite_conv2d_is16os16ws16_fxp( + int16_t* output, + const int16_t* input, + const int16_t* weights, + const int16_t* bias, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_size filt_pad_x, + const ai_size filt_pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const uint8_t* shifts, + const uint8_t* bias_shifts + ); + +/*! + * @brief Conv2d layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support signed integer 16 input and unsigned integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @param output Pointer to the output buffer + * @param input Pointer to the input buffer + * @param weights Pointer to the weights array + * @param n_channel_in Number of input channels + * @param n_channel_out Number of output channels, i.e.,the number of conv2d hidden filters + * @param width_in Input width + * @param height_in Input height + * @param width_out Output width + * @param height_out Output height + * @param filt_width Filters width + * @param filt_height Filters height + * @param filt_pad_x Filters pad width + * @param filt_pad_y Filters pad height + * @param stride_x Stride width + * @param stride_y Stride height + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + * @param signed_input Signed input flag + * @param signed_output Signed output flag +*/ +LITE_API_ENTRY +void forward_lite_conv2d_is16ou16ws16_fxp( + uint16_t* output, + const int16_t* input, + const int16_t* weights, + const int16_t* bias, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_size filt_pad_x, + const ai_size filt_pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const uint8_t* shifts, + const uint8_t* bias_shifts + ); + +/*! + * @brief Conv2d layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support unsigned integer 16 input and signed integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @param output Pointer to the output buffer + * @param input Pointer to the input buffer + * @param weights Pointer to the weights array + * @param n_channel_in Number of input channels + * @param n_channel_out Number of output channels, i.e.,the number of conv2d hidden filters + * @param width_in Input width + * @param height_in Input height + * @param width_out Output width + * @param height_out Output height + * @param filt_width Filters width + * @param filt_height Filters height + * @param filt_pad_x Filters pad width + * @param filt_pad_y Filters pad height + * @param stride_x Stride width + * @param stride_y Stride height + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + * @param signed_input Signed input flag + * @param signed_output Signed output flag +*/ +LITE_API_ENTRY +void forward_lite_conv2d_iu16os16ws16_fxp( + int16_t* output, + const uint16_t* input, + const int16_t* weights, + const int16_t* bias, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_size filt_pad_x, + const ai_size filt_pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const uint8_t* shifts, + const uint8_t* bias_shifts + ); + +/*! + * @brief Conv2d layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support unsigned integer 16 input and unsigned integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @param output Pointer to the output buffer + * @param input Pointer to the input buffer + * @param weights Pointer to the weights array + * @param n_channel_in Number of input channels + * @param n_channel_out Number of output channels, i.e.,the number of conv2d hidden filters + * @param width_in Input width + * @param height_in Input height + * @param width_out Output width + * @param height_out Output height + * @param filt_width Filters width + * @param filt_height Filters height + * @param filt_pad_x Filters pad width + * @param filt_pad_y Filters pad height + * @param stride_x Stride width + * @param stride_y Stride height + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + * @param signed_input Signed input flag + * @param signed_output Signed output flag +*/ +LITE_API_ENTRY +void forward_lite_conv2d_iu16ou16ws16_fxp( + uint16_t* output, + const uint16_t* input, + const int16_t* weights, + const int16_t* bias, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_size filt_pad_x, + const ai_size filt_pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const uint8_t* shifts, + const uint8_t* bias_shifts + ); + +#endif /* LITE_CONV2D_IS16_H */ diff --git a/lib/stai/libstai/include/lite_conv2d_sssa8_ch.h b/lib/stai/libstai/include/lite_conv2d_sssa8_ch.h new file mode 100644 index 000000000..b314a009b --- /dev/null +++ b/lib/stai/libstai/include/lite_conv2d_sssa8_ch.h @@ -0,0 +1,498 @@ +/** + ****************************************************************************** + * @file lite_conv2d_sssa8_ch.h + * @author AIS + * @brief ST header for signed simmetric signed antisimmetric 8 bits + * layers with channel quantization + ****************************************************************************** + * @attention + * + * Copyright (c) 2021-2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_SSSA8_CH_H +#define LITE_CONV2D_SSSA8_CH_H + +void +forward_lite_conv2d_rgb_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel, + const ai_u16 padding, + const ai_u16 stride, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +void +forward_lite_conv2d_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + + +void forward_lite_conv2d_hsp_1step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void forward_lite_conv2d_hsp_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void forward_lite_conv2d_hsp_3step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_conv2d_dilated_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt_0, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void forward_lite_conv2d_deep_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt_0, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void forward_lite_conv2d_deep_3x3_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt_0, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + + +void +forward_lite_pw_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_pw_hsp_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_pw_hsp_1step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_pw_hsp_3step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_dw_dm_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 ch_im_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_hsp_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_hsp_1step_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_hsp_3Step_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u32 scratch_size, + ai_i16 *bufferA); + + +void +forward_lite_dw_3x3_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_3x3_ch1st_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + + +void +forward_lite_dw_1xN_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + + + +#endif /* LITE_CONV2D_SSSA8_CH_H */ diff --git a/lib/stai/libstai/include/lite_convert_dqnn.h b/lib/stai/libstai/include/lite_convert_dqnn.h new file mode 100644 index 000000000..a17621334 --- /dev/null +++ b/lib/stai/libstai/include/lite_convert_dqnn.h @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file lite_convert_dqnn.h + * @author AIS + * @brief header file of AI platform lite convert kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONVERT_DQNN_H +#define LITE_CONVERT_DQNN_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +LITE_API_ENTRY +void forward_lite_node_convert_is1os8( + const ai_pbits *p_in, + ai_i8 *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 *n_values); + + +LITE_API_ENTRY +void forward_lite_node_convert_is1os16( + const ai_pbits *p_in, + ai_i16 *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i16 *n_values); + + +LITE_API_ENTRY +void forward_lite_node_convert_is1of32( + const ai_pbits *p_in, + ai_float *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_float *n_values); + + +/*! + * @brief Handles data conversion from 8-bits signed input to signed binary + * outputs - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_node_convert_is8os1( + const ai_i8 *p_in, + ai_pbits *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 zp, + const ai_i8 pad); + + +LITE_API_ENTRY +void forward_lite_node_convert_is16os1( + const ai_i16 *p_in, + ai_pbits *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 zp, + const ai_i8 pad); + + +LITE_API_ENTRY +void forward_lite_node_convert_if32os1( + const ai_float *p_in, + ai_pbits *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 zp, + const ai_i8 pad); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_if32os8( + const ai_float *p_in, + ai_i8 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_i8 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_if32ou8( + const ai_float *p_in, + ai_u8 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_u8 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8of32( + const ai_i8 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_i8 in_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8of32( + const ai_u8 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_u8 in_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_if32os16( + const ai_float *p_in, + ai_i16 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_i16 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_if32ou16( + const ai_float *p_in, + ai_u16 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_u16 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_is16of32( + const ai_i16 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_i16 in_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_iu16of32( + const ai_u16 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_u16 in_zeropoint); + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8os8( + const ai_i8 *p_in, + ai_i8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i16 in_zp, + const ai_i16 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8ou8( + const ai_u8 *p_in, + ai_u8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_u8 in_zp, + const ai_u8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8os8( + const ai_u8 *p_in, + ai_i8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_u8 in_zp, + const ai_i8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8os8_fast( + const ai_u8 *p_in, + ai_i8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_u8 in_zp, + const ai_i8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8ou8( + const ai_i8 *p_in, + ai_u8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i8 in_zp, + const ai_u8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8ou8_fast( + const ai_i8 *p_in, + ai_u8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i8 in_zp, + const ai_u8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_is16ou16( + const ai_i16 *p_in, + ai_u16 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i16 in_zp, + const ai_u16 out_zp); + +#endif /*LITE_CONVERT_DQNN_H*/ diff --git a/lib/stai/libstai/include/lite_dense_if32.h b/lib/stai/libstai/include/lite_dense_if32.h new file mode 100644 index 000000000..b44376561 --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_if32.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file lite_dense_if32.h + * @author STMicroelectronics + * @brief Definitions of runtime-lite dense core kernels (with float f32 input) + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IF32_H +#define LITE_DENSE_IF32_H + +#include "ai_lite_interface.h" + +/*! + * @brief decompress the weights into a scratch buffer + + * @ingroup lite_dense_if32 + * @param out pointer to the scratch buffer data + * @param lut pointer to the compression dictionary + * @param lut_bits bits used for compression (only 4 or 8 supported) + * @param n_in if last dimension is not even, specify its size for padding + * @param n_out: number of elements to be decompressed + */ +LITE_API_ENTRY +const uint8_t* lite_decompress_ilutof32( + float* out, const uint8_t* data0, + const float* lut, const uint16_t lut_bits, + const ai_size n_in, const ai_size n_out); + + +/*! + * @brief C struct for a dense layer with signed float input, signed float output, and float weights. + * @ingroup lite_dense_if32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. + */ +typedef struct { + ai_float* output; + const ai_float* input; + const ai_float* weights; + const ai_float* bias; + const ai_size n_channel_in; + const ai_size n_channel_out; + const ai_size n_elements; +} forward_lite_dense_if32of32wf32_args; + + +/*! + * @brief Forward function for a dense layer with signed float input, + * signed float output, and float weights. + * @ingroup lite_dense_if32 + * @param args pointer to @ref forward_lite_dense_if32of32wf32_args structure + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32wf32( + forward_lite_dense_if32of32wf32_args* args); + + +/*! + * @brief Forward function for a dense layer with signed float input, + * signed float output, and 4bit LUT compressed weights. + * @ingroup lite_dense_if32 + * @param output The pointer to output buffer. + * @param weights_lut The pointer to compressed weights LUT table (16 entries). + * @param input The pointer to input buffer. + * @param weights_indeces The pointer to compressed weights indeces table (packed 4bits buffer). + * @param scratch_lut The pointer to cache buffer where to prefetch weights_lut values. (optional) + * @param bias The pointer to bias (NULL if not available). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. + * @param n_elements The number of elements to process + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32wf32_lut4( + ai_float* output, const ai_float* input, + const ai_u8* weights_indeces, const ai_float* weights_lut, ai_float* scratch_lut, + const ai_float* bias, + const ai_size n_channel_in, const ai_size n_channel_out, + const ai_size n_elements); + + +/*! + * @brief Forward function for a dense layer with signed float input, + * signed float output, and 8bit LUT compressed weights. + * @ingroup lite_dense_if32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights_indeces The pointer to compressed weights indeces table (8bits buffer). + * @param weights_lut The pointer to compressed weights LUT table (256 entries). + * @param scratch_lut The pointer to cache buffer where to prefetch weights_lut values. (optional) + * @param bias The pointer to bias (NULL if not available). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. + * @param n_elements The number of elements to process + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32wf32_lut8( + ai_float* output, const ai_float* input, + const ai_u8* weights_indeces, const ai_float* weights_lut, ai_float* scratch_lut, + const ai_float* bias, + const ai_size n_channel_in, const ai_size n_channel_out, + const ai_size n_elements); + + +#endif /* LITE_DENSE_IF32_H */ diff --git a/lib/stai/libstai/include/lite_dense_is1.h b/lib/stai/libstai/include/lite_dense_is1.h new file mode 100644 index 000000000..afa27a5ca --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_is1.h @@ -0,0 +1,71 @@ +/** + ****************************************************************************** + * @file lite_dense_is1.h + * @author AIS + * @brief header file of AI platform lite argmin argmax funcions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS1_H +#define LITE_DENSE_IS1_H + + +#include "ai_lite_interface.h" + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed float output, and float weights. + * @ingroup lite_dense_is1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1of32wf32( + ai_float *output, const ai_pbits *input, const ai_float *weights, + const ai_float *bias, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed float output, and float weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1of32wf32_bn( + ai_float *output, const ai_pbits *input, const ai_float *weights, + const ai_float *scale, const ai_float *offset, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + +#endif /* LITE_DENSE_IS1_H */ diff --git a/lib/stai/libstai/include/lite_dense_is16.h b/lib/stai/libstai/include/lite_dense_is16.h new file mode 100644 index 000000000..a7a5c9615 --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_is16.h @@ -0,0 +1,140 @@ + +/** + ****************************************************************************** + * @file lite_dense_is16.h + * @author Giacomo Turati + * @brief header file of AI platform lite dense kernel (with signed int16 input) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS16_H +#define LITE_DENSE_IS16_H + + +#include "stai.h" +#include "ai_lite_interface.h" + +/*! + * @brief Dense layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support signed integer 16 input and signed integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @ingroup lite_dense_ws16 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + */ +LITE_API_ENTRY +void forward_lite_dense_is16os16ws16_fxp( + int16_t* output, + const int16_t* input, + const int16_t* weights, + const int16_t* bias, + const uint32_t n_channel_in, + const uint32_t n_channel_out, + const uint8_t* shifts, + const uint8_t* bias_shifts +); + +/*! + * @brief Dense layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support signed integer 16 input and unsigned integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @ingroup lite_dense_ws16 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + */ + +LITE_API_ENTRY +void forward_lite_dense_is16ou16ws16_fxp( + uint16_t* output, + const int16_t* input, + const int16_t* weights, + const int16_t* bias, + const uint32_t n_channel_in, + const uint32_t n_channel_out, + const uint8_t* shifts, + const uint8_t* bias_shifts +); + +/*! + * @brief Dense layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support unsigned integer 16 input and signed integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @ingroup lite_dense_ws16 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + */ +LITE_API_ENTRY +void forward_lite_dense_iu16os16ws16_fxp( + int16_t* output, + const uint16_t* input, + const int16_t* weights, + const int16_t* bias, + const uint32_t n_channel_in, + const uint32_t n_channel_out, + const uint8_t* shifts, + const uint8_t* bias_shifts +); + +/*! + * @brief Dense layer with fixed-point int16_t weights (e.g., Qkeras "auto_po2"). + * Support unsigned integer 16 input and unsigned integer 16 output activations. + * Both weights and bias (if any) must be quantized with 16 bits. + * Manage different fixed-point scales between weights and bias (if any). + * @ingroup lite_dense_ws16 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param shifts Array of fixed-point binary scales for the weights + * @param bias_shifts Array of fixed-point binary scales for the bias + */ + +/*! + * @brief Signed input / signed output API wrapper for _conv2d_ws16_fxp_backend. + * @ingroup lite_conv2d_ws16 + */ +LITE_API_ENTRY +void forward_lite_dense_iu16ou16ws16_fxp( + uint16_t* output, + const uint16_t* input, + const int16_t* weights, + const int16_t* bias, + const uint32_t n_channel_in, + const uint32_t n_channel_out, + const uint8_t* shifts, + const uint8_t* bias_shifts +); + +#endif /* LITE_DENSE_IS16_H */ diff --git a/lib/stai/libstai/include/lite_dense_is1ws1.h b/lib/stai/libstai/include/lite_dense_is1ws1.h new file mode 100644 index 000000000..8fcbe7b4a --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_is1ws1.h @@ -0,0 +1,170 @@ +/** + ****************************************************************************** + * @file lite_dense_is1ws1.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS1WS1_H +#define LITE_DENSE_IS1WS1_H + +#include "stai.h" +#include "ai_lite_interface.h" + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer. + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os1ws1( + ai_pbits *output, const ai_pbits *input, const ai_pbits *weights, + const ai_pbits *bias, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer. + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os1ws1_bn( + ai_pbits *output, const ai_pbits *input, const ai_pbits *weights, + const ai_float *scale, const ai_float *offset, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed 16bit weights. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (signed 32bit). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os16ws1( + ai_i16 *output, const ai_pbits *input, const ai_pbits *weights, + const ai_pbits *bias, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed 16bit weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (signed 32bit). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os16ws1_bn( + ai_i16 *output, const ai_pbits *input, const ai_pbits *weights, + const ai_float *scale, const ai_float *offset, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed float output, and signed binary weights. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1of32ws1( + ai_float *output, const ai_pbits *input, const ai_pbits *weights, + const ai_pbits *bias, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + + +/*! + * @brief C struct for a dense layer with signed binary input, + * signed float output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +typedef struct { + float* output; + const stai_pbits* input; + const stai_pbits* weights; + const float* scale; + const float* offset; + int32_t* scratch; + const uint32_t n_channel_in; + const uint32_t n_channel_out; +} forward_lite_dense_is1of32ws1_bn_args; + + +LITE_API_ENTRY +void forward_lite_dense_is1of32ws1_bn( + forward_lite_dense_is1of32ws1_bn_args* args); + + +#endif /*LITE_DENSE_IS1WS1_H*/ diff --git a/lib/stai/libstai/include/lite_dense_is8os1ws1.h b/lib/stai/libstai/include/lite_dense_is8os1ws1.h new file mode 100644 index 000000000..3c9cae19b --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_is8os1ws1.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file lite_dense_is8os1ws1.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS8OS1WS1_H +#define LITE_DENSE_IS8OS1WS1_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Forward function for a dense layer with signed 8 bits input, + * binary weights and binary output. + * @ingroup lite_dense_is8os1ws1 + * @param out_ptr The pointer to output buffer. + *@param data_in_init_ptr The pointer to input buffer. + * @param weights_ptr The pointer to weights. + * @param scratch_ptr The pointer to scratch buffer. + * @param scratch_size The value of scratch tensor size. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param n_channel_in The number of channels of the input. + * @param scale_ptr The pointer to scale buffer of BN. + * @param offset_ptr The pointer to offset buffer of BN. + */ +LITE_API_ENTRY +void forward_lite_dense_is8os1ws1_bn_fxp(ai_pbits *out_ptr, + const ai_i8 *data_in_init_ptr, + const ai_pbits *weights_ptr, + ai_i32 *scratch_ptr, + const ai_u32 scratch_size, + const ai_u32 n_channel_out, + const ai_u32 n_channel_in, + const ai_i32 *threshold_ptr); + +#endif /*LITE_DENSE_IS8OS1WS1_H*/ diff --git a/lib/stai/libstai/include/lite_dense_is8os8ws8.h b/lib/stai/libstai/include/lite_dense_is8os8ws8.h new file mode 100644 index 000000000..9a0b127a5 --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_is8os8ws8.h @@ -0,0 +1,97 @@ +/** + ****************************************************************************** + * @file lite_dense_is8os8ws8.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS8OS8WS8_H +#define LITE_DENSE_IS8OS8WS8_H + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Forward function for a dense layer with signed input, + * signed output and signed weights all at 8 bits. + * @ingroup lite_dense_is8os8ws8 + * @param input The pointer to input buffer. + * @param output The pointer to output buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param in_zeropoint The value of the zero point of the input. + * @param out_zeropoint TThe value of the zero point of the output. + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param n_pixels Total number of pixels. + */ +LITE_API_ENTRY +void forward_lite_dense_is8os8ws8(ai_i8 * pDataOut, + const ai_i8 *pDataIn, + const ai_i8 *pWeights, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size n_pixels, + const ai_float in_scale, + const ai_float out_scale, + const ai_float Wt_scale, + ai_i16 *pBuffer_a); + +void forward_lite_dense_hsp_is8os8ws8(ai_i8 * pDataOut, + const ai_i8 *pDataIn, + const ai_i8 *pWeights, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size n_pixels, + const ai_float in_scale, + const ai_float out_scale, + const ai_float Wt_scale); + +void forward_lite_dense_hsp_3step_is8os8ws8(ai_i8 * pDataOut, + const ai_i8 *pDataIn, + const ai_i8 *pWeights, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size n_pixels, + const ai_float in_scale, + const ai_float out_scale, + const ai_float Wt_scale); + +void forward_lite_dense_is8os8ws8_ch(ai_i8 * pDataOut, + const ai_i8 *pDataIn, + const ai_i8 *pWeights, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size n_pixels, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i16 *pBuffer_a); + +#endif /*LITE_DENSE_IS8OS8WS8_H*/ diff --git a/lib/stai/libstai/include/lite_dense_ws1.h b/lib/stai/libstai/include/lite_dense_ws1.h new file mode 100644 index 000000000..69cee29cc --- /dev/null +++ b/lib/stai/libstai/include/lite_dense_ws1.h @@ -0,0 +1,171 @@ +/** + ****************************************************************************** + * @file lite_dense_ws1.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes (1bit weights) + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_WS1_H +#define LITE_DENSE_WS1_H + + +#include "stai.h" +#include "ai_lite_interface.h" + + +/*! + * @brief Forward function for a dense layer with signed 16bit input, + * signed 16bit output, binary weights and binary bias. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is16os16ws1( + ai_i16* output, const ai_i16* input, + const ai_pbits* weights, + const ai_pbits* bias, ai_i32* scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed 16bit input, + * signed 16bit output, binary weights and binary bias. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is16os16ws1_bn( + ai_i16* output, const ai_i16* input, + const ai_pbits* weights, + const ai_float *scale, const ai_float *offset, ai_i32* scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, binary weights and binary bias. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_if32os1ws1( + ai_pbits *output, const ai_float *input, const ai_pbits *weights, + const ai_float *bias, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief C struct for a dense layer with signed f32 input, + * f32 output, binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +typedef struct { + stai_pbits* output; + const float* input; + const stai_pbits* weights; + const float* scale; + const float* offset; + float* scratch; + const uint32_t n_channel_in; + const uint32_t n_channel_out; +} forward_lite_dense_if32os1ws1_bn_args; + + +LITE_API_ENTRY +void forward_lite_dense_if32os1ws1_bn(forward_lite_dense_if32os1ws1_bn_args* args); + + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to binary bias. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32ws1( + ai_float* output, const ai_float* input, + const ai_pbits* weights, + const ai_pbits* bias, ai_float* scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32ws1_bn( + ai_float *output, const ai_float *input, const ai_pbits *weights, + const ai_float *scale, const ai_float *offset, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + +#endif /* LITE_DENSE_IS1WS1_H */ diff --git a/lib/stai/libstai/include/lite_dw.h b/lib/stai/libstai/include/lite_dw.h new file mode 100644 index 000000000..a98868f0c --- /dev/null +++ b/lib/stai/libstai/include/lite_dw.h @@ -0,0 +1,253 @@ +/** + ****************************************************************************** + * @file lite_dw.h + * @author AIS + * @brief header file of AI platform lite depthwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DW_H +#define LITE_DW_H + + +#include "ai_lite_interface.h" + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles dw convolutions generic case (supports depth multiplier >= 1) + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_dm_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 ch_im_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/*! + * @brief Handles dw convolutions with depth multiplier = 1 only + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/* Variant optimized for HSP */ +void +forward_lite_dw_hsp_1step_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_hsp_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u32 scratch_size, + ai_i16 *bufferA); + + +/* Variant optimized for HSP: Large tensors */ +void +forward_lite_dw_hsp_3step_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_x_r, + const ai_u16 padding_y, + const ai_u16 padding_y_b, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/*! + * @brief Handles dw convolutions with depth multiplier = 1, valid padding + * and 3*3 kernel size + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_3x3_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/*! + * @brief Handles dw convolutions with depth multiplier = 1, valid padding, + * 3*3 kernel size, stride_x = 1 and weights/input are channel first + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_3x3_ch1st_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + + +/*! + * @brief Handles dw convolutions with depth multiplier = 1, valid padding, + * 1*N kernel size, stride_x = 1 + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_1xN_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + + + +#endif /*LITE_DW_H*/ diff --git a/lib/stai/libstai/include/lite_dw_dqnn.h b/lib/stai/libstai/include/lite_dw_dqnn.h new file mode 100644 index 000000000..5a2e4b28c --- /dev/null +++ b/lib/stai/libstai/include/lite_dw_dqnn.h @@ -0,0 +1,131 @@ +/** + ****************************************************************************** + * @file lite_dw_dqnn.h + * @author AIS + * @brief header file of AI platform lite integer depthwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DW_DQNN_H +#define LITE_DW_DQNN_H + + +#include "ai_lite_interface.h" + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles 2D DW convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad0(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D DW convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * - Optimized thanks to Optim3 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad0_optim3(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad1(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + + /*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim3 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad1_optim3(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + + +#endif /*LITE_DW_DQNN_H*/ diff --git a/lib/stai/libstai/include/lite_generic_float.h b/lib/stai/libstai/include/lite_generic_float.h new file mode 100644 index 000000000..c16d4a019 --- /dev/null +++ b/lib/stai/libstai/include/lite_generic_float.h @@ -0,0 +1,243 @@ +/** + ****************************************************************************** + * @file lite_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform lite conv kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_GENERIC_FLOAT_H +#define LITE_GENERIC_FLOAT_H + +#include "ai_lite_interface.h" +#include "layers_generic.h" + +/*****************************************************************************/ +/* Generic Forward Functions Section */ +/*****************************************************************************/ + +/** Reduce Generic Kernels *************************************************/ +LITE_API_ENTRY +void forward_lite_func_reduce_l1_if32of32( + ai_float* out_ptr, const ai_float* in_ptr, + const ai_size out_size, const ai_size in_step, + const ai_size axis_size, const ai_size axis_step); + + +LITE_API_ENTRY +void forward_lite_func_reduce_l2_if32of32( + ai_float* out_ptr, const ai_float* in_ptr, + const ai_size out_size, const ai_size in_step, + const ai_size axis_size, const ai_size axis_step); + +/** GatherND Kernels **************************************************/ + +/*! + * @brief C struct for a gather_nd layer. + * @ingroup lite_generic + * @param src_in list of pointers for the outputs buffers. + * @param dst_out list of pointers for the outputs buffers. + * @param index_data indices to select slices of input tensor. + * @param height_in H dimension of input tensor. + * @param width_in W dimension of input tensor. + * @param n_channel_in CH dimension of input tensor. + * @param height_index H dimension of indices tensor. + * @param width_index W dimension of indices tensor. + * @param d_in D dimension of input tensor. + * @param ch_index CH dimension of indices tensor. + * @param ch_stride_in CH stride of input tensor. + */ +typedef struct { + stai_ptr src_in; + stai_ptr dst_out; + ai_i32* index_data; + ai_size height_in; + ai_size width_in; + ai_size n_channel_in; + ai_size height_index; + ai_size width_index; + ai_size d_in; + ai_size ch_index; + int32_t ch_stride_in; +} forward_lite_gather_nd_args; + + +LITE_API_ENTRY +void forward_lite_gather_nd( + forward_lite_gather_nd_args* args); + +/** GatherND channel first Kernels **************************************************/ + +/*! + * @brief C struct for a gather_nd layer (Channel first). + * @ingroup lite_generic + * @param src_in list of pointers for the outputs buffers. + * @param dst_out list of pointers for the outputs buffers. + * @param index_data indices to select slices of input tensor. + * @param height_in H dimension of input tensor. + * @param width_in W dimension of input tensor. + * @param n_channel_in CH dimension of input tensor. + * @param height_index H dimension of indices tensor. + * @param width_index W dimension of indices tensor. + * @param ch_index CH dimension of indices tensor. + * @param ch_stride_in CH stride of input tensor. + * @param height_out H dimension of output tensor. + * @param width_out W dimension of output tensor. + * @param d_out D dimension of output tensor. + * @param ch_out CH dimension of output tensor. + */ +typedef struct { + stai_ptr src_in; + stai_ptr dst_out; + ai_i32* index_data; + ai_size height_in; + ai_size width_in; + ai_size n_channel_in; + ai_size height_index; + ai_size width_index; + ai_size ch_index; + int32_t ch_stride_in; + ai_size height_out; + ai_size width_out; + ai_size d_out; + ai_size ch_out; +} forward_lite_gather_nd_channel_first_args; + + +LITE_API_ENTRY +void forward_lite_gather_nd_channel_first( + forward_lite_gather_nd_channel_first_args* args); + +/** ScatterND Kernels **************************************************/ + +/*! + * @brief C struct for a scatter_nd layer. + * @ingroup lite_generic + * @param src_in list of pointers for the outputs buffers. + * @param dst_out list of pointers for the outputs buffers. + * @param index_data indices to select slices of input tensor. + * @param update_data values to be inserted into the input tensor. + * @param height_in H dimension of input tensor. + * @param width_in W dimension of input tensor. + * @param n_channel_in CH dimension of input tensor. + * @param height_index H dimension of indices tensor. + * @param width_index W dimension of indices tensor. + * @param d_in D dimension of input tensor. + * @param ch_index CH dimension of indices tensor. + * @param ch_stride_in CH stride of input tensor. + */ +typedef struct { + stai_ptr src_in; + stai_ptr dst_out; + ai_i32* index_data; + stai_ptr update_data; + ai_scatter_nd_reduction reduction; + func_binary func; + ai_size height_in; + ai_size width_in; + ai_size n_channel_in; + ai_size height_index; + ai_size width_index; + ai_size d_index; + ai_size d_in; + ai_size ch_index; + int32_t ch_stride_in; +} forward_lite_scatter_nd_args; + + +LITE_API_ENTRY +void forward_lite_scatter_nd( + forward_lite_scatter_nd_args* args); + +/** Split Generic Kernels **************************************************/ + +/*! + * @brief C struct for a generic split layer. + * @ingroup lite_generic + * @param outputs_ptr list of pointers for the outputs buffers. + * @param n_outputs_ptr the number of outputs + * @param n_outer_elems the number of elements to copy in a single split + * @param input_ptr the pointer to input buffer to split. + * @param splits_strides the pointer to array defining outputs split strides. + * @param splits_step the offset between split strides + */ +typedef struct { + stai_ptr* outputs_ptr; + const stai_size n_outputs_ptr; + const stai_size n_outer_elems; + const stai_ptr input_ptr; + const int32_t* splits_strides; + const stai_size splits_step; +} forward_lite_split_generic_args; + + +LITE_API_ENTRY +void forward_lite_split_generic( + forward_lite_split_generic_args* args); + + +/** TopK Generic Kernels ***************************************************/ +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_topK_axis_0_if32of32( + const ai_float *pDataIn_init, + ai_float *pDataOut_values_init, + ai_i32 *pDataOut_index_init, + const ai_size height_in, + const ai_size width_in, + const ai_size n_channel_in, + const ai_size k, ai_i16 largest, + void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) +); + + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * - Optimized thanks to Optim0 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_topK_axis_1_if32of32( + const ai_float *pDataIn_init, + ai_float *pDataOut_values_init, + ai_i32 *pDataOut_index_init, + const ai_size height_in, + const ai_size width_in, + const ai_size n_channel_in, + const ai_size k, ai_i16 largest, + void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) +); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_topK_axis_2_if32of32( + const ai_float *pDataIn_init, + ai_float *pDataOut_values_init, + ai_i32 *pDataOut_index_init, + const ai_size height_in, + const ai_size width_in, + const ai_size n_channel_in, + const ai_size k, ai_i16 largest, + void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) +); + + +#endif /*LITE_GENERIC_FLOAT_H*/ diff --git a/lib/stai/libstai/include/lite_gru_f32.h b/lib/stai/libstai/include/lite_gru_f32.h new file mode 100644 index 000000000..cd8c84703 --- /dev/null +++ b/lib/stai/libstai/include/lite_gru_f32.h @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * @file lite_gru_f32.h + * @author AIS + * @brief header file of AI platform lite gru kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_GRU_F32_H +#define LITE_GRU_F32_H + + +#include "ai_lite_interface.h" + +/*! + * @brief Forward function for a stateless GRU (gate recurrent unit) layer with + * signed float input, signed float output, and float parameters. + * @ingroup lite_gru_f32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param gru_kernel The pointer to gru kernel param. + * @param gru_recurrent The pointer to gru recurrent param. + * @param gru_bias The pointer to bias. + * @param gru_scratch The pointer to GRU scratch. + * @param n_units The number of GRU cells (dimensionality of output space). + * @param n_timesteps The number of timesteps of the input sequence. + * @param n_features The number of features of the input sequence. + * @param activation_nl The activation function used to update memory state. + * @param recurrent_nl The activation function to use for the recurrent step. + * @param return_seq If True, returns the full output sequence, else only the last output. + * @param go_backwards If True, process the input sequence backwards. + * @param reverse_seq If True, reverse the input sequence + * @param reset_after Whether to apply reset gate after (True) or before (False) matmul. + * @param activation_param The parameters for activation_nl (can be NULL) + * @param recurrent_param The parameters for recurrent_nl (can be NULL) + * @param initial_hidden Initial state of hidden layer (can be NULL) + */ +LITE_API_ENTRY +void forward_lite_gru_if32of32wf32( + ai_float* output, const ai_float* input, const ai_float* gru_kernel, + const ai_float* gru_recurrent, const ai_float* gru_bias, ai_float* gru_scratch, + const ai_u32 n_units, const ai_size n_timesteps, const ai_size n_features, + ai_handle activation_nl, ai_handle recurrent_nl, ai_bool return_seq, + ai_bool go_backwards, ai_bool reverse_seq, ai_bool reset_after, + const ai_float* activation_param, const ai_float* recurrent_param, + const ai_float* initial_hidden); + + +#endif /* LITE_GRU_F32_H */ diff --git a/lib/stai/libstai/include/lite_internal_apis.h b/lib/stai/libstai/include/lite_internal_apis.h new file mode 100644 index 000000000..481fbafe4 --- /dev/null +++ b/lib/stai/libstai/include/lite_internal_apis.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file lite_internal_apis.h + * @author STMicroelectronics + * @brief + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LITE_INTERNAL_APIS +#define LITE_INTERNAL_APIS + +#include "ai_platform.h" +#include "ai_lite_interface.h" + +/* lite_nl_generic_float */ +#define LITE_NL_ENTRY(nl_id_, nl_name_, nl_op_, nl_op_args_) \ +/** \ + * @brief lite function for a templated non-linearity nl_op_. \ + * @ingroup lite_nl_generic_float \ + * @param out_ptr The pointer to output buffer. \ + * @param in_ptr The pointer to input buffer. \ + * @param in_size. The size of the input. \ + * @param params opaque handler to optional NL params (not used). \ + */ \ +LITE_API_ENTRY \ +void forward_lite_nl_ ## nl_name_ ## _if32of32( \ + ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_handle params); + +#include "lite_nl_list.h" + +/** + * @brief lite function for a float softmax non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_float + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param in_size The size of the input. + * @param inner_loop_cnt The size of the inner loop (elements after the selected axis) + * @param axis_elem The elements number along the selected axis. + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_if32of32( + ai_handle out_ptr, const ai_handle in_ptr, + const ai_size in_size, const ai_size inner_loop_cnt, const ai_size axis_elem); + + +/** + * @brief lite function for a float softmax zero channel non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_float + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param in_size. The size of the input. + * @param channel_size The nsize of each channel. + * @param in_channel_step + * @param out_channel_step + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_zero_channel_if32of32( + ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_size ch_size, + const ai_i32 in_ch_step, const ai_i32 out_ch_step); + +/*! + * @typedef (*func_nl_lite) + * @ingroup layers_nl + * @brief Fuction pointer for generic non linear transform + * this function pointer abstracts a generic non linear layer. + * see @ref nl_func_tanh_array_f32 and similar as examples. + */ + typedef void (*func_nl_lite)(ai_handle out_ptr, const ai_handle in_ptr, + const ai_i32 in_size, const ai_handle params); + +/** + * @brief lite function for a float gelu non-linearity. + * @ingroup lite_nl_generic_float \ + * @param out_ptr The pointer to output buffer. \ + * @param in_ptr The pointer to input buffer. \ + * @param in_size. The size of the input. \ + * @param params opaque handler to optional NL params. \ + */ +LITE_API_ENTRY +void forward_lite_nl_gelu_if32of32( + ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_handle params); + +#endif /* LITE_INTERNAL_APIS */ diff --git a/lib/stai/libstai/include/lite_lstm.h b/lib/stai/libstai/include/lite_lstm.h new file mode 100644 index 000000000..06584e5a2 --- /dev/null +++ b/lib/stai/libstai/include/lite_lstm.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file lite_lstm.h + * @author AIS + * @brief header file of AI platform lite lstm kernel + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_LSTM_H +#define LITE_LSTM_H + +#include "ai_lite_interface.h" +#include "ai_math_helpers.h" + +#include "lite_internal_apis.h" + +enum { + AI_LITE_LSTM_INPUT = 0, + AI_LITE_LSTM_FORGET = 1, + AI_LITE_LSTM_CELL = 2, + AI_LITE_LSTM_OUTPUT = 3, + AI_LITE_LSTM_MAX +}; + +void forward_lite_lstm_if32of32wf32( AI_CONST ai_float* kernel, + AI_CONST ai_float* recurrent, + AI_CONST ai_float* bias, + func_nl_lite activation_nl, /**< activation nonlinearity (input to cell) */ + AI_CONST ai_float* activation_param, /**< activation NL parameters */ + func_nl_lite recurrent_nl, /**< recurrent nonlinearity (hidden to cell) */ + AI_CONST ai_float* recurrent_param, /**< activation NL parameters */ + ai_float* hidden, + AI_CONST ai_float* initial_hidden, + ai_float* out_hidden, + ai_u16 n_features, + ai_u16 n_cell, + AI_CONST ai_float* peepholes, + ai_handle state, + ai_float* cell, + AI_CONST ai_float* initial_cell, + func_nl_lite out_nl, + AI_CONST ai_float* out_param, + ai_float cell_clip, + ai_float* data_in, + ai_float** data_out, + ai_ptr_offset *out_offset, + ai_float* gates, + ai_i32 timesteps, + ai_i32 nb_t_out, + ai_bool go_backwards, + ai_bool reverse_seq, + ai_bool stateful, + ai_bool return_state); + + +void forward_lite_lstm_is8os8ws8( AI_CONST ai_i8* kernel[AI_LITE_LSTM_MAX], + AI_CONST ai_i8* recurrent[AI_LITE_LSTM_MAX], + AI_CONST ai_i32* bias[AI_LITE_LSTM_MAX], + AI_CONST ai_i8* initial_hidden, + ai_i8* out_hidden, + ai_u16 batch_size, + ai_u16 n_features, + ai_u16 n_cell, + AI_CONST ai_i16* initial_cell, + ai_i16* out_cell, + ai_i8* data_in, + const ai_i8 in_zeropoint, + const ai_float in_scale, + ai_i8* data_out, + const ai_i8 out_zeropoint, + const ai_float out_scale, + const ai_float kernel_scale[AI_LITE_LSTM_MAX], + const ai_float recurrent_scale[AI_LITE_LSTM_MAX], + ai_i32 timesteps, + ai_i32 nb_t_out, + ai_bool go_backwards, + ai_bool reverse_seq, + ai_bool stateful, + ai_bool time_major, + ai_bool return_state, + ai_i32 scratch_size, + ai_i8 *p_scratch_data); + +#endif /* LITE_LSTM_H */ + diff --git a/lib/stai/libstai/include/lite_maxpool_dqnn.h b/lib/stai/libstai/include/lite_maxpool_dqnn.h new file mode 100644 index 000000000..349d2e5be --- /dev/null +++ b/lib/stai/libstai/include/lite_maxpool_dqnn.h @@ -0,0 +1,157 @@ +/** + ****************************************************************************** + * @file lite_maxpool_dqnn.h + * @author AIS + * @brief header file of AI platform lite dqnn maxpool kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_MAXPOOL_DQNN_H +#define LITE_MAXPOOL_DQNN_H + + +#include "ai_lite_interface.h" + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles maxpool with binary input and binary output - Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is1os1(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i32 width_in, + const ai_i32 width_out, + const ai_i32 height_in, + const ai_i32 height_out, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 pool_width, + const ai_i32 pool_height, + const ai_i32 pool_pad_x, + const ai_i32 pool_pad_y, + const ai_i32 pool_stride_x, + const ai_i32 pool_stride_y, + const ai_u32 pool_pad_value, + ai_float *pScratch_32); + + +/*! + * @brief Handles maxpool with 8 bits signed input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is8os8_scalepos(const ai_i8 *pDataIn, + ai_i8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint); + + +/*! + * @brief Handles maxpool with 8 bits signed input and output with a negative scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is8os8_scaleneg(const ai_i8 *pDataIn, + ai_i8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint); + + +/*! + * @brief Handles maxpool with 8 bits unsigned input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_iu8ou8_scalepos(const ai_u8 *pDataIn, + ai_u8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_u8 In_ZeroPoint, + const ai_u8 Out_ZeroPoint); + + +/*! + * @brief Handles maxpool with 8 bits unsigned input and output with a negative scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_iu8ou8_scaleneg(const ai_u8 *pDataIn, + ai_u8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_u8 In_ZeroPoint, + const ai_u8 Out_ZeroPoint); + +/*! + * @brief Handles maxpool with 16 bits signed input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is16os16_scalepos(const ai_i16 *pApInput, + ai_i16 *pApOutput, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_i16 In_ZeroPoint, + const ai_i16 Out_ZeroPoint); + +/*! + * @brief Handles maxpool with 16 bits unsigned input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_iu16ou16_scalepos(const ai_u16 *pApInput, + ai_u16 *pApOutput, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_u16 In_ZeroPoint, + const ai_u16 Out_ZeroPoint); + +#endif /*LITE_MAXPOOL_DQNN_H*/ diff --git a/lib/stai/libstai/include/lite_nl_generic_integer.h b/lib/stai/libstai/include/lite_nl_generic_integer.h new file mode 100644 index 000000000..b40648032 --- /dev/null +++ b/lib/stai/libstai/include/lite_nl_generic_integer.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file lite_nl_generic_integer.h + * @author AIS + * @brief header file of AI platform lite integer non linearities + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_NL_GENERIC_INTEGER_H +#define LITE_NL_GENERIC_INTEGER_H + + +#include "ai_lite_interface.h" + +/** + * @brief forward lite function for a s8 softmax non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_integer + * @param output The pointer to output buffer (s8). + * @param input The pointer to input buffer (s8). + * @param in_size The size of the input (including channels). + * @param inner_loop_cnt The size after the selected axis. + * @param axis_elem size The number of elements along the selected axis. + * @param mult + * @param shift + * @param min_diff + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_is8os8( + ai_i8* out_ptr, const ai_i8* in_ptr, + const ai_size in_size, const ai_size inner_loop_cnt, const ai_size axis_elem, + const ai_i32 mult, const ai_i32 shift, const ai_i32 min_diff, + ai_i32* scratch); + + +/** + * @brief forward lite function for a u8 softmax non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_integer + * @param output The pointer to output buffer (s8). + * @param input The pointer to input buffer (s8). + * @param in_size The size of the input (including channels). + * @param inner_loop_cnt The size after the selected axis. + * @param axis_elem size The number of elements along the selected axis. + * @param mult + * @param shift + * @param min_diff + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_iu8ou8( + ai_u8* out_ptr, const ai_u8* in_ptr, + const ai_size in_size, const ai_size inner_loop_cnt, const ai_size axis_elem, + const ai_i32 mult, const ai_i32 shift, const ai_i32 min_diff, + ai_i32* scratch); + +#endif /* LITE_NL_GENERIC_INTEGER_H */ diff --git a/lib/stai/libstai/include/lite_nl_list.h b/lib/stai/libstai/include/lite_nl_list.h new file mode 100644 index 000000000..e0638ccbd --- /dev/null +++ b/lib/stai/libstai/include/lite_nl_list.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file lite_nl_list.h + * @author STMicroelectronics + * @brief header file of lite supported non-linearities routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +// #define LITE_NL_ENTRY(nl_id_, nl_name_, nl_op_, nl_op_args_) + +/* No sentry. This is deliberate!! */ + +LITE_NL_ENTRY(1, abs, AI_ABS, 1) +LITE_NL_ENTRY(2, acos, AI_MATH_ACOS, 1) +LITE_NL_ENTRY(3, acosh, AI_MATH_ACOSH, 1) +LITE_NL_ENTRY(4, asin, AI_MATH_ASIN, 1) +LITE_NL_ENTRY(5, asinh, AI_MATH_ASINH, 1) +LITE_NL_ENTRY(6, atan, AI_MATH_ATAN, 1) +LITE_NL_ENTRY(7, atanh, AI_MATH_ATANH, 1) +LITE_NL_ENTRY(8, ceil, AI_CEIL, 1) +LITE_NL_ENTRY(9, cos, AI_MATH_COS, 1) +LITE_NL_ENTRY(10, cosh, AI_MATH_COSH, 1) +LITE_NL_ENTRY(11, erf, AI_MATH_ERF, 1) +LITE_NL_ENTRY(12, exp, AI_MATH_EXP, 1) +LITE_NL_ENTRY(13, floor, AI_FLOOR, 1) +LITE_NL_ENTRY(14, hardmax, /**/, 0) +LITE_NL_ENTRY(15, log, AI_MATH_LOG, 1) +LITE_NL_ENTRY(16, logistic, AI_MATH_LOGISTIC, 1) +LITE_NL_ENTRY(17, neg, AI_NEG, 1) +LITE_NL_ENTRY(18, rsqrt, AI_MATH_RSQRT, 1) +LITE_NL_ENTRY(19, sin, AI_MATH_SIN, 1) +LITE_NL_ENTRY(20, sinh, AI_MATH_SINH, 1) +LITE_NL_ENTRY(21, tan, AI_MATH_TAN, 1) +LITE_NL_ENTRY(22, square, AI_MATH_SQUARE, 1) +LITE_NL_ENTRY(23, reciprocal, AI_RECIPROCAL, 1) +LITE_NL_ENTRY(24, round, AI_ROUND, 1) +LITE_NL_ENTRY(25, sigmoid, AI_MATH_SIGMOID, 1) +LITE_NL_ENTRY(26, swish, AI_MATH_SWISH, 1) +LITE_NL_ENTRY(27, hard_swish, AI_MATH_HARD_SWISH, 1) +LITE_NL_ENTRY(28, sign, AI_SIGN, 1) +LITE_NL_ENTRY(29, sqrt, AI_MATH_SQRT, 1) +// LITE_NL_ENTRY(30, softmax, /**/, 0) // for future changes +// LITE_NL_ENTRY(31, softmax_zero_channel, /**/, 0) // for future changes +LITE_NL_ENTRY(32, soft_plus, AI_MATH_SOFT_PLUS, 1) +LITE_NL_ENTRY(33, soft_sign, AI_MATH_SOFT_SIGN, 1) +LITE_NL_ENTRY(34, tanh, AI_MATH_TANH, 1) +LITE_NL_ENTRY(35, prelu, /**/, 0) +LITE_NL_ENTRY(36, relu, AI_MATH_RELU, 1) +LITE_NL_ENTRY(37, relu_generic, /**/, 0) + +LITE_NL_ENTRY(101, elu, AI_MATH_ELU, 2) +LITE_NL_ENTRY(102, relu_thresholded, AI_MATH_RELU_THRESHOLDED, 2) + + +LITE_NL_ENTRY(201, clip, AI_CLAMP, 3) +LITE_NL_ENTRY(202, hard_sigmoid, AI_MATH_HARD_SIGMOID, 3) +LITE_NL_ENTRY(203, selu, AI_MATH_SELU, 3) +// LITE_NL_ENTRY(204, gelu, AI_MATH_GELU, 2) + + +#undef LITE_NL_ENTRY +#undef LITE_NL_IIF_0 +#undef LITE_NL_IIF_1 +#undef LITE_NL_IIF_2 +#undef LITE_NL_IIF_3 diff --git a/lib/stai/libstai/include/lite_norm_f32.h b/lib/stai/libstai/include/lite_norm_f32.h new file mode 100644 index 000000000..1de19a93b --- /dev/null +++ b/lib/stai/libstai/include/lite_norm_f32.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file lite_norm_f32.h + * @author AIS + * @brief header file of AI platform norm in lite mode + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_NORM_F32_H +#define LITE_NORM_F32_H +#pragma once + +#include "ai_lite_interface.h" + +enum ai_lite_norm_type_ { + AI_LITE_NORM_NONE = 0, + AI_LITE_NORM_L1 = 1, + AI_LITE_NORM_L2 = 2, + AI_LITE_NORM_MAX = 3, +}; + +/*! + * @brief Forward function for a batch normalization (BN) layer with + * signed float input, signed float output, and float parameters. + * @ingroup lite_norm_f32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param scale The pointer to BN scale param. + * @param bias The pointer to bias. + * @param n_elements The number of elements in the input tensor. + * @param n_channel_in The number of channel in the input tensor. + */ +LITE_API_ENTRY +void forward_lite_norm_if32of32( ai_float* output, + const ai_float* input, + const ai_u32 ai_lite_norm_type, + const ai_float exponent, + const ai_size n_axis, + const ai_size n_axis_stride, + const ai_size n_el, + ai_bool scale); + +#endif /* LITE_NORM_F32_H */ diff --git a/lib/stai/libstai/include/lite_operators.h b/lib/stai/libstai/include/lite_operators.h new file mode 100644 index 000000000..04fbff1e7 --- /dev/null +++ b/lib/stai/libstai/include/lite_operators.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file lite_operators.h + * @author AIS + * @brief main header file of AI platform lite operators list + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_OPERATORS_H +#define LITE_OPERATORS_H + +#include "lite_internal_apis.h" + +#include "lite_bn_f32.h" +#include "lite_bn_integer.h" +#include "lite_conv2d.h" +#include "lite_conv2d_dqnn.h" +#include "lite_conv2d_is16.h" +#include "lite_convert_dqnn.h" +#include "lite_dense_if32.h" +#include "lite_dense_is1.h" +#include "lite_dense_is16.h" +#include "lite_dense_is1ws1.h" +#include "lite_dense_ws1.h" +#include "lite_gru_f32.h" +#include "lite_dw_dqnn.h" +#include "lite_pw_dqnn.h" +#include "lite_conv2d_sssa8_ch.h" + +#include "lite_dense_is8os8ws8.h" +#include "lite_dense_is8os1ws1.h" +#include "lite_generic_float.h" +#include "lite_pool_f32.h" +#include "lite_maxpool_dqnn.h" +#include "lite_nl_generic_integer.h" +#include "lite_pad_generic.h" +#include "lite_pad_dqnn.h" +#include "lite_upsample_generic.h" +#include "lite_resize.h" +#include "lite_lstm.h" +#include "lite_argminmax.h" +#include "lite_pool_is8os8.h" + +#endif /* LITE_OPERATORS_H */ diff --git a/lib/stai/libstai/include/lite_pad_dqnn.h b/lib/stai/libstai/include/lite_pad_dqnn.h new file mode 100644 index 000000000..afc585131 --- /dev/null +++ b/lib/stai/libstai/include/lite_pad_dqnn.h @@ -0,0 +1,48 @@ +/** + ****************************************************************************** + * @file lite_pad_dqnn.h + * @author AIS + * @brief header file of AI platform lite padding kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PADDING_DQNN_H +#define LITE_PADDING_DQNN_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles padding with binary input and binary output - Lite I/F + * @ingroup lite_padding_dqnn + */ +LITE_API_ENTRY +void forward_lite_pad_is1os1(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i32 width_in, + const ai_i32 width_out, + const ai_i32 height_in, + const ai_i32 height_out, + const ai_u32 n_channel_out, + const ai_i32 mode, + const ai_u16 pads_x, + const ai_u16 pads_y, + const ai_u16 pads_x_r, + const ai_u16 pads_y_b, + const ai_u32 pad_value); + + +#endif /*LITE_PADDING_DQNN_H*/ diff --git a/lib/stai/libstai/include/lite_pad_generic.h b/lib/stai/libstai/include/lite_pad_generic.h new file mode 100644 index 000000000..7a15a821c --- /dev/null +++ b/lib/stai/libstai/include/lite_pad_generic.h @@ -0,0 +1,111 @@ +/** + ****************************************************************************** + * @file lite_pad_generic.h + * @author AIS + * @brief header file of AI platform lite padding kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PAD_GENERIC_H +#define LITE_PAD_GENERIC_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles padding with 8 bits input/output in constant mode - Lite I/F + * Channel 1st Format Input and Output + * @ingroup lite_padding_dqnn + */ + +/* Variant used for padding pattern = (1, 1, 1, 1) */ +LITE_API_ENTRY +void forward_lite_pad_8bit_ch1st_3x3_constant_P1111(ai_ptr_const in_data_tensor, + ai_ptr out_data_tensor, + const ai_handle fill_value, + const ai_i32 height_in, + const ai_i32 channel_in, + const ai_ptr_offset ch_stride_in, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset h_stride_pad); + +/* Variant used for padding pattern = (0, 0, 2, 2) */ +LITE_API_ENTRY +void forward_lite_pad_8bit_ch1st_3x3_constant_P0022(ai_ptr_const in_data_tensor, + ai_ptr out_data_tensor, + const ai_handle fill_value, + const ai_i32 height_in, + const ai_i32 channel_in, + const ai_ptr_offset ch_stride_in, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset h_stride_pad); + +/*! + * @brief Handles padding with 8 bits input/output in constant mode - Lite I/F + * @ingroup lite_padding_dqnn + */ +LITE_API_ENTRY +void forward_lite_pad_constant(ai_ptr_const in_data, + ai_ptr out_data, + const ai_handle fill_value, + const ai_i16 in_bits, + const ai_i32 height_in, + const ai_ptr_offset ch_stride_in, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset h_stride_pad, + const ai_ptr_offset h_stride_pad_b, + const ai_ptr_offset w_stride_pad, + const ai_ptr_offset w_stride_pad_r); + +/*! + * @brief Handles padding with 8 bits input/output in edge mode - Lite I/F + * @ingroup lite_padding_dqnn + */ +void forward_lite_pad_edge(ai_ptr_const in_data_tensor, + ai_ptr out_data, + const ai_i32 height_in, + const ai_i16 pads_y, + const ai_i16 pads_x_r, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset w_stride_in, + const ai_ptr_offset h_stride_out, + const ai_ptr_offset h_stride_pad, + const ai_ptr_offset w_stride_pad, + const ai_ptr_offset h_stride_pad_b); + +/*! + * @brief Handles padding with 8 bits input/output in reflect mode - Lite I/F + * @ingroup lite_padding_dqnn + */ +void forward_lite_pad_reflect(ai_ptr_const in_data, + ai_ptr out_data, + const ai_i32 depth, + const ai_i32 height_in, + const ai_i32 width_in, + const ai_i32 height_out, + const ai_i32 width_out, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset w_stride_in, + const ai_ptr_offset h_stride_out, + const ai_ptr_offset w_stride_out, + const ai_i16 pads_x, + const ai_i16 pads_y, + const ai_i16 pads_y_b, + const ai_ptr_offset h_stride_pad, + const ai_ptr_offset w_stride_pad, + const ai_ptr_offset w_stride_pad_r); + +#endif /* LITE_PAD_GENERIC_H */ diff --git a/lib/stai/libstai/include/lite_pool_f32.h b/lib/stai/libstai/include/lite_pool_f32.h new file mode 100644 index 000000000..2603bbb06 --- /dev/null +++ b/lib/stai/libstai/include/lite_pool_f32.h @@ -0,0 +1,69 @@ +/** + ****************************************************************************** + * @file lite_maxpool_dqnn.h + * @author AIS + * @brief header file of AI platform lite maxpool kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_POOL_F32_H +#define LITE_POOL_F32_H + +#include "ai_lite_interface.h" + + +#define FUNC_POOL(handle) \ + ((func_pool)(handle)) + + +/*! + * @typedef (*func_pool) + * @ingroup layers_pool + * @brief Fuction pointer for generic pooling transform + * this function pointer abstracts a generic pooling layer. + * see @ref pool_func_ap_array_f32 as examples + */ +typedef void (*func_pool)(ai_float* in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_float* out); + + +/******************************************************************************/ +/** Conv2d Functions Section **/ +/******************************************************************************/ + +AI_INTERNAL_API +void pool_func_mp_array_f32(ai_float* pData_in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_float* pData_out); + +AI_INTERNAL_API +void pool_func_ap_array_f32(ai_float *pData_in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_float *pData_out); + +#endif // LITE_POOL_F32_H_ diff --git a/lib/stai/libstai/include/lite_pool_is8os8.h b/lib/stai/libstai/include/lite_pool_is8os8.h new file mode 100644 index 000000000..34a2c654e --- /dev/null +++ b/lib/stai/libstai/include/lite_pool_is8os8.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file lite_pool_is8os8.h + * @author AIS + * @brief header file of AI platform lite integer pooling function + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_POOL_IS8OS8 +#define LITE_POOL_IS8OS8 + +#include "ai_lite_interface.h" + +/** + * @brief lite function for average pooling. + * @ingroup lite_nl_generic_integer + * @param input The pointer to input buffer. + * @param output The pointer to output buffer. + * @param[in] dim_im_in_x dimension of the input width + * @param[in] dim_im_in_y dimension of the input height + * @param[in] ch_im_in number of the input channel + * @param[in] dim_kernel_x dimension of the kernel width + * @param[in] dim_kernel_y dimension of the kernel height + * @param[in] padding_x first dimension of the padding + * @param[in] padding_y second dimension of the padding + * @param[in] stride_x first dimension of the stride + * @param[in] stride_y second dimension of the stride + * @param[in] dim_im_out_x dimension of the output width + * @param[in] dim_im_out_y dimension of the output height + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + */ +void forward_lite_avepool_is8os8( const ai_i8 *pData_in, + ai_i8* pData_out, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_float in_scale, + const ai_i8 in_zeropoint, + const ai_float out_scale, + const ai_i8 out_zeropoint); +#endif /* LITE_POOL_IS8OS8 */ + diff --git a/lib/stai/libstai/include/lite_pw.h b/lib/stai/libstai/include/lite_pw.h new file mode 100644 index 000000000..5f9e40cb3 --- /dev/null +++ b/lib/stai/libstai/include/lite_pw.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file lite_pw.h + * @author AIS + * @brief header file of AI platform lite pointwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PW_H +#define LITE_PW_H + + +#include "ai_lite_interface.h" + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles pw convolutions generic case + * @ingroup lite_pw + */ +LITE_API_ENTRY +void +forward_lite_pw_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_pw_hsp_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_pw_hsp_1step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + + +void +forward_lite_pw_hsp_3step_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +#endif /*LITE_PW_H*/ diff --git a/lib/stai/libstai/include/lite_pw_dqnn.h b/lib/stai/libstai/include/lite_pw_dqnn.h new file mode 100644 index 000000000..b818f3d24 --- /dev/null +++ b/lib/stai/libstai/include/lite_pw_dqnn.h @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file lite_pw_dqnn.h + * @author AIS + * @brief header file of AI platform lite dqnn pointwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PW_DQNN_H +#define LITE_PW_DQNN_H + + +#include "ai_lite_interface.h" + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os1ws1_bn(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 *pThreshold); + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights - Lite API version - Optimized thanks to Optim2 + * assumptions + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os1ws1_bn_optim2(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 *pThreshold); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os8ws1_bn(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights - Lite API version - Optimized thanks to Optim1 + * assumptions + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os8ws1_bn_optim1(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1of32ws1_bn(const ai_u32 *pDataIn_init, + ai_float *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights - Lite API version - Optimized thanks to Optim1 + * assumptions + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1of32ws1_bn_optim1(const ai_u32 *pDataIn_init, + ai_float *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + + +#endif /*LITE_PW_DQNN_H*/ diff --git a/lib/stai/libstai/include/lite_resize.h b/lib/stai/libstai/include/lite_resize.h new file mode 100644 index 000000000..4203649dd --- /dev/null +++ b/lib/stai/libstai/include/lite_resize.h @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file lite_resize.h + * @author AIS + * @brief header file of AI platform lite resize kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + + ****************************************************************************** + */ +#ifndef LITE_RESIZE_H +#define LITE_RESIZE_H +#pragma once + +#include "ai_lite_interface.h" + +void forward_lite_resize_nearest(ai_ptr in_data, + ai_ptr out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_ptr_offset stride_ch, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_nearest_mode mode, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +void forward_lite_resize_bilinear_if32of32( const ai_float* in_data, + ai_float* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +void forward_lite_resize_bilinear_is8os8( const ai_i8* in_data, + ai_i8* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +void forward_lite_resize_bilinear_is16os16( const ai_i16* in_data, + ai_i16* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +#endif /*LITE_RESIZE__H*/ diff --git a/lib/stai/libstai/include/lite_upsample.h b/lib/stai/libstai/include/lite_upsample.h new file mode 100644 index 000000000..094dbcfa6 --- /dev/null +++ b/lib/stai/libstai/include/lite_upsample.h @@ -0,0 +1,239 @@ +/** + ****************************************************************************** + * @file lite_upsample.h + * @author AIS + * @brief header file of AI platform lite upsample kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_UPSAMPLE_H +#define LITE_UPSAMPLE_H +#pragma once + +#include "ai_lite_interface.h" + + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are float. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_if32of32(const ai_float* in_data, + ai_float* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are signed int8. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_is8os8(const ai_i8* in_data, + ai_i8* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are unsinged int8. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_iu8ou8(const ai_u8* in_data, + ai_u8* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are signed int16. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] center centered coordinates + * @param[in] channel_in input/output channels. + */ +void forward_lite_upsample_bilinear_is16os16(const ai_i16* in_data, + ai_i16* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are unsigned int16. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_iu16ou16(const ai_u16* in_data, + ai_u16* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in zero mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are singed int8. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] zero_s8 out zeropoint value + */ +void forward_lite_upsample_zeros_is8os8( const ai_i8 *in_data, + ai_i8 *out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size channel_in, + const ai_i8 zero_s8); + +/** + * @brief Function to upsample in zero mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are signed int16. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] zero_s16 out zeropoint value + */ +void forward_lite_upsample_zeros_is16os16( const ai_i16 *in_data, + ai_i16 *out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size channel_in, + const ai_size width_out, + const ai_size height_out, + const ai_i16 zero_s16); + +/** + * @brief Function to upsample in zero mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are float. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + */ +void forward_lite_upsample_zeros_if32of32( const ai_float *in_data, + ai_float *out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size channel_in, + const ai_size width_out, + const ai_size height_out); + +#endif /*LITE_UPSAMPLE__H*/ diff --git a/lib/stai/libstai/include/lite_upsample_generic.h b/lib/stai/libstai/include/lite_upsample_generic.h new file mode 100644 index 000000000..fdf32d6e0 --- /dev/null +++ b/lib/stai/libstai/include/lite_upsample_generic.h @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * @file lite_upsample.h + * @author AIS + * @brief header file of AI platform lite upsample kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_UPSAMPLE_GENERIC_H +#define LITE_UPSAMPLE_GENERIC_H + + +#include "ai_lite_interface.h" + + +void forward_lite_upsample_generic_nearest(const ai_u8* in_data, + ai_u8* out_data, + const ai_size width_in, + const ai_size width_out, + const ai_float width_scale, + const ai_size height_out, + const ai_float height_scale, + const ai_u32 output_tensor_w_stride, + const ai_float offset_round_coeff); + +void forward_lite_upsample_nearest(ai_ptr in_data, + ai_ptr out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_ptr_offset stride_w, + const ai_float offset_round_coeff); + +void forward_lite_upsample_zeros( ai_ptr in_data, + ai_ptr out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_ptr_offset stride_ch, + const ai_ptr_offset stride_w, + const ai_handle p_zero_value); + +#endif /*LITE_UPSAMPLE_GENERIC_H*/ diff --git a/lib/stai/libstai/include/ll_aton.h b/lib/stai/libstai/include/ll_aton.h new file mode 100644 index 000000000..32ea2c44f --- /dev/null +++ b/lib/stai/libstai/include/ll_aton.h @@ -0,0 +1,799 @@ +/** + ****************************************************************************** + * @file ll_aton.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_H +#define __LL_ATON_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include + +#include "ll_aton_attributes.h" +#include "ll_aton_config.h" + +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_EC_TRACE) +#include "ll_aton_osal.h" +#include "ll_aton_platform.h" +#endif // LL_ATON_PLATFORM != LL_ATON_PLAT_EC_TRACE + +/** @defgroup ATON_LL ATON_LL_Driver + * @{ + */ + +/* LL ATON error codes */ +#define LL_ATON_OK (0) +#define LL_ATON_INVALID_ID (-1) +#define LL_ATON_INVALID_PARAM (-2) +#define LL_ATON_TIMEOUT (-3) + + /* this is needed to avoid some compilers (e.g. KEIL) that observe a strict semantic about conversion of + * pointers to integers in const initializers + */ + typedef union + { + unsigned char *p; + uintptr_t i; + } ll_aton_pointer; + + /* Method that translates an address from physical to virtual */ + unsigned char *LL_Address_Physical2Virtual(unsigned char *address); + + /* Method that translates an address from virtual to physical */ + unsigned char *LL_Address_Virtual2Physical(unsigned char *address); + +/** + * @brief ATON User Configuration macros + */ +/* Set beyond macro to 1 if you want to enable the generation of ATON event interrupts */ +#ifndef LL_ATON_EN_EVENT_IRQ +#define LL_ATON_EN_EVENT_IRQ 1 +#endif + +/* Set beyond macro to 1 if you want to enable the generation of ATON configuration error interrupts */ +#ifndef LL_ATON_EN_ERROR_IRQ +#define LL_ATON_EN_ERROR_IRQ 1 +#endif + + /** @defgroup ATON_INIT ATON Global initialization/deinitialization functions + * @{ + */ + int LL_ATON_Init(void); + int LL_ATON_DeInit(void); + /** + * @} + */ + + /** + * @brief List of acceleration units types + */ + enum AccelUnitsType + { + STRENG = 0, + STRENG64, + CONVACC, + DECUN, + ACTIV, + ARITH, + POOL, + IMC, + RECBUF, + }; + + typedef struct + { + enum AccelUnitsType unit_type; + unsigned short unit_num; + } AccelUnits; + + /** + * @brief Converts an Aton unit cardinal group id into a global one + * @param type enum specifying the unit group + * @param id Cardinal id of the unit in the group + * @retval ATON Unit index + * @todo Add boundary checks + */ + static inline AccelUnits LL_ATON_GetUnit_From_Cardinal_ID(enum AccelUnitsType type, int id) + { + return (AccelUnits){type, (unsigned short)id}; + } + + /** + * @brief Activation Unit function types + */ + typedef enum + { + ACTIV_RELU = 1, + ACTIV_PRELU, + ACTIV_TRELU, + ACTIV_FUNC, + ACTIV_LUT + } LL_Activacc_Op; + + /** + * @brief Activation unit Accelerator configuration structure + */ + typedef struct + { + unsigned rounding_f : 1; /**< Input feature data rounding control: 1=enable,0=disable */ + unsigned saturation_f : 1; /**< Input feature data saturation control: 1=enable,0=disable */ + unsigned round_mode_f : 2; /**< Input feature round mode */ + unsigned inbytes_f : 2; /**< Input data width in bytes. Valid values are 1, 2 or 3 bytes */ + unsigned outbytes_f : 2; /**< Input feature output bytes after shift. Valid values are 1 or 2 bytes */ + unsigned rounding_o : 1; /**< Output rounding control, 1=enable,0=disable */ + unsigned saturation_o : 1; /**< Output saturation control,1=enable,0=disable */ + unsigned round_mode_o : 1; /**< Output rounding mode */ + unsigned relu_mode_o : 1; /**< Apply Relu operation before rounding */ + unsigned outbytes_o : 2; /**< Number of output bytes: 1, 2 or 3 */ + unsigned signedop : 1; /**< Signed/unsigned activations: 0: unsigned activations, 1 signed */ + unsigned char shift_f; /**< Input feature data shift. Negative values represent left shifts */ + unsigned char shift_o; /**< Optional right shift to be applied to the function evaluator final result */ + unsigned parameter; /**< ReLU parameter */ + unsigned parameter_2; /**< Zero offset for TRELU operation for use in scale/offset integer arithmetic. + * Needs zp alignment */ + unsigned nbytes; /**< Number of bytes of input data */ + ll_aton_pointer ROM0_vector; /**< Address of ROM0 coefficients table */ + ll_aton_pointer ROM1_vector; /**< Address of ROM1 coefficients table */ + ll_aton_pointer LUT_vector; /**< Address of LUT coefficients table */ + unsigned ROM0_nbytes; /**< Length of ROM0 table */ + unsigned ROM1_nbytes; /**< Length of ROM1 table */ + unsigned char shift_b; /**< Optional left shift to be applied to coefficient B */ + unsigned char shift_c; /**< Optional left shift to be applied to coefficient C */ + unsigned char shift_norm; /**< Function input range normalization left shift parameter */ + unsigned char bwidth; /**< Number of MSB bits of the input activation to be used to address ROM0. + * This field configures the number of outer segments (max outer segments = 32). + * Valid values range = 0,1,2,3,4 and 5 corresponding to 1,2,4,8,16 and 32 outer segment(s) + * respectively */ + int fsub; /**< Feature data subtract value */ + LL_Activacc_Op operation; /**< Activation type. See LL_Activacc_Op */ + } LL_Activacc_InitTypeDef; + + /** @defgroup LL_ACTIV Activation unit configuration functions + * @{ + */ + int LL_Activacc_Init(int id, const LL_Activacc_InitTypeDef *Activacc_InitStruct); + /** + * @} + */ + + /** + * @brief Arithmetic unit operations + */ + typedef enum + { + ARITH_AFFINE = 1, + ARITH_MIN, + ARITH_MAX, + ARITH_MUL, + ARITH_X_AND_Y, + ARITH_X_OR_Y, + ARITH_NOT_X, + ARITH_X_XOR_Y, + ARITH_X_EQ_Y, + ARITH_X_LT_Y, + ARITH_X_LE_Y, + ARITH_X_GT_Y, + ARITH_X_GE_Y, + ARITH_ABS_X, + ARITH_SIGN_X, + ARITH_CLIP + } LL_Arithacc_Op; + + /** + * @brief Arithmetic constant broadcast modes + */ + typedef enum + { + ARITH_BCAST_NONE, + ARITH_BCAST_CHAN, + ARITH_BCAST_HEIGHT, + ARITH_BCAST_WIDTH, + ARITH_BCAST_HEIGHT_WIDTH, + ARITH_BCAST_SCALAR, + } LL_Arithacc_Bcast; + + /** + * @brief Arithmetic unit Accelerator configuration structure + */ + typedef struct + { + unsigned rounding_x : 1; /**< Input feature data rounding for stream X */ + unsigned saturation_x : 1; /**< Input feature data saturation for stream X */ + unsigned round_mode_x : 2; /**< Input feature data rounding mode for stream X */ + unsigned inbytes_x : 2; /**< Input data width in bytes for stream X. Valid values are 1, 2 or 3 bytes */ + unsigned outbytes_x : 2; /**< Number of output bytes to use for input feature data of stream X after rounding or + * saturation. Valid values are 1 or 2 bytes */ + signed char shift_x; /**< Input feature data shift for stream X. Use negative values for left shift */ + unsigned rounding_y : 1; /**< Input feature data rounding for stream Y */ + unsigned saturation_y : 1; /**< Input feature data saturation for stream Y */ + unsigned round_mode_y : 2; /**< Input feature data rounding mode for stream Y */ + unsigned inbytes_y : 2; /**< Input data width in bytes for stream Y. Valid values are 1, 2 or 3 bytes */ + unsigned outbytes_y : 2; /**< Number of output bytes to use for input feature data of stream Y after rounding or + * saturation. Valid values are 1 or 2 bytes */ + unsigned combinebc : 1; /**< Combine coeff B and C to form a 32b coeff BC = {B[15:0],C[15:0]} */ + unsigned clipout : 1; /**< Controls output clipping to range specified by clip range configuration, 1=enable, + * 0=disable */ + signed char shift_y; /**< Input feature data shift for stream Y. Use negative values for left shift */ + unsigned rounding_o : 1; /**< Rounding control, 1=enable, 0=disable */ + unsigned saturation_o : 1; /**< Saturation control, 1=enable, 0=disable */ + unsigned round_mode_o : 1; /**< Otput rounding mode control */ + unsigned relu_mode_o : 1; /**< Apply Relu operation before rounding */ + unsigned outbytes_o : 2; /**< Number of output bytes: 1 or 2 */ + unsigned char shift_o; /**< Optional right shift to apply to final result of operation */ + unsigned scalar : 1; /**< Set Scalar/Vector mode */ + unsigned dualinput : 1; /**< Dual input control, 1=both X,Y streams valid, 0=only X stream is valid */ + LL_Arithacc_Op operation; /**< Arithmetic operation to be applied. See LL_Arithacc_Op */ + LL_Arithacc_Bcast bcast; /**< Set constant broadcast modes. See LL_Arithacc_Bcast */ + unsigned char Ax_shift; /**< Optional right shift to result of Ax */ + unsigned char By_shift; /**< Optional right shift to result of By */ + unsigned char C_shift; /**< Optional left shift to apply to C */ + unsigned fWidth; /**< Feature width */ + unsigned fHeight; /**< Feature height */ + unsigned short fChannels; /**< Number of feature channels */ + unsigned short batchDepth; /**< Batch depth */ + short clipmin; /**< Signed 16b value specifying output clip min */ + short clipmax; /**< Signed 16b value specifying output clip max */ + short A_scalar; /**< Scalar coefficient A */ + short B_scalar; /**< Scalar coefficient B */ + short C_scalar; /**< Scalar coefficient C */ + ll_aton_pointer A_vector; /**< Address of A vector table */ + ll_aton_pointer B_vector; /**< Address of B vector table */ + ll_aton_pointer C_vector; /**< Address of C vector table */ + unsigned char vec_precision[3]; /**< Number of bits for A, B and C vectors */ + } LL_Arithacc_InitTypeDef; + + /** @defgroup LL_ARITH Arithmetic Unit configuration functions + * @{ + */ + int LL_Arithacc_Init(int id, const LL_Arithacc_InitTypeDef *Arithacc_InitStruct); + /** + * @} + */ + + typedef enum + { + AFILT_MODE_NONE = 0, + AFILT_MODE_PIXELDROP = 1, + AFILT_MODE_FRAMEDROP = 2, + AFILT_MODE_FRAMEZERO = 3 + } LL_Convacc_Afilt_Mode; + + /** + * @brief Convolutional Accelerator configuration structure + */ + typedef struct + { + unsigned rounding_f : 1; /**< Input feature data rounding */ + unsigned saturation_f : 1; /**< Input feature data saturation */ + unsigned round_mode_f : 2; /**< Output data rounding mode */ + unsigned inbytes_f : 2; /**< Input data width in bytes */ + unsigned rounding_o : 1; /**< Output data rounding after right shift */ + unsigned saturation_o : 1; /**< Output saturation */ + unsigned round_mode_o : 1; /**< Output data rounding mode */ + unsigned relu_mode_o : 1; /**< Apply Relu operation before rounding */ + unsigned outbytes_o : 2; /**< Output data width in bytes */ + unsigned simd : 2; /**< Enable 8x8bit (1) or 16x8bit (2) SIMD mode */ + unsigned accumulate : 1; /**< Sum and synchronize with stream link input #2 */ + unsigned accumulate_first : 1; /**< No sum and synchronization with stream link input #2 for the first frame */ + unsigned accumulate_gen_first : 1; /**< Generate first accumulator input frame internally */ + unsigned fstat : 1; /**< Feature data stationary */ + unsigned raw_o : 1; /**< Use RAW file output format */ + unsigned kt1_mode : 1; /**< Load kernel from T1 buffer */ + unsigned deepmode : 1; /**< Enable Deep1x1 optimized mode */ + unsigned dss2mode : 1; /**< Enable DSS2 (depth separable stride 2) optimized mode */ + unsigned f_unsigned : 1; /**< Feature data unsigned */ + unsigned k_unsigned : 1; /**< Kernel data unsigned */ + unsigned kseten : 2; /**< Enable kernel set 0 (bit 0) or 1 (bit 1) if KT1 is 1, + * otherwise select byte 1 (0), byte 2 (1), byte 3 (2) or + * all bytes (Deep1x1 mode only) (3) of kernel stream in SIMD mode */ + unsigned char shift_f; /**< Input feature data shift */ + unsigned char shift_a; /**< Accumulator data input signed left shift */ + unsigned char shift_o; /**< Result data output signed right shift */ + unsigned fWidth; /**< Feature data width */ + unsigned fHeight; /**< Feature data height */ + unsigned char kernelWidth; /**< Kernel width */ + unsigned char kernelHeight; /**< Kernel height */ + unsigned char nKernels; /**< Total number of parallel kernels */ + unsigned short batchDepth; /**< Batch Depth */ + unsigned char hstride; /**< Horizontal stride */ + unsigned char vstride; /**< Vertical stride */ + unsigned short left_padding; /**< Number of vertical left dummy columns */ + unsigned short right_padding; /**< Number of vertical right dummy columns */ + unsigned short top_padding; /**< Number of horizontal top dummy lines */ + unsigned short bot_padding; /**< Number of horizontal bottom dummy lines */ + unsigned short left_crop; /**< Left feature data boundary */ + unsigned short right_crop; /**< Right feature data boundary */ + unsigned short top_crop; /**< Top feature data boundary */ + unsigned short bot_crop; /**< Bottom feature data boundary */ + unsigned short fstatcnt; /**< Number of frames before next reload of feature stationary frame */ + LL_Convacc_Afilt_Mode afilt_mode; /**< Accumulator port filter mode. See LL_Convacc_Afilt_Mode */ + unsigned char afilt_tot; /**< Total number of accumulation tensors */ + unsigned char afilt_first; /**< First accumulation tensor */ + unsigned char afilt_last; /**< Last accumulation tensor */ + unsigned char kfilt_tot; /**< Total number of kernels */ + unsigned char kfilt_first; /**< First kernel */ + unsigned char kfilt_last; /**< Last kernel */ + int fsub; /**< Feature data subtract value */ + short zfbias; /**< Bias added to zero frames */ + } LL_Convacc_InitTypeDef; + + /** @defgroup LL_CONVACC Convolutional accelerator unit configuration functions + * @{ + */ + int LL_Convacc_Init(int id, const LL_Convacc_InitTypeDef *Convacc_InitStruct); + /** + * @} + */ + + /** + * @brief Pooling Acceleration supported operations + */ + typedef enum + { + POOL_MAX = 1, + POOL_MIN, + POOL_AVG, + POOL_GMAX, + POOL_GMIN, + POOL_GAVG + } LL_Poolacc_Op; + + /** + * @brief Pooling Accelerator configuration structure + */ + typedef struct + { + LL_Poolacc_Op operation; /**< Pooling operation type. See LL_Poolacc_Op */ + unsigned avgnopad : 1; /**< Average pooling operation without padding */ + unsigned short inputX; /**< Size X of the input feature */ + unsigned short inputY; /**< Size Y of the input feature */ + unsigned short outputX; /**< Size X of the output data */ + unsigned short outputY; /**< Size Y of the output data */ + unsigned char poolWinX; /**< Size X of pooling window */ + unsigned char poolWinY; /**< Size Y of pooling window */ + unsigned char strideX; /**< Stride value in X direction */ + unsigned char strideY; /**< Stride value in Y direction */ + unsigned short topCrop; /**< Top cropping size */ + unsigned short bottomCrop; /**< Bottom cropping size */ + unsigned short leftCrop; /**< Left cropping size */ + unsigned short rightCrop; /**< Right cropping size */ + unsigned short topPad; /**< Top padding size */ + unsigned short bottomPad; /**< Bottom padding size */ + unsigned short leftPad; /**< Left padding size */ + unsigned short rightPad; /**< Right padding size */ + unsigned short batchSize; /**< Batch size */ + unsigned char shift_f; /**< Input feature data shift */ + unsigned char shift_o; /**< Optional right shift to apply the average pooling output */ + unsigned dualLine : 1; /**< Enable dual line, allows each linebuffer line to work as 2 lines, + * applicable for 8-bit data */ + unsigned nbytes : 2; /**< input data number of bytes */ + unsigned rounding_f : 1; /**< Input feature data rounding */ + unsigned saturation_f : 1; /**< Input feature data saturation */ + unsigned round_mode_f : 2; /**< Rounding mode to apply to input feature data */ + unsigned inbytes_f : 2; /**< Input data width in bytes. Valid values are 1, 2 or 3 bytes */ + unsigned outbytes_f : 2; /**< Number of output bytes to use for final result after rounding or saturation. + * Valid values are 1 or 2 bytes */ + unsigned rounding_o : 1; /**< Enable output rounding using round-to-nearest (round up) + * (applicable to average pooling operations) */ + unsigned saturation_o : 1; /**< Enable output saturation (applicable to average pooling operations) */ + unsigned round_mode_o : 1; /**< Rounding mode to apply to output feature data */ + unsigned relu_mode_o : 1; /**< Apply Relu operation before rounding */ + unsigned outbytes_o : 2; /**< Number of output bytes to use for final result after rounding or saturation. + * Valid values are 1 or 2 bytes */ + short mulval; /**< constant to be multiplied to accumulated sum of pooling window. + * For average operation, it represents the reciprocal of the divisor in 16-bit fixed point. + * The average is computed by multiplying this constant with the accumulated sum and then applying the + * relevant right shift at the output. (Applicable to average pooling operations) */ + unsigned pad_val_en : 1; /**< Enable padding value */ + short pad_val; /**< Padding value to be used for padding operation */ + } LL_Poolacc_InitTypeDef; + + /** + * @brief Epoch Controller configuration structure + */ + typedef struct + { + uint32_t blobaddr; /**< Blob code start address. Must be 8 byte aligned */ + unsigned stepmode : 1; /**< Enable step mode. Used for debugging purposes */ + } LL_EpochCtrl_InitTypeDef; + + /** @defgroup LL_POOL Pooling unit configuration functions + * @{ + */ + int LL_Poolacc_Init(int id, const LL_Poolacc_InitTypeDef *conf); + /** + * @} + */ + + /** + * @brief Streaming engine configuration structure + */ + typedef struct + { + unsigned dir : 1; /**< Stream Direction: 0 input, 1 output */ + unsigned raw : 1; /**< Set RAW mode (1) or raster mode (0) */ + unsigned raw_out : 1; /**< Force RAW output (bus to stream only) + * even if the engine is programmed in raster mode */ + unsigned continuous : 1; /**< Do not restart address pointer at end of frame */ + unsigned noblk : 1; /**< Do not use blocks wider that the native bus size */ + unsigned noinc : 1; /**< Do not increment address */ + unsigned align_right : 1; /**< Alignment for data on switch (default left) */ + unsigned mem_lsb : 1; /**< For when nbits_in != nbits_out to decide which bits are read/written + * (default msb) */ + unsigned sync_with_other : 1; /**< Enable synchronizations signals between engines */ + unsigned nbits_unsigned : 1; /**< Disable sign extension */ + unsigned bus_cid : 3; /**< Set Compartment ID cache attribute */ + unsigned cacheable : 1; /**< Set cacheable bus attribute */ + unsigned cache_allocate : 1; /**< Set cache allocate bus attribute */ + unsigned bus_pfetch : 1; /**< Enable bus prefetch */ + unsigned cache_linesize : 2; /**< Cache Line size: 0 -> 64B, 1 -> 128B, 2 -> 256B, 3 -> 512B */ + unsigned cipher_en : 1; /**< Enable ciphering: 0 -> disable, 1-> enable */ + unsigned key_sel : 1; /**< Bus Interface key to be used for ciphering (0, 1) */ + unsigned char sync_dma; /**< Synchronization signals source engine */ + ll_aton_pointer addr_base; /**< Source/Destination base address */ + unsigned offset_start; /**< Offset of the Source/Destination start address from the base address */ + unsigned offset_end; /**< Offset of the Source/Destination end address from the base address */ + unsigned offset_limit; /**< Offset of the Stream engine address limit from the base address. + * Used to prevent prefetch beyond memory boundaries */ + unsigned frame_count; /**< Number of frames to transfer */ + unsigned fwidth; /**< Frame width (pixel per line) */ + unsigned fheight; /**< Frame height (number of lines) */ + unsigned batch_depth; /**< Batch depth (subpix per pixel) */ + unsigned batch_offset; /**< Offset (bytes) between batches */ + unsigned frame_offset; /**< Offset between multiple frames within frame repetition loop */ + unsigned line_offset; /**< Offset between multiple frames within frame repetition loop. + * If set to zero it's derived from width and batch_offset */ + unsigned loop_offset; /**< Offset between frame repetition loops */ + unsigned frame_loop_cnt; /**< Number of frames to loop */ + unsigned frame_tot_cnt; /**< Frame limit */ + unsigned char nbits_in; /**< Data size in bits if reading */ + unsigned char nbits_out; /**< Data size in bits if writing */ + } LL_Streng_TensorInitTypeDef; + + static inline unsigned char *LL_Streng_addr_start(const LL_Streng_TensorInitTypeDef *conf) + { + return conf->addr_base.p + conf->offset_start; + } + + static inline unsigned char *LL_Streng_addr_end(const LL_Streng_TensorInitTypeDef *conf) + { + return conf->addr_base.p + conf->offset_end; + } + + static inline unsigned char *LL_Streng_addr_limit(const LL_Streng_TensorInitTypeDef *conf) + { + return conf->addr_base.p + conf->offset_limit; + } + + static inline uint32_t LL_Streng_len(const LL_Streng_TensorInitTypeDef *conf) + { + return conf->offset_end - conf->offset_start; + } + + /** + * @brief Streaming engine External Sync configuration structure + */ + typedef struct + { + unsigned int enable : 1; /**< Enable/disable external sync feature (0, 1) */ + unsigned int trig_source : 4; /**< Trigger source signal ID [0..3] */ + unsigned int lines; /**< Number of lines associated to each trigger rising edge */ + unsigned int lines_offset; /**< Number of lines after which the special offset will be applied */ + unsigned int offset; /**< Special line offset */ + } LL_Streng_ExtSyncTypedef; + + /** @defgroup LL_STRENG Streaming Engine configuration and operation functions + * @{ + */ + int LL_Streng_TensorInit(int id, const LL_Streng_TensorInitTypeDef *, int n); + int LL_Streng_ExtSyncInit(int id, LL_Streng_ExtSyncTypedef *); + int LL_Streng_Wait(uint32_t mask); + /** + * @} + */ + + /** @defgroup LL_BUSIF Bus Interface configuration functions + * @{ + */ + int LL_Busif_SetKeys(int id, int key, uint64_t key_low, uint64_t key_hi); + /** + * @} + */ + + enum SwitchUnitsType + { + STRSWITCH = 0, + STRSWITCH64, + STRSWITCH_VC, + }; + + extern unsigned __atonn_getSrcPortID(enum SwitchUnitsType sut, unsigned char su_num, enum AccelUnitsType aut, + unsigned char au_num, unsigned char port); + extern unsigned __atonn_getDstPortID(enum SwitchUnitsType sut, unsigned char su_num, enum AccelUnitsType aut, + unsigned char au_num, unsigned char port); + +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_EC_TRACE) + + typedef unsigned int SourcePort; +#define ATONN_SRCPORT(S, J, U, I, P) ATON_##S##_##J##_LINK_##U##_##I##_##P +// Convert SourcePort in ID needed to configure HW +#define ATONN_SRCPORT_ID(S) (S) + + typedef unsigned int DestPort; +#define ATONN_DSTPORT(S, J, U, I, P) ATON_##S##_DST_OFFSET(J, ATON_##S##_##J##_DST##U##_##I##_##P##_IDX) + +// Convert DestPort in ID needed to configure HW +#define ATONN_DSTPORT_ID(D) (D) + +#else + +typedef struct +{ + enum SwitchUnitsType s; + unsigned char s_num; + enum AccelUnitsType u; + unsigned char u_num; + unsigned char port; +} SourcePort; +#define ATONN_SRCPORT(S, J, U, I, P) \ + { \ + .s = S, .s_num = J, .u = U, .u_num = I, .port = P \ + } +static inline unsigned _atonn_getSrcPortID(SourcePort s) +{ + return __atonn_getSrcPortID(s.s, s.s_num, s.u, s.u_num, s.port); +} +#define ATONN_SRCPORT_ID(S) _atonn_getSrcPortID(S) + +typedef struct +{ + enum SwitchUnitsType s; + unsigned char s_num; + enum AccelUnitsType u; + unsigned char u_num; + unsigned char port; +} DestPort; +#define ATONN_DSTPORT(S, J, U, I, P) \ + { \ + .s = S, .s_num = J, .u = U, .u_num = I, .port = P \ + } +static inline unsigned _atonn_getDstPortID(DestPort d) +{ + return __atonn_getDstPortID(d.s, d.s_num, d.u, d.u_num, d.port); +} +#define ATONN_DSTPORT_ID(D) _atonn_getDstPortID(D) + +#endif + +/** + * @brief Stream Switch source ports identifiers + */ +#define STRENG_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, STRENG, I, P) +#define CONVACC_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, CONVACC, I, P) +#define DECUN_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, DECUN, I, P) +#define ACTIV_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, ACTIV, I, P) +#define ARITH_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, ARITH, I, P) +#define POOL_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, POOL, I, P) +#define RECBUF_SRC(I, P) ATONN_SRCPORT(STRSWITCH, 0, RECBUF, I, P) + +/** + * @brief Stream Switch destination ports identifiers + */ +#define STRENG_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, STRENG, I, P) +#define CONVACC_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, CONVACC, I, P) +#define DECUN_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, DECUN, I, P) +#define ACTIV_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, ACTIV, I, P) +#define ARITH_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, ARITH, I, P) +#define POOL_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, POOL, I, P) +#define RECBUF_DST(I, P) ATONN_DSTPORT(STRSWITCH, 0, RECBUF, I, P) + +/** + * @brief Streaming switch configuration structure + */ +#define ATON_SWITCH_CONTEXT_NUM 2 + +#if ATON_SWITCH_CONTEXT_NUM == 2 +#define LL_Switch_Init_Dest() .dest +#define LL_Switch_Init_Source(x) .source##x +#define LL_Switch_Init_Context(x) .context##x +#define LL_Switch_Init_Frames(x) .frames##x + typedef struct + { + SourcePort source0; /**< Must be one of SourcePort */ + SourcePort source1; /**< Must be one of SourcePort */ + DestPort dest; /**< Must be one of DestPort */ + unsigned char frames0; + unsigned char frames1; + unsigned context0 : 1; + unsigned context1 : 1; + } LL_Switch_InitTypeDef; +#else +#define LL_Switch_Init_Dest() .dest +#define LL_Switch_Init_Source(x) .source[x] +#define LL_Switch_Init_Context(x) .context[x] +#define LL_Switch_Init_Frames(x) .frames[x] +typedef struct +{ + SourcePort source[ATON_SWITCH_CONTEXT_NUM]; /**< Must be one of SourcePort */ + DestPort dest; /**< Must be one of DestPort */ + unsigned char context[ATON_SWITCH_CONTEXT_NUM]; + unsigned char frames[ATON_SWITCH_CONTEXT_NUM]; +} LL_Switch_InitTypeDef; +#endif + + typedef LL_Switch_InitTypeDef LL_Switch_DeinitTypeDef; + + /** + * @brief Streaming switch with virtual channels configuration structure + */ + +#define LL_SwitchVC_Init_Dest() .dest +#define LL_SwitchVC_Init_Source() .source + typedef struct + { + SourcePort source; /**< Must be one of SourcePort */ + DestPort dest; /**< Must be one of DestPort */ + } LL_SwitchVC_InitTypeDef; + + typedef LL_SwitchVC_InitTypeDef LL_SwitchVC_DeinitTypeDef; + + /** @defgroup STRSWTCH_VC Streaming Switch with virtual channels connection/disconnection functions + * @{ + */ + int LL_SwitchVC_Init_NoReset(const LL_SwitchVC_InitTypeDef *LL_SwitchVC_InitStruct, int n); + int LL_SwitchVC_Init(const LL_SwitchVC_InitTypeDef *LL_SwitchVC_InitStruct, int n); + int LL_SwitchVC_Deinit(const LL_SwitchVC_DeinitTypeDef *LL_SwitchVC_DenitStruct, int n); + int LL_SwitchVC_Deinit_Fine_Grained(const LL_SwitchVC_DeinitTypeDef *LL_SwitchVC_DenitStruct, int n); + /** + * @} + */ + + /** @defgroup STRSWTCH Streaming Switch connection/disconnection functions + * @{ + */ + int LL_Switch_Init_NoReset(const LL_Switch_InitTypeDef *LL_Switch_InitStruct, int n); + int LL_Switch_Init(const LL_Switch_InitTypeDef *LL_Switch_InitStruct, int n); + int LL_Switch_Deinit(const LL_Switch_DeinitTypeDef *LL_Switch_DenitStruct, int n); + int LL_Switch_Deinit_Fine_Grained(const LL_Switch_DeinitTypeDef *LL_Switch_DenitStruct, int n); + /** + * @} + */ + + /** + * @brief Decompression Unint configuration structure + */ + typedef struct + { + unsigned short nCVperCB; /**< Number of CodeVectors per CodeBook */ + unsigned char nCWperCV; /**< Number of CodeWords per CodeVector */ + unsigned char nRCWlastCV; /**< Number of read CodeWords from the last CodeVector */ + unsigned char nFormatBytes; /**< Number of bytes of a CodeWord */ + unsigned short nBatches; /**< Number of consecutive Batches used with a CodeBook */ + unsigned noDualInput : 1; /**< Disable the CodeBook stream link */ + unsigned noOverWrite : 1; /**< Disable CodeBooks overwriting */ + ll_aton_pointer CBs_vector; /**< Pointer to CodeBooks storage */ + unsigned CBs_size; /**< Size of CodeBooks in Memory */ + } LL_Decun_InitTypeDef; + + /** @defgroup LL_DECUN Decompression Unit configuration functions + * @{ + */ + int LL_Decun_Init(int id, const LL_Decun_InitTypeDef *LL_Decun_InitStruct); + /** + * @} + */ + + /** @defgroup LL_EPOCHCTRL Epoch controller functions + * @{ + */ + int LL_EpochCtrl_Init(int id, const LL_EpochCtrl_InitTypeDef *conf); + int LL_EpochCtrl_Step(int id); + int LL_EpochCtrl_Wait(uint32_t mask); + unsigned int LL_EpochCtrl_GetBlobSize(uint32_t *eb_addr); + /** + * @} + */ + + /** + * @brief Structure defining a unit to be activated + */ + typedef struct + { + AccelUnits unit; /**< Must be one of AccelUnits */ + // unsigned int flags; // To be implemented e.g. clear, etc. + } LL_ATON_EnableUnits_InitTypeDef; + + typedef LL_ATON_EnableUnits_InitTypeDef LL_ATON_DisableUnits_InitTypeDef; + + /** @addtogroup ATON_LL_UNITS ATON Units enabling/disabling functions + * @{ + */ + int LL_ATON_EnableUnits_Init(const LL_ATON_EnableUnits_InitTypeDef *LL_ATON_EnableUnits_InitStruct, int n); + int LL_ATON_DisableUnits_Init(const LL_ATON_DisableUnits_InitTypeDef *LL_ATON_DisableUnits_InitStruct, int n); + /** + * @} + */ + + /** @addtogroup ATON Clock Gating functions + * @{ + */ + void LL_ATON_EnableClock(unsigned int clock); + void LL_ATON_DisableClock(unsigned int clock); + /** + * @} + */ + + /** @defgroup Helper functions (use just for debug/testing purposes) + * @{ + */ + + /** + * @brief DMA version of a memcpy functionality, this function could be overloaded if a system DMA could be used + * @param dst destination memory address + * @param src source memory address + * @param src_limit memory pool end address of `src` + * @param n number of bytes to be transferred + * @param dst_cached Destination under cache flag + * @param dst_cached Source under cache flag + * @retval Error code E.g.: Invalid ID, invalid parameters, not idle,.. + * + * @note: This function completely undermines any possibility for integrating correctly + * SW operators (or any other functionality which calls this function) in any of the three ATON runtime + * scheduling modes. In other words, function `LL_ATON_Dma_memcpy()` and its usage are incompatible with the ATON + * runtime. Therefore either `memcpy()` should be used in its place or calls to `LL_ATON_Dma_memcpy()` need to be + * transformed in a sequence of "epoch blocks" which can be integrated with the ATON runtime (as an example see the + * ATON-accelerated implementation of operator `Concat`)! + */ + void *LL_ATON_Dma_memcpy(void *dst, void *src, void *src_limit, size_t n, int dst_cached, int src_cached); + + /** + * @} + */ + + /** @defgroup Watchdog management functions. Used for polling mode only + * @{ + */ + int startWatchdog(uint32_t timeout); + int checkWatchdog(void); + + /** + * @} + */ + + /** @defgroup External Trigger functions. Used to trigger external units (e.g. HSP) using an ATON interrupt lines + * @{ + */ + int LL_TriggerHigh(int irq); + int LL_TriggerLow(int irq); + /** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} + */ diff --git a/lib/stai/libstai/include/ll_aton_NN_interface.h b/lib/stai/libstai/include/ll_aton_NN_interface.h new file mode 100644 index 000000000..6999d3a70 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_NN_interface.h @@ -0,0 +1,612 @@ +/** + ****************************************************************************** + * @file ll_aton_NN_interface.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface that defines a NN generated by the AtoNN Compiler. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_NN_INTERFACE_H +#define __LL_ATON_NN_INTERFACE_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include + +#include "ll_aton_config.h" + +#include "ll_aton_attributes.h" +#include "ll_aton_util.h" + + /* this is needed to avoid some compilers (e.g. KEIL) that observe a strict semantic about conversion of + * pointers to integers in cost initializers + */ + typedef union + { + unsigned char *p; + uintptr_t i; + } __LL_address_t; + + typedef void (*EpochBlock_FuncPtr_t)(const void *epoch_block); + + typedef enum LL_ATON_RT_RetValues + { + LL_ATON_RT_NO_WFE = 0, + LL_ATON_RT_WFE, + LL_ATON_RT_DONE, + } LL_ATON_RT_RetValues_t; + + typedef enum LL_ATON_RT_Callbacktype + { + LL_ATON_RT_Callbacktype_PRE_START, /**< Callback called before start_epoch_block */ + LL_ATON_RT_Callbacktype_POST_START, /**< Callback called after start_epoch_block */ + LL_ATON_RT_Callbacktype_PRE_END, /**< Callback called before end_epoch_block */ + LL_ATON_RT_Callbacktype_POST_END, /**< Callback called after end_epoch_block */ + LL_ATON_RT_Callbacktype_NN_Init, /**< Callback called after `LL_ATON_RT_Init_Network`, + * NOTE: 3rd parameter passed is `NULL` */ + LL_ATON_RT_Callbacktype_NN_DeInit, /**< Callback called after `LL_ATON_RT_DeInit_Network`, + * NOTE: 3rd parameter passed is `NULL` */ + LL_ATON_RT_Callbacktype_RT_Init, /**< Callback called after `LL_ATON_RT_RuntimeInit` */ + LL_ATON_RT_Callbacktype_RT_Deinit, /**< Callback called before `LL_ATON_RT_RuntimeDeInit` */ + } LL_ATON_RT_Callbacktype_t; + + typedef enum LL_ATON_User_IO_Result + { + LL_ATON_User_IO_NOERROR, /**< */ + LL_ATON_User_IO_WRONG_ALIGN, /**< */ + LL_ATON_User_IO_WRONG_SIZE, /**< */ + LL_ATON_User_IO_WRONG_INDEX, /**< */ + } LL_ATON_User_IO_Result_t; + + typedef enum + { + EpochBlock_Flags_NONE = 0x0, /**< */ + EpochBlock_Flags_epoch_start = (0x1 << 0), /**< First EpochBlock of an Epoch */ + EpochBlock_Flags_epoch_end = (0x1 << 1), /**< Last EpochBlock of an Epoch */ + EpochBlock_Flags_blob = (0x1 << 2), /**< Item is an Epoch Blob */ + EpochBlock_Flags_last_eb = (0x1 << 3), /**< Last EpochBlock */ + EpochBlock_Flags_pure_hw = (0x1 << 4), /**< Pure HW EpochBlock */ + EpochBlock_Flags_pure_sw = (0x1 << 5), /**< Pure SW EpochBlock */ + EpochBlock_Flags_hybrid = (0x1 << 6), /**< Hybrid EpochBlock (i.e. mixed HW/SW) */ + EpochBlock_Flags_internal = (0x1 << 7), /**< ATON lib internal EpochBlock (used to implement hybrid epochs) */ + } EpochBlock_Flags_t; + + typedef struct + { + EpochBlock_FuncPtr_t start_epoch_block; /**< Method to execute the EpochBlock */ + EpochBlock_FuncPtr_t end_epoch_block; /**< Method to be executed when the EpochBlock ends */ + uintptr_t blob_address; /**< Blob address (in case this EpochBlock represents an epoch blob) */ + uint32_t wait_mask; /**< Mask needed to check when an EpochBlock ends + * - if epoch blob: number (not bitmask) of epoch controller unit to use + * - otherwise: bitmask with all output streaming engines to wait for before ending epoch */ + uint16_t flags; /**< EpochBlock flags */ +#ifdef LL_ATON_EB_DBG_INFO + int16_t epoch_num; /**< Epoch number / First epoch number within blob */ + int16_t last_epoch_num; /**< Epoch number / Last epoch number within blob */ + uint32_t in_streng_mask; /**< Debug information about input streaming engines used in epoch */ + uint32_t out_streng_mask; /**< Debug information about output streaming engines used in epoch */ + uint64_t estimated_npu_cycles; /**< Debug information estimates for NPU cycles in epoch w/o memory penalty */ + uint64_t estimated_tot_cycles; /**< Debug information estimates for NPU cycles in epoch w/ memory penalty */ +#endif // LL_ATON_EB_DBG_INFO + } EpochBlock_ItemTypeDef; + + /** + * @brief Checks if the pointed element is the last one of an array of `const EpochBlock_ItemTypeDef` + * + */ + static inline bool EpochBlock_IsLastEpochBlock(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is the first EpochBlock of an Epoch + * + */ + static inline bool EpochBlock_IsEpochStart(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is the last EpochBlock of an Epoch + * + */ + static inline bool EpochBlock_IsEpochEnd(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is the an Epoch Blob + * + */ + static inline bool EpochBlock_IsEpochBlob(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is pure SW epoch + * + */ + static inline bool EpochBlock_IsEpochPureSW(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is a pure HW or mixed SW/HW epoch + * + */ + static inline bool EpochBlock_IsEpochPureHW(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is a hybrid epoch + * + */ + static inline bool EpochBlock_IsEpochHybrid(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Checks if the pointed element is an internal epoch + * + */ + static inline bool EpochBlock_IsEpochInternal(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Returns the Epoch controller id to use + * + */ + static inline uint32_t EpochBlock_EpochControllerUnit(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief Returns the address of the configuration of the epoch controller (the blob address) + * + */ + static inline uintptr_t EpochBlock_EpochBlobAddr(const EpochBlock_ItemTypeDef *eb); + + /** + * @brief ATON buffer types definition + */ + + typedef enum + { + DataType_UNDEFINED = 0, + DataType_FLOAT = 1, + DataType_UINT8 = 2, + DataType_INT8 = 3, + DataType_UINT16 = 4, + DataType_INT16 = 5, + DataType_INT32 = 6, + DataType_INT64 = 7, + DataType_STRING = 8, + DataType_BOOL = 9, + DataType_FLOAT16 = 10, + DataType_DOUBLE = 11, + DataType_UINT32 = 12, + DataType_UINT64 = 13, + DataType_COMPLEX64 = 14, + DataType_COMPLEX128 = 15, + DataType_BFLOAT16 = 16, + DataType_FXP = 100 // AtoNN specific + } Buffer_DataType_TypeDef; + + /** + * @brief ATON buffer Channel position + */ + + typedef enum + { + CHPos_UNDEFINED = 0, /**< No channel present */ + CHPos_First = 1, /**< Channel First ( ...B C H W )*/ + CHPos_Last = 2, /**< Channel Last ( ...B H W C ) */ + CHPos_Mixed = 3, /**< Channel with Batch(b) ( ...B C/b H W b ) */ + } Buffer_CHPos_TypeDef; + + /** + * @brief ATON buffer definition + */ + typedef struct + { + const char *name; /**< Buffer name. NULL if end of list */ + __LL_address_t addr_base; /**< Buffer base address */ + uint32_t offset_start; /**< Offset of the buffer start address from the base address */ + uint32_t offset_end; /**< Offset of the buffer end address from the base address + * (first bytes address beyond buffer length) */ + uint32_t offset_limit; /**< Offset of the limiter address from the base address, + * (needed for configuring streaming engines) */ + uint8_t is_user_allocated; /**< */ + uint8_t is_param; /**< */ + uint16_t epoch; /**< */ + uint32_t batch; /**< */ + const uint32_t *mem_shape; /**< shape as seen by the user in memory (only valid for input/output buffers) */ + uint16_t mem_ndims; /**< Number of dimensions of mem_shape (Length of mem_shape) */ + Buffer_CHPos_TypeDef chpos; /**< Position of channels dimension in mem shape */ + Buffer_DataType_TypeDef type; /**< */ + int8_t Qm; /**< */ + int8_t Qn; /**< */ + uint8_t Qunsigned; /**< */ + uint8_t ndims; /**< */ + uint8_t nbits; /**< */ + uint8_t per_channel; /**< */ + const uint32_t *shape; /**< */ + const float *scale; /**< */ + const int16_t *offset; /**< This can become int8 or uint8 based on the Qunsigned field. + * (This field Must have the same format of the quantized value) */ + } LL_Buffer_InfoTypeDef; + + /** + * @brief returns the base address of the mem pool the buffer is allocated in + * + */ + static inline unsigned char *LL_Buffer_addr_base(const LL_Buffer_InfoTypeDef *buf); + + /** + * @brief returns the start address of the buffer + * + */ + static inline unsigned char *LL_Buffer_addr_start(const LL_Buffer_InfoTypeDef *buf); + + /** + * @brief returns the end address of the buffer + * + */ + static inline unsigned char *LL_Buffer_addr_end(const LL_Buffer_InfoTypeDef *buf); + + /** + * @brief returns the limit address of the buffer + * + */ + static inline unsigned char *LL_Buffer_addr_limit(const LL_Buffer_InfoTypeDef *buf); + + /** + * @brief returns the length of the buffer + * + */ + static inline uint32_t LL_Buffer_len(const LL_Buffer_InfoTypeDef *buf); + + /** + * @brief returns the buffer elements number of bits + * + */ + static inline uint32_t LL_Buffer_bits(const LL_Buffer_InfoTypeDef *buf); + + /** @defgroup ATONN_COMPILER Functions autogenerated by the AtoNN compiler + * @{ + */ + + /** + * @brief Initialize a Network internal structures for the Epoch Controller + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @retval returns if the action succeded or an error occured + */ + extern bool LL_ATON_EC_Network_Init_Default(void); + + /** + * @brief Update a Network internal structures for the Epoch Controller before the execution of an Inference + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @retval returns if the action succeded or an error occured + */ + extern bool LL_ATON_EC_Inference_Init_Default(void); + + /** + * @brief Sets user allocated inputs (one at a time) + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @param num zero base index of the input buffer to set + * @param buffer pointer to the area used to store this input + * @param size size of the memory reserved for this input + */ + extern LL_ATON_User_IO_Result_t LL_ATON_Set_User_Input_Buffer_Default(uint32_t num, void *buffer, uint32_t size); + + /** + * @brief Gets user allocated inputs (one at a time) + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @param num zero base index of the input buffer to get + * @retval returns a pointer to the specified user allocated input + */ + extern void *LL_ATON_Get_User_Input_Buffer_Default(uint32_t num); + + /** + * @brief Sets user allocated outputs (one at a time) + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @param num zero base index of the output buffer to set + * @param buffer pointer to the area used to store this output + * @param size size of the memory reserved for this output + */ + extern LL_ATON_User_IO_Result_t LL_ATON_Set_User_Output_Buffer_Default(uint32_t num, void *buffer, uint32_t size); + + /** + * @brief Gets user allocated inputs (one at a time) + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @param num zero base index of the output buffer to get + * @retval returns a pointer to the specified user allocated output + */ + extern void *LL_ATON_Get_User_Output_Buffer_Default(uint32_t num); + + /** + * @brief Returns an array of structures describing the epoch blocks of the NN to execute + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @retval returns a pointer to an array of `const EpochBlock_ItemTypeDef`, + * if `flags` contain `EpochBlock_Flags_last_eb` identifies the last (empty) EpochBlock (i.e. we are done) + * (see helper function `EpochBlock_IsLastEpochBlock()`) + */ + extern const EpochBlock_ItemTypeDef *LL_ATON_EpochBlockItems_Default(void); + + /** + * @brief Returns an array of structures describing input buffers + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @retval returns a pointer to the array of LL_Buffer_InfoTypeDef, name is NULL for the last one + */ + extern const LL_Buffer_InfoTypeDef *LL_ATON_Output_Buffers_Info_Default(void); + + /** + * @brief Returns an array of structures describing output buffers + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @retval Returns a pointer to the array of LL_Buffer_InfoTypeDef, name is NULL for the last one + */ + extern const LL_Buffer_InfoTypeDef *LL_ATON_Input_Buffers_Info_Default(void); + + /** + * @brief Returns an array of structures describing epoch output transient buffers + * @note This function is generated by the AtoNN compiler when called without a network name + * (i.e. without option `--network-name`) + * @note Use macro `LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name)` instead when the network has been generated + * (by the AtoNN compiler) with a network name (i.e. with option `--network-name`) + * @retval Returns a pointer to the array of LL_Buffer_InfoTypeDef, name is NULL for the last one + */ + extern const LL_Buffer_InfoTypeDef *LL_ATON_Internal_Buffers_Info_Default(void); + +/** + * @brief Declare the function prototypes for named NN interface functions generated by the AtoNN compiler + * @param network_name name of the network as provided by option `--network-name` + */ +#define LL_ATON_DECLARE_NAMED_NN_PROTOS(network_name) \ + extern bool LL_ATON_EC_Network_Init_##network_name(void); \ + extern bool LL_ATON_EC_Inference_Init_##network_name(void); \ + extern LL_ATON_User_IO_Result_t LL_ATON_Set_User_Input_Buffer_##network_name(uint32_t num, void *buffer, \ + uint32_t size); \ + extern void *LL_ATON_Get_User_Input_Buffer_##network_name(uint32_t num); \ + extern LL_ATON_User_IO_Result_t LL_ATON_Set_User_Output_Buffer_##network_name(uint32_t num, void *buffer, \ + uint32_t size); \ + extern void *LL_ATON_Get_User_Output_Buffer_##network_name(uint32_t num); \ + extern const EpochBlock_ItemTypeDef *LL_ATON_EpochBlockItems_##network_name(void); \ + extern const LL_Buffer_InfoTypeDef *LL_ATON_Output_Buffers_Info_##network_name(void); \ + extern const LL_Buffer_InfoTypeDef *LL_ATON_Input_Buffers_Info_##network_name(void); \ + extern const LL_Buffer_InfoTypeDef *LL_ATON_Internal_Buffers_Info_##network_name(void); + + /** + * @brief Type definitions for NN interface functions + */ + typedef bool (*NN_EC_Hook_TypeDef)(void); + typedef LL_ATON_User_IO_Result_t (*NN_InputSetter_TypeDef)(uint32_t num, void *buffer, uint32_t size); + typedef void *(*NN_InputGetter_TypeDef)(uint32_t num); + typedef LL_ATON_User_IO_Result_t (*NN_OutputSetter_TypeDef)(uint32_t num, void *buffer, uint32_t size); + typedef void *(*NN_OutputGetter_TypeDef)(uint32_t num); + typedef const EpochBlock_ItemTypeDef *(*NN_EpochBlockItems_TypeDef)(void); + typedef const LL_Buffer_InfoTypeDef *(*NN_Buffers_Info_TypeDef)(void); + + typedef void (*TraceRuntime_FuncPtr_t)(LL_ATON_RT_Callbacktype_t ctype); + + struct __nn_instance_struct; // forward declaration + typedef struct __nn_instance_struct NN_Instance_TypeDef; + typedef void (*TraceEpochBlock_FuncPtr_t)(LL_ATON_RT_Callbacktype_t ctype, const NN_Instance_TypeDef *nn_instance, + const EpochBlock_ItemTypeDef *epoch_block); + + typedef struct + { + const char *network_name; + NN_EC_Hook_TypeDef ec_network_init; + NN_EC_Hook_TypeDef ec_inference_init; + NN_InputSetter_TypeDef input_setter; + NN_InputGetter_TypeDef input_getter; + NN_OutputSetter_TypeDef output_setter; + NN_OutputGetter_TypeDef output_getter; + NN_EpochBlockItems_TypeDef epoch_block_items; + NN_Buffers_Info_TypeDef output_buffers_info; + NN_Buffers_Info_TypeDef input_buffers_info; + NN_Buffers_Info_TypeDef internal_buffers_info; + } NN_Interface_TypeDef; + + typedef struct + { + const EpochBlock_ItemTypeDef *volatile current_epoch_block; // pointer to current epoch block + const EpochBlock_ItemTypeDef *volatile first_epoch_block; // pointer to first epoch block in current epoch list + const EpochBlock_ItemTypeDef *volatile next_epoch_block; // pointer to epoch block to be inserted + + const EpochBlock_ItemTypeDef *volatile saved_current_epoch_block; // pointer to saved current epoch list + const EpochBlock_ItemTypeDef + *volatile saved_first_epoch_block; // pointer to saved first epoch block in current epoch list + + bool inference_started; // inference has been started + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + volatile uint32_t triggered_events; // currently triggered events/IRQs in current epoch + volatile bool current_epoch_block_started; // has current epoch block already been started +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + +#ifndef NDEBUG + volatile uint32_t + nr_of_epoch_blocks; // number of epoch blocks in network (includes also terminating empty epoch block) + volatile uint32_t saved_nr_of_epoch_blocks; // number of epoch blocks in saved network (includes also terminating + // empty epoch block) +#endif // NDEBUG + + TraceEpochBlock_FuncPtr_t epoch_callback_function; // epoch callback function + +#if defined(LL_ATON_RT_RELOC) + uint32_t inst_reloc; +#endif + + } NN_Execution_State_TypeDef; + + struct __nn_instance_struct + { + const NN_Interface_TypeDef *network; + NN_Execution_State_TypeDef exec_state; + }; + +/** + * @brief Declare and fill a constant named NN interface object + * @param nn_if_name name of the network as provided by option `--network-name` + */ +#define LL_ATON_DECLARE_NAMED_NN_INTERFACE(nn_if_name) \ + LL_ATON_DECLARE_NAMED_NN_PROTOS(nn_if_name); \ + \ + static const NN_Interface_TypeDef NN_Interface_##nn_if_name = { \ + .network_name = #nn_if_name, \ + .ec_network_init = &LL_ATON_EC_Network_Init_##nn_if_name, \ + .ec_inference_init = &LL_ATON_EC_Inference_Init_##nn_if_name, \ + .input_setter = &LL_ATON_Set_User_Input_Buffer_##nn_if_name, \ + .input_getter = &LL_ATON_Get_User_Input_Buffer_##nn_if_name, \ + .output_setter = &LL_ATON_Set_User_Output_Buffer_##nn_if_name, \ + .output_getter = &LL_ATON_Get_User_Output_Buffer_##nn_if_name, \ + .epoch_block_items = &LL_ATON_EpochBlockItems_##nn_if_name, \ + .output_buffers_info = &LL_ATON_Output_Buffers_Info_##nn_if_name, \ + .input_buffers_info = &LL_ATON_Input_Buffers_Info_##nn_if_name, \ + .internal_buffers_info = &LL_ATON_Internal_Buffers_Info_##nn_if_name} + +/** + * @brief Declare and fill a non-constant named NN execution instance + * @param nn_exec_name typically name of the network as provided by option `--network-name` + * @param _nn_if_name pointer to network interface + */ +#define LL_ATON_DECLARE_NAMED_NN_INSTANCE(nn_exec_name, _nn_if_name) \ + static NN_Instance_TypeDef NN_Instance_##nn_exec_name = {.network = _nn_if_name, .exec_state = {0}} + +/** + * @brief Declare and fill a non-constant named NN execution instance and constant network interface, + * which get linked together (by this macro). + * @param nn_name name of the network as provided by option `--network-name` + */ +#define LL_ATON_DECLARE_NAMED_NN_INSTANCE_AND_INTERFACE(nn_name) \ + LL_ATON_DECLARE_NAMED_NN_INTERFACE(nn_name); \ + LL_ATON_DECLARE_NAMED_NN_INSTANCE(nn_name, &NN_Interface_##nn_name); + + /** + * @} + */ + + static inline bool EpochBlock_IsLastEpochBlock(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_last_eb) != 0); + } + + static inline bool EpochBlock_IsEpochStart(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_epoch_start) != 0); + } + + static inline bool EpochBlock_IsEpochEnd(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_epoch_end) != 0); + } + + static inline bool EpochBlock_IsEpochBlob(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_blob) != 0); + } + + static inline bool EpochBlock_IsEpochPureSW(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_pure_sw) != 0); + } + + static inline bool EpochBlock_IsEpochPureHW(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_pure_hw) != 0); + } + + static inline bool EpochBlock_IsEpochHybrid(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_hybrid) != 0); + } + + static inline bool EpochBlock_IsEpochInternal(const EpochBlock_ItemTypeDef *eb) + { + return ((eb->flags & EpochBlock_Flags_internal) != 0); + } + + static inline uint32_t EpochBlock_EpochControllerUnit(const EpochBlock_ItemTypeDef *eb) + { + LL_ATON_ASSERT(EpochBlock_IsEpochBlob(eb)); + return eb->wait_mask; + } + + static inline uintptr_t EpochBlock_EpochBlobAddr(const EpochBlock_ItemTypeDef *eb) + { + LL_ATON_ASSERT(EpochBlock_IsEpochBlob(eb)); + return eb->blob_address; + } + + static inline unsigned char *LL_Buffer_addr_base(const LL_Buffer_InfoTypeDef *buf) + { + if (buf->is_user_allocated) + { + unsigned char **tmp = (unsigned char **)buf->addr_base.p; + return *tmp; + } + return buf->addr_base.p; + } + + static inline unsigned char *LL_Buffer_addr_start(const LL_Buffer_InfoTypeDef *buf) + { + return LL_Buffer_addr_base(buf) + buf->offset_start; + } + + static inline unsigned char *LL_Buffer_addr_end(const LL_Buffer_InfoTypeDef *buf) + { + return LL_Buffer_addr_base(buf) + buf->offset_end; + } + + static inline unsigned char *LL_Buffer_addr_limit(const LL_Buffer_InfoTypeDef *buf) + { + return LL_Buffer_addr_base(buf) + buf->offset_limit; + } + + static inline uint32_t LL_Buffer_len(const LL_Buffer_InfoTypeDef *buf) + { + return buf->offset_end - buf->offset_start; + } + + static inline uint32_t LL_Buffer_bits(const LL_Buffer_InfoTypeDef *buf) + { + return buf->Qm + buf->Qn + (buf->Qunsigned ? 0 : 1); + } + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} + */ diff --git a/lib/stai/libstai/include/ll_aton_attributes.h b/lib/stai/libstai/include/ll_aton_attributes.h new file mode 100644 index 000000000..af2963edf --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_attributes.h @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file ll_aton_attributes.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON library attributes handling. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_ATTRIBUTES_H +#define __LL_ATON_ATTRIBUTES_H + +/* + * Exported attributes handling: + * LL_ATON_API_ENTRY + * LL_ATON_ALIGNED(x) + * LL_ATON_LIB_UNUSED(x) + * LL_ATON_CONCAT(a, b) + * LL_ATON_CONCAT3(a, b, c) + * LL_ATON_WEAK + * + */ + +/* Exported attributes handling */ + +#if defined(__clang__) +#undef __weak +#define __weak __attribute__((weak)) +#endif +#if defined(__GNUC__) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#endif /* __GNUC__ */ +#define LL_ATON_WEAK __weak + +#define LL_ATON_LIB_UNUSED(x) ((void)(x)) // prevent from eventual compiler warnings due to unused variables + +#define __LL_ATON_CONCAT_ARG(a, b) a##b +#define LL_ATON_CONCAT(a, b) __LL_ATON_CONCAT_ARG(a, b) +#define LL_ATON_CONCAT3(a, b, c) LL_ATON_CONCAT(a, LL_ATON_CONCAT(b, c)) + +/* Alignment macros borrowed from ST.AI (file `stai.h`) */ +#if defined(_MSC_VER) +#define LL_ATON_API_ENTRY __declspec(dllexport) +#define LL_ATON_ALIGNED(x) __declspec(align(x)) +#elif defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__) +#define LL_ATON_API_ENTRY /* LL_ATON_API_ENTRY */ +#define LL_ATON_ALIGNED(x) LL_ATON_CONCAT(LL_ATON_ALIGNED_, x) +#define LL_ATON_ALIGNED_1 _Pragma("data_alignment = 1") +#define LL_ATON_ALIGNED_2 _Pragma("data_alignment = 2") +#define LL_ATON_ALIGNED_4 _Pragma("data_alignment = 4") +#define LL_ATON_ALIGNED_8 _Pragma("data_alignment = 8") +#define LL_ATON_ALIGNED_16 _Pragma("data_alignment = 16") +#define LL_ATON_ALIGNED_32 _Pragma("data_alignment = 32") +#define LL_ATON_ALIGNED_64 _Pragma("data_alignment = 64") +#elif defined(__CC_ARM) +#define LL_ATON_API_ENTRY __attribute__((visibility("default"))) +#define LL_ATON_ALIGNED(x) __attribute__((aligned(x))) +/* Keil disallows anonymous union initialization by default */ +#pragma anon_unions +#elif defined(__GNUC__) +// #define LL_ATON_API_ENTRY __attribute__((visibility("default"))) +#define LL_ATON_API_ENTRY /* LL_ATON_API_ENTRY */ +#define LL_ATON_ALIGNED(x) __attribute__((aligned(x))) +#else +/* Dynamic libraries are not supported by the compiler */ +#define LL_ATON_API_ENTRY /* LL_ATON_API_ENTRY */ +#define LL_ATON_ALIGNED(x) /* LL_ATON_ALIGNED(x) */ +#endif + +#endif diff --git a/lib/stai/libstai/include/ll_aton_caches_interface.h b/lib/stai/libstai/include/ll_aton_caches_interface.h new file mode 100644 index 000000000..d0064334a --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_caches_interface.h @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file ll_aton_caches_interface.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file for defining an implementing generic cache handling + * functions for the application writer + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_CACHES_H +#define __LL_ATON_CACHES_H + +#include + +#include "ll_aton_osal.h" +#include "ll_aton_platform.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_STM32N6) + + /* + * Note: For relocatable mode, the fcts are implemented in the ll_aton_reloc_callbacks.c. + * Only the declaration is requested here, to avoid to inline them the relocatable binary model. + */ + +/*** MCU cache maintenance functions ***/ + +/** + * @brief perform MCU cache clean maintenance operation on an address range + * @details whenever the content of a buffer is changed by the application (which is especially the case for input + * buffers) cache maintenance MUST be taken into account before being able to run the network. + * @param[in] virtual_addr start address (host-side/virtual) of address range + * @param[in] size size of address range + * + * @note the address range should fulfill alignment constraints with respect to the MCU cache line size + * for both its `address` & `size` (to better correspond to what this operation will actually do)! + * @note this function is intended to handle the case where a buffer has been filled by the MCU/processor (such + * passing thru the MCU cache) and should be called AFTER that the buffer has been filled + */ +#if defined(LL_ATON_RT_RELOC) && defined(BUILD_AI_NETWORK_RELOC) + void LL_ATON_Cache_MCU_Clean_Range(uintptr_t virtual_addr, uint32_t size); +#else + static inline void LL_ATON_Cache_MCU_Clean_Range(uintptr_t virtual_addr, uint32_t size) + { + LL_ATON_OSAL_LOCK_MCU_CACHE(); + mcu_cache_clean_range(virtual_addr, virtual_addr + size); + LL_ATON_OSAL_UNLOCK_MCU_CACHE(); + } +#endif + +/** + * @brief perform MCU cache invalidate maintenance operation on an address range + * @details whenever the content of a buffer is changed by the application (which is especially the case for input + * buffers) cache maintenance MUST be taken into account before being able to run the network. + * @param[in] virtual_addr start address (host-side/virtual) of address range + * @param[in] size size of address range + * + * @note the address range should fulfill alignment constraints with respect to the MCU cache line size + * for both its `address` & `size` (to better correspond to what this operation will actually do)! + * @note this function is intended to handle the case where a buffer has been filled by-passing the MCU/processor + * cache (e.g. using a DMA) and should be called BEFORE the buffer gets filled + */ +#if defined(LL_ATON_RT_RELOC) && defined(BUILD_AI_NETWORK_RELOC) + void LL_ATON_Cache_MCU_Invalidate_Range(uintptr_t virtual_addr, uint32_t size); +#else + static inline void LL_ATON_Cache_MCU_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) + { + LL_ATON_OSAL_LOCK_MCU_CACHE(); + mcu_cache_invalidate_range(virtual_addr, virtual_addr + size); + LL_ATON_OSAL_UNLOCK_MCU_CACHE(); + } +#endif + +/** + * @brief perform MCU cache clean & invalidate maintenance operation on an address range + * @details whenever the content of a buffer is changed by the application (which is especially the case for input + * buffers) cache maintenance MUST be taken into account before being able to run the network. + * @param[in] virtual_addr start address (host-side/virtual) of address range + * @param[in] size size of address range + * + * @note the address range should fulfill alignment constraints with respect to the MCU cache line size + * for both its `address` & `size` (to better correspond to what this operation will actually do)! + * @note this function is intended to handle the case where a buffer has been filled by the MCU/processor + * (such passing thru the MCU cache) and is gonna to be modified immediately afterwards by-passing + * the MCU/processor cache (e.g. using a DMA). It should be called AFTER that the buffer has been + * filled + */ +#if defined(LL_ATON_RT_RELOC) && defined(BUILD_AI_NETWORK_RELOC) + void LL_ATON_Cache_MCU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size); +#else + static inline void LL_ATON_Cache_MCU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) + { + LL_ATON_OSAL_LOCK_MCU_CACHE(); + mcu_cache_clean_invalidate_range(virtual_addr, virtual_addr + size); + LL_ATON_OSAL_UNLOCK_MCU_CACHE(); + } +#endif + +/*** NPU cache maintainence functions ***/ + +/** + * @brief perform NPU cache clean maintenance operation on an address range + * @details whenever the content of a buffer is changed by the application (which is especially the case for input + * buffers) cache maintenance MUST be taken into account before being able to run the network. + * @param[in] address start address (host-side/virtual) of address range + * @param[in] size size of address range + * + * @note this cache maintainence function needs only be called for buffers which are NPU cacheable + * @note the address range should fulfill alignment constraints with respect to the NPU cache line size + * for both its `address` & `size` (to better correspond to what this operation will actually do)! + * @note this function is intended to handle the case where a buffer has been filled passing thru the NPU cache + * and should be called AFTER that the buffer has been filled + */ +#if defined(LL_ATON_RT_RELOC) && defined(BUILD_AI_NETWORK_RELOC) + void LL_ATON_Cache_NPU_Clean_Range(uintptr_t virtual_addr, uint32_t size); +#else + static inline void LL_ATON_Cache_NPU_Clean_Range(uintptr_t virtual_addr, uint32_t size) + { + LL_ATON_OSAL_LOCK_NPU_CACHE(); + npu_cache_clean_range(ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(virtual_addr), + ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(virtual_addr + size)); + LL_ATON_OSAL_UNLOCK_NPU_CACHE(); + } +#endif + +/** + * @brief perform NPU cache clean & invalidate maintenance operation on an address range + * @details whenever the content of a buffer is changed by the application (which is especially the case for input + * buffers) cache maintenance MUST be taken into account before being able to run the network. + * @param[in] address start address (host-side/virtual) of address range + * @param[in] size size of address range + * + * @note this cache maintainence function needs only be called for buffers which are NPU cacheable + * @note the address range should fulfill alignment constraints with respect to the NPU cache line size + * for both its `address` & `size` (to better correspond to what this operation will actually do)! + * @note this function is intended to handle the case where a buffer is NPU cacheable and has been filled by-passing + * the NPU cache and should be called BEFORE the buffer gets filled + * @note the NPU cache provides only a "clean & invalidate range" (and not a - pure - "invalidate range") cache + * maintenance function which will be called by "stai_ext_cache_npu_clean_invalidate_range()", therefore it is + * even more important to call it BEFORE the buffer gets filled + */ +#if defined(LL_ATON_RT_RELOC) && defined(BUILD_AI_NETWORK_RELOC) + void LL_ATON_Cache_NPU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size); +#else + static inline void LL_ATON_Cache_NPU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) + { + /* NOTE: The ATON NPU cache does not provide a pure invalidate-range function, but only a clean-invalidate range + function! One has to take this into account when using `stai_ext_cache_npu_clean_invalidate_range`. */ + LL_ATON_OSAL_LOCK_NPU_CACHE(); + npu_cache_clean_invalidate_range(ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(virtual_addr), + ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(virtual_addr + size)); + LL_ATON_OSAL_UNLOCK_NPU_CACHE(); + } +#endif + +/** + * @brief perform NPU cache invalidate maintenance operation. + * @details The whole NPU cache is invalidated. + */ +#if defined(LL_ATON_RT_RELOC) && defined(BUILD_AI_NETWORK_RELOC) + void LL_ATON_Cache_NPU_Invalidate(void); +#else + static inline void LL_ATON_Cache_NPU_Invalidate(void) + { + LL_ATON_OSAL_LOCK_NPU_CACHE(); + npu_cache_invalidate(); + LL_ATON_OSAL_UNLOCK_NPU_CACHE(); + } +#endif + +#else // (LL_ATON_PLATFORM != LL_ATON_PLAT_STM32N6) +/* MCU */ +static inline void LL_ATON_Cache_MCU_Clean_Range(uintptr_t virtual_addr, uint32_t size) +{ +} +static inline void LL_ATON_Cache_MCU_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ +} +static inline void LL_ATON_Cache_MCU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ +} + +/* NPU */ +static inline void LL_ATON_Cache_NPU_Clean_Range(uintptr_t virtual_addr, uint32_t size) +{ +} +static inline void LL_ATON_Cache_NPU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ +} +#endif // (LL_ATON_PLATFORM != LL_ATON_PLAT_STM32N6) + +#ifdef __cplusplus +} +#endif + +#endif // __LL_ATON_CACHES_H diff --git a/lib/stai/libstai/include/ll_aton_cipher.h b/lib/stai/libstai/include/ll_aton_cipher.h new file mode 100644 index 000000000..4543447ef --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_cipher.h @@ -0,0 +1,89 @@ +/** + ****************************************************************************** + * @file ll_aton_cipher.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_CIPHER_H +#define __LL_ATON_CIPHER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + + /** + * @brief Encryption configuration structure for Streaming Engines and Epoch Controller units + */ + typedef struct + { + unsigned int enable; /**< Enable/disable encryption (0, 1) */ + uint64_t encryption_id; /**< 43 bit Encryption ID */ + unsigned int rounds; /**< Number of encryption rounds: 0->12 rounds, 1->9 rounds */ + unsigned int key_sel; /**< Bus Interface encryption key selection (0, 1) */ + unsigned int increment; /**< Encryption ID increment rate: 0 -> no increment, -> +1 every n frames */ + } LL_Streng_EncryptionTypedef; + + typedef enum + { + CYPHER_CACHE_NONE = 0, + CYPHER_CACHE_SRC, + CYPHER_CACHE_DST, + } CypherCacheSourceMask; + + typedef enum + { + CYPHER_DISABLE_MASK = 0, + CYPHER_SRC_MASK, + CYPHER_DST_MASK, + } CypherEnableMask; + + /** + * @brief Cyphering configuration structure for DmaCypher function + */ + + typedef struct + { + uint32_t srcAdd; /**< Transfer source address */ + uint32_t dstAdd; /**< Transfer destination address */ + uint32_t len; /**< Transfer size */ + CypherCacheSourceMask cypherCacheMask; /**< Cache usage mask: + * 0-no cache + * 1-cache source + * 2-cache destination */ + CypherEnableMask cypherEnableMask; /**< Cyphering channel mask: + * 0-no cypher + * 1-cypher source + * 2-cypher destination */ + uint64_t busIfKeyLsb; /**< Bus interface LSB Key */ + uint64_t busIfKeyMsb; /**< Bus interface MSB Key */ + } LL_Cypher_InitTypeDef; + +#define CYPHER_SRC_STRENG_ID 0 /**< Stream engine used for source data in Dma/Cypher function */ +#define CYPHER_DST_STRENG_ID 1 /**< Stream engine used for destination data in Dma/Cypher function */ +#define CYPHER_CACHE_SIZE 0x40000 /**< N6 cache size */ + + int LL_Streng_EncryptionInit(int id, LL_Streng_EncryptionTypedef *); + int LL_Streng_WeightEncryptionInit(int id); + int LL_EpochCtrl_EncryptionInit(int id, LL_Streng_EncryptionTypedef *conf); + int LL_DmaCypherInit(LL_Cypher_InitTypeDef *cypherInfo); + +#ifdef __cplusplus +} +#endif + +#endif //__LL_ATON_CIPHER_H diff --git a/lib/stai/libstai/include/ll_aton_config.h b/lib/stai/libstai/include/ll_aton_config.h new file mode 100644 index 000000000..a7da3e309 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_config.h @@ -0,0 +1,181 @@ +/** + ****************************************************************************** + * @file ll_aton_config.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON runtime/library configuration. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_CONFIG_H +#define __LL_ATON_CONFIG_H + +/* STEdgeAI runtime build info bit-field sizes (may not be modified) */ +#define LL_ATON_CONFIG_PLAT_BSIZE 8 +#define LL_ATON_CONFIG_OSAL_BSIZE 8 +#define LL_ATON_CONFIG_RT_MODE_BSIZE 4 +#define LL_ATON_CONFIG_BINFO_BSIZE 4 +#define LL_ATON_CONFIG_CLKG_BSIZE 4 +#define LL_ATON_CONFIG_SWF_BSIZE 1 +#define LL_ATON_CONFIG_DD_BSIZE 1 +#define LL_ATON_CONFIG_EBDBG_BSIZE 1 + +/* + * Configuration defines: + * mandatory LL_ATON_PLATFORM + * mandatory LL_ATON_OSAL + * optional LL_ATON_RT_MODE + * optional LL_ATON_SW_FALLBACK enable support for SW inference library integration + * optional LL_ATON_DUMP_DEBUG_API enable buffer dumping functions (for debug purposes only) + * optional LL_ATON_EB_DBG_INFO enable compilation of epoch block debug information + * optional LL_ATON_DBG_BUFFER_INFO_EXCLUDED exclude debug info from buffer info arrays + * (to be defined as `0` or `1`) + * optional LL_ATON_ENABLE_CLOCK_GATING used to enable/disable clock gating of the ATON units not involved + * during epoch execution (to be defined as `0` or `1`) + * + * NOTE: `mandatory` means that these macros must be predefined using `-D` options in the command-line of the + * C compiler a/o preprocessor! + * + * NOTE: the beyond macros MUST be set to the same values when compiling the different ATON runtime/library and + * AtoNN compiler generated files! + */ + +/* Definition of ATON platforms */ +#define LL_ATON_PLAT_NCSIM 1 +#define LL_ATON_PLAT_STICE4 2 +#define LL_ATON_PLAT_ZC706 3 +#define LL_ATON_PLAT_SWEMUL 4 +#define LL_ATON_PLAT_TLM_MCD 5 +#define LL_ATON_PLAT_TSTXPL 6 +#define LL_ATON_PLAT_NEUROMEM_SIM 7 +#define LL_ATON_PLAT_IMAGING_SIM 8 +#define LL_ATON_PLAT_CENTAURI 9 +#define LL_ATON_PLAT_IWAVE 10 +#define LL_ATON_PLAT_N64 11 +#define LL_ATON_PLAT_STM32N6 12 +#define LL_ATON_PLAT_BITTWARE 13 +#define LL_ATON_PLAT_EC_TRACE 14 +#define LL_ATON_PLAT_STM32H7P 15 + +/* Definition of ATON RTOS abstraction layers */ +#define LL_ATON_OSAL_BARE_METAL 1 +#define LL_ATON_OSAL_LINUX_UIO 2 +#define LL_ATON_OSAL_LINUX_BW 3 +#define LL_ATON_OSAL_THREADX 4 +#define LL_ATON_OSAL_FREERTOS 5 +#define LL_ATON_OSAL_ZEPHYR 6 + +#define LL_ATON_OSAL_USER_IMPL \ + ((1 << LL_ATON_CONFIG_OSAL_BSIZE) - \ + 1) /* "Backdoor" for OSAL implementations of custom RTOSes not officially supported by our distribution */ + +/* Definition of the two different modes for ATON runtime */ +/* `LL_ATON_RT_ASYNC` is RECOMMENDED + */ +#define LL_ATON_RT_POLLING 1 +#define LL_ATON_RT_ASYNC 2 + +/* Check definition of LL_ATON_PLATFORM */ +#ifndef LL_ATON_PLATFORM +#error "Needed define 'LL_ATON_PLATFORM' undefined" +#endif + +/* Check definition of LL_ATON_OSAL */ +#ifndef LL_ATON_OSAL +#error "Needed define 'LL_ATON_OSAL' undefined (old default was LL_ATON_OSAL_BARE_METAL)" +#endif + +/* Set beyond macro to one of the above three modes */ +#ifndef LL_ATON_RT_MODE +#define LL_ATON_RT_MODE LL_ATON_RT_ASYNC +#endif + +/* Default values for the other remaining optional macros */ +#ifndef LL_ATON_SW_FALLBACK +#define LL_ATON_SW_FALLBACK 0 +#elif LL_ATON_SW_FALLBACK != 0 && LL_ATON_SW_FALLBACK != 1 +#undef LL_ATON_SW_FALLBACK +#define LL_ATON_SW_FALLBACK 1 +#endif + +#ifndef LL_ATON_DUMP_DEBUG_API +// #define LL_ATON_DUMP_DEBUG_API +#endif + +#ifndef LL_ATON_EB_DBG_INFO +// #define LL_ATON_EB_DBG_INFO +#endif + +#ifndef LL_ATON_DBG_BUFFER_INFO_EXCLUDED +#define LL_ATON_DBG_BUFFER_INFO_EXCLUDED 0 +#endif + +#ifndef LL_ATON_ENABLE_CLOCK_GATING +#define LL_ATON_ENABLE_CLOCK_GATING 1 +#endif + +/* Check if selected values are valid */ +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_NCSIM) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_STICE4) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_ZC706) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_SWEMUL) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_TLM_MCD) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_TSTXPL) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_NEUROMEM_SIM) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_IMAGING_SIM) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_CENTAURI) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_IWAVE) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_N64) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_STM32N6) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_BITTWARE) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_EC_TRACE) +#if (LL_ATON_PLATFORM != LL_ATON_PLAT_STM32H7P) +#error "Wrong definition of `LL_ATON_PLATFORM`" +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif + +#if (LL_ATON_OSAL != LL_ATON_OSAL_BARE_METAL) +#if (LL_ATON_OSAL != LL_ATON_OSAL_LINUX_UIO) +#if (LL_ATON_OSAL != LL_ATON_OSAL_LINUX_BW) +#if (LL_ATON_OSAL != LL_ATON_OSAL_THREADX) +#if (LL_ATON_OSAL != LL_ATON_OSAL_FREERTOS) +#if (LL_ATON_OSAL != LL_ATON_OSAL_ZEPHYR) +#if (LL_ATON_OSAL != LL_ATON_OSAL_USER_IMPL) +#error "Wrong definition of `LL_ATON_OSAL`" +#endif +#endif +#endif +#endif +#endif +#endif +#endif + +#if (LL_ATON_RT_MODE != LL_ATON_RT_POLLING) +#if (LL_ATON_RT_MODE != LL_ATON_RT_ASYNC) +#error "Wrong definition of `LL_ATON_RT_MODE`" +#endif +#endif + +#endif // __LL_ATON_CONFIG_H diff --git a/lib/stai/libstai/include/ll_aton_dbgtrc.h b/lib/stai/libstai/include/ll_aton_dbgtrc.h new file mode 100644 index 000000000..d7f548f06 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_dbgtrc.h @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * @file ll_aton_dbgtrc.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON Debug and Trace unit LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_DBGTRC_H +#define __LL_ATON_DBGTRC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/* Monitored signals offsets list. TODO: move them in compatibility layer */ +#define DBGTRC_GND 0 +#define DBGTRC_VDD 1 +#define SWITCH_OSTRX_STALL 2 +#define DBGTRC_SWITCH_OSTRX_HENV 56 +#define SWITCH_ISTRX_STALL 83 +#define DBGTRC_SWITCH_ISTRX_HENV 165 +#define EXT_TRIGGERS_SYNC 216 +#define DBGTRC_INTCTRL_SIGNALS 220 +#define BUS_INTERFACE_READ1X8B 276 +#define BUS_INTERFACE_READ2X8B 278 +#define BUS_INTERFACE_READ4X8B 280 +#define BUS_INTERFACE_READ8X8B 282 +#define BUS_INTERFACE_WRITE1X8B 284 +#define BUS_INTERFACE_WRITE2X8B 286 +#define BUS_INTERFACE_WRITE4X8B 288 +#define BUS_INTERFACE_WRITE8X8B 290 + +/* Event type descriptors */ +#define DBGTRC_EVT_LOW 0 +#define DBGTRC_EVT_HI 1 +#define DBGTRC_EVT_POSEDGE 2 +#define DBGTRC_EVT_NEGEDGE 3 + +/* Get the cardinal number of a given destination port. + * To be used, for example, with DBGTRC_SWITCH_ISTRX_HENV signals + */ +#define GET_STRSWTCH_DEST(X) ((X - ATON_STRSWITCH_DSTSTRENG0_OFFSET) >> 2) + + /** + * @brief Configuration structure for Debug and Trace unit triggers + */ + typedef struct + { + unsigned int signal; + unsigned char evt_type; + unsigned int filter; + } LL_Dbgtrc_Trigger_InitTypedef; + + /** + * @brief Configuration structure for Debug and Trace unit counters + */ + typedef struct + { + unsigned int signal; /* Signal to monitor */ + unsigned char evt_type; /* Event type (low, hi, posedge, negedge) */ + unsigned char wrap; /* Wrap counter */ + unsigned char countdown; /* Count-up/down. Interrupt can be fired on countdown to zero */ + unsigned char int_disable; /* Mask interrupt */ + uint32_t counter; /* Counter value */ + } LL_Dbgtrc_Counter_InitTypdef; + + /** + * @brief Configuration structure for Debug and Trace unit tracers + */ + typedef struct + { + LL_Dbgtrc_Trigger_InitTypedef triggerconf; /* Trigger configuration */ + unsigned char verbosity; /* Tracer verbosity */ + unsigned int token; /* Optional user token */ + } LL_Dbgtrc_Tracer_InitTypedef; + + /** + * @brief Configuration structure for a 'stopwatch' + * To be used with LL_Dbgtrc_Counter_StopWatch function + */ + typedef struct + { + unsigned char mainCounter; /* ID of the main counter */ + unsigned char startCounter; /* ID of the start event counter */ + unsigned int startSignal; /* Signal triggering the start event */ + unsigned char startEvent; /* Event type of the start condition */ + unsigned char stopCounter; /* ID of the stop event counter */ + unsigned int stopSignal; /* Signal triggering the stop event */ + unsigned char stopEvent; /* Event type of the stop condition */ + } LL_Dbgtrc_StopWatch_InitTypdef; + + /* Global */ + int LL_Dbgtrc_Init(int id); + int LL_Dbgtrc_Deinit(int id); + void LL_Dbgtrc_EnableClock(void); + void LL_Dbgtrc_DisableClock(void); + + uint64_t LL_Dbgtrc_Read_Stalls(int id, unsigned char iolink); + int LL_Dbgtrc_Read_IStall(int id, unsigned int signal); + int LL_Dbgtrc_Read_OStall(int id, unsigned int signal); + + /* Triggers */ + int LL_Dbgtrc_Trigger_Init(int id, int trigger, LL_Dbgtrc_Trigger_InitTypedef *Trigger_InitStruct); + int LL_Dbgtrc_Trigger_Swtrig(int id, int trigger); + int LL_Dbgtrc_Trigger_GetOVR(int id, int trigger); + + /* Counters management */ + int LL_Dbgtrc_Counter_Init(int id, int counter, LL_Dbgtrc_Counter_InitTypdef *Counter_InitStruct); + int LL_Dbgtrc_Counter_Start(int id, int counter); + int LL_Dbgtrc_Counter_Stop(int id, int counter); + uint32_t LL_Dbgtrc_Counter_Read(int id, int counter); + int LL_Dbgtrc_Counter_BindStart(int id, int srccounter, int dstcounter); + int LL_Dbgtrc_Counter_BindStop(int id, int srccounter, int dstcounter); + int LL_Dbgtrc_Counter_StopWatch(int id, LL_Dbgtrc_StopWatch_InitTypdef *StopWatch_InitStruct); + + /* Tracers management */ + int LL_Dbgtrc_Tracer_Init(int id, int tracer, LL_Dbgtrc_Tracer_InitTypedef *Tracer_InitStruct); + int LL_Dbgtrc_Tracer_Bind(int id, int streng, uint8_t *stream_addr, size_t n); + int LL_Dbgtrc_Tracer_Start(int id, int tracer); + int LL_Dbgtrc_Tracer_Stop(int id, int tracer); + int LL_Dbgtrc_Tracer_Enable_Watchdog(int id, unsigned int period); + int LL_Dbgtrc_Tracer_Disable_Watchdog(int id); + + /* Examples */ + + /* Counts IRQs emitted by a given unit */ + int LL_Dbgtrc_Count_IRQs(unsigned int counter, unsigned int unitirq); + + /* Compute Epoch Length by monitoring two stream engines */ + int LL_Dbgtrc_Count_Epoch_Len(unsigned int counter, unsigned int istreng, unsigned int ostreng); + + /* Counts stall/actove signal periods */ + int LL_Dbgtrc_Count_Stalls(unsigned int counter, unsigned char iostall, unsigned int signal, unsigned int hilow); + + /* Burst Lengths computations */ + int LL_Dbgtrc_Count_BurstsLen(unsigned int counter, unsigned char busif, unsigned char readwrite); + int LL_Dbgtrc_BurstLenBenchStart(unsigned int counter); + int LL_Dbgtrc_BurstLenGet(unsigned int counter, unsigned int *counters); + int LL_Dbgtrc_GetTotalTranfers(unsigned int counter_id, unsigned int *totalWrites, unsigned int *totalReads); + int LL_Dbgtrc_LogTransfers(unsigned int counter); + int LL_Dbgtrc_LogTransfers_epoch(unsigned int counter_id, unsigned int *counters, int first); + + /* Count external trigger events. Useful, for example, to detect if a camera has emitted sync signal */ + int LL_Dbgtrc_Count_ExtTrigger(unsigned int counter, unsigned char trigger); + + /* Monitor Stream Engines' active times. Usefult to detect epochs' stall time ratios */ + int LL_Dbgtrc_Count_StrengActive_Config(uint32_t istreng, uint32_t ostreng, unsigned int counter); + int LL_Dbgtrc_Count_StrengActive_Start(uint32_t istreng, uint32_t ostreng, unsigned int counter); + int LL_Dbgtrc_Count_StrengActive_Stop(uint32_t istreng, uint32_t ostreng, unsigned int counter); + unsigned int LL_Dbgtrc_Count_StrengActive_GetMAX(uint32_t istreng, uint32_t ostreng, unsigned int counter, + unsigned int *argmax); + int LL_Dbgtrc_Count_StrengActive_Print(uint32_t istreng, uint32_t ostreng, unsigned int counter); + + /* Monitor input Stream Engines' HENV signal */ + int LL_Dbgtrc_Count_StrengHENV_Config(uint32_t istreng, unsigned int counter); + int LL_Dbgtrc_Count_StrengHENV_Start(uint32_t istreng, unsigned int counter); + int LL_Dbgtrc_Count_StrengHENV_Stop(uint32_t istreng, unsigned int counter); + int LL_Dbgtrc_Count_StrengHENV_Print(uint32_t istreng, unsigned int counter); + + int LL_Dbgtrc_SynchronousCountersTest(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/stai/libstai/include/ll_aton_debug.h b/lib/stai/libstai/include/ll_aton_debug.h new file mode 100644 index 000000000..0cc563a3a --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_debug.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file ll_aton_debug.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON LL low level lib debug module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_DEBUG_H +#define __LL_ATON_DEBUG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +#include "ll_aton_NN_interface.h" + + /** + * * @brief enumerator type for dump_xxx functions + * */ + enum + { + MODE_RAW = 0x1, // Dump buffer with data as is present in memory (i.e. flattend) + MODE_ONNX = 0x2, // Dump buffer considering shape info and in ONNX canonical form (consider batch info) + MODE_INBITS = 0x4, // Dump elements as raw bits (as integers) + MODE_INFLOAT = 0x8, // Dump elements interpreting Qmn format info (as floats) + + MODE_RAW_INBITS = MODE_RAW | MODE_INBITS, + MODE_ONNX_INBITS = MODE_ONNX | MODE_INBITS, + MODE_RAW_INFLOAT = MODE_RAW | MODE_INFLOAT, + MODE_ONNX_INFLOAT = MODE_ONNX | MODE_INFLOAT, + + MODE_8BIT = MODE_RAW_INBITS, // Deprecated defines + MODE_16BIT = MODE_RAW_INBITS, // Deprecated defines + MODE_QMN = MODE_ONNX_INFLOAT, // Deprecated defines + }; + + /** + * @brief enumerator type identifying buffer group (in,out,internal) for dump_xxx functions + */ + enum + { + BUFF_OUT = 1, + BUFF_IN = 2, + BUFF_INT = 4, + }; + + /** + * @brief convert + * @param addr + * @retval pointer + */ + void *LL_ATON_physical_to_virtual(uintptr_t addr); + + /** + * @brief retrieve pointer to a given graph in/output buffer + * @param bufname tensor name + * @param buffer group identifier + * @param pointer to integer to be set with buffer length + * @param pointer to integer to be set with buffer bitwidth + * @param pointer to neural network interface structure + * @retval pointer to buffer or null of not found + */ + void *get_buffer(const char *bufname, int in, unsigned *_len, unsigned *_bits, + const NN_Interface_TypeDef *nn_interface); + + /** + * @brief retrieve buffer info structure for a given graph in/output buffer + * @param bufname tensor name + * @param buffer group identifier + * @param pointer to LL_Buffer_InfoTypeDef to be used to store buffer info + * @param pointer to neural network interface structure + * @retval 1 if buffer is found 0 otherwise + */ + int get_buffer_info(const char *bufname, int in, LL_Buffer_InfoTypeDef *ret, + const NN_Interface_TypeDef *nn_interface); + + /** + * @brief fill all buffers according to buffer group identifier with a given value + * @param in group identifier + * @param val filler value + * @param pointer to neural network interface structure + * @retval none + */ + void set_all_buffers(int in, unsigned val, const NN_Interface_TypeDef *nn_interface); + + /** + * @brief dump a buffer with a given mode + * @param mode dump mode specifier + * @param bufname tensor name + * @param in buffer group identifier + * @param pointer to neural network interface structure + * @retval none + */ + void dump_buffer(int mode, const char *bufname, int in, const NN_Interface_TypeDef *nn_interface); + + /** + * @brief dump all buffers according to buffer group identifier with a given mode + * @param mode dump mode specifier + * @param in buffer groups identifiers + * @param pointer to neural network interface structure + * @retval none + */ + void dump_all_buffers(int mode, int in, const NN_Interface_TypeDef *nn_interface); + + /** + * @brief dump all internal buffers whose epoch matches (to be used in epoch hooks, or if scheduling epoch + * expliciclty) + * @param mode dump mode specifier + * @param epoch epoch number + * @retval none + */ + void dump_epoch_buffers(int mode, int epoch, const NN_Interface_TypeDef *nn_interface); + +// Deprecated methods, implemented as wrappers around new methods +#if defined(__GNUC__) + static inline void dump_tensor_Qmn(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated("use dump_buffer method"))); + static inline void dump_output_16bit(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated("use dump_buffer method"))); + static inline void dump_output_8bit(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated("use dump_buffer method"))); + static inline void dump_all_epoch_buffers(int mode, int epoch, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated("use dump_epoch_buffers method"))); +#else +static inline void dump_tensor_Qmn(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated)); +static inline void dump_output_16bit(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated)); +static inline void dump_output_8bit(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated)); +static inline void dump_all_epoch_buffers(int mode, int epoch, int in, const NN_Interface_TypeDef *nn_interface) + __attribute__((deprecated)); +#endif + + static inline void dump_tensor_Qmn(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + { + dump_buffer(MODE_ONNX_INFLOAT, bufname, in, nn_interface); + } + + static inline void dump_output_16bit(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + { + dump_buffer(MODE_RAW_INBITS, bufname, in, nn_interface); + } + + static inline void dump_output_8bit(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) + { + dump_buffer(MODE_RAW_INBITS, bufname, in, nn_interface); + } + + static inline void dump_all_epoch_buffers(int mode, int epoch, int in, const NN_Interface_TypeDef *nn_interface) + { + dump_epoch_buffers(mode, epoch, nn_interface); + } + + unsigned int get_params_len(const NN_Interface_TypeDef *nn_interface); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/stai/libstai/include/ll_aton_ec_trace.h b/lib/stai/libstai/include/ll_aton_ec_trace.h new file mode 100644 index 000000000..22462df81 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_ec_trace.h @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file ll_aton_ec_trace.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file for defining epoch controller trace methods + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_EC_TRACE_H +#define __LL_ATON_EC_TRACE_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + + typedef struct mpool_reloc_info_t + { + const char *name; + const char *base_symbol; + uintptr_t base_address; + int is_absolute; + int is_user_io; + } mpool_reloc_info_t; + + // array of memory pool info needed for relocation (ends when name == NULL) + extern mpool_reloc_info_t mpool_reloc_info[]; + + extern uintptr_t get_ec_aton_base(void); + extern void initialize_ec_aton_base(void); + + extern void ec_trace_comment(const char *comment); + + extern void ec_trace_init(const char *out_filenamme, const char *network_name); + extern void ec_trace_start_blob(const char *blob_name); + extern void ec_trace_end_blob(const char *blob_name); + extern void ec_trace_start_epoch(unsigned int num); + extern void ec_trace_end_epoch(unsigned int num); + extern void ec_trace_all_blobs_done(void); + + extern void ec_trace_wait_epoch_end(uint32_t wait_mask); + + extern void ec_trace_unsupported(void); + + extern unsigned int ec_trace_get_IP_id(uintptr_t unitbase); + extern unsigned int ec_trace_get_REG_id(unsigned int regoffset); + + extern void ec_trace_write(uintptr_t dstreg, unsigned int val); + extern void ec_trace_write_reloc(uintptr_t dstreg, unsigned int base, unsigned int offset); + extern void ec_trace_reg_write(unsigned int IP_id, unsigned int REG_id, unsigned int val); + extern void ec_trace_reg_write_reloc(unsigned int IP_id, unsigned int REG_id, unsigned int base, unsigned int offset); + extern void ec_trace_reg_writefield(unsigned int IP_id, unsigned int REG_id, unsigned int lsb, unsigned int num_bits, + unsigned int val); + extern void ec_trace_reg_poll(unsigned int IP_id, unsigned int REG_id, unsigned int lsb, unsigned int num_bits, + unsigned int val); + +#ifdef __cplusplus +} +#endif + +#endif // __LL_ATON_EC_TRACE_H diff --git a/lib/stai/libstai/include/ll_aton_lib.h b/lib/stai/libstai/include/ll_aton_lib.h new file mode 100644 index 000000000..b3c051ea1 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_lib.h @@ -0,0 +1,503 @@ +/** + ****************************************************************************** + * @file ll_aton_lib.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON LL low level lib module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_LIB_H +#define __LL_ATON_LIB_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ll_aton.h" +#include "ll_aton_NN_interface.h" +#include "ll_aton_caches_interface.h" +#include "ll_aton_lib_sw_operators.h" + +#ifndef _LL_LIB_DEBUG +#define _LL_LIB_DEBUG 1 +#endif + +#if _LL_LIB_DEBUG + /** + * * @brief library error helper types, functions, and macros + * */ + enum __ll_lib_errors + { + _ERR_UNKNOWN = 0, + _ERR_NINPUTS, + _ERR_NOUTPUTS, + _ERR_AXIS, + _ERR_FRACTIONAL, + _ERR_DATATYPE, + _ERR_NBITS, + _ERR_NBITS_IN, + _ERR_NBITS_OUT, + _ERR_SHAPE, + _ERR_SHAPE_IN, + _ERR_SHAPE_OUT, + _ERR_BUFFER, + _ERR_BUFFER_IN, + _ERR_BUFFER_OUT, + _ERR_RANK, + _ERR_MODE, + }; + + /* Forward declaration for global function to be used only by `ll_lib` library */ + extern void __ll_lib_error(int err_code, int line, const char *func); + +#define __LL_LIB_ERROR(_x, _y) \ + { \ + __ll_lib_error(_x, __LINE__, __FUNCTION__); \ + return _y; \ + } +#else // !_LL_LIB_DEBUG +#define __LL_LIB_ERROR(_x, _y) return _y +#endif // !_LL_LIB_DEBUG + +#if 0 +/** + * * @brief tensor data type info structure + * */ +/* Note: the data type values match ONNX TensorProto.DataType enum */ +typedef enum +{ + TENSORINFO_DATATYPE_UNDEFINED = 0, + TENSORINFO_DATATYPE_FLOAT = 1, + TENSORINFO_DATATYPE_UINT8 = 2, + TENSORINFO_DATATYPE_INT8 = 3, + TENSORINFO_DATATYPE_UINT16 = 4, + TENSORINFO_DATATYPE_INT16 = 5, + TENSORINFO_DATATYPE_INT32 = 6, + TENSORINFO_DATATYPE_INT64 = 7, + TENSORINFO_DATATYPE_STRING = 8, + TENSORINFO_DATATYPE_BOOL = 9, + TENSORINFO_DATATYPE_FLOAT16 = 10, + TENSORINFO_DATATYPE_DOUBLE = 11, + TENSORINFO_DATATYPE_UINT32 = 12, + TENSORINFO_DATATYPE_UINT64 = 13, + TENSORINFO_DATATYPE_COMPLEX64 = 14, + TENSORINFO_DATATYPE_COMPLEX128 = 15, + TENSORINFO_DATATYPE_BFLOAT16 = 16, + TENSORINFO_DATATYPE_QMN = 100, // ATONN specific +} LL_LIB_TensorInfo_DataType_TypeDef; + +/** + * * @brief tensor info structure + * */ +typedef struct +{ + ll_aton_pointer addr_base; + int offset_start; + int offset_end; + int batches; // not sure we'll support this!!! + int nchannels; + int fwidth; + int fheight; + int ndims; + int nbits; + int Qm; + int Qn; + int Qunsigned; + int dtype; // it's a LL_LIB_TensorInfo_DataType_TypeDef +} LL_LIB_TensorInfo_TypeDef; + +typedef LL_Buffer_InfoTypeDef LL_LIB_TensorInfo_TypeDef; + +#define _TDIM(x) ((x) != 0 ? (x) : 1) +#define LL_LIB_TENSOR_ELEMENTS(t) \ + (_TDIM((t)->batches) * _TDIM((t)->fwidth) * _TDIM((t)->fheight) * _TDIM((t)->nchannels)) +#else +/* ATON canonical positions */ +#define TDIM_NKERNELS 0 +#define TDIM_FHEIGHT 1 +#define TDIM_FWIDTH 2 +#define TDIM_NCHANNELS 3 + +#define _TDIM(x) ((x) != 0 ? (x) : 1) + +typedef LL_Buffer_InfoTypeDef LL_LIB_TensorInfo_TypeDef; + +#if 0 +#define LL_LIB_TENSOR_ELEMENTS(t) \ + (_TDIM((t)->shape[TDIM_NKERNELS]) * _TDIM((t)->shape[TDIM_FWIDTH]) * _TDIM((t)->shape[TDIM_FHEIGHT]) * \ + _TDIM((t)->shape[TDIM_NCHANNELS])) +#else +int LL_LIB_TENSOR_ELEMENTS(const LL_LIB_TensorInfo_TypeDef *t); +#endif + +/* ONNX canonical positions */ +#define TDIM_ONNX_NKERNELS 0 +#define TDIM_ONNX_NCHANNELS 1 +#define TDIM_ONNX_FHEIGHT 2 +#define TDIM_ONNX_FWIDTH 3 +#endif + + /** + * * @brief Heap typedefs + * */ + typedef struct + { + /* Generic fields common to all cases */ + LL_Streng_TensorInitTypeDef g_dma_in; + LL_Streng_TensorInitTypeDef g_dma_out; + + /* Generic fields common at least for two cases */ + int g_idx; + int g_size; + + unsigned char *g_dst_o_src; + unsigned int g_offset_limit; + unsigned int g_not_continuous; // 0 or 1 used by batched version of memcpy + + unsigned int g_num_tensors; + const void *g_tensors; + + uint32_t g_wait_mask; + + /* Special field(s) for single cases */ + union + { + /* Concat_Case3 */ + struct + { + unsigned int outer_idx; + unsigned int in_fheight; + unsigned int nbytes; + unsigned int out_line_size; + unsigned char *in_curr; + } concat_case3; + /* Pad */ + __ll_pad_sw_params_t pad; + } special; + } __ll_lib_params_t; + + typedef union + { + uint32_t _alignment; // align `__ll_lib_params_t` to 4 bytes + __ll_lib_params_t heap_params; + } __ll_lib_params_align_t; + + typedef union + { + uint32_t _alignment; // align `LL_Buffer_InfoTypeDef` to 4 bytes + LL_Buffer_InfoTypeDef buffer_info; + } __ll_lib_buffer_align_t; + +/* "Heap" dedicated for the implementation of HW-accelerated operators, + * based on maximum number of tensors to be supported */ +#define __LL_MAX_TENSORS 24 + +#define __LL_LOWER_HEAP_SIZE ((sizeof(__ll_lib_buffer_align_t) * __LL_MAX_TENSORS) / sizeof(uint32_t)) // in words +#define __LL_LIB_HEAP_SIZE ((sizeof(__ll_lib_params_align_t) / sizeof(uint32_t)) + __LL_LOWER_HEAP_SIZE) // in words + +#ifndef offsetof +#define offsetof(st, m) ((size_t) & (((st *)0)->m)) +#endif + +#define __LL_DMA_PAD_MAX_DIMS \ + ((__LL_LOWER_HEAP_SIZE * sizeof(uint32_t)) / \ + (sizeof(__ll_pad_sw_params_t) - offsetof(__ll_pad_sw_params_t, min_shape))) + +#define __LL_DMA_MIN_BUFF_LEN 40 + + /** + * @brief performs a concat operation according to ONNX semantics + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structure + * @param axis for concatenation + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Concat function + * * @{ + * */ + int LL_ATON_LIB_Concat(const LL_Buffer_InfoTypeDef *, unsigned int, const LL_Buffer_InfoTypeDef *, unsigned int, int, + int); + /** + * * @} + * */ + + /** + * @brief performs a tensor ImageToRow transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * @param stride_h vertical stride for the sliding window + * @param stride_w horizontal stride for the sliding window + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ + /** @defgroup LL_ATON_LIB_DMA_ImageToRow function + * * @{ + * */ + int LL_ATON_LIB_DMA_ImageToRow(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + unsigned stride_h, unsigned stride_w, int dma_in, int dma_out); + /** + * * @} + * */ + + /** + * @brief performs a tensor SpaceToDepth transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ + /** @defgroup LL_ATON_LIB_DMA_SpaceToDepth function + * * @{ + * */ + int LL_ATON_LIB_DMA_SpaceToDepth(const LL_LIB_TensorInfo_TypeDef *, unsigned int, const LL_LIB_TensorInfo_TypeDef *, + unsigned, unsigned, int, int); + + /** + * * @} + * */ + + /** + * @brief performs a tensor RowToImage transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * @param stride_h vertical stride for the sliding window + * @param stride_w horizontal stride for the sliding window + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ + int LL_ATON_LIB_DMA_RowToImage(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + unsigned stride_h, unsigned stride_w, int dma_in, int dma_out); + + /** + * * @} + * */ + + /** + * @brief performs a tensor DepthToSpace transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Supports only DCR (depth-column-row) order re-arrangement + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ + /** @defgroup LL_ATON_LIB_DMA_DepthToSpace function + * * @{ + * */ + + int LL_ATON_LIB_DMA_DepthToSpace(const LL_LIB_TensorInfo_TypeDef *, unsigned int, const LL_LIB_TensorInfo_TypeDef *, + unsigned, unsigned, int, int); + + /** + * * @} + * */ + + /** + * @brief performs a cast operation to/from Qmn and float + * @param input tensor info structure + * @param output tensor info structure + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Cast function + * * @{ + * */ + int LL_ATON_LIB_Cast(const LL_LIB_TensorInfo_TypeDef *, const LL_LIB_TensorInfo_TypeDef *, int, int); + /** + * * @} + * */ + + /** + * @brief performs a Softmax operation on float inputs and output operands according to ONNX semantics + * @param input tensor info structure + * @param output tensor info structure + * @param axis for coalescing of shape into a 2D matrix + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Softmax function + * * @{ + * */ + int LL_ATON_LIB_Softmax(const LL_LIB_TensorInfo_TypeDef *, const LL_LIB_TensorInfo_TypeDef *, unsigned int, int); + /** + * * @} + * */ + + /** + * @brief performs flat copy operation on an input and several outputs using DMA + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param nr_of_outputs number of output tensors + * @param dma_in DMA number of DMA reading from memory + * @param dma_in DMA number of DMA writing to memory + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DMA_Outputs_Flat_Copy function + * * @{ + * */ + int LL_ATON_LIB_DMA_Outputs_Flat_Copy(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, + int dma_in, int dma_out); + /** + * * @} + * */ + + /** + * @brief perform split-like slice operation using DMAs + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param tot_out_size size of output buffer + * @param width_in_bytes number of bytes per `memcpy` + * @param fheight DMA `fheight` field + * @param line_offset DMA `line_offset` field + * @param n_bits DMA channel size + * @param dma_in DMA number of DMA reading from memory + * @param dma_in DMA number of DMA writing to memory + * @return Error code + */ + int LL_ATON_LIB_DMA_Outputs_Slice_SplitLike(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *output, int32_t tot_out_size, + int32_t width_in_bytes, int32_t fheight, int32_t line_offset, + int8_t n_bits, int dma_in, int dma_out); + /** + * * @} + * */ + + /** + * @brief performs channel-split copy operation on an input and several outputs (both in ATON canonical format) using + * DMA + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param nr_of_outputs number of output tensors + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton function + * * @{ + * */ + int LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton(const LL_LIB_TensorShape_TypeDef *, const LL_LIB_TensorShape_TypeDef *, + unsigned int, unsigned int leading_dims, int dma_in, int dma_out); + /** + * * @} + * */ + + /** + * @brief performs a channel-split memory copy operation from one input (ATON canonical) to `noutputs` + * non-ATON-canonical outputs using stream engines `dma_in` and `dma_out` + * @param src source address + * @param outputs list of output tensor shape structures + * @param noutputs number of outputs + * @retval Error code + */ + int LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, + unsigned int nr_of_outputs, int dma_in, int dma_out); + /** @defgroup LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched function + * * @{ + * */ + + /** + * @brief performs an optimized `memset` for the `Pad` operator using DMA (aka Framing) + * @param output destination address of `memset` operation + * @param constant_value constant value to be set + * @param out_size number of bytes to output + * @param common_params parameters needed to setup DMAs and to forward to eventual callback function + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DMA_Pad_Memset function + * * @{ + * */ + int LL_ATON_LIB_DMA_Pad_Memset(void *output, int32_t constant_value, size_t out_size, + __ll_pad_sw_params_t *common_params); + /** + * * @} + * */ + + /** + * @brief performs HW accelerated filling operation for `Pad` operator (aka Filling) + * @param init_common_params parameters needed to setup DMAs and to forward to eventual callback function + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DMA_Pad_Filling function + * * @{ + * */ + int LL_ATON_LIB_DMA_Pad_Filling(__ll_pad_sw_params_t *init_common_params); + /** + * * @} + * */ + + /** + * @brief performs a transpose operation on a (4-dimensional) matrix using DMA + * currently supported permutation(s) is/are: (0, 2, 1, 3)-onnx + * @param input tensor shape structure + * @param output tensor shape structure + * @param target_pos target positions of input tensor + * @param perm_to_use permutation to apply (when using fallback to pure SW) + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DMA_Transpose function + * * @{ + * */ + int LL_ATON_LIB_DMA_Transpose(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + const uint8_t *target_pos, const uint8_t *perm_to_use, int dma_in, int dma_out); + + /** + * @} + */ + + /** + * @brief performs a ConvInteger operation + * @param input tensor shape structure + * @param ninputs number of inputs feat, kern, bias (optional) + * @param output tensor shape structure + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DMA_Transpose function + * * @{ + * */ + + int LL_ATON_LIB_ConvInteger(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output); + /** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/stai/libstai/include/ll_aton_lib_sw_operators.h b/lib/stai/libstai/include/ll_aton_lib_sw_operators.h new file mode 100644 index 000000000..355498bad --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_lib_sw_operators.h @@ -0,0 +1,231 @@ +/** + ****************************************************************************** + * @file ll_aton_lib_sw_operators.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON library for pure SW operators + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_LIB_SW_OPERATORS_H +#define __LL_ATON_LIB_SW_OPERATORS_H + +#include +#include + +#include "ll_aton_NN_interface.h" +#include "ll_aton_caches_interface.h" +#include "ll_aton_lib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define __LL_PAD_FRAMING_DMA_MIN_BUFF_LEN 9500 +#define __LL_PAD_FILLING_DMA_MIN_BUFF_LEN 1200 + + // Uncomment beyond line to get runtime information about beyond SW operator's execution + // #define DUMP_DEBUG_SW_OPS + + // Uncomment beyond line to dump operation results for `Pad` operator + // #define DUMP_RESULTS_PAD_OP + + typedef LL_Buffer_InfoTypeDef LL_LIB_TensorShape_TypeDef; +#define LL_LIB_NBYTES(x) ((x) + 7) >> 3 + + /** + * @} + */ + + /** + * @brief performs a split operation on a (multi-dimensional) matrix + * @param input tensor shape structure + * @param aton_canonical is input tensor ATON canonical + * @param output tensors shape structures + * @param noutput number of of output tensors + * @param rank rank of split operation's input matrix + * @param split_onnx_axis which axis to split on (ONNX value) + * @param leading_dims product of leading dimensions + * @param split_case optimization to be used + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Split function + * * @{ + * */ + int LL_ATON_LIB_Split(const LL_LIB_TensorShape_TypeDef *input, bool aton_canonical, + const LL_LIB_TensorShape_TypeDef (*outputs)[], uint32_t noutputs, uint32_t rank, + uint32_t split_onnx_axis, uint32_t leading_dims, int split_case, int dma_in, int dma_out); + + /** + * @brief performs a slice operation on a (multi-dimensional) matrix + * @param input tensor shape structure + * @param output tensor shape structure + * @param slice_rank rank of slice operation's input matrix + * @param slice_starts 1-D tensor of starting indices of corresponding axis from 0 to rank-1 + * @param slice_ends 1-D tensor of ending indices (exclusive) of corresponding axis from 0 to rank-1 + * @param slice_steps 1-D tensor of slice step of corresponding axis from 0 to rank-1 + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Slice function + * * @{ + * */ + int LL_ATON_LIB_Slice(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + uint32_t slice_rank, const int32_t *slice_starts, const int32_t *slice_ends, + const int32_t *slice_steps); + + /** + * * @} + * */ + + /** + * @brief performs a `SpaceToDepth` operation on a 4-dimensional matrix purely in SW + * @param input tensor shape structure + * @param output tensor shape structure + * @param bs_h height dimension of blocksize of `SpaceToDepth` operation + * @param bs_w width dimension of blocksize of `SpaceToDepth` operation + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_SpaceToDepth function + * * @{ + * */ + int LL_ATON_LIB_SW_SpaceToDepth(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + uint32_t bs_h, uint32_t bs_w); + + /** + * * @} + * */ + + /** + * @brief performs a `DepthToSpace` operation on a 4-dimensional matrix purely in SW + * @param input tensor shape structure + * @param output tensor shape structure + * @param bs_h height dimension of blocksize of `DepthToSpace` operation + * @param bs_w width dimension of blocksize of `DepthToSpace` operation + * @param mode of `DepthToSpace` operation (0 = `DCR` - depth-column-row, 1 = `CRD` - column-row-depth) + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_DepthToSpace function + * * @{ + * */ + int LL_ATON_LIB_SW_DepthToSpace(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + uint32_t bs_h, uint32_t bs_w, uint32_t mode); + + /** + * * @} + * */ + + /** + * @brief performs a transpose operation on a (multi-dimensional) matrix + * @param input tensor shape structure + * @param output tensor shape structure + * @param perm permutation to apply + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Transpose function + * * @{ + * */ + int LL_ATON_LIB_Transpose(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + const uint8_t *perm); + /** + * * @} + * */ + + /** + * @brief performs a `Pad` operation - composed of several HW-accelerated or pure SW `framing`/`memset` and `filling` + * functions - on a (multi-dimensional) matrix + * @param input start address of input tensor + * @param output start address of output tensor + * @param min_shape shape obtained by performing element-wise `min` on each axis of reduced input vs output tensor + * @param mode where 0 == `constant`, 1 == `reflect`, 2 ==`edge` + * @param nbytes 8-bit or 16-bit mode + * @param out_elems number of output elements + * @param constant_value constant value to be `memset` + * @param consecutive_axis last input axis with all zero start/end paddings and whose following axes also have all + * zero paddings (or last axis) + * @param consecutive_elems number of consecutive elements to copy in each repetition + * @param pad_in_offsets_start vector containing amount (in bytes) of input padding data added at beginning of each + * axis + * @param pad_in_offsets_end vector containing amount (in bytes) of input padding data added at and of each axis + * @param pad_out_offsets_start vector containing amount (in bytes) of output padding data added at beginning of each + * axis + * @param pad_out_offsets_end vector containing amount (in bytes) of output padding data added at and of each axis + * @param out_shape shape of output tensor + * @param out_offsets offset of each output tensor item + * @param tensor_rank rank of input and output tensors + * @retval Error code + */ + /** @defgroup LL_ATON_LIB_Pad function + * * @{ + * */ + int LL_ATON_LIB_Pad(unsigned char *input, unsigned char *output, unsigned char *input_limit, + unsigned char *output_limit, const uint32_t *min_shape, uint8_t mode, uint8_t nbytes, + uint32_t out_elems, int32_t constant_value, uint32_t consecutive_axis, uint32_t consecutive_elems, + const int32_t *pad_in_offsets_start, const int32_t *pad_in_offsets_end, + const int32_t *pad_out_offsets_start, const int32_t *pad_out_offsets_end, + const int32_t *out_shape, const int32_t *out_offsets, size_t tensor_rank, int dma_in, + int dma_out); + /** + * * @} + * */ + + typedef int (*pad_callback_func_t)(void *); + typedef struct + { + int8_t *in_target; + int8_t *out_target; + int8_t *in_limit; + int8_t *out_limit; + uint32_t consecutive_axis; + uint32_t consecutive_bytes; + uint8_t nbytes; // 1, 2, 3, or 4 bytes + uint8_t mode; // where 0 == `constant`, 1 == `reflect`, 2 ==`edge` + int8_t *saved_in_target; + int8_t *saved_out_target; + size_t tensor_rank; + int8_t *end_out_target; + pad_callback_func_t callback_function; + int dma_in; + int dma_out; +#if defined(DUMP_RESULTS_PAD_OP) + size_t out_size; // in bytes +#endif + + /* Please add (not deep-copy) items above this line!!! */ + + const uint32_t *min_shape; // must be first deep-copy item!!! + const int32_t *pad_in_offsets_start; + const int32_t *pad_in_offsets_end; + const int32_t *pad_out_offsets_start; + const int32_t *pad_out_offsets_end; + const int32_t *out_shape; + const int32_t *out_offsets; + uint32_t *indexes; + } __ll_pad_sw_params_t; + + /** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif // __LL_ATON_LIB_SW_OPERATORS_H + +/** + * @} + */ diff --git a/lib/stai/libstai/include/ll_aton_osal.h b/lib/stai/libstai/include/ll_aton_osal.h new file mode 100644 index 000000000..24a84d660 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_osal.h @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file ll_aton_osal.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file for defining an abstraction of RTOS differences + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_OSAL_H +#define __LL_ATON_OSAL_H + +/*** Platform choice ***/ +#include "ll_aton_config.h" + +/*** Platform dependent definitions & includes ***/ + +/* Bare metal Cortex-M NCSIM simulator OSAL*/ +#if (LL_ATON_OSAL == LL_ATON_OSAL_BARE_METAL) + +/* Macros for (de-)initialization of OSAL layer */ +#define LL_ATON_OSAL_INIT() +#define LL_ATON_OSAL_DEINIT() + +/* Wait for / signal event from ATON runtime */ +#define LL_ATON_OSAL_WFE() __WFE() +#define LL_ATON_OSAL_SIGNAL_EVENT() + +#elif (LL_ATON_OSAL == LL_ATON_OSAL_LINUX_UIO) + +#include "ll_aton_osal_linux_uio.h" + +/* Macros for (de-)initialization of OSAL layer */ +#define LL_ATON_OSAL_INIT() linux_init() +#define LL_ATON_OSAL_DEINIT() linux_uninit() + +/* Wait for / signal event from ATON runtime */ +#define LL_ATON_OSAL_WFE() linux_wfe() +#define LL_ATON_OSAL_SIGNAL_EVENT() + +#define LL_ATON_OSAL_INSTALL_IRQ(irq_aton_line_nr, handler) linux_install_irq(irq_aton_line_nr, handler) +#define LL_ATON_OSAL_REMOVE_IRQ(irq_aton_line_nr) linux_install_irq(irq_aton_line_nr, NULL) +#define LL_ATON_OSAL_ENABLE_IRQ(irq_aton_line_nr) linux_enable_irq(irq_aton_line_nr, true) +#define LL_ATON_OSAL_DISABLE_IRQ(irq_aton_line_nr) linux_enable_irq(irq_aton_line_nr, false) + +/* Enter/exit a critical section for the ATON runtime thread/task */ +#define LL_ATON_OSAL_ENTER_CS() /* NVIC_DisableIRQ(CDNN0_IRQn) */ +#define LL_ATON_OSAL_EXIT_CS() /* NVIC_EnableIRQ(CDNN0_IRQn) */ + +/* Data synchronization barrier */ +#ifdef __ARM_ARCH +#include +#define LL_ATON_OSAL_DSB() __DSB() +#else +#include +#define LL_ATON_OSAL_DSB() _mm_lfence() +#endif + +#elif (LL_ATON_OSAL == LL_ATON_OSAL_LINUX_BW) +#include "ll_aton_osal_linux_bw.h" + +/* Macros for (de-)initialization of OSAL layer */ +#define LL_ATON_OSAL_INIT() bw_init() +#define LL_ATON_OSAL_DEINIT() bw_uninit() + +/* Wait for / signal event from ATON runtime */ +#define LL_ATON_OSAL_WFE() bw_wfe() +#define LL_ATON_OSAL_SIGNAL_EVENT() bw_post_event() + +#define LL_ATON_OSAL_INSTALL_IRQ(irq_aton_line_nr, handler) bw_install_irq(irq_aton_line_nr, handler) +#define LL_ATON_OSAL_REMOVE_IRQ(irq_aton_line_nr) bw_uninstall_irq(irq_aton_line_nr) +#define LL_ATON_OSAL_ENABLE_IRQ(irq_aton_line_nr) +#define LL_ATON_OSAL_DISABLE_IRQ(irq_aton_line_nr) +#define LL_ATON_OSAL_ENTER_CS() bw_enter_cs() +#define LL_ATON_OSAL_EXIT_CS() bw_exit_cs() + +#include +#define LL_ATON_OSAL_DSB() _mm_lfence() + +#elif (LL_ATON_OSAL == LL_ATON_OSAL_THREADX) +#include "ll_aton_osal_threadx.h" + +#define LL_ATON_OSAL_INIT() aton_osal_threadx_init() +#define LL_ATON_OSAL_DEINIT() aton_osal_threadx_deinit() + +/* Wait for / signal event from ATON runtime */ +#define LL_ATON_OSAL_WFE() aton_osal_threadx_wfe() +#define LL_ATON_OSAL_SIGNAL_EVENT() aton_osal_threadx_signal_event() + +/* Locks */ +#if APP_HAS_PARALLEL_NETWORKS +#ifdef LL_ATON_OSAL_TX_OLD +#define LL_ATON_OSAL_LOCK_ATON() aton_osal_threadx_pb_lock() +#define LL_ATON_OSAL_UNLOCK_ATON() aton_osal_threadx_pb_unlock() +#else // LL_ATON_OSAL_TX_OLD +#define LL_ATON_OSAL_LOCK_ATON() aton_osal_threadx_dao_lock() +#define LL_ATON_OSAL_UNLOCK_ATON() aton_osal_threadx_dao_unlock() +#endif // LL_ATON_OSAL_TX_OLD +#endif // APP_HAS_PARALLEL_NETWORKS + +#define LL_ATON_OSAL_LOCK_NPU_CACHE() aton_osal_threadx_lock() +#define LL_ATON_OSAL_UNLOCK_NPU_CACHE() aton_osal_threadx_unlock() + +#elif (LL_ATON_OSAL == LL_ATON_OSAL_FREERTOS) +#include "ll_aton_osal_freertos.h" + +#define LL_ATON_OSAL_INIT() aton_osal_freertos_init() +#define LL_ATON_OSAL_DEINIT() aton_osal_freertos_deinit() + +/* Wait for / signal event from ATON runtime */ +#define LL_ATON_OSAL_WFE() aton_osal_freertos_wfe() +#define LL_ATON_OSAL_SIGNAL_EVENT() aton_osal_freertos_signal_event() + +/* Locks */ +#if APP_HAS_PARALLEL_NETWORKS +#define LL_ATON_OSAL_LOCK_ATON() aton_osal_freertos_dao_lock() +#define LL_ATON_OSAL_UNLOCK_ATON() aton_osal_freertos_dao_unlock() +#endif // APP_HAS_PARALLEL_NETWORKS + +#define LL_ATON_OSAL_LOCK_NPU_CACHE() aton_osal_freertos_lock() +#define LL_ATON_OSAL_UNLOCK_NPU_CACHE() aton_osal_freertos_unlock() + +#elif (LL_ATON_OSAL == LL_ATON_OSAL_ZEPHYR) +#include "ll_aton_osal_zephyr.h" + +/* Init & De-Initialization */ +#define LL_ATON_OSAL_INIT() aton_osal_zephyr_init() +#define LL_ATON_OSAL_DEINIT() aton_osal_zephyr_deinit() + +/* IRQ handling */ +#define LL_ATON_OSAL_INSTALL_IRQ(irq_aton_line_nr, handler) aton_osal_zephyr_install_irq(irq_aton_line_nr, handler) +#define LL_ATON_OSAL_REMOVE_IRQ(irq_aton_line_nr) aton_osal_zephyr_uninstall_irq(irq_aton_line_nr) +#define LL_ATON_OSAL_ENABLE_IRQ(irq_aton_line_nr) aton_osal_zephyr_enable_irq(irq_aton_line_nr) +#define LL_ATON_OSAL_DISABLE_IRQ(irq_aton_line_nr) aton_osal_zephyr_disable_irq(irq_aton_line_nr) +#define LL_ATON_OSAL_ENTER_CS() aton_osal_zephyr_enter_cs() +#define LL_ATON_OSAL_EXIT_CS() aton_osal_zephyr_exit_cs() + +/* Wait for / signal event from ATON runtime */ +#define LL_ATON_OSAL_WFE() aton_osal_zephyr_wfe() +#define LL_ATON_OSAL_SIGNAL_EVENT() aton_osal_zephyr_signal_event() + +/* Locks */ +#if APP_HAS_PARALLEL_NETWORKS +#define LL_ATON_OSAL_LOCK_ATON() aton_osal_zephyr_dao_lock() +#define LL_ATON_OSAL_UNLOCK_ATON() aton_osal_zephyr_dao_unlock() +#endif // APP_HAS_PARALLEL_NETWORKS + +#define LL_ATON_OSAL_LOCK_NPU_CACHE() aton_osal_zephyr_lock() +#define LL_ATON_OSAL_UNLOCK_NPU_CACHE() aton_osal_zephyr_unlock() + +#elif (LL_ATON_OSAL == LL_ATON_OSAL_USER_IMPL) +#include "ll_aton_osal_user_impl.h" /* file to be provided together with an implemetation of the custom OSAL by the user */ + +#else +#error No target OSAL is specified. Please define macro `LL_ATON_OSAL` +#endif + +/*** Default implementations ***/ + +/* Handling of ATON IRQ */ +#ifndef LL_ATON_OSAL_INSTALL_IRQ +#define LL_ATON_OSAL_INSTALL_IRQ(irq_aton_line_nr, handler) +#endif // LL_ATON_OSAL_INSTALL_IRQ + +#ifndef LL_ATON_OSAL_REMOVE_IRQ +#define LL_ATON_OSAL_REMOVE_IRQ(irq_aton_line_nr) +#endif // LL_ATON_OSAL_REMOVE_IRQ + +#ifndef LL_ATON_OSAL_ENABLE_IRQ +#define LL_ATON_OSAL_ENABLE_IRQ(irq_aton_line_nr) \ + do \ + { \ + switch (irq_aton_line_nr) \ + { \ + case 0: \ + NVIC_EnableIRQ(CDNN0_IRQn); \ + break; \ + case 1: \ + NVIC_EnableIRQ(CDNN1_IRQn); \ + break; \ + case 2: \ + NVIC_EnableIRQ(CDNN2_IRQn); \ + break; \ + case 3: \ + NVIC_EnableIRQ(CDNN3_IRQn); \ + break; \ + default: \ + assert(0); \ + break; \ + } \ + } while (0) +#endif // LL_ATON_OSAL_ENABLE_IRQ + +#ifndef LL_ATON_OSAL_DISABLE_IRQ +#define LL_ATON_OSAL_DISABLE_IRQ(irq_aton_line_nr) \ + do \ + { \ + switch (irq_aton_line_nr) \ + { \ + case 0: \ + NVIC_DisableIRQ(CDNN0_IRQn); \ + break; \ + case 1: \ + NVIC_DisableIRQ(CDNN1_IRQn); \ + break; \ + case 2: \ + NVIC_DisableIRQ(CDNN2_IRQn); \ + break; \ + case 3: \ + NVIC_DisableIRQ(CDNN3_IRQn); \ + break; \ + default: \ + assert(0); \ + break; \ + } \ + } while (0) +#endif // LL_ATON_OSAL_DISABLE_IRQ + +#ifndef LL_ATON_OSAL_SET_PRIORITY +#define LL_ATON_OSAL_SET_PRIORITY(irq_aton_line_nr, prio) \ + do \ + { \ + switch (irq_aton_line_nr) \ + { \ + case 0: \ + NVIC_SetPriority(CDNN0_IRQn, prio); \ + break; \ + case 1: \ + NVIC_SetPriority(CDNN1_IRQn, prio); \ + break; \ + case 2: \ + NVIC_SetPriority(CDNN2_IRQn, prio); \ + break; \ + case 3: \ + NVIC_SetPriority(CDNN3_IRQn, prio); \ + break; \ + default: \ + assert(0); \ + break; \ + } \ + } while (0) +#endif // LL_ATON_OSAL_SET_PRIORITY + +/* Enter/exit a critical section for the ATON runtime thread/task */ + +// NOTE: here we need to block also execution of IRQ handler +#ifndef LL_ATON_OSAL_ENTER_CS +#define LL_ATON_OSAL_ENTER_CS() NVIC_DisableIRQ(ATON_STD_IRQn) +#endif // LL_ATON_OSAL_ENTER_CS + +#ifndef LL_ATON_OSAL_EXIT_CS +#define LL_ATON_OSAL_EXIT_CS() NVIC_EnableIRQ(ATON_STD_IRQn) +#endif // LL_ATON_OSAL_EXIT_CS + +/* Data synchronization barrier */ +#ifndef LL_ATON_OSAL_DSB +#define LL_ATON_OSAL_DSB() __DSB() +#endif // LL_ATON_OSAL_DSB + +/** Locking mechanisms for thread-safe ATON runtime **/ + +/* ATON IP */ +#ifndef LL_ATON_OSAL_LOCK_ATON +#define LL_ATON_OSAL_LOCK_ATON() +#endif // !LL_ATON_OSAL_LOCK_ATON + +#ifndef LL_ATON_OSAL_UNLOCK_ATON +#define LL_ATON_OSAL_UNLOCK_ATON() +#endif // !LL_ATON_OSAL_UNLOCK_ATON + +/* NPU Cache Lock */ +// NOTE: Needs to be implemented only if NPU cache maintenance operations cannot be performed in parallel +// NOTE: This lock may be taken while the ATON IP lock (aka `LL_ATON_OSAL_LOCK_ATON`) is held. +// Therfore, either use two independent locking mechanisms for them or one re-entrant mechanism +#ifndef LL_ATON_OSAL_LOCK_NPU_CACHE +#define LL_ATON_OSAL_LOCK_NPU_CACHE() +#define LL_HAS_NO_ATON_OSAL_LOCK_NPU_CACHE +#endif // !LL_ATON_OSAL_LOCK_NPU_CACHE + +#ifndef LL_ATON_OSAL_UNLOCK_NPU_CACHE +#define LL_ATON_OSAL_UNLOCK_NPU_CACHE() +#endif // !LL_ATON_OSAL_UNLOCK_NPU_CACHE + +/* MCU Cache Lock */ +// NOTE: Needs to be implemented only if MCU cache maintenance operations cannot be performed in parallel +// NOTE: This lock may be taken while the ATON IP lock (aka `LL_ATON_OSAL_LOCK_ATON`) is held. +// Therfore, either use two independent locking mechanisms for them or one re-entrant mechanism +#ifndef LL_ATON_OSAL_LOCK_MCU_CACHE +#define LL_ATON_OSAL_LOCK_MCU_CACHE() +#define LL_HAS_NO_ATON_OSAL_LOCK_MCU_CACHE +#endif // !LL_ATON_OSAL_LOCK_MCU_CACHE + +#ifndef LL_ATON_OSAL_UNLOCK_MCU_CACHE +#define LL_ATON_OSAL_UNLOCK_MCU_CACHE() +#endif // !LL_ATON_OSAL_UNLOCK_MCU_CACHE + +#endif // __LL_ATON_OSAL_H diff --git a/lib/stai/libstai/include/ll_aton_osal_freertos.h b/lib/stai/libstai/include/ll_aton_osal_freertos.h new file mode 100644 index 000000000..5308ba794 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_osal_freertos.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_freertos.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface to FreeRTOS as the underlying OS/platform for ATON + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_OSAL_FREERTOS_H +#define __LL_ATON_OSAL_FREERTOS_H + +/*** Common macro for all RTOS OSAL ports ***/ +/* Please make sure that beyond macro value fits your application needs or define the correct value on the compiler + command line! + Note, this value should be equal to `1` only if there are parallel neural network (aka NN) execution + threads in your application. */ +#ifndef APP_HAS_PARALLEL_NETWORKS +#define APP_HAS_PARALLEL_NETWORKS 1 // there are parallel networks in the application +#warning Using default value `1` for macro `APP_HAS_PARALLEL_NETWORKS`. +#endif // APP_HAS_PARALLEL_NETWORKS + +/*** FreeRTOS includes ***/ +#include "FreeRTOS.h" + +#include "semphr.h" +#include "task.h" + +/*** `LL_ATON` includes */ +#include "ll_aton_attributes.h" +#include "ll_aton_osal.h" +#include "ll_aton_platform.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /* API functions*/ + void aton_osal_freertos_init(void); + void aton_osal_freertos_deinit(void); + + void aton_osal_freertos_wfe(void); + void aton_osal_freertos_signal_event(void); + + void aton_osal_freertos_dao_lock(void); + void aton_osal_freertos_dao_unlock(void); + + void aton_osal_freertos_lock(void); + void aton_osal_freertos_unlock(void); + +/*** FreeRTOS dependent type macros ***/ +#define _DaoMutexNoWaitersType_ SemaphoreHandle_t +#define _DaoWaitQueueType_ SemaphoreHandle_t +#define _DaoWaitQueueValueType_ UBaseType_t +#define _WfeSemaphoreType_ SemaphoreHandle_t +#define _CacheMutexType_ SemaphoreHandle_t +#define _TaskHandleType_ TaskHandle_t +#define _PriorityType_ UBaseType_t +#define _ReturnType_ BaseType_t + +/*** FreeRTOS dependent values ***/ +#define _OsTrue_ pdTRUE +#define _NullHandle_ NULL + + /*** Helper inline functions ***/ + static inline _ReturnType_ _my_xSemaphoreCreateBinaryStatic(SemaphoreHandle_t *dao_addr, + StaticSemaphore_t *static_buffer) + { + SemaphoreHandle_t ret = xSemaphoreCreateBinaryStatic(static_buffer); + if (ret != _NullHandle_) + { + *dao_addr = ret; + return _OsTrue_; + } + else + { + return pdFALSE; + } + } + + static inline _ReturnType_ _my_xSemaphoreCreateCountingStatic(SemaphoreHandle_t *dao_addr, + StaticSemaphore_t *static_buffer) + { + SemaphoreHandle_t ret = xSemaphoreCreateCountingStatic(0xFFFFFFFF, 0, static_buffer); + if (ret != _NullHandle_) + { + *dao_addr = ret; + return _OsTrue_; + } + else + { + return pdFALSE; + } + } + + static inline _ReturnType_ _my_xSemaphoreCreateMutexStatic(SemaphoreHandle_t *dao_addr, + StaticSemaphore_t *static_buffer) + { + SemaphoreHandle_t ret = xSemaphoreCreateMutexStatic(static_buffer); + if (ret != _NullHandle_) + { + *dao_addr = ret; + return _OsTrue_; + } + else + { + return pdFALSE; + } + } + +/*** FreeRTOS function macros ***/ +#define _CreateDaoMutexNoWaiters_(_dao_obj, _dao_static_buffer) \ + _my_xSemaphoreCreateBinaryStatic(&(_dao_obj), &(_dao_static_buffer)) +#define _CreateDaoWaitQueue_(_dao_obj, _dao_static_buffer) \ + _my_xSemaphoreCreateBinaryStatic(&(_dao_obj), &(_dao_static_buffer)) +#define _CreateWfeSemaphore_(_dao_obj, _dao_static_buffer) \ + _my_xSemaphoreCreateCountingStatic(&(_dao_obj), &(_dao_static_buffer)) +#define _CreateCacheMutex_(_dao_obj, _dao_static_buffer) \ + _my_xSemaphoreCreateMutexStatic(&(_dao_obj), &(_dao_static_buffer)) + +#define _FinalizeIRQHandling_() \ + LL_ATON_OSAL_SET_PRIORITY( \ + ATON_STD_IRQ_LINE, \ + configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); // must use `configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY` as we + // use `NVIC_SetPriority()` + +#define _DisablePreemption_() vTaskSuspendAll() +#define _EnablePreemption_() xTaskResumeAll() + +#define _InitNonDao_() /* nothing to do */ +#define _DeInitNonDao_() /* nothing to do */ + +#define _GetCurrentTaskHandle_() xTaskGetCurrentTaskHandle() +#define _GetTaskPriority_(_task) uxTaskPriorityGet(_task) +#define _SetTaskPriority_(_task, _prio) vTaskPrioritySet(_task, _prio) +#define _YieldCurrentTask_() taskYIELD() + +#define _MakeDaoMutexNoWaitersAvailable_(_mutex) xSemaphoreGive(_mutex) +#define _GetDaoMutexNoWaiters_(_mutex) xSemaphoreTake((_mutex), 0) +#define _ReleaseDaoMutexNoWaiters_(_mutex) xSemaphoreGive(_mutex) + +#define _MakeDaoWaitQueueUnavailable_(_wq) +#define _GetDaoWaitQueueValue_(_wq) uxSemaphoreGetCount(_wq) +#define _GetDaoWaitQueue_(_wq) xSemaphoreTake(_wq, portMAX_DELAY) +#define _ReleaseDaoWaitQueue_(_wq) xSemaphoreGive(_wq) + +#define _MakeWfeSemaphoreUnavailable_(_sem) +#define _GetWfeSemaphore_(_sem) xSemaphoreTake(_sem, portMAX_DELAY) +#define _ReleaseWfeSemaphore_(_sem) xSemaphoreGive(_sem) +#define _ReleaseWfeSemaphoreISR_(_sem, ...) xSemaphoreGiveFromISR(_sem, __VA_ARGS__) + +#define _MakeCacheMutexAvailable_(_mutex) +#define _GetCacheMutex_(_mutex) xSemaphoreTake(_mutex, portMAX_DELAY) +#define _ReleaseCacheMutex_(_mutex) xSemaphoreGive(_mutex) + +#define _HeadIsrCode_(...) +#define _TailIsrCode_(...) portYIELD_FROM_ISR(__VA_ARGS__) + +#define _FirstPrioHigherThanScnd_(_first, _second) ((_first) > (_second)) // smaller numbers mean lower priority + +#ifdef __cplusplus +} +#endif + +#endif //__LL_ATON_OSAL_FREERTOS_H diff --git a/lib/stai/libstai/include/ll_aton_osal_threadx.h b/lib/stai/libstai/include/ll_aton_osal_threadx.h new file mode 100644 index 000000000..c99e83b12 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_osal_threadx.h @@ -0,0 +1,255 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_threadx.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface to ThreadX as the underlying OS/platform for ATON + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_OSAL_THREADX_H +#define __LL_ATON_OSAL_THREADX_H + +/*** Common macro for all RTOS OSAL ports ***/ +/* Please make sure that beyond macro value fits your application needs or define the correct value on the compiler + command line! + Note, this value should be equal to `1` only if there are parallel neural network (aka NN) execution + threads in your application. */ +#ifndef APP_HAS_PARALLEL_NETWORKS +#define APP_HAS_PARALLEL_NETWORKS 1 // there are parallel networks in the application +#warning Using default value `1` for macro `APP_HAS_PARALLEL_NETWORKS`. +#endif // APP_HAS_PARALLEL_NETWORKS + +/*** ThreadX includes ***/ +#include "tx_api.h" +#include "tx_thread.h" + +/*** `LL_ATON` includes */ +#include "ll_aton_attributes.h" +#include "ll_aton_osal.h" +#include "ll_aton_platform.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /* API functions*/ + void aton_osal_threadx_init(void); + void aton_osal_threadx_deinit(void); + + void aton_osal_threadx_wfe(void); + void aton_osal_threadx_signal_event(void); + + void aton_osal_threadx_dao_lock(void); + void aton_osal_threadx_dao_unlock(void); + + void aton_osal_threadx_lock(void); + void aton_osal_threadx_unlock(void); + +#ifdef NDEBUG +#define SUCCESS_ASSERT(ret) LL_ATON_LIB_UNUSED(ret) +#else +#define SUCCESS_ASSERT(ret) assert((ret) == TX_SUCCESS) +#endif + +/*** ThreadX dependent type macros ***/ +#define _DaoMutexNoWaitersType_ TX_MUTEX +#define _DaoWaitQueueType_ TX_SEMAPHORE +#define _DaoWaitQueueValueType_ ULONG +#define _WfeSemaphoreType_ TX_SEMAPHORE +#define _CacheMutexType_ TX_MUTEX +#define _TaskHandleType_ TX_THREAD * +#define _PriorityType_ UINT +#define _ReturnType_ UINT + +/*** ThreadX dependent values ***/ +#define _OsTrue_ TX_SUCCESS +#define _NullHandle_ TX_NULL + + /*** Helper inline functions ***/ + /** + * @brief Disable preemption + * @note Unfortunately, ThreadX does not provide a direct API to enable/disable preemption + * and therefore we're forced to dive straight into the bowels of the kernel + */ + static inline void _my_disable_preemption(void) + { + TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts */ + TX_DISABLE + /* increment global ThreadX preemption counter */ + _tx_thread_preempt_disable++; + /* Restore interrupts */ + TX_RESTORE + } + + /** + * @brief Enable preemption + * @note Unfortunately, ThreadX does not provide a direct API to enable/disable preemption + * and therefore we're forced to dive straight into the bowels of the kernel + */ + static inline void _my_enable_preemption(void) + { + TX_INTERRUPT_SAVE_AREA + assert(_tx_thread_preempt_disable > 0); + + /* Disable interrupts */ + TX_DISABLE + /* decrement global ThreadX preemption counter */ + _tx_thread_preempt_disable--; + /* Restore interrupts */ + TX_RESTORE + + /* Check for preemption */ + _tx_thread_system_preempt_check(); + } + + static inline void _my_threadx_deinit(TX_MUTEX *_dao_mutex, TX_SEMAPHORE *_dao_wait_queue, TX_SEMAPHORE *_wfe_sem, + TX_MUTEX *_cache_mutex) // de-initialize ThreadX OSAL implementation + { + UINT ret; + + /* delete DAO mutex with no waiters */ + ret = tx_mutex_delete(_dao_mutex); + SUCCESS_ASSERT(ret); + + /* delete DAO wait queue */ + ret = tx_semaphore_delete(_dao_wait_queue); + SUCCESS_ASSERT(ret); + + /* delete WFE semaphore */ + ret = tx_semaphore_delete(_wfe_sem); + SUCCESS_ASSERT(ret); + + /* delete cache mutex */ + ret = tx_mutex_delete(_cache_mutex); + SUCCESS_ASSERT(ret); + } + + static inline UINT _my_tx_thread_priority_get(TX_THREAD *thread_ptr) + { + UINT priority; + UINT ret = tx_thread_info_get(thread_ptr, TX_NULL, TX_NULL, TX_NULL, &priority, TX_NULL, TX_NULL, TX_NULL, TX_NULL); + SUCCESS_ASSERT(ret); + return priority; + } + + static inline void _my_tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority) + { + UINT ret; + UINT old_priority; + + ret = tx_thread_priority_change(thread_ptr, new_priority, + /* may not be `NULL` */ &old_priority); // changes also preemption threshold + SUCCESS_ASSERT(ret); + } + + static inline ULONG _my_tx_get_count(TX_SEMAPHORE *sem) + { + ULONG current_value; + UINT ret = tx_semaphore_info_get(sem, TX_NULL, ¤t_value, TX_NULL, TX_NULL, TX_NULL); + SUCCESS_ASSERT(ret); + return current_value; + } + + static inline UINT _my_tx_mutex_put_prioritized(TX_MUTEX *mutex) + { + UINT ret = tx_mutex_prioritize(mutex); // need to wake up highest priority thread + SUCCESS_ASSERT(ret); + + ret = tx_mutex_put(mutex); + + return ret; + } + + static inline UINT _my_tx_semaphore_put_prioritized(TX_SEMAPHORE *sem) + { + UINT ret = tx_semaphore_prioritize(sem); // need to wake up highest priority thread + SUCCESS_ASSERT(ret); + + ret = tx_semaphore_put(sem); + + return ret; + } + + static inline UINT _my_tx_semaphore_put_isr_non_prioritized(TX_SEMAPHORE *sem) + { + UINT ret; + + // Save the interrupt context + TX_INTERRUPT_SAVE_AREA + + // Disable interrupts + TX_DISABLE + + // Give the semaphore + ret = tx_semaphore_put(sem); + + // Restore interrupts + TX_RESTORE + + return ret; + } + +/*** ThreadX function macros ***/ +#define _CreateDaoMutexNoWaiters_(_dao_obj, _dao_static_buffer) tx_mutex_create(&(_dao_obj), TX_NULL, TX_NO_INHERIT) +#define _CreateDaoWaitQueue_(_dao_obj, _dao_static_buffer) tx_semaphore_create(&(_dao_obj), TX_NULL, 0) +#define _CreateWfeSemaphore_(_dao_obj, _dao_static_buffer) tx_semaphore_create(&(_dao_obj), TX_NULL, 0) +#define _CreateCacheMutex_(_dao_obj, _dao_static_buffer) tx_mutex_create(&(_dao_obj), TX_NULL, TX_INHERIT) + +#define _FinalizeIRQHandling_() /* using default IRQ priority */ + +#define _DisablePreemption_() _my_disable_preemption() +#define _EnablePreemption_() _my_enable_preemption() + +#define _InitNonDao_() /* nothing to do */ +#define _DeInitNonDao_() _my_threadx_deinit(&_dao_mutex, &_dao_wait_queue, &_wfe_sem, &_cache_mutex) + +#define _GetCurrentTaskHandle_() tx_thread_identify() +#define _GetTaskPriority_(_task) _my_tx_thread_priority_get(_task) +#define _SetTaskPriority_(_task, _prio) _my_tx_thread_priority_change(_task, _prio) +#define _YieldCurrentTask_() tx_thread_relinquish() + +#define _MakeDaoMutexNoWaitersAvailable_(_mutex) +#define _GetDaoMutexNoWaiters_(_mutex) tx_mutex_get(&(_mutex), TX_NO_WAIT) // no waiters +#define _ReleaseDaoMutexNoWaiters_(_mutex) \ + tx_mutex_put(&(_mutex)) // no prioritization necessary as there are no waiters + +#define _MakeDaoWaitQueueUnavailable_(_wq) +#define _GetDaoWaitQueueValue_(_wq) _my_tx_get_count(&(_wq)) +#define _GetDaoWaitQueue_(_wq) tx_semaphore_get(&(_wq), TX_WAIT_FOREVER) +#define _ReleaseDaoWaitQueue_(_wq) _my_tx_semaphore_put_prioritized(&(_wq)) + +#define _MakeWfeSemaphoreUnavailable_(_sem) +#define _GetWfeSemaphore_(_sem) tx_semaphore_get(&(_sem), TX_WAIT_FOREVER) +#define _ReleaseWfeSemaphore_(_sem) \ + tx_semaphore_put(&(_sem)) // only the ATON IP owner may wait on this semaphore (i.e. no prioritization necessary) +#define _ReleaseWfeSemaphoreISR_(_sem, ...) \ + _my_tx_semaphore_put_isr_non_prioritized( \ + &(_sem)) // only the ATON IP owner may wait on this semaphore (i.e. no prioritization necessary) + +#define _MakeCacheMutexAvailable_(_mutex) +#define _GetCacheMutex_(_mutex) tx_mutex_get(&(_mutex), TX_WAIT_FOREVER) +#define _ReleaseCacheMutex_(_mutex) _my_tx_mutex_put_prioritized(&(_mutex)) + +#define _HeadIsrCode_(...) +#define _TailIsrCode_(...) + +#define _FirstPrioHigherThanScnd_(_first, _second) ((_first) < (_second)) // smaller numbers mean higher priority + +#ifdef __cplusplus +} +#endif + +#endif //__LL_ATON_OSAL_THREADX_H diff --git a/lib/stai/libstai/include/ll_aton_osal_zephyr.h b/lib/stai/libstai/include/ll_aton_osal_zephyr.h new file mode 100644 index 000000000..131aa6abc --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_osal_zephyr.h @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_zephyr.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface to Zephyr as the underlying OS/platform for ATON + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_OSAL_ZEPHYR_H +#define __LL_ATON_OSAL_ZEPHYR_H + +/*** Common macro for all RTOS OSAL ports ***/ +/* Please make sure that beyond macro value fits your application needs or define the correct value on the compiler + command line! + Note, this value should be equal to `1` only if there are parallel neural network (aka NN) execution + threads in your application. */ +#ifndef APP_HAS_PARALLEL_NETWORKS +#define APP_HAS_PARALLEL_NETWORKS 1 // there are parallel networks in the application +#warning Using default value `1` for macro `APP_HAS_PARALLEL_NETWORKS`. +#endif // APP_HAS_PARALLEL_NETWORKS + +/*** Zephyr includes ***/ +#include +#include + +/*** `LL_ATON` includes */ +#include "ll_aton_attributes.h" +#include "ll_aton_osal.h" +#include "ll_aton_platform.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /* API functions*/ + void aton_osal_zephyr_init(void); + void aton_osal_zephyr_deinit(void); + + void aton_osal_zephyr_wfe(void); + void aton_osal_zephyr_signal_event(void); + + void aton_osal_zephyr_dao_lock(void); + void aton_osal_zephyr_dao_unlock(void); + + void aton_osal_zephyr_lock(void); + void aton_osal_zephyr_unlock(void); + + void aton_osal_zephyr_install_irq(int irq_aton_line_nr, void (*handler)(void)); + void aton_osal_zephyr_uninstall_irq(int irq_aton_line_nr); + + void aton_osal_zephyr_enable_irq(int irq_aton_line_nr); + void aton_osal_zephyr_disable_irq(int irq_aton_line_nr); + + void aton_osal_zephyr_enter_cs(void); + void aton_osal_zephyr_exit_cs(void); + +/*** Zephyr dependent type macros ***/ +#define _DaoMutexNoWaitersType_ struct k_mutex +#define _DaoWaitQueueType_ struct k_sem +#define _DaoWaitQueueValueType_ unsigned int +#define _WfeSemaphoreType_ struct k_sem +#define _CacheMutexType_ struct k_mutex +#define _TaskHandleType_ k_tid_t +#define _PriorityType_ int +#define _ReturnType_ int + +/*** Zephyr dependent values ***/ +#define _OsTrue_ 0 +#define _NullHandle_ NULL + + /*** Helper inline functions ***/ + static inline int _my_zephyr_mutex_create(struct k_mutex *dao_addr) + { + k_mutex_init(dao_addr); // mutex afterwards is available + return 0; + } + + static inline int _my_zephyr_binary_semaphore_create(struct k_sem *dao_addr) + { + k_sem_init(dao_addr, 0, 1); // initial count is 0 (i.e. unavailable), max count is 1 + return 0; + } + + static inline int _my_zephyr_counting_semaphore_create(struct k_sem *dao_addr) + { + k_sem_init(dao_addr, 0, UINT_MAX); // initial count is 0 (i.e. unavailable), max count is `UINT_MAX` + return 0; + } + + static inline int _my_sem_give(struct k_sem *sem) + { + k_sem_give(sem); + return 0; + } + +/*** Zephyr function macros ***/ +#define _CreateDaoMutexNoWaiters_(_dao_obj, _dao_static_buffer) _my_zephyr_mutex_create(&(_dao_obj)) +#define _CreateDaoWaitQueue_(_dao_obj, _dao_static_buffer) _my_zephyr_binary_semaphore_create(&(_dao_obj)) +#define _CreateWfeSemaphore_(_dao_obj, _dao_static_buffer) _my_zephyr_counting_semaphore_create(&(_dao_obj)) +#define _CreateCacheMutex_(_dao_obj, _dao_static_buffer) _my_zephyr_mutex_create(&(_dao_obj)) + +#define _FinalizeIRQHandling_() /* using default IRQ priority */ + +#define _DisablePreemption_() k_sched_lock() +#define _EnablePreemption_() k_sched_unlock() + +#define _InitNonDao_() /* nothing to do */ +#define _DeInitNonDao_() /* nothing to do */ + +#define _GetCurrentTaskHandle_() k_current_get() +#define _GetTaskPriority_(_task) k_thread_priority_get(_task) +#define _SetTaskPriority_(_task, _prio) k_thread_priority_set(_task, _prio) +#define _YieldCurrentTask_() k_yield() + +#define _MakeDaoMutexNoWaitersAvailable_(_mutex) +#define _GetDaoMutexNoWaiters_(_mutex) k_mutex_lock(&(_mutex), K_NO_WAIT) // no waiters +#define _ReleaseDaoMutexNoWaiters_(_mutex) k_mutex_unlock(&(_mutex)) + +#define _MakeDaoWaitQueueUnavailable_(_wq) +#define _GetDaoWaitQueueValue_(_wq) k_sem_count_get(&(_wq)) +#define _GetDaoWaitQueue_(_wq) k_sem_take(&(_wq), K_FOREVER) +#define _ReleaseDaoWaitQueue_(_wq) _my_sem_give(&(_wq)) + +#define _MakeWfeSemaphoreUnavailable_(_sem) +#define _GetWfeSemaphore_(_sem) k_sem_take(&(_sem), K_FOREVER) +#define _ReleaseWfeSemaphore_(_sem) _my_sem_give(&(_sem)) +#define _ReleaseWfeSemaphoreISR_(_sem, ...) _my_sem_give(&(_sem)) + +#define _MakeCacheMutexAvailable_(_mutex) +#define _GetCacheMutex_(_mutex) k_mutex_lock(&(_mutex), K_FOREVER) +#define _ReleaseCacheMutex_(_mutex) k_mutex_unlock(&(_mutex)) + +#define _HeadIsrCode_(...) +#define _TailIsrCode_(...) + +#define _FirstPrioHigherThanScnd_(_first, _second) \ + ((_first) < (_second)) // in Zephyr, lower numerical values represent higher priorities. + +#ifdef __cplusplus +} +#endif + +#endif //__LL_ATON_OSAL_ZEPHYR_H diff --git a/lib/stai/libstai/include/ll_aton_platform.h b/lib/stai/libstai/include/ll_aton_platform.h new file mode 100644 index 000000000..7821bb0d5 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_platform.h @@ -0,0 +1,494 @@ +/** + ****************************************************************************** + * @file ll_aton_platform.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file for defining platform dependencies + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_PLATFORM_H +#define __LL_ATON_PLATFORM_H + +#include + +#include "ll_aton_config.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Default timeout is 10s, but can be overridden */ +#ifndef ATON_EPOCH_TIMEOUT_MS +#define ATON_EPOCH_TIMEOUT_MS 10000 +#endif + +/*** Platform dependent definitions & includes ***/ + +/* Bare metal Cortex-M NCSIM simulator platform*/ +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_NCSIM) +#define ATON_PLAT_HAS_FFLUSH (0) +#define ATON_BASE 0xA0000000 +#define SYSMEM1_BASE 0xA0080000 +#define SYSMEM2_BASE 0xA00A0000 +#define SYSMEM3_BASE 0xA00C0000 +#define SYSMEM4_BASE 0xA00E0000 +#define SYSMEM_LENGTH 0x00020000 +#define DUMMY_MEM_BASE 0x40000000 +#define DUMP_CONFIG_BASE_ADDR 0xA0108000 +#define CDMA_BASE_ADDR 0xA0100000 +#define OSPI2_BASE_ADDR 0x3D710000 +#define OSPI1_BASE_ADDR 0x3D700000 +#define OSPIIOM_BASE_ADDR 0x3D720000 +#define OSPI_HSEL_SEL 0x3D83100C +#define OSPI1_MEM 0x60000000 +#define OSPI2_MEM 0x80000000 +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) +#include "cm4ikmcu.h" + +/* Neuromem simulation environment */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_NEUROMEM_SIM) +#define ATON_PLAT_HAS_FFLUSH (0) +#define ATON_BASE 0xA0000000 +#define SYSMEM1_BASE 0xA0080000 +#define SYSMEM2_BASE 0xA00A0000 +#define SYSMEM3_BASE 0xA00C0000 +#define SYSMEM4_BASE 0xA00E0000 +#define SYSMEM_LENGTH 0x00020000 +#define DUMP_CONFIG_BASE_ADDR 0x3D807c00 +#define CDMA_BASE_ADDR 0xA0100000 +#define OSPI2_BASE_ADDR 0xA0150000 +#define OSPI1_BASE_ADDR 0xA0160000 +#define OSPI1_MEM 0x00000000 +#define OSPI2_MEM 0x80000000 +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +#define ATON_INT_NR (2 * 6 + 2 + 2) // 6 streng, 6 streng err, 2 convacc, 2 busif + +/* These macros are not available in Neuromem ATON.h so define them here */ +#define ATON_STRENG_INT_MASK(A, B, C) (0x003f) +#define ATON_STRENG_ERR_INT_MASK(A, B, C) (0x0fc0) +#define ATON_CONVACC_INT_MASK(A, B, C) (0x3000) +#define ATON_BUSIF_INT_MASK(A, B, C) (0xc000) + +#ifndef ATON_STRENG_NUM +#define ATON_STRENG_NUM 6 +#define ATON_CONVACC_NUM 2 +#define ATON_DECUN_NUM 1 +#define ATON_ACTIV_NUM 1 +#define ATON_ARITH_NUM 1 +#define ATON_POOL_NUM 1 +#define ATON_BUSIF_NUM 2 +#endif + +#ifndef ATON_STRENG_CTRL_DT +#define ATON_STRENG_CTRL_DT ATON_STRENG_CTRL_RESET +#endif +#ifndef ATON_DECUN_CTRL_DT +#define ATON_DECUN_CTRL_DT ATON_DECUN_CTRL_RESET +#endif +#ifndef ATON_CONVACC_CTRL_DT +#define ATON_CONVACC_CTRL_DT ATON_CONVACC_CTRL_RESET +#endif +#ifndef ATON_ACTIV_CTRL_DT +#define ATON_ACTIV_CTRL_DT ATON_ACTIV_CTRL_RESET +#endif +#ifndef ATON_ARITH_CTRL_DT +#define ATON_ARITH_CTRL_DT ATON_ARITH_CTRL_RESET +#endif +#ifndef ATON_POOL_CTRL_DT +#define ATON_POOL_CTRL_DT ATON_POOL_CTRL_RESET +#endif +#ifndef ATON_ACTIV_FUNC_DT +#define ATON_ACTIV_FUNC_DT ATON_ACTIV_FUNC_RESET +#endif +#ifndef ATON_ACTIV_ACTIVPARAM_DT +#define ATON_ACTIV_ACTIVPARAM_DT ATON_ACTIV_ACTIVPARAM_RESET +#endif +#ifndef ATON_ACTIV_ACTIVPARAM2_DT +#define ATON_ACTIV_ACTIVPARAM2_DT ATON_ACTIV_ACTIVPARAM2_RESET +#endif + +#include "cm4ikmcu.h" + +/* Imaging simulation environment */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_IMAGING_SIM) +#define ATON_PLAT_HAS_FFLUSH (0) +#define ATON_BASE 0xA0000000 +#define SYSMEM1_BASE 0xB0000000 +#define SYSMEM2_BASE 0xB0040000 +#define SYSMEM3_BASE 0xB0080000 +#define SYSMEM_LENGTH 0x00040000 +#define DUMMY_MEM_BASE 0x40000000 +#define DUMP_CONFIG_BASE_ADDR 0xA0108000 +#define CDMA_BASE_ADDR 0xA0100000 +#define OSPI2_BASE_ADDR 0x3D710000 +#define OSPI1_BASE_ADDR 0x3D700000 +#define OSPIIOM_BASE_ADDR 0x3D720000 +#define OSPI_HSEL_SEL 0x3D83100C +#define OSPI1_MEM 0x60000000 +#define OSPI2_MEM 0x80000000 +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) +#include "cm4ikmcu.h" + +#define ATON_STRENG_CID_CACHE_SET_ALLOC(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_CACHEABLE(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_CID(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_LINESIZE(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_PFETCH(a, b) 0 + +/* Bare metal Cortex-M STICE4 FPGA platform */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STICE4) +#define ATON_PLAT_HAS_FFLUSH (1) +#define ATON_BASE 0x51100000 + +typedef int32_t IRQn_Type; + +#include "stm32h7_map.h" + +#include + +#define CDNN0_IRQn (123) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +/* Linux based Xilinx ZC706 FPGA platform */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_ZC706) || (LL_ATON_PLATFORM == LL_ATON_PLAT_IWAVE) || \ + (LL_ATON_PLATFORM == LL_ATON_PLAT_BITTWARE) +#define ATON_PLAT_HAS_FFLUSH (1) +extern uint8_t *get_zynq_aton_base(void); +#define NVIC_EnableIRQ(x) +#define NVIC_DisableIRQ(x) +#define ATON_BASE (get_zynq_aton_base()) +/* Timer clock is 100MHz. Compute timeout accordingly. */ +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 100 * 1000) + +/* PC based Orlando Simulator platform */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_SWEMUL) +#define ATON_PLAT_HAS_FFLUSH (1) + +#define __WFE() +#define NVIC_EnableIRQ(x) +#define NVIC_DisableIRQ(x) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +/* Bare metal Cortex-M TLM simulator platform as used by MCD */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_TLM_MCD) +#define ATON_PLAT_HAS_FFLUSH (1) + +#include "cnn1_top_mapping.h" + +#define ATON_BASE CNN1_TOP_BASEADDR +#define SYSMEM1_BASE AXI_MEM0 +#define SYSMEM2_BASE AXI_MEM1 +#define SYSMEM3_BASE AXI_MEM2 +#define SYSMEM4_BASE AXI_MEM3 +#define SYSMEM_LENGTH 0x00020000 +#define DUMMY_MEM_BASE AXI_FLASH +#define DUMP_CONFIG_BASE_ADDR ATON_BASE + 0x108000 +#define CDMA_BASE_ADDR ATON_BASE + 0x100000 + +#define __WFE() esw_sleep() +#define __DSB() +#define NVIC_EnableIRQ(x) +#define NVIC_DisableIRQ(x) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +/* PC based Test Explorer application platform */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_TSTXPL) +#define ATON_PLAT_HAS_FFLUSH (1) + +#define __WFE() (complete_dmas()) +#define __DSB() +#define NVIC_EnableIRQ(x) +#define NVIC_DisableIRQ(x) +uintptr_t get_aton_base(void); +void complete_dmas(void); +#define ATON_BASE (get_aton_base()) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) +#include "ll_aton_ec_trace.h" + +#define ATON_PLAT_HAS_FFLUSH (1) + +#define ATON_BASE (get_ec_aton_base()) + +#define __WFE() +#define __DSB() +#define NVIC_EnableIRQ(x) +#define NVIC_DisableIRQ(x) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +#define ATON_REG_WRITE_RELOC(regaddr, base, offset) \ + ec_trace_write_reloc((uintptr_t)regaddr, (uint32_t)base, (uint32_t)offset) +#define ATON_REG_WRITE(regaddr, val) ec_trace_write((uintptr_t)regaddr, (uint32_t)val) +#define ATON_REG_WRITE_FIELD_RANGE(unitname, id, reg, start, fsize, val) \ + ec_trace_reg_writefield(ec_trace_get_IP_id(ATON_##unitname##_BASE(id)), \ + ec_trace_get_REG_id(ATON_##unitname##_##reg##_OFFSET), start, fsize, val) +#define ATON_REG_WRITE_FIELD(unitname, id, reg, field, val) \ + ATON_REG_WRITE_FIELD_RANGE(unitname, id, reg, ATON_##unitname##_##reg##_##field##_LSB, \ + ATON_##unitname##_##reg##_##field##_W, val) +#define ATON_REG_POLL(unitname, id, reg, field, val) \ + ec_trace_reg_poll(ec_trace_get_IP_id(ATON_##unitname##_BASE(id)), \ + ec_trace_get_REG_id(ATON_##unitname##_##reg##_OFFSET), ATON_##unitname##_##reg##_##field##_LSB, \ + ATON_##unitname##_##reg##_##field##_W, (uint32_t)val) + +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_CENTAURI) +#define ATON_BASE 0xA0000000 +#define SYSMEM1_BASE 0xA0080000 +#define SYSMEM2_BASE 0xA00A0000 +#define SYSMEM3_BASE 0xA00C0000 +#define SYSMEM4_BASE 0xA00E0000 +#define SYSMEM_LENGTH 0x00020000 +#define DUMMY_MEM_BASE 0x40000000 +#define DUMP_CONFIG_BASE_ADDR 0xA0108000 +#define CDMA_BASE_ADDR 0xA0100000 +#define OSPI2_BASE_ADDR 0x3D710000 +#define OSPI1_BASE_ADDR 0x3D700000 +#define OSPIIOM_BASE_ADDR 0x3D720000 +#define OSPI_HSEL_SEL 0x3D83100C +#define OSPI1_MEM 0x60000000 +#define OSPI2_MEM 0x80000000 +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +//#define ATON_INT_NR (2 * 16 + 6 + 4) /* 16 streng, 6 convacc, 4 busif */ +#define ATON_INT_NR 32 //>32 not supported yet +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) +#error Only supported `LL_ATON_RT_MODE==LL_ATON_RT_POLLING` +#endif +#include "cm4ikmcu.h" + +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_N64) +#define ATON_PLAT_HAS_FFLUSH (1) +#define ATON_BASE 0x3d83d000 +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) +#define ATON_STRENG_CID_CACHE_SET_ALLOC(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_CACHEABLE(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_CID(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_LINESIZE(a, b) 0 +#define ATON_STRENG_CID_CACHE_SET_PFETCH(a, b) 0 + +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STM32N6) +// Cache maintenance +#include "mcu_cache.h" +#include "npu_cache.h" + +#include "stm32n6xx.h" + +#define ATON_N6_DRIVERS_v0200 \ + ((0x0 << 24U) | /* MAIN */ \ + (0x2 << 16) | /* SUB1 */ \ + (0x0 << 8) | /* SUB2 */ \ + (0x0) /* RC */ \ + ) +#define ATON_GET_VERSION_RC(x) ((x)&0xFF) +#define ATON_GET_VERSION_FIRST_THREE(x) ((x) >> 8) +#define ATON_IS_AT_LEAST_VERSION(x, v) \ + (((ATON_GET_VERSION_RC(x) == 0x0) && (ATON_GET_VERSION_FIRST_THREE(x) >= ATON_GET_VERSION_FIRST_THREE(v))) || \ + (((ATON_GET_VERSION_RC(x) != 0x0) && (ATON_GET_VERSION_RC(v) == 0x0)) && \ + (ATON_GET_VERSION_FIRST_THREE(x) > ATON_GET_VERSION_FIRST_THREE(v))) || \ + (((ATON_GET_VERSION_RC(x) != 0x0) && (ATON_GET_VERSION_RC(v) != 0x0)) && ((x) >= (v)))) + +#if !ATON_IS_AT_LEAST_VERSION(__STM32N6xx_HAL_VERSION, ATON_N6_DRIVERS_v0200) +#define CDNN0_IRQHandler NPU_END_OF_EPOCH_IRQHandler +#define CDNN1_IRQHandler NPU_INT1_IRQHandler +#define CDNN2_IRQHandler NPU_INT2_IRQHandler +#define CDNN3_IRQHandler NPU_INT3_IRQHandler + +#define CDNN0_IRQn NPU_END_OF_EPOCH_IRQn +#define CDNN1_IRQn NPU_INT1_IRQn +#define CDNN2_IRQn NPU_INT2_IRQn +#define CDNN3_IRQn NPU_INT3_IRQn +#else // ATON_IS_AT_LEAST_VERSION +#define CDNN0_IRQHandler NPU0_IRQHandler +#define CDNN1_IRQHandler NPU1_IRQHandler +#define CDNN2_IRQHandler NPU2_IRQHandler +#define CDNN3_IRQHandler NPU3_IRQHandler + +#define CDNN0_IRQn NPU0_IRQn +#define CDNN1_IRQn NPU1_IRQn +#define CDNN2_IRQn NPU2_IRQn +#define CDNN3_IRQn NPU3_IRQn +#endif // ATON_IS_AT_LEAST_VERSION + +#define ATON_PLAT_HAS_FFLUSH (0) +#if defined(CPU_IN_SECURE_STATE) +#define ATON_BASE NPU_BASE_S +#else +#define ATON_BASE NPU_BASE_NS +#endif +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STM32H7P) +/* Cache maintenance */ +//#include "mcu_cache.h" /* TODO */ +//#include "npu_cache.h" /* TODO */ +#include "stm32h7p4xx.h" + +#define CDNN0_IRQHandler NPU_IT0_IRQHandler +#define CDNN1_IRQHandler NPU_IT1_IRQHandler +#define CDNN2_IRQHandler NPU_IT2_IRQHandler +#define CDNN3_IRQHandler NPU_IT2_IRQHandler /* Only three interrupts here */ + +#define CDNN0_IRQn NPU_IT0_IRQn +#define CDNN1_IRQn NPU_IT1_IRQn +#define CDNN2_IRQn NPU_IT2_IRQn +#define CDNN3_IRQn NPU_IT2_IRQn +#define ATON_BASE 0x520E0000 /* Not yet defined in HAL */ + +#define ATON_PLAT_HAS_FFLUSH (0) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +/* Stellar P3 support: TODO when information is available */ +#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STELLARP3) +/* Cache maintenance */ +//#include "mcu_cache.h" /* TODO */ +//#include "npu_cache.h" /* TODO */ +//#include "stellarp3.h" + +#define CDNN0_IRQHandler NPU_IT0_IRQHandler +#define CDNN1_IRQHandler NPU_IT1_IRQHandler +#define CDNN2_IRQHandler NPU_IT2_IRQHandler +#define CDNN3_IRQHandler NPU_IT3_IRQHandler + +#define CDNN0_IRQn 506 /* To R52 Kite Cluster */ +#define CDNN1_IRQn 507 /* To R52 Kite Cluster */ +#define CDNN2_IRQn 92 /* To Cortex-M4 */ +#define CDNN3_IRQn 93 /* To Cortex-M4 */ +#define ATON_BASE 0x75600000 + +#define ATON_PLAT_HAS_FFLUSH (0) +#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000) + +#else +#error No target platform is specified. Please define macro `LL_ATON_PLATFORM` +#endif + +// may be included just here because of the platform dependent definitions (above all `ATON_BASE`) +#include "ATON.h" +#include "ll_aton_rcompat.h" + +/* Default macro for physical to virtual address translation (direct mapping) */ +#ifndef ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR +#define ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(address) (address) +#endif // !ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR + +/* Default macro for virtual to physical address translation (direct mapping) */ +#ifndef ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR +#define ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(address) (address) +#endif // !ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR + +// converts signed shift (negative value are left shift) to HW encoding Range 39:0. No shift 16 +#ifndef ATON_SHIFT +#define ATON_SHIFT(x) ((x) + 16) +#endif // ATON_SHIFT + +// Generic boilerplate for enabling an ATON unit +#define ATON_ENABLE(unitname, id) ATON_REG_WRITE_FIELD(unitname, id, CTRL, EN, 1) + +// Generic boilerplate for disabling, stopping pending transactions (aka "clearing"), and clearing the configuration of +// an ATON unit +#ifndef ATON_DISABLE_CLR_CONFCLR +#define ATON_DISABLE_CLR_CONFCLR(unitname, id) \ + do \ + { \ + t = ATON_##unitname##_CTRL_DT; \ + t = ATON_##unitname##_CTRL_SET_EN(t, 0); \ + t = ATON_##unitname##_CTRL_SET_CLR(t, 1); \ + ATON_##unitname##_CTRL_SET(id, t); \ + /* wait for unit to terminate clearing of configuration registers */ \ + ATON_REG_POLL(unitname, id, CTRL, CLR, 0); \ + \ + t = ATON_##unitname##_CTRL_DT; \ + t = ATON_##unitname##_CTRL_SET_CONFCLR(t, 1); \ + ATON_##unitname##_CTRL_SET(id, t); \ + /* wait for unit to terminate clearing of configuration registers */ \ + ATON_REG_POLL(unitname, id, CTRL, CONFCLR, 0); \ + } while (0) +#endif // ATON_DISABLE_CLR_CONFCLR + +#ifndef ATON_REG_WRITE_RELOC +#define ATON_REG_WRITE_RELOC(regaddr, base, offset) \ + do \ + { \ + *(volatile uint32_t *)(uintptr_t)(regaddr) = (base) + (offset); \ + } while (0) +#endif // ATON_REG_WRITE_RELOC + +#ifndef ATON_REG_WRITE +#define ATON_REG_WRITE(regaddr, val) \ + do \ + { \ + *(volatile uint32_t *)(uintptr_t)(regaddr) = (val); \ + } while (0) +#endif // ATON_REG_WRITE + +#ifndef ATON_REG_WRITE_FIELD_RANGE +#define ATON_REG_WRITE_FIELD_RANGE(unitname, id, reg, start, fsize, val) \ + do \ + { \ + uint32_t t = ATON_##unitname##_##reg##_GET(id); \ + t = ATON_SET_FIELD(t, start, fsize, val); \ + ATON_##unitname##_##reg##_SET(id, t); \ + } while (0) +#endif // ATON_REG_WRITE_FIELD_RANGE + +#ifndef ATON_REG_WRITE_FIELD +#define ATON_REG_WRITE_FIELD(unitname, id, reg, field, val) \ + do \ + { \ + uint32_t t = ATON_##unitname##_##reg##_GET(id); \ + t = ATON_##unitname##_##reg##_SET_##field(t, val); \ + ATON_##unitname##_##reg##_SET(id, t); \ + } while (0) +#endif // ATON_REG_WRITE_FIELD + +#ifndef ATON_REG_POLL +#define ATON_REG_POLL(unitname, id, reg, field, val) \ + do \ + { \ + while (ATON_##unitname##_##reg##_GET_##field(ATON_##unitname##_##reg##_GET(id)) != val) \ + { \ + } \ + } while (0) +#endif // ATON_REG_POLL + +/* Interrupt line(s) to use */ +/* ATON_STD_IRQ_LINE MUST be within the range of available ATON interrupt lines, i.e. within [0 - 3] */ +#ifndef ATON_STD_IRQ_LINE +#define ATON_STD_IRQ_LINE 0 +#endif + +#if (ATON_STD_IRQ_LINE != 0) && (ATON_STD_IRQ_LINE != 1) && (ATON_STD_IRQ_LINE != 2) && (ATON_STD_IRQ_LINE != 3) +#error invalid interrupt line number `ATON_STD_IRQ_LINE` (must be in range [0 - 3]) +#endif // ATON_STD_IRQ_LINE + +// Beyond macros may be defined just here +#define ATON_STD_IRQHandler LL_ATON_CONCAT3(CDNN, ATON_STD_IRQ_LINE, _IRQHandler) +#define ATON_STD_IRQn LL_ATON_CONCAT3(CDNN, ATON_STD_IRQ_LINE, _IRQn) +#define ATON_STD_INTANDMSK LL_ATON_CONCAT(INTANDMSK, ATON_STD_IRQ_LINE) +#define ATON_STD_INTORMSK LL_ATON_CONCAT(INTORMSK, ATON_STD_IRQ_LINE) +#define ATON_INTCTRL_STD_INTANDMSK_SET(DATA) ATON_INTCTRL_INTANDMSK_SET(0, ATON_STD_IRQ_LINE, DATA) +#define ATON_INTCTRL_STD_INTANDMSK_GET ATON_INTCTRL_INTANDMSK_GET(0, ATON_STD_IRQ_LINE) +#define ATON_INTCTRL_STD_INTORMSK_SET(DATA) ATON_INTCTRL_INTORMSK_SET(0, ATON_STD_IRQ_LINE, DATA) +#define ATON_INTCTRL_STD_INTORMSK_GET ATON_INTCTRL_INTORMSK_GET(0, ATON_STD_IRQ_LINE) +#if (ATON_INT_NR > 32) +#define ATON_INTCTRL_STD_INTORMSK_H_SET(DATA) ATON_INTCTRL_INTORMSK_H_SET(0, ATON_STD_IRQ_LINE, DATA) +#define ATON_INTCTRL_STD_INTANDMSK_H_SET(DATA) ATON_INTCTRL_INTANDMSK_H_SET(0, ATON_STD_IRQ_LINE, DATA) +#endif // (ATON_INT_NR > 32) + +#ifdef __cplusplus +} +#endif + +#endif // __LL_ATON_PLATFORM_H diff --git a/lib/stai/libstai/include/ll_aton_profiler.h b/lib/stai/libstai/include/ll_aton_profiler.h new file mode 100644 index 000000000..8a1b6b0eb --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_profiler.h @@ -0,0 +1,27 @@ +/** + ****************************************************************************** + * @file ll_aton_profiler.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON LL low level lib module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_PROFILER_H +#define __LL_ATON_PROFILER_H + +#include "ll_aton.h" +#include "ll_aton_NN_interface.h" +#include "ll_aton_lib.h" +#include "ll_aton_lib_sw_operators.h" + +#endif \ No newline at end of file diff --git a/lib/stai/libstai/include/ll_aton_rcompat.h b/lib/stai/libstai/include/ll_aton_rcompat.h new file mode 100644 index 000000000..3098d7242 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_rcompat.h @@ -0,0 +1,592 @@ +/** + ****************************************************************************** + * @file ll_aton_rcompat.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Backward compatibility layer for raSTa flow. + * Enables using ATON.h files generated by old regparser. + * Tested with N6 RTL. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_COMPAT_H +#define __LL_ATON_COMPAT_H + +/* Macros not yet defined in ATON.h + * TODO: add them to raSTa generation + */ + +#ifndef ATON_DECUN_MEM_LOW_DT +#define ATON_DECUN_MEM_LOW_IDX_MIN (0) +#define ATON_DECUN_MEM_LOW_IDX_MAX (256 - 1) +#define ATON_DECUN_MEM_LOW_ADDR(UNIT, IDX) (ATON_DECUN_BASE(UNIT) + 0x800 + 8 * (IDX)) +#define ATON_DECUN_MEM_LOW_DT (0) +#define ATON_DECUN_MEM_LOW_SET_MOD8_0(REG, DATA) ATON_SET_FIELD(REG, 0UL, 8UL, DATA) +#define ATON_DECUN_MEM_LOW_SET_MOD8_1(REG, DATA) ATON_SET_FIELD(REG, 8UL, 8UL, DATA) +#define ATON_DECUN_MEM_LOW_SET_MOD8_2(REG, DATA) ATON_SET_FIELD(REG, 16UL, 8UL, DATA) +#define ATON_DECUN_MEM_LOW_SET_MOD8_3(REG, DATA) ATON_SET_FIELD(REG, 24UL, 8UL, DATA) +#define ATON_DECUN_MEM_LOW_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_DECUN_MEM_LOW_ADDR(UNIT, IDX), (DATA)) +#endif + +#ifndef ATON_DECUN_MEM_HIGH_DT +#define ATON_DECUN_MEM_HIGH_IDX_MIN (0) +#define ATON_DECUN_MEM_HIGH_IDX_MAX (256 - 1) +#define ATON_DECUN_MEM_HIGH_ADDR(UNIT, IDX) (ATON_DECUN_BASE(UNIT) + 0x800 + 8 * (IDX) + 4) +#define ATON_DECUN_MEM_HIGH_DT (0) +#define ATON_DECUN_MEM_HIGH_SET_MOD8_0(REG, DATA) ATON_SET_FIELD(REG, 0UL, 8UL, DATA) +#define ATON_DECUN_MEM_HIGH_SET_MOD8_1(REG, DATA) ATON_SET_FIELD(REG, 8UL, 8UL, DATA) +#define ATON_DECUN_MEM_HIGH_SET_MOD8_2(REG, DATA) ATON_SET_FIELD(REG, 16UL, 8UL, DATA) +#define ATON_DECUN_MEM_HIGH_SET_MOD8_3(REG, DATA) ATON_SET_FIELD(REG, 24UL, 8UL, DATA) +#define ATON_DECUN_MEM_HIGH_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_DECUN_MEM_HIGH_ADDR(UNIT, IDX), (DATA)) +#endif + +#ifndef RASTA_SVN_REV + +/** Generic macros + */ +#define ATON_ADDR_SPACE_SIZE ATON_SIZE + +/** Interrupt controller macros + */ +#define ATON_INTCTRL_INTS(UNIT) ATON_INT_NR +#define ATON_STRENG_INT(IDX) ATON_STRENG##IDX##_INT +#define ATON_INTCTRL_INTORMSK_OFFSET(UNIT, IOM) (((IOM) >= 0) && ((IOM) <= 3) ? (0x4 * (IOM) + UINT32_C(0x14)) : 0) +#define ATON_INTCTRL_INTORMSK_ADDR(UNIT, IOM) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK_OFFSET(UNIT, IOM)) +#define ATON_INTCTRL_INTORMSK_GET(UNIT, IOM) ATON_GET_REG32(ATON_INTCTRL_INTORMSK_ADDR(UNIT, IOM)) +#define ATON_INTCTRL_INTORMSK_SET(UNIT, IOM, DATA) \ + do \ + { \ + ATON_SET_REG32(ATON_INTCTRL_INTORMSK_ADDR(UNIT, IOM), DATA); \ + } while (0) +#define ATON_INTCTRL_INTANDMSK_OFFSET(UNIT, IAM) (((IAM) >= 0) && ((IAM) <= 3) ? (0x4 * (IAM) + UINT32_C(0x24)) : 0) +#define ATON_INTCTRL_INTANDMSK_ADDR(UNIT, IAM) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK_OFFSET(UNIT, IAM)) +#define ATON_INTCTRL_INTANDMSK_GET(UNIT, IAM) ATON_GET_REG32(ATON_INTCTRL_INTANDMSK_ADDR(UNIT, IAM)) +#define ATON_INTCTRL_INTANDMSK_SET(UNIT, IAM, DATA) \ + do \ + { \ + ATON_SET_REG32(ATON_INTCTRL_INTANDMSK_ADDR(UNIT, IAM), DATA); \ + } while (0) + +#define ATON_STRENG_INT_MASK(UNIT, INDEX, DATA) ATON_STRENG_INT_GET_MASK(UNIT, DATA) +#define ATON_STRENG_ERR_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_STRENG_ERR_INT_GET_MASK(UNIT, REG_IDX) +#define ATON_STRSWITCH_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_STRSWITCH_INT_GET_MASK(UNIT, REG_IDX) +#define ATON_BUSIF_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_BUSIF_INT_GET_MASK(UNIT, REG_IDX) + +#if (ATON_INT_NR > 32) +#define ATON_INT_GET_MASK(_macro_, _unit_) (_macro_(_unit_, 0, 0) | (((uint64_t)_macro_(_unit_, 1, 0)) << 32)) +#define __ATON_INTCTRL_INTORMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTORMSK_H_SET(IDX, DATA) +#define __ATON_INTCTRL_INTANDMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTANDMSK_H_SET(IDX, DATA) +#else //(ATON_INT_NR <= 32) +#define ATON_INT_GET_MASK(_macro_, _unit_) _macro_(_unit_, 0, 0) +#endif //(ATON_INT_NR <= 32) + +#define ATON_INTCTRL_0_INTSET_STRENG_0_0_IDX ATON_STRENG0_INT +#define ATON_INTCTRL_0_INTSET_STRENG_1_0_IDX ATON_STRENG1_INT +#define ATON_INTCTRL_0_INTSET_STRENG_2_0_IDX ATON_STRENG2_INT +#define ATON_INTCTRL_0_INTSET_STRENG_3_0_IDX ATON_STRENG3_INT +#define ATON_INTCTRL_0_INTSET_STRENG_4_0_IDX ATON_STRENG4_INT +#define ATON_INTCTRL_0_INTSET_STRENG_5_0_IDX ATON_STRENG5_INT +#define ATON_INTCTRL_0_INTSET_STRENG_6_0_IDX ATON_STRENG6_INT +#define ATON_INTCTRL_0_INTSET_STRENG_7_0_IDX ATON_STRENG7_INT +#define ATON_INTCTRL_0_INTSET_STRENG_8_0_IDX ATON_STRENG8_INT +#define ATON_INTCTRL_0_INTSET_STRENG_9_0_IDX ATON_STRENG9_INT +#define ATON_INTCTRL_0_INTSET_STRENG_0_1_IDX ATON_STRENG0_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_1_1_IDX ATON_STRENG1_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_2_1_IDX ATON_STRENG2_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_3_1_IDX ATON_STRENG3_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_4_1_IDX ATON_STRENG4_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_5_1_IDX ATON_STRENG5_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_6_1_IDX ATON_STRENG6_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_7_1_IDX ATON_STRENG7_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_8_1_IDX ATON_STRENG8_ERR_INT +#define ATON_INTCTRL_0_INTSET_STRENG_9_1_IDX ATON_STRENG9_ERR_INT +#define ATON_INTCTRL_0_INTSET_CONVACC_0_IDX ATON_CONVACC0_INT +#define ATON_INTCTRL_0_INTSET_CONVACC_1_IDX ATON_CONVACC1_INT +#define ATON_INTCTRL_0_INTSET_CONVACC_2_IDX ATON_CONVACC2_INT +#define ATON_INTCTRL_0_INTSET_CONVACC_3_IDX ATON_CONVACC3_INT +#define ATON_INTCTRL_0_INTSET_BUSIF_0_IDX ATON_BUSIF0_INT +#define ATON_INTCTRL_0_INTSET_BUSIF_1_IDX ATON_BUSIF1_INT +#define ATON_INTCTRL_0_INTSET_STRSWITCH_0_IDX ATON_STRSWITCH_INT +#define ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_0_IDX ATON_EPOCHCTRL0_INT +#define ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_1_IDX ATON_EPOCHCTRL0_NOACK_INT +#define ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_2_IDX ATON_EPOCHCTRL0_ERR_INT +#define ATON_INTCTRL_0_INTSET_DEBUG_TRACE_0_IDX ATON_DEBUG_TRACE0_INT + +#define ATON_INTCTRL_0_INTCLR_STRENG_0_0_IDX ATON_STRENG0_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_1_0_IDX ATON_STRENG1_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_2_0_IDX ATON_STRENG2_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_3_0_IDX ATON_STRENG3_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_4_0_IDX ATON_STRENG4_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_5_0_IDX ATON_STRENG5_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_6_0_IDX ATON_STRENG6_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_7_0_IDX ATON_STRENG7_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_8_0_IDX ATON_STRENG8_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_9_0_IDX ATON_STRENG9_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_0_1_IDX ATON_STRENG0_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_1_1_IDX ATON_STRENG1_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_2_1_IDX ATON_STRENG2_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_3_1_IDX ATON_STRENG3_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_4_1_IDX ATON_STRENG4_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_5_1_IDX ATON_STRENG5_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_6_1_IDX ATON_STRENG6_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_7_1_IDX ATON_STRENG7_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_8_1_IDX ATON_STRENG8_ERR_INT +#define ATON_INTCTRL_0_INTCLR_STRENG_9_1_IDX ATON_STRENG9_ERR_INT +#define ATON_INTCTRL_0_INTCLR_CONVACC_0_IDX ATON_CONVACC0_INT +#define ATON_INTCTRL_0_INTCLR_CONVACC_1_IDX ATON_CONVACC1_INT +#define ATON_INTCTRL_0_INTCLR_CONVACC_2_IDX ATON_CONVACC2_INT +#define ATON_INTCTRL_0_INTCLR_CONVACC_3_IDX ATON_CONVACC3_INT +#define ATON_INTCTRL_0_INTCLR_BUSIF_0_IDX ATON_BUSIF0_INT +#define ATON_INTCTRL_0_INTCLR_BUSIF_1_IDX ATON_BUSIF1_INT +#define ATON_INTCTRL_0_INTCLR_STRSWITCH_0_IDX ATON_STRSWITCH_INT +#define ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_0_IDX ATON_EPOCHCTRL0_INT +#define ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_1_IDX ATON_EPOCHCTRL0_NOACK_INT +#define ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_2_IDX ATON_EPOCHCTRL0_ERR_INT +#define ATON_INTCTRL_0_INTCLR_DEBUG_TRACE_0_IDX ATON_DEBUG_TRACE0_INT + +#define ATON_INTCTRL_0_INTORMSK_STRENG_0_0_IDX ATON_STRENG0_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_1_0_IDX ATON_STRENG1_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_2_0_IDX ATON_STRENG2_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_3_0_IDX ATON_STRENG3_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_4_0_IDX ATON_STRENG4_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_5_0_IDX ATON_STRENG5_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_6_0_IDX ATON_STRENG6_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_7_0_IDX ATON_STRENG7_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_8_0_IDX ATON_STRENG8_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_9_0_IDX ATON_STRENG9_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_0_1_IDX ATON_STRENG0_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_1_1_IDX ATON_STRENG1_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_2_1_IDX ATON_STRENG2_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_3_1_IDX ATON_STRENG3_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_4_1_IDX ATON_STRENG4_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_5_1_IDX ATON_STRENG5_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_6_1_IDX ATON_STRENG6_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_7_1_IDX ATON_STRENG7_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_8_1_IDX ATON_STRENG8_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_STRENG_9_1_IDX ATON_STRENG9_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_CONVACC_0_IDX ATON_CONVACC0_INT +#define ATON_INTCTRL_0_INTORMSK_CONVACC_1_IDX ATON_CONVACC1_INT +#define ATON_INTCTRL_0_INTORMSK_CONVACC_2_IDX ATON_CONVACC2_INT +#define ATON_INTCTRL_0_INTORMSK_CONVACC_3_IDX ATON_CONVACC3_INT +#define ATON_INTCTRL_0_INTORMSK_BUSIF_0_IDX ATON_BUSIF0_INT +#define ATON_INTCTRL_0_INTORMSK_BUSIF_1_IDX ATON_BUSIF1_INT +#define ATON_INTCTRL_0_INTORMSK_STRSWITCH_0_IDX ATON_STRSWITCH_INT +#define ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_0_IDX ATON_EPOCHCTRL0_INT +#define ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_1_IDX ATON_EPOCHCTRL0_NOACK_INT +#define ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_2_IDX ATON_EPOCHCTRL0_ERR_INT +#define ATON_INTCTRL_0_INTORMSK_DEBUG_TRACE_0_IDX ATON_DEBUG_TRACE0_INT + +/** + * Stream Switch macros + */ +#define ATON_STRSWITCH_0_LINK_STRENG_0_0 ATON_LINK_STRENG0 +#define ATON_STRSWITCH_0_LINK_STRENG_1_0 ATON_LINK_STRENG1 +#define ATON_STRSWITCH_0_LINK_STRENG_2_0 ATON_LINK_STRENG2 +#define ATON_STRSWITCH_0_LINK_STRENG_3_0 ATON_LINK_STRENG3 +#if defined(ATON_LINK_STRENG4) +#define ATON_STRSWITCH_0_LINK_STRENG_4_0 ATON_LINK_STRENG4 +#define ATON_STRSWITCH_0_LINK_STRENG_5_0 ATON_LINK_STRENG5 +#endif +#if defined(ATON_LINK_STRENG6) +#define ATON_STRSWITCH_0_LINK_STRENG_6_0 ATON_LINK_STRENG6 +#define ATON_STRSWITCH_0_LINK_STRENG_7_0 ATON_LINK_STRENG7 +#define ATON_STRSWITCH_0_LINK_STRENG_8_0 ATON_LINK_STRENG8 +#define ATON_STRSWITCH_0_LINK_STRENG_9_0 ATON_LINK_STRENG9 +#endif + +#ifdef ATON_CONVACC_NUM +#define ATON_CONVACC_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_CONVACC_INT_GET_MASK(UNIT, REG_IDX) +#define ATON_STRSWITCH_0_LINK_CONVACC_0_0 ATON_LINK_CONVACC0 +#define ATON_STRSWITCH_0_LINK_CONVACC_1_0 ATON_LINK_CONVACC1 +#if defined(ATON_LINK_CONVACC2) +#define ATON_STRSWITCH_0_LINK_CONVACC_2_0 ATON_LINK_CONVACC2 +#define ATON_STRSWITCH_0_LINK_CONVACC_3_0 ATON_LINK_CONVACC3 +#endif // ATON_LINK_CONVACC2 +#endif // ATON_CONVACC_NUM + +#ifdef ATON_ARITH_NUM +#if defined(ATON_LINK_ARITH0) +#define ATON_STRSWITCH_0_LINK_ARITH_0_0 ATON_LINK_ARITH0 +#endif +#if defined(ATON_LINK_ARITH1) +#define ATON_STRSWITCH_0_LINK_ARITH_1_0 ATON_LINK_ARITH1 +#endif +#if defined(ATON_LINK_ARITH2) +#define ATON_STRSWITCH_0_LINK_ARITH_2_0 ATON_LINK_ARITH2 +#endif +#if defined(ATON_LINK_ARITH3) +#define ATON_STRSWITCH_0_LINK_ARITH_3_0 ATON_LINK_ARITH3 +#endif +#endif // ATON_ARITH_NUM + +#ifdef ATON_POOL_NUM +#if defined(ATON_LINK_POOL0) +#define ATON_STRSWITCH_0_LINK_POOL_0_0 ATON_LINK_POOL0 +#endif +#if defined(ATON_LINK_POOL1) +#define ATON_STRSWITCH_0_LINK_POOL_1_0 ATON_LINK_POOL1 +#endif +#if defined(ATON_LINK_POOL2) +#define ATON_STRSWITCH_0_LINK_POOL_2_0 ATON_LINK_POOL2 +#endif +#endif // ATON_POOL_NUM + +#ifdef ATON_ACTIV_NUM +#if defined(ATON_LINK_ACTIV0) +#define ATON_STRSWITCH_0_LINK_ACTIV_0_0 ATON_LINK_ACTIV0 +#endif +#if defined(ATON_LINK_ACTIV1) +#define ATON_STRSWITCH_0_LINK_ACTIV_1_0 ATON_LINK_ACTIV1 +#endif +#if defined(ATON_LINK_ACTIV2) +#define ATON_STRSWITCH_0_LINK_ACTIV_2_0 ATON_LINK_ACTIV2 +#endif +#endif // ATON_ACTIV_NUM + +#ifdef ATON_DECUN_NUM +#define ATON_STRSWITCH_0_LINK_DECUN_0_0 ATON_LINK_DECUN0 +#if defined(ATON_LINK_DECUN1) +#define ATON_STRSWITCH_0_LINK_DECUN_1_0 ATON_LINK_DECUN1 +#endif +#if defined(ATON_LINK_DECUN2) +#define ATON_STRSWITCH_0_LINK_DECUN_2_0 ATON_LINK_DECUN2 +#endif +#endif // ATON_DECUN_NUM + +#ifdef ATON_IMC_NUM +#define ATON_STRSWITCH64_0_LINK_IMC_0_0 ATON_LINK_IMC00 +#define ATON_STRSWITCH64_0_LINK_IMC_0_1 ATON_LINK_IMC01 +#define ATON_STRSWITCH64_0_LINK_IMC_0_2 ATON_LINK_IMC02 +#define ATON_STRSWITCH64_0_LINK_IMC_0_3 ATON_LINK_IMC03 +#define ATON_STRSWITCH64_0_LINK_IMC_0_4 ATON_LINK_IMC04 +#define ATON_STRSWITCH64_0_LINK_IMC_0_5 ATON_LINK_IMC05 +#define ATON_STRSWITCH64_0_LINK_IMC_0_6 ATON_LINK_IMC06 +#define ATON_STRSWITCH64_0_LINK_IMC_0_7 ATON_LINK_IMC07 +#define ATON_STRSWITCH64_0_LINK_IMC_0_8 ATON_LINK_IMC08 +#define ATON_STRSWITCH64_0_LINK_IMC_0_9 ATON_LINK_IMC09 +#endif + +#if defined(ATON_DEBUG_TRACE_NUM) +#define ATON_DEBUG_TRACE_CLKB_CLK(UNIT) ATON_DEBUG_TRACE0_CLK_CLKB +#undef ATON_DEBUG_TRACE_CTRL_DT +#define ATON_DEBUG_TRACE_CTRL_DT(UNIT) 0 +#endif + +#ifdef ATON_RECBUF_NUM +#define ATON_RECBUF_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_RECBUF_INT_GET_MASK(UNIT, REG_IDX) +#endif + +#ifdef ATON_EPOCHCTRL_NUM +#define ATON_EPOCHCTRL_ERR_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_EPOCHCTRL_ERR_INT_GET_MASK(UNIT, REG_IDX) +#define ATON_EPOCHCTRL_NOACK_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_EPOCHCTRL_NOACK_INT_GET_MASK(UNIT, REG_IDX) +#define ATON_EPOCHCTRL_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_EPOCHCTRL_INT_GET_MASK(UNIT, REG_IDX) +#endif + +#if defined(ATON_LINK_CONVACC2) +// compiling for N6 4CA // FIXME this is a very shallow check +#define ATON_STRSWITCH_0_DSTSTRENG_0_0_IDX 0 +#define ATON_STRSWITCH_0_DSTSTRENG_1_0_IDX 1 +#define ATON_STRSWITCH_0_DSTSTRENG_2_0_IDX 2 +#define ATON_STRSWITCH_0_DSTSTRENG_3_0_IDX 3 +#define ATON_STRSWITCH_0_DSTSTRENG_4_0_IDX 4 +#define ATON_STRSWITCH_0_DSTSTRENG_5_0_IDX 5 +#define ATON_STRSWITCH_0_DSTSTRENG_6_0_IDX 6 +#define ATON_STRSWITCH_0_DSTSTRENG_7_0_IDX 7 +#define ATON_STRSWITCH_0_DSTSTRENG_8_0_IDX 8 +#define ATON_STRSWITCH_0_DSTSTRENG_9_0_IDX 9 +#define ATON_STRSWITCH_0_DSTCONVACC_0_0_IDX 10 +#define ATON_STRSWITCH_0_DSTCONVACC_0_1_IDX 11 +#define ATON_STRSWITCH_0_DSTCONVACC_0_2_IDX 12 +#define ATON_STRSWITCH_0_DSTCONVACC_1_0_IDX 13 +#define ATON_STRSWITCH_0_DSTCONVACC_1_1_IDX 14 +#define ATON_STRSWITCH_0_DSTCONVACC_1_2_IDX 15 +#define ATON_STRSWITCH_0_DSTCONVACC_2_0_IDX 16 +#define ATON_STRSWITCH_0_DSTCONVACC_2_1_IDX 17 +#define ATON_STRSWITCH_0_DSTCONVACC_2_2_IDX 18 +#define ATON_STRSWITCH_0_DSTCONVACC_3_0_IDX 19 +#define ATON_STRSWITCH_0_DSTCONVACC_3_1_IDX 20 +#define ATON_STRSWITCH_0_DSTCONVACC_3_2_IDX 21 +#define ATON_STRSWITCH_0_DSTDECUN_0_0_IDX 22 +#define ATON_STRSWITCH_0_DSTDECUN_0_1_IDX 23 +#define ATON_STRSWITCH_0_DSTDECUN_1_0_IDX 24 +#define ATON_STRSWITCH_0_DSTDECUN_1_1_IDX 25 +#define ATON_STRSWITCH_0_DSTACTIV_0_0_IDX 26 +#define ATON_STRSWITCH_0_DSTACTIV_1_0_IDX 27 +#define ATON_STRSWITCH_0_DSTARITH_0_0_IDX 28 +#define ATON_STRSWITCH_0_DSTARITH_0_1_IDX 29 +#define ATON_STRSWITCH_0_DSTARITH_1_0_IDX 30 +#define ATON_STRSWITCH_0_DSTARITH_1_1_IDX 31 +#define ATON_STRSWITCH_0_DSTARITH_2_0_IDX 32 +#define ATON_STRSWITCH_0_DSTARITH_2_1_IDX 33 +#define ATON_STRSWITCH_0_DSTARITH_3_0_IDX 34 +#define ATON_STRSWITCH_0_DSTARITH_3_1_IDX 35 +#define ATON_STRSWITCH_0_DSTPOOL_0_0_IDX 36 +#define ATON_STRSWITCH_0_DSTPOOL_1_0_IDX 37 +#define ATON_STRSWITCH_0_DSTRECBUF_0_0_IDX 38 +#define ATON_STRSWITCH_0_DSTRECBUF_0_1_IDX 39 +#define ATON_STRSWITCH_0_DSTRECBUF_0_2_IDX 40 +// additional destination indices for old ATON.h of hybrid RTL +#ifdef ATON_IMC_NUM +#define ATON_STRSWITCH_0_DSTSSCONN_0_0_IDX 41 +#define ATON_STRSWITCH_0_DSTSSCONN_1_0_IDX 42 +#define ATON_STRSWITCH_0_DSTSSCONN_2_0_IDX 43 +#define ATON_STRSWITCH_0_DSTSSCONN_3_0_IDX 44 +#endif // ATON_IMC_NUM + +#else +// compiling for tiny N6 (2CA) +#define ATON_STRSWITCH_0_DSTSTRENG_0_0_IDX 0 +#define ATON_STRSWITCH_0_DSTSTRENG_1_0_IDX 1 +#define ATON_STRSWITCH_0_DSTSTRENG_2_0_IDX 2 +#define ATON_STRSWITCH_0_DSTSTRENG_3_0_IDX 3 +#define ATON_STRSWITCH_0_DSTSTRENG_4_0_IDX 4 +#define ATON_STRSWITCH_0_DSTSTRENG_5_0_IDX 5 +#define ATON_STRSWITCH_0_DSTCONVACC_0_0_IDX 6 +#define ATON_STRSWITCH_0_DSTCONVACC_0_1_IDX 7 +#define ATON_STRSWITCH_0_DSTCONVACC_0_2_IDX 8 +#define ATON_STRSWITCH_0_DSTCONVACC_1_0_IDX 9 +#define ATON_STRSWITCH_0_DSTCONVACC_1_1_IDX 10 +#define ATON_STRSWITCH_0_DSTCONVACC_1_2_IDX 11 +#define ATON_STRSWITCH_0_DSTDECUN_0_0_IDX 12 +#define ATON_STRSWITCH_0_DSTDECUN_0_1_IDX 13 +#define ATON_STRSWITCH_0_DSTACTIV_0_0_IDX 14 +#define ATON_STRSWITCH_0_DSTARITH_0_0_IDX 15 +#define ATON_STRSWITCH_0_DSTARITH_0_1_IDX 16 +#define ATON_STRSWITCH_0_DSTPOOL_0_0_IDX 17 +#define ATON_STRSWITCH_0_DSTRECBUF_0_0_IDX 18 +#define ATON_STRSWITCH_0_DSTRECBUF_0_1_IDX 19 +#define ATON_STRSWITCH_0_DSTRECBUF_0_2_IDX 20 +#endif + +/* Compute offset instead of doing 40 ifs */ +#define ATON_STRSWITCH_DST_OFFSET(UNIT, IDX) (ATON_STRSWITCH_DSTSTRENG0_OFFSET + ((IDX) << 2)) + +#define ATON_STRSWITCH_DST_EN0_LSB ATON_STRSWITCH_DSTSTRENG1_EN0_LSB +#define ATON_STRSWITCH_DST_EN1_LSB ATON_STRSWITCH_DSTSTRENG1_EN1_LSB +#define ATON_STRSWITCH_DST_LINK0_LSB ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB +#define ATON_STRSWITCH_DST_LINK1_LSB ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB +#define ATON_STRSWITCH_DST_FNR0_LSB ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB +#define ATON_STRSWITCH_DST_FNR1_LSB ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB +#define ATON_STRSWITCH_DST_FNR0_MASK ATON_STRSWITCH_DSTSTRENG0_FNR0_MASK +#define ATON_STRSWITCH_DST_FNR1_MASK ATON_STRSWITCH_DSTSTRENG0_FNR1_MASK + +/** Debug and Trace Unit macros + */ +#define ATON_DEBUG_TRACE_TRIG_ADDR(UNIT, IDX) (ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT) + ((IDX) << 2)) +#define ATON_DEBUG_TRACE_EVENT_ADDR(UNIT, IDX) (ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT) + ((IDX) << 2)) +#define ATON_DEBUG_TRACE_EVENT_CNT_ADDR(UNIT, IDX) (ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT) + ((IDX) << 2)) + +#define ATON_DEBUG_TRACE_TRIG_DT ATON_DEBUG_TRACE_TRIG_0_DT +#define ATON_DEBUG_TRACE_EVENT_DT ATON_DEBUG_TRACE_EVENT_0_DT +#define ATON_DEBUG_TRACE_TRIG_SET_SEL(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_SEL(REG, DATA) +#define ATON_DEBUG_TRACE_TRIG_SET_EVENT_TYPE(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_EVENT_TYPE(REG, DATA) +#define ATON_DEBUG_TRACE_TRIG_SET_FILTER(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_FILTER(REG, DATA) +#define ATON_DEBUG_TRACE_TRIG_SET_EN(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_EN(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_SEL(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_SEL(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_EVENT_TYPE(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_EVENT_TYPE(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_WRAP(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_WRAP(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_CNT_DOWN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_CNT_DOWN(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_EN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_EN(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_INT_DISABLE(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_INT_DISABLE(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_START_EVENT_EN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_START_EVENT_SEL(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_STOP_EVENT_EN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(REG, DATA) +#define ATON_DEBUG_TRACE_EVENT_SET_STOP_EVENT_SEL(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(REG, DATA) + +#define ATON_DEBUG_TRACE_TRIG_OVR_MASK ATON_DEBUG_TRACE_TRIG_0_OVR_MASK +#define ATON_DEBUG_TRACE_TRIG_SWTRIG_LSB ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB + +#define ATON_DEBUG_TRACE_ILINK_STATES_GET(unit, idx) \ + (idx == 0 ? ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET(unit) : ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET(unit)) +#define ATON_DEBUG_TRACE_OLINK_STATES_GET(unit, idx) \ + (idx == 0 ? ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET(unit) : ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET(unit)) +#define ATON_DEBUG_TRACE_ILINK_STATES_IDX_MAX(id) 1 +#define ATON_DEBUG_TRACE_OLINK_STATES_IDX_MAX(id) 1 + +/** + * Bus Interface crypto engine macros: straight from raSTa header + */ +#define ATON_BUSIF_0_KEY0_31_0_IDX 0 +#define ATON_BUSIF_0_KEY0_31_0_S 0 +#define ATON_BUSIF_0_KEY0_63_32_IDX 0 +#define ATON_BUSIF_0_KEY0_63_32_S 1 +#define ATON_BUSIF_0_KEY0_95_64_IDX 0 +#define ATON_BUSIF_0_KEY0_95_64_S 2 +#define ATON_BUSIF_0_KEY0_127_96_IDX 0 +#define ATON_BUSIF_0_KEY0_127_96_S 3 +#define ATON_BUSIF_0_KEY1_31_0_IDX 1 +#define ATON_BUSIF_0_KEY1_31_0_S 0 +#define ATON_BUSIF_0_KEY1_63_32_IDX 1 +#define ATON_BUSIF_0_KEY1_63_32_S 1 +#define ATON_BUSIF_0_KEY1_95_64_IDX 1 +#define ATON_BUSIF_0_KEY1_95_64_S 2 +#define ATON_BUSIF_0_KEY1_127_96_IDX 1 +#define ATON_BUSIF_0_KEY1_127_96_S 3 +#define ATON_BUSIF_0_KEY0_31_0_IDX 0 +#define ATON_BUSIF_0_KEY0_31_0_S 0 +#define ATON_BUSIF_0_KEY0_63_32_IDX 0 +#define ATON_BUSIF_0_KEY0_63_32_S 1 +#define ATON_BUSIF_0_KEY0_95_64_IDX 0 +#define ATON_BUSIF_0_KEY0_95_64_S 2 +#define ATON_BUSIF_0_KEY0_127_96_IDX 0 +#define ATON_BUSIF_0_KEY0_127_96_S 3 +#define ATON_BUSIF_0_KEY1_31_0_IDX 1 +#define ATON_BUSIF_0_KEY1_31_0_S 0 +#define ATON_BUSIF_0_KEY1_63_32_IDX 1 +#define ATON_BUSIF_0_KEY1_63_32_S 1 +#define ATON_BUSIF_0_KEY1_95_64_IDX 1 +#define ATON_BUSIF_0_KEY1_95_64_S 2 +#define ATON_BUSIF_0_KEY1_127_96_IDX 1 +#define ATON_BUSIF_0_KEY1_127_96_S 3 + +#ifndef ATON_HIDE_REG_MACROS +#define ATON_GET_REG32(ADDR) (*((volatile uint32_t *)(uintptr_t)(ADDR))) + +#define ATON_SET_REG32(ADDR, DATA) \ + do \ + { \ + *((volatile uint32_t *)(uintptr_t)(ADDR)) = (DATA); \ + } while (0); +#endif // #ifndef ATON_HIDE_REG_MACROS + +#define ATON_BUSIF_KEY_OFFSET(UNIT, IDX, S) \ + (((IDX) == 0) && ((S) == 0) ? 0x14UL \ + : ((IDX) == 0) && ((S) == 1) ? 0x18UL \ + : ((IDX) == 0) && ((S) == 2) ? 0x1cUL \ + : ((IDX) == 0) && ((S) == 3) ? 0x20UL \ + : ((IDX) == 1) && ((S) == 0) ? 0x24UL \ + : ((IDX) == 1) && ((S) == 1) ? 0x28UL \ + : ((IDX) == 1) && ((S) == 2) ? 0x2cUL \ + : ((IDX) == 1) && ((S) == 3) ? 0x30UL \ + : 0) + +#define ATON_BUSIF_KEY_ADDR(UNIT, IDX, S) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY_OFFSET(UNIT, IDX, S)) +#define ATON_BUSIF_KEY_SET(UNIT, IDX, S, DATA) ATON_SET_REG32(ATON_BUSIF_KEY_ADDR(UNIT, IDX, S), DATA) + +/* + * STRENG ENCR registers, macros copied from RaSTa-produced ATON.h + */ +#ifndef ATON_STRENG_ENCR_LSB_SET + +#define ATON_STRENG_ENCR_LSB_SET(UNIT, DATA) ATON_SET_REG32(ATON_STRENG_ENCR_LSB_ADDR(UNIT), DATA) +#define ATON_STRENG_ENCR_MSB_SET_ID_MSB(REG, DATA) \ + ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ID_MSB_LSB, ATON_STRENG_ENCR_MSB_ID_MSB_W, DATA) +#define ATON_STRENG_ENCR_MSB_SET_EN(REG, DATA) \ + ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_EN_LSB, ATON_STRENG_ENCR_MSB_EN_W, DATA) +#define ATON_STRENG_ENCR_MSB_SET_ROUNDS(REG, DATA) \ + ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ROUNDS_LSB, ATON_STRENG_ENCR_MSB_ROUNDS_W, DATA) +#define ATON_STRENG_ENCR_MSB_SET_KEY_SEL(REG, DATA) \ + ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_KEY_SEL_LSB, ATON_STRENG_ENCR_MSB_KEY_SEL_W, DATA) +#define ATON_STRENG_ENCR_MSB_SET_INC(REG, DATA) \ + ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_INC_LSB, ATON_STRENG_ENCR_MSB_INC_W, DATA) +#define ATON_STRENG_ENCR_MSB_SET(UNIT, DATA) ATON_SET_REG32(ATON_STRENG_ENCR_MSB_ADDR(UNIT), DATA) + +#endif + +/** Clock gating macros + */ +#define ATON_STRENG_CLKB_CLK(X) (ATON_STRENG0_CLK_CLKB + X) +#define ATON_CONVACC_CLKB_CLK(X) (ATON_CONVACC0_CLK_CLKB + X) +#define ATON_DECUN_CLKB_CLK(X) (ATON_DECUN0_CLK_CLKB + X) +#define ATON_ACTIV_CLKB_CLK(X) (ATON_ACTIV0_CLK_CLKB + X) +#define ATON_ARITH_CLKB_CLK(X) (ATON_ARITH0_CLK_CLKB + X) +#define ATON_POOL_CLKB_CLK(X) (ATON_POOL0_CLK_CLKB + X) +#define ATON_RECBUF_CLKB_CLK(X) (ATON_RECBUF0_CLK_CLKB + X) +#define ATON_EPOCHCTRL_CLKB_CLK(X) (ATON_EPOCHCTRL0_CLK_CLKB + X) + +/** Coefficients tables offset macros + */ +#define ATON_ACTIV_ROM0_IDX_MIN (0) +#define ATON_ACTIV_ROM0_IDX_MAX (32 - 1) +#define ATON_ACTIV_ROM0_OFFSET(UNIT, IDX) (ATON_ACTIV_ROM_OFFSET_0 + 4 * (IDX)) +#define ATON_ACTIV_ROM0_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM0_OFFSET(UNIT, IDX)) +#define ATON_ACTIV_ROM0_DT (0x0) +#define ATON_ACTIV_ROM0_SET_ENTRY(REG, DATA) ATON_SET_FIELD(REG, 0UL, 8UL, DATA) +#define ATON_ACTIV_ROM0_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ACTIV_ROM0_ADDR(UNIT, IDX), (DATA)) +#define ATON_ACTIV_ROM0_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM0_OFFSET(UNIT, IDX)) + +#define ATON_ACTIV_ROM1_AB_IDX_MIN (0) +#define ATON_ACTIV_ROM1_AB_IDX_MAX (64 - 1) +#define ATON_ACTIV_ROM1_AB_OFFSET(UNIT, IDX) (ATON_ACTIV_ROM_OFFSET_1 + 8 * (IDX)) +#define ATON_ACTIV_ROM1_AB_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM1_AB_OFFSET(UNIT, IDX)) +#define ATON_ACTIV_ROM1_AB_DT (0x0) +#define ATON_ACTIV_ROM1_AB_SET_A(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA) +#define ATON_ACTIV_ROM1_AB_SET_B(REG, DATA) ATON_SET_FIELD(REG, 16UL, 16UL, DATA) +#define ATON_ACTIV_ROM1_AB_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ACTIV_ROM1_AB_ADDR(UNIT, IDX), (DATA)) + +#define ATON_ACTIV_ROM1_C_IDX_MIN (0) +#define ATON_ACTIV_ROM1_C_IDX_MAX (64 - 1) +#define ATON_ACTIV_ROM1_C_OFFSET(UNIT, IDX) (ATON_ACTIV_ROM_OFFSET_1 + 8 * (IDX) + 4) +#define ATON_ACTIV_ROM1_C_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM1_C_OFFSET(UNIT, IDX)) +#define ATON_ACTIV_ROM1_C_DT (0x0) +#define ATON_ACTIV_ROM1_C_SET_C(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA) +#define ATON_ACTIV_ROM1_C_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ACTIV_ROM1_C_ADDR(UNIT, IDX), (DATA)) + +#define ATON_ARITH_COEFF_AB_IDX_MIN (0) +#define ATON_ARITH_COEFF_AB_IDX_MAX ((3 * 128) - 1) +#define ATON_ARITH_COEFF_AB_OFFSET(UNIT, IDX) (ATON_ARITH_MEM_OFFSET + 8 * (IDX)) +#define ATON_ARITH_COEFF_AB_ADDR(UNIT, IDX) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFF_AB_OFFSET(UNIT, IDX)) +#define ATON_ARITH_COEFF_AB_DT (0x0) +#define ATON_ARITH_COEFF_AB_SET_A(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA) +#define ATON_ARITH_COEFF_AB_SET_B(REG, DATA) ATON_SET_FIELD(REG, 16UL, 16UL, DATA) +#define ATON_ARITH_COEFF_AB_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ARITH_COEFF_AB_ADDR(UNIT, IDX), (DATA)) + +#define ATON_ARITH_COEFF_C_IDX_MIN (0) +#define ATON_ARITH_COEFF_C_IDX_MAX ((3 * 128) - 1) +#define ATON_ARITH_COEFF_C_OFFSET(UNIT, IDX) (ATON_ARITH_MEM_OFFSET + 8 * (IDX) + 4) +#define ATON_ARITH_COEFF_C_ADDR(UNIT, IDX) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFF_C_OFFSET(UNIT, IDX)) +#define ATON_ARITH_COEFF_C_DT (0x0) +#define ATON_ARITH_COEFF_C_SET_C(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA) +#define ATON_ARITH_COEFF_C_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ARITH_COEFF_C_ADDR(UNIT, IDX), (DATA)) + +#else // defined RASTA_SVN_REV + +#if (ATON_INTCTRL_INTS(0) > 32) +#define ATON_INT_GET_MASK(_macro_, _unit_) (_macro_(_unit_, 0, 0) | (((uint64_t)_macro_(_unit_, 1, 0)) << 32)) +#define __ATON_INTCTRL_INTORMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTORMSK_H_SET(0, IDX, DATA) +#define __ATON_INTCTRL_INTANDMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTANDMSK_H_SET(0, IDX, DATA) +#else //(ATON_INT_NR <= 32) +#define ATON_INT_GET_MASK(_macro_, _unit_) _macro_(_unit_, 0, 0) +#endif //(ATON_INT_NR <= 32) + +#endif // RASTA_SVN_REV + +/* These macros are NOT defined in some older versions of ATON.h + (namely Neuromem & Centauri), so define them here */ +/* TODO: should not be here as ll_aton_rcompat.h is meant for raSTa compatibility only */ + +#ifndef ATON_DECUN_BFORMAT_DT +#define ATON_DECUN_BFORMAT_DT \ + ((ATON_DECUN_BFORMAT_CVS_DT << ATON_DECUN_BFORMAT_CVS_LSB) | \ + (ATON_DECUN_BFORMAT_CWS_DT << ATON_DECUN_BFORMAT_CWS_LSB) | \ + (ATON_DECUN_BFORMAT_OSAM_DT << ATON_DECUN_BFORMAT_OSAM_LSB)) +#endif + +#ifndef ATON_DECUN_DFORMAT_DT +#define ATON_DECUN_DFORMAT_DT \ + ((ATON_DECUN_DFORMAT_CV8_DT << ATON_DECUN_DFORMAT_CV8_LSB) | \ + (ATON_DECUN_DFORMAT_RAWLINE_DT << ATON_DECUN_DFORMAT_RAWLINE_LSB)) +#endif + +#ifndef ATON_DECUN_FFORMAT_DT +#define ATON_DECUN_FFORMAT_DT (ATON_DECUN_FFORMAT_BN_DT << ATON_DECUN_FFORMAT_BN_LSB) +#endif + +#ifndef ATON_DECUN_CTRL_SET_PAGEADDR +#define ATON_DECUN_CTRL_SET_PAGEADDR(REG, DATA) ATON_SET_FIELD(REG, 4UL, 3UL, DATA) +#endif + +#ifndef ATON_SET_FIELD +#define ATON_SET_FIELD ATON_SET_FIELD32 +#endif + +#endif //__LL_ATON_COMPAT_H diff --git a/lib/stai/libstai/include/ll_aton_reloc_network.h b/lib/stai/libstai/include/ll_aton_reloc_network.h new file mode 100644 index 000000000..209ded87e --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_reloc_network.h @@ -0,0 +1,513 @@ +/** + ****************************************************************************** + * @file ll_aton_reloc_network.h + * @author MCD/AIS Team + * @brief Header file of ATON LL module for relocatable model support + ****************************************************************************** + * @attention + * + * Copyright (c) 2024, 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_RELOC_NETWORK_H__ +#define __LL_ATON_RELOC_NETWORK_H__ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ll_aton_lib.h" + +#if !defined(LL_ATON_RT_RELOC) +#error "LL_ATON_RT_RELOC should be defined to use the relocatable models" +#endif + +/* ----------------------------------------------------------------------------- + * AI RELOC definition + * ----------------------------------------------------------------------------- + */ + +/* version of the AI RELOC runtime (bootstrap) */ +#define AI_RELOC_RT_VERSION_MAJOR 8 /* for NPU/ATON env. */ +#define AI_RELOC_RT_VERSION_MINOR 0 + +/* AI RT executing mode definitions */ +#define AI_RELOC_RT_LOAD_MODE_XIP \ + (1 << 0) /* (default) only the data/bss section are \ + copied in RAM, code is executed in-place */ +#define AI_RELOC_RT_LOAD_MODE_COPY (1 << 1) /* code and data sections are copied in RAM */ +#define AI_RELOC_RT_LOAD_MODE_CLEAR (1 << 2) /* clear the acts memory pools */ + +/* AI RT error definitions */ +#define AI_RELOC_RT_ERR_NONE (0) +#define AI_RELOC_RT_ERR_INVALID_BIN (-1) /* Invalid binary object */ +#define AI_RELOC_RT_ERR_MEMORY (-2) /* RAM size is insufficient */ +#define AI_RELOC_RT_ERR_NOT_SUPPORTED (-3) /* feature/option not supported */ +#define AI_RELOC_RT_ERR_ARG (-4) /* argument not valid */ +#define AI_RELOC_RT_ERR_INVALID_HDL (-5) /* handle not valid */ +#define AI_RELOC_RT_ERR_INSTALL (-6) /* installation failed */ +#define AI_RELOC_RT_ERR_PARAM_ADDR (-7) /* invalid param addr */ +#define AI_RELOC_RT_ERR_PARAM_DESC (-8) /* invalid param descriptor */ + +/* + * AI RELOC flags (32b) - part of the binary header + * + * b31..b24 : 8b - RELOC API version major.minor (4b+4b) + * + * b23..b20 : 4b - fields reserved for post-process script + * b20 : SECURE mode + * b21 : LL_ATON_EB_DBG_INFO + * b22 : LL_ATON_RT_MODE == LL_ATON_RT_ASYNC + * b23 : reserved + * + * Variant fields + * + * b19..b12 : 8b - compilation options: ARM tool-chain, FPU, FLOAT-ABI + * b19..b16: 4b - ARM tool-chain - 1000b: GNU Arm Embedded Tool-chain + * b15: 1b - reserved + * b14.b13: 2b - Floating-point EABI used - '00b':soft, '01b':softfp, '10b':hard + * b12: 1b - FPU is used + * b11..b0 : 12b - CPUID (Part Number fields of the @0xE000ED00 CPUID register) + */ + +/* CPUID/Cortex-mM definition */ +#define AI_RELOC_ARM_CORTEX_M0P (0xC60UL) +#define AI_RELOC_ARM_CORTEX_M3 (0xC23UL) +#define AI_RELOC_ARM_CORTEX_M4 (0xC24UL) +#define AI_RELOC_ARM_CORTEX_M7 (0xC27UL) +#define AI_RELOC_ARM_CORTEX_M33 (0xD21UL) +#define AI_RELOC_ARM_CORTEX_M55 (0xD22UL) + +/* Tool-chain definition (ONLY this tool-chain is currently supported)*/ +#define AI_RELOC_TOOLCHAIN_ARM_EMBEDDED (0x8UL) + +/* Floating-point ABI definition (in relation with the tool-chain) */ +#define AI_RELOC_TOOLCHAIN_FP_ABI_SOFT (0x0UL) +#define AI_RELOC_TOOLCHAIN_FP_ABI_SOFTFP (0x1UL) +#define AI_RELOC_TOOLCHAIN_FP_ABI_HARD (0x2UL) + +/* Getter/setter macros to read/write the flags */ +#define AI_RELOC_RT_SET_FLAGS(_var, _extra) \ + (((AI_RELOC_RT_VERSION_MAJOR << 4 | AI_RELOC_RT_VERSION_MINOR << 0) << 24) | (((_extra)&0xF) << 20) | \ + ((_var)&0xFFFFF)) + +#define AI_RELOC_RT_GET_MAJOR(_flags) (int)(((_flags) >> 28) & 0xF) +#define AI_RELOC_RT_GET_MINOR(_flags) (int)(((_flags) >> 24) & 0xF) + +#define AI_RELOC_RT_GET_VARIANT(_flags) ((_flags)&0xFFFFF) +#define AI_RELOC_RT_GET_EXTRA(_flags) (((_flags) >> 20) & 0xF) + +/* VARIANT */ +#define AI_RELOC_RT_GET_CPUID(_flags) (((_flags) >> 0) & 0xFFF) +#define AI_RELOC_RT_GET_COMPILER(_flags) (((_flags) >> 16) & 0xF) +#define AI_RELOC_RT_GET_FPEABI(_flags) (((_flags) >> 13) & 0x3) +#define AI_RELOC_RT_FPU_USED(_flags) (((_flags) >> 12) & 1) + +#define AI_RELOC_RT_SET_TOOLS(_val) ((_val & 0xF) << 16) +#define AI_RELOC_RT_SET_ABI(_val) ((_val & 3) << 13) +#define AI_RELOC_RT_SET_FPU(_val) ((_val & 1) << 12) +#define AI_RELOC_RT_SET_MCU_CONF(_val) (_val & 0xFFF) + +/* EXTRA flags */ +#define AI_RELOC_RT_SECURE(_flags) (((_flags) >> 20) & 1) +#define AI_RELOC_RT_DBG_INFO(_flags) (((_flags) >> 21) & 1) +#define AI_RELOC_RT_ASYNC_MODE(_flags) (((_flags) >> 22) & 1) + +#define AI_RELOC_MAGIC (0x4E49424EUL) + + /* Callback functions */ + struct ll_aton_reloc_callback + { + /* services */ + void (*assert_func)(const char *filename, int line, const char *assert_func, const char *expr); + void (*ll_lib_error)(int err_code, int line, const char *func); + + /* cache operations */ + void (*ll_aton_cache_mcu_clean_range)(uintptr_t virtual_addr, uint32_t size); + void (*ll_aton_cache_mcu_invalidate_range)(uintptr_t virtual_addr, uint32_t size); + void (*ll_aton_cache_mcu_clean_invalidate_range)(uintptr_t virtual_addr, uint32_t size); + void (*ll_aton_cache_npu_clean_range)(uintptr_t virtual_addr, uint32_t size); + void (*ll_aton_cache_npu_clean_invalidate_range)(uintptr_t virtual_addr, uint32_t size); + + /* ll aton lib */ + int (*ll_aton_lib_concat)(const LL_Buffer_InfoTypeDef *inputs, unsigned int ninputs, + const LL_Buffer_InfoTypeDef *output, unsigned int axis, int dma_in, int dma_out); + int (*ll_aton_lib_cast)(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, int dma_in, + int dma_out); + int (*ll_aton_lib_softmax)(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, + unsigned int axis, int legacy); + int (*ll_aton_lib_dma_imagetorow)(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, + unsigned blocksize_w, unsigned stride_h, unsigned stride_w, int dma_in, + int dma_out); + int (*ll_aton_lib_dma_spacetodepth)(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, + unsigned blocksize_w, int dma_in, int dma_out); + int (*ll_aton_lib_dma_rowtoimage)(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, + unsigned blocksize_w, unsigned stride_h, unsigned stride_w, int dma_in, + int dma_out); + int (*ll_aton_lib_dma_depthtospace)(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, + unsigned blocksize_w, int dma_in, int dma_out); + int (*ll_aton_lib_dma_outputs_flat_copy)(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, + int dma_in, int dma_out); + int (*ll_aton_lib_dma_outputs_slice_splitlike)(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *output, int32_t tot_out_size, + int32_t width_in_bytes, int32_t fheight, int32_t line_offset, + int8_t n_bits, int dma_in, int dma_out); + int (*ll_aton_lib_dma_outputs_channel_split_aton)(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, + unsigned int nr_of_outputs, unsigned int leading_dims, int dma_in, + int dma_out); + int (*ll_aton_lib_dma_outputs_channel_split_batched)(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, + unsigned int nr_of_outputs, int dma_in, int dma_out); + int (*ll_aton_lib_dma_pad_memset)(void *output, int32_t constant_value, size_t c, + __ll_pad_sw_params_t *common_params); + int (*ll_aton_lib_dma_pad_filling)(__ll_pad_sw_params_t *init_common_params); + int (*ll_aton_lib_dma_transpose)(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + const uint8_t *target_pos, const uint8_t *perm_to_use, int dma_in, int dma_out); + }; + + /* AI RELOC RT context definition */ + struct ai_reloc_rt_ctx + { + volatile uint32_t state; /* current state */ + uint32_t file_addr; /* file address of the binary (flashed location) */ + uint32_t ram_addr; /* loaded base address for the RAM segment */ + uint32_t rom_addr; /* loaded base address for the ROM segment */ + struct ll_aton_reloc_callback *cbs; /* callback functions */ + const char *c_name; /* c-name of model */ + const uint32_t acts_sz; /* size for the activations */ + const uint32_t params_sz; /* size for the params/weights */ + const uint32_t ext_ram_sz; /* requested external ram size for the activations (and params) */ + const char *rt_version_desc; /* rt description */ + const uint32_t rt_version; /* rt version */ + const uint32_t rt_version_extra; /* rt version extra */ + const uint32_t params_bin_sz; /* size of the binary blob to handle the params/weights */ + const uint32_t params_bin_crc32; /* crc32 value of the binary blob */ + NN_Instance_TypeDef *ll_instance; /* associated user NN Instance for LL ATON code */ + const NN_Interface_TypeDef *itf_network; + }; + +#define AI_RELOC_RT_STATE_NOT_INITIALIZED (0) +#define AI_RELOC_RT_STATE_INITIALIZED (1 << 0) +#define AI_RELOC_RT_STATE_XIP_MODE (1 << 1) + + typedef struct _ll_aton_reloc_info + { + const char *c_name; /* c-name of the model */ + uint32_t variant; /* 32-b word to handle the reloc rt version, + the used ARM Embedded compiler, + Cortex-Mx (CPUID) and if the FPU is requested */ + uint32_t code_sz; /* size of the code (header + txt + rodata + data + got + rel sections) */ + uint32_t params_off; /* offset (in bytes) of the weights */ + uint32_t params_sz; /* size (in bytes) of the weights */ + uint32_t acts_sz; /* minimum requested RAM size (in bytes) for the activations buffer */ + uint32_t ext_ram_sz; /* requested external ram size for the activations (and params) */ + uint32_t rt_ram_xip; /* minimum requested RAM size to install it, XIP mode */ + uint32_t rt_ram_copy; /* minimum requested RAM size to install it, COPY mode */ + const char *rt_version_desc; /* rt description */ + uint32_t rt_version; /* rt version */ + uint32_t rt_version_extra; /* rt version extra */ + } ll_aton_reloc_info; + + typedef struct _ll_aton_reloc_config + { + uintptr_t exec_ram_addr; /* base@ of the exec memory region to place the relocatable code/data (8-Bytes aligned) */ + uint32_t exec_ram_size; /* max size in byte of the exec memory region */ + uintptr_t ext_ram_addr; /* base@ of the external memory region to place the external pool (if requested) */ + size_t ext_ram_size; /* max size in byte of the external memory region */ + uintptr_t ext_param_addr; /* base@ of the param memory region (if requested) */ + uint32_t mode; + } ll_aton_reloc_config; + + typedef struct _ll_aton_reloc_mem_pool_desc + { + const char *name; /* name */ + uint32_t flags; /* type definition: 32b:4x8b */ + uint32_t foff; /* offset in the binary file */ + uint32_t dst; /* dst @ */ + uint32_t size; /* real size */ + } ll_aton_reloc_mem_pool_desc; + +#define AI_RELOC_MPOOL_TYPE_RELOC 1 +#define AI_RELOC_MPOOL_TYPE_COPY 2 +#define AI_RELOC_MPOOL_TYPE_RESET 3 + +#define AI_RELOC_MPOOL_GET_TYPE(_flags) (((_flags) >> 24) & 0xFF) + +#define AI_RELOC_MPOOL_IS_RELOC(_flags) (AI_RELOC_MPOOL_GET_TYPE(_flags) == AI_RELOC_MPOOL_TYPE_RELOC) +#define AI_RELOC_MPOOL_IS_COPY(_flags) (AI_RELOC_MPOOL_GET_TYPE(_flags) == AI_RELOC_MPOOL_TYPE_COPY) +#define AI_RELOC_MPOOL_IS_RESET(_flags) (AI_RELOC_MPOOL_GET_TYPE(_flags) == AI_RELOC_MPOOL_TYPE_RESET) + +#define AI_RELOC_MPOOL_DTYPE_PARAM 1 +#define AI_RELOC_MPOOL_DTYPE_ACTIV 2 +#define AI_RELOC_MPOOL_DTYPE_MIXED 3 + +#define AI_RELOC_MPOOL_GET_DTYPE(_flags) (((_flags) >> 16) & 0xFF) + +#define AI_RELOC_MPOOL_IS_PARAM(_flags) (AI_RELOC_MPOOL_GET_DTYPE(_flags) == AI_RELOC_MPOOL_DTYPE_PARAM) +#define AI_RELOC_MPOOL_IS_ACTIV(_flags) (AI_RELOC_MPOOL_GET_DTYPE(_flags) == AI_RELOC_MPOOL_DTYPE_ACTIV) +#define AI_RELOC_MPOOL_IS_MIXED(_flags) (AI_RELOC_MPOOL_GET_DTYPE(_flags) == AI_RELOC_MPOOL_DTYPE_MIXED) + +#define AI_RELOC_MPOOL_DATTR_READ 1 +#define AI_RELOC_MPOOL_DATTR_WRITE 2 +#define AI_RELOC_MPOOL_DATTR_CACHEABLE 4 + +#define AI_RELOC_MPOOL_GET_ATTR(_flags) (((_flags) >> 8) & 0xFF) + +#define AI_RELOC_MPOOL_IS_CACHEABLE(_flags) (AI_RELOC_MPOOL_GET_ATTR(_flags) & AI_RELOC_MPOOL_DATTR_CACHEABLE) +#define AI_RELOC_MPOOL_IS_READ(_flags) (AI_RELOC_MPOOL_GET_ATTR(_flags) & AI_RELOC_MPOOL_DATTR_READ) +#define AI_RELOC_MPOOL_IS_WRITE(_flags) (AI_RELOC_MPOOL_GET_ATTR(_flags) & AI_RELOC_MPOOL_DATTR_WRITE) + +#define AI_RELOC_MPOOL_GET_ID(_flags) ((_flags)&0xFF) + + /* ----------------------------------------------------------------------------- + * Public API declaration + * ----------------------------------------------------------------------------- */ + + void ll_aton_reloc_log_info(const uintptr_t file_ptr); + + int ll_aton_reloc_get_info(const uintptr_t file_ptr, ll_aton_reloc_info *rt); + + int ll_aton_reloc_install(const uintptr_t file_ptr, const ll_aton_reloc_config *config, + NN_Instance_TypeDef *nn_instance); + + int ll_aton_reloc_is_valid(const NN_Instance_TypeDef *nn_instance); + int ll_aton_reloc_get_file_ptr(const NN_Instance_TypeDef *nn_instance, uintptr_t *file_ptr); + + const LL_Buffer_InfoTypeDef *ll_aton_reloc_get_input_buffers_info(const NN_Instance_TypeDef *nn_instance, + int32_t num); + const LL_Buffer_InfoTypeDef *ll_aton_reloc_get_output_buffers_info(const NN_Instance_TypeDef *nn_instance, + int32_t num); + + LL_ATON_User_IO_Result_t ll_aton_reloc_set_input(const NN_Instance_TypeDef *nn_instance, uint32_t num, void *buffer, + uint32_t size); + LL_ATON_User_IO_Result_t ll_aton_reloc_set_output(const NN_Instance_TypeDef *nn_instance, uint32_t num, void *buffer, + uint32_t size); + void *ll_aton_reloc_get_input(const NN_Instance_TypeDef *nn_instance, uint32_t num); + void *ll_aton_reloc_get_output(const NN_Instance_TypeDef *nn_instance, uint32_t num); + + const LL_Buffer_InfoTypeDef *ll_aton_reloc_get_internal_buffers_info(const NN_Instance_TypeDef *nn_instance); + + ll_aton_reloc_mem_pool_desc *ll_aton_reloc_get_mem_pool_desc(const uintptr_t file_ptr, int index); + int ll_aton_reloc_set_callbacks(const NN_Instance_TypeDef *nn_instance, const struct ll_aton_reloc_callback *cbs); + + /* ----------------------------------------------------------------------------- + * Internal entry points of the relocatable model + * ----------------------------------------------------------------------------- */ + + bool ai_rel_network_ec_network_init(uintptr_t inst); + bool ai_rel_network_ec_inference_init(uintptr_t inst); + + LL_ATON_User_IO_Result_t ai_rel_network_set_input(uintptr_t inst, uint32_t num, void *buffer, uint32_t size); + void *ai_rel_network_get_input(uintptr_t inst, uint32_t num); + + LL_ATON_User_IO_Result_t ai_rel_network_set_output(uintptr_t inst, uint32_t num, void *buffer, uint32_t size); + void *ai_rel_network_get_output(uintptr_t inst, uint32_t num); + + const EpochBlock_ItemTypeDef *ai_rel_network_get_epoch_items(uintptr_t inst); + const LL_Buffer_InfoTypeDef *ai_rel_network_get_output_buffers_info(uintptr_t inst); + const LL_Buffer_InfoTypeDef *ai_rel_network_get_input_buffers_info(uintptr_t inst); + const LL_Buffer_InfoTypeDef *ai_rel_network_get_internal_buffers_info(uintptr_t inst); + + typedef void (*volatile start_end_func_ptr)(const void *epoch_block); + + void ai_rel_call_start_end_function(uintptr_t inst, start_end_func_ptr fct, const void *epoch_block); + +#if defined(BUILD_AI_NETWORK_RELOC) + + /* ----------------------------------------------------------------------------- + * This part is only used during the compilation of the network.c to + * generate the entry points (see linker and relocatable_pp.py files). + * ----------------------------------------------------------------------------- + */ + +#if !defined(MODEL_CONF) +#include "network_reloc_conf.h" +#endif + +#if !defined(C_NAME) +#define C_NAME "network" +#endif + +#if !defined(ACTS_SZ) +#define ACTS_SZ (2222) +#endif + +#if !defined(PARAMS_SZ) +#define PARAMS_SZ (3333) +#endif + +#if !defined(EXT_RAM_SZ) +#error "EXT_RAM_SZ should be defined" +#endif + +#if !defined(RUNTIME_DESC) +#define RUNTIME_DESC "RUNTIME undefined" +#endif + +#if !defined(RUNTIME_VERSION) +#define RUNTIME_VERSION (0) +#endif + +#if !defined(RUNTIME_VERSION_DEV) +#define RUNTIME_VERSION_DEV (0) +#endif + +#if !defined(ARM_MCU_CONF) +#define ARM_MCU_CONF AI_RELOC_ARM_CORTEX_M55 +#endif + +#if !defined(ARM_TOOLS_CONF) +#define ARM_TOOLS_CONF AI_RELOC_TOOLCHAIN_ARM_EMBEDDED +#endif + +#if !defined(SECURE_CONF) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SECURE_FLAG 1 +#else +#define SECURE_FLAG 0 +#endif +#endif + +#if defined(LL_ATON_EB_DBG_INFO) +#define DBG_INFO_FLAG 1 +#else +#define DBG_INFO_FLAG 0 +#endif + +#if defined(LL_ATON_RT_MODE) && LL_ATON_RT_MODE == LL_ATON_RT_ASYNC +#define ASYNC_MODE_FLAG 1 +#else +#define ASYNC_MODE_FLAG 0 +#endif + +/* build EXTRA flags defintion */ +#define EXTRA (SECURE_FLAG | (DBG_INFO_FLAG << 1) | (ASYNC_MODE_FLAG << 2)) + + /* https://developer.arm.com/documentation/dui0774/l/Other-Compiler-specific-Features/Predefined-macros?lang=en#a183-predefined-macros__when-the-softfp-predefined-macro-is-defined + */ + +#if __ARM_FP /* Set if hardware floating-point is available */ +#define _FPU 1UL +#if __SOFTFP__ +#define _EABI AI_RELOC_TOOLCHAIN_FP_ABI_SOFT /* -mfloat-abi=soft */ +#else +#define _EABI AI_RELOC_TOOLCHAIN_FP_ABI_HARD /* -mfloat-abi=hard */ +#endif +#else /* __ARM_FP */ +#define _FPU 0UL +#if __SOFTFP__ +#define _EABI AI_RELOC_TOOLCHAIN_FP_ABI_SOFT /* -mfloat-abi=soft */ +#else +#define _EABI AI_RELOC_TOOLCHAIN_FP_ABI_HARD /* -mfloat-abi=hard */ +#endif +#endif /* !__ARM_FP */ + +#if _EABI != AI_RELOC_TOOLCHAIN_FP_ABI_HARD +#error "Only -mfloat-abi=hard is supported" +#endif + +#if !defined(VARIANT) +/* Default variant definition */ +#define VARIANT \ + (AI_RELOC_RT_SET_TOOLS(ARM_TOOLS_CONF) | AI_RELOC_RT_SET_ABI(_EABI) | AI_RELOC_RT_SET_FPU(_FPU) | \ + AI_RELOC_RT_SET_MCU_CONF(ARM_MCU_CONF)) +#endif + +#if !defined(__GNUC__) +#error "AI_NETWORK_RELOC code generation is only supported with a GCC-based tool-chain" +#endif + +#if !defined(INCLUDE_INTERNAL_BUFFERS) + const LL_Buffer_InfoTypeDef *LL_ATON_Internal_Buffers_Info_Default_Empty(void) + { + return NULL; + }; + +#define _LL_ATON_INTERNAL_BUFFERS LL_ATON_Internal_Buffers_Info_Default_Empty +#else +#define _LL_ATON_INTERNAL_BUFFERS LL_ATON_Internal_Buffers_Info_Default +#endif + + /* + * Entry table to handle the offset of network entry point and + * the RT context. + */ + struct ai_reloc_network_entries + { + bool (*ec_network_init)(void); + bool (*ec_inference_init)(void); + LL_ATON_User_IO_Result_t (*input_setter)(uint32_t num, void *buffer, uint32_t size); + void *(*input_getter)(uint32_t num); + LL_ATON_User_IO_Result_t (*output_setter)(uint32_t num, void *buffer, uint32_t size); + void *(*output_getter)(uint32_t num); + const EpochBlock_ItemTypeDef *(*get_epoch_items)(void); + const LL_Buffer_InfoTypeDef *(*get_output_buffers_info)(void); + const LL_Buffer_InfoTypeDef *(*get_input_buffers_info)(void); + const LL_Buffer_InfoTypeDef *(*get_internal_buffers_info)(void); + struct ai_reloc_rt_ctx *rt_ctx; + }; + + const NN_Interface_TypeDef _itf_network = {.network_name = C_NAME}; + +#define AI_RELOC_NETWORK() \ + struct ai_reloc_rt_ctx __attribute__((used, section(".network_rt_ctx"), )) _network_rt_ctx = {0, \ + 0, \ + 0, \ + 0, \ + NULL, \ + C_NAME, \ + ACTS_SZ, \ + PARAMS_SZ, \ + EXT_RAM_SZ, \ + RUNTIME_DESC, \ + RUNTIME_VERSION, \ + RUNTIME_VERSION_DEV, \ + PARAMS_BIN_SZ, \ + PARAMS_BIN_CRC32, \ + NULL, \ + &_itf_network}; \ + const struct ai_reloc_network_entries __attribute__((used, section(".network_entries"), visibility("default"))) \ + _network_entries = { \ + .ec_network_init = &LL_ATON_EC_Network_Init_Default, \ + .ec_inference_init = &LL_ATON_EC_Inference_Init_Default, \ + .input_setter = &LL_ATON_Set_User_Input_Buffer_Default, \ + .input_getter = &LL_ATON_Get_User_Input_Buffer_Default, \ + .output_setter = &LL_ATON_Set_User_Output_Buffer_Default, \ + .output_getter = &LL_ATON_Get_User_Output_Buffer_Default, \ + .get_epoch_items = &LL_ATON_EpochBlockItems_Default, \ + .get_output_buffers_info = &LL_ATON_Output_Buffers_Info_Default, \ + .get_input_buffers_info = &LL_ATON_Input_Buffers_Info_Default, \ + .get_internal_buffers_info = &_LL_ATON_INTERNAL_BUFFERS, \ + .rt_ctx = &_network_rt_ctx, \ + }; \ + const uint32_t __attribute__((used, section(".network_flags"), visibility("default"))) _network_flags = \ + AI_RELOC_RT_SET_FLAGS(VARIANT, EXTRA); + +#else + +#define AI_RELOC_NETWORK() + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LL_ATON_RELOC_NETWORK_H__ */ diff --git a/lib/stai/libstai/include/ll_aton_runtime.h b/lib/stai/libstai/include/ll_aton_runtime.h new file mode 100644 index 000000000..6590d7bf7 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_runtime.h @@ -0,0 +1,305 @@ +/** + ****************************************************************************** + * @file ll_aton_runtime.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON LL runtime. + * @note ATON LL runtime currently assumes a single network run + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_RUNTIME_H +#define __LL_ATON_RUNTIME_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include + +#include "ll_aton_config.h" + +#include "ll_aton_NN_interface.h" +#include "ll_aton_osal.h" +#include "ll_aton_platform.h" +#include "ll_aton_util.h" + + /*** Types ***/ + + typedef EpochBlock_ItemTypeDef LL_ATON_RT_EpochBlockItem_t; + + /*** Helper Functions ***/ + + static inline void __ll_set_aton_owner(NN_Instance_TypeDef *new_owner) + { + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(new_owner != __ll_current_aton_ip_owner); + + LL_ATON_OSAL_LOCK_ATON(); + + LL_ATON_ASSERT(__ll_current_aton_ip_owner == NULL); + +#ifndef NDEBUG + extern uint32_t volatile __ll_current_wait_mask; + LL_ATON_ASSERT(__ll_current_wait_mask == 0); +#endif // NDEBUG + + __ll_current_aton_ip_owner = new_owner; + } + + static inline void __ll_clear_aton_owner(NN_Instance_TypeDef *current_owner) + { + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(current_owner == __ll_current_aton_ip_owner); + +#ifndef NDEBUG + extern uint32_t volatile __ll_current_wait_mask; + LL_ATON_ASSERT(__ll_current_wait_mask == 0); +#endif // NDEBUG + + __ll_current_aton_ip_owner = NULL; + LL_ATON_OSAL_UNLOCK_ATON(); + } + + /** + * Note: the following function may only be called at the beginning of + * `LL_ATON_Start_EpochBlock()` functions, assuming also that at that point + * no streaming engine interrupts might trigger (anymore)! + **/ + static inline void __LL_ATON_RT_Start_AtoNN_Epoch(NN_Instance_TypeDef *nn_instance) + { + LL_ATON_ASSERT(nn_instance != NULL); +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + LL_ATON_ASSERT(nn_instance->exec_state.triggered_events == + 0x0); // with the removal of parallel SW/HW epochs execution all triggered events must have been + // cleared at this point in time! +#endif + } + + static inline uint32_t __LL_ATON_RT_GetCurrEpochBlockIndex(NN_Instance_TypeDef *nn_instance) + { + const LL_ATON_RT_EpochBlockItem_t *_current_epoch_block = nn_instance->exec_state.current_epoch_block; + const LL_ATON_RT_EpochBlockItem_t *_first_epoch_block = nn_instance->exec_state.first_epoch_block; + LL_ATON_ASSERT(_first_epoch_block <= _current_epoch_block); // should never happen + + return (_current_epoch_block - _first_epoch_block); + } + + static inline void __LL_ATON_RT_SetCurrentEpochBlock(int32_t index, NN_Instance_TypeDef *nn_instance) + { +#ifndef NDEBUG + /* should never happen (assumes that a `nn_instance->exec_state.current_epoch_block++` will be + performed by the runtime immediately afterwards) */ + LL_ATON_ASSERT(index < (int32_t)(nn_instance->exec_state.nr_of_epoch_blocks - 1)); +#endif + + nn_instance->exec_state.current_epoch_block = &nn_instance->exec_state.first_epoch_block[index]; + } + + /* set wait mask(s) in interrupt controller */ + static inline void __LL_ATON_RT_SetWaitMask(uint32_t wait_mask) + { +#ifndef NDEBUG + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + + extern uint32_t volatile __ll_current_wait_mask; + __ll_current_wait_mask = wait_mask; +#endif // NDEBUG + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + wait_mask <<= ATON_STRENG_INT(0); +#ifndef LL_ATON_RT_USE_IRQ_OR_MASK + /* configure interrupt controller AND mask for epoch block */ + ATON_INTCTRL_STD_INTANDMSK_SET(~wait_mask); +#else // LL_ATON_RT_USE_IRQ_OR_MASK + /* configure interrupt controller OR mask for epoch block */ + uint32_t val = ATON_STRENG_INT_MASK(ATON_STRENG_NUM, 0, 0); // disable all streaming engine events in OR mask + // (all other events & errors are enabled) + val &= ~wait_mask; + ATON_INTCTRL_STD_INTORMSK_SET(val); +#endif // LL_ATON_RT_USE_IRQ_OR_MASK +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + } + + /* return from inserted epoch block */ + static inline void __LL_ATON_RT_RetFromLibEpochBlockArray(bool unlock, NN_Instance_TypeDef *nn_instance) + { + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + + if (!unlock) + { + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + LL_ATON_ASSERT(nn_instance == NULL); + + nn_instance = __ll_current_aton_ip_owner; + } + + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + LL_ATON_ASSERT(unlock ? EpochBlock_IsLastEpochBlock(nn_instance->exec_state.current_epoch_block) + : EpochBlock_IsEpochInternal(nn_instance->exec_state.current_epoch_block)); + LL_ATON_ASSERT(EpochBlock_IsEpochHybrid(nn_instance->exec_state.saved_current_epoch_block)); + + /* Clear owner */ + if (unlock) + { + __ll_clear_aton_owner(__ll_current_aton_ip_owner); + } + + /* set old context */ + LL_ATON_ASSERT(nn_instance->exec_state.next_epoch_block == NULL); + nn_instance->exec_state.current_epoch_block = nn_instance->exec_state.saved_current_epoch_block; + nn_instance->exec_state.first_epoch_block = nn_instance->exec_state.saved_first_epoch_block; + +#ifndef NDEBUG + nn_instance->exec_state.nr_of_epoch_blocks = nn_instance->exec_state.saved_nr_of_epoch_blocks; +#endif + + /* reset saved context */ + nn_instance->exec_state.saved_current_epoch_block = NULL; + nn_instance->exec_state.saved_first_epoch_block = NULL; +#ifndef NDEBUG + nn_instance->exec_state.saved_nr_of_epoch_blocks = 0; +#endif + } + + /*** AtoNN API Functions ***/ + + static inline void LL_ATON_RT_Insert_LibEpochBlockArray(const LL_ATON_RT_EpochBlockItem_t *new_epoch_block_array) + { + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + + // only one saved context at a time allowed! + LL_ATON_ASSERT(__ll_current_aton_ip_owner->exec_state.next_epoch_block == NULL); + LL_ATON_ASSERT(__ll_current_aton_ip_owner->exec_state.saved_current_epoch_block == NULL); + + __ll_current_aton_ip_owner->exec_state.next_epoch_block = new_epoch_block_array; + } + + /** + * Note: the following two API functions may only be called at the end of `LL_ATON_End_EpochBlock()` functions + * (otherwise the runtime will fail)!!! + **/ + static inline void LL_ATON_RT_IncCurrEpochBlock(uint32_t inc) + { + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + + uint32_t current_index = __LL_ATON_RT_GetCurrEpochBlockIndex(__ll_current_aton_ip_owner); + current_index += inc; + __LL_ATON_RT_SetCurrentEpochBlock(current_index, __ll_current_aton_ip_owner); + } + + static inline void LL_ATON_RT_DecCurrEpochBlock(uint32_t dec) + { + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + + uint32_t current_index = __LL_ATON_RT_GetCurrEpochBlockIndex(__ll_current_aton_ip_owner); + LL_ATON_ASSERT((current_index + 1) >= dec); // should never happen + int32_t new_index = current_index - dec; + __LL_ATON_RT_SetCurrentEpochBlock(new_index, __ll_current_aton_ip_owner); + } + + /*** User API Functions ***/ + + /** + * @brief Register callback for ATON runtime related events (e.g. initialization/deinitialization, see + * `LL_ATON_RT_Callbacktype_t`) + * @param rt_callback Function pointer to callback function (set to `NULL` to disable epoch tracing) + * + * @note This function must only be called when no network is currently executing! + */ + void LL_ATON_RT_SetRuntimeCallback(TraceRuntime_FuncPtr_t rt_callback); + + /** + * @brief Register callback for tracing epoch/network related events (see `LL_ATON_RT_Callbacktype_t`) + * @param epoch_block_callback Function pointer to callback function (set to `NULL` to disable epoch tracing) + * @param nn_instance Pointer to network instance for which to set the callback (may not be `NULL`) + * + * @note This function must only be called while the passed network instance is not executing + * and should be called before `LL_ATON_RT_Init_Network()`! + */ + void LL_ATON_RT_SetEpochCallback(TraceEpochBlock_FuncPtr_t epoch_block_callback, NN_Instance_TypeDef *nn_instance); + + /** + * @brief Initialise a network instance + * @param nn_instance Pointer to network instance to initialize + */ + void LL_ATON_RT_Init_Network(NN_Instance_TypeDef *nn_instance); + + /** + * @brief De-initialise a network instance + * @param nn_instance Pointer to network instance to de-initialize + */ + void LL_ATON_RT_DeInit_Network(NN_Instance_TypeDef *nn_instance); + + /** + * @brief Reset network instance for getting ready for a new inference + * @param nn_instance Pointer to network instance to initialize + * + * @note May only be called in case `LL_ATON_RT_RunEpochBlock()` returned either `LL_ATON_RT_DONE` or + * `LL_ATON_RT_NO_WFE` + */ + void LL_ATON_RT_Reset_Network(NN_Instance_TypeDef *nn_instance); + + /** + * @brief Initialize the ATON runtime + */ + void LL_ATON_RT_RuntimeInit(void); + + /** + * @brief De-initialize the ATON runtime + */ + void LL_ATON_RT_RuntimeDeInit(void); + + /** + * @brief Checks status of previously started epoch block and + * starts execution of next epoch block of the NN provided the previous epoch block has terminated + * @param nn_instance Pointer to network instance to run/continue (may not be `NULL`) + * @retval LL_ATON_RT_NO_WFE Next epoch block may be started, NN execution not finished, do not call + * `LL_ATON_OSAL_WFE()` + * @retval LL_ATON_RT_WFE Epoch block is still running, NN execution not finished, you may call + * `LL_ATON_OSAL_WFE()`. + * NOTE, that in this case no other network instance may be run/continued from within the + * same thread! + * It is entirely the user's responsibility to comply with this restriction! + * @retval LL_ATON_RT_DONE NN execution finished + */ + LL_ATON_RT_RetValues_t LL_ATON_RT_RunEpochBlock(NN_Instance_TypeDef *nn_instance); + + /** + * @brief Template for synchronously executing a single network instance (e.g. regression tests) + * @param network_instance pointer to the network instance representing the network and execution instance to execute. + * The instance object MUST have already set a valid link to a network interface. + * The user may declare/instantiate such an object by using either macro + * `LL_ATON_DECLARE_NAMED_NN_INSTANCE_AND_INTERFACE()` to create both the execution instance + * and the network interface, or macros + * `LL_ATON_DECLARE_NAMED_NN_INTERFACE()` & `LL_ATON_DECLARE_NAMED_NN_INSTANCE()` to + * create/instantiate the objects separately. + */ + void LL_ATON_RT_Main(NN_Instance_TypeDef *network_instance); + + /** @brief Dumps status of all DMAs. Used for debugging purposes + */ + void dump_dma_state(void); + +#ifdef __cplusplus +} +#endif + +#endif // __LL_ATON_RUNTIME_H diff --git a/lib/stai/libstai/include/ll_aton_util.h b/lib/stai/libstai/include/ll_aton_util.h new file mode 100644 index 000000000..7ccab4088 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_util.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file ll_aton_util.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON utility functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_UTIL_H +#define __LL_ATON_UTIL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include + +#ifndef NDEBUG + +#define LL_ATON_PRINTF(...) printf(__VA_ARGS__) +#define LL_ATON_PUTS(...) puts(__VA_ARGS__) +#define LL_ATON_FFLUSH(...) fflush(__VA_ARGS__) + +#define LL_ATON_ASSERT(...) assert(__VA_ARGS__) + +#define LL_ATON_PROFILER_PRINTF(...) printf(__VA_ARGS__) +#define LL_ATON_PROFILER_ASSERT(...) assert(__VA_ARGS__) + +#else + +#define LL_ATON_PRINTF(...) +#define LL_ATON_PUTS(...) +#define LL_ATON_FFLUSH(...) + +#define LL_ATON_ASSERT(...) +#define LL_ATON_ASSERTF(...) + +#define LL_ATON_PROFILER_PRINTF(...) +#define LL_ATON_PROFILER_ASSERT(...) + +#endif + +#define __clean_errno() (errno == 0 ? "None" : strerror(errno)) +#define __log_error(M, ...) \ + LL_ATON_PRINTF("[ERROR] (%s:%d: errno: %s) " M "\n", __FILE__, __LINE__, __clean_errno(), ##__VA_ARGS__) + +/** + * @brief Cheks a condition: if it evaluates to false, prints an error message and asserts(false). + * @param COND the condition to check. + * @param MSG the message to print if the condition evaluates to false (can be a formatted string as well) + * @param ASSERT_COND boolean parameter: if 1, this command will LL_ATON_ASSERT(COND), otherwise il will + * LL_ATON_ASSERT(0) + * @param variadic_args the (potential) variables to print in the message's formatted string, if any + */ +#define assertf(COND, ASSERT_COND, MSG, ...) \ + if (!(COND)) \ + { \ + __log_error(MSG, ##__VA_ARGS__); \ + if (ASSERT_COND) \ + LL_ATON_ASSERT(COND); \ + else \ + LL_ATON_ASSERT(0); \ + } + + /** + * @brief Helper function. Extracts bitfield from a buffer + * @param bits Pointer of the buffer to extract bits from + * @param pos Global bit position of the bitfield to extract + * @retval nbits Number of bits to extract + */ + uint32_t LL_ATON_getbits(uint32_t *bits, unsigned int pos, int nbits); + + /** + * @brief Helper function. Packs bitfield into a buffer + * @param bits Pointer of the buffer to pack bits into + * @param pos Global position of the bitfield to pack + * @retval nbits Number of bits to extract + */ + void LL_ATON_setbits(uint32_t *bits, unsigned int pos, int nbits, unsigned int val); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/stai/libstai/include/ll_aton_version.h b/lib/stai/libstai/include/ll_aton_version.h new file mode 100644 index 000000000..57c42fcd7 --- /dev/null +++ b/lib/stai/libstai/include/ll_aton_version.h @@ -0,0 +1,28 @@ +/** + ****************************************************************************** + * @file ll_aton_version.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ATON Verion information + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_ATON_VERSION_H +#define __LL_ATON_VERSION_H + +#define LL_ATON_VERSION_NAME "atonn-v1.1.0-31-g27f5d5bc" +#define LL_ATON_VERSION_MAJOR (1) +#define LL_ATON_VERSION_MINOR (1) +#define LL_ATON_VERSION_MICRO (0) +#define LL_ATON_VERSION_DEV (31) + +#endif diff --git a/lib/stai/libstai/include/ll_sw.h b/lib/stai/libstai/include/ll_sw.h new file mode 100644 index 000000000..6ba0c7e7d --- /dev/null +++ b/lib/stai/libstai/include/ll_sw.h @@ -0,0 +1,598 @@ + +/** + ****************************************************************************** + * @file ll_sw.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ll_sw low level software library module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_SW_H__ +#define __LL_SW_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "ll_sw_float.h" +#include "ll_sw_integer.h" + + // ############################ ############################ ########################### + // ############################ SUPPORTED NODES TYPES ########################### + // ############################ ############################ ########################### + + typedef enum + { + LL_SW_CONV = 0, + LL_SW_RELU, + LL_SW_PRELU, + LL_SW_THRESHOLDEDRELU, + LL_SW_ELU, + LL_SW_SELU, + LL_SW_MAXPOOL, + LL_SW_MINPOOL, + LL_SW_AVGPOOL, + LL_SW_SOFTMAX, + LL_SW_BATCHNORM, + LL_SW_LRN, + LL_SW_ARITHADD, + LL_SW_ARITHSUM, + LL_SW_ARITHSUB, + LL_SW_ARITHMUL, + LL_SW_ARITHDIV, + LL_SW_CONCAT, + LL_SW_SPLIT, + LL_SW_SLICE, + LL_SW_SIGMOID, + LL_SW_ATAN, + LL_SW_ATANH, + LL_SW_ACOS, + LL_SW_ACOSH, + LL_SW_ASIN, + LL_SW_ASINH, + LL_SW_TAN, + LL_SW_TANH, + LL_SW_COS, + LL_SW_COSH, + LL_SW_SIN, + LL_SW_SINH, + LL_SW_SQRT, + LL_SW_CEIL, + LL_SW_GATHER, + LL_SW_FLOOR, + LL_SW_EXP, + LL_SW_LOG, + LL_SW_QLINEARCONV, + LL_SW_QUANTIZELINEAR, + LL_SW_REQUANTIZELINEAR, + LL_SW_DEQUANTIZELINEAR, + LL_SW_QLINEARMATMUL, + LL_SW_GEMM, + LL_SW_RESIZE, + LL_SW_ERF, + LL_SW_POW, + LL_SW_AND, + LL_SW_OR, + LL_SW_XOR, + LL_SW_EQUAL, + LL_SW_GREATER, + LL_SW_LESS, + LL_SW_GREATEROREQUAL, + LL_SW_LESSOREQUAL, + LL_SW_CLIP, + LL_SW_HARDSIGMOID, + LL_SW_HARDMAX, + LL_SW_HARDSWISH, + LL_SW_SWISH, + LL_SW_ABS, + LL_SW_INSTANCENORM, + LL_SW_REDUCESUM, + LL_SW_REDUCEMIN, + LL_SW_REDUCEMEAN, + LL_SW_REDUCEMAX, + LL_SW_REDUCEPROD, + LL_SW_SOFTSIGN, + LL_SW_SOFTPLUS, + LL_SW_LPNORM, + LL_SW_ARGMIN, + LL_SW_ARGMAX, + LL_SW_MATMUL, + LL_SW_MIN, + LL_SW_MAX, + LL_SW_NEG, + LL_SW_RECIPROCAL, + LL_SW_MOD, + LL_SW_ROUND, + LL_SW_REDUCELOGSUMEXP, + LL_SW_SIGN, + LL_SW_TILE + } NodeType; + + // ############################ ############################ ########################### + // ############################ GENERAL HELPER NODES STRUCTS ########################### + // ############################ ############################ ########################### + + typedef struct LL_SW_State_Monitor + { + long unsigned int id[16]; + } LL_SW_State_Monitor; + + typedef struct Tensor_dim_info + { + uint32_t tensor_h; + uint32_t tensor_w; + uint32_t tensor_c; + uint32_t tensor_b; + uint32_t num_elem; + } Tensor_dim_info; + + typedef struct Tensor_stride_info + { + uint32_t h; + uint32_t w; + uint32_t c; + uint32_t b; + } Tensor_stride_info; + + typedef struct + { + unsigned char *start_offset; + } Tensor_mem_info; + + typedef struct + { + bool is_signed; + } Tensor_format_info; + + typedef struct + { + unsigned char *scale; + unsigned char *offset; + } Tensor_int_metadata_info; + + typedef struct Tensor_info + { + Tensor_dim_info dim; + Tensor_stride_info stride; + Tensor_mem_info mem; + Tensor_format_info format; + } Tensor_info; + + typedef struct General + { + NodeType type; + // info for the input tensor + Tensor_info input; + Tensor_info output; + + } General; + + // tensor quantization info + typedef struct intq_info_ + { + const float *scale; + const void *zeropoint; + } intq_info; + + typedef struct intq_info_list_ + { + uint16_t flags; /**< optional flags to store intq info attributes */ + uint16_t size; /**< number of elements in the the intq_info list */ + const intq_info *info; /**< pointer to an array of metainfo associated to the intq_info list */ + } intq_info_list; + + // ############################ ############################ ########################### + // ############################ FLOATING POINT NODES STRUCTS ########################### + // ############################ ############################ ########################### + + typedef struct Conv_sw_info + { + General general; + Tensor_info weights; + Tensor_info scratch; + Tensor_info bias; + Tensor_info weights_permuted; + int ngroup; // should it change? + long int pads[4]; + long int strides[4]; + long int dilations[2]; + } Conv_sw_info; + + typedef struct Bn_sw_info + { + General general; + Tensor_info bias; + Tensor_info scale; + Tensor_info mean; + Tensor_info var; + } Bn_sw_info; + + typedef struct Instance_normalization_sw_info + { + General general; + Tensor_info bias; + Tensor_info scale; + float epsilon; + } Instance_normalization_sw_info; + + typedef struct Argmin_sw_info + { + General general; + int axis; + int keepdims; + int select_last_index; + } Argmin_sw_info; + typedef struct Argmax_sw_info + { + General general; + int axis; + int keepdims; + int select_last_index; + } Argmax_sw_info; + + typedef struct Arith_sw_info + { + General general; + Tensor_info operand; + Tensor_info operand1; + Tensor_info operand2; + unsigned int num_of_inputs; + } Arith_sw_info; + + typedef struct Pool_sw_info + { + General general; + int ngroup; // should it change? + long int pads[4]; + long int strides[4]; + long int k_shape[2]; + bool count_include_pad; + } Pool_sw_info; + + typedef struct Lrn_sw_info + { + General general; + uint32_t size; // should it change? + float alpha; + float beta; + float bias; + } Lrn_sw_info; + + typedef struct Lpnormalization_sw_info + { + General general; + int axis; + int p; + } Lpnormalization_sw_info; + + typedef struct Sign_sw_info + { + General general; + } Sign_sw_info; + + typedef enum + { + RESIZE_ZEROS = 0x0, + RESIZE_NEAREST, + RESIZE_LINEAR, + RESIZE_CUBIC + } resize_mode; + + typedef enum + { + HALF_PIXEL = 0x0, + PYTORCH_HALF_PIXEL, + ALIGN_CORNERS, + ASYMMETRIC, + TF_HALF_PIXEL_FOR_NN, + TF_CROP_AND_RESIZE + } coord_transf_mode; + + typedef enum + { + ROUND_PREFER_FLOOR = 0x0, + ROUND_PREFER_CEIL, + FLOOR, + CEIL + } nearest_mode; + + typedef struct Resize_sw_info + { + General general; + Tensor_info scales; + Tensor_info roi; + Tensor_info sizes; + float cubic_coeff_a; /**< the coefficient 'a' used in cubic interpolation */ + bool exclude_outside; /**< exclude outside pixels flag */ + float extrapol_val; /**< used in tf_crop_and_resize cas */ + resize_mode mode; /**< resize mode */ + nearest_mode nearest_mode; /**< used in nearest mode */ + coord_transf_mode coord_transf_mode; /**< coordinate tranformation mode */ + } Resize_sw_info; + + typedef struct Activ_sw_info + { + General general; + Tensor_info operand; + float alpha; + float beta; + float gamma; + float min; + float max; + } Activ_sw_info; + + typedef struct Softmax_sw_info + { + General general; + Tensor_info scratch; + int axis; + } Softmax_sw_info; + + typedef struct Concat_sw_info + { + General general; + unsigned int concat_axis; + unsigned int num_of_inputs; + Tensor_info operand; + Tensor_info operand1; + Tensor_info operand2; + } Concat_sw_info; + + typedef struct Gather_sw_info + { + General general; + Tensor_info operand; + int axis; + } Gather_sw_info; + + typedef struct Global_pool_sw_info + { + General general; + } Global_pool_sw_info; + + typedef struct Reduce_sw_info + { + General general; + int axis; + } Reduce_sw_info; + + typedef struct Gemm_sw_info + { + General general; + Tensor_info operand_b; + Tensor_info operand_c; + float alpha; /**< alpha coefficient */ + float beta; /**< beta coefficient */ + uint8_t tA; /**< transpose A flag */ + uint8_t tB; /**< transpose B flag */ + } Gemm_sw_info; + + typedef struct Matmul_sw_info + { + General general; + Tensor_info operand_b; + } Matmul_sw_info; + typedef struct Tile_sw_info + { + General general; + int16_t repeats[4]; + } Tile_sw_info; + + // ############################ ############################ ########################### + // ############################ SCALE OFFSET NODES STRUCTS ########################### + // ############################ ############################ ########################### + + typedef enum + { + LL_SW_SSSA_PW_CONV, + LL_SW_SSSA_RGB_CONV, + LL_SW_SSSA_DW_CONV, + LL_SW_SSSA_DILATED_CONV, + LL_SW_SSSA_GENERIC_CONV, + LL_SW_GENERIC_CONV + } conv_fwd_case; + + typedef struct Qlinearconv_sw_info + { + General general; + Tensor_info weights; + Tensor_info scratch; + Tensor_info bias; + Tensor_info ws; + Tensor_info wzp; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + int ngroup; + long int pads[4]; + long int strides[4]; + long int dilations[2]; + conv_fwd_case fwd_func; + } Qlinearconv_sw_info; + + typedef struct Qlinearmatmul_sw_info + { + General general; + Tensor_info weights; + Tensor_info scratch; + Tensor_info bias; + Tensor_info ws; + Tensor_info wzp; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + } Qlinearmatmul_sw_info; + + typedef struct Gemm_integer_sw_info + { + General general; + Tensor_info weights; + Tensor_info scratch; + Tensor_info bias; + Tensor_info ws; + Tensor_info wzp; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + float alpha; /**< alpha coefficient */ + float beta; /**< beta coefficient */ + uint8_t tA; /**< transpose A flag */ + uint8_t tB; /**< transpose B flag */ + } Gemm_integer_sw_info; + + typedef struct Conv_integer_sw_info + { + General general; + Tensor_info weights; + Tensor_info scratch; + Tensor_info bias; + Tensor_info ws; + Tensor_info wzp; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + int ngroup; // should it change? + long int pads[4]; + long int strides[4]; + long int dilations[2]; + conv_fwd_case fwd_func; + } Conv_integer_sw_info; + + typedef struct Pool_integer_sw_info + { + General general; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + int ngroup; + long int pads[4]; + long int strides[4]; + long int k_shape[2]; + bool count_include_pad; + } Pool_integer_sw_info; + + typedef struct Global_pool_integer_sw_info + { + General general; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + int ngroup; + long int pads[4]; + long int strides[4]; + long int k_shape[2]; + } Global_pool_integer_sw_info; + + typedef struct Activ_integer_sw_info + { + General general; + Tensor_info operand; + Tensor_info operand_s; + Tensor_info operand_zp; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + float alpha; + float gamma; + float min; + float max; + } Activ_integer_sw_info; + + typedef struct Softmax_integer_sw_info + { + General general; + Tensor_info scratch; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + int32_t quantized_multiplier; + int32_t left_shift; + int32_t diff_min; + int32_t axis; + } Softmax_integer_sw_info; + + typedef struct Eltwise_integer_sw_info + { + General general; + Tensor_info operand; + Tensor_info operand_s; + Tensor_info operand_zp; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + unsigned int num_of_inputs; + } Eltwise_integer_sw_info; + + typedef struct Resize_integer_sw_info + { + General general; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + Tensor_info scales; + Tensor_info roi; + Tensor_info sizes; + float cubic_coeff_a; /**< the coefficient 'a' used in cubic interpolation */ + bool exclude_outside; /**< exclude outside pixels flag */ + float extrapol_val; /**< used in tf_crop_and_resize cas */ + resize_mode mode; /**< resize mode */ + nearest_mode nearest_mode; /**< used in nearest mode */ + coord_transf_mode coord_transf_mode; /**< coordinate tranformation mode */ + } Resize_integer_sw_info; + + // ############################ ########################### ########################### + // ############################ QUANT/DEQUANT NODES STRUCTS ########################### + // ############################ ########################### ########################### + + typedef struct Quantizelinear_sw_info + { + General general; + Tensor_info os; + Tensor_info ozp; + } Quantizelinear_sw_info; + + typedef struct Dequantizelinear_sw_info + { + General general; + Tensor_info is; + Tensor_info izp; + } Dequantizelinear_sw_info; + + typedef struct Requantizelinear_sw_info + { + General general; + Tensor_info is; + Tensor_info izp; + Tensor_info os; + Tensor_info ozp; + } Requantizelinear_sw_info; + +#ifdef __cplusplus +} +#endif + +#endif //__LL_SW_H__ diff --git a/lib/stai/libstai/include/ll_sw_float.h b/lib/stai/libstai/include/ll_sw_float.h new file mode 100644 index 000000000..c1212fea4 --- /dev/null +++ b/lib/stai/libstai/include/ll_sw_float.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file ll_sw_float.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ll_sw_float low level software library module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_SW_FLOAT_H__ +#define __LL_SW_FLOAT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + void ll_sw_forward_conv(void *sw_info_struct); + void ll_sw_forward_gemm(void *sw_info_struct); + void ll_sw_forward_matmul(void *sw_info_struct); + void ll_sw_forward_pool(void *sw_info_struct); + void ll_sw_forward_global_pool(void *sw_info_struct); + void ll_sw_forward_activ(void *sw_info_struct); + void ll_sw_forward_arith(void *sw_info_struct); + void ll_sw_forward_bn(void *sw_info_struct); + void ll_sw_forward_instance_normalization(void *sw_info_struct); + void ll_sw_forward_lrn(void *sw_info_struct); + void ll_sw_forward_concat(void *sw_info_struct); + void ll_sw_forward_resize(void *sw_info_struct); + void ll_sw_forward_reduce(void *sw_info_struct); + void ll_sw_forward_lpnormalization(void *sw_info_struct); + void ll_sw_forward_argmin(void *sw_info_struct); + void ll_sw_forward_argmax(void *sw_info_struct); + void ll_sw_forward_gather(void *sw_info_struct); + void ll_sw_forward_sign(void *sw_info_struct); + void ll_sw_forward_tile(void *sw_info_struct); + void ll_sw_forward_softmax(void *sw_info_struct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/stai/libstai/include/ll_sw_integer.h b/lib/stai/libstai/include/ll_sw_integer.h new file mode 100644 index 000000000..6d56a2acd --- /dev/null +++ b/lib/stai/libstai/include/ll_sw_integer.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file ll_sw_integer.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Header file of ll_sw_integer low level software library module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __LL_SW_INTEGER_H__ +#define __LL_SW_INTEGER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + void ll_sw_forward_dequantizelinear(void *sw_info_struct); + void ll_sw_forward_quantizelinear(void *sw_info_struct); + void ll_sw_forward_requantizelinear(void *sw_info_struct); + void ll_sw_forward_qlinearconv(void *sw_info_struct); + void ll_sw_forward_qlinearmatmul(void *sw_info_struct); + void ll_sw_forward_conv_integer(void *sw_info_struct); + void ll_sw_forward_pool_integer(void *sw_info_struct); + void ll_sw_forward_global_pool_integer(void *sw_info_struct); + void ll_sw_forward_activ_integer(void *sw_info_struct); + void ll_sw_forward_eltwise_integer(void *sw_info_struct); + void ll_sw_forward_gemm_integer(void *sw_info_struct); + void ll_sw_forward_softmax_integer(void *sw_info_struct); + void ll_sw_forward_resize_integer(void *sw_info_struct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/stai/libstai/include/mcu_cache.h b/lib/stai/libstai/include/mcu_cache.h new file mode 100644 index 000000000..770825616 --- /dev/null +++ b/lib/stai/libstai/include/mcu_cache.h @@ -0,0 +1,41 @@ +/** + ****************************************************************************** + * @file mcu_cache.h + * @brief Prototypes of MCU cache-handling functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __MCU_CACHE_H +#define __MCU_CACHE_H + +#include "stm32n6xx_hal.h" + +__STATIC_FORCEINLINE int mcu_cache_enabled(void) { +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_DC_Msk) return 1; /* return `1` if DCache is enabled */ +#endif // (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + + return 0; +} + + +int mcu_cache_enable(void); +int mcu_cache_disable(void); +int mcu_cache_invalidate(void); +int mcu_cache_clean(void); +int mcu_cache_clean_invalidate(void); +int mcu_cache_invalidate_range(uint32_t start_addr, uint32_t end_addr); +int mcu_cache_clean_range(uint32_t start_addr, uint32_t end_addr); +int mcu_cache_clean_invalidate_range(uint32_t start_addr, uint32_t end_addr); + +#endif // __MCU_CACHE_H diff --git a/lib/stai/libstai/include/npu_cache.h b/lib/stai/libstai/include/npu_cache.h new file mode 100644 index 000000000..89c6df534 --- /dev/null +++ b/lib/stai/libstai/include/npu_cache.h @@ -0,0 +1,38 @@ +/** + ****************************************************************************** + * @file npu_cache.h + * @brief Prototypes of NPU-cache-handling functions (CACHEAXI) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef NPU_CACHE_H +#define NPU_CACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32n6xx_hal.h" + +void npu_cache_init(void); +void npu_cache_enable(void); +void npu_cache_disable(void); +void npu_cache_invalidate(void); +void npu_cache_clean_invalidate_range(uint32_t start_addr, uint32_t end_addr); +void npu_cache_clean_range(uint32_t start_addr, uint32_t end_addr); + +#ifdef __cplusplus +} +#endif + +#endif /* NPU_CACHE_H */ diff --git a/lib/stai/libstai/include/stai.h b/lib/stai/libstai/include/stai.h new file mode 100644 index 000000000..988fe4437 --- /dev/null +++ b/lib/stai/libstai/include/stai.h @@ -0,0 +1,468 @@ +/** + ****************************************************************************** + * @file stai.h + * @author STMicroelectronics + * @brief Definitions of ST.AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STAI_H +#define STAI_H + +#include +#include + +#define STAI_API_VERSION_MAJOR (1) +#define STAI_API_VERSION_MINOR (0) +#define STAI_API_VERSION_MICRO (0) + +#define STAI_TOOLS_VERSION_MAJOR (2) +#define STAI_TOOLS_VERSION_MINOR (1) +#define STAI_TOOLS_VERSION_MICRO (0) + +/*****************************************************************************/ +#ifdef __cplusplus +#define STAI_API_DECLARE_BEGIN extern "C" { +#define STAI_API_DECLARE_END } +#else +#include +#define STAI_API_DECLARE_BEGIN /* STAI_API_DECLARE_BEGIN */ +#define STAI_API_DECLARE_END /* STAI_API_DECLARE_END */ +#endif + +/*****************************************************************************/ +#define STAI_PACK(...) \ + __VA_ARGS__ + +#define STAI_UNUSED(x) \ + (void)(x); + +#if defined(_MSC_VER) + #define STAI_API_ENTRY __declspec(dllexport) + #define STAI_ALIGNED(x) __declspec(align(x)) +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define STAI_API_ENTRY /* STAI_API_ENTRY */ + #define STAI_ALIGNED(x) _STAI_ALIGNED_X(x) + #define _STAI_ALIGNED_XY(x, y) x ## y + #define _STAI_ALIGNED_X(x) _STAI_ALIGNED_XY(_STAI_ALIGNED_,x) + #define _STAI_ALIGNED_1 _Pragma("data_alignment = 1") + #define _STAI_ALIGNED_2 _Pragma("data_alignment = 2") + #define _STAI_ALIGNED_4 _Pragma("data_alignment = 4") + #define _STAI_ALIGNED_8 _Pragma("data_alignment = 8") + #define _STAI_ALIGNED_16 _Pragma("data_alignment = 16") + #define _STAI_ALIGNED_32 _Pragma("data_alignment = 32") + #define _STAI_ALIGNED_64 _Pragma("data_alignment = 64") +#elif defined(__CC_ARM) + #define STAI_API_ENTRY __attribute__((visibility("default"))) + #define STAI_ALIGNED(x) __attribute__((aligned (x))) + /* Keil disallows anonymous union initialization by default */ + #pragma anon_unions +#elif defined(__GNUC__) + // #define STAI_API_ENTRY __attribute__((visibility("default"))) + #define STAI_API_ENTRY /* STAI_API_ENTRY */ + #define STAI_ALIGNED(x) __attribute__((aligned(x))) +#else + /* Dynamic libraries are not supported by the compiler */ + #define STAI_API_ENTRY /* STAI_API_ENTRY */ + #define STAI_ALIGNED(x) /* STAI_ALIGNED(x) */ +#endif + + +/*****************************************************************************/ +/*** Formats field getters/setters Macros Section and family enums ***/ + +typedef enum { + STAI_FORMAT_TYPE_NONE = 0x00, + STAI_FORMAT_TYPE_FLOAT = 0x01, + STAI_FORMAT_TYPE_Q = 0x02, + STAI_FORMAT_TYPE_BOOL = 0x03, +} stai_format_type; + +/* Get format type */ +#define STAI_FORMAT_GET_TYPE(format) \ + ((stai_format_type)(((format)>>17) & 0xF)) + +/* Get format sign : 0 or 1 allowed */ +#define STAI_FORMAT_GET_SIGN(format) \ + (((format)>>23) & 0x1) + +/* Get format bits - including sign, fractional bits. padding bits are not included */ +#define STAI_FORMAT_GET_BITS(format) \ + (((format)>>7) & 0x7F) + +/* Get format integer bits, i.e. integer bits are bits minus sign minus fractional bits */ +#define STAI_FORMAT_GET_IBITS(format) \ + (STAI_FORMAT_GET_BITS(format) - STAI_FORMAT_GET_FBITS(format) - STAI_FORMAT_GET_SIGN(format)) + +/* Get format fractional bits */ +#define STAI_FORMAT_GET_FBITS(format) \ + ((((format)>>0) & 0x7F) - 64) + + +/*****************************************************************************/ +#define STAI_NETWORK_CONTEXT_DECLARE(_context_name, _context_size) \ + STAI_ALIGNED(8) \ + stai_network _context_name[_context_size] = {0}; + + +/*****************************************************************************/ +/** I/O FLAGS Section **/ +#define STAI_FLAG_NONE (0x0) + +/* buffer is preallocated by system */ +#define STAI_FLAG_PREALLOCATED (0x1 << 0) + +/* buffer address field `buffer_descriptor::address` may not be used by the user and functions `get_buffer_address()`, + `set_buffer_address()` must be used instead */ +#define STAI_FLAG_INDIRECT (0x1 << 1) + +/* buffer may be replaced by user */ +#define STAI_FLAG_REPLACEABLE (0x1 << 2) + +/* buffer content may be overridden by network */ +#define STAI_FLAG_OVERRIDE (0x1 << 3) + +#define STAI_FLAG_CHANNEL_FIRST (0x1 << 6) +#define STAI_FLAG_CHANNEL_LAST (0x1 << 7) +#define STAI_FLAG_HAS_BATCH (0x1 << 8) + +/** Network FLAGS Section **/ +#define STAI_FLAG_ACTIVATIONS (0x1 << 26) +#define STAI_FLAG_INPUTS (0x1 << 27) +#define STAI_FLAG_OUTPUTS (0x1 << 28) +#define STAI_FLAG_STATES (0x1 << 29) +#define STAI_FLAG_WEIGHTS (0x1 << 30) + + +/*****************************************************************************/ +STAI_API_DECLARE_BEGIN + +/* STAI Enums Section */ +/* return codes >= STAI_ERROR_GENERIC are errors. + all codes < STAI_ERROR_GENERIC are available for managing extended set of implementation specific return codes + APIs track only 1 error: the 1st one generated while calling the APIs. No multiple error handling considered. + NOTE: need also to provide proper handling of a new return code in stai_get_return_code_name() implementation. +*/ +typedef enum { + STAI_SUCCESS = 0x000000, + STAI_RUNNING_NO_WFE = 0x000010, + STAI_RUNNING_WFE = 0x000011, + STAI_DONE = 0x000012, + STAI_ERROR_GENERIC = 0x020000, + STAI_ERROR_NETWORK_INVALID_API_ARGUMENTS = 0x020001, + STAI_ERROR_NETWORK_INVALID_CONTEXT_HANDLE = 0x030000, + STAI_ERROR_NETWORK_INVALID_CONTEXT_SIZE = 0x030001, + STAI_ERROR_NETWORK_INVALID_CONTEXT_ALIGNMENT = 0x030002, + STAI_ERROR_NETWORK_INVALID_INFO = 0x030010, + STAI_ERROR_NETWORK_INVALID_RUN = 0x030020, + STAI_ERROR_NETWORK_INVALID_RUNTIME = 0x030030, + STAI_ERROR_NETWORK_INVALID_ACTIVATIONS_PTR = 0x040000, + STAI_ERROR_NETWORK_INVALID_ACTIVATIONS_NUM = 0x040001, + STAI_ERROR_NETWORK_INVALID_IN_PTR = 0x040010, + STAI_ERROR_NETWORK_INVALID_IN_NUM = 0x040011, + STAI_ERROR_NETWORK_INVALID_OUT_PTR = 0x040020, + STAI_ERROR_NETWORK_INVALID_OUT_NUM = 0x040021, + STAI_ERROR_NETWORK_INVALID_STATES_PTR = 0x040030, + STAI_ERROR_NETWORK_INVALID_STATES_NUM = 0x040031, + STAI_ERROR_NETWORK_INVALID_WEIGHTS_PTR = 0x040040, + STAI_ERROR_NETWORK_INVALID_WEIGHTS_NUM = 0x040041, + STAI_ERROR_NETWORK_INVALID_CALLBACK = 0x040050, + STAI_ERROR_NOT_IMPLEMENTED = 0x040060, + STAI_ERROR_INVALID_BUFFER_ALIGNMENT = 0x040070, + + /* asynchronous execution errors */ + STAI_ERROR_NETWORK_STILL_RUNNING = 0x050000, + + /* platform (de-)init errors */ + STAI_ERROR_STAI_INIT_FAILED = 0x060000, + STAI_ERROR_STAI_DEINIT_FAILED = 0x060001, +} stai_return_code; + + +/*! + * @enum buffer formats enum list + * @ingroup ai_platform + * + * List of supported ai_buffer format types. + */ +typedef enum { + STAI_FORMAT_NONE = 0x00000040, + + STAI_FORMAT_FLOAT32 = 0x00821040, + STAI_FORMAT_FLOAT64 = 0x00822040, + + STAI_FORMAT_U1 = 0x000400c0, + STAI_FORMAT_U8 = 0x00040440, + STAI_FORMAT_U16 = 0x00040840, + STAI_FORMAT_U32 = 0x00041040, + STAI_FORMAT_U64 = 0x00042040, + + STAI_FORMAT_S1 = 0x008400c0, + STAI_FORMAT_S8 = 0x00840440, + STAI_FORMAT_S16 = 0x00840840, + STAI_FORMAT_S32 = 0x00841040, + STAI_FORMAT_S64 = 0x00842040, + + STAI_FORMAT_Q = 0x00840040, + STAI_FORMAT_Q7 = 0x00840447, + STAI_FORMAT_Q15 = 0x0084084f, + + STAI_FORMAT_UQ = 0x00040040, + STAI_FORMAT_UQ7 = 0x00040447, + STAI_FORMAT_UQ15 = 0x0004084f, + + STAI_FORMAT_BOOL = 0x00060440, +} stai_format; + + +typedef enum { + STAI_MODE_SYNC = 0x01, + STAI_MODE_ASYNC = 0x02, +} stai_run_mode; + + +/*****************************************************************************/ + +/* 32bit mask to code flags about e.g. I/O buffers or network properties */ +typedef int32_t stai_flags; + + +/* Opaque network handler exposed to application */ +/* it is defined as int8 to allow static memory allocation of context on app side + as an opaque uint8_t byte buffer to ensure alignment to 8 bytes */ +typedef uint8_t stai_network; + +/* Generic byte pointer for byte offset addressing */ +typedef uint8_t* stai_ptr; + +/* Generic type size */ +typedef uint32_t stai_size; + +/* Packed bits arrays are padded to 32bits */ +typedef int32_t stai_pbits; + + +/*****************************************************************************/ +typedef struct { + stai_size size; + stai_ptr const * data; +} stai_array_const_ptr; + +typedef struct { + stai_size size; + stai_ptr* data; +} stai_array_ptr; + + +typedef struct { + stai_size size; + const float* data; +} stai_array_f32; + + +typedef struct { + stai_size size; + const int8_t* data; +} stai_array_s8; + + +typedef struct { + stai_size size; + const uint8_t* data; +} stai_array_u8; + + +typedef struct { + stai_size size; + const int16_t* data; +} stai_array_s16; + + +typedef struct { + stai_size size; + const uint16_t* data; +} stai_array_u16; + + +typedef struct { + stai_size size; + const int32_t* data; +} stai_array_s32; + + +typedef struct { + stai_size size; + const uint32_t* data; +} stai_array_u32; + + +typedef struct { + uint8_t major; + uint8_t minor; + uint8_t micro; + uint8_t reserved; +} stai_version; + + +typedef stai_array_s32 stai_shape; + + +typedef struct { + stai_size size; + uintptr_t address; + stai_flags flags; + // stai_format format; +} stai_buffer; + + +typedef struct { + stai_size size_bytes; + stai_flags flags; + stai_format format; + stai_shape shape; + stai_array_f32 scale; + stai_array_s16 zeropoint; + const char* name; +} stai_tensor; + + +/*****************************************************************************/ +typedef struct { + /* Original model signature */ + const char* model_signature; + + /* C generated model info */ + const char* c_compile_datetime; + const char* c_model_name; + const char* c_model_datetime; + uint32_t c_model_signature; + + stai_version runtime_version; + stai_version tool_version; + stai_version api_version; + + /* C model macc operations */ + uint64_t n_macc; + + /* C model graph nodes */ + uint32_t n_nodes; + + /* C model flags */ + int32_t flags; + + /* Number of c model network I/O, Activations, Weights, States */ + uint16_t n_inputs; + uint16_t n_outputs; + uint16_t n_activations; + uint16_t n_weights; + uint16_t n_states; + + /* I/O networks tensors c_model info (as arrays of size n_inputs/n)outputs */ + const stai_tensor* inputs; + const stai_tensor* outputs; + + /* Activations, weights, states info */ + const stai_tensor* activations; + const stai_tensor* weights; + const stai_tensor* states; +} stai_network_info; + + +/*****************************************************************************/ +/* C struct used in file network_details.h to provide info about a node */ +typedef struct { + const int32_t id; + const int16_t type; + const stai_array_s32 input_tensors; + const stai_array_s32 output_tensors; +} stai_node_details; + + +/*****************************************************************************/ +/* C struct used in file network_details.h to provide info about the network */ +typedef struct { + const stai_tensor * const tensors; + const stai_node_details * const nodes; + const uint32_t n_nodes; +} stai_network_details; + + +/* C enum to list supported compilers */ +typedef enum { + STAI_COMPILER_ID_NONE = 0x00, + STAI_COMPILER_ID_GCC = 0x01, + STAI_COMPILER_ID_GHS = 0x10, + STAI_COMPILER_ID_HIGHTECH = 0x20, + STAI_COMPILER_ID_IAR = 0x30, + STAI_COMPILER_ID_KEIL = 0x40, + STAI_COMPILER_ID_KEIL_AC6 = 0x50, +} stai_compiler_id; + + +/* C struct to provide info about ST.AI C runtime */ +typedef struct { + stai_version api_version; /* X.Y.Z version of the ST Edge AI APIs */ + stai_version runtime_version; /* X.Y.Z version of the runtime */ + stai_version tools_version; /* version of the tool compatible with the run-time */ + uint32_t runtime_build; /* 32bit run-time identifier (i.e. build info) */ + stai_compiler_id compiler_id; /* compiler ID enum */ + const char* compiler_desc; /* string with a short description of the compiler */ +} stai_runtime_info; + + +/*****************************************************************************/ +/** STAI event callback and datatypes definition **/ + +#define STAI_EVENT_NONE (0x00) + +typedef int32_t stai_event_type; + +/** + * This is the generic network event callback signature + * @param cb_cookie is the opaque handler provided by caller (i.e. the application) + * @param event_type is the unique event type identifier + * @param event is the the opaque handler to event payload struct (Optional, may be NULL) + **/ +typedef void (*stai_event_cb)( + void* cb_cookie, + const stai_event_type event_type, + const void* event_payload); + + +/*****************************************************************************/ +/** ST.AI Runtime APIs section **/ +/** Initialize ST Edge AI runtime **/ +STAI_API_ENTRY +stai_return_code stai_runtime_init(void); + +/** De-initialize ST Edge AI runtime **/ +STAI_API_ENTRY +stai_return_code stai_runtime_deinit(void); + +/** Get ST Edge AI runtime info (versions, build, compiler, etc.) **/ +STAI_API_ENTRY +stai_return_code stai_runtime_get_info(stai_runtime_info* info); + +/** Set ST Edge AI runtime callback **/ +STAI_API_ENTRY +stai_return_code stai_runtime_set_callback(const stai_event_cb cb, void *cb_cookie); + +/*****************************************************************************/ +/** Helpers routines **/ +/** Helper API to generate a stai_format enum with provided info **/ +STAI_API_ENTRY +stai_format stai_init_format( + const stai_format_type type, const int8_t sign, const int32_t bits, const int32_t fbits); + +STAI_API_DECLARE_END + +#endif /* STAI_H */ diff --git a/lib/stai/libstai/include/stai_debug.h b/lib/stai/libstai/include/stai_debug.h new file mode 100644 index 000000000..ab3f812b3 --- /dev/null +++ b/lib/stai/libstai/include/stai_debug.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file stai_debug.h + * @author STMicroelectronics + * @brief Definitions of ST.AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STAI_DEBUG_H +#define STAI_DEBUG_H + +#include "stai.h" + +/*****************************************************************************/ +#ifdef HAS_AI_ASSERT +// Override __FILE__ macro to disable full path asserts() +// Need to add during build also -Wbuiltin-macro-redefined options to avoid warnings +#undef __FILE__ +#define __FILE__ (__builtin_strrchr("/" __BASE_FILE__, '/') + 1) + +#include + +#define STAI_ASSERT(_cond) \ + do { assert(_cond); } while(0); + +#else + +#define STAI_ASSERT(_cond) \ + do { /* STAI_ASSERT() */ } while (0); + +#endif /* HAS_AI_ASSERT */ + +#define STAI_PRINT(_fmt, ...) \ + do { /* STAI_PRINT() */ } while (0); + + +STAI_API_DECLARE_BEGIN + + +/*****************************************************************************/ + +STAI_API_ENTRY +const char* stai_get_return_code_name(const stai_return_code code); + + +STAI_API_ENTRY +const char* stai_get_format_type_name(const stai_format_type fmt_type); + + +STAI_API_ENTRY +const char* stai_get_format_name(const stai_format fmt); + + +STAI_API_DECLARE_END + +#endif /* STAI_DEBUG_H */ diff --git a/lib/stai/libstai/include/stai_events.h b/lib/stai/libstai/include/stai_events.h new file mode 100644 index 000000000..0a85107c3 --- /dev/null +++ b/lib/stai/libstai/include/stai_events.h @@ -0,0 +1,51 @@ +/** + ****************************************************************************** + * @file stai_events.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of ST.AI registered events + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STAI_EVENTS_H +#define STAI_EVENTS_H +#include "stai.h" + + +STAI_API_DECLARE_BEGIN + +/*****************************************************************************/ +/** STAI event IDs definition + * This is the list of stai supported events that could be triggered by network + * callback. Each event has an associated datastruct that provides the payload + * for a give event. All supported payloads are defined int the @ref stai_event union. + * New events could be defined by: + * 1) Add a new entry in stai_event_type with unique type id + * 2) Add a new datastruct definition fpr the new event that specified its payload + * 3) Add a pointer to this payload into stai_event union to make it public + **/ +#define STAI_EVENT_NODE_START (0x01) +#define STAI_EVENT_NODE_STOP (0x02) + + +/*****************************************************************************/ +/** STAI events definitions + * ADD YOUR EVENT HERE AND ADD TO STAI_EVENT if public + **/ +typedef struct { + int32_t node_id; + stai_array_const_ptr buffers; +} stai_event_node_start_stop; + + +STAI_API_DECLARE_END + +#endif /* STAI_EVENTS_H */ diff --git a/lib/stai/libstai/ll_aton/ai_reloc_network.c b/lib/stai/libstai/ll_aton/ai_reloc_network.c new file mode 100644 index 000000000..5e1dd7103 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ai_reloc_network.c @@ -0,0 +1,795 @@ +/** + ****************************************************************************** + * @file ai_reloc_network.h + * @author MCD/AIS Team + * @brief Relocatable network support + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019,2021 STMicroelectronics. + * All rights reserved.

+ * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include + +#if defined(STM32F7) +#include "stm32f7xx_hal.h" +#endif + +#if defined(STM32H7) +#include "stm32h7xx_hal.h" +#endif + +#include + +/* ----------------------------------------------------------------------------- + * APP definitions + * ----------------------------------------------------------------------------- + */ + +#if !defined(APP_DEBUG) +#define APP_DEBUG 1 /* 1: enable debug trace (printf-based) */ +#endif + +#if !defined(AI_RELOC_RT_MCU_CHECKING) +#define AI_RELOC_RT_MCU_CHECKING 1 /* 1: enable RT MCU checking */ +#endif + +#ifndef AI_RELOC_MALLOC +#define AI_RELOC_MALLOC(_size) malloc(_size) +#endif + +#ifndef AI_RELOC_FREE +#define AI_RELOC_FREE(_ptr) free(_ptr) +#endif + + +/* ----------------------------------------------------------------------------- + * AI RELOC definitions to manage the binary image + * ----------------------------------------------------------------------------- + */ + +#define AI_RELOC_MAGIC (0x4E49424E) + +#define AI_RELOC_FLASH_BASE (0x20000000) +#define AI_RELOC_RAM_BASE (0x80000000) + +#define AI_RELOC_MASK_OFFSET (0x0FFFFFFF) + +#define AI_RELOC_GET_OFFSET(laddr) (uintptr_t)((laddr) & AI_RELOC_MASK_OFFSET) + +#define AI_RELOC_GET_ADDR(_base, _off) ((uintptr_t)_base + AI_RELOC_GET_OFFSET(_off)) +#define AI_RELOC_GET_VAL(_base, _off) ((uintptr_t)_base + AI_RELOC_GET_OFFSET(_off)) + +#define AI_RELOC_IN_RAM(val) \ + ((val & 0xF0000000) == AI_RELOC_RAM_BASE) + +#define AI_RELOC_IN_FLASH(val) \ + ((val & 0xF0000000) == AI_RELOC_FLASH_BASE) + +#define AI_RELOC_ROUND_UP(_v) (((_v) + 3) & ~3) + +#define AI_RELOC_IS_ALIGNED(_v) (((_v) & 0x3) == 0) + +struct bin_hdr { + uint32_t magic; + uint32_t flags; +}; + +struct sec_info { + uint32_t data_start; + uint32_t data_end; + uint32_t data_data; + + uint32_t bss_start; + uint32_t bss_end; + + uint32_t got_start; + uint32_t got_end; + uint32_t rel_start; + uint32_t rel_end; + uint32_t weights_start; + uint32_t weights_end; +}; + +struct net_entries { + uint32_t create; + uint32_t init; + uint32_t init_v2; + uint32_t run; + uint32_t report; + uint32_t error; + uint32_t destroy; + uint32_t forward; + uint32_t plt_obs_register; + uint32_t plt_obs_unregister; + uint32_t plt_obs_node_info; + uint32_t ctx; +}; + +struct ai_reloc_bin_hdr { + struct bin_hdr hdr; + struct sec_info sect; + struct net_entries vec; +}; + +#define APP_FLASH_RELOC(laddr, offset)\ + (laddr + (offset & AI_RELOC_MASK_OFFSET)) + +/* + * Naked function to set the R9 value and to call the entry point + * without a "prolog" and "epilog". + * + * r0 = ROM base address + * r1 = offset of the function + * r2 = RAM base address (used for R9) + * r3 = arg1 -> r0 + * sp[0] = arg2 -> r1 + * sp[0+4] = arg3 -> r2 + * + */ + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* GNU compiler */ + +static uintptr_t __attribute__((naked)) call_with_r9(const void *base, + uint32_t offset, void *data, + uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + asm volatile ( + "add r12, r0, r1 \n" + "mov r0, r3 \n" + "ldr r1, [sp] \n" + "push {r9, lr} \n" + "mov r9, r2 \n" + "ldr r2, [sp, #12] \n" + "blx r12 \n" + "pop {r9, pc} \n" + ); + + return 0; // dummy to fool gcc +} + +#elif defined(__ICCARM__) /* IAR compiler */ + +__task __irq uintptr_t call_with_r9(const void *base, + uint32_t offset, void *data, + uintptr_t arg1, uintptr_t arg2, uintptr_t arg3); +__task __irq uintptr_t call_with_r9(const void *base, + uint32_t offset, void *data, + uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + asm volatile ( + "add r12, r0, r1 \n" + "mov r0, r3 \n" + "ldr r1, [sp] \n" + "push {r9, lr} \n" + "mov r9, r2 \n" + "ldr r2, [sp, #12] \n" + "blx r12 \n" + "pop {r9, pc} \n" + ); + + return 0; // dummy to fool gcc +} + +#elif defined(__CC_ARM) /* Arm compiler 4/5 */ + +__asm uintptr_t call_with_r9(const void *base, + uint32_t offset, void *data, + uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + add r12, r0, r1 + mov r0, r3 + ldr r1, [sp] + push {r9, lr} + mov r9, r2 + ldr r2, [sp, #12] + blx r12 + pop {r9, pc} +} + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* Arm Compiler 6 */ + +static uintptr_t __attribute__((naked)) call_with_r9(const void *base, + uint32_t offset, void *data, + uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + __asm ( + "add r12, r0, r1 \n" + "mov r0, r3 \n" + "ldr r1, [sp] \n" + "push {r9, lr} \n" + "mov r9, r2 \n" + "ldr r2, [sp, #12] \n" + "blx r12 \n" + "pop {r9, pc} \n" + ); + +} + +#else + +#error Unknown compiler. + +#endif + + + +AI_DECLARE_STATIC +ai_handle _ai_reloc_network_data_weights_get(const void* obj) +{ + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)obj; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0)) + return AI_HANDLE_NULL; + + if ((bin->sect.weights_start == bin->sect.weights_end) || + (bin->sect.weights_start == 0)) + return AI_HANDLE_NULL; + + const uint32_t off = AI_RELOC_GET_OFFSET(bin->sect.weights_start); + + return (ai_handle)((uintptr_t)obj + off); +} + +AI_DECLARE_STATIC +uint32_t _ai_reloc_code_size(const void* obj) +{ + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)obj; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0)) + return 0; + + const ai_size ro_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(bin->sect.data_data)); + + return ro_sz; +} + +AI_DECLARE_STATIC +ai_size _ai_reloc_requested_ram_size(const void* obj, uint32_t mode) +{ + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)obj; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0)) + return 0; + + const ai_size rw_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(bin->sect.bss_end)); + const ai_size ro_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(bin->sect.data_data)); + + if ((mode & AI_RELOC_RT_LOAD_MODE_XIP) == AI_RELOC_RT_LOAD_MODE_XIP) + return rw_sz; + else + return rw_sz + ro_sz; +} + + +#if defined(APP_DEBUG) && APP_DEBUG == 1 +AI_DECLARE_STATIC +char* _magic_to_str(uint32_t val) { + static char res[5]; + res[3] = val >> 24; + res[2] = val >> 16; + res[1] = val >> 8; + res[0] = val >> 0; + return res; +} +#endif + +#define _CPUID *(volatile uint32_t *)(0xE000ED00) +#define _CPACR *(volatile uint32_t *)(0xE000ED88) + +#define _CPUID_PART_NUMBER (0xFFF << 4) /* Part Number */ +#define _CPACR_CPx (0xF << 20) /* CP1 & CP0 bits */ + +#define _GET_PART_NUMBER() (int)((_CPUID & _CPUID_PART_NUMBER) >> 4) +#define _GET_FPU_CPX() (int)((_CPACR & _CPACR_CPx) >> 20) + +AI_DECLARE_STATIC +int ai_reloc_rt_mcu_checking(const struct ai_reloc_bin_hdr *bin) +{ +#if defined(AI_RELOC_RT_MCU_CHECKING) && AI_RELOC_RT_MCU_CHECKING == 1 + const uint32_t flags = bin->hdr.flags; + const uint32_t cpuid = _GET_PART_NUMBER(); + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0)) { +#if defined(APP_DEBUG) && APP_DEBUG == 1 + printf("AI RELOC ERROR: Binary is invalid\r\n"); +#endif + return -1; + } + + if (cpuid != AI_RELOC_RT_GET_CPUID(flags)) { +#if defined(APP_DEBUG) && APP_DEBUG == 1 + printf("AI RELOC ERROR: CPUID is invalid 0x%03X (expected 0x%03X)\r\n", (int)cpuid, + (int)AI_RELOC_RT_GET_CPUID(flags)); +#endif + return -2; + } + if (AI_RELOC_RT_FPU_USED(flags)) { + if (!_GET_FPU_CPX()) { +#if defined(APP_DEBUG) && APP_DEBUG == 1 + printf("AI RELOC ERROR: FPU should be initialized\r\n"); +#endif + return -3; + } + } +#endif /* AI_RELOC_RT_MCU_CHECKING == 1 */ + return 0; +} + +AI_DECLARE_STATIC +void ai_reloc_log_hdr(const struct ai_reloc_bin_hdr *bin, uint32_t mode) +{ +#if defined(APP_DEBUG) && APP_DEBUG == 1 + ai_rel_network_info rt_info; + + ai_rel_network_rt_get_info(bin, &rt_info); + + printf("\r\nAI binary network image (0x%08x)\r\n", (int)bin); + printf(" c-name : \"%s\"\r\n", rt_info.c_name); + printf(" activations : %d\r\n", (int)rt_info.acts_sz); + printf(" weights : %d\r\n", (int)rt_info.weights_sz); + printf(" ram size : %d for XIP mode (%d for COPY mode)\r\n", + (int)rt_info.rt_ram_xip, + (int)rt_info.rt_ram_copy); + printf(" requested mode : %s\r\n", + mode == AI_RELOC_RT_LOAD_MODE_XIP?"XIP":"COPY"); + + printf("\r\n Binary header\r\n"); + printf(" magic : 0x%08X (%s)\r\n", (int)bin->hdr.magic, + _magic_to_str(bin->hdr.magic)); + printf(" flags : v%d.%d (0x%08X)\r\n", + AI_RELOC_RT_GET_MAJOR(rt_info.variant), + AI_RELOC_RT_GET_MINOR(rt_info.variant), + (int)rt_info.variant); + printf(" size : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.rel_end)); + printf(" .txt/.rodata : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.data_data)); + printf(" .data : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.data_end) - + (int)AI_RELOC_GET_OFFSET(bin->sect.data_start)); + printf(" .got : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.got_end) - + (int)AI_RELOC_GET_OFFSET(bin->sect.got_start)); + printf(" .rel : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.rel_end) - + (int)AI_RELOC_GET_OFFSET(bin->sect.rel_start)); + printf(" .bss : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.bss_end) - + (int)AI_RELOC_GET_OFFSET(bin->sect.bss_start)); + printf(" .weights : %d (0x%08x)\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.weights_end) - + (int)AI_RELOC_GET_OFFSET(bin->sect.weights_start), (int)rt_info.weights); + + printf("\r\n Runtime\r\n"); + int fpu_is_enabled = _GET_FPU_CPX(); + printf(" CPUID : 0x%03x (FPU is %s)\r\n", _GET_PART_NUMBER(), + fpu_is_enabled?"enabled":"disabled"); + + printf("\r\n"); +#endif /* APP_DEBUG == 1 */ +} + +/* + * Low level function to update the GOT section in RAM. + */ +AI_DECLARE_STATIC +int _ai_reloc_got_update(const struct ai_reloc_bin_hdr *bin, void* ram_addr) +{ + uint32_t *got_start = (uint32_t *)AI_RELOC_GET_ADDR(ram_addr, bin->sect.got_start); + uint32_t *got_end = (uint32_t *)AI_RELOC_GET_ADDR(ram_addr, bin->sect.got_end); + + for (uint32_t *p = got_start; p < got_end; p++) { + uint32_t val = *p; + if AI_RELOC_IN_RAM(val) { + val = (uint32_t)AI_RELOC_GET_VAL(ram_addr, val); + } else if AI_RELOC_IN_FLASH(val) { + val = (uint32_t)AI_RELOC_GET_VAL(bin, val); + } else if (val != 0) { +#if defined(APP_DEBUG) && APP_DEBUG == 1 + printf("AI RELOC ERROR: _ai_reloc_got_update - val is invalid %08x\r\n", (int)val); +#endif + return -1; + } + *p = val; + } + return 0; +} + +/* + * Low level function to update the DATA section in RAM. + */ +AI_DECLARE_STATIC +int _ai_reloc_ram_update(const struct ai_reloc_bin_hdr *bin, void* ram_addr, const void* obj) +{ + uint32_t *rel_start = (uint32_t *)AI_RELOC_GET_ADDR(obj, bin->sect.rel_start); + uint32_t *rel_end = (uint32_t *)AI_RELOC_GET_ADDR(obj, bin->sect.rel_end); + + for (uint32_t *p = rel_start; p < rel_end; p++) { + uint32_t add = *p; + uint32_t val = *(uint32_t*)AI_RELOC_GET_VAL(ram_addr, add); + if AI_RELOC_IN_RAM(val) { + val = (uint32_t)AI_RELOC_GET_VAL(ram_addr, val); + } else if AI_RELOC_IN_FLASH(val) { + val = (uint32_t)AI_RELOC_GET_VAL(bin, val); + } else if (val != 0) { +#if defined(APP_DEBUG) && APP_DEBUG == 1 + printf("AI RELOC ERROR: _ai_reloc_ram_update - val is invalid %08x\r\n", (int)val); +#endif + return -1; + } + uint32_t *dest = (uint32_t *)AI_RELOC_GET_ADDR(ram_addr, add); + *dest = val; + } + return 0; +} + +/* + * Low level function to install the relocatable code. + * + * - 'obj' address of the memory-mapped binary object. + * - ram_addr/ram_size indicates the location (and the size) + * of the buffer destination to install and to update the data/got + * and bss sections for XIP mode or including the hdr/text and + * rodata sections for COPY mode. rel section is only used + * at init time. Note: if ram_addr and/or ram_size are NULL, + * requested RAM size is dynamically allocated in the system + * heap (AI_RELOC_MALLOC/AI_RELOC_FREE macros). + * - 'mode' indicates the load mode: XIP or COPY. + * - if successful, 0 is returned and the 'hdl' parameter is + * updated with the address of an internal opaque structure. This + * handle should be used for the other function ai_reloc_XX. + * + * Loading mode: + * + * XIP mode - only the RW and got sections are copied in RAM + * data/got section is updated according the ram/rom@ + * and the info from the rel section. + * code (text/rodata section) is executed-in-place + * COPY mode - code is also copied in RAM + * + * + * obj@ ram_addr@ + * ----------- rom_addr@ ----------- + * [ hdr ] [ data ] + * [ text ] [ got ] + * [ rodata ] -- XIP mode -> [ bss ] + * ----------- ----------- + * [ data ] + * [ got ] + * [ rel ] + * ----------- + * ram_addr@ -> rom_addr@ + * ----------- + * [ hd ] + * -- COPY mode --> [ text ] + * [ rodata ] + * ----------- new ram_addr@ + * [ data ] + * [ got ] + * [ bss ] + * ----------- + * + */ +AI_DECLARE_STATIC +int _ai_reloc_install(const void* obj, void* ram_addr, size_t ram_size, + ai_handle* hdl, uint32_t mode) +{ + uint32_t state = AI_RELOC_RT_STATE_NOT_INITIALIZED; + struct ai_reloc_bin_hdr *rom_addr = (struct ai_reloc_bin_hdr *)obj; + const uint32_t req_ram_size = _ai_reloc_requested_ram_size(obj, mode); + void *ram_alloc_addr = NULL; + + /* RT checking */ + if (ai_reloc_rt_mcu_checking(rom_addr)) { + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + /* Parameter check */ + if (!req_ram_size) + return AI_RELOC_RT_ERR_INVALID_BIN; + + if (((mode != AI_RELOC_RT_LOAD_MODE_XIP) && + (mode != AI_RELOC_RT_LOAD_MODE_COPY)) || (!hdl)) + return AI_RELOC_RT_ERR_PARAM; + + if (ram_addr && ram_size && !AI_RELOC_IS_ALIGNED((uintptr_t)ram_addr)) + return AI_RELOC_RT_ERR_MEMORY; + + /* Allocate memory if necessary */ + if (!ram_addr || !ram_size) { + ram_size = req_ram_size; + ram_alloc_addr = AI_RELOC_MALLOC(ram_size + 4); + if (ram_alloc_addr) { + ram_addr = (void *)AI_RELOC_ROUND_UP((uintptr_t)ram_alloc_addr); + } + else + return AI_RELOC_RT_ERR_MEMORY; + } + else if (req_ram_size > ram_size) + return AI_RELOC_RT_ERR_MEMORY; + + if (mode & AI_RELOC_RT_LOAD_MODE_COPY) { + /* Copy hrd, txt and rodata sections in RAM */ + const uint32_t ro_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(rom_addr->sect.data_data)); + memcpy(ram_addr, obj, ro_sz); + +#if defined(STM32F7) || defined(STM32H7) + SCB_CleanDCache(); +#endif + + /* Update the rom_addr/ram_addr pointers */ + rom_addr = (struct ai_reloc_bin_hdr *)(ram_addr); + ram_addr = (void *)((uintptr_t)ram_addr + ro_sz); + } + else { + state |= AI_RELOC_RT_STATE_XIP_MODE; + } + + ai_reloc_log_hdr(rom_addr, mode); + + const uintptr_t bss_start = AI_RELOC_GET_ADDR(ram_addr, rom_addr->sect.bss_start); + const uint32_t bss_size = rom_addr->sect.bss_end - rom_addr->sect.bss_start; + const uintptr_t src_data = AI_RELOC_GET_ADDR(obj, rom_addr->sect.data_data); + const uint32_t rw_sz = AI_RELOC_GET_OFFSET(rom_addr->sect.bss_end); + + /* Copy the data section, including the got section */ + memcpy(ram_addr, (const void*)src_data, rw_sz - bss_size); + + /* Clear the bss section */ + memset((void *)bss_start, 0, bss_size); + + /* Update the relocation table and data */ + if (_ai_reloc_got_update(rom_addr, ram_addr)) + return AI_RELOC_RT_ERR_INVALID_BIN; + + if (_ai_reloc_ram_update(rom_addr, ram_addr, obj)) + return AI_RELOC_RT_ERR_INVALID_BIN; + + /* Update the RT context */ + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)AI_RELOC_GET_ADDR(ram_addr, + rom_addr->vec.ctx); + + rt_ctx->rom_addr = (uint32_t)rom_addr; + rt_ctx->ram_addr = (uint32_t)ram_addr; + rt_ctx->ram_alloc_addr = (uint32_t)ram_alloc_addr; + rt_ctx->state = (state | AI_RELOC_RT_STATE_INITIALIZED); + + *hdl = (ai_handle)(rt_ctx); + + return 0; +} + +AI_DECLARE_STATIC +int _ai_rel_check_handler(ai_handle hdl) +{ + if (!hdl) + return -1; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || !(rt_ctx->state & AI_RELOC_RT_STATE_INITIALIZED)) + return -1; + + return 0; +} + +AI_DECLARE_STATIC +ai_error _ai_rel_create(ai_handle* hdl, const ai_buffer* network_config) +{ + if (!hdl || _ai_rel_check_handler(*hdl)) { + ai_error err = {AI_ERROR_INVALID_HANDLE, AI_ERROR_CODE_INVALID_PTR}; + return err; + } + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)*hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.create), + (void *)rt_ctx->ram_addr, (uintptr_t)&rt_ctx->network, (uintptr_t)network_config, 0); + + const ai_error err = { .type = (res & 0xFF), .code = (res & 0xFFFFFF00) >> 8 }; + return err; +} + +/* ----------------------------------------------------------------------------- + * Public API implementation + * ----------------------------------------------------------------------------- + */ + +AI_API_ENTRY +ai_error ai_rel_network_rt_get_info(const void* obj, ai_rel_network_info* rt) +{ + struct ai_reloc_bin_hdr *bin = (struct ai_reloc_bin_hdr *)obj; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0) || (!rt)) { +#if defined(APP_DEBUG) && APP_DEBUG == 1 + printf("AI RELOC ERROR: Binary is invalid\r\n"); +#endif + ai_error err = {AI_ERROR_INVALID_HANDLE, AI_ERROR_CODE_INVALID_PTR}; + return err; + } + + struct ai_reloc_rt_ctx *rt_ctx = + (struct ai_reloc_rt_ctx *)AI_RELOC_GET_ADDR(bin + + AI_RELOC_GET_OFFSET(bin->sect.data_data), bin->vec.ctx); + + const char *c_name = (const char *)AI_RELOC_GET_ADDR(bin, + AI_RELOC_GET_OFFSET((int)rt_ctx->c_name)); + + rt->c_name = c_name; + rt->variant = (ai_u32)bin->hdr.flags; + rt->weights = _ai_reloc_network_data_weights_get(obj); + rt->weights_sz = (ai_size)rt_ctx->weights_size; + rt->acts_sz = (ai_size)rt_ctx->act_size; + rt->rt_ram_xip = _ai_reloc_requested_ram_size(obj, AI_RELOC_RT_LOAD_MODE_XIP); + rt->rt_ram_copy = _ai_reloc_requested_ram_size(obj, AI_RELOC_RT_LOAD_MODE_COPY); + rt->code_sz = _ai_reloc_code_size(obj); + + ai_error err = {AI_ERROR_NONE, AI_ERROR_CODE_NONE}; + return err; +} + +AI_API_ENTRY +ai_error ai_rel_network_load_and_create(const void* obj, ai_handle ram_addr, + ai_size ram_size, uint32_t mode, + ai_handle* hdl) +{ + if (!hdl || !obj) { + ai_error err = {AI_ERROR_INVALID_HANDLE, AI_ERROR_CODE_INVALID_PTR}; + return err; + } + + int res = _ai_reloc_install(obj, ram_addr, ram_size, hdl, mode); + + if (!res) { + return _ai_rel_create(hdl, NULL); + } + + ai_error err = {AI_ERROR_CREATE_FAILED, AI_ERROR_CODE_NETWORK}; + + return err; +} + +AI_API_ENTRY +ai_bool ai_rel_network_init(ai_handle hdl, const ai_handle *weights, const ai_handle *act) +{ + if (_ai_rel_check_handler(hdl)) + return false; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.init_v2), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, (uintptr_t)weights, (uintptr_t)act); + + return res?true:false; +} + +AI_API_ENTRY +ai_bool ai_rel_network_get_report(ai_handle hdl, ai_network_report* report) +{ + if (_ai_rel_check_handler(hdl)) + return false; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.report), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, (uintptr_t)report, 0); + + return res?true:false; +} + +AI_API_ENTRY +ai_error ai_rel_network_get_error(ai_handle hdl) +{ + if (_ai_rel_check_handler(hdl)) { + ai_error err = {AI_ERROR_INVALID_HANDLE, AI_ERROR_CODE_NETWORK}; + return err; + } + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.error), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, 0, 0); + + const ai_error err = { .type = (res & 0xFF), .code = (res & 0xFFFFFF00) >> 8 } ; + return err; +} + +AI_API_ENTRY +ai_i32 ai_rel_network_run(ai_handle hdl, const ai_buffer* input, ai_buffer* output) +{ + if (_ai_rel_check_handler(hdl)) + return 0; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.run), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, + (uintptr_t)input, (uintptr_t)output); + + return (ai_i32)res; +} + +AI_API_ENTRY +ai_handle ai_rel_network_destroy(ai_handle hdl) +{ + if (!_ai_rel_check_handler(hdl)) + return 0; + + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.destroy), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, 0, 0); + + rt_ctx->network = (ai_handle)res; + if (rt_ctx->ram_alloc_addr) { + AI_RELOC_FREE((void *)rt_ctx->ram_alloc_addr); + } + rt_ctx->state = AI_RELOC_RT_STATE_INITIALIZED; + + return rt_ctx->network; +} + +AI_API_ENTRY +ai_bool ai_rel_platform_observer_register(ai_handle hdl, + ai_observer_node_cb cb, ai_handle cookie, ai_u32 flags) +{ + if (_ai_rel_check_handler(hdl)) + return false; + + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + rt_ctx->obs_ctx.on_node = cb; + rt_ctx->obs_ctx.cookie = (ai_handle)cookie; + rt_ctx->obs_ctx.flags = flags; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, + AI_RELOC_GET_OFFSET(bin->vec.plt_obs_register), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, (uintptr_t)&rt_ctx->obs_ctx, 0); + + return res?true:false; +} + +AI_API_ENTRY +ai_bool ai_rel_platform_observer_unregister(ai_handle hdl, + ai_observer_node_cb cb, ai_handle cookie) +{ + if (_ai_rel_check_handler(hdl)) + return false; + + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, + AI_RELOC_GET_OFFSET(bin->vec.plt_obs_unregister), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, (uintptr_t)&rt_ctx->obs_ctx, 0); + + return res?true:false; +} + +AI_API_ENTRY +ai_bool ai_rel_platform_observer_node_info(ai_handle hdl, + ai_observer_node *node_info) +{ + if (_ai_rel_check_handler(hdl)) + return false; + + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, + AI_RELOC_GET_OFFSET(bin->vec.plt_obs_node_info), + (void *)rt_ctx->ram_addr, (uintptr_t)rt_ctx->network, (uintptr_t)node_info, 0); + + return res?true:false; +} + diff --git a/lib/stai/libstai/ll_aton/ecloader.c b/lib/stai/libstai/ll_aton/ecloader.c new file mode 100644 index 000000000..95eec1803 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ecloader.c @@ -0,0 +1,547 @@ +/** + ****************************************************************************** + * @file ecloader.h + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Loader for Epoch Controller BLobs. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined(USE_FILES) +#include +#endif + +#include +#include + +#include "ecloader.h" +#include "ll_aton_util.h" + +#ifdef USE_FILES + +/** + * Return the size of a file. + * + * \param[in] path is the path of the file + * + * \return the size of file having path equal to \e path, or -1 in case of errors + */ + +long ec_file_size(const char *path) +{ + FILE *file = fopen(path, "r+"); + + if (file == NULL) + { + LL_ATON_PRINTF("Error: Cannot open file '%s'\n", path); + + return -1; + } + + fseek(file, 0, SEEK_END); + + long pos = ftell(file); + + fclose(file); + + return pos; +} + +/** + * Copy a file to memory. + * + * \param[in] path is the path of the file + * \param[in] ptr is the pointer to the memory area (which must be already allocated and large enough) where the file + * must be copied + * + * \retval \e true on success + * \retval \e false otherwise + */ + +bool ec_copy_file(const char *path, uint8_t *ptr) +{ + FILE *file = fopen(path, "r+"); + + if (file == NULL) + { + LL_ATON_PRINTF("Error: Cannot open file '%s'\n", path); + + return false; + } + + while (true) + { + uint8_t byte; + + if (fread(&byte, sizeof(uint8_t), 1, file) != 1) + break; + + *ptr = byte; + + ptr++; + } + + fclose(file); + + return true; +} + +#endif /* #ifdef USE_FILES */ + +/** + * Copy to memory an Epoch Controller program contained in an Epoch Controller binary. + * The magic number and the length of the program will be copied as well. + * + * \param[in] file_ptr is the pointer to the memory area containing the whole Epoch Controller binary + * \param[out] program is the pointer to the memory area (which must be already allocated and large enough) that + * will contain the Epoch Controller program + * \param[in,out] program_size is the pointer to the variable that, if \e + * program is not \e NULL, contains the size in terms of 32-bit words of the memory area pointed by \e program or, if \e + * program is \e NULL, will contain the size in terms of 32-bit words of the Epoch Controller program (including magic + * number and program length): + * - program == NULL && program_size != NULL ==> the size of the program section + * must be retrieved + * - program != NULL && program_size != NULL ==> the program section must be copied + * (\e program_size is used for checking that the allocated space is sufficient) + * - program != NULL && program_size == NULL ==> not allowed + * - program == NULL && program_size == NULL ==> not allowed + * + * \retval \e true on success + * \retval \e false otherwise + */ + +bool ec_copy_program(const uint8_t *file_ptr, ECInstr *program, unsigned int *program_size) +{ + const uint8_t *ptr = file_ptr; + + // read the file header + + ECFileEntry magic = 0; + ECFileEntry program_offset = 0; + + magic = *((ECFileEntry *)ptr); + + ptr += sizeof(ECFileEntry); + + if (magic != ECASM_BINARY_MAGIC) + { + LL_ATON_PRINTF("Error: Epoch Controller binary is invalid\n"); + + return false; + } + + ptr = file_ptr + sizeof(ECFileEntry) + 2 * sizeof(ECFileEntry); + + program_offset = *((ECFileEntry *)ptr); + + ptr += sizeof(ECFileEntry); + + if (program_offset == 0) + { + LL_ATON_PRINTF("Error: Program section offset in binary file is invalid\n"); + + return false; + } + + // read the Epoch Controller program section + + ptr = file_ptr + program_offset; + + ECInstr program_magic = 0; + + program_magic = *((ECInstr *)ptr); + + ptr += sizeof(ECInstr); + + if (program_magic != ECASM_PROGRAM_MAGIC) + { + LL_ATON_PRINTF("Error: Invalid magic number of Epoch Controller program\n"); + + return false; + } + + ECInstr size = 0; + + size = *((ECInstr *)ptr); + + ptr += sizeof(ECInstr); + + if (program == NULL) + { + if (program_size != NULL) + *program_size = size + 2; + } + else + { + if ((((intptr_t)program) % 8) != 0) + { + LL_ATON_PRINTF("Error: Memory allocated for the Epoch Controller program must be 8-byte aligned\n"); + + return false; + } + + if (program_size == NULL) + { + LL_ATON_PRINTF("Error: Size of memory allocated for the Epoch Controller program has not been specified\n"); + + return false; + } + + if (*program_size < (size + 2)) + { + LL_ATON_PRINTF( + "Error: Memory allocated for the Epoch Controller program is not sufficient (at least space for %" PRIu32 + " 32-bit words must be allocated)\n", + size + 2); + + return false; + } + + program[0] = program_magic; + program[1] = size; + + for (unsigned int i = 0; i < size; i++, ptr += sizeof(ECInstr)) + program[i + 2] = *((ECInstr *)ptr); + } + + return true; +} + +/** + * Copy to memory the relocation table contained in an Epoch Controller binary. + * + * \param[in] file_ptr is the pointer to the memory area containing the whole Epoch Controller binary + * \param[out] reloc_table is the pointer to the memory area (which must be already allocated and large enough) + * that will contain the Epoch Controller program + * \param[in,out] reloc_table_size is the pointer to the variable that, + * if \e reloc_table is not \e NULL, contains the size in terms of 32-bit words of the memory area pointed by \e + * reloc_table or, if \e reloc_table is \e NULL, will contain the size in terms of 32-bit words of the relocation table: + * - reloc_table == NULL && reloc_table_size != NULL ==> the size of the relocation + * table must be retrieved + * - reloc_table != NULL && reloc_table_size != NULL ==> the relocation table must + * be copied + * (\e reloc_table_size is used for checking that the allocated space is sufficient) + * - reloc_table != NULL && reloc_table_size == NULL ==> not allowed + * - reloc_table == NULL && reloc_table_size == NULL ==> not allowed + * + * \retval \e true on success + * \retval \e false otherwise + */ + +bool ec_copy_reloc_table(const uint8_t *file_ptr, ECFileEntry *reloc_table, unsigned int *reloc_table_size) +{ + const ECFileEntry *ptr = (const ECFileEntry *)file_ptr; + + // read the file header + + ECFileEntry magic = *ptr++; + + if (magic != ECASM_BINARY_MAGIC) + { + LL_ATON_PRINTF("Error: Epoch Controller binary is invalid\n"); + + return false; + } + + ECFileEntry reloc_table_offset = *((ECFileEntry *)ptr++); + ECFileEntry debug_offset = *((ECFileEntry *)ptr++); + ECFileEntry program_offset = *((ECFileEntry *)ptr++); + + if (reloc_table_offset == 0) + { + LL_ATON_PRINTF("Error: Relocation table is not present\n"); + + return false; + } + + ECFileEntry size = ((debug_offset == 0) ? program_offset : debug_offset) - reloc_table_offset; + + if ((size % 4) != 0) + { + LL_ATON_PRINTF("Error: Size of the relocation table of an Epoch Controller program must be 4-byte aligned\n"); + + return false; + } + + size /= 4; + + if (reloc_table == NULL) + { + if (reloc_table_size != NULL) + *reloc_table_size = size; + } + else + { + if ((((intptr_t)reloc_table) % 4) != 0) + { + LL_ATON_PRINTF( + "Error: Memory allocated for the relocation table of the Epoch Controller program must be 4-byte aligned\n"); + + return false; + } + + if (reloc_table_size == NULL) + { + LL_ATON_PRINTF( + "Error: Size of memory allocated for the relocation table of the Epoch Controller has not been specified\n"); + + return false; + } + + if (*reloc_table_size < size) + { + LL_ATON_PRINTF( + "Error: Memory allocated for the relocation table of the Epoch Controller program is not sufficient (at " + "least space for %" PRIu32 " 32-bit words must be allocated)\n", + size); + + return false; + } + + memcpy(reloc_table, file_ptr + reloc_table_offset, size * 4); + } + + return true; +} + +/** + * Get the pointer to the relocation table contained in an Epoch Controller binary. + * + * \param[in] file_ptr is the pointer to the memory area containing the whole Epoch Controller binary + * + * \return the pointer to the relocation table contained in the Epoch Controller binary pointed by \e file_ptr, or \e + * NULL if the Epoch Controller binary does not contain any relocation table or on errors + */ + +const ECFileEntry *ec_get_reloc_table_ptr(const uint8_t *file_ptr) +{ + const uint8_t *ptr = file_ptr; + + // read the file header + + ECFileEntry magic = 0; + ECFileEntry reloc_offset = 0; + + magic = *((ECFileEntry *)ptr); + + ptr += sizeof(ECFileEntry); + + if (magic != ECASM_BINARY_MAGIC) + { + LL_ATON_PRINTF("Error: Epoch Controller binary is invalid\n"); + + return NULL; + } + + reloc_offset = *((ECFileEntry *)ptr); + + return (reloc_offset == 0) ? NULL : (const ECFileEntry *)(file_ptr + reloc_offset); +} + +/** + * Return the number of different relocations contained in an Epoch Controller binary. + * + * \param[in] reloc_table_ptr is the pointer to the relocation table (contained in an Epoch Controller binary or + * copied from it) + * + * \return the number of different relocations contained in the relocation table contained in the memory area starting + * at \e reloc_table_ptr + */ + +unsigned int ec_get_num_relocs(const ECFileEntry *reloc_table_ptr) +{ + ECFileEntry size = 0; + + // read the relocation table, if any + if (reloc_table_ptr != NULL) + size = *reloc_table_ptr; + + return size; +} + +/** + * Return the identifier of a relocation contained in an Epoch Controller binary. + * + * \param[in] reloc_table_ptr is the pointer to the relocation table (contained in an Epoch Controller binary or + * copied from it) + * \param[in] idx is the index of the relocation whose identifier must be retrieved + * + * \return the identifier of relocation having index \e idx among the relocations contained in the relocation table + * contained in the memory area starting at \e reloc_table_ptr, or \e NULL if that relocation does not exist + */ + +const char *ec_get_reloc_id(const ECFileEntry *reloc_table_ptr, unsigned int idx) +{ + // read the relocation table, if any + if (reloc_table_ptr != NULL) + { + const ECFileEntry *ptr = reloc_table_ptr; + + ECFileEntry size = *ptr; + + if (idx < size) + { + ptr = reloc_table_ptr + 3 * idx + 1; + + ECFileEntry offset = *ptr; + + return (const char *)((const uint8_t *)reloc_table_ptr + offset); + } + } + + return NULL; +} + +/** + * Relocate all the values associated with a relocation specified by using an index. + * + * \param[in] reloc_table_ptr is the pointer to the relocation table (contained in an Epoch Controller binary or + * copied from it) + * \param[out] program is the pointer to the memory area containing the Epoch Controller + * program (that will be patched) + * \param[in] idx is the index of the relocation whose values must be + * relocated + * \param[in] base is the offset that must be added to the values to be relocated + * \param[in,out] prev_base is the pointer to a memory location containing the previous value of the base address + * associated with this relocation (this memory location will be updated with \e base if this function completes + * successfully) + * + * \retval \e true on success + * \retval \e false otherwise + */ + +bool ec_reloc(const ECFileEntry *reloc_table_ptr, ECInstr *program, unsigned int idx, ECAddr base, ECAddr *prev_base) +{ + if (reloc_table_ptr == NULL) + { + LL_ATON_PRINTF("Error: Cannot relocate because the pointer to the Epoch Controller relocation table is invalid\n"); + + return false; + } + + if (base == *prev_base) + return true; + + const ECFileEntry *ptr = reloc_table_ptr; + + ECFileEntry size = *ptr; + + if (idx < size) + { + ptr = reloc_table_ptr + 3 * idx + 2; + + ECFileEntry num = *ptr++; + + ECFileEntry offset = *ptr; + + if ((offset % sizeof(ECFileEntry)) != 0) + { + LL_ATON_PRINTF("Error: Offset %lu in Epoch Controller binary is invalid\n", (unsigned long)offset); + + return false; + } + + ptr = (const ECFileEntry *)((const uint8_t *)reloc_table_ptr + offset); + + for (unsigned int i = 0; i < num; i++) + { + ECFileEntry offset = *ptr++; + + // offset is from the real beginning of the EC program, that is, from the first real instruction (the one + // following the magic number of the EC program and its size) + program[offset + 2] += base - *prev_base; + } + } + + *prev_base = base; + + return true; +} + +/** + * Relocate all the values associated with a relocation specified by using an identifier. + * + * \param[in] reloc_table_ptr is the pointer to the relocation table (contained in an Epoch Controller binary or + * copied from it) + * \param[out] program is the pointer to the memory area containing the Epoch Controller + * program (that will be patched) + * \param[in] id is the identifier of the relocation whose values must be relocated + * \param[in] base is the offset that must be added to the values to be relocated + * \param[in,out] prev_base is the pointer to a memory location containing the previous value of the base address + * associated with this relocation (this memory location will be updated with \e base if this function completes + * successfully) + * + * \retval \e true on success + * \retval \e false otherwise + */ + +bool ec_reloc_by_id(const ECFileEntry *reloc_table_ptr, ECInstr *program, const char *id, ECAddr base, + ECAddr *prev_base) +{ + if (reloc_table_ptr == NULL) + { + LL_ATON_PRINTF("Error: Cannot relocate because the pointer to the Epoch Controller relocation table is invalid\n"); + + return false; + } + + if (base == *prev_base) + return true; + + const ECFileEntry *ptr = reloc_table_ptr; + + ECFileEntry size = *ptr; + + for (unsigned int n = 0; n < size; n++) + { + ptr = reloc_table_ptr + 3 * n + 1; + + ECFileEntry offset = *ptr; + + const char *tmp_id = (const char *)((const uint8_t *)reloc_table_ptr + offset); + + if (strcmp(id, tmp_id) == 0) + { + ptr++; + + ECFileEntry num = *ptr++; + + ECFileEntry offset = *ptr; + + if ((offset % sizeof(ECFileEntry)) != 0) + { + LL_ATON_PRINTF("Error: Offset %lu in Epoch Controller binary is invalid\n", (unsigned long)offset); + + return false; + } + + ptr = (const ECFileEntry *)((const uint8_t *)reloc_table_ptr + offset); + + for (unsigned int i = 0; i < num; i++) + { + ECFileEntry offset = *ptr++; + + // offset is from the real beginning of the EC program, that is, from the first real instruction (the one + // following the magic number of the EC program and its size) + program[offset + 2] += base - *prev_base; + } + + *prev_base = base; + + return true; + } + } + + LL_ATON_PRINTF("Error: Relocation symbol '%s' not found in Epoch Controller relocation table\n", id); + + return false; +} diff --git a/lib/stai/libstai/ll_aton/ll_aton.c b/lib/stai/libstai/ll_aton/ll_aton.c new file mode 100644 index 000000000..c112d0196 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton.c @@ -0,0 +1,2680 @@ +/** + ****************************************************************************** + * @file ll_aton.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include +#include +#include + +#include "ll_aton.h" +#include "ll_aton_caches_interface.h" +#include "ll_aton_util.h" + +#define ATONN_CONST_SRCPORT(S, J, U, I, P) ATON_##S##_##J##_LINK_##U##_##I##_##P +#define ATONN_CONST_DSTPORT(S, J, U, I, P) ATON_##S##_DST_OFFSET(J, ATON_##S##_##J##_DST##U##_##I##_##P##_IDX) + +#ifdef ATON_CONVACC_NUM +static uint32_t Conv_ctrl_bits[ATON_CONVACC_NUM]; // this is an hack FIXME !!! +#endif + +#if (ATON_POOL_VERSION_MAJOR_DT < 1) || ((ATON_POOL_VERSION_MAJOR_DT == 1) && (ATON_POOL_VERSION_MINOR_DT <= 0)) +#define POOL_RC14 /* Pooling unit is not yet patched with respect to auto-clearing of `CLR` bit and consistent SW/HW \ + reset values */ +#endif + +#define ASSERT_UNITS_VERS_W_MSG(unitname, rtl_unitver) \ + do \ + { \ + rtl_unitver = ATON_##unitname##_VERSION_GET(0); \ + } while (rtl_unitver == 0); \ + assertf(ATON_##unitname##_VERSION_GET_TYPE(rtl_unitver) == ATON_##unitname##_VERSION_TYPE_DT && \ + ATON_##unitname##_VERSION_GET_MAJOR(rtl_unitver) == ATON_##unitname##_VERSION_MAJOR_DT && \ + ATON_##unitname##_VERSION_GET_MINOR(rtl_unitver) == ATON_##unitname##_VERSION_MINOR_DT, \ + 0, \ + "%s unit ver mismatch: RTL:t=%" PRIu32 ",ver=%" PRIu32 ".%" PRIu32 " ATON.h:t=%" PRIu32 ",ver=%" PRIu32 \ + ".%" PRIu32 "\n\r", \ + #unitname, ATON_##unitname##_VERSION_GET_TYPE(rtl_unitver), \ + ATON_##unitname##_VERSION_GET_MAJOR(rtl_unitver), ATON_##unitname##_VERSION_GET_MINOR(rtl_unitver), \ + (uint32_t)ATON_##unitname##_VERSION_TYPE_DT, (uint32_t)ATON_##unitname##_VERSION_MAJOR_DT, \ + (uint32_t)ATON_##unitname##_VERSION_MINOR_DT) + +/** @defgroup Simple watchdog management functions. + * Used to exit from LL_Streng_Wait() in case epoch locks + * @{ + */ + +static inline void ll_aton_static_checks(void) +{ + static char done = 0; + + if (done != 0) + return; + done = 1; + +#define ASSERT_ATONN_SRCPORT(S, J, U, I, P) \ + LL_ATON_ASSERT(ATONN_CONST_SRCPORT(S, J, U, I, P) == __atonn_getSrcPortID(S, J, U, I, P)) +#define ASSERT_ATONN_DSTPORT(S, J, U, I, P) \ + LL_ATON_ASSERT(ATONN_CONST_DSTPORT(S, J, U, I, P) == __atonn_getDstPortID(S, J, U, I, P)) + +#if ATON_STRENG_NUM > 1 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, STRENG, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, STRENG, 1, 0); +#endif +#if ATON_STRENG_NUM > 2 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, STRENG, 2, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, STRENG, 2, 0); +#endif + +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) + +#if ATON_CONVACC_NUM > 1 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, CONVACC, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, CONVACC, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, CONVACC, 1, 1); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, CONVACC, 1, 2); +#endif + +#if ATON_CONVACC_NUM > 2 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, CONVACC, 2, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, CONVACC, 2, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, CONVACC, 2, 1); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, CONVACC, 2, 2); +#endif + +#if ATON_POOL_NUM > 1 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, POOL, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, POOL, 1, 0); +#endif + +#if ATON_ARITH_NUM > 1 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, ARITH, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, ARITH, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, ARITH, 1, 1); +#endif + +#if ATON_ACTIV_NUM > 1 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, ACTIV, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, ACTIV, 1, 0); +#endif + +#if ATON_DECUN_NUM > 1 + ASSERT_ATONN_SRCPORT(STRSWITCH, 0, DECUN, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, DECUN, 1, 0); + ASSERT_ATONN_DSTPORT(STRSWITCH, 0, DECUN, 1, 1); +#endif + +#endif // (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) + +#undef ASSERT_ATONN_SRCPORT +#undef ASSERT_ATONN_DSTPORT +} + +unsigned char *LL_Address_Physical2Virtual(unsigned char *address) +{ + return ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(address); +} + +unsigned char *LL_Address_Virtual2Physical(unsigned char *address) +{ + return ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(address); +} + +/** + * @brief Starts watchdog + * @param timeout Watchdog timeout in cycles + * @retval ATON Error code + */ +LL_ATON_WEAK int startWatchdog(uint32_t timeout) +{ + (void)timeout; + + return 0; +} + +/** + * @brief Checkes whether watchdog has expired or not + * @retval ATON Error code + */ +LL_ATON_WEAK int checkWatchdog(void) +{ + return 0; +} + +/** + * @} + */ + +/** + * @brief ATON global initialization. Initializes clocks and bus interfaces. Must be called before anything else + * @retval Always zero + */ +int LL_ATON_Init(void) +{ + uint32_t t; + int i; + + ll_aton_static_checks(); + + /* Clear pipeline */ + t = ATON_CLKCTRL_CTRL_GET(0); + t = ATON_CLKCTRL_CTRL_SET_CLR(t, 1); + ATON_CLKCTRL_CTRL_SET(0, t); + + /* Enable all ATON clocks */ + ATON_CLKCTRL_CTRL_SET(0, 1); + ATON_CLKCTRL_AGATES0_SET(0, 0xffffffff); + ATON_CLKCTRL_AGATES1_SET(0, 0xffffffff); + +#if (LL_ATON_ENABLE_CLOCK_GATING == 1) +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) + ATON_CLKCTRL_BGATES_SET(0, (1 << ATON_EPOCHCTRL_CLKB_CLK(0))); +#else + ATON_CLKCTRL_BGATES_SET(0, 0x0); +#endif +#else + ATON_CLKCTRL_BGATES_SET(0, 0xffffffff); +#endif + +#ifdef ATON_CLKCTRL_BGATES1_OFFSET + ATON_CLKCTRL_BGATES1_SET(0, 0xffffffff); +#endif + + /* Check that RTL and ATON.h match. Only check first unit */ + ASSERT_UNITS_VERS_W_MSG(STRENG, t); + +#ifdef ATON_CONVACC_NUM + ASSERT_UNITS_VERS_W_MSG(CONVACC, t); +#endif + +#ifdef ATON_POOL_NUM + ASSERT_UNITS_VERS_W_MSG(POOL, t); +#endif + +#ifdef ATON_ARITH_NUM + ASSERT_UNITS_VERS_W_MSG(ARITH, t); +#endif + +#ifdef ATON_ACTIV_NUM + ASSERT_UNITS_VERS_W_MSG(ACTIV, t); +#endif + +#ifdef ATON_DECUN_NUM + ASSERT_UNITS_VERS_W_MSG(DECUN, t); +#endif + +#ifdef ATON_EPOCHCTRL_VERSION_TYPE_DT + ASSERT_UNITS_VERS_W_MSG(EPOCHCTRL, t); +#endif + +#ifdef ATON_RECBUF_VERSION_TYPE_DT + ASSERT_UNITS_VERS_W_MSG(RECBUF, t); +#endif + +#ifdef ATON_STRENG64_NUM + ASSERT_UNITS_VERS_W_MSG(STRENG64, t); +#endif + +#ifdef ATON_STRSWITCH64_NUM + ASSERT_UNITS_VERS_W_MSG(STRSWITCH64, t); +#endif + +#ifdef ATON_STRSWITCH_VC_NUM + ASSERT_UNITS_VERS_W_MSG(STRSWITCH_VC, t); +#endif + +#ifdef ATON_IMC_NUM + ASSERT_UNITS_VERS_W_MSG(IMC, t); +#endif + + ASSERT_UNITS_VERS_W_MSG(CLKCTRL, t); + + ASSERT_UNITS_VERS_W_MSG(INTCTRL, t); + + ASSERT_UNITS_VERS_W_MSG(STRSWITCH, t); + + ASSERT_UNITS_VERS_W_MSG(BUSIF, t); + + /* Enable Bus Interfaces */ + for (i = 0; i < ATON_BUSIF_NUM; i++) + { + ATON_BUSIF_CTRL_SET(i, 1); + } + + /* Enable Interrupt Controller */ + ATON_INTCTRL_CTRL_SET(0, 1); + + return 0; +} + +/** + * @brief ATON global de-initialization. Must be called at the very end + * @retval Always zero + */ +int LL_ATON_DeInit(void) +{ + int i; + + /* Disable Interrupt Controller */ + ATON_INTCTRL_CTRL_SET(0, 0); + + /* Disable Bus Interfaces */ + for (i = 0; i < ATON_BUSIF_NUM; i++) + { + ATON_BUSIF_CTRL_SET(i, 0); + } + + /* Disable all ATON clocks */ + ATON_CLKCTRL_AGATES0_SET(0, 0); + ATON_CLKCTRL_AGATES1_SET(0, 0); + ATON_CLKCTRL_BGATES_SET(0, 0); +#ifdef ATON_CLKCTRL_BGATES1_OFFSET + ATON_CLKCTRL_BGATES1_SET(0, 0); +#endif + ATON_CLKCTRL_CTRL_SET(0, 0); + + return 0; +} + +/** + * @brief Enables a set of ATON units + * @param LL_ATON_EnableUnits_InitStruct Array of units to enable + * @param n Lenght of the initialization array + * @retval Error code + * @todo Add boundary checks + */ +int LL_ATON_EnableUnits_Init(const LL_ATON_EnableUnits_InitTypeDef *LL_ATON_EnableUnits_InitStruct, int n) +{ + int i; + enum AccelUnitsType unitType; + uint32_t unitId; + + for (i = 0; i < n; i++) + { + unitType = LL_ATON_EnableUnits_InitStruct[i].unit.unit_type; + unitId = LL_ATON_EnableUnits_InitStruct[i].unit.unit_num; + + switch (unitType) + { + case STRENG: + ATON_ENABLE(STRENG, unitId); + break; + +#ifdef ATON_STRENG64_NUM + case STRENG64: + ATON_ENABLE(STRENG64, unitId); + break; +#endif + +#ifdef ATON_CONVACC_NUM + case CONVACC: +#if 0 + ATON_ENABLE(CONVACC, unitId); +#else + ATON_CONVACC_CTRL_SET(unitId, ATON_CONVACC_CTRL_SET_EN(Conv_ctrl_bits[unitId], 1)); +#endif + break; +#endif + +#ifdef ATON_DECUN_NUM + case DECUN: + ATON_ENABLE(DECUN, unitId); + break; +#endif + +#ifdef ATON_ACTIV_NUM + case ACTIV: + ATON_ENABLE(ACTIV, unitId); + break; +#endif + +#ifdef ATON_ARITH_NUM + case ARITH: + ATON_ENABLE(ARITH, unitId); + break; +#endif + +#ifdef ATON_POOL_NUM + case POOL: +#ifdef POOL_RC14 + ATON_POOL_CTRL_SET(unitId, ATON_POOL_CTRL_SET_EN(ATON_POOL_CTRL_GET(unitId), 1)); +#else // !POOL_RC14 + ATON_ENABLE(POOL, unitId); +#endif // !POOL_RC14 + break; +#endif +#ifdef ATON_RECBUF_NUM + case RECBUF: + ATON_ENABLE(RECBUF, unitId); + break; +#endif + + default: + break; + } + } + + return 0; +} + +/** + * @brief Disables a set of ATON units + * @param LL_ATON_DisableUnits_InitTypeDef Array of units to disable + * @param n Length of the initialization array + * @retval Error code + */ +int LL_ATON_DisableUnits_Init(const LL_ATON_DisableUnits_InitTypeDef *LL_ATON_DisableUnits_InitStruct, int n) +{ + int i; + enum AccelUnitsType unitType; + uint32_t unitId; + uint32_t t; + + for (i = 0; i < n; i++) + { + unitType = LL_ATON_DisableUnits_InitStruct[i].unit.unit_type; + unitId = LL_ATON_DisableUnits_InitStruct[i].unit.unit_num; + + switch (unitType) + { +#ifdef ATON_STRENG_NUM + case STRENG: + ATON_DISABLE_CLR_CONFCLR(STRENG, unitId); + LL_ATON_DisableClock(ATON_STRENG_CLKB_CLK(unitId)); + break; +#endif + +#ifdef ATON_CONVACC_NUM + case CONVACC: + ATON_DISABLE_CLR_CONFCLR(CONVACC, unitId); + LL_ATON_DisableClock(ATON_CONVACC_CLKB_CLK(unitId)); + break; +#endif + +#ifdef ATON_DECUN_NUM + case DECUN: + ATON_DISABLE_CLR_CONFCLR(DECUN, unitId); + LL_ATON_DisableClock(ATON_DECUN_CLKB_CLK(unitId)); + break; +#endif + +#ifdef ATON_ACTIV_NUM + case ACTIV: + ATON_DISABLE_CLR_CONFCLR(ACTIV, unitId); + LL_ATON_DisableClock(ATON_ACTIV_CLKB_CLK(unitId)); + break; +#endif + +#ifdef ATON_ARITH_NUM + case ARITH: + ATON_DISABLE_CLR_CONFCLR(ARITH, unitId); + LL_ATON_DisableClock(ATON_ARITH_CLKB_CLK(unitId)); + break; +#endif + +#ifdef ATON_POOL_NUM + case POOL: +#ifdef POOL_RC14 + ATON_POOL_CTRL_SET(unitId, ATON_POOL_CTRL_SET_EN(ATON_POOL_CTRL_GET(unitId), 0)); +#else // !POOL_RC14 + ATON_DISABLE_CLR_CONFCLR(POOL, unitId); +#endif // !POOL_RC14 + + LL_ATON_DisableClock(ATON_POOL_CLKB_CLK(unitId)); + break; +#endif + +#ifdef ATON_RECBUF_NUM + case RECBUF: + ATON_DISABLE_CLR_CONFCLR(RECBUF, unitId); + LL_ATON_DisableClock(ATON_RECBUF_CLKB_CLK(unitId)); + break; +#endif + + default: + return LL_ATON_INVALID_PARAM; + } + } + + return LL_ATON_OK; +} + +/** + * @brief Waits for streaming engine(s) to become idle + * @param mask Bitmask of DMA identifiers + * @retval Error code + */ +int LL_Streng_Wait(uint32_t mask) +{ + int i; + uint32_t enableFlags; + + startWatchdog(ATON_EPOCH_TIMEOUT); + + do + { + enableFlags = 0; + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if (mask & (1 << i)) + { + enableFlags |= (ATON_STRENG_CTRL_GET(i) & (1U << ATON_STRENG_CTRL_RUNNING_LSB)); + } + } + + LL_ATON_ASSERT(checkWatchdog() == 0); + + } while (enableFlags); + + return LL_ATON_OK; +} + +/** + * @brief Configures streaming engine + * @param id Streaming engine identifier [0..ATON_STRENG_NUM-1] + * @param conf Pointer to structure(s) describing initialization parameters + * @param n Number of elements in initialization structure array + * @retval error code. E.g.: Invalid ID, invalid parameters, not idle,.. + */ +int LL_Streng_TensorInit(int id, const LL_Streng_TensorInitTypeDef *conf, int n) +{ + uint32_t t; + + /* deferred register values */ + uint32_t t_streng_strd = ATON_STRENG_STRD_DT; + uint32_t t_streng_cid_cache = ATON_STRENG_CID_CACHE_DT; + uint32_t t_streng_event = ATON_STRENG_EVENT_DT; + + if (id >= ATON_STRENG_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_STRENG_CLKB_CLK(id)); + +#define _LL_min(x, y) ((x) > (y) ? (y) : (x)) + + if (n != 1) + return -1; + // if (conf->dir == 0 && (conf->nbits_in > conf->nbits_out)) return -1; +#ifndef ATON_IMC_NUM + if (conf->nbits_in > 24 || conf->nbits_out > 24) + return -1; +#endif + + t = ATON_STRENG_CTRL_DT; + t = ATON_STRENG_CTRL_SET_DIR(t, (conf->dir != 0)); + t = ATON_STRENG_CTRL_SET_RAW(t, (conf->raw != 0)); +#ifdef ATON_STRENG_CTRL_SET_RAW_OUT + t = ATON_STRENG_CTRL_SET_RAW_OUT(t, conf->raw_out); +#else + /* Hardware feature not supported */ + LL_ATON_ASSERT(conf->raw_out == 0); +#endif + t = ATON_STRENG_CTRL_SET_NOBLK(t, (conf->noblk != 0)); + t = ATON_STRENG_CTRL_SET_NOINC(t, (conf->noinc == 1)); + t = ATON_STRENG_CTRL_SET_SINGLE(t, conf->frame_tot_cnt == 1); + t = ATON_STRENG_CTRL_SET_CONT(t, conf->continuous == 1); + t = ATON_STRENG_CTRL_SET_LSBMODE(t, conf->align_right == 1); + t = ATON_STRENG_CTRL_SET_SIGNEXT(t, conf->align_right == 1 && conf->nbits_unsigned == 0); + + int ch_bits[3] = {0, 0, 0}; + int in_bits[3]; + int out_bits[3]; + int nbits_out = conf->nbits_out; + int nbits_in = conf->nbits_in; + + // case 0: bus -> stream --> in_bits > out_bits -> use FRONT_GAP + // | + // case 1: --> in_bits <= out_bits -> use lanes but valid for out_bits=8,16,24 for other bit length out + // is right shifted by (8,16,24) - out_bits + // + // case 2: stream->bus --> in_bits >= out_bits -> use lanes but valid for in_bits=8,16,24 for other bit length out is + // right shifted by (8,16,24) - out_bits + // | + // case 3: --> in_bits < out_bits -> use FRONT_GAP + + int io_case = ((conf->dir != 0) << 1); + io_case += (conf->dir == 0 ? (conf->nbits_in <= conf->nbits_out) : (conf->nbits_in < conf->nbits_out)); + + switch (io_case) + { + case 0: // in_bits > out_bits && bus->stream + // must use FRONT_GAP + { + if (conf->mem_lsb) + t_streng_strd = ATON_STRENG_STRD_SET_FGAP(t_streng_strd, (nbits_in - nbits_out)); + else + t_streng_strd = ATON_STRENG_STRD_SET_BGAP(t_streng_strd, (nbits_in - nbits_out)); + nbits_in = nbits_out; + } + // intentional fall through + case 1: // in_bits <= out_bits && bus->stream + in_bits[0] = _LL_min(8, nbits_in); + in_bits[1] = nbits_in > 8 ? _LL_min(8, nbits_in - 8) : 0; + in_bits[2] = nbits_in > 16 ? _LL_min(8, nbits_in - 16) : 0; + if (conf->align_right) + { + ch_bits[0] = in_bits[0]; + ch_bits[1] = in_bits[1]; + ch_bits[2] = in_bits[2]; + } + else + { + if (nbits_out > 16) + { + ch_bits[2] = in_bits[0]; + ch_bits[1] = in_bits[1]; + ch_bits[0] = in_bits[2]; + } + else if (nbits_out > 8) + { + ch_bits[1] = in_bits[0]; + ch_bits[0] = in_bits[1]; + } // N.B. the DMA stuffs the bits to the left of the channel + else + ch_bits[0] = in_bits[0]; + } + break; + case 3: // in_bits < out_bits && stream->bus + { + if (conf->mem_lsb) + t_streng_strd = ATON_STRENG_STRD_SET_FGAP(t_streng_strd, (nbits_out - nbits_in)); + else + t_streng_strd = ATON_STRENG_STRD_SET_BGAP(t_streng_strd, (nbits_out - nbits_in)); + nbits_out = nbits_in; + } + // intentional fall through + case 2: // in_bits >= out_bits && stream->bus + out_bits[0] = _LL_min(8, nbits_out); + out_bits[1] = nbits_out > 8 ? _LL_min(8, nbits_out - 8) : 0; + out_bits[2] = nbits_out > 16 ? _LL_min(8, nbits_out - 16) : 0; + if (conf->align_right) + { + ch_bits[0] = out_bits[0]; + ch_bits[1] = out_bits[1]; + ch_bits[2] = out_bits[2]; + } + else + { + if (nbits_in > 16) + { + ch_bits[2] = out_bits[0]; + ch_bits[1] = out_bits[1]; + ch_bits[0] = out_bits[2]; + } + else if (nbits_in > 8) + { + ch_bits[1] = out_bits[0]; + ch_bits[0] = out_bits[1]; + } // N.B. the DMA stuffs the bits to the left of the channel + else + ch_bits[0] = out_bits[0]; + } + break; + } + +/* Take care of N64 single size register. TODO: double check this */ +#ifdef ATON_STRENG_CTRL_SET_SIZE1 + t = ATON_STRENG_CTRL_SET_SIZE0(t, ch_bits[0]); + t = ATON_STRENG_CTRL_SET_SIZE1(t, ch_bits[1]); + t = ATON_STRENG_CTRL_SET_SIZE2(t, ch_bits[2]); +#else + if (conf->dir) + t = ATON_STRENG_CTRL_SET_SIZE0(t, conf->nbits_out); + else + t = ATON_STRENG_CTRL_SET_SIZE0(t, conf->nbits_in); +#endif + + ATON_STRENG_CTRL_SET(id, t); + + // ATON_STRENG_ADDR_SET(id, conf->addr_start.i); + ATON_REG_WRITE_RELOC(((volatile uint32_t *)(uintptr_t)ATON_STRENG_ADDR_ADDR(id)), conf->addr_base.i, + conf->offset_start); + + if (conf->raw) + { + if (conf->frame_count) + t = conf->frame_count; + else + { + // N.B. end - start must contain padding if nbits_in is not power of two + t = (LL_Streng_len(conf) * 8) / (conf->dir == 0 ? conf->nbits_in : conf->nbits_out); + } + ATON_STRENG_FSIZE_SET(id, t); + } + else + { + t = ATON_STRENG_FSIZE_DT; + t = ATON_STRENG_FSIZE_SET_WIDTH(t, conf->fwidth); + t = ATON_STRENG_FSIZE_SET_HEIGHT(t, conf->fheight); + ATON_STRENG_FSIZE_SET(id, t); + + uint32_t line_offset = conf->line_offset == 0 ? conf->fwidth * conf->batch_offset : conf->line_offset; + // if line_offset is left=0 then it's computed from the standard geometry of lines and batch + t_streng_strd = ATON_STRENG_STRD_SET_LOFF(t_streng_strd, line_offset); + +#if defined(ATON_STRENG_CID_CACHE_SET_LOFF_MSB) + t = t_streng_cid_cache; + t = ATON_STRENG_CID_CACHE_SET_LOFF_MSB(t, (line_offset >> ATON_STRENG_STRD_LOFF_W)); + t_streng_cid_cache = t; +#endif + + t = ATON_STRENG_DEPTH_DT; + t = ATON_STRENG_DEPTH_SET_SIZE(t, conf->batch_depth); + t = ATON_STRENG_DEPTH_SET_OFFSET(t, conf->batch_offset); + ATON_STRENG_DEPTH_SET(id, t); + } + + ATON_STRENG_FRPTOFF_SET(id, conf->loop_offset); + ATON_STRENG_FRAME_RPT_SET(id, conf->frame_loop_cnt); + ATON_STRENG_FOFFSET_SET(id, conf->frame_offset); + + t = ATON_STRENG_LIMITEN_DT; // all other fields set to zero + t = ATON_STRENG_LIMITEN_SET_FRAMELIMIT(t, 1); +#if defined(ATON_STRENG_LIMITEN_SET_DOFF_MSB) + t = ATON_STRENG_LIMITEN_SET_DOFF_MSB(t, conf->batch_offset >> ATON_STRENG_DEPTH_OFFSET_W); +#endif + ATON_STRENG_LIMITEN_SET(id, t); + + if (/*(conf->dir == 0) && */ (conf->offset_limit != 0x0)) + { + t = ATON_STRENG_LIMITEN_SET_ADDRLIMIT(t, 1); + t = ATON_STRENG_LIMITEN_SET_STOPPREFTC(t, 1); + ATON_STRENG_LIMITEN_SET(id, t); + // NOTE: limiter is to be set to last accessible byte address + // ATON_STRENG_LIMITADDR_SET(id, (conf->addr_limit.i - 1)); + ATON_REG_WRITE_RELOC(((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITADDR_ADDR(id)), conf->addr_base.i, + conf->offset_limit - 1); + } + + ATON_STRENG_LIMIT_SET(id, conf->frame_tot_cnt); + // LL_ATON_PRINTF("frame_tot_cnt=%d\n", conf->frame_tot_cnt); + +#if defined(ATON_STRENG_CID_CACHE_SET_CID) + t_streng_cid_cache = ATON_STRENG_CID_CACHE_SET_CID(t_streng_cid_cache, conf->bus_cid); + t_streng_cid_cache = ATON_STRENG_CID_CACHE_SET_CACHEABLE(t_streng_cid_cache, conf->cacheable); + t_streng_cid_cache = ATON_STRENG_CID_CACHE_SET_ALLOC(t_streng_cid_cache, conf->cache_allocate); + t_streng_cid_cache = ATON_STRENG_CID_CACHE_SET_PFETCH(t_streng_cid_cache, conf->bus_pfetch); + t_streng_cid_cache = ATON_STRENG_CID_CACHE_SET_LINESIZE(t_streng_cid_cache, conf->cache_linesize); +#endif + + /* Enable event interrupts */ + if (conf->dir == 1) + { +#if LL_ATON_EN_EVENT_IRQ + t_streng_event = 0; + t_streng_event = ATON_STRENG_EVENT_SET_EN_OFLOW_FRM(t_streng_event, 1); // enable frame overflow interrupt +#if 0 + t_streng_event = ATON_STRENG_EVENT_SET_EN_OFLOW_ADD(t_streng_event, 1); // enable address limiter interrupt +#endif +#endif // LL_ATON_EN_EVENT_IRQ + } + + /* Enable illegal configuration interrupts */ +#if LL_ATON_EN_ERROR_IRQ + t = t_streng_event; + t = ATON_STRENG_EVENT_SET_EN_ILLCFG(t, 1); // Enable Illegal Configuration interrupt + // t = ATON_STRENG_EVENT_SET_EN_FMTMM(t, 1); // Enable Format Mismatch interrupt (intentionally not enabled) + t_streng_event = t; +#endif // LL_ATON_EN_ERROR_IRQ + + if ((conf->dir == 0) && conf->sync_with_other) + { + t = t_streng_event; + t = ATON_STRENG_EVENT_SET_FRMTRG_EN(t, 1); // Enable synchronizations of frames with other dma + t = ATON_STRENG_EVENT_SET_FRMTRG_SRC(t, conf->sync_dma); // Enable synchronizations of frames with other dma + t_streng_event = t; + } + +#if 1 + t = ATON_STRENG_POS_DT; + t = ATON_STRENG_POS_SET_GAPCYCLES(t, 0); // set interline gap cycle to 0, as it should be safe to do so + ATON_STRENG_POS_SET(id, t); +#endif + + /* deferred register setting */ + ATON_STRENG_STRD_SET(id, t_streng_strd); + ATON_STRENG_CID_CACHE_SET(id, t_streng_cid_cache); + ATON_STRENG_EVENT_SET(id, t_streng_event); + + /* Ciphering settings */ +#if (ATON_STRENG_VERSION_ENCR_DT == 1) + t = ATON_STRENG_ENCR_MSB_DT; + t = ATON_STRENG_ENCR_MSB_SET_EN(t, conf->cipher_en); + t = ATON_STRENG_ENCR_MSB_SET_KEY_SEL(t, conf->key_sel); + ATON_STRENG_ENCR_MSB_SET(id, t); +#endif + + return 0; +} + +/** + * @brief Configures the Streaming Engine External trigger source + * To be used, for example, for configuring synchronization with DCMIPP + * @param id Streaming engine identifier [0..ATON_STRENG_NUM-1] + * @param conf Pointer to structure describing External Sync configuration + */ +int LL_Streng_ExtSyncInit(int id, LL_Streng_ExtSyncTypedef *conf) +{ +#ifdef ATON_STRENG_EXTSYNC_SET + uint32_t t; + + if (id >= ATON_STRENG_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_STRENG_CLKB_CLK(id)); + + t = ATON_STRENG_EXTSYNC_DT; + t = ATON_STRENG_EXTSYNC_SET_EN(t, conf->enable); + t = ATON_STRENG_EXTSYNC_SET_SRC(t, conf->trig_source); + t = ATON_STRENG_EXTSYNC_SET_LINES(t, conf->lines); + ATON_STRENG_EXTSYNC_SET(id, t); + + t = ATON_STRENG_EXTSYNC2_DT; + t = ATON_STRENG_EXTSYNC2_SET_LINES(t, conf->lines_offset); + t = ATON_STRENG_EXTSYNC2_SET_OFF(t, conf->offset); + ATON_STRENG_EXTSYNC2_SET(id, t); +#endif + return 0; +} + +#if defined(ATON_EPOCHCTRL_NUM) +/** + * @brief Sets external trigger signal to hi. Used to synchronize with external units, e.g.: HSP + * @param irq Interrupt line used as trigger signal + * @note uses Epoch Controller noack interrupt as irq source + */ +int LL_TriggerHigh(int irq) +{ + if (irq >= ATON_INTCTRL_INTS(0)) + return LL_ATON_INVALID_PARAM; + + ATON_INTCTRL_INTORMSK_SET(0, irq, ~(1 << ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_1_IDX)); + ATON_INTCTRL_INTSET_SET(0, (1 << ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_1_IDX)); + return 0; +} + +/** + * @brief Sets external trigger signal to low. Used to synchronize with external units, e.g.: HSP + * @param irq Interrupt line used as trigger signal + * @note uses Epoch Controller noack interrupt as irq source + */ +int LL_TriggerLow(int irq) +{ + if (irq >= ATON_INTCTRL_INTS(0)) + return LL_ATON_INVALID_PARAM; + + ATON_INTCTRL_INTCLR_SET(0, (1 << ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_1_IDX)); + return 0; +} +#endif + +unsigned __atonn_getSrcPortID(enum SwitchUnitsType sut, unsigned char su_num, enum AccelUnitsType aut, + unsigned char au_num, unsigned char port) +{ + // FIXME + LL_ATON_ASSERT(su_num == 0); + switch (sut) + { + case STRSWITCH: + switch (aut) + { +#if defined(ATON_STRENG_NUM) + case STRENG: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_STRENG_NUM); + return ATONN_CONST_SRCPORT(STRSWITCH, 0, STRENG, 0, 0) + au_num; + break; +#endif +#if defined(ATON_CONVACC_NUM) + case CONVACC: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_CONVACC_NUM); + return ATONN_CONST_SRCPORT(STRSWITCH, 0, CONVACC, 0, 0) + au_num; + break; +#endif +#if defined(ATON_DECUN_NUM) + case DECUN: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_DECUN_NUM); + return ATONN_CONST_SRCPORT(STRSWITCH, 0, DECUN, 0, 0) + au_num; + break; +#endif +#if defined(ATON_ACTIV_NUM) + case ACTIV: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_ACTIV_NUM); + return ATONN_CONST_SRCPORT(STRSWITCH, 0, ACTIV, 0, 0) + au_num; + break; +#endif +#if defined(ATON_ARITH_NUM) + case ARITH: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_ARITH_NUM); + return ATONN_CONST_SRCPORT(STRSWITCH, 0, ARITH, 0, 0) + au_num; + break; +#endif +#if defined(ATON_POOL_NUM) + case POOL: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_POOL_NUM); + return ATONN_CONST_SRCPORT(STRSWITCH, 0, POOL, 0, 0) + au_num; + break; +#endif + default: + LL_ATON_ASSERT(0); + break; + } + break; + case STRSWITCH64: + // TODO + LL_ATON_ASSERT(0); + break; + case STRSWITCH_VC: + // TODO + LL_ATON_ASSERT(0); + break; + } + return 0; +} + +unsigned __atonn_getDstPortID(enum SwitchUnitsType sut, unsigned char su_num, enum AccelUnitsType aut, + unsigned char au_num, unsigned char port) +{ + // FIXME + LL_ATON_ASSERT(su_num == 0); + switch (sut) + { + case STRSWITCH: + switch (aut) + { +#if defined(ATON_STRENG_NUM) + case STRENG: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_STRENG_NUM); + return ATONN_CONST_DSTPORT(STRSWITCH, 0, STRENG, 0, 0) + (0x4 * au_num); + break; +#endif +#if defined(ATON_CONVACC_NUM) + case CONVACC: + LL_ATON_ASSERT(port < 3); + LL_ATON_ASSERT(au_num < ATON_CONVACC_NUM); + return ATONN_CONST_DSTPORT(STRSWITCH, 0, CONVACC, 0, 0) + (0x4 * (3 * au_num + port)); + break; +#endif +#if defined(ATON_DECUN_NUM) + case DECUN: + LL_ATON_ASSERT(port < 2); + LL_ATON_ASSERT(au_num < ATON_DECUN_NUM); + return ATONN_CONST_DSTPORT(STRSWITCH, 0, DECUN, 0, 0) + (0x4 * (2 * au_num + port)); + break; +#endif +#if defined(ATON_ACTIV_NUM) + case ACTIV: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_ACTIV_NUM); + return ATONN_CONST_DSTPORT(STRSWITCH, 0, ACTIV, 0, 0) + (0x4 * au_num); + break; +#endif +#if defined(ATON_ARITH_NUM) + case ARITH: + LL_ATON_ASSERT(port < 2); + LL_ATON_ASSERT(au_num < ATON_ARITH_NUM); + return ATONN_CONST_DSTPORT(STRSWITCH, 0, ARITH, 0, 0) + (0x4 * (2 * au_num + port)); + break; +#endif +#if defined(ATON_POOL_NUM) + case POOL: + LL_ATON_ASSERT(port == 0); + LL_ATON_ASSERT(au_num < ATON_POOL_NUM); + return ATONN_CONST_DSTPORT(STRSWITCH, 0, POOL, 0, 0) + (0x4 * au_num); + break; +#endif + default: + LL_ATON_ASSERT(0); + break; + } + break; + case STRSWITCH64: + // TODO + LL_ATON_ASSERT(0); + break; + case STRSWITCH_VC: + // TODO + LL_ATON_ASSERT(0); + break; + } + return 0; +} + +/** + * @brief Connects input and output port(s) on the streaming switch (without clearing configuration) + * @param LL_Switch_InitStruct Pointer to structure(s) describing ports to be connected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_Switch_Init_NoReset(const LL_Switch_InitTypeDef *LL_Switch_InitStruct, int n) +{ + int i; + volatile uint32_t *reg; + uint32_t t; + unsigned int en_shift[ATON_SWITCH_CONTEXT_NUM] = {ATON_STRSWITCH_DST_EN0_LSB, ATON_STRSWITCH_DST_EN1_LSB}; + unsigned int link_shift[ATON_SWITCH_CONTEXT_NUM] = {ATON_STRSWITCH_DST_LINK0_LSB, ATON_STRSWITCH_DST_LINK1_LSB}; + unsigned int fnr_shift[ATON_SWITCH_CONTEXT_NUM] = {ATON_STRSWITCH_DST_FNR0_LSB, ATON_STRSWITCH_DST_FNR1_LSB}; + unsigned int fnr_mask[ATON_SWITCH_CONTEXT_NUM] = {ATON_STRSWITCH_DST_FNR0_MASK, ATON_STRSWITCH_DST_FNR1_MASK}; + + /* Enable Switch */ + t = ATON_STRSWITCH_CTRL_DT; + t = ATON_STRSWITCH_CTRL_SET_EN(t, 1); + ATON_STRSWITCH_CTRL_SET(0, t); + + for (i = 0; i < n; i++) + { + /* Compute target destination configuration register */ + reg = (uint32_t *)(ATON_STRSWITCH_BASE(0) + ATONN_DSTPORT_ID(LL_Switch_InitStruct[i].dest)); + t = 0; + /* Enable Context and create link */ +#if ATON_SWITCH_CONTEXT_NUM == 2 + t |= ((LL_Switch_InitStruct[i].context0 != 0) << en_shift[0]); + t |= (ATONN_SRCPORT_ID(LL_Switch_InitStruct[i].source0) << link_shift[0]); + t |= ((LL_Switch_InitStruct[i].frames0 << fnr_shift[0]) & fnr_mask[0]); + t |= ((LL_Switch_InitStruct[i].context1 != 0) << en_shift[1]); + t |= (ATONN_SRCPORT_ID(LL_Switch_InitStruct[i].source1) << link_shift[1]); + t |= ((LL_Switch_InitStruct[i].frames1 << fnr_shift[1]) & fnr_mask[1]); +#else + int c; + for (c = 0; c < ATON_SWITCH_CONTEXT_NUM; c++) + { + t |= ((LL_Switch_InitStruct[i].context[c] != 0) << en_shift[c]); + t |= (ATONN_SRCPORT_ID(LL_Switch_InitStruct[i].source[c]) << link_shift[c]); + t |= ((LL_Switch_InitStruct[i].frames[c] << fnr_shift[c]) & fnr_mask[c]); + } +#endif + + ATON_REG_WRITE(reg, t); + } + + return 0; +} + +/** + * @brief Connects input and output port(s) on the streaming switch (clearing configuration at the beginning) + * @param LL_Switch_InitStruct Pointer to structure(s) describing ports to be connected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_Switch_Init(const LL_Switch_InitTypeDef *LL_Switch_InitStruct, int n) +{ + uint32_t t; + +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) + ll_aton_static_checks(); +#endif + + /* Clear Configuration */ + ATON_DISABLE_CLR_CONFCLR(STRSWITCH, 0); + + return LL_Switch_Init_NoReset(LL_Switch_InitStruct, n); +} + +/** + * @brief Fully disconnect a destination port from source ports on the streaming switch + * @param LL_Switch_InitStruct Pointer to structure(s) describing ports to be disconnected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_Switch_Deinit(const LL_Switch_InitTypeDef *LL_Switch_InitStruct, int n) +{ + int i; + volatile uint32_t *reg; + + for (i = 0; i < n; i++) + { + /* Compute target destination configuration register */ + reg = (uint32_t *)(ATON_STRSWITCH_BASE(0) + ATONN_DSTPORT_ID(LL_Switch_InitStruct[i].dest)); + + /* Disable contexts */ + ATON_REG_WRITE(reg, 0); + } + + return 0; +} + +/** + * @brief Disconnects destination and source port(s) on the streaming switch + * @param LL_Switch_InitStruct Pointer to structure(s) describing ports to be disconnected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_Switch_Deinit_Fine_Grained(const LL_Switch_InitTypeDef *LL_Switch_InitStruct, int n) +{ + int i; + volatile uint32_t *reg; + unsigned int en_shift[ATON_SWITCH_CONTEXT_NUM] = {ATON_STRSWITCH_DST_EN0_LSB, ATON_STRSWITCH_DST_EN1_LSB}; + + for (i = 0; i < n; i++) + { + /* Compute target destination configuration register */ + reg = (uint32_t *)(ATON_STRSWITCH_BASE(0) + ATONN_DSTPORT_ID(LL_Switch_InitStruct[i].dest)); + + /* Disable context */ + uint32_t t = *reg; +#if ATON_SWITCH_CONTEXT_NUM == 2 + t &= ~((LL_Switch_InitStruct[i].context0 != 0) << en_shift[0]); + t &= ~((LL_Switch_InitStruct[i].context1 != 0) << en_shift[1]); +#else + int c; + for (c = 0; c < ATON_SWITCH_CONTEXT_NUM; c++) + t &= ~((LL_Switch_InitStruct[i].context[c] != 0) << en_shift[c]); +#endif + ATON_REG_WRITE(reg, t); + } + + return 0; +} + +#ifdef ATON_STRSWITCH_VC_NUM + +/** + * @brief Connects input and output port(s) on the streaming switch with virtual channels (without clearing + * configuration) + * @param LL_SwitchVC_InitStruct Pointer to structure(s) describing ports to be connected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_SwitchVC_Init_NoReset(const LL_SwitchVC_InitTypeDef *LL_SwitchVC_InitStruct, int n) +{ + int i; + volatile uint32_t *reg; + uint32_t t; + unsigned int en_shift = ATON_STRSWITCH_VC_DST_EN_LSB; + unsigned int src_shift = ATON_STRSWITCH_VC_DST_SRC_LSB; + + /* Enable Switch */ + t = ATON_STRSWITCH_VC_CTRL_DT; + t = ATON_STRSWITCH_VC_CTRL_SET_EN(t, 1); + ATON_STRSWITCH_VC_CTRL_SET(0, t); + + for (i = 0; i < n; i++) + { + /* Compute target destination configuration register */ + reg = (uint32_t *)(ATON_STRSWITCH_VC_BASE(0) + ATONN_DSTPORT_ID(LL_SwitchVC_InitStruct[i].dest)); + t = 0; + /* Enable Context and create link */ + t |= (1 << en_shift); + t |= (ATONN_SRCPORT_ID(LL_SwitchVC_InitStruct[i].source) << src_shift); + ATON_REG_WRITE(reg, t); + } + + return 0; +} + +/** + * @brief Connects input and output port(s) on the streaming switch with virtual channels (clearing configuration at + * the beginning) + * @param LL_SwitchVC_InitStruct Pointer to structure(s) describing ports to be connected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_SwitchVC_Init(const LL_SwitchVC_InitTypeDef *LL_SwitchVC_InitStruct, int n) +{ + uint32_t t; + + /* Clear Configuration */ + ATON_DISABLE_CLR_CONFCLR(STRSWITCH_VC, 0); + + return LL_SwitchVC_Init_NoReset(LL_SwitchVC_InitStruct, n); +} + +/** + * @brief Fully disconnect a destination port from source ports on the streaming switch with virtual channels + * @param LL_SwitchVC_InitStruct Pointer to structure(s) describing ports to be disconnected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_SwitchVC_Deinit(const LL_SwitchVC_InitTypeDef *LL_SwitchVC_InitStruct, int n) +{ + int i; + volatile uint32_t *reg; + + for (i = 0; i < n; i++) + { + /* Compute target destination configuration register */ + reg = (uint32_t *)(ATON_STRSWITCH_VC_BASE(0) + ATONN_DSTPORT_ID(LL_SwitchVC_InitStruct[i].dest)); + + /* Disable contexts */ + ATON_REG_WRITE(reg, 0); + } + + return 0; +} + +/** + * @brief Disconnects destination and source port(s) on the streaming switch with virtual channels + * @param LL_SwitchVC_InitStruct Pointer to structure(s) describing ports to be disconnected + * @param n Number of entries in configuration array + * @retval Error code + */ +int LL_SwitchVC_Deinit_Fine_Grained(const LL_SwitchVC_InitTypeDef *LL_SwitchVC_InitStruct, int n) +{ + int i; + volatile uint32_t *reg; + unsigned int en_shift = ATON_STRSWITCH_VC_DST_EN_LSB; + + for (i = 0; i < n; i++) + { + /* Compute target destination configuration register */ + reg = (uint32_t *)(ATON_STRSWITCH_VC_BASE(0) + ATONN_DSTPORT_ID(LL_SwitchVC_InitStruct[i].dest)); + + /* Disable context */ + uint32_t t = *reg; + t &= ~(1 << en_shift); + ATON_REG_WRITE(reg, t); + } + + return 0; +} +#endif // ATON_STRSWITCH_VC_NUM + +#ifdef ATON_DECUN_NUM + +static inline uint32_t decun_inc_page_addr(int id, uint32_t ctrl_val) +{ + uint32_t page_addr = ATON_DECUN_CTRL_GET_PAGEADDR(ctrl_val); + page_addr++; + ctrl_val = ATON_DECUN_CTRL_SET_PAGEADDR(ctrl_val, page_addr); + ATON_DECUN_CTRL_SET(id, ctrl_val); + return ctrl_val; +} + +static void LL_Decun_CB_1byte(int id, const LL_Decun_InitTypeDef *conf, uint32_t ctrl_val) +{ + unsigned CBsize = conf->CBs_size; + unsigned i, k; + unsigned mem_idx_num = ATON_DECUN_MEM_LOW_IDX_MAX - ATON_DECUN_MEM_LOW_IDX_MIN + 1; + + if (conf->nCWperCV == 1) + { + uint8_t *CBp = (uint8_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i++) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 2) + { +#if 0 + uint8_t *CBp = (uint8_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 2) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 8); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num ) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#else + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 2; i++) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#endif + } + if (conf->nCWperCV == 3) + { + uint8_t *CBp = (uint8_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 3) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 8) | (CBp[i + 2] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 4 || conf->nCWperCV == 8) + { + uint32_t *CBp = (uint32_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 4; i++) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 5) + { + uint8_t *CBp = (uint8_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 5) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 8) | (CBp[i + 2] << 16) | (CBp[i + 3] << 24); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + temp = CBp[i + 4]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 6) + { +#if 0 + uint8_t *CBp = (uint8_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 6) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 8) | (CBp[i + 2] << 16) | (CBp[i + 3] << 24); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + temp = CBp[i + 4] | (CBp[i + 5] << 8); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num ) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#else + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 2; i += 3) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + temp = CBp[i + 2]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#endif + } + if (conf->nCWperCV == 7) + { + uint8_t *CBp = (uint8_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 7) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 8) | (CBp[i + 2] << 16) | (CBp[i + 3] << 24); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + temp = CBp[i + 4] | (CBp[i + 5] << 8) | (CBp[i + 6] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } +} + +static void LL_Decun_CB_2byte(int id, const LL_Decun_InitTypeDef *conf, uint32_t ctrl_val) +{ + unsigned CBsize = conf->CBs_size / 2; + unsigned i, k; + unsigned mem_idx_num = ATON_DECUN_MEM_LOW_IDX_MAX - ATON_DECUN_MEM_LOW_IDX_MIN + 1; + + if (conf->nCWperCV == 1) + { + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i++) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 2) + { +#if 0 + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 2) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num ) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#else + uint32_t *CBp = (uint32_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 2; i++) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#endif + } + if (conf->nCWperCV == 3) + { + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 3) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 2]; + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 4) + { + uint32_t *CBp = (uint32_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 2; i += 2) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 1]; + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 5) + { + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 5) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 2] | (CBp[i + 3] << 16); + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + temp = CBp[i + 4]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 6) + { +#if 0 + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 6) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 2] | (CBp[i + 3] << 16); + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + if (k == mem_idx_num ) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + temp = CBp[i + 4] | (CBp[i + 5] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num ) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#else + uint32_t *CBp = (uint32_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 2; i += 3) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 1]; + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + temp = CBp[i + 2]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } +#endif + } + if (conf->nCWperCV == 7) + { + uint16_t *CBp = (uint16_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize; i += 7) + { + uint32_t temp = CBp[i] | (CBp[i + 1] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 2] | (CBp[i + 3] << 16); + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + temp = CBp[i + 4] | (CBp[i + 5] << 16); + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 6]; + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } + if (conf->nCWperCV == 8) + { + uint32_t *CBp = (uint32_t *)conf->CBs_vector.p; + for (i = 0, k = 0; i < CBsize / 2; i += 2) + { + uint32_t temp = CBp[i]; + ATON_DECUN_MEM_LOW_SET(id, k, temp); + temp = CBp[i + 1]; + ATON_DECUN_MEM_HIGH_SET(id, k, temp); + k++; + if (k == mem_idx_num) + { + ctrl_val = decun_inc_page_addr(id, ctrl_val); + k = 0; + } + } + } +} + +/** + * @brief Configures Decompression Unit accelerator + * @param id Decompression Unit identifier (Always 0 fo Tiny Orlando) + * @param conf Pointer to structure describing decompression unit configuration + * @retval Error code + */ +int LL_Decun_Init(int id, const LL_Decun_InitTypeDef *conf) +{ + uint32_t t; + + if (id >= ATON_DECUN_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_DECUN_CLKB_CLK(id)); + + t = ATON_DECUN_CTRL_DT; + t = ATON_DECUN_CTRL_SET_DUALIN(t, (conf->noDualInput != 0)); + t = ATON_DECUN_CTRL_SET_OW(t, (conf->noOverWrite != 0)); + ATON_DECUN_CTRL_SET(id, t); + + if (conf->CBs_size != 0) + { + if (conf->nFormatBytes == 1) + { + LL_Decun_CB_1byte(id, conf, t); + } + else + { + // LL_ATON_ASSERT(conf->nFormatBytes == 2); + LL_Decun_CB_2byte(id, conf, t); + } + } + + t = ATON_DECUN_BFORMAT_DT; + t = ATON_DECUN_BFORMAT_SET_CVS(t, conf->nCVperCB - 1); + t = ATON_DECUN_BFORMAT_SET_CWS(t, conf->nCWperCV - 1); + t = ATON_DECUN_BFORMAT_SET_OSAM(t, conf->nRCWlastCV); + ATON_DECUN_BFORMAT_SET(id, t); + + LL_ATON_ASSERT((conf->nFormatBytes == 1) || (conf->nFormatBytes == 2)); + + t = ATON_DECUN_DFORMAT_DT; + t = ATON_DECUN_DFORMAT_SET_CV8(t, conf->nFormatBytes & 0x1); + ATON_DECUN_DFORMAT_SET(id, t); + + t = ATON_DECUN_FFORMAT_DT; + t = ATON_DECUN_FFORMAT_SET_BN(t, conf->nBatches); + ATON_DECUN_FFORMAT_SET(id, t); + + return LL_ATON_OK; +} +#endif // ATON_DECUN_NUM + +#ifdef ATON_CONVACC_NUM +/** + * @brief Configures Convolution Accelerator + * @param id Convolutional Accelerator identifier [0, ATON_CONVACC_NUM-1] + * @param Convacc_InitStruct Structure describing initialization parameters + * @retval Error code E.g.: Invalid ID, invalid parameters, not idle,.. + */ +int LL_Convacc_Init(int id, const LL_Convacc_InitTypeDef *conf) +{ + uint32_t t; + + if (id >= ATON_CONVACC_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_CONVACC_CLKB_CLK(id)); + + t = ATON_CONVACC_CTRL_DT; + t = ATON_CONVACC_CTRL_SET_NOSUM(t, (conf->accumulate == 0)); + t = ATON_CONVACC_CTRL_SET_NO1SUM(t, (conf->accumulate_first == 0)); + t = ATON_CONVACC_CTRL_SET_GEN1SUM(t, (conf->accumulate_gen_first != 0)); + t = ATON_CONVACC_CTRL_SET_AFILTMODE(t, conf->afilt_mode); + t = ATON_CONVACC_CTRL_SET_SIMD(t, (conf->simd)); + t = ATON_CONVACC_CTRL_SET_KT1(t, (conf->kt1_mode != 0)); + t = ATON_CONVACC_CTRL_SET_KSETEN(t, conf->kseten); + t = ATON_CONVACC_CTRL_SET_FUNSIGNED(t, conf->f_unsigned); + t = ATON_CONVACC_CTRL_SET_KUNSIGNED(t, conf->k_unsigned); +#if defined(ATON_CONVACC_CTRL_SET_FSTAT) + t = ATON_CONVACC_CTRL_SET_FSTAT(t, (conf->fstat != 0)); +#endif + +#if defined(ATON_CONVACC_CTRL_GET_DEEPMODE) + t = ATON_CONVACC_CTRL_SET_DEEPMODE(t, (conf->deepmode != 0)); +#if defined(ATON_CONVACC_CTRL_SET_FSTAT) + // deepmode and feature stats are incompatible + if ((conf->fstat != 0) && (conf->deepmode != 0)) + { + return LL_ATON_INVALID_PARAM; + } +#endif +#endif + +#if defined(ATON_CONVACC_CTRL_GET_DSS2MODE) + t = ATON_CONVACC_CTRL_SET_DSS2MODE(t, (conf->dss2mode != 0)); +#if defined(ATON_CONVACC_CTRL_SET_FSTAT) + // deepmode and feature stats are incompatible + if ((conf->fstat != 0) && (conf->dss2mode != 0)) + { + return LL_ATON_INVALID_PARAM; + } +#endif +#endif + +#if defined(ATON_CONVACC_CTRL_SET_DSS2MODE) && defined(ATON_CONVACC_CTRL_SET_DEEPMODE) + // deepmode and dss2mode stats are incompatible + if ((conf->dss2mode != 0) && (conf->deepmode != 0)) + { + return LL_ATON_INVALID_PARAM; + } +#endif + + ATON_CONVACC_CTRL_SET(id, t); + Conv_ctrl_bits[id] = t; + + if (conf->afilt_mode != AFILT_MODE_NONE) + { + t = ATON_CONVACC_AFILT_DT; + t = ATON_CONVACC_AFILT_SET_TOT(t, conf->afilt_tot); + t = ATON_CONVACC_AFILT_SET_FIRST(t, conf->afilt_first); + t = ATON_CONVACC_AFILT_SET_LAST(t, conf->afilt_last); + ATON_CONVACC_AFILT_SET(id, t); + } + + if (conf->kfilt_tot > 0) + { + t = ATON_CONVACC_KFILT_DT; + t = ATON_CONVACC_KFILT_SET_TOT(t, conf->kfilt_tot); + t = ATON_CONVACC_KFILT_SET_FIRST(t, conf->kfilt_first); + t = ATON_CONVACC_KFILT_SET_LAST(t, conf->kfilt_last); + ATON_CONVACC_KFILT_SET(id, t); + } + + t = ATON_CONVACC_DFORMAT_DT; + t = ATON_CONVACC_DFORMAT_SET_FROUND(t, conf->rounding_f); + t = ATON_CONVACC_DFORMAT_SET_FSAT(t, conf->saturation_f); + t = ATON_CONVACC_DFORMAT_SET_FRNDMODE(t, conf->round_mode_f); + t = ATON_CONVACC_DFORMAT_SET_FBYTES(t, conf->inbytes_f); + t = ATON_CONVACC_DFORMAT_SET_FSHIFT(t, ATON_SHIFT(conf->shift_f)); + + t = ATON_CONVACC_DFORMAT_SET_ROUND(t, conf->rounding_o); + t = ATON_CONVACC_DFORMAT_SET_SAT(t, conf->saturation_o); + t = ATON_CONVACC_DFORMAT_SET_ORNDMODE(t, (conf->relu_mode_o << 1) | conf->round_mode_o); + t = ATON_CONVACC_DFORMAT_SET_OBYTES(t, conf->outbytes_o); + t = ATON_CONVACC_DFORMAT_SET_OUTSHIFT(t, conf->shift_o); // shift right only + t = ATON_CONVACC_DFORMAT_SET_RAW(t, conf->raw_o); + + t = ATON_CONVACC_DFORMAT_SET_INSHIFT(t, conf->shift_a); // accumulator shift left really (macro name is misleading) + ATON_CONVACC_DFORMAT_SET(id, t); + + t = ATON_CONVACC_FFORMAT_DT; + t = ATON_CONVACC_FFORMAT_SET_WIDTH(t, conf->fWidth * conf->batchDepth); + t = ATON_CONVACC_FFORMAT_SET_HEIGHT(t, conf->fHeight); + ATON_CONVACC_FFORMAT_SET(id, t); + + t = ATON_CONVACC_KFORMAT_DT; + t = ATON_CONVACC_KFORMAT_SET_WIDTH(t, conf->kernelWidth); + t = ATON_CONVACC_KFORMAT_SET_HEIGHT(t, conf->kernelHeight); + t = ATON_CONVACC_KFORMAT_SET_BTCDEPTH(t, conf->batchDepth); + t = ATON_CONVACC_KFORMAT_SET_NR(t, conf->nKernels); + ATON_CONVACC_KFORMAT_SET(id, t); + + // LL_ATON_PRINTF("depth=%d k_w=%d k_h=%d\n",conf->batchDepth,conf->kernelWidth,conf->kernelHeight); + // LL_ATON_PRINTF("pad_t=%d pad_b=%d pad_l=%d + // pad_r=%d\n",conf->top_padding,conf->bot_padding,conf->left_padding,conf->right_padding); + + int p_top = (conf->top_padding < conf->kernelHeight ? conf->top_padding : conf->kernelHeight - 1); + int p_bot = (conf->bot_padding < conf->kernelHeight ? conf->bot_padding : conf->kernelHeight - 1); + int p_left = (conf->left_padding < conf->kernelWidth ? conf->left_padding : conf->kernelWidth - 1); + int p_right = (conf->right_padding < conf->kernelWidth ? conf->right_padding : conf->kernelWidth - 1); + + p_top = (p_top <= 2 ? p_top : 2); + p_bot = (p_bot <= 2 ? p_bot : 2); + p_left = (p_left <= 2 ? p_left : 2); + p_right = (p_right <= 2 ? p_right : 2); + // LL_ATON_PRINTF("p_t=%d p_b=%d p_l=%d p_r=%d\n",p_top,p_bot,p_left,p_right); + +#if defined(ATON_CONVACC_CTRL_GET_DEEPMODE) + // no pad mode available in 1x1 deepmode + // will accomodate padding only with zframe below + if (conf->deepmode != 0) + p_top = p_bot = p_left = p_right = 0; +#endif +#if defined(ATON_CONVACC_CTRL_GET_DSS2MODE) + // no pad mode available in dss2mode + // will accomodate padding only with zframe below + if (conf->dss2mode != 0) + p_top = p_bot = p_left = p_right = 0; +#endif +#if defined(ATON_CONVACC_ZFBIAS_SET) + // no pad mode available if zfbias is set + // will accomodate padding only with zframe below + if (conf->zfbias != 0) + p_top = p_bot = p_left = p_right = 0; +#endif + + int z_top = (conf->top_padding - p_top); + int z_bot = (conf->bot_padding - p_bot); + int z_left = (conf->left_padding - p_left); + int z_right = (conf->right_padding - p_right); + // LL_ATON_PRINTF("z_t=%d z_b=%d z_l=%d z_r=%d\n",z_top,z_bot,z_left*conf->batchDepth,z_right*conf->batchDepth); + + t = ATON_CONVACC_ZFRAME_DT; + t = ATON_CONVACC_ZFRAME_SET_TOP(t, z_top); + t = ATON_CONVACC_ZFRAME_SET_BOTTOM(t, z_bot); + t = ATON_CONVACC_ZFRAME_SET_LEFT(t, z_left * conf->batchDepth); + t = ATON_CONVACC_ZFRAME_SET_RIGHT(t, z_right * conf->batchDepth); + ATON_CONVACC_ZFRAME_SET(id, t); + + t = ATON_CONVACC_SAMPLE_DT; + t = ATON_CONVACC_SAMPLE_SET_TPAD(t, p_top); + t = ATON_CONVACC_SAMPLE_SET_BPAD(t, p_bot); + t = ATON_CONVACC_SAMPLE_SET_LPAD(t, p_left); + t = ATON_CONVACC_SAMPLE_SET_RPAD(t, p_right); + t = ATON_CONVACC_SAMPLE_SET_HSTRD(t, conf->hstride); + t = ATON_CONVACC_SAMPLE_SET_VSTRD(t, conf->vstride); +#if defined(ATON_CONVACC_SAMPLE_SET_FSTATCNT) + if (conf->fstat != 0) + t = ATON_CONVACC_SAMPLE_SET_FSTATCNT(t, conf->fstatcnt); +#endif + ATON_CONVACC_SAMPLE_SET(id, t); + + // LL_ATON_PRINTF("crop_t=%d crop_b=%d crop_l=%d crop_r=%d\n",z_top,z_bot,z_left,z_right); + t = ATON_CONVACC_FHCROP_DT; + if (conf->left_crop > 0) + t = ATON_CONVACC_FHCROP_SET_LEFT(t, conf->left_crop * conf->batchDepth); + if (conf->right_crop > 0) + t = ATON_CONVACC_FHCROP_SET_RIGHT(t, conf->right_crop * conf->batchDepth + (conf->batchDepth - 1)); + ATON_CONVACC_FHCROP_SET(id, t); + + t = ATON_CONVACC_FVCROP_DT; + if (conf->top_crop > 0) + t = ATON_CONVACC_FVCROP_SET_TOP(t, conf->top_crop); + if (conf->bot_crop > 0) + t = ATON_CONVACC_FVCROP_SET_BOTTOM(t, conf->bot_crop); + ATON_CONVACC_FVCROP_SET(id, t); + // LL_ATON_PRINTF("c_t=%d c_b=%d c_l=%d c_r=%d\n",conf->top_crop,conf->bot_crop,conf->left_crop * + // conf->batchDepth,conf->right_crop * conf->batchDepth + (conf->batchDepth - 1)); + +#if defined(ATON_CONVACC_FSUB_SET) + if (conf->fsub != 0) + { + t = ATON_CONVACC_FSUB_DT; + t = ATON_CONVACC_FSUB_SET_FSUB(t, conf->fsub); + ATON_CONVACC_FSUB_SET(id, t); + } +#endif +#if defined(ATON_CONVACC_ZFBIAS_SET) + t = ATON_CONVACC_ZFBIAS_DT; + if (conf->zfbias != 0) + { + t = ATON_CONVACC_ZFBIAS_SET_ZFBIAS(t, conf->zfbias); + } + + /* If hardware supports it (e.g.: 4CA2P), manage Batch Depths not fitting 8 bits */ +#if defined(ATON_CONVACC_ZFBIAS_SET_ZFLEFTMSB) + t = ATON_CONVACC_ZFBIAS_SET_ZFLEFTMSB(t, (z_left * conf->batchDepth) >> ATON_CONVACC_ZFRAME_LEFT_W); + t = ATON_CONVACC_ZFBIAS_SET_ZFRIGHTMSB(t, (z_right * conf->batchDepth) >> ATON_CONVACC_ZFRAME_RIGHT_W); +#endif + + ATON_CONVACC_ZFBIAS_SET(id, t); +#endif + + return 0; +} +#endif // ATON_CONVACC_NUM + +#ifdef ATON_ACTIV_NUM + +static int32_t get_Activacc_type(LL_Activacc_Op op) +{ + switch (op) + { + case ACTIV_RELU: + return ATON_ACTIVTYPE_RELU; + case ACTIV_PRELU: + return ATON_ACTIVTYPE_PRELU; + case ACTIV_TRELU: + return ATON_ACTIVTYPE_TRELU; + case ACTIV_FUNC: + return ATON_ACTIVTYPE_FUNCTION; +#if defined ATON_ACTIVTYPE_LUT + case ACTIV_LUT: + return ATON_ACTIVTYPE_LUT; +#endif + default: + break; + } + LL_ATON_ASSERT(0); + return 0; +} + +/** + * @brief Configures Activation Accelerator + * @param id Activation Accelerator identifier [0..ATON_ACTIV_NUM-1] + * @param Activacc_InitStruct Structure describing initialization parameters + * @retval Error code E.g.: Invalid ID, invalid parameters, not idle,.. + */ +int LL_Activacc_Init(int id, const LL_Activacc_InitTypeDef *conf) +{ + uint32_t t; + + if (id >= ATON_ACTIV_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_ACTIV_CLKB_CLK(id)); + + t = ATON_ACTIV_CTRL_DT; + t = ATON_ACTIV_CTRL_SET_TYPE(t, get_Activacc_type(conf->operation)); + t = ATON_ACTIV_CTRL_SET_FBYTES(t, conf->inbytes_f); + t = ATON_ACTIV_CTRL_SET_FSHIFT(t, ATON_SHIFT(conf->shift_f)); + t = ATON_ACTIV_CTRL_SET_FROUND(t, conf->rounding_f); + t = ATON_ACTIV_CTRL_SET_FSAT(t, (conf->saturation_f != 0)); + t = ATON_ACTIV_CTRL_SET_FRNDMODE(t, conf->round_mode_f); + t = ATON_ACTIV_CTRL_SET_FOBYTES(t, conf->outbytes_f); + + t = ATON_ACTIV_CTRL_SET_ROUND(t, (conf->rounding_o != 0)); + t = ATON_ACTIV_CTRL_SET_SAT(t, (conf->saturation_o != 0)); + t = ATON_ACTIV_CTRL_SET_OBYTES(t, conf->outbytes_o); + t = ATON_ACTIV_CTRL_SET_ORNDMODE(t, (conf->relu_mode_o << 1) | conf->round_mode_o); + ATON_ACTIV_CTRL_SET(id, t); + +#if defined(ATON_ACTIV_FSUB_SET) + if (conf->fsub != 0) + { + t = ATON_ACTIV_FSUB_DT; + t = ATON_ACTIV_FSUB_SET_FSUB(t, conf->fsub); + ATON_ACTIV_FSUB_SET(id, t); + } +#endif + + switch (conf->operation) + { + case ACTIV_RELU: + case ACTIV_PRELU: + case ACTIV_TRELU: + t = ATON_ACTIV_ACTIVPARAM_DT; + t = ATON_ACTIV_ACTIVPARAM_SET_PARAM(t, conf->parameter); + ATON_ACTIV_ACTIVPARAM_SET(id, t); + + t = ATON_ACTIV_ACTIVPARAM2_DT; + t = ATON_ACTIV_ACTIVPARAM2_SET_PARAM2(t, conf->parameter_2); + ATON_ACTIV_ACTIVPARAM2_SET(id, t); + + t = ATON_ACTIV_FUNC_DT; + t = ATON_ACTIV_FUNC_SET_SIGNEDOP(t, (conf->signedop != 0)); + t = ATON_ACTIV_FUNC_SET_OUTSHIFT(t, conf->shift_o); + ATON_ACTIV_FUNC_SET(id, t); + break; + case ACTIV_FUNC: + { + t = ATON_ACTIV_FUNC_DT; + t = ATON_ACTIV_FUNC_SET_SIGNEDOP(t, (conf->signedop != 0)); + t = ATON_ACTIV_FUNC_SET_OUTSHIFT(t, conf->shift_o); + t = ATON_ACTIV_FUNC_SET_BSHIFT(t, conf->shift_b); + t = ATON_ACTIV_FUNC_SET_CSHIFT(t, conf->shift_c); + t = ATON_ACTIV_FUNC_SET_BWIDTH(t, conf->bwidth); + ATON_ACTIV_FUNC_SET(id, t); + + t = ATON_ACTIV_ACTIVPARAM_DT; + t = ATON_ACTIV_ACTIVPARAM_SET_PARAM(t, conf->parameter); + t = ATON_ACTIV_ACTIVPARAM_SET_FUNC(t, conf->shift_norm); + ATON_ACTIV_ACTIVPARAM_SET(id, t); + + { + uint8_t *R0p = (uint8_t *)conf->ROM0_vector.p; + unsigned ROM0_rows = conf->ROM0_nbytes / (1 * 1); + for (int i = 0; i < ROM0_rows; i++) + { + t = ATON_ACTIV_ROM0_DT; + t = ATON_ACTIV_ROM0_SET_ENTRY(t, R0p[i]); + ATON_ACTIV_ROM0_SET(id, i, t); + } + } + { + uint16_t *R1p = (uint16_t *)conf->ROM1_vector.p; + unsigned ROM1_rows = conf->ROM1_nbytes / (3 * 2); + for (int i = 0; i < ROM1_rows; i++) + { + t = ATON_ACTIV_ROM1_AB_DT; + t = ATON_ACTIV_ROM1_AB_SET_A(t, R1p[3 * i + 0]); + t = ATON_ACTIV_ROM1_AB_SET_B(t, R1p[3 * i + 1]); + ATON_ACTIV_ROM1_AB_SET(id, i, t); + t = ATON_ACTIV_ROM1_C_DT; + t = ATON_ACTIV_ROM1_C_SET_C(t, R1p[3 * i + 2]); + ATON_ACTIV_ROM1_C_SET(id, i, t); + } + } + } + break; + case ACTIV_LUT: +#if defined ATON_ACTIVTYPE_LUT + { + uint8_t *Lutp = (uint8_t *)conf->LUT_vector.p; + for (int i = 0; i < 64; i++) + { + uint32_t val = ATON_ACTIV_LUT_DT; + val = ATON_ACTIV_LUT_SET_MOD8_1(val, Lutp[4 * i]); + val = ATON_ACTIV_LUT_SET_MOD8_2(val, Lutp[4 * i + 1]); + val = ATON_ACTIV_LUT_SET_MOD8_3(val, Lutp[4 * i + 2]); + val = ATON_ACTIV_LUT_SET_MOD8_4(val, Lutp[4 * i + 3]); + ATON_ACTIV_LUT_SET(id, i, val); + } + } +#else + assert("Unsupported Activation LUT configuration"); +#endif + break; + default: + return -1; + } + + return 0; +} +#endif // ATON_ACTIV_NUM + +#ifdef ATON_ARITH_NUM + +static int32_t get_Arithacc_type(LL_Arithacc_Op op) +{ + switch (op) + { + case ARITH_AFFINE: + return ATON_ARITHOP_AX_BY_C; + case ARITH_MIN: + return ATON_ARITHOP_MIN_X_Y; + case ARITH_MAX: + return ATON_ARITHOP_MAX_X_Y; + case ARITH_MUL: + return ATON_ARITHOP_XY; + case ARITH_X_AND_Y: + return ATON_ARITHOP_X_AND_Y; + case ARITH_X_OR_Y: + return ATON_ARITHOP_X_OR_Y; + case ARITH_NOT_X: + return ATON_ARITHOP_NOT_X; + case ARITH_X_XOR_Y: + return ATON_ARITHOP_X_XOR_Y; + case ARITH_X_EQ_Y: + return ATON_ARITHOP_X_EQ_Y; + case ARITH_X_LT_Y: + return ATON_ARITHOP_X_LT_Y; + case ARITH_X_LE_Y: + return ATON_ARITHOP_X_LE_Y; + case ARITH_X_GT_Y: + return ATON_ARITHOP_X_GT_Y; + case ARITH_X_GE_Y: + return ATON_ARITHOP_X_GE_Y; + case ARITH_ABS_X: + return ATON_ARITHOP_ABS_X; + case ARITH_SIGN_X: + return ATON_ARITHOP_SIGN_X; + case ARITH_CLIP: + return ATON_ARITHOP_CLIP; + default: + break; + } + LL_ATON_ASSERT(0); + return 0; +} + +/** + * @brief Configures Arithmetic Accelerator + * @param id Arithmetic Accelerator identifier [0..ATON_ARITH_NUM-1] + * @param Arithacc_InitStruct Structure describing initialization parameters + * @retval Error code E.g.: Invalid ID, invalid parameters, not idle,.. + */ +int LL_Arithacc_Init(int id, const LL_Arithacc_InitTypeDef *conf) +{ + uint32_t t; + char sshift; + + if (id >= ATON_ARITH_NUM) + return LL_ATON_INVALID_ID; + + /* Deal with Arith Acc V3 shifts extensions */ + if (ATON_ARITH_VERSION_MAJOR_DT >= 3) + sshift = 16; + else + sshift = 0; + + LL_ATON_EnableClock(ATON_ARITH_CLKB_CLK(id)); + + t = ATON_ARITH_CTRL_DT; + ATON_ARITH_CTRL_SET(id, t); + + t = ATON_ARITH_CTRL_DT; + t = ATON_ARITH_CTRL_SET_CNT1(t, (conf->scalar == 0)); // these must be handled yet FIXME !!! + t = ATON_ARITH_CTRL_SET_CNT2(t, (conf->scalar == 0) && (conf->bcast == ARITH_BCAST_CHAN)); + t = ATON_ARITH_CTRL_SET_CNT3(t, (conf->scalar == 0) && (conf->bcast == ARITH_BCAST_CHAN)); + t = ATON_ARITH_CTRL_SET_ROUND(t, (conf->rounding_o != 0)); + t = ATON_ARITH_CTRL_SET_ORNDMODE(t, (conf->relu_mode_o << 1) | conf->round_mode_o); + // t = ATON_ARITH_CTRL_SET_OBYTES(t,((conf->dataw_o + 7) >> 3)); + t = ATON_ARITH_CTRL_SET_OBYTES(t, conf->outbytes_o); + t = ATON_ARITH_CTRL_SET_SAT(t, (conf->saturation_o != 0)); + t = ATON_ARITH_CTRL_SET_COEFFA(t, (conf->scalar == 0)); + t = ATON_ARITH_CTRL_SET_COEFFB(t, (conf->scalar == 0)); + t = ATON_ARITH_CTRL_SET_COEFFC(t, (conf->scalar == 0)); + t = ATON_ARITH_CTRL_SET_DUALIN(t, (conf->dualinput != 0)); + t = ATON_ARITH_CTRL_SET_COMBINEBC(t, (conf->combinebc != 0)); +#ifdef ATON_ARITH_CTRL_SET_CLIPOUT + t = ATON_ARITH_CTRL_SET_CLIPOUT(t, (conf->clipout != 0)); +#endif + t = ATON_ARITH_CTRL_SET_OP(t, get_Arithacc_type(conf->operation)); + if (conf->operation == ARITH_NOT_X) + { // WORKAROUND + t = ATON_ARITH_CTRL_SET_LOGICALOP(t, 1); + } + ATON_ARITH_CTRL_SET(id, t); + + t = ATON_ARITH_INSHIFTER_DT; + t = ATON_ARITH_INSHIFTER_SET_FBYTESX(t, conf->inbytes_x); + t = ATON_ARITH_INSHIFTER_SET_FSHIFTX(t, ATON_SHIFT(conf->shift_x)); + t = ATON_ARITH_INSHIFTER_SET_FROUNDX(t, (conf->rounding_x != 0)); + t = ATON_ARITH_INSHIFTER_SET_FSATX(t, (conf->saturation_x != 0)); + t = ATON_ARITH_INSHIFTER_SET_FRNDMODEX(t, conf->round_mode_x); + t = ATON_ARITH_INSHIFTER_SET_FOBYTESX(t, conf->outbytes_x); + + t = ATON_ARITH_INSHIFTER_SET_FBYTESY(t, conf->inbytes_y); + t = ATON_ARITH_INSHIFTER_SET_FSHIFTY(t, ATON_SHIFT(conf->shift_y)); + t = ATON_ARITH_INSHIFTER_SET_FROUNDY(t, (conf->rounding_y != 0)); + t = ATON_ARITH_INSHIFTER_SET_FSATY(t, (conf->saturation_y != 0)); + t = ATON_ARITH_INSHIFTER_SET_FRNDMODEY(t, conf->round_mode_y); + t = ATON_ARITH_INSHIFTER_SET_FOBYTESY(t, conf->outbytes_y); + ATON_ARITH_INSHIFTER_SET(id, t); + + t = ATON_ARITH_SHIFT_DT; + t = ATON_ARITH_SHIFT_SET_AX(t, conf->Ax_shift + sshift); + t = ATON_ARITH_SHIFT_SET_BY(t, conf->By_shift + sshift); + t = ATON_ARITH_SHIFT_SET_C(t, conf->C_shift + sshift); + t = ATON_ARITH_SHIFT_SET_RES(t, conf->shift_o); // right shift only + ATON_ARITH_SHIFT_SET(id, t); + + t = ATON_ARITH_COEFFAC_DT; + t = ATON_ARITH_COEFFAC_SET_A(t, conf->A_scalar); + t = ATON_ARITH_COEFFAC_SET_C(t, conf->C_scalar); + ATON_ARITH_COEFFAC_SET(id, t); + + t = ATON_ARITH_COEFFB_DT; + t = ATON_ARITH_COEFFB_SET_B(t, conf->B_scalar); + ATON_ARITH_COEFFB_SET(id, t); + +#ifdef ATON_ARITH_CLIPRANGE_SET + if (conf->clipout) + { + t = ATON_ARITH_CLIPRANGE_DT; + t = ATON_ARITH_CLIPRANGE_SET_CLIPMAX(t, (conf->clipmax & 0xFFFFU)); + t = ATON_ARITH_CLIPRANGE_SET_CLIPMIN(t, (conf->clipmin & 0xFFFFU)); + ATON_ARITH_CLIPRANGE_SET(id, t); + +#ifdef ATON_ARITH_CLIPRANGE_MSB_SET + t = ATON_ARITH_CLIPRANGE_MSB_DT; + t = ATON_ARITH_CLIPRANGE_MSB_SET_CLIPMAX(t, (conf->clipmax >> 16)); + t = ATON_ARITH_CLIPRANGE_MSB_SET_CLIPMIN(t, (conf->clipmin >> 16)); + ATON_ARITH_CLIPRANGE_MSB_SET(id, t); +#endif + } +#endif + + ATON_ARITH_COEFFADDR_SET(id, 0); + + int maxc = 0; + if (conf->scalar == 0) + { // vector mode + switch (conf->bcast) + { + case ARITH_BCAST_CHAN: + t = ATON_ARITH_INCCNT_SET_INCVAL(0, 0); + ATON_ARITH_INCCNT_SET(id, t); + + t = ATON_ARITH_RSTCNT1_SET_RSTCNT(0, (conf->batchDepth - 1)); + ATON_ARITH_RSTCNT1_SET(id, t); + + t = ATON_ARITH_RSTCNT2_SET_RSTCNT( + 0, (conf->fWidth * conf->fHeight * conf->batchDepth - 1)); // must check this fits into 27 bits FIXME !!! + ATON_ARITH_RSTCNT2_SET(id, t); + + t = ATON_ARITH_RSTCNT3_SET_RSTCNT( + 0, (conf->fWidth * conf->fHeight * conf->fChannels - 1)); // must check this fits into 27 bits FIXME !!! + ATON_ARITH_RSTCNT3_SET(id, t); + + t = ATON_ARITH_INCOFFSET_SET_VAL(0, 1); + ATON_ARITH_INCOFFSET_SET(id, t); + + t = ATON_ARITH_ADDROFFSET_SET_OFFSET1(0, -(conf->batchDepth - 1)); + t = ATON_ARITH_ADDROFFSET_SET_OFFSET2(t, 1); + t = ATON_ARITH_ADDROFFSET_SET_OFFSET3(t, -(conf->fChannels - 1)); + ATON_ARITH_ADDROFFSET_SET(id, t); + maxc = conf->fChannels; + break; + case ARITH_BCAST_HEIGHT: + t = ATON_ARITH_INCCNT_SET_INCVAL(0, (conf->fWidth * conf->batchDepth - 1)); + ATON_ARITH_INCCNT_SET(id, t); + + t = ATON_ARITH_RSTCNT1_SET_RSTCNT(0, (conf->fWidth * conf->fHeight * conf->batchDepth - 1)); + ATON_ARITH_RSTCNT1_SET(id, t); + + t = ATON_ARITH_INCOFFSET_SET_VAL(0, 1); + ATON_ARITH_INCOFFSET_SET(id, t); + + t = ATON_ARITH_ADDROFFSET_SET_OFFSET1(0, -(conf->fHeight - 1)); + ATON_ARITH_ADDROFFSET_SET(id, t); + maxc = conf->fHeight; + break; + case ARITH_BCAST_WIDTH: + t = ATON_ARITH_INCCNT_SET_INCVAL(0, (conf->batchDepth - 1)); + ATON_ARITH_INCCNT_SET(id, t); + + t = ATON_ARITH_RSTCNT1_SET_RSTCNT(0, (conf->fWidth * conf->batchDepth - 1)); + ATON_ARITH_RSTCNT1_SET(id, t); + + t = ATON_ARITH_INCOFFSET_SET_VAL(0, 1); + ATON_ARITH_INCOFFSET_SET(id, t); + + t = ATON_ARITH_ADDROFFSET_SET_OFFSET1(0, -(conf->fWidth - 1)); + ATON_ARITH_ADDROFFSET_SET(id, t); + maxc = conf->fWidth; + break; + case ARITH_BCAST_HEIGHT_WIDTH: + t = ATON_ARITH_INCCNT_SET_INCVAL(0, (conf->batchDepth - 1)); + ATON_ARITH_INCCNT_SET(id, t); + + t = ATON_ARITH_RSTCNT1_SET_RSTCNT(0, (conf->fHeight * conf->fWidth * conf->batchDepth - 1)); + ATON_ARITH_RSTCNT1_SET(id, t); + + t = ATON_ARITH_INCOFFSET_SET_VAL(0, 1); + ATON_ARITH_INCOFFSET_SET(id, t); + + t = ATON_ARITH_ADDROFFSET_SET_OFFSET1(0, -(conf->fHeight * conf->fWidth - 1)); + ATON_ARITH_ADDROFFSET_SET(id, t); + maxc = conf->fHeight * conf->fWidth; + break; + case ARITH_BCAST_SCALAR: + t = ATON_ARITH_INCCNT_SET_INCVAL(0, 0); + ATON_ARITH_INCCNT_SET(id, t); + + t = ATON_ARITH_INCOFFSET_SET_VAL(0, 0); + ATON_ARITH_INCOFFSET_SET(id, t); + + maxc = 1; + break; + default: + return LL_ATON_INVALID_PARAM; + } + + maxc = (maxc > 512 ? 512 : maxc); + int i, k; + uint32_t *Ap = (uint32_t *)conf->A_vector.p; + uint32_t *Bp = (uint32_t *)conf->B_vector.p; + uint32_t *Cp = (uint32_t *)conf->C_vector.p; + int nbits_A = conf->vec_precision[0]; + int nbits_B = conf->vec_precision[1]; + int nbits_C = conf->vec_precision[2]; + int bitcnt_A = 0; + int bitcnt_B = 0; + int bitcnt_C = 0; + int mem_idx_num = ATON_ARITH_COEFF_AB_IDX_MAX - ATON_ARITH_COEFF_AB_IDX_MIN + 1; + + int32_t c_sign = (conf->C_scalar == -1 ? -1 : 1); +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) + ec_trace_comment("Block ECASM optimizations to move reg writes pass this point"); +#endif + ATON_ARITH_TRANSLATEADDR_SET(id, 1); // map 0x400 onto 0x0 offset for coefficients + for (i = 0, k = 0; i < maxc; i++, k++) + { + uint32_t t; + uint32_t A = Ap != NULL ? LL_ATON_getbits(Ap, bitcnt_A, nbits_A) : (uint32_t)conf->A_scalar; + uint32_t B = Bp != NULL ? LL_ATON_getbits(Bp, bitcnt_B, nbits_B) : (uint32_t)conf->B_scalar; + uint32_t C = Cp != NULL ? (c_sign * LL_ATON_getbits(Cp, bitcnt_C, nbits_C)) : (uint32_t)conf->C_scalar; + if (conf->combinebc) + { + B = (C >> 16); + C = (C & 0xFFFF); + } + if (k == mem_idx_num) + { +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) + ec_trace_comment("Block ECASM optimizations to move reg writes pass this point"); +#endif + ATON_ARITH_TRANSLATEADDR_SET(id, 0); // map 0xC00 onto 0xC00 offset for coefficients + k -= (256 / 2); + } + t = ATON_ARITH_COEFF_AB_DT; + t = ATON_ARITH_COEFF_AB_SET_A(t, A); + t = ATON_ARITH_COEFF_AB_SET_B(t, B); + ATON_ARITH_COEFF_AB_SET(id, k, t); + t = ATON_ARITH_COEFF_C_DT; + t = ATON_ARITH_COEFF_C_SET_C(t, C); + ATON_ARITH_COEFF_C_SET(id, k, t); + + bitcnt_A += nbits_A; + bitcnt_B += nbits_B; + bitcnt_C += nbits_C; + } + } + return 0; +} +#endif // ATON_ARITH_NUM + +#ifdef ATON_POOL_NUM + +static int32_t get_Poolacc_type(LL_Poolacc_Op op) +{ + switch (op) + { + case POOL_MAX: + return ATON_POOLTYPE_MAX_POOLING; + case POOL_MIN: + return ATON_POOLTYPE_MIN_POOLING; + case POOL_AVG: + return ATON_POOLTYPE_AVG_POOLING; + case POOL_GMAX: + return ATON_POOLTYPE_GMAX_POOLING; + case POOL_GMIN: + return ATON_POOLTYPE_GMIN_POOLING; + case POOL_GAVG: + return ATON_POOLTYPE_GAVG_POOLING; + default: + break; + } + LL_ATON_ASSERT(0); + return 0; +} + +/** + * @brief Configure Pooling Accelerator + * @param id Pooling Accelerator identifier [0..ATON_POOL_NUM-1] + * @param Poolacc_InitStruct Structure describing initialization parameters + * @retval Error code E.g.: Invalid ID, invalid parameters, not idle,.. + */ +int LL_Poolacc_Init(int id, const LL_Poolacc_InitTypeDef *conf) +{ + uint32_t t; + + if (id >= ATON_POOL_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_POOL_CLKB_CLK(id)); + +#ifdef POOL_RC14 + /* Clear pipeline */ + t = ATON_POOL_CTRL_GET(id); + t = ATON_POOL_CTRL_SET_EN(t, 0); + t = ATON_POOL_CTRL_SET_CLR(t, 1); + t = ATON_POOL_CTRL_SET_CONFCLR(t, 1); + ATON_POOL_CTRL_SET(id, t); +#endif // POOL_RC14 + + /* Initialize CTRL register parameters */ + t = ATON_POOL_CTRL_DT; + t = ATON_POOL_CTRL_SET_TYPE(t, get_Poolacc_type(conf->operation)); + t = ATON_POOL_CTRL_SET_ROUND(t, (conf->rounding_o != 0)); + t = ATON_POOL_CTRL_SET_SAT(t, (conf->saturation_o != 0)); + t = ATON_POOL_CTRL_SET_OUTSHIFT(t, conf->shift_o); + t = ATON_POOL_CTRL_SET_FBYTES(t, conf->inbytes_f); + t = ATON_POOL_CTRL_SET_FSHIFT(t, ATON_SHIFT(conf->shift_f)); + t = ATON_POOL_CTRL_SET_FROUND(t, (conf->rounding_f != 0)); + t = ATON_POOL_CTRL_SET_FSAT(t, (conf->saturation_f != 0)); +#ifdef ATON_POOL_CTRL_SET_AVGNOPAD + t = ATON_POOL_CTRL_SET_AVGNOPAD(t, (conf->avgnopad != 0)); +#endif + t = ATON_POOL_CTRL_SET_DUALLINE(t, conf->dualLine); +#if 0 + int crop_en = ((conf->leftCrop > 0) || (conf->rightCrop > 0) || (conf->topCrop > 0) || (conf->bottomCrop > 0)); +#else + int crop_en = 1; +#endif + t = ATON_POOL_CTRL_SET_CROPEN(t, crop_en); + ATON_POOL_CTRL_SET(id, t); + + /* configure remaining in/out shifters */ + t = ATON_POOL_RNDCTRL_DT; + t = ATON_POOL_RNDCTRL_SET_FOBYTES(t, conf->outbytes_f); + t = ATON_POOL_RNDCTRL_SET_FRNDMODE(t, conf->round_mode_f); + t = ATON_POOL_RNDCTRL_SET_OBYTES(t, conf->outbytes_o); + t = ATON_POOL_RNDCTRL_SET_ORNDMODE(t, (conf->relu_mode_o << 1) | conf->round_mode_o); + ATON_POOL_RNDCTRL_SET(id, t); + + /* Configure Pooling unit dimensions register */ + t = ATON_POOL_PDIMS_DT; + t = ATON_POOL_PDIMS_SET_WINX(t, conf->poolWinX); + t = ATON_POOL_PDIMS_SET_WINY(t, conf->poolWinY); + t = ATON_POOL_PDIMS_SET_STRDX(t, conf->strideX); + t = ATON_POOL_PDIMS_SET_STRDY(t, conf->strideY); + t = ATON_POOL_PDIMS_SET_TPAD(t, conf->topPad); + t = ATON_POOL_PDIMS_SET_BPAD(t, conf->bottomPad); + t = ATON_POOL_PDIMS_SET_LPAD(t, conf->leftPad); + t = ATON_POOL_PDIMS_SET_RPAD(t, conf->rightPad); + t = ATON_POOL_PDIMS_SET_BSIZE(t, conf->batchSize); + ATON_POOL_PDIMS_SET(id, t); + + /* Configure Pooling unit FDIMS register */ + t = ATON_POOL_FDIMS_DT; + t = ATON_POOL_FDIMS_SET_FEATX(t, conf->inputX * conf->batchSize); + t = ATON_POOL_FDIMS_SET_FEATY(t, conf->inputY); + ATON_POOL_FDIMS_SET(id, t); + + /* Configure Pooling unit OUTDIMS register */ + t = ATON_POOL_OUTDIMS_DT; + t = ATON_POOL_OUTDIMS_SET_FEATX(t, conf->outputX); + t = ATON_POOL_OUTDIMS_SET_FEATY(t, conf->outputY); + ATON_POOL_OUTDIMS_SET(id, t); + + /* Configure mulval */ + t = ATON_POOL_MULVAL_DT; + t = ATON_POOL_MULVAL_SET_MULVAL(t, conf->mulval); + ATON_POOL_MULVAL_SET(id, t); + + /* Mulval is scattered across different registers from V3 onwards. TODO: use ATON.h macros */ +#if (ATON_POOL_VERSION_MAJOR_DT >= 3) + unsigned int wsize = conf->poolWinX * conf->poolWinY; + if (wsize > 0 && wsize < 9) + { + uint32_t *mulval_addr = (uint32_t *)ATON_POOL_MULVAL_1_2_ADDR(id); + wsize--; + mulval_addr += (wsize / 2); + if (wsize & 1) + *mulval_addr |= ((conf->mulval) << 16); + else + *mulval_addr |= conf->mulval; + } +#endif + + /* Configure cropping if needed */ + t = ATON_POOL_XCROP_DT; + if (conf->leftCrop > 0) + t = ATON_POOL_XCROP_SET_LCROP(t, conf->leftCrop * conf->batchSize); + int r_crop = conf->rightCrop * conf->batchSize + (conf->batchSize - 1); + if (r_crop > 0) + t = ATON_POOL_XCROP_SET_RCROP(t, conf->rightCrop * conf->batchSize + (conf->batchSize - 1)); + ATON_POOL_XCROP_SET(id, t); + + t = ATON_POOL_YCROP_DT; + if (conf->topCrop > 0) + t = ATON_POOL_YCROP_SET_TCROP(t, conf->topCrop); + if (conf->bottomCrop > 0) + t = ATON_POOL_YCROP_SET_BCROP(t, conf->bottomCrop); + ATON_POOL_YCROP_SET(id, t); + +#ifdef ATON_POOL_USER_PAD_VALUE_SET + if (conf->pad_val_en) + { + t = ATON_POOL_USER_PAD_VALUE_DT; + t = ATON_POOL_USER_PAD_VALUE_SET_PADVAL(t, conf->pad_val); + t = ATON_POOL_USER_PAD_VALUE_SET_PADVALEN(t, 1); + ATON_POOL_USER_PAD_VALUE_SET(id, t); + } +#endif + + return 0; +} +#endif // ATON_POOL_NUM + +#if defined(ATON_EPOCHCTRL_NUM) +/** + * @brief Configure Epoch Controller + * @param id Epoch Controller identifier [0..ATON_EPOCHCTRL_NUM-1] + * @param conf Structure describing Epoch Controller initialization parameters + * @retval Error code + */ +int LL_EpochCtrl_Init(int id, const LL_EpochCtrl_InitTypeDef *conf) +{ + uint32_t t; + + if (id >= ATON_EPOCHCTRL_NUM) + return LL_ATON_INVALID_ID; + + LL_ATON_EnableClock(ATON_EPOCHCTRL_CLKB_CLK(id)); + + /* Configure CTRL register */ + t = ATON_EPOCHCTRL_CTRL_DT; + t = ATON_EPOCHCTRL_CTRL_SET_SM(t, conf->stepmode); + ATON_EPOCHCTRL_CTRL_SET(id, t); + + /* Check address is 8 byte aligned */ + if (conf->blobaddr & 0x7) + return LL_ATON_INVALID_PARAM; + + ATON_EPOCHCTRL_ADDR_SET(id, conf->blobaddr); + + return LL_ATON_OK; +} + +/** + * @brief Trigger Epoch Controller Single Step execution + * @param id Epoch Controller identifier [0..ATON_EPOCHCTRL_NUM-1] + * @retval Error code + */ +int LL_EpochCtrl_Step(int id) +{ + uint32_t t; + + t = ATON_EPOCHCTRL_IRQ_GET(id); + t = ATON_EPOCHCTRL_IRQ_SET_SM(t, 1); + ATON_EPOCHCTRL_IRQ_SET(id, t); + + return 0; +} + +/** + * @brief Waits for epoch controller to become idle + * @param id Bitmask of EC identifiers + * @retval Error code + */ +int LL_EpochCtrl_Wait(uint32_t mask) +{ + int i; + uint32_t enableFlags; + + startWatchdog(ATON_EPOCH_TIMEOUT); + + do + { + enableFlags = 0; + for (i = 0; i < ATON_EPOCHCTRL_NUM; i++) + { + if (mask & (1 << i)) + { + enableFlags |= (ATON_EPOCHCTRL_CTRL_GET(i) & (1U << ATON_EPOCHCTRL_CTRL_RUNNING_LSB)); + } + } + + LL_ATON_ASSERT(checkWatchdog() == 0); + + } while (enableFlags); + + return LL_ATON_OK; +} + +/** + * @brief Returns the size of a blob + * @param eb_addr Pointer to blob + * @retval Size in bytes of the blob + */ +unsigned int LL_EpochCtrl_GetBlobSize(uint32_t *eb_addr) +{ + unsigned bloblines = eb_addr[1] + 2; + return bloblines * 4; +} +#endif // ATON_EPOCHCTRL_NUM + +void LL_ATON_EnableClock(unsigned int clock) +{ +#if (LL_ATON_ENABLE_CLOCK_GATING == 1) + ATON_REG_WRITE_FIELD_RANGE(CLKCTRL, 0, BGATES, clock, 1, 1); +#endif +} + +void LL_ATON_DisableClock(unsigned int clock) +{ +#if (LL_ATON_ENABLE_CLOCK_GATING == 1) + ATON_REG_WRITE_FIELD_RANGE(CLKCTRL, 0, BGATES, clock, 1, 0); +#endif +} + +/** + * @brief DMA version of a memcpy functionality, this function could be overloaded if a system DMA could be used + * @param dst destination memory address + * @param src source memory address + * @param src_limit memory pool end address of `src` + * @param n number of bytes to be transferred + * @param dst_cached Destination under cache flag + * @param dst_cached Source under cache flag + * @retval Error code E.g.: Invalid ID, invalid parameters, not idle,.. + * + * @note: This function completely undermines any possibility for integrating correctly + * SW operators (or any other functionality which calls this function) in any of the three ATON runtime + * scheduling modes. In other words, function `LL_ATON_Dma_memcpy()` and its usage are incompatible with the ATON + * runtime. Therefore either `memcpy()` should be used in its place or calls to `LL_ATON_Dma_memcpy()` need to be + * transformed in a sequence of "epoch blocks" which can be integrated with the ATON runtime (as an example see the + * ATON-accelerated implementation of operator `Concat`)! + */ +/* N.B. assumes DMA0 and 1 are free to use */ +#define MIN_BUFF_LEN 40 +LL_ATON_WEAK void *LL_ATON_Dma_memcpy(void *dst, void *src, void *src_limit, size_t n, int dst_cached, int src_cached) +{ + uint8_t *_dst_orig = dst; + + int prolog_len = (n % 3); + int i; + uint8_t *_dst = (uint8_t *)dst; + uint8_t *_src = (uint8_t *)src; + + if (n < MIN_BUFF_LEN) + prolog_len = n; // not worth it ... + // LL_ATON_PRINTF("n=%d prolog=%d\n",n,prolog_len); + + for (i = 0; i < prolog_len; i++) + *_dst++ = *_src++; + n -= prolog_len; + + if (prolog_len > 0) + { + /* *** MCU cache clean & invalidate operation (SW) *** */ + LL_ATON_Cache_MCU_Clean_Invalidate_Range(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR((uintptr_t)_dst_orig), prolog_len); + } + + if (n > 0) + { + LL_Streng_TensorInitTypeDef dma_in = { + .dir = 0, + .addr_base = {_src}, + .offset_start = 0, + .offset_end = n, + .offset_limit = ((uintptr_t)src_limit - (uintptr_t)src), // awful FIXME Francesco + .raw = 1, + .frame_count = 0, + .fwidth = 0, + .fheight = 0, + .batch_depth = 0, + .batch_offset = 0, + .frame_offset = n, + .line_offset = 0, + .loop_offset = 0, + .frame_loop_cnt = 0, + .frame_tot_cnt = 1, + .nbits_in = 24, + .nbits_out = 24, + .nbits_unsigned = 0, + .align_right = 0, + .noblk = 0, + }; + + LL_Streng_TensorInitTypeDef dma_out = { + .dir = 1, + .addr_base = {_dst}, + .offset_start = 0, + .offset_end = n, + .raw = 1, + .frame_count = 0, + .fwidth = 0, + .fheight = 0, + .batch_depth = 0, + .batch_offset = 0, + .frame_offset = n, + .line_offset = 0, + .loop_offset = 0, + .frame_loop_cnt = 0, + .frame_tot_cnt = 1, + .nbits_in = 24, + .nbits_out = 24, + .nbits_unsigned = 0, + .align_right = 0, + .noblk = 0, + }; + + if (src_cached) + { + dma_in.cacheable = 1; + dma_in.cache_allocate = 1; + } + + if (dst_cached) + { + dma_out.cacheable = 1; + dma_out.cache_allocate = 1; + } + + const LL_Switch_InitTypeDef switch_init = {LL_Switch_Init_Dest() = ATONN_DSTPORT(STRSWITCH, 0, STRENG, 1, 0), + LL_Switch_Init_Source(0) = ATONN_SRCPORT(STRSWITCH, 0, STRENG, 0, 0), + LL_Switch_Init_Context(0) = 1, LL_Switch_Init_Frames(0) = 0}; + const LL_ATON_EnableUnits_InitTypeDef dma_units[] = {{{STRENG, 1}}, {{STRENG, 0}}}; + const uint32_t dma_wait_mask = 0x2; + + LL_Streng_TensorInit(0, &dma_in, 1); + LL_Streng_TensorInit(1, &dma_out, 1); + LL_Switch_Init(&switch_init, 1); + LL_ATON_EnableUnits_Init(dma_units, 2); + LL_Streng_Wait(dma_wait_mask); + LL_ATON_DisableUnits_Init(dma_units, 1); + LL_Switch_Deinit(&switch_init, 1); + } + + return dst; +} + +#if (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE) +static void *ec_aton_base; + +uintptr_t get_ec_aton_base(void) +{ + return (uintptr_t)ec_aton_base; +} + +void initialize_ec_aton_base(void) +{ + ec_aton_base = malloc(ATON_SIZE); +} + +/* Called by patched ATON.h to trace ATON register stores */ +void ec_trace_write(uintptr_t dstreg, unsigned int val) +{ + uint32_t IP_id = ec_trace_get_IP_id(dstreg); + uint32_t regaddr_offset = dstreg - (uintptr_t)ATON_BASE; + uint32_t REG_id = ec_trace_get_REG_id(regaddr_offset); + ec_trace_reg_write(IP_id, REG_id, val); +} + +void ec_trace_write_reloc(uintptr_t dstreg, unsigned int base, unsigned int offset) +{ + uint32_t IP_id = ec_trace_get_IP_id(dstreg); + uint32_t regaddr_offset = dstreg - (uintptr_t)ATON_BASE; + uint32_t REG_id = ec_trace_get_REG_id(regaddr_offset); + ec_trace_reg_write_reloc(IP_id, REG_id, base, offset); +} + +unsigned int ec_trace_get_IP_id(uintptr_t dstreg) +{ + uint32_t regaddr_offset = dstreg - (uintptr_t)ATON_BASE; + uint32_t IP_id = (uint32_t)((regaddr_offset & 0x0ffff000) >> 12); + return IP_id; +} +unsigned int ec_trace_get_REG_id(unsigned int regoffset) +{ + return (regoffset & 0xfff) >> 2; +} + +void ec_trace_wait_epoch_end(uint32_t wait_mask) +{ + // TODO: Only polling mode supported at the moment + for (unsigned i = 0; i < 32; i++) + { + if (wait_mask & (1 << i)) + { + ATON_REG_POLL(STRENG, i, CTRL, RUNNING, 0); + } + } +} + +#endif diff --git a/lib/stai/libstai/ll_aton/ll_aton_cipher.c b/lib/stai/libstai/ll_aton/ll_aton_cipher.c new file mode 100644 index 000000000..90413bb0c --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_cipher.c @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file ll_aton_cipher.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_cipher.h" +#include "ll_aton.h" +#include "ll_aton_platform.h" + +#if !defined(DEFAULT_WEIGHT_ENCRYPTION_ID) +#define DEFAULT_WEIGHT_ENCRYPTION_ID 0 +#endif +#if !defined(DEFAULT_WEIGHT_ENCRYPTION_ROUNDS) +#define STRENG_WEIGHT_ENCRYPTION_ROUNDS_12 0 +#define STRENG_WEIGHT_ENCRYPTION_ROUNDS_9 1 +#define DEFAULT_WEIGHT_ENCRYPTION_ROUNDS STRENG_WEIGHT_ENCRYPTION_ROUNDS_12 +#endif +#if !defined(DEFAULT_WEIGHT_KEY_SEL) +#define DEFAULT_WEIGHT_KEY_SEL 0 +#endif + +#if (ATON_STRENG_VERSION_ENCR_DT == 1) +/** + * @brief Configures the Streaming Engine Encryption support + * @param id Streaming engine identifier [0..ATON_STRENG_NUM-1] + * @param LL_Streng_EncryptionStruct Pointer to structure describing encryption parameters + * @note Encryption keys are set in the Bus Interfaces using LL_Busif_SetKeys function + * @note Each Stream Engine is associated to a Bus Interface. Machine descriptor json file describes how they are + * grouped + */ +int LL_Streng_EncryptionInit(int id, LL_Streng_EncryptionTypedef *LL_Streng_EncryptionStruct) +{ + uint32_t t; + + if (id >= ATON_STRENG_NUM) + return LL_ATON_INVALID_ID; + + t = LL_Streng_EncryptionStruct->encryption_id & 0xffffffff; + ATON_STRENG_ENCR_LSB_SET(id, t); + + t = ATON_STRENG_ENCR_MSB_DT; + t = ATON_STRENG_ENCR_MSB_SET_ID_MSB(t, (LL_Streng_EncryptionStruct->encryption_id >> 32) & 0x7ff); + t = ATON_STRENG_ENCR_MSB_SET_EN(t, LL_Streng_EncryptionStruct->enable); + t = ATON_STRENG_ENCR_MSB_SET_ROUNDS(t, LL_Streng_EncryptionStruct->rounds); + t = ATON_STRENG_ENCR_MSB_SET_KEY_SEL(t, LL_Streng_EncryptionStruct->key_sel); + t = ATON_STRENG_ENCR_MSB_SET_INC(t, LL_Streng_EncryptionStruct->increment); + ATON_STRENG_ENCR_MSB_SET(id, t); + + return 0; +} + +int LL_Streng_WeightEncryptionInit(int id) +{ + LL_Streng_EncryptionTypedef LL_Streng_EncryptionStruct = { + .enable = 1, + .encryption_id = DEFAULT_WEIGHT_ENCRYPTION_ID, + .rounds = DEFAULT_WEIGHT_ENCRYPTION_ROUNDS, + .key_sel = DEFAULT_WEIGHT_KEY_SEL, + .increment = 0, + }; + return LL_Streng_EncryptionInit(id, &LL_Streng_EncryptionStruct); +} + +/** + * @brief Configures Bus Interface encryption keys + * @param id, Bus Interface identifier [0..ATON_BUSIF_NUM-1] + * @param key Selects key to configure [0..1] + * @param key_low lowest 64 bits of the key + * @param key_hi highest 64 bits of the key + */ +int LL_Busif_SetKeys(int id, int key, uint64_t key_low, uint64_t key_hi) +{ + if (id >= ATON_BUSIF_NUM) + return LL_ATON_INVALID_ID; + + if (key == 0) + { + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY0_31_0_IDX, ATON_BUSIF_0_KEY0_31_0_S, key_low & 0xffffffff); + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY0_63_32_IDX, ATON_BUSIF_0_KEY0_63_32_S, key_low >> 32); + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY0_95_64_IDX, ATON_BUSIF_0_KEY0_95_64_S, key_hi & 0xffffffff); + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY0_127_96_IDX, ATON_BUSIF_0_KEY0_127_96_S, key_hi >> 32); + } + else if (key == 1) + { + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY1_31_0_IDX, ATON_BUSIF_0_KEY1_31_0_S, key_low & 0xffffffff); + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY1_63_32_IDX, ATON_BUSIF_0_KEY1_63_32_S, key_low >> 32); + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY1_95_64_IDX, ATON_BUSIF_0_KEY1_95_64_S, key_hi & 0xffffffff); + ATON_BUSIF_KEY_SET(id, ATON_BUSIF_0_KEY1_127_96_IDX, ATON_BUSIF_0_KEY1_127_96_S, key_hi >> 32); + } + else + { + return LL_ATON_INVALID_ID; + } + + return 0; +} + +/** + * @brief Configures Epoch Controller Encryption support + * @param id Epoch Controller identifier [0..ATON_EPOCHCTRL_NUM-1] + * @param conf Pointer to LL_Streng_EncryptionTypedef structure describing Encryption parameters + * @retval Error code + * @note Encryption configuration structure is the same as the Stream Engine one + * @note Encryption keys are set in the Epoch Controller's Bus Interface using LL_Busif_SetKeys function + * @note Epoch Controller Bus Interface ID is ATON_BUSIF_NUM-1 + */ +int LL_EpochCtrl_EncryptionInit(int id, LL_Streng_EncryptionTypedef *conf) +{ + uint32_t t; + + if (id >= ATON_EPOCHCTRL_NUM) + return LL_ATON_INVALID_ID; + + t = conf->encryption_id & 0xffffffff; + ATON_EPOCHCTRL_ENCR_LSB_SET(id, t); + + t = ATON_EPOCHCTRL_ENCR_MSB_DT; + t = ATON_EPOCHCTRL_ENCR_MSB_SET_ID_MSB(t, (conf->encryption_id >> 32) & 0x7ff); + t = ATON_EPOCHCTRL_ENCR_MSB_SET_EN(t, conf->enable); + t = ATON_EPOCHCTRL_ENCR_MSB_SET_ROUNDS(t, conf->rounds); + t = ATON_EPOCHCTRL_ENCR_MSB_SET_KEY_SEL(t, conf->key_sel); + ATON_EPOCHCTRL_ENCR_MSB_SET(id, t); + + return 0; +} + +/** + * @brief Handles Dma/Cypher data transfer + * @param cypherInfo: transfer parameters (addresses, keys, ... ) + * @retval Error code (0: og - -1: ko) + * @note The function uses stream engines 0 and 1 + * @note It uses default (0) values for encryption id and round (12) + */ + +int LL_DmaCypherInit(LL_Cypher_InitTypeDef *cypherInfo) +{ + uint32_t limit; + uint32_t lastAdd; + + if (cypherInfo->cypherCacheMask != 0 && cypherInfo->len > CYPHER_CACHE_SIZE) + { + return (-1); + } + + LL_ATON_Init(); + + /* Use stream engine 0 as source channel */ + + lastAdd = cypherInfo->srcAdd + cypherInfo->len; + limit = (uint32_t)cypherInfo->len + (8 - (lastAdd & 7)); + limit += (8 - (limit & 7)); + + LL_Streng_TensorInitTypeDef dma_in = {.dir = 0, + .addr_base.i = (uint32_t)cypherInfo->srcAdd, + .offset_start = 0, + .offset_end = (uint32_t)cypherInfo->len, + .offset_limit = limit, + .raw = 1, + .frame_tot_cnt = 1, + .nbits_in = 8, + .nbits_out = 8, + .nbits_unsigned = 0}; + + /* Use stream engine 0 as destination channel */ + + lastAdd = cypherInfo->dstAdd + cypherInfo->len; + limit = (uint32_t)cypherInfo->len + (8 - (lastAdd & 7)); + limit += (8 - (limit & 7)); + + LL_Streng_TensorInitTypeDef dma_out = {.dir = 1, + .addr_base.i = (uint32_t)cypherInfo->dstAdd, + .offset_start = 0, + .offset_end = (uint32_t)cypherInfo->len, + .offset_limit = limit, + .raw = 1, + .frame_tot_cnt = 1, + .nbits_in = 8, + .nbits_out = 8, + .nbits_unsigned = 0}; + + if (0 != (cypherInfo->cypherCacheMask & CYPHER_CACHE_SRC)) + { + dma_in.cacheable = 1; + dma_in.cache_allocate = 1; + } + else + { + dma_in.cacheable = 0; + dma_in.cache_allocate = 0; + } + + if (0 != (cypherInfo->cypherCacheMask & CYPHER_CACHE_DST)) + { + dma_out.cacheable = 1; + dma_out.cache_allocate = 1; + } + else + { + dma_out.cacheable = 0; + dma_out.cache_allocate = 0; + } + + /* Configure stream switch */ + + const LL_Switch_InitTypeDef switch_init = {LL_Switch_Init_Dest() = ATONN_DSTPORT(STRSWITCH, 0, STRENG, 1, 0), + LL_Switch_Init_Source(0) = ATONN_SRCPORT(STRSWITCH, 0, STRENG, 0, 0), + LL_Switch_Init_Context(0) = 1, LL_Switch_Init_Frames(0) = 0}; + + /* Initialize stream engines */ + + const LL_ATON_EnableUnits_InitTypeDef dma_units[] = {{{STRENG, 1}}, {{STRENG, 0}}}; + + if (cypherInfo->cypherEnableMask != 0) + { + if ((cypherInfo->cypherEnableMask & CYPHER_SRC_MASK) != 0) + { + /* Enable encryption on input stream engine */ + dma_in.cipher_en = 1; + } + else if ((cypherInfo->cypherEnableMask & CYPHER_DST_MASK) != 0) + { + /* Enable encryption on output stream engine */ + + dma_out.cipher_en = 1; + } + else + { + return (-1); + } + + /* Set encryption keys into Bus Interafce */ + + LL_Busif_SetKeys(0, 0, cypherInfo->busIfKeyLsb, cypherInfo->busIfKeyMsb); + } + + LL_Streng_TensorInit(CYPHER_SRC_STRENG_ID, &dma_in, 1); + LL_Streng_TensorInit(CYPHER_DST_STRENG_ID, &dma_out, 1); + + /* Enable stream switch */ + + LL_Switch_Init(&switch_init, 1); + + /* Start */ + + LL_ATON_EnableUnits_Init(dma_units, 2); + + /* Wait for end of transfer */ + + const uint32_t dma_wait_mask = 1 << CYPHER_DST_STRENG_ID; // Wait for destination stream engine + + LL_Streng_Wait(dma_wait_mask); + + /* Disabkle and deinit */ + + LL_ATON_DisableUnits_Init(dma_units, 1); + + LL_Switch_Deinit(&switch_init, 1); + + return (0); +} + +#endif //(ATON_STRENG_VERSION_ENCR_DT == 1) diff --git a/lib/stai/libstai/ll_aton/ll_aton_dbgtrc.c b/lib/stai/libstai/ll_aton/ll_aton_dbgtrc.c new file mode 100644 index 000000000..6940832d2 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_dbgtrc.c @@ -0,0 +1,1086 @@ +/** + ****************************************************************************** + * @file ll_aton_dbgtrc.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON Debug and Trace unit LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include + +#include "ll_aton.h" +#include "ll_aton_dbgtrc.h" +#include "ll_aton_util.h" + +#if defined(ATON_DEBUG_TRACE_NUM) + +/** + * @brief Initializes the Debug and Trace unit + * @param id Id of the target debug and trace unit to be initialized + */ +int LL_Dbgtrc_Init(int id) +{ + uint32_t t = ATON_DEBUG_TRACE_CTRL_DT(id); + + /* Enable clock and unit */ + LL_ATON_EnableClock(ATON_DEBUG_TRACE_CLKB_CLK(id)); + + /* Start tracers, if available */ +#ifdef ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS +#if ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS(0) > 0 + /* Start now */ + ATON_DEBUG_TRACE_START_LSB_SET(id, 0x0); + ATON_DEBUG_TRACE_START_MSB_SET(id, 0x0); + + /* Stop never */ + ATON_DEBUG_TRACE_STOP_LSB_SET(id, 0xffffffff); + ATON_DEBUG_TRACE_STOP_MSB_SET(id, 0xffffffff); + + /* Use timestamps as start/stop conditions */ + t = ATON_DEBUG_TRACE_CTRL_SET_TRACE_START_EVTYPE(t, 1); + t = ATON_DEBUG_TRACE_CTRL_SET_TRACE_STOP_EVTYPE(t, 1); +#endif +#endif + + t = ATON_DEBUG_TRACE_CTRL_SET_EN(t, 1); + + ATON_DEBUG_TRACE_CTRL_SET(id, t); + + return 0; +} + +/** + * @brief Deinitializes the Debug and Trace unit + * @param id Id of the target debug and trace unit to be deinitialized + */ +int LL_Dbgtrc_Deinit(int id) +{ + /* Disable unit and gate its clock */ + ATON_DEBUG_TRACE_CTRL_SET(id, 0); + + LL_ATON_DisableClock(ATON_DEBUG_TRACE_CLKB_CLK(id)); + + return 0; +} + +/** + * @brief Enables Debug and Trace Unit clock via Clock Controller unit + * @note This is used as method/workaround to start counters synchronously + * @todo Fix for Puma design + */ +void LL_Dbgtrc_EnableClock(void) +{ + uint32_t t = ATON_CLKCTRL_BGATES_GET(0); + t |= (1 << ATON_DEBUG_TRACE_CLKB_CLK(0)); + ATON_CLKCTRL_BGATES_SET(0, t); +} + +/** + * @brief Disables Debug and Trace Unit clock via Clock Controller unit + * @note This is used as method/workaround to stop counters synchronously + * @todo Fix for Puma design + */ +void LL_Dbgtrc_DisableClock(void) +{ + uint32_t t = ATON_CLKCTRL_BGATES_GET(0); + t &= ~(1 << ATON_DEBUG_TRACE_CLKB_CLK(0)); + ATON_CLKCTRL_BGATES_SET(0, t); +} + +/** + * @brief Returns the status of current stall signals + * @note This function is deprecated, use LL_Dbgtrc_Read_IStall/LL_Dbgtrc_Read_OStall instead + * @param iolink If not zero return the status of the Input Links. Return the Output Links otherwise + * @retval Stall signals bitfield + */ +uint64_t LL_Dbgtrc_Read_Stalls(int id, unsigned char iolink) +{ + uint64_t stalls = 0; + + if (iolink) + { + stalls = (uint64_t)ATON_DEBUG_TRACE_ILINK_STATES_GET(id, 0); + if (ATON_DEBUG_TRACE_ILINK_STATES_IDX_MAX(id) > 0) + stalls |= (uint64_t)ATON_DEBUG_TRACE_ILINK_STATES_GET(id, 1) << 32; + } + else + { + stalls = (uint64_t)ATON_DEBUG_TRACE_OLINK_STATES_GET(id, 0); + if (ATON_DEBUG_TRACE_ILINK_STATES_IDX_MAX(id) > 0) + stalls |= (uint64_t)ATON_DEBUG_TRACE_OLINK_STATES_GET(id, 1) << 32; + } + + return stalls; +} + +/** + * @brief Returns the status of a given input stall signal + * @param signal Input stall signal id + * @retval Status of the stall signal (0 or 1). -1 if error + */ +int LL_Dbgtrc_Read_IStall(int id, unsigned int signal) +{ + int idx = signal >> 5; + int bitpos = signal & 0x1f; + + if (idx > ATON_DEBUG_TRACE_ILINK_STATES_IDX_MAX(id)) + return -1; + + return (ATON_DEBUG_TRACE_ILINK_STATES_GET(id, idx) >> bitpos) & 1; +} + +/** + * @brief Returns the status of a given output stall signal + * @param signal Output stall signal id + * @retval Status of the stall signal (0 or 1). -1 if error + */ +int LL_Dbgtrc_Read_OStall(int id, unsigned int signal) +{ + int idx = signal >> 5; + int bitpos = signal & 0x1f; + + if (idx > ATON_DEBUG_TRACE_OLINK_STATES_IDX_MAX(id)) + return -1; + + return (ATON_DEBUG_TRACE_OLINK_STATES_GET(id, idx) >> bitpos) & 1; +} + +/** + * @brief Initializes and starts a trigger + * @param id Id of the target debug and trace unit + * @param trigger The trigger to be used [0..7] + * @param Trigger_InitStruct Trigger descriptor structure + * @note Triggers can be captured via CoreSight System Trace Macrocell (STM) + */ +int LL_Dbgtrc_Trigger_Init(int id, int trigger, LL_Dbgtrc_Trigger_InitTypedef *Trigger_InitStruct) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_TRIG_ADDR(id, trigger)); + uint32_t t = ATON_DEBUG_TRACE_TRIG_DT; + + t = ATON_DEBUG_TRACE_TRIG_SET_SEL(t, Trigger_InitStruct->signal); + t = ATON_DEBUG_TRACE_TRIG_SET_EVENT_TYPE(t, Trigger_InitStruct->evt_type); + t = ATON_DEBUG_TRACE_TRIG_SET_FILTER(t, Trigger_InitStruct->filter); + t = ATON_DEBUG_TRACE_TRIG_SET_EN(t, 1); + *reg = t; + + return 0; +} + +/** + * @brief Generates software trigger + * @param id Id of the target debug and trace unit + * @param trigger Destination trigger [0..7] + */ +int LL_Dbgtrc_Trigger_Swtrig(int id, int trigger) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_TRIG_ADDR(id, trigger)); + *reg |= (1 << ATON_DEBUG_TRACE_TRIG_SWTRIG_LSB); + + return 0; +} + +/** + * @brief Returns the overrunt status of a given trigger + * @param id Id of the target debug and trace unit + * @param trigger Destination trigger [0..7] + * @retval Overrun bit status + */ +int LL_Dbgtrc_Trigger_GetOVR(int id, int trigger) +{ + uint32_t ovr; + + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_TRIG_ADDR(id, trigger)); + ovr = *reg & ATON_DEBUG_TRACE_TRIG_OVR_MASK; + + return ovr == 0 ? 0 : 1; +} + +/** + * @brief Configure a counter + * @param id Id of the target debug and trace unit + * @param counter The counter to be used [0..15] + * @param Counter_InitStruct Counter descriptor structure + */ +int LL_Dbgtrc_Counter_Init(int id, int counter, LL_Dbgtrc_Counter_InitTypdef *Counter_InitStruct) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_ADDR(id, counter)); + uint32_t t = ATON_DEBUG_TRACE_EVENT_DT; + + t = ATON_DEBUG_TRACE_EVENT_SET_SEL(t, Counter_InitStruct->signal); + t = ATON_DEBUG_TRACE_EVENT_SET_EVENT_TYPE(t, Counter_InitStruct->evt_type); + t = ATON_DEBUG_TRACE_EVENT_SET_WRAP(t, Counter_InitStruct->wrap); + t = ATON_DEBUG_TRACE_EVENT_SET_CNT_DOWN(t, Counter_InitStruct->countdown); + t = ATON_DEBUG_TRACE_EVENT_SET_INT_DISABLE(t, Counter_InitStruct->int_disable); + + *reg = t; + + reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_CNT_ADDR(id, counter)); + *reg = Counter_InitStruct->counter; + + return 0; +} + +/** + * @brief Start a counter + * @param id Id of the target debug and trace unit + * @param counter The counter to be used [0..15] + * @note Do not use this when binding a Start event or the counter will start + */ +int LL_Dbgtrc_Counter_Start(int id, int counter) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_ADDR(id, counter)); + uint32_t t = *reg; + + t = ATON_DEBUG_TRACE_EVENT_SET_EN(t, 1); + *reg = t; + + return 0; +} + +/** + * @brief Stop a counter + * @param id Id of the target debug and trace unit + * @param counter The counter to be used [0..15] + * @note Do not use this when binding a Stop event or the counter will stop + */ +int LL_Dbgtrc_Counter_Stop(int id, int counter) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_ADDR(id, counter)); + uint32_t t = *reg; + + t = ATON_DEBUG_TRACE_EVENT_SET_EN(t, 0); + *reg = t; + + return 0; +} + +/** + * @brief Returns the counter value of a given observer + * @param id Id of the target debug and trace unit + * @param counter The counter to be used [0..15] + * @retval Counter's value + */ +uint32_t LL_Dbgtrc_Counter_Read(int id, int counter) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_CNT_ADDR(id, counter)); + return *reg; +} + +/** + * @brief Binds the start of a counter to another counters' countdown event + * @param id Id of the target debug and trace unit + * @param srccounter The counter which triggers the Start event of the dstcounter + * @param dstcounter The counter which starts upon srccounter contdown event + * @TODO: add parameters checkers, e.g. throw error if source counter countdown is not enabled + */ +int LL_Dbgtrc_Counter_BindStart(int id, int srccounter, int dstcounter) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_ADDR(id, dstcounter)); + uint32_t t = *reg; + + t = ATON_DEBUG_TRACE_EVENT_SET_START_EVENT_EN(t, 1); + t = ATON_DEBUG_TRACE_EVENT_SET_START_EVENT_SEL(t, srccounter); + *reg = t; + + return 0; +} + +/** + * @brief Binds the stop of a counter to another counters' countdown event + * @param id Id of the target debug and trace unit + * @param srccounter The counter which triggers the Stop event of the dstcounter + * @param dstcounter The counter which starts upon srccounter contdown event + * @TODO: add parameters checkers, e.g. throw error if source counter countdown is not enabled + */ +int LL_Dbgtrc_Counter_BindStop(int id, int srccounter, int dstcounter) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_EVENT_ADDR(id, dstcounter)); + uint32_t t = *reg; + + t = ATON_DEBUG_TRACE_EVENT_SET_STOP_EVENT_EN(t, 1); + t = ATON_DEBUG_TRACE_EVENT_SET_STOP_EVENT_SEL(t, srccounter); + *reg = t; + + return 0; +} + +/** + * @brief Configures a stopwatch + * @param id The Debug and Trace unit id to be used + * @param StopWatch_InitStruct Stopwatch descriptor structure + */ +int LL_Dbgtrc_Counter_StopWatch(int id, LL_Dbgtrc_StopWatch_InitTypdef *StopWatch_InitStruct) +{ + LL_Dbgtrc_Counter_InitTypdef counterConf = {0}; + + /* Configure stopwatch start event */ + counterConf.signal = StopWatch_InitStruct->startSignal; + counterConf.evt_type = StopWatch_InitStruct->startEvent; + counterConf.wrap = 0; + counterConf.countdown = 1; + counterConf.int_disable = 1; + counterConf.counter = 0; + LL_Dbgtrc_Counter_Init(id, StopWatch_InitStruct->startCounter, &counterConf); + + /* Configure stopwatch stop event */ + counterConf.signal = StopWatch_InitStruct->stopSignal; + counterConf.evt_type = StopWatch_InitStruct->stopEvent; + counterConf.wrap = 0; + counterConf.countdown = 1; + counterConf.int_disable = 1; + counterConf.counter = 0; + LL_Dbgtrc_Counter_Init(id, StopWatch_InitStruct->stopCounter, &counterConf); + + /* Configure main counter, bind start/stop counters to it and start them */ + counterConf.signal = DBGTRC_VDD; + counterConf.evt_type = DBGTRC_EVT_HI; + counterConf.wrap = 0; + counterConf.countdown = 0; + counterConf.int_disable = 1; + LL_Dbgtrc_Counter_Init(id, StopWatch_InitStruct->mainCounter, &counterConf); + + LL_Dbgtrc_Counter_BindStart(id, StopWatch_InitStruct->startCounter, StopWatch_InitStruct->mainCounter); + LL_Dbgtrc_Counter_BindStop(id, StopWatch_InitStruct->stopCounter, StopWatch_InitStruct->mainCounter); + + LL_Dbgtrc_Counter_Start(id, StopWatch_InitStruct->startCounter); + LL_Dbgtrc_Counter_Start(id, StopWatch_InitStruct->stopCounter); + + return 0; +} + +/** Tracers support. Only build if hardware is available + */ +#ifdef ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS +#if ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS(0) > 0 +/** + * @brief Initializes a Tracer Unit + * @param id Debug and Trace Unit ID to configure + * @param tracer Tracer ID to configure [0..ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS-1] + * @param Tracer_InitStruct Tracer initialization structure + */ +int LL_Dbgtrc_Tracer_Init(int id, int tracer, LL_Dbgtrc_Tracer_InitTypedef *Tracer_InitStruct) +{ + /* Enable associated Trigger unit */ + LL_Dbgtrc_Trigger_Init(id, tracer, &(Tracer_InitStruct->triggerconf)); + + /* Configure Tracer unit. Use LL_Dbgtrc_Tracer_Start to start it */ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_TRACE_CTRL_ADDR(id, tracer)); + uint32_t t = *reg; + t = ATON_DEBUG_TRACE_TRACE_CTRL_SET_USER_TOKEN(t, Tracer_InitStruct->token); + t = ATON_DEBUG_TRACE_TRACE_CTRL_SET_VERBOSITY(t, Tracer_InitStruct->verbosity); + *reg = t; + + return 0; +} + +/** + * @brief Starts a Tracer Unit + * @param id Target Debug and Trace Unit ID + * @param tracer Tracer ID to start [0..ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS-1] + */ +int LL_Dbgtrc_Tracer_Start(int id, int tracer) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_TRACE_CTRL_ADDR(id, tracer)); + uint32_t t = *reg; + t = ATON_DEBUG_TRACE_TRACE_CTRL_SET_EN(t, 1); + *reg = t; + + return 0; +} + +/** + * @brief Stops a Tracer Unit + * @param id Target Debug and Trace Unit ID + * @param tracer Tracer ID to stop [0..ATON_DEBUG_TRACE_DEBUG_TRACE_N_TRACERS-1] + */ +int LL_Dbgtrc_Tracer_Stop(int id, int tracer) +{ + volatile uint32_t *reg = (volatile uint32_t *)(ATON_DEBUG_TRACE_TRACE_CTRL_ADDR(id, tracer)); + uint32_t t = *reg; + t = ATON_DEBUG_TRACE_TRACE_CTRL_SET_EN(t, 0); + *reg = t; + + return 0; +} + +/** + * @brief Enables Tracers Watchdog packet emission + * @param id Target Debug and Trace Unit ID + * @param period Watchdog period in clock cycles + */ +int LL_Dbgtrc_Tracer_Enable_Watchdog(int id, unsigned int period) +{ + uint32_t t = ATON_DEBUG_TRACE_WATCHDOG_DT; + t = ATON_DEBUG_TRACE_WATCHDOG_SET_PERIOD(t, period); + t = ATON_DEBUG_TRACE_WATCHDOG_SET_EN(t, 1); + ATON_DEBUG_TRACE_WATCHDOG_SET(id, t); + + return 0; +} + +/** + * @brief DisablesTracers Watchdog packet emission + * @param id Target Debug and Trace Unit ID + */ +int LL_Dbgtrc_Tracer_Disable_Watchdog(int id) +{ + uint32_t t = ATON_DEBUG_TRACE_WATCHDOG_GET(id); + t = ATON_DEBUG_TRACE_WATCHDOG_SET_EN(t, 0); + ATON_DEBUG_TRACE_WATCHDOG_SET(id, t); + + return 0; +} + +/** + * @brief Selects the Stream Engine in charge of emitting Tracers packets + * @param id Debug and Trace Unit ID to configure + * @param streng The Stream Engin ID to be used. Make sure it's not already used! + * @param stream_addr Start address for trace emission + * @param n Max trace emission length + */ +int LL_Dbgtrc_Tracer_Bind(int id, int streng, uint8_t *stream_addr, size_t n) +{ + LL_Streng_TensorInitTypeDef dma_out = { + .dir = 1, + .addr_base = {stream_addr}, + .offset_start = 0, + .offset_end = n, + .raw = 1, + .frame_count = 0, + .fwidth = 0, + .fheight = 0, + .batch_depth = 0, + .batch_offset = 0, + .frame_offset = n, + .line_offset = 0, + .loop_offset = 0, + .frame_loop_cnt = 0, + .frame_tot_cnt = 1, + .nbits_in = 24, + .nbits_out = 24, + .nbits_unsigned = 0, + .align_right = 0, + .noblk = 0, + }; + + /* Connect Debug and Trace Unit to stream engine */ + const LL_Switch_InitTypeDef switch_init = {LL_Switch_Init_Dest() = + __atonn_getDstPortID(STRSWITCH, 0, STRENG, streng, 0), + LL_Switch_Init_Source(0) = ATONN_SRCPORT(STRSWITCH, 0, DEBUG_TRACE, 0, 0), + LL_Switch_Init_Context(0) = 1, LL_Switch_Init_Frames(0) = 0}; + + LL_Switch_Init(&switch_init, 1); + + /* Configure and start target stream engine */ + const LL_ATON_EnableUnits_InitTypeDef dma_unit = {{STRENG, streng}}; + LL_Streng_TensorInit(streng, &dma_out, 1); + LL_ATON_EnableUnits_Init(&dma_unit, 1); + + return 0; +} +#endif +#endif + +/* Examples */ + +/** + * @brief Counts the number of interrupts triggered by a given unit + * @param counter The Counter ID to be used [0..15] + * @param unitirq The interrupt ID of the observed unit, e.g.: ATON_STRENG2_INT + * @note Use LL_Dbgtrc_Counter_Read(0, counter) to retrieve the number of interrupts + */ +int LL_Dbgtrc_Count_IRQs(unsigned int counter, unsigned int unitirq) +{ + LL_Dbgtrc_Counter_InitTypdef dbgtrc_init = { + .signal = DBGTRC_INTCTRL_SIGNALS + unitirq, + .evt_type = DBGTRC_EVT_POSEDGE, + }; + + LL_Dbgtrc_Init(0); + LL_Dbgtrc_Counter_Init(0, counter, &dbgtrc_init); + LL_Dbgtrc_Counter_Start(0, counter); + + return 0; +} + +/** + * @brief Computes the duration of an epoch + * @param counter The Counter ID to be used [0..15] + * @param istreng The ID of the input stream engine triggering the start of epoch + * First rising edge of OSTRX_HENV signal marks the start of the epoch. + * @param ostreng The ID of the output stream engine triggering the end of epoch + * Output stream engine interrupt rising edge marks the end of the epoch + * @note Use LL_Dbgtrc_Counter_Read(0, counter) to retrieve the number of cycles the epoch lasted + * @note Uses counter+1 and counter+2 as start/stop event sources + * @note Uses input stream engine HENV signal to trigger counter start. + * Uses output stream engine interrupt to trigger counter stop + */ +int LL_Dbgtrc_Count_Epoch_Len(unsigned int counter, unsigned int istreng, unsigned int ostreng) +{ + LL_Dbgtrc_StopWatch_InitTypdef stopwatch_init = { + .mainCounter = counter, + .startCounter = counter + 1, + .startSignal = DBGTRC_SWITCH_OSTRX_HENV + ATON_STRSWITCH_0_LINK_STRENG_0_0 + istreng, + .startEvent = DBGTRC_EVT_POSEDGE, + .stopCounter = counter + 2, + .stopSignal = DBGTRC_INTCTRL_SIGNALS + ATON_STRENG_INT(0) + ostreng, + .stopEvent = DBGTRC_EVT_POSEDGE, + }; + + LL_Dbgtrc_Init(0); + LL_Dbgtrc_Counter_StopWatch(0, &stopwatch_init); + + return 0; +} + +/** @defgroup Stream Engines' Stall signals monitoring + * @{ + */ + +/** + * @brief Counts the number cycles a given Stream Switch stall signal is hi or low + * @param counter The counter to be used + * @param iostall If non-zero count the ISTALL events. If zero count the OSTALL events + * @param signal The signal to be monitored. E.g.: GET_STRSWTCH_DEST(ATON_STRSWITCH_DSTSTRENG0_OFFSET) for ISTALL or + * ATON_LINK_STRENG0 for OSTALL + * @param Set to 1 to count when the stall signal is hi. Set to 0 to count when the signal is low + * @note If a unit is idle, its stall signal is high + */ +int LL_Dbgtrc_Count_Stalls(unsigned int counter, unsigned char iostall, unsigned int signal, unsigned int hilow) +{ + signal += (iostall ? SWITCH_ISTRX_STALL : SWITCH_OSTRX_STALL); + unsigned int event_type = hilow ? DBGTRC_EVT_HI : DBGTRC_EVT_LOW; + + LL_Dbgtrc_Counter_InitTypdef dbgtrc_init = { + .signal = signal, + .evt_type = event_type, + }; + + LL_Dbgtrc_Init(0); + LL_Dbgtrc_Counter_Init(0, counter, &dbgtrc_init); + LL_Dbgtrc_Counter_Start(0, counter); + + return 0; +} + +/** + * @brief Configures a group of counters to measure the number of cycles a given set of stream engines are active (i.e.: + * not stalled) during an epoch execution + * @param istreng the input stream engine mask + * @param ostreng the output stream engine mask + * @param counter The Debug and Trace counter ID to start with + * @retval Number of counters used. Negative error code otherwise + * @note This function is meant to be called from Epoch PRE START callback + * @note To be used in conjunction with LL_Dbgtrc_Count_StrengActive_Start/Stop() + */ +int LL_Dbgtrc_Count_StrengActive_Config(uint32_t istreng, uint32_t ostreng, unsigned int counter) +{ + int i; + int ncounters = 0; + LL_Dbgtrc_Counter_InitTypdef counter_init = {0}; + + counter_init.evt_type = DBGTRC_EVT_LOW; + counter_init.wrap = 0; + counter_init.countdown = 0; + counter_init.int_disable = 1; + counter_init.counter = 0; + + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if (istreng & (1 << i)) + { + counter_init.signal = SWITCH_OSTRX_STALL + 0 + i; + LL_Dbgtrc_Counter_Init(0, counter, &counter_init); + counter++; + ncounters++; + } + + if (ostreng & (1 << i)) + { + counter_init.signal = SWITCH_ISTRX_STALL + 0 + i; + LL_Dbgtrc_Counter_Init(0, counter, &counter_init); + counter++; + ncounters++; + } + } + + return ncounters; +} + +/** + * @brief Starts a set of counters configured with LL_Dbgtrc_Count_StrengActive_Config + * @param istreng the input stream engine mask + * @param ostreng the output stream engine mask + * @param counter The Debug and Trace counter ID to start with + * @retval Zero if ok, error code otherwise + * @note This function is meant to be called from Epoch Start callback + * @note To be used in conjunction with LL_Dbgtrc_Count_StrengActive_Stop() + */ +int LL_Dbgtrc_Count_StrengActive_Start(uint32_t istreng, uint32_t ostreng, unsigned int counter) +{ + int i; + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if ((istreng | ostreng) & (1 << i)) + LL_Dbgtrc_Counter_Start(0, counter++); + } + + return 0; +} + +/** + * @brief Stops the counters being started with LL_Dbgtrc_Count_StrengActive_Start + * @param istreng the input stream engine mask + * @param ostreng the output stream engine mask + * @param counter The Debug and Trace counter ID to start with + * @retval Zero if ok, error code otherwise + * @note This function is meant to be called from Epoch Stop callback + * @note To be used in conjunction with LL_Dbgtrc_Count_StrengActive_Config/Start() + */ +int LL_Dbgtrc_Count_StrengActive_Stop(uint32_t istreng, uint32_t ostreng, unsigned int counter) +{ + int i; + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if ((istreng | ostreng) & (1 << i)) + LL_Dbgtrc_Counter_Stop(0, counter++); + } + + return 0; +} + +/** + * @brief Prints statistics on stream engine's active periods + * @param istreng the input stream engine mask + * @param ostreng the output stream engine mask + * @param counter The Debug and Trace counter ID to start with + * @retval Zero if ok, error code otherwise + * @note To be used in conjunction with LL_Dbgtrc_Count_StrengActive_Config/Start/Stop() + */ +int LL_Dbgtrc_Count_StrengActive_Print(uint32_t istreng, uint32_t ostreng, unsigned int counter) +{ + int i; + + LL_ATON_PRINTF("STRENG active: "); + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if ((istreng | ostreng) & (1 << i)) + LL_ATON_PRINTF("%" PRIu32 " ", LL_Dbgtrc_Counter_Read(0, counter++)); + } + LL_ATON_PRINTF("\n"); + + return 0; +} + +/** + * @brief Returns the biggest value of the counters configured and started with + * LL_Dbgtrc_Count_StrengActive_Config/Start() + * @param istreng the input stream engine mask + * @param ostreng the output stream engine mask + * @param counter The Debug and Trace counter ID to start with + * @param argmax The ID of Stream Engine with the max active time + * @retval The value of bigger counter + * @note This function is meant to be called from Epoch Stop callback + * @note To be used in conjunction with LL_Dbgtrc_Count_StrengActive_Start/Stop() + */ +unsigned int LL_Dbgtrc_Count_StrengActive_GetMAX(uint32_t istreng, uint32_t ostreng, unsigned int counter, + unsigned int *argmax) +{ + int i; + unsigned int maxcount = 0; + + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if ((istreng | ostreng) & (1 << i)) + { + if (LL_Dbgtrc_Counter_Read(0, counter) > maxcount) + { + maxcount = LL_Dbgtrc_Counter_Read(0, counter); + *argmax = i; + } + counter++; + } + } + + return maxcount; +} + +/** + * @} + */ + +/** @defgroup HENV counters + * oHENV signal is high when the corresponding link is transferring data so it can be used to measure link activity + * of the input stream engines (i.e.: reading data) and check whether there are bootlenecks in reading from memory. + * @{ + */ + +/** + * @brief Configures a group of counters to measure the number of cycles a given set of input stream engines have HENV + * signal high + * @param istreng the input stream engine mask + * @param counter The Debug and Trace counter ID to start with + * @retval Number of counters used. Negative error code otherwise + * @note This function is meant to be called from Epoch PRE START callback + * @note To be used in conjunction with LL_Dbgtrc_Count_StrengHENV_Start/Stop/Print() + */ +int LL_Dbgtrc_Count_StrengHENV_Config(uint32_t istreng, unsigned int counter) +{ + int i; + int ncounters = 0; + LL_Dbgtrc_Counter_InitTypdef counter_init = {0}; + + counter_init.evt_type = DBGTRC_EVT_HI; + counter_init.wrap = 0; + counter_init.countdown = 0; + counter_init.int_disable = 1; + counter_init.counter = 0; + + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if (istreng & (1 << i)) + { + counter_init.signal = DBGTRC_SWITCH_OSTRX_HENV + ATON_STRSWITCH_0_LINK_STRENG_0_0 + i; + LL_Dbgtrc_Counter_Init(0, counter, &counter_init); + counter++; + ncounters++; + } + } + + return ncounters; +} + +/** + * @brief Starts the counters previously configured with LL_Dbgtrc_Count_StrengHENV_Config + * @param istreng the input stream engine mask + * @param counter The Debug and Trace counter ID to start with + */ +int LL_Dbgtrc_Count_StrengHENV_Start(uint32_t istreng, unsigned int counter) +{ + int i; + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if (istreng & (1 << i)) + LL_Dbgtrc_Counter_Start(0, counter++); + } + + return 0; +} + +/** + * @brief Stops the counters previously started with LL_Dbgtrc_Count_StrengHENV_Start + * @param istreng the input stream engine mask + * @param counter The Debug and Trace counter ID to start with + */ +int LL_Dbgtrc_Count_StrengHENV_Stop(uint32_t istreng, unsigned int counter) +{ + int i; + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if (istreng & (1 << i)) + LL_Dbgtrc_Counter_Start(0, counter++); + } + + return 0; +} + +/** + * @brief Prints the contents of the counters configured with LL_Dbgtrc_Count_StrengHENV_Config + * @param istreng the input stream engine mask + * @param counter The Debug and Trace counter ID to start with + */ +int LL_Dbgtrc_Count_StrengHENV_Print(uint32_t istreng, unsigned int counter) +{ + int i; + + LL_ATON_PRINTF("STRENG HENV: "); + for (i = 0; i < ATON_STRENG_NUM; i++) + { + if (istreng & (1 << i)) + LL_ATON_PRINTF("%" PRIu32 " ", LL_Dbgtrc_Counter_Read(0, counter++)); + } + LL_ATON_PRINTF("\n"); + + return 0; +} + +/** + * @} + */ + +/** @defgroup Burst Length counters + * @{ + */ + +/** + * @brief Counts the burst lenghts on a given Bus Interface + * @param counter The counter ID to start from. Four counters are used: counter, counter+1, counter+2, counter+3 + * @param busif The Bus Interface to monitor + * @param readwrite If non-zero count the Read burst lengths. If zero, count the Write burst lenghts + * @note Uses four counters starting from 'counter' to count four possible burst lenghts [1, 2, 4, 8] + */ +int LL_Dbgtrc_Count_BurstsLen(unsigned int counter, unsigned char busif, unsigned char readwrite) +{ + unsigned int signal = readwrite ? BUS_INTERFACE_READ1X8B : BUS_INTERFACE_WRITE1X8B; + int i; + + signal += busif; + + LL_Dbgtrc_Counter_InitTypdef dbgtrc_init = { + .evt_type = DBGTRC_EVT_HI, + }; + + LL_Dbgtrc_Init(0); + + for (i = 0; i < 4; i++) + { + dbgtrc_init.signal = signal + 2 * i; + LL_Dbgtrc_Counter_Init(0, counter + i, &dbgtrc_init); + LL_Dbgtrc_Counter_Start(0, counter + i); + } + + return 0; +} + +/** + * @brief Initialize and start counters to analyze Write and Read accesses on both Bus Interfaces + * @param counter_id The counter to start from. Uses 16 counters starting from 'counter_id' + */ +int LL_Dbgtrc_BurstLenBenchStart(unsigned int counter_id) +{ + LL_Dbgtrc_Count_BurstsLen(counter_id, 0, 0); /* Busif 0 writes */ + LL_Dbgtrc_Count_BurstsLen(counter_id + 4, 0, 1); /* Busif 0 reads */ + LL_Dbgtrc_Count_BurstsLen(counter_id + 8, 1, 0); /* Busif 1 writes */ + LL_Dbgtrc_Count_BurstsLen(counter_id + 12, 1, 1); /* Busif 1 reads */ + + return 0; +} + +/** + * @brief Retrieves the Burst Length counters from Debug and Trace Unit and stores them in a given array + * @param counter_id The counter ID to start from + * @param counters Pointer to the buffer where to store the counter values. Must be at least 16 elements + */ +int LL_Dbgtrc_BurstLenGet(unsigned int counter_id, unsigned int *counters) +{ + int i; + + for (i = 0; i < 16; i++) + counters[i] = LL_Dbgtrc_Counter_Read(0, counter_id + i); + + return 0; +} + +/** + * @brief Computes the total amount of written and read bytes transited on both Bus Interfaces + * @param counter_id The counter ID to start from + * @param totalWrites [OUT] Holds the total number of written bytes + * @param totalReads [OUT] Holds the total number of read bytes + * @note + */ +int LL_Dbgtrc_GetTotalTranfers(unsigned int counter_id, unsigned int *totalWrites, unsigned int *totalReads) +{ + int i; + *totalWrites = *totalReads = 0; + unsigned int counters[16]; + + LL_Dbgtrc_BurstLenGet(counter_id, counters); + + /* Compute total writes. AWLEN is one of 0, 1, 3, 7 */ + for (i = 0; i < 4; i++) + { + *totalWrites += (1 << i) * counters[i]; + *totalWrites += (1 << i) * counters[8 + i]; + } + + /* AWSIZE is always 3 (8 byte beats) */ + *totalWrites <<= 3; + + /* Same for reads */ + for (i = 0; i < 4; i++) + { + *totalReads += (1 << i) * counters[4 + i]; + *totalReads += (1 << i) * counters[12 + i]; + } + + *totalReads <<= 3; + + return 0; +} + +/** + * @brief Prints to standard output Burst Length statistics + * @param counter_id The counter to start from + */ +int LL_Dbgtrc_LogTransfers(unsigned int counter_id) +{ + unsigned int counters[16]; + unsigned int totalReads, totalWrites; + + LL_Dbgtrc_BurstLenGet(counter_id, counters); + + LL_ATON_PRINTF("\n"); + LL_ATON_PRINTF("------------------------------------------\n"); + LL_ATON_PRINTF("BURSTLEN 1 2 4 8\n"); + LL_ATON_PRINTF("------------------------------------------\n"); + LL_ATON_PRINTF("BUSIF0 Writes %6u %6u %6u %6u\n", counters[0], counters[1], counters[2], counters[3]); + LL_ATON_PRINTF("BUSIF0 Reads %6u %6u %6u %6u\n", counters[4], counters[5], counters[6], counters[7]); + LL_ATON_PRINTF("BUSIF1 Writes %6u %6u %6u %6u\n", counters[8], counters[9], counters[10], counters[11]); + LL_ATON_PRINTF("BUSIF1 Reads %6u %6u %6u %6u\n", counters[12], counters[13], counters[14], counters[15]); + LL_ATON_PRINTF("------------------------------------------\n"); + + LL_Dbgtrc_GetTotalTranfers(counter_id, &totalWrites, &totalReads); + + LL_ATON_PRINTF("Total Writes: %u bytes\n", totalWrites); + LL_ATON_PRINTF("Total Reads : %u bytes\n", totalReads); + + return 0; +} + +/** + * @brief Prints to standard output Burst Length statistics per epoch + * @param counter_id The counter to start from + * @param counters The counters accumulated by some other means + * @param first =0 prints header, =1 prints counters values, =2 prints footers + */ +int LL_Dbgtrc_LogTransfers_epoch(unsigned int counter_id, unsigned int *counters, int first) +{ + unsigned int totalReads, totalWrites; + + if (first == 0) + { + LL_ATON_PUTS(""); + LL_ATON_PRINTF( + "-----------------------------------------------------------------------------------------------------------" + "----------------------\n"); + LL_ATON_PRINTF( + "BURSTLEN 1 2 4 8 | 1 2 4 8 | 1 2 4 8 | " + "1 2 4 8\n"); + LL_ATON_PRINTF( + " BUSIF0 Writes BUSIF0 Reads BUSIF1 Writes " + " BUSIF1 Reads\n"); + LL_ATON_PRINTF( + "-----------------------------------------------------------------------------------------------------------" + "----------------------\n"); + } + else if (first == 1) + { + LL_ATON_PRINTF(" %6u %6u %6u %6u ", counters[0], counters[1], counters[2], counters[3]); + LL_ATON_PRINTF("%6u %6u %6u %6u ", counters[4], counters[5], counters[6], counters[7]); + LL_ATON_PRINTF("%6u %6u %6u %6u ", counters[8], counters[9], counters[10], counters[11]); + LL_ATON_PRINTF("%6u %6u %6u %6u ", counters[12], counters[13], counters[14], counters[15]); + LL_ATON_PUTS(""); + } + else + { + LL_Dbgtrc_GetTotalTranfers(counter_id, &totalWrites, &totalReads); + + LL_ATON_PRINTF("\nTotal Writes: %u bytes\n", totalWrites); + LL_ATON_PRINTF("Total Reads : %u bytes\n", totalReads); + } + + return 0; +} + +/** + * @} + */ + +/** + * @brief Counts the external trigger signals occurences + * @param counter The counter to be used + * @param trigger The External Trigger signal to monitor [0..3] + */ +int LL_Dbgtrc_Count_ExtTrigger(unsigned int counter, unsigned char trigger) +{ + LL_Dbgtrc_Counter_InitTypdef dbgtrc_init = {.evt_type = DBGTRC_EVT_POSEDGE, .signal = EXT_TRIGGERS_SYNC + trigger}; + + LL_Dbgtrc_Init(0); + LL_Dbgtrc_Counter_Init(0, counter, &dbgtrc_init); + LL_Dbgtrc_Counter_Start(0, counter); + + return 0; +} + +/** + * @brief Example showing how to start/stop counters synchronously + * @note This is a workaroud for ATON RTL <= 1.6. Proper sync start/stop implemented later versions + */ +int LL_Dbgtrc_SynchronousCountersTest(void) +{ + int counter; + LL_Dbgtrc_Counter_InitTypdef dbgtrc_init = {.evt_type = DBGTRC_EVT_HI, .signal = DBGTRC_VDD}; + + LL_ATON_Init(); + LL_Dbgtrc_Init(0); + + /* Starts counters and stops them in reverse order. Shows counters scews + */ + for (counter = 0; counter < 8; counter++) + LL_Dbgtrc_Counter_Init(0, counter, &dbgtrc_init); + + for (counter = 0; counter < 8; counter++) + LL_Dbgtrc_Counter_Start(0, counter); + + /* Wait for counter to reach given value */ + while (LL_Dbgtrc_Counter_Read(0, 0) < 100000) + ; + + /* Stop counters in reverse order */ + for (counter = 8; counter > 0; counter--) + LL_Dbgtrc_Counter_Stop(0, counter); + + /* Check scews */ + for (counter = 0; counter < 8; counter++) + LL_ATON_PRINTF("Non synced counters: %u %" PRIu32 "\n", (unsigned)counter, LL_Dbgtrc_Counter_Read(0, counter)); + + /* Starts counters and stops them in reverse order. Gates clock to sync counters + */ + LL_Dbgtrc_Counter_InitTypdef noevt_init = {.evt_type = DBGTRC_EVT_HI, .signal = DBGTRC_GND}; + + /* Starts counter with no event */ + for (counter = 0; counter < 8; counter++) + { + LL_Dbgtrc_Counter_Init(0, counter, &noevt_init); + LL_Dbgtrc_Counter_Start(0, counter); + } + + /* Gate clock */ + LL_Dbgtrc_DisableClock(); + + /* Re-configure with event to monitor */ + for (counter = 0; counter < 8; counter++) + { + LL_Dbgtrc_Counter_Init(0, counter, &dbgtrc_init); + LL_Dbgtrc_Counter_Start(0, counter); + } + + /* Give clock */ + LL_Dbgtrc_EnableClock(); + + /* Wait for counter to reach given value */ + while (LL_Dbgtrc_Counter_Read(0, 0) < 100000) + ; + + LL_Dbgtrc_DisableClock(); + + /* Check scews */ + for (counter = 0; counter < 8; counter++) + LL_ATON_PRINTF("Synced counters: %u %" PRIu32 "\n", (unsigned)counter, LL_Dbgtrc_Counter_Read(0, counter)); + + return 0; +} + +#endif // ATON_DEBUG_TRACE_NUM diff --git a/lib/stai/libstai/ll_aton/ll_aton_debug.c b/lib/stai/libstai/ll_aton/ll_aton_debug.c new file mode 100644 index 000000000..fc0210144 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_debug.c @@ -0,0 +1,800 @@ +/** + ****************************************************************************** + * @file ll_aton_debug.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL library support for debugging (buffer dumpers, ...). + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined(DUMP_DEBUG_API) +#warning "deprecated use of DUMP_DEBUG_API (define LL_ATON_DUMP_DEBUG_API instead)" +#define LL_ATON_DUMP_DEBUG_API +#endif + +#if defined(LL_ATON_DUMP_DEBUG_API) + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ll_aton_util.h" // Leave blank line after the include + +#include "ll_aton_NN_interface.h" +#include "ll_aton_debug.h" + +LL_ATON_WEAK void *LL_ATON_physical_to_virtual(uintptr_t addr) +{ + return (void *)(uintptr_t)addr; +} + +static const LL_Buffer_InfoTypeDef *__get_buffer(const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) +{ + const LL_Buffer_InfoTypeDef *bufs = + (in == BUFF_IN ? nn_interface->input_buffers_info() + : (in == BUFF_OUT ? nn_interface->output_buffers_info() : nn_interface->internal_buffers_info())); + + while (bufs != NULL && bufs->name != NULL) + { + if (strcmp(bufs->name, bufname) == 0) + { + return bufs; + } + bufs++; + } + return NULL; +} + +static void __set_buffer(const LL_Buffer_InfoTypeDef *buf, unsigned val) +{ + uint32_t len = LL_Buffer_len(buf); + int t; + unsigned char *p = (unsigned char *)LL_Buffer_addr_start(buf); + for (t = 0; t < len; t++) + p[t] = (unsigned char)val; +} + +static void __set_all_buffers(const LL_Buffer_InfoTypeDef *bufs, unsigned val) +{ + while (bufs != NULL && bufs->name != NULL) + { + __set_buffer(bufs, val); + bufs++; + } +} + +#ifndef NDEBUG +static float Q_to_floating(int i, int Qm, int Qn) +{ + if (Qn >= 0) + return ((float)i / (float)((int)1 << Qn)); + if (Qn < 0) + return ((float)i * (float)((int)1 << -Qn)); + return 0.f; +} + +static void __dump_buffer_info(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + LL_ATON_PRINTF("dumping [%s] len = %d phy: %p\n", buf->name, (int)len, (void *)LL_Buffer_addr_start(buf)); + + LL_ATON_ASSERT(buf->ndims >= 3); + int32_t dim_b_c = buf->batch; + int32_t dim_c = buf->shape[buf->ndims - 1]; + dim_c = (dim_c == 0) ? 1 : dim_c; + LL_ATON_ASSERT(dim_b_c != 0); + int32_t num_batch = dim_c / dim_b_c; + + /* output onnx shape */ + LL_ATON_PRINTF(" name = %s, onnx shape(", buf->name); + int32_t channel_onnx_idx = buf->ndims - 3; + uint32_t i; + for (i = 0; i < channel_onnx_idx; i++) + { + int32_t tmp = (int32_t)buf->shape[i]; + tmp = (tmp == 0) ? 1 : tmp; + if (tmp > 1) + LL_ATON_PRINTF("%" PRId32 ",", tmp); + } + LL_ATON_PRINTF("%" PRId32 ",", dim_c); + for (; i < (buf->ndims - 1); i++) + { + int32_t tmp = (int32_t)buf->shape[i]; + tmp = (tmp == 0) ? 1 : tmp; + if (tmp > 1) + { + LL_ATON_PRINTF("%" PRId32, tmp); + if (i != (buf->ndims - 2)) + LL_ATON_PRINTF(","); + } + } + + /* output batch & num_batch */ + LL_ATON_PRINTF("), num_batch=%" PRId32 ", batch=%" PRId32 ", ", num_batch, dim_b_c); + + /* output memory layout */ + LL_ATON_PRINTF("memory layout("); + bool leading = true; + for (i = 0; i < channel_onnx_idx; i++) + { + int32_t tmp = (int32_t)buf->shape[i]; + tmp = (tmp == 0) ? 1 : tmp; + if (!leading || (tmp > 1)) + { + LL_ATON_PRINTF("%" PRId32 ",", tmp); + leading = false; + } + } + if (num_batch != 1) + { + LL_ATON_PRINTF("%" PRId32 ",", num_batch); + leading = false; + } + for (; i < (buf->ndims - 1); i++) + { + int32_t tmp = (int32_t)buf->shape[i]; + tmp = (tmp == 0) ? 1 : tmp; + if (!leading || (tmp > 1)) + { + leading = false; + LL_ATON_PRINTF("%" PRId32 "", tmp); + if (i != (buf->ndims - 2)) + LL_ATON_PRINTF(","); + } + } + if (dim_b_c > 1) + { + LL_ATON_PRINTF(",%" PRId32, dim_b_c); + } + + /* output format information */ + LL_ATON_PRINTF("), Qmn=(%d,%d,%s)", buf->Qm, buf->Qn, buf->Qunsigned ? "unsigned" : "signed"); + if (buf->scale != 0) + { + LL_ATON_PRINTF(", \"has scale"); + if (buf->offset != 0) + { + LL_ATON_PRINTF("/has offset\""); + } + else + { + LL_ATON_PRINTF("\""); + } + } + else + { // no scale + if (buf->offset != 0) + { + LL_ATON_PRINTF(", \"has offset\""); + } + } + + int is_scale_off = buf->scale != 0 || buf->offset != 0; + LL_ATON_PRINTF(" %s", is_scale_off ? (buf->per_channel ? "per channel" : "per tensor") : ""); + if (is_scale_off) + { + if (buf->per_channel == 0) + LL_ATON_PRINTF(" (%f, %d)", buf->scale[0], (int)buf->offset[0]); + else + { + for (uint32_t c = 0; c < dim_c; c++) + { + LL_ATON_PRINTF(" (%g, %d)", buf->scale[c], (int)buf->offset[c]); + if (c < (dim_c - 1)) + LL_ATON_PRINTF(","); + } + } + } + LL_ATON_PUTS(""); +} + +static void __dump_buffer_Qmn_8bit(const LL_Buffer_InfoTypeDef *buf) +{ + // uintptr_t len = LL_Buffer_len(buf); + LL_ATON_ASSERT(LL_Buffer_bits(buf) == 8); + + int32_t ndims = (int32_t)buf->ndims; + LL_ATON_ASSERT(ndims >= 4); + + int32_t dim_m = 1; + int32_t dim_h = (int32_t)buf->shape[(ndims - 4) + 1]; + int32_t dim_w = (int32_t)buf->shape[(ndims - 4) + 2]; + int32_t dim_c = (int32_t)buf->shape[(ndims - 4) + 3]; + + for (int32_t i = 0; i <= ndims - 4; i++) + { + uint32_t tmp = (int32_t)buf->shape[i]; + dim_m *= (tmp == 0 ? 1 : tmp); + } + + dim_m = dim_m == 0 ? 1 : dim_m; + dim_h = dim_h == 0 ? 1 : dim_h; + dim_w = dim_w == 0 ? 1 : dim_w; + dim_c = dim_c == 0 ? 1 : dim_c; + + int32_t Qm = buf->Qm; + + int32_t Qn = buf->Qn; + // int32_t Qsign = buf->Qunsigned == 1 ? 0 : 1; + + int32_t dim_b_c = buf->batch; + // int32_t num_batch = dim_c / dim_b_c; + + // int32_t dim_k_m = 1; // buf->kbatch; + // int32_t = dim_m / dim_k_m; + + LL_ATON_PRINTF("uint8 ["); + uint8_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int is_unsigned = buf->Qunsigned; + for (int32_t m = 0; m < dim_m; ++m) + { // M + if (m) + LL_ATON_PRINTF("\n"); + LL_ATON_PRINTF("["); + for (int32_t c = 0; c < dim_c; ++c) + { // C + if (c) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t h = 0; h < dim_h; ++h) + { // H + if (h) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("[ "); + for (int32_t w = 0; w < dim_w; ++w) + { // W + uint32_t off_orlando = /* m * dim_c * dim_h * dim_w + */ (c / dim_b_c) * dim_b_c * dim_h * dim_w + + h * dim_w * dim_b_c + w * dim_b_c + (c % dim_b_c); + int32_t data = p[off_orlando]; + data = is_unsigned ? data : (int8_t)(data); + if (Qn == 0) + LL_ATON_PRINTF("%-.0f. ", Q_to_floating(data, Qm, Qn)); + else + LL_ATON_PRINTF("%0.6f ", Q_to_floating(data, Qm, Qn)); + } + LL_ATON_PRINTF("]"); + } + LL_ATON_PRINTF("]"); + if (c < (dim_c - 1)) + LL_ATON_PRINTF("\n"); + } + LL_ATON_PRINTF("]\n"); + p += dim_c * dim_h * dim_w; + } + LL_ATON_PRINTF("]\n"); +} + +static void __dump_buffer_Qmn_16bit(const LL_Buffer_InfoTypeDef *buf) +{ + // uintptr_t len = LL_Buffer_len(buf); + LL_ATON_ASSERT(LL_Buffer_bits(buf) == 16); + + int32_t ndims = (int32_t)buf->ndims; + LL_ATON_ASSERT(ndims >= 4); + + int32_t dim_m = 1; + int32_t dim_h = (int32_t)buf->shape[(ndims - 4) + 1]; + int32_t dim_w = (int32_t)buf->shape[(ndims - 4) + 2]; + int32_t dim_c = (int32_t)buf->shape[(ndims - 4) + 3]; + + for (int32_t i = 0; i <= ndims - 4; i++) + { + uint32_t tmp = (int32_t)buf->shape[i]; + dim_m *= (tmp == 0 ? 1 : tmp); + } + + LL_ATON_PRINTF("dim_m=%" PRId32 " off=%" PRId32, dim_m, dim_c * dim_h * dim_w); + + int32_t Qm = buf->Qm; + int32_t Qn = buf->Qn; + // int32_t Qsign = buf->Qunsigned == 1 ? 0 : 1; + + int32_t dim_b_c = buf->batch; + // int32_t num_batch = dim_c / dim_b_c; + + // int32_t dim_k_m = 1; // buf->kbatch; + // int32_t = dim_m / dim_k_m; + + LL_ATON_PRINTF("uint16 ["); + uint16_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int is_unsigned = buf->Qunsigned; + for (int32_t m = 0; m < dim_m; ++m) + { // M + if (m) + LL_ATON_PRINTF("\n"); + LL_ATON_PRINTF("["); + for (int32_t c = 0; c < dim_c; ++c) + { // C + if (c) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t h = 0; h < dim_h; ++h) + { // H + if (h) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t w = 0; w < dim_w; ++w) + { // W + uint32_t off_orlando = /* m * dim_c * dim_h * dim_w +*/ (c / dim_b_c) * dim_b_c * dim_h * dim_w + + h * dim_w * dim_b_c + w * dim_b_c + (c % dim_b_c); + // LL_ATON_PRINTF("m=%d c=%d c/dim_b_c=%d h=%d w=%d c %% dim_b_c=%d off=%d\n",m,c,c/dim_b_c, h,w,c % + // dim_b_c,off_orlando); + int32_t data = p[off_orlando]; + data = is_unsigned ? data : (int16_t)(data); +#if 0 + if (Qn == 0) + LL_ATON_PRINTF("%-.0f. ", Q_to_floating(data, Qm, Qn)); + else +#endif + if (data == ((1 << (Qm)) - 1)) + LL_ATON_PRINTF("+sat "); + else if (data == -(1 << (Qm))) + LL_ATON_PRINTF("-sat "); + else if (Qn == 0) + LL_ATON_PRINTF("%-.0f ", Q_to_floating(data, Qm, Qn)); + else + LL_ATON_PRINTF("%0.6f ", Q_to_floating(data, Qm, Qn)); + } + LL_ATON_PRINTF("]"); + } + LL_ATON_PRINTF("]"); + if (c < (dim_c - 1)) + LL_ATON_PRINTF("\n"); + } + LL_ATON_PRINTF("]\n"); + p += dim_c * dim_h * dim_w; + } + LL_ATON_PRINTF("]\n"); +} + +static void __dump_buffer_Qmn_32bit(const LL_Buffer_InfoTypeDef *buf) +{ + // uintptr_t len = LL_Buffer_len(buf); + LL_ATON_ASSERT(LL_Buffer_bits(buf) == 32); + + int32_t ndims = (int32_t)buf->ndims; + LL_ATON_ASSERT(ndims >= 4); + + int32_t dim_m = 1; + int32_t dim_h = (int32_t)buf->shape[(ndims - 4) + 1]; + int32_t dim_w = (int32_t)buf->shape[(ndims - 4) + 2]; + int32_t dim_c = (int32_t)buf->shape[(ndims - 4) + 3]; + + for (int32_t i = 0; i <= ndims - 4; i++) + { + uint32_t tmp = (int32_t)buf->shape[i]; + dim_m *= (tmp == 0 ? 1 : tmp); + } + + LL_ATON_PRINTF("dim_m=%" PRId32 " off=%" PRId32, dim_m, dim_c * dim_h * dim_w); + + int32_t Qm = buf->Qm; + int32_t Qn = buf->Qn; + // int32_t Qsign = buf->Qunsigned == 1 ? 0 : 1; + + int32_t dim_b_c = buf->batch; + + // int32_t num_batch = dim_c / dim_b_c; + + // int32_t dim_k_m = 1; // buf->kbatch; + // int32_t = dim_m / dim_k_m; + + LL_ATON_PRINTF("int32 ["); + int32_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + for (int32_t m = 0; m < dim_m; ++m) + { // M + if (m) + LL_ATON_PRINTF("\n"); + LL_ATON_PRINTF("["); + for (int32_t c = 0; c < dim_c; ++c) + { // C + if (c) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t h = 0; h < dim_h; ++h) + { // H + if (h) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t w = 0; w < dim_w; ++w) + { // W + uint32_t off_orlando = /* m * dim_c * dim_h * dim_w +*/ (c / dim_b_c) * dim_b_c * dim_h * dim_w + + h * dim_w * dim_b_c + w * dim_b_c + (c % dim_b_c); + // LL_ATON_PRINTF("m=%d c=%d c/dim_b_c=%d h=%d w=%d c %% dim_b_c=%d off=%d\n",m,c,c/dim_b_c, h,w,c % + // dim_b_c,off_orlando); + int32_t data = p[off_orlando]; + + if (Qn == 0) + LL_ATON_PRINTF("%-.0f. ", Q_to_floating(data, Qm, Qn)); + else + LL_ATON_PRINTF("%0.6f ", Q_to_floating(data, Qm, Qn)); + } + LL_ATON_PRINTF("]"); + } + LL_ATON_PRINTF("]"); + if (c < (dim_c - 1)) + LL_ATON_PRINTF("\n"); + } + LL_ATON_PRINTF("]\n"); + p += dim_c * dim_h * dim_w; + } + LL_ATON_PRINTF("]\n"); +} + +static void __dump_buffer_float(const LL_Buffer_InfoTypeDef *buf) +{ + LL_ATON_ASSERT(buf->type == DataType_FLOAT); + + int32_t ndims = (int32_t)buf->ndims; + LL_ATON_ASSERT(ndims >= 4); + + int32_t dim_m = 1; + int32_t dim_h = (int32_t)buf->shape[(ndims - 4) + 1]; + int32_t dim_w = (int32_t)buf->shape[(ndims - 4) + 2]; + int32_t dim_c = (int32_t)buf->shape[(ndims - 4) + 3]; + + for (int32_t i = 0; i <= ndims - 4; i++) + { + uint32_t tmp = (int32_t)buf->shape[i]; + dim_m *= (tmp == 0 ? 1 : tmp); + } + + dim_m = dim_m == 0 ? 1 : dim_m; + dim_h = dim_h == 0 ? 1 : dim_h; + dim_w = dim_w == 0 ? 1 : dim_w; + dim_c = dim_c == 0 ? 1 : dim_c; + + int32_t dim_b_c = buf->batch; + + LL_ATON_PRINTF("["); + float *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + for (int32_t m = 0; m < dim_m; ++m) + { // M + if (m) + LL_ATON_PRINTF("\n"); + LL_ATON_PRINTF("["); + for (int32_t c = 0; c < dim_c; ++c) + { // C + if (c) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t h = 0; h < dim_h; ++h) + { // H + if (h) + LL_ATON_PRINTF("\n "); + LL_ATON_PRINTF("["); + for (int32_t w = 0; w < dim_w; ++w) + { // W + uint32_t off_orlando = /* m * dim_c * dim_h * dim_w +*/ (c / dim_b_c) * dim_b_c * dim_h * dim_w + + h * dim_w * dim_b_c + w * dim_b_c + (c % dim_b_c); + float data = p[off_orlando]; + LL_ATON_PRINTF("%f. ", data); + } + LL_ATON_PRINTF("]"); + } + LL_ATON_PRINTF("]"); + if (c < (dim_c - 1)) + LL_ATON_PRINTF("\n"); + } + LL_ATON_PRINTF("]\n"); + p += dim_c * dim_h * dim_w; + } + LL_ATON_PRINTF("]\n"); +} + +static void __dump_buffer_raw_Qmn_8bit(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + LL_ATON_ASSERT(LL_Buffer_bits(buf) == 8); + int32_t Qm = buf->Qm; + int32_t Qn = buf->Qn; + // int32_t Qsign = buf->Qunsigned == 1 ? 0 : 1; + const char *pformat = (Qn == 0) ? "%-.0f. " : "%0.3f "; + + uint8_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int is_unsigned = buf->Qunsigned; + int cont = 0; + for (unsigned i = 0; i < len; i++) + { + int32_t data = p[i]; + data = is_unsigned ? data : (int8_t)(data); + LL_ATON_PRINTF(pformat, Q_to_floating(data, Qm, Qn)); + if (cont++ == 30) + { + cont = 0; + LL_ATON_PUTS(""); + } + } + LL_ATON_PRINTF("\n"); +} + +static void __dump_buffer_raw_Qmn_16bit(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + LL_ATON_ASSERT(LL_Buffer_bits(buf) == 16); + int32_t Qm = buf->Qm; + int32_t Qn = buf->Qn; + // int32_t Qsign = buf->Qunsigned == 1 ? 0 : 1; + const char *pformat = (Qn == 0) ? "%-.0f. " : "%0.3g "; + + uint16_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int is_unsigned = buf->Qunsigned; + int cont = 0; + for (unsigned i = 0; i < len / 2; i++) + { + int32_t data = p[i]; + data = is_unsigned ? data : (int16_t)(data); + LL_ATON_PRINTF(pformat, Q_to_floating(data, Qm, Qn)); + if (cont++ == 30) + { + cont = 0; + LL_ATON_PUTS(""); + } + } + LL_ATON_PRINTF("\n"); +} + +static void __dump_buffer_raw_Qmn_32bit(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + LL_ATON_ASSERT(LL_Buffer_bits(buf) == 32); + + int32_t Qm = buf->Qm; + int32_t Qn = buf->Qn; + // int32_t Qsign = buf->Qunsigned == 1 ? 0 : 1; + const char *pformat = (Qn == 0) ? "%-.0f. " : "%0.3g "; + + int32_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int cont = 0; + for (unsigned i = 0; i < len / 4; i++) + { + int32_t data = p[i]; + LL_ATON_PRINTF(pformat, Q_to_floating(data, Qm, Qn)); + if (cont++ == 30) + { + cont = 0; + LL_ATON_PUTS(""); + } + } + LL_ATON_PRINTF("\n"); +} + +static void __dump_buffer_raw_16bit(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + uint16_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int is_unsigned = buf->Qunsigned; + + int cont = 0; + for (unsigned i = 0; i < len / 2; i++) + { + int32_t data = p[i]; + data = is_unsigned ? data : (int16_t)(data); + LL_ATON_PRINTF("%" PRId32 " ", data); + if (cont++ == 30) + { + cont = 0; + LL_ATON_PUTS(""); + } + } + LL_ATON_PRINTF("\n"); +} + +static void __dump_buffer_raw_32bit(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + uint32_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + + int cont = 0; + int is_unsigned = buf->Qunsigned; + for (unsigned i = 0; i < len / 4; i++) + { + uint32_t data = p[i]; + if (is_unsigned) + LL_ATON_PRINTF("%" PRIu32 " ", data); + else + LL_ATON_PRINTF("%" PRId32 " ", (int32_t)data); + if (cont++ == 30) + { + cont = 0; + LL_ATON_PUTS(""); + } + } + LL_ATON_PRINTF("\n"); +} + +static void __dump_buffer_raw_8bit(const LL_Buffer_InfoTypeDef *buf) +{ + uintptr_t len = LL_Buffer_len(buf); + uint8_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + int cont = 0; + int is_unsigned = buf->Qunsigned; + for (unsigned i = 0; i < len; i++) + { + int32_t data = p[i]; + data = is_unsigned ? data : (int8_t)(data); + LL_ATON_PRINTF("%" PRId32 " ", data); + if (cont++ == 30) + { + cont = 0; + LL_ATON_PUTS(""); + } + } + LL_ATON_PRINTF("\n"); +} + +static void __dump_buffer(int mode, const LL_Buffer_InfoTypeDef *buf) +{ + if (buf != NULL) + { + __dump_buffer_info(buf); + switch (mode) + { + case MODE_RAW_INBITS: + if (LL_Buffer_bits(buf) == 8) + { + __dump_buffer_raw_8bit(buf); + break; + } + if (LL_Buffer_bits(buf) == 16) + { + __dump_buffer_raw_16bit(buf); + break; + } + if (LL_Buffer_bits(buf) == 32) + { + __dump_buffer_raw_32bit(buf); + break; + } + // intentional fall-thru + case MODE_RAW_INFLOAT: + if (buf->type == DataType_FLOAT) + { + for (float *lfd = (float *)LL_Buffer_addr_start(buf); lfd < (float *)LL_Buffer_addr_end(buf); lfd++) + { + LL_ATON_PRINTF("%f\n", *lfd); + } + +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif + return; + } + if (LL_Buffer_bits(buf) == 8) + __dump_buffer_raw_Qmn_8bit(buf); + if (LL_Buffer_bits(buf) == 16) + __dump_buffer_raw_Qmn_16bit(buf); + if (LL_Buffer_bits(buf) == 32) + __dump_buffer_raw_Qmn_32bit(buf); + break; + case MODE_ONNX_INFLOAT: + switch (buf->type) + { + case DataType_FLOAT: + __dump_buffer_float(buf); + break; + default: + if (LL_Buffer_bits(buf) == 8) + __dump_buffer_Qmn_8bit(buf); + if (LL_Buffer_bits(buf) == 16) + __dump_buffer_Qmn_16bit(buf); + if (LL_Buffer_bits(buf) == 32) + __dump_buffer_Qmn_32bit(buf); + break; + } + break; + default: + LL_ATON_PRINTF("Buffer Dump ignored: unrecognized dump mode\n"); + break; + } + } +} + +static void __dump_epoch_buffers(const LL_Buffer_InfoTypeDef *bufs, int mode, int epoch) +{ + while (bufs != NULL && bufs[0].name != NULL) + { + if (epoch == -1 || bufs[0].epoch == epoch) + { + __dump_buffer(mode, bufs); + } + bufs++; + } +} +#endif // NDEBUG + +void *get_buffer(const char *bufname, int in, unsigned *_len, unsigned *_bits, const NN_Interface_TypeDef *nn_interface) +{ + const LL_Buffer_InfoTypeDef *buf = __get_buffer(bufname, in, nn_interface); + if (buf != NULL) + { + uint8_t *p = LL_ATON_physical_to_virtual((uintptr_t)LL_Buffer_addr_start(buf)); + *_len = LL_Buffer_len(buf); + *_bits = LL_Buffer_bits(buf); + return (void *)p; + } + return NULL; +} + +int get_buffer_info(const char *bufname, int in, LL_Buffer_InfoTypeDef *ret, const NN_Interface_TypeDef *nn_interface) +{ + const LL_Buffer_InfoTypeDef *buf = __get_buffer(bufname, in, nn_interface); + if (buf != NULL) + { + *ret = *buf; + ret->addr_base.i = (uintptr_t)LL_ATON_physical_to_virtual((uintptr_t)buf->addr_base.i); + ret->offset_start = buf->offset_start; + ret->offset_end = buf->offset_end; + return 1; + } + return 0; +} + +void set_all_buffers(int in, unsigned val, const NN_Interface_TypeDef *nn_interface) +{ + if ((in & BUFF_IN) != 0) + __set_all_buffers(nn_interface->input_buffers_info(), val); + if ((in & BUFF_OUT) != 0) + __set_all_buffers(nn_interface->output_buffers_info(), val); + if ((in & BUFF_INT) != 0) + __set_all_buffers(nn_interface->internal_buffers_info(), val); +} + +void dump_buffer(int mode, const char *bufname, int in, const NN_Interface_TypeDef *nn_interface) +{ +#ifndef NDEBUG + __dump_buffer(mode, __get_buffer(bufname, in, nn_interface)); +#endif // NDEBUG +} + +void dump_all_buffers(int mode, int in, const NN_Interface_TypeDef *nn_interface) +{ +#ifndef NDEBUG + if ((in & BUFF_IN) != 0) + __dump_epoch_buffers(nn_interface->input_buffers_info(), mode, -1); + if ((in & BUFF_OUT) != 0) + __dump_epoch_buffers(nn_interface->output_buffers_info(), mode, -1); + if ((in & BUFF_INT) != 0) + __dump_epoch_buffers(nn_interface->internal_buffers_info(), mode, -1); +#endif // NDEBUG +} + +void dump_epoch_buffers(int mode, int epoch, const NN_Interface_TypeDef *nn_interface) +{ +#ifndef NDEBUG + __dump_epoch_buffers(nn_interface->internal_buffers_info(), mode, epoch); +#endif // NDEBUG +} + +/** @brief Return the total length of network parameters + */ +unsigned int get_params_len(const NN_Interface_TypeDef *nn_interface) +{ + LL_Buffer_InfoTypeDef *bufdesc = (LL_Buffer_InfoTypeDef *)nn_interface->input_buffers_info(); + unsigned int plen = 0; + + while (bufdesc->name) + { + if (bufdesc->is_param) + plen += LL_Buffer_len(bufdesc); + bufdesc++; + } + + return plen; +} + +#endif diff --git a/lib/stai/libstai/ll_aton/ll_aton_lib.c b/lib/stai/libstai/ll_aton/ll_aton_lib.c new file mode 100644 index 000000000..7c345881a --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_lib.c @@ -0,0 +1,3559 @@ +/** + ****************************************************************************** + * @file ll_aton_lib.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL library for basic kernels making use of HW blocks driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ll_aton_util.h" // Leave blank line after the include + +#include "ll_aton_caches_interface.h" +#include "ll_aton_lib.h" +#include "ll_aton_runtime.h" + +#if _LL_LIB_DEBUG +#include + +// if set it will perform CHECKDISTANCE with COSINE_SIMILARIY and not with MAXDISTANCE +#define USE_COSINE_SIMILARITY +// CHECKDISTANCE mode thresholds +#define MAXDISTANCE_TH 3 +#define COSINE_SIMILARITY_TH 0.9 + +int LL_LIB_TENSOR_ELEMENTS(const LL_LIB_TensorInfo_TypeDef *t) +{ + int cont = 1; + for (int i = 0; i < t->ndims; i++) + cont *= t->shape[i]; + return cont; +} + +void __ll_lib_error(int err_code, int line, const char *func) // for library internal use only +{ +#ifndef NDEBUG + char *errs; + switch (err_code) + { + case _ERR_NINPUTS: + errs = "Wrong number of inputs"; + break; + case _ERR_NOUTPUTS: + errs = "Wrong number of outputs"; + break; + case _ERR_AXIS: + errs = "Axis mismatch or not supported"; + break; + case _ERR_FRACTIONAL: + errs = "Fractional bits not supported"; + break; + case _ERR_DATATYPE: + errs = "Datatype not supported"; + break; + case _ERR_NBITS: + errs = "Number of bits unsupported or in/out mismatch"; + break; + case _ERR_NBITS_IN: + errs = "Number of bits unsupported or in(s) mismatch"; + break; + case _ERR_NBITS_OUT: + errs = "Number of bits unsupported or out(s) mismatch"; + break; + case _ERR_SHAPE: + errs = "Shape unsupported or in/out mismatch"; + break; + case _ERR_SHAPE_IN: + errs = "Shape unsupported or in(s) mismatch"; + break; + case _ERR_SHAPE_OUT: + errs = "Shape unsupported or out(s) mismatch"; + break; + case _ERR_BUFFER: + errs = "Buffer sizes in/out mismatch"; + break; + case _ERR_BUFFER_IN: + errs = "Buffer sizes in(s) mismatch"; + break; + case _ERR_BUFFER_OUT: + errs = "Buffer sizes out(s) mismatch"; + break; + case _ERR_RANK: + errs = "Inconsistent or unexpected rank value(s)"; + break; + case _ERR_MODE: + errs = "Unknown or not supported modality"; + break; + case _ERR_UNKNOWN: + default: + errs = "Unknown"; + break; + } + LL_ATON_PRINTF("%s line %d LL_LIB Error: %s\n", func, line, errs); +#endif // NDEBUG +} +#endif // _LL_LIB_DEBUG + +/*** Heap for hybrid operator implementations ***/ +static uint32_t __ll_lib_heap[__LL_LIB_HEAP_SIZE]; // REMEMBER: static variables are not suited for + // multithreaded etc. environments +/** Static constants **/ +static LL_Switch_InitTypeDef switch_init[] = {{LL_Switch_Init_Dest() = ATONN_DSTPORT(STRSWITCH, 0, STRENG, 1, 0), + LL_Switch_Init_Source(0) = ATONN_SRCPORT(STRSWITCH, 0, STRENG, 0, 0), + LL_Switch_Init_Context(0) = 1, LL_Switch_Init_Frames(0) = 0}}; +static int dma_unit_id[] = {1, 0}; /* {, } */ +static LL_ATON_EnableUnits_InitTypeDef dma_units[] = {{{STRENG, 1}}, {{STRENG, 0}}}; +static const LL_Streng_TensorInitTypeDef _static_const_dma_in = { + .dir = 0, .raw = 1, .frame_tot_cnt = 1, .nbits_in = 24, .nbits_out = 24}; +static const LL_Streng_TensorInitTypeDef _static_const_dma_out = { + .dir = 1, .raw = 1, .frame_tot_cnt = 1, .nbits_in = 24, .nbits_out = 24}; + +/** Helper function(s) **/ +static inline __ll_lib_params_t *__ll_lib_get_params(void) +{ + return (__ll_lib_params_t *)__ll_lib_heap; +} + +static inline void *__ll_lib_get_lower_heap(void) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + params++; + return (void *)params; +} + +static inline void __ll_lib_dump_strswitch(int dma_in, int dma_out) +{ +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("===\n"); + LL_ATON_PRINTF("dma_in: %d, dma_out: %d\n", dma_in, dma_out); + LL_ATON_PRINTF("---\n"); + LL_ATON_PRINTF("dest: %d\n", ATONN_DSTPORT_ID(switch_init[0].dest)); + LL_ATON_PRINTF("---\n"); + LL_ATON_PRINTF("source0: %d\n", ATONN_SRCPORT_ID(switch_init[0].source0)); + LL_ATON_PRINTF("frames0: %d\n", switch_init[0].frames0); + LL_ATON_PRINTF("context0: %d\n", switch_init[0].context0); + LL_ATON_PRINTF("---\n"); + LL_ATON_PRINTF("source1: %d\n", ATONN_SRCPORT_ID(switch_init[0].source1)); + LL_ATON_PRINTF("frames1: %d\n", switch_init[0].frames1); + LL_ATON_PRINTF("context1: %d\n", switch_init[0].context1); + LL_ATON_PRINTF("===\n"); + +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif // !DUMP_DEBUG_SW_OPS +} + +static void __ll_lib_strswitch_set_dmas(int dma_in, int dma_out, LL_ATON_RT_EpochBlockItem_t *epoch_block_array) +{ + __ll_lib_dump_strswitch(dma_in, dma_out); + + __ll_lib_params_t *params = __ll_lib_get_params(); + + switch_init[0].source0 = __atonn_getSrcPortID(STRSWITCH, 0, STRENG, dma_in, 0); + switch_init[0].dest = __atonn_getDstPortID(STRSWITCH, 0, STRENG, dma_out, 0); + + AccelUnits dma_in_streng = {STRENG, dma_in}; + AccelUnits dma_out_streng = {STRENG, dma_out}; + + dma_units[1].unit = dma_in_streng; + dma_unit_id[1] = dma_in; + dma_units[0].unit = dma_out_streng; + dma_unit_id[0] = dma_out; + + uint32_t wait_mask = (0x1 << dma_out); + params->g_wait_mask = wait_mask; + epoch_block_array->wait_mask = wait_mask; + + __ll_lib_dump_strswitch(dma_in, dma_out); +} + +static inline void __ll_lib_start_transfer(__ll_lib_params_t *params) +{ + LL_Streng_TensorInit(dma_unit_id[1], ¶ms->g_dma_in, 1); + LL_Streng_TensorInit(dma_unit_id[0], ¶ms->g_dma_out, 1); + LL_Switch_Init_NoReset(switch_init, 1); + LL_ATON_EnableUnits_Init(dma_units, 2); +} + +static inline void __ll_lib_stop_transfer(void) +{ + LL_Switch_Deinit(switch_init, 1); + LL_ATON_DisableUnits_Init(dma_units, 2); +} + +static inline uint32_t __ll_lib_set_wait_mask(LL_ATON_RT_EpochBlockItem_t *eb, uint32_t wait_mask) +{ + uint32_t previous_value; + previous_value = eb->wait_mask; + eb->wait_mask = wait_mask; + + __LL_ATON_RT_SetWaitMask(eb->wait_mask); + + return previous_value; +} + +static inline void __ll_lib_prepare_inputs_epoch(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_Streng_TensorInitTypeDef *dma_in, + const LL_Streng_TensorInitTypeDef *dma_out, unsigned char *out_start, + int nbytes_or_line_size) +{ + /* get pointers to static structures */ + __ll_lib_params_t *params = __ll_lib_get_params(); + void *inputs_copy = __ll_lib_get_lower_heap(); + + /* fill `inputs_copy` */ + // NOTE: must treat the failing of the beyond `LL_ATON_ASSERT` statement as error! + // TODO: must be changed in a way that allows both a return from this function + // and to return control back to the user's main loop + // e.g. by using an internal flag/variable to signal the error, + // then performing a `LL_ATON_RT_RuntimeDeInit()`, + // and returning with a respective (new) return value (of type `LL_ATON_RT_RetValues_t`), + // reporting about the error, from the latest call to `LL_ATON_RT_RunEpochBlock()` + LL_ATON_ASSERT(ninputs <= __LL_MAX_TENSORS); + memcpy(inputs_copy, inputs, sizeof(LL_LIB_TensorInfo_TypeDef) * ninputs); + + params->g_tensors = inputs_copy; + params->g_num_tensors = ninputs; + + params->g_dma_in = *dma_in; + params->g_dma_out = *dma_out; + + params->g_dst_o_src = out_start; + params->g_not_continuous = 0; // signals that destination is not written linearly + + params->g_size = nbytes_or_line_size; + params->g_idx = 0; + + params->g_offset_limit = 0; +} + +static inline void __ll_lib_prepare_outputs_epoch(const LL_LIB_TensorShape_TypeDef *outputs, unsigned int noutputs, + const LL_Streng_TensorInitTypeDef *dma_in, + const LL_Streng_TensorInitTypeDef *dma_out, + const LL_LIB_TensorShape_TypeDef *input) +{ + /* get pointers to static structures */ + __ll_lib_params_t *params = __ll_lib_get_params(); + void *outputs_copy = __ll_lib_get_lower_heap(); + + /* fill `outputs_copy` */ + // NOTE: must treat the failing of the beyond `LL_ATON_ASSERT` statement as error! + // TODO: must be changed in a way that allows both a return from this function + // and to return control back to the user's main loop + // e.g. by using an internal flag/variable to signal the error, + // then performing a `LL_ATON_RT_RuntimeDeInit()`, + // and returning with a respective (new) return value (of type `LL_ATON_RT_RetValues_t`), + // reporting about the error, from the latest call to `LL_ATON_RT_RunEpochBlock()` + LL_ATON_ASSERT(noutputs <= __LL_MAX_TENSORS); + memcpy(outputs_copy, outputs, sizeof(LL_LIB_TensorShape_TypeDef) * noutputs); + + params->g_tensors = outputs_copy; + params->g_num_tensors = noutputs; + + params->g_dma_in = *dma_in; + params->g_dma_out = *dma_out; + + params->g_dst_o_src = LL_Buffer_addr_start(input); + params->g_dst_o_src = LL_Buffer_addr_start(input); + params->g_not_continuous = 0; // signals that source is not read linearly + + params->g_size = -1; + params->g_idx = 0; + + params->g_offset_limit = input->offset_limit; +} + +/* `memcpy` generic epoch blocks */ +static inline size_t __ll_lib_memcpy_prolog(void **dst, void **src, size_t n) +{ + uint8_t *_dst_orig = *dst; + + int prolog_len = (n % 3); + int i; + uint8_t **_dst = (uint8_t **)dst; + uint8_t **_src = (uint8_t **)src; + + if (n < __LL_DMA_MIN_BUFF_LEN) + prolog_len = n; // not worth it ... + + for (i = 0; i < prolog_len; i++) + { + **_dst = **_src; + (*_dst)++; + (*_src)++; + } + n -= prolog_len; + + if (prolog_len > 0) + { + /* *** MCU cache clean & invalidate operation (SW) *** */ + LL_ATON_Cache_MCU_Clean_Invalidate_Range(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR((uintptr_t)_dst_orig), prolog_len); + } + + return n; +} + +static void __ll_lib_inputs_memcpy_start(const void *epoch_block, uint8_t *_src) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + uint8_t *_dst = (uint8_t *)params->g_dst_o_src; + size_t n; + + if (params->g_size < 0) + { + n = LL_Buffer_len(((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + params->g_idx); + } + else + { + n = params->g_size; + } + + if (params->g_not_continuous == 0) + n = __ll_lib_memcpy_prolog((void **)&_dst, (void **)&_src, n); + + if (n > 0) + { + params->g_dma_in.addr_base.p = _src; + params->g_dma_in.offset_start = 0; + params->g_dma_in.offset_end = n; // not used for batched output version g_not_continuous == 1 + params->g_dma_in.offset_limit = ((LL_LIB_TensorInfo_TypeDef *)params->g_tensors)[params->g_idx].offset_limit; + + params->g_dma_out.addr_base.p = _dst; + params->g_dma_out.offset_start = 0; + params->g_dma_out.offset_end = n; // not used for batched input version g_not_continuous == 1 + + __ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, params->g_wait_mask); + + __ll_lib_start_transfer(params); + } + else + { + /* do not start any transfer and wait, just proceed to end function */ + __ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0); + } +} + +static void __ll_lib_outputs_memcpy_start(const void *epoch_block, uint8_t *_dst) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + uint8_t *_src = (uint8_t *)params->g_dst_o_src; + size_t n; + + if (params->g_size < 0) + { + n = LL_Buffer_len(((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx); + } + else + { + n = params->g_size; + } + + if (params->g_not_continuous == 0) + n = __ll_lib_memcpy_prolog((void **)&_dst, (void **)&_src, n); + + if (n > 0) + { + params->g_dma_out.addr_base.p = _dst; + params->g_dma_out.offset_start = 0; + params->g_dma_out.offset_end = n; + + if (params->g_not_continuous == 0) + { + params->g_dma_in.addr_base.p = _src; + params->g_dma_in.offset_start = 0; + params->g_dma_in.offset_end = n; + } + params->g_dma_in.offset_limit = params->g_offset_limit; + + __ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, params->g_wait_mask); + __ll_lib_start_transfer(params); + } + else + { + /* do not start any transfer and wait, just proceed to end function */ + __ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0); + } +} + +/** Epoch start/end functions and epoch block arrays **/ + +static void __LL_LIB_Concat_Case3_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + LL_ATON_ASSERT((params->special.concat_case3.outer_idx < params->g_num_tensors) && + (params->g_idx < params->special.concat_case3.in_fheight)); // must be checked before + + __ll_lib_inputs_memcpy_start(epoch_block, (uint8_t *)params->special.concat_case3.in_curr); +} + +static void __LL_LIB_Concat_Case3_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + params->g_idx++; + + if (params->g_idx < params->special.concat_case3.in_fheight) + { + params->g_dst_o_src += params->special.concat_case3.out_line_size; + params->special.concat_case3.in_curr += params->g_size; + + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + params->special.concat_case3.outer_idx++; + + if (params->special.concat_case3.outer_idx < params->g_num_tensors) + { + int in_ndims = ((LL_LIB_TensorInfo_TypeDef *)params->g_tensors)[params->special.concat_case3.outer_idx].ndims; + unsigned int pix_size = params->special.concat_case3.nbytes * + ((LL_LIB_TensorInfo_TypeDef *)params->g_tensors)[params->special.concat_case3.outer_idx] + .shape[(in_ndims - 4) + TDIM_NCHANNELS]; + params->g_size = + pix_size * ((LL_LIB_TensorInfo_TypeDef *)params->g_tensors)[params->special.concat_case3.outer_idx] + .shape[(in_ndims - 4) + TDIM_FWIDTH]; + params->g_dst_o_src += params->g_size; + params->special.concat_case3.in_curr = LL_Buffer_addr_start(((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + + params->special.concat_case3.outer_idx); + params->g_idx = 0; + + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + /* proceed to next epoch block */ + } + } +} + +static void __LL_LIB_Inputs_Memcpy_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + LL_ATON_ASSERT(params->g_idx < params->g_num_tensors); // must be checked before + + uint8_t *src = (uint8_t *)LL_Buffer_addr_start(((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + params->g_idx); + __ll_lib_inputs_memcpy_start(epoch_block, src); +} + +static void __LL_LIB_Inputs_Memcpy_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + if (params->g_size < 0) + { + params->g_dst_o_src += LL_Buffer_len(((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + params->g_idx); + } + else + { + params->g_dst_o_src += (params->g_size); + } + params->g_idx++; + + if (params->g_idx < params->g_num_tensors) + { + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + /* proceed to next epoch block */ + } +} + +static void __LL_LIB_Inputs_Batched_Memcpy_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + LL_ATON_ASSERT(params->g_idx < params->g_num_tensors); // must be checked before + params->g_not_continuous = + 1; // disables code in __ll_lib_inputs_memcpy_start that assumes a flat copy operation e.g. prolog test + + uint8_t *src = (uint8_t *)LL_Buffer_addr_start(((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + params->g_idx); + __ll_lib_inputs_memcpy_start(epoch_block, src); +} + +static void __LL_LIB_Inputs_Batched_Memcpy_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + LL_LIB_TensorInfo_TypeDef *in = ((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + params->g_idx; + int in_ndims = in->ndims; + int in_nchannels_old = in->shape[(in_ndims - 4) + TDIM_NCHANNELS]; + + params->g_idx++; + + if (params->g_idx < params->g_num_tensors) + { + in = ((LL_LIB_TensorInfo_TypeDef *)params->g_tensors) + params->g_idx; + + int nbits = in->nbits; + int nbytes = (nbits + 7) >> 3; + int in_batch = in->batch; + int in_fheight = in->shape[(in_ndims - 4) + TDIM_FHEIGHT]; + int in_fwidth = in->shape[(in_ndims - 4) + TDIM_FWIDTH]; + int in_nchannels = in->shape[(in_ndims - 4) + TDIM_NCHANNELS]; + + params->g_dst_o_src += in_nchannels_old * nbytes; + + // LL_ATON_PRINTF("nbytes=%d fw=%d fh=%d inb=%d inc=%d\n", nbytes, in_fwidth, in_fheight, in_batch, in_nchannels); + + params->g_dma_out.batch_depth = (nbytes == 4) ? (2 * in_batch) : in_batch; // this must be updated on all inputs + params->g_dma_out.frame_offset = in_batch * nbytes; // this must be updated on all inputs + params->g_dma_out.frame_loop_cnt = in_nchannels / in_batch; // this must be updated on all inputs + params->g_dma_out.frame_tot_cnt = in_nchannels / in_batch; // this must be updated on all inputs + params->g_dma_out.loop_offset = in_fheight * in_fwidth * in_batch * nbytes; // this must be updated on all inputs + + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + /* proceed to next epoch block */ + } +} + +static void __LL_LIB_Outputs_Channel_Split_Aton_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + LL_ATON_ASSERT(params->g_idx < params->g_num_tensors); // must be checked before + params->g_not_continuous = + 1; // disables code in __ll_lib_outputs_memcpy_start that assumes a flat copy operation e.g. prolog test + + uint8_t *dst = (uint8_t *)LL_Buffer_addr_start(((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx); + __ll_lib_outputs_memcpy_start(epoch_block, dst); +} + +static void __LL_LIB_Outputs_Channel_Split_Aton_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + LL_LIB_TensorShape_TypeDef *out = ((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx; + int out_rank_old = out->ndims; + int out_nchannels_old = out->shape[(out_rank_old - 4) + 1 /* ONNX_CHANNEL_OFFSET */]; + + params->g_idx++; + + if (params->g_idx < params->g_num_tensors) + { + out = ((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx; + + uint32_t out_ndims = out->ndims; + LL_ATON_ASSERT(out_ndims >= 3); + uint32_t nbytes = LL_LIB_NBYTES(out->nbits); + uint32_t out_fwidth = out->shape[(out_ndims - 4) + TDIM_ONNX_FWIDTH]; + uint32_t out_fheight = out->shape[(out_ndims - 4) + TDIM_ONNX_FHEIGHT]; + uint32_t out_nchannels = out->shape[(out_ndims - 4) + TDIM_ONNX_NCHANNELS]; + + // program output DMA + params->g_dma_out.addr_base.p = out->addr_base.p; + params->g_dma_out.offset_start = out->offset_start; + params->g_dma_out.offset_end = out->offset_end; + + // LL_ATON_PRINTF("\ndma_out: addr_start=%p, addr_end=%p\n", LL_Streng_addr_start(&(params->g_dma_out)), + // LL_Streng_addr_end(&(params->g_dma_out)); + + unsigned batch_depth = (nbytes == 4) ? (2 * out_nchannels) : out_nchannels; + unsigned frame_size = out_fwidth * out_fheight * batch_depth; + + // program input DMA + if (frame_size != 1) + { + params->g_dma_in.raw = 0; // this must be updated on all outputs + params->g_dma_in.offset_start += out_nchannels_old * nbytes; // this must be updated on all outputs + params->g_dma_in.batch_depth = batch_depth; // this must be updated on all outputs + + // LL_ATON_PRINTF("dma_in: frame_size=%d, nbytes=%u, out_nchannels_old=%d, out_nchannels=%u, src=%p, + // out_fwidth=%u, out_fheight=%u, batch_depth=%u, batch_offset=%u, line_offset=%u, frame_offset=%u, + // frame_tot_cnt=%u\n", + // frame_size, nbytes, out_nchannels_old, out_nchannels, LL_Streng_addr_start(&(params->g_dma_in)), + // params->g_dma_in.fwidth, params->g_dma_in.fheight, params->g_dma_in.batch_depth, + // params->g_dma_in.batch_offset, params->g_dma_in.line_offset, params->g_dma_in.frame_offset, + // params->g_dma_in.frame_tot_cnt); + // LL_ATON_FFLUSH(stdout); + } + else + { // frame_size == 1 +#if 1 + LL_ATON_ASSERT(0); // should never happen!!! +#else + params->g_dma_in.raw = 1; // this must be updated on all outputs + params->g_dma_in.offset_start += out_nchannels_old * nbytes; // this must be updated on all outputs + params->g_dma_in.offset_end += + params->g_dma_in.offset_start + + nbytes; // this must be updated on all outputs FIXME Francesco incorrect calculation +#endif + } + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + /* proceed to next epoch block */ + } +} + +static void __LL_LIB_Outputs_Channel_Split_Batched_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + LL_ATON_ASSERT(params->g_idx < params->g_num_tensors); // must be checked before + params->g_not_continuous = + 1; // disables code in __ll_lib_outputs_memcpy_start that assumes a flat copy operation e.g. prolog test + + uint8_t *dst = (uint8_t *)LL_Buffer_addr_start(((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx); + __ll_lib_outputs_memcpy_start(epoch_block, dst); +} + +static void __LL_LIB_Outputs_Channel_Split_Batched_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + LL_LIB_TensorShape_TypeDef *out = ((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx; + int out_rank_old = out->ndims; + int out_nchannels_old = out->shape[(out_rank_old - 4) + 1 /* ONNX_CHANNEL_OFFSET */]; + + params->g_idx++; + + if (params->g_idx < params->g_num_tensors) + { + out = ((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx; + + uint32_t out_ndims = out->ndims; + LL_ATON_ASSERT(out_ndims >= 3); + uint32_t nbytes = LL_LIB_NBYTES(out->nbits); + uint32_t out_fwidth = out->shape[(out_ndims - 4) + TDIM_ONNX_FWIDTH]; + uint32_t out_fheight = out->shape[(out_ndims - 4) + TDIM_ONNX_FHEIGHT]; + uint32_t out_nchannels = out->shape[(out_ndims - 4) + TDIM_ONNX_NCHANNELS]; + uint16_t out_batch = out->batch; + LL_ATON_ASSERT((out_nchannels % out_batch) == 0); + + // program output DMA + params->g_dma_out.addr_base.p = out->addr_base.p; + params->g_dma_out.offset_start = out->offset_start; + params->g_dma_out.offset_end = out->offset_end; + + // LL_ATON_PRINTF("\ndma_out: addr_start=%p, addr_end=%p\n", LL_Streng_addr_start(&(params->g_dma_out)), + // LL_Streng_addr_end(&(params->g_dma_out))); + + unsigned batch_depth = (nbytes == 4) ? (2 * out_batch) : out_batch; + unsigned frame_size = out_fwidth * out_fheight * batch_depth; + + // program input DMA + if (frame_size != 1) + { + params->g_dma_in.raw = 0; // this must be updated on all outputs + params->g_dma_in.offset_start += out_nchannels_old * nbytes; // this must be updated on all outputs + params->g_dma_in.batch_depth = batch_depth; // this must be updated on all outputs + params->g_dma_in.frame_tot_cnt = out_nchannels / out_batch; // this must be updated on all outputs + params->g_dma_in.loop_offset = out_batch * nbytes; // this must be updated on all outputs + + // LL_ATON_PRINTF("dma_in: frame_size=%d, nbytes=%u, out_nchannels_old=%d, out_nchannels=%u, src=%p, + // out_fwidth=%u, out_fheight=%u, batch_depth=%u, batch_offset=%u, line_offset=%u, frame_offset=%u, + // frame_tot_cnt=%u\n", + // frame_size, nbytes, out_nchannels_old, out_nchannels, LL_Streng_addr_start(&(params->g_dma_in)), + // params->g_dma_in.fwidth, params->g_dma_in.fheight, params->g_dma_in.batch_depth, + // params->g_dma_in.batch_offset, params->g_dma_in.line_offset, params->g_dma_in.frame_offset, + // params->g_dma_in.frame_tot_cnt); + // LL_ATON_FFLUSH(stdout); + } + else + { // frame_size == 1 +#if 1 + LL_ATON_ASSERT(0); // should never happen!!! +#else + // TODO (as not yet adapted for this case) + params->g_dma_in.raw = 1; // this must be updated on all outputs + params->g_dma_in.offset_start += out_nchannels_old * nbytes; // this must be updated on all outputs + params->g_dma_in.offset_end += + params->g_dma_in.offset_start + + nbytes; // this must be updated on all outputs FIXME Francesco incorrect calculation +#endif + } + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + /* proceed to next epoch block */ + } +} + +static void __LL_LIB_Outputs_Memcpy_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + LL_ATON_ASSERT(params->g_idx < params->g_num_tensors); // must be checked before + + uint8_t *dst = (uint8_t *)LL_Buffer_addr_start(((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx); + __ll_lib_outputs_memcpy_start(epoch_block, dst); +} + +static void __LL_LIB_Outputs_Memcpy_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + if (params->g_size < 0) + { + params->g_dst_o_src += LL_Buffer_len(((LL_LIB_TensorShape_TypeDef *)params->g_tensors) + params->g_idx); + } + else + { + params->g_dst_o_src += (params->g_size); + } + params->g_idx++; + + if (params->g_idx < params->g_num_tensors) + { + /* loop back one epoch block */ + LL_ATON_RT_DecCurrEpochBlock(1); + } + else + { + /* proceed to next epoch block */ + } +} + +static void __LL_LIB_DMA_Pad_Memset_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + + __ll_lib_stop_transfer(); + + if (params->special.pad.callback_function != NULL) + { + /* return from current epoch block */ + __LL_ATON_RT_RetFromLibEpochBlockArray(false, NULL); + /* call follow-up function */ + (*params->special.pad.callback_function)(¶ms->special.pad); + } +} + +static void __LL_LIB_DMA_Pad_Filling_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + __ll_pad_sw_params_t *common_params = ¶ms->special.pad; + + /* set destination address */ + params->g_dst_o_src = (unsigned char *)common_params->out_target; + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): ASSIGN in=%lx, out=%lx, bytes=%u\n", __func__, __LINE__, (uintptr_t)common_params->in_target, + (uintptr_t)common_params->out_target, common_params->consecutive_bytes); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + + /* start `memcpy` */ + { + uint8_t *_dst = (uint8_t *)params->g_dst_o_src; + uint8_t *_src = (uint8_t *)common_params->in_target; + size_t n; + + n = params->g_size; + n = __ll_lib_memcpy_prolog((void **)&_dst, (void **)&_src, n); + + if (n > 0) + { + params->g_dma_in.addr_base.p = (uint8_t *)_src; + params->g_dma_in.offset_start = 0; + params->g_dma_in.offset_end = n; + params->g_dma_in.offset_limit = (uint8_t *)common_params->in_limit - (uint8_t *)_src; /* awful FIXME Francesco */ + + params->g_dma_out.addr_base.p = _dst; + params->g_dma_out.offset_start = 0; + params->g_dma_out.offset_end = n; + + __ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, params->g_wait_mask); + + __ll_lib_start_transfer(params); + } + else + { + /* do not start any transfer and wait, just proceed to end function */ + __ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0); + } + } +} + +static void __LL_LIB_DMA_Pad_Filling_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + __ll_pad_sw_params_t *common_params = ¶ms->special.pad; + + if (__ll_lib_set_wait_mask((LL_ATON_RT_EpochBlockItem_t *)epoch_block, 0)) + { + __ll_lib_stop_transfer(); + } + + bool return_from_memcpy = true; + + do + { + if (common_params->pad_out_offsets_end[params->g_idx] > 0) + { + common_params->out_target += common_params->pad_out_offsets_end[params->g_idx]; + } + + if (common_params->pad_in_offsets_end[params->g_idx] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_end[params->g_idx]; + } + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - end offsets for: curr_axis=%u, index=%u\n", __func__, __LINE__, params->g_idx, + common_params->indexes[params->g_idx]); +#endif + + /* returning from `memcpy` or coming from `end of do-while-loop` */ + if (return_from_memcpy) + { // returning from `memcpy` + LL_ATON_ASSERT(params->g_idx == common_params->consecutive_axis); +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - return from memcpy: curr_axis=%u, index=%u\n", __func__, __LINE__, params->g_idx, + common_params->indexes[params->g_idx]); +#endif + common_params->in_target += common_params->consecutive_bytes; + common_params->out_target += common_params->consecutive_bytes; + + if (params->g_idx == 0) + { + break; + } + } + + LL_ATON_ASSERT(params->g_idx > 0); + params->g_idx--; +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - return to previous axis: curr_axis=%u, index=%u\n", __func__, __LINE__, params->g_idx, + common_params->indexes[params->g_idx]); +#endif + + common_params->indexes[params->g_idx] += 1; +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - inc axis index: curr_axis=%u, index=%u\n", __func__, __LINE__, params->g_idx, + common_params->indexes[params->g_idx]); +#endif + if (common_params->indexes[params->g_idx] < common_params->min_shape[params->g_idx]) + { + inner_loop: + params->g_idx++; +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF( + "%s(%d) - valid axis value, proceeded to next axis & apply start offsets: curr_axis=%u, index=%u\n", __func__, + __LINE__, params->g_idx, common_params->indexes[params->g_idx]); +#endif + + if (common_params->pad_out_offsets_start[params->g_idx] > 0) + { + common_params->out_target += common_params->pad_out_offsets_start[params->g_idx]; + } + + if (common_params->pad_in_offsets_start[params->g_idx] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_start[params->g_idx]; + } + + if (params->g_idx == common_params->consecutive_axis) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - reached consecutive axis -> memcpy: curr_axis=%u, index=%u\n", __func__, __LINE__, + params->g_idx, common_params->indexes[params->g_idx]); +#endif + /* loop back one epoch block to start DMAs for filling next `consecutive bytes` */ + LL_ATON_RT_DecCurrEpochBlock(1); + return; + } + else + { // normal axis +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - repeat inner loop: curr_axis=%u, index=%u\n", __func__, __LINE__, params->g_idx, + common_params->indexes[params->g_idx]); +#endif + goto inner_loop; + } + } + else + { + common_params->indexes[params->g_idx] = 0; +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d) - axis overflow -> end loop & return to prev axis: curr_axis=%u, index=%u\n", __func__, + __LINE__, params->g_idx, common_params->indexes[params->g_idx]); +#endif + } + return_from_memcpy = false; + } while (params->g_idx > 0); + + if (params->special.pad.callback_function != NULL) + { + /* return from current epoch block */ + __LL_ATON_RT_RetFromLibEpochBlockArray(false, NULL); + /* call follow-up function */ + (*params->special.pad.callback_function)(¶ms->special.pad); + return; + } + +#if defined(DUMP_RESULTS_PAD_OP) + /* debug output print */ + switch (common_params->nbytes) + { + case 1: + { + int8_t *ptr = (int8_t *)common_params->saved_out_target; + for (uint32_t i = 0; i < common_params->out_size; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 2: + { + int16_t *ptr = (int16_t *)(int8_t *)common_params->saved_out_target; + for (uint32_t i = 0; i < common_params->out_size / 2; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 3: // NOTE: assuming no alignment + { + /* check endianess */ + const int32_t _const_val = 0x01020304; + const int8_t *_const_val_ptr = (int8_t *)&_const_val; + bool is_little_endian = (_const_val_ptr[0] == 0x04); + + int8_t *ptr = (int8_t *)common_params->saved_out_target; + if (is_little_endian) + { + for (uint32_t i = 0; i < common_params->out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i]; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2] << 16; + + LL_ATON_PRINTF("%d\n", value); + } + } + else + { + for (uint32_t i = 0; i < common_params->out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i] << 16; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2]; + + LL_ATON_PRINTF("%d\n", value); + } + } + } + break; + case 4: + { + int32_t *ptr = (int32_t *)(int8_t *)common_params->saved_out_target; + for (uint32_t i = 0; i < common_params->out_size / 4; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + default: + LL_ATON_ASSERT(false); + break; + } +#endif // DUMP_RESULTS_PAD_OP +} + +static void __LL_LIB_DMA_Transfer_Start_EpochBlock(const void *epoch_block) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + __ll_lib_start_transfer(params); +} + +static void __LL_LIB_DMA_Transfer_End_EpochBlock(const void *epoch_block) +{ + __ll_lib_stop_transfer(); + + /* proceed to next epoch block */ +} + +static LL_ATON_RT_EpochBlockItem_t _concat_case3_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_Concat_Case3_Start_EpochBlock, + .end_epoch_block = __LL_LIB_Concat_Case3_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -1, + .last_epoch_num = -1, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _inputs_memcpy_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_Inputs_Memcpy_Start_EpochBlock, + .end_epoch_block = __LL_LIB_Inputs_Memcpy_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -2, + .last_epoch_num = -2, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _inputs_batched_memcpy_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_Inputs_Batched_Memcpy_Start_EpochBlock, + .end_epoch_block = __LL_LIB_Inputs_Batched_Memcpy_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -3, + .last_epoch_num = -3, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _outputs_memcpy_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_Outputs_Memcpy_Start_EpochBlock, + .end_epoch_block = __LL_LIB_Outputs_Memcpy_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -4, + .last_epoch_num = -4, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _outputs_channel_split_aton_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_Outputs_Channel_Split_Aton_Start_EpochBlock, + .end_epoch_block = __LL_LIB_Outputs_Channel_Split_Aton_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -5, + .last_epoch_num = -5, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _outputs_channel_split_batched_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_Outputs_Channel_Split_Batched_Start_EpochBlock, + .end_epoch_block = __LL_LIB_Outputs_Channel_Split_Batched_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -6, + .last_epoch_num = -6, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _dma_ri2ir_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_DMA_Transfer_Start_EpochBlock, + .end_epoch_block = __LL_LIB_DMA_Transfer_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -7, + .last_epoch_num = -7, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _dma_Pad_memset_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_DMA_Transfer_Start_EpochBlock, + .end_epoch_block = __LL_LIB_DMA_Pad_Memset_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -8, + .last_epoch_num = -8, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _dma_Pad_filling_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_DMA_Pad_Filling_Start_EpochBlock, + .end_epoch_block = __LL_LIB_DMA_Pad_Filling_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -9, + .last_epoch_num = -9, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _dma_transpose_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_DMA_Transfer_Start_EpochBlock, + .end_epoch_block = __LL_LIB_DMA_Transfer_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -10, + .last_epoch_num = -10, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +static LL_ATON_RT_EpochBlockItem_t _slice_split_like_epoch_block_array[] = { + // REMEMBER: static variables are not suited for multithreaded etc. environments + { + .start_epoch_block = __LL_LIB_DMA_Transfer_Start_EpochBlock, + .end_epoch_block = __LL_LIB_DMA_Transfer_End_EpochBlock, + .flags = EpochBlock_Flags_internal, +#ifdef LL_ATON_EB_DBG_INFO + .epoch_num = -11, + .last_epoch_num = -11, +#endif + }, + {.flags = EpochBlock_Flags_last_eb}, +}; + +/** + * @brief performs a memory copy operation from `ninputs` inputs to one output using stream engines `dma_in` and + * `dma_out` + * @param inputs list of input tensor info structures + * @param ninputs number of inputs + * @param dst destination address + * @param nbytes number of bytes to copy (-1 means: derive from `inputs` structure) + */ +static void __LL_ATON_LIB_DMA_Inputs_Memcpy(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + unsigned char *dst, int nbytes, int dma_in, int dma_out) +{ + /* start epoch block sequence */ + if (ninputs > 0) + { + /* prepare epoch */ + __ll_lib_prepare_inputs_epoch(inputs, ninputs, &_static_const_dma_in, &_static_const_dma_out, dst, nbytes); + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _inputs_memcpy_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_inputs_memcpy_epoch_block_array); + } + else + { + /* proceed to next epoch block */ + } +} + +/** + * @brief performs a memory copy operation from `ninputs` inputs with a channel batch to one output (with a canonical + * format batch == channels) using stream engines `dma_in` and `dma_out` + * @param inputs list of input tensor info structures + * @param ninputs number of inputs + * @param dst destination address + */ +static void __LL_ATON_LIB_DMA_Inputs_Batched_Memcpy(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + unsigned char *dst, int dma_in, int dma_out) +{ + uint32_t nbits = inputs[0].nbits; + uint32_t in_ndims = inputs[0].ndims; + uint32_t nbytes = (nbits + 7) >> 3; + uint32_t in_fwidth = inputs[0].shape[(in_ndims - 4) + TDIM_FWIDTH]; + uint32_t in_fheight = inputs[0].shape[(in_ndims - 4) + TDIM_FHEIGHT]; + uint32_t in_batch = inputs[0].batch; + uint32_t in_nchannels = inputs[0].shape[(in_ndims - 4) + TDIM_NCHANNELS]; + uint32_t in_nkernels = inputs[0].shape[(in_ndims - 4) + TDIM_NKERNELS]; + uint32_t out_nchannels = 0; + uint32_t in_bytes_size = in_fwidth * in_fheight * in_nchannels * in_nkernels * nbytes; + int i; + + for (i = 0; i < ninputs; i++) + out_nchannels += inputs[i].shape[(in_ndims - 4) + TDIM_NCHANNELS]; + /* prepare epoch */ + + // LL_ATON_PRINTF("nbytes=%d fw=%d fh=%d inb=%d inc=%d outc=%d\n", nbytes, in_fwidth, in_fheight, in_batch, + // in_nchannels, out_nchannels); + + // memset(dst, 100, out_nchannels * nbytes * in_fwidth * in_fheight); + + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .raw = 1, + .addr_base.p = inputs[0].addr_base.p, // this must be updated on all inputs + .offset_start = inputs[0].offset_start, // this must be updated on all inputs + .offset_end = inputs[0].offset_start + in_bytes_size, // this must be updated on all inputs + .frame_tot_cnt = 1, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + }; + + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .raw = 0, + .addr_base.p = dst, // this must be updated on all inputs + .offset_start = 0, // this must be updated on all inputs + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + + .fwidth = in_fwidth, + .fheight = in_fheight, + .batch_depth = (nbytes == 4) ? (2 * in_batch) : in_batch, // this must be updated on all inputs + .batch_offset = out_nchannels * nbytes, + .frame_offset = in_batch * nbytes, // this must be updated on all inputs + + .frame_loop_cnt = in_nchannels / in_batch, // this must be updated on all inputs + .frame_tot_cnt = in_nchannels / in_batch, // this must be updated on all inputs + .loop_offset = in_fheight * in_fwidth * in_batch * nbytes, // this must be updated on all inputs + }; + + /* start epoch block sequence */ + if (ninputs > 0) + { + /* prepare epoch */ + __ll_lib_prepare_inputs_epoch(inputs, ninputs, &_dma_in, &_dma_out, dst, -1); + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _inputs_batched_memcpy_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_inputs_batched_memcpy_epoch_block_array); + } + else + { + /* proceed to next epoch block */ + } +} + +/** + * @brief performs a memory copy operation from one input to `noutputs` outputs using stream engines `dma_in` and + * `dma_out` + * @param src source address + * @param outputs list of output tensor shape structures + * @param noutputs number of outputs + */ +static void __LL_ATON_LIB_DMA_Outputs_Memcpy(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int noutputs, + int dma_in, int dma_out) +{ + /* start epoch block sequence */ + if (noutputs > 0) + { + /* prepare epoch */ + __ll_lib_prepare_outputs_epoch(outputs, noutputs, &_static_const_dma_in, &_static_const_dma_out, input); + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _outputs_memcpy_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_outputs_memcpy_epoch_block_array); + } + else + { + /* proceed to next epoch block */ + } +} + +/** + * @brief performs channel-split copy operation on an input and several outputs (both in ATON canonical format) using + * DMA + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param nr_of_outputs number of output tensors + */ +static void __LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, + unsigned int noutputs, unsigned int leading_dims, int dma_in, + int dma_out) +{ + uint32_t out_ndims = outputs[0].ndims; + LL_ATON_ASSERT(out_ndims >= 3); + uint32_t nbytes = + LL_LIB_NBYTES(outputs[0].nbits); // assuming that value is the same for all output tensors and input tensor + uint32_t out_fwidth = outputs[0].shape[(out_ndims - 4) + TDIM_ONNX_FWIDTH]; // assuming that value is the same for all + // output tensors and input tensor + uint32_t out_fheight = outputs[0].shape[(out_ndims - 4) + TDIM_ONNX_FHEIGHT]; // assuming that value is the same for + // all output tensors and input tensor + uint32_t out_nchannels = outputs[0].shape[(out_ndims - 4) + TDIM_ONNX_NCHANNELS]; + + uint32_t in_nchannels = 0; + int i; + + for (i = 0; i < noutputs; i++) + in_nchannels += outputs[i].shape[(out_ndims - 4) + 1 /* ONNX_CHANNEL_OFFSET */]; + + unsigned char nbits = (nbytes == 4) ? 16 : (nbytes * 8); // same for all output tensors and input tensor + + // LL_ATON_PRINTF("\ndma_out: addr_start=%p, addr_end=%p\n", LL_Buffer_addr_start(outputs + 0), + // LL_Buffer_addr_end(outputs + 0)); + + /* prepare epoch */ + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .raw = 1, + .addr_base.p = outputs[0].addr_base.p, // this must be updated on all outputs + .offset_start = outputs[0].offset_start, // this must be updated on all outputs + .offset_end = outputs[0].offset_end, // this must be updated on all outputs + .frame_tot_cnt = 1, + .nbits_in = nbits, + .nbits_out = nbits, + }; + + unsigned batch_depth = (nbytes == 4) ? (2 * out_nchannels) : out_nchannels; + unsigned frame_size = out_fwidth * out_fheight * batch_depth; + + if (frame_size != 1) + { + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .raw = 0, // this must be updated on all outputs + .addr_base.p = input->addr_base.p, // this must be updated on all outputs + .offset_start = input->offset_start, // this must be updated on all outputs + .nbits_in = nbits, + .nbits_out = nbits, + + .fwidth = out_fwidth, + .fheight = out_fheight, + .batch_depth = batch_depth, // this must be updated on all outputs + .batch_offset = in_nchannels * nbytes, + + .line_offset = in_nchannels * out_fwidth * nbytes, + + .frame_offset = in_nchannels * out_fheight * out_fwidth * nbytes, + + .frame_loop_cnt = 0, + .frame_tot_cnt = leading_dims, + .loop_offset = 0, + }; + + // LL_ATON_PRINTF("dma_in: frame_size=%d, nbytes=%u, in_nchannels=%u, out_nchannels=%u, src=%p, out_fwidth=%u, + // out_fheight=%u, batch_depth=%u, batch_offset=%u, line_offset=%u, frame_offset=%u, frame_tot_cnt=%u\n", + // frame_size, nbytes, in_nchannels, out_nchannels, LL_Streng_addr_start(&_dma_in), + // _dma_in.fwidth, _dma_in.fheight, _dma_in.batch_depth, _dma_in.batch_offset, _dma_in.line_offset, + // _dma_in.frame_offset, _dma_in.frame_tot_cnt); + // LL_ATON_FFLUSH(stdout); + + __ll_lib_prepare_outputs_epoch(outputs, noutputs, &_dma_in, &_dma_out, input); + } + else // frame_size == 1 + { +#if 1 + LL_ATON_ASSERT(0); // should never happen!!! +#else + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .raw = 1, // this must be updated on all outputs + .addr_base.p = src, // this must be updated on all outputs + .offset_start = 0, // this must be updated on all outputs + .offset_end = nbytes, // this must be updated on all outputs + .nbits_in = nbits, + .nbits_out = nbits, + + .frame_offset = in_nchannels * out_fheight * out_fwidth * nbytes, + + .frame_loop_cnt = 0, + .frame_tot_cnt = leading_dims, + .loop_offset = 0, + }; + + __ll_lib_prepare_outputs_epoch(outputs, noutputs, &_dma_in, &_dma_out, src); +#endif + } + + /* start epoch block sequence */ + if (noutputs > 0) + { + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _outputs_channel_split_aton_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_outputs_channel_split_aton_epoch_block_array); + } + else + { + /* proceed to next epoch block */ + } +} + +/** + * @brief performs a channel-split memory copy operation from one input (ATON canonical) to `noutputs` + * non-ATON-canonical outputs using stream engines `dma_in` and `dma_out` + * @param src source address + * @param outputs list of output tensor shape structures + * @param noutputs number of outputs + */ +static void __LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, + unsigned int noutputs, int dma_in, int dma_out) +{ + uint32_t out_ndims = outputs[0].ndims; + LL_ATON_ASSERT(out_ndims >= 3); + uint32_t nbytes = + LL_LIB_NBYTES(outputs[0].nbits); // assuming that value is the same for all output tensors and input tensor + uint32_t out_fwidth = outputs[0].shape[(out_ndims - 4) + TDIM_ONNX_FWIDTH]; // assuming that value is the same for all + // output tensors and input tensor + uint32_t out_fheight = outputs[0].shape[(out_ndims - 4) + TDIM_ONNX_FHEIGHT]; // assuming that value is the same for + // all output tensors and input tensor + uint32_t out_nchannels = outputs[0].shape[(out_ndims - 4) + TDIM_ONNX_NCHANNELS]; + + uint32_t in_nchannels = 0; + int i; + + uint16_t out_batch = outputs[0].batch; + + for (i = 0; i < noutputs; i++) + in_nchannels += outputs[i].shape[(out_ndims - 4) + 1 /* ONNX_CHANNEL_OFFSET */]; + + LL_ATON_ASSERT((input->batch == 0) || (input->batch == in_nchannels)); + LL_ATON_ASSERT((out_nchannels % out_batch) == 0); + + unsigned char nbits = (nbytes == 4) ? 16 : (nbytes * 8); // same for all output tensors and input tensor + + // LL_ATON_PRINTF("\ndma_out: addr_start=%p, addr_end=%p\n", LL_Buffer_addr_start(outputs + 0), + // LL_Buffer_addr_end(outputs + 0)); + + /* prepare epoch */ + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .raw = 1, + .addr_base.p = outputs[0].addr_base.p, // this must be updated on all outputs + .offset_start = outputs[0].offset_start, // this must be updated on all outputs + .offset_end = outputs[0].offset_end, // this must be updated on all outputs + .frame_tot_cnt = 1, + .nbits_in = nbits, + .nbits_out = nbits, + }; + + unsigned batch_depth = (nbytes == 4) ? (2 * out_batch) : out_batch; + unsigned frame_size = out_fwidth * out_fheight * batch_depth; + + if (frame_size != 1) + { + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .raw = 0, // this must be updated on all outputs + .addr_base.p = input->addr_base.p, // this must be updated on all outputs + .offset_start = input->offset_start, // this must be updated on all outputs + .nbits_in = nbits, + .nbits_out = nbits, + + .fwidth = out_fwidth, + .fheight = out_fheight, + .batch_depth = batch_depth, // this must be updated on all outputs + .batch_offset = in_nchannels * nbytes, + + .line_offset = in_nchannels * out_fwidth * nbytes, + + .frame_offset = in_nchannels * out_fheight * out_fwidth * nbytes, + + .frame_loop_cnt = 1, + .frame_tot_cnt = out_nchannels / out_batch, // this must be updated on all outputs + .loop_offset = out_batch * nbytes, // this must be updated on all outputs + }; + + // LL_ATON_PRINTF("dma_in: frame_size=%d, nbytes=%u, in_nchannels=%u, out_nchannels=%u, src=%p, out_fwidth=%u, + // out_fheight=%u, batch_depth=%u, batch_offset=%u, line_offset=%u, frame_offset=%u, frame_tot_cnt=%u\n", + // frame_size, nbytes, in_nchannels, out_nchannels, LL_Streng_addr_start(&_dma_in), + // _dma_in.fwidth, _dma_in.fheight, _dma_in.batch_depth, _dma_in.batch_offset, _dma_in.line_offset, + // _dma_in.frame_offset, _dma_in.frame_tot_cnt); + // LL_ATON_FFLUSH(stdout); + + __ll_lib_prepare_outputs_epoch(outputs, noutputs, &_dma_in, &_dma_out, input); + } + else // frame_size == 1 + { +#if 1 + LL_ATON_ASSERT(0); // should never happen!!! +#else + // TODO (as not yet adapted for this case) + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .raw = 1, // this must be updated on all outputs + .addr_base.p = src, // this must be updated on all outputs + .offset_start = 0, // this must be updated on all outputs + .offset_end = nbytes, // this must be updated on all outputs + .nbits_in = nbits, + .nbits_out = nbits, + + .frame_offset = in_nchannels * out_fheight * out_fwidth * nbytes, + + .frame_loop_cnt = 0, + .frame_tot_cnt = leading_dims, + .loop_offset = 0, + }; + + __ll_lib_prepare_outputs_epoch(outputs, noutputs, &_dma_in, &_dma_out, src); +#endif + } + + /* start epoch block sequence */ + if (noutputs > 0) + { + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _outputs_channel_split_aton_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_outputs_channel_split_batched_epoch_block_array); + } + else + { + /* proceed to next epoch block */ + } +} + +/** + * @brief performs a tensor ImageToRow transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * @param stride_h vertical stride for the sliding window + * @param stride_w horizontal stride for the sliding window + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ +int LL_ATON_LIB_DMA_ImageToRow(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + unsigned stride_h, unsigned stride_w, int dma_in, int dma_out) +{ + uint32_t in_batches = inputs[0].shape[TDIM_NKERNELS]; + uint32_t in_fwidth = inputs[0].shape[TDIM_FWIDTH]; + uint32_t in_fheight = inputs[0].shape[TDIM_FHEIGHT]; + uint32_t in_nchannels = inputs[0].shape[TDIM_NCHANNELS]; + uint32_t out_batches = output->shape[TDIM_NKERNELS]; + uint32_t out_fwidth = output->shape[TDIM_FWIDTH]; + uint32_t out_fheight = output->shape[TDIM_FHEIGHT]; + uint32_t out_nchannels = output->shape[TDIM_NCHANNELS]; + uint32_t nbits = inputs[0].nbits; + uint32_t nbits_unsigned = inputs[0].Qunsigned; + uint32_t nbytes = (nbits + 7) >> 3; + uint32_t in_bytes_size = in_fwidth * in_fheight * in_nchannels * in_batches * nbytes; + + /* +LL_ATON_PRINTF("in: b=%d w=%d g=%d c=%d\n",in_batches,in_fwidth,in_fheight,in_nchannels); +LL_ATON_PRINTF("out: b=%d w=%d g=%d c=%d ndims=%d\n",out_batches,out_fwidth,out_fheight,out_nchannels,output->ndims); + */ + + if (ninputs != 1) + __LL_LIB_ERROR(_ERR_NINPUTS, LL_ATON_INVALID_PARAM); + + if (nbits != output->nbits) + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + + if ((output->ndims < 1) || (output->ndims > 4)) + __LL_LIB_ERROR(_ERR_SHAPE_OUT, LL_ATON_INVALID_PARAM); + + if ((inputs[0].ndims < 1) || (inputs[0].ndims > 4)) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + + if (in_batches != out_batches || out_nchannels != in_nchannels * (blocksize_h * blocksize_w) || + (in_fwidth < blocksize_w) || (in_fheight < blocksize_h) || ((in_fwidth - blocksize_w) % stride_w) || + ((in_fheight - blocksize_h) % stride_h) || (out_fwidth != (((in_fwidth - blocksize_w) / stride_w) + 1)) || + (out_fheight != (((in_fheight - blocksize_h) / stride_h) + 1))) + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + + /* prepare epoch */ + /* the output DMA goes just sequential with non batched output */ + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .raw = 1, + .addr_base.i = output->addr_base.i, + .offset_start = output->offset_start, + .offset_end = output->offset_start + in_bytes_size, + .frame_tot_cnt = 1, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = nbits_unsigned, + }; + + unsigned batch_depth = (nbytes == 4) ? (2 * in_nchannels) : in_nchannels; + + /* this DMA scans the input one block at a time of size blocksize_h * blocksize_w * in_nchannels */ + if ((blocksize_w * blocksize_h * batch_depth) != 1) + { + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .addr_base.i = inputs[0].addr_base.i, + .offset_start = inputs[0].offset_start, + .offset_limit = inputs[0].offset_limit, + .raw = 0, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = nbits_unsigned, + + .fwidth = blocksize_w, + .batch_depth = batch_depth, + .batch_offset = in_nchannels * nbytes, + + .fheight = blocksize_h, + .line_offset = in_fwidth * in_nchannels * nbytes, + + .frame_loop_cnt = ((in_fwidth - blocksize_w) / stride_w) + 1, // nframes = frame_loop_cnt + .frame_offset = stride_w * in_nchannels * nbytes, + + .frame_tot_cnt = + in_batches * (((in_fheight - blocksize_h) / stride_h) + 1) * (((in_fwidth - blocksize_w) / stride_w) + 1), + .loop_offset = stride_h * in_fwidth * in_nchannels * nbytes, + }; + + __ll_lib_prepare_inputs_epoch(inputs, ninputs, &_dma_in, &_dma_out, + /* all of the rest of parameters are irrelevant to this use */ 0, 0); + } + else // blocksize_w * blocksize_h * batch_depth) == 1 + { // use raw mode + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .addr_base.i = inputs[0].addr_base.i, + .offset_start = inputs[0].offset_start, + .offset_end = inputs[0].offset_start + nbytes, + .offset_limit = inputs[0].offset_limit, + .raw = 1, + .nbits_in = (nbytes * 8), // nbytes != 4 + .nbits_out = (nbytes * 8), // nbytes != 4 + .nbits_unsigned = nbits_unsigned, + + .frame_loop_cnt = ((in_fwidth - blocksize_w) / stride_w) + 1, // nframes = frame_loop_cnt + .frame_offset = stride_w * in_nchannels * nbytes, + + .frame_tot_cnt = + in_batches * (((in_fheight - blocksize_h) / stride_h) + 1) * (((in_fwidth - blocksize_w) / stride_w) + 1), + .loop_offset = stride_h * in_fwidth * in_nchannels * nbytes, + }; + + __ll_lib_prepare_inputs_epoch(inputs, ninputs, &_dma_in, &_dma_out, + /* all of the rest of parameters are irrelevant to this use */ 0, 0); + } + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _dma_ri2ir_epoch_block_array); + + /* start epoch block sequence */ + LL_ATON_RT_Insert_LibEpochBlockArray(_dma_ri2ir_epoch_block_array); + + return LL_ATON_OK; +} + +/** + * @brief performs a tensor SpaceToDepth transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ +int LL_ATON_LIB_DMA_SpaceToDepth(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + int dma_in, int dma_out) +{ + return LL_ATON_LIB_DMA_ImageToRow(inputs, ninputs, output, blocksize_h, blocksize_w, blocksize_h, blocksize_w, dma_in, + dma_out); +} + +/** + * @brief performs a tensor RowToImage transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * @param stride_h vertical stride for the sliding window + * @param stride_w horizontal stride for the sliding window + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ +int LL_ATON_LIB_DMA_RowToImage(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + unsigned stride_h, unsigned stride_w, int dma_in, int dma_out) +{ + int in_batches = inputs[0].shape[TDIM_NKERNELS]; + int in_fwidth = inputs[0].shape[TDIM_FWIDTH]; + int in_fheight = inputs[0].shape[TDIM_FHEIGHT]; + int in_nchannels = inputs[0].shape[TDIM_NCHANNELS]; + int out_batches = output->shape[TDIM_NKERNELS]; + int out_fwidth = output->shape[TDIM_FWIDTH]; + int out_fheight = output->shape[TDIM_FHEIGHT]; + int out_nchannels = output->shape[TDIM_NCHANNELS]; + int nbits = inputs[0].nbits; + unsigned nbits_unsigned = inputs[0].Qunsigned; + int nbytes = (nbits + 7) >> 3; + uint32_t in_bytes_size = in_fwidth * in_fheight * in_nchannels * in_batches * nbytes; + + /* +LL_ATON_PRINTF("in: b=%d w=%d g=%d c=%d\n",in_batches,in_fwidth,in_fheight,in_nchannels); +LL_ATON_PRINTF("out: b=%d w=%d g=%d c=%d ndims=%d\n",out_batches,out_fwidth,out_fheight,out_nchannels,output->ndims); + */ + + if (ninputs != 1) + __LL_LIB_ERROR(_ERR_NINPUTS, LL_ATON_INVALID_PARAM); + + if (nbits != output->nbits) + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + + if ((output->ndims < 1) || (output->ndims > 4)) + __LL_LIB_ERROR(_ERR_SHAPE_OUT, LL_ATON_INVALID_PARAM); + + if ((inputs[0].ndims < 1) || (inputs[0].ndims > 4)) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + + if (in_batches != out_batches || in_nchannels != out_nchannels * (blocksize_h * blocksize_w) || + (out_fwidth < blocksize_w) || (out_fheight < blocksize_h) || ((out_fwidth - blocksize_w) % stride_w) || + ((out_fheight - blocksize_h) % stride_h) || (in_fwidth != (((out_fwidth - blocksize_w) / stride_w) + 1)) || + (in_fheight != (((out_fheight - blocksize_h) / stride_h) + 1))) + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + + /* prepare epoch */ + /* the input DMA goes just sequential with non batched input */ + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, // input + .raw = 1, + .addr_base.i = inputs[0].addr_base.i, + .offset_start = inputs[0].offset_start, + .offset_end = inputs[0].offset_start + in_bytes_size, + .offset_limit = inputs[0].offset_limit, + .frame_tot_cnt = 1, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = nbits_unsigned, + }; + + /* this DMA scans the output one block at a time of size blocksize_h * blocksize_w * out_nchannels */ + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .addr_base.i = output->addr_base.i, + .offset_start = output->offset_start, + .raw = 0, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = nbits_unsigned, + + .fwidth = blocksize_w, + .batch_depth = (nbytes == 4) ? (2 * out_nchannels) : out_nchannels, + .batch_offset = out_nchannels * nbytes, + + .fheight = blocksize_h, + .line_offset = out_fwidth * out_nchannels * nbytes, + + .frame_loop_cnt = ((out_fwidth - blocksize_w) / stride_w) + 1, // nframes = frame_loop_cnt + .frame_offset = stride_w * out_nchannels * nbytes, + + .frame_tot_cnt = + out_batches * (((out_fheight - blocksize_h) / stride_h) + 1) * (((out_fwidth - blocksize_w) / stride_w) + 1), + .loop_offset = stride_h * out_fwidth * out_nchannels * nbytes, + }; + + /* prepare epoch */ + __ll_lib_prepare_inputs_epoch(inputs, ninputs, &_dma_in, &_dma_out, + /* all of the rest of parameters are irrelevant to this use */ 0, 0); + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _dma_ri2ir_epoch_block_array); + + /* start epoch block sequence */ + LL_ATON_RT_Insert_LibEpochBlockArray(_dma_ri2ir_epoch_block_array); + + return LL_ATON_OK; +} + +/** + * @brief performs a tensor DepthToSpace transfer operation using stream engines `dma_in` and `dma_out` + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structures + * @param blocksize_h vertical dimension for the blocksize + * @param blocksize_w horizontal dimension for the blocksize + * + * @note Supports only input and output tensors in ATON canonical format + * + * @note Supports only DCR (depth-column-row) order re-arrangement + * + * @note Bit-sizes are rounded up to multiples of 8-bits + * + */ +int LL_ATON_LIB_DMA_DepthToSpace(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + int dma_in, int dma_out) +{ + return LL_ATON_LIB_DMA_RowToImage(inputs, ninputs, output, blocksize_h, blocksize_w, blocksize_h, blocksize_w, dma_in, + dma_out); +} + +int LL_ATON_LIB_DMA_Transpose(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + const uint8_t *target_pos, const uint8_t *perm_to_use, int dma_in, int dma_out) +{ + if (LL_Buffer_len(output) < __LL_DMA_MIN_BUFF_LEN) + { // not worth doing it in HW +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("===> running pure SW version of `Transpose`\n"); +#endif + + return LL_ATON_LIB_Transpose(input, input_axes_offsets, output, output_axes_offsets, perm_to_use); + } + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("===> running DMA version of `Transpose`\n"); +#endif + + // parameter checks + if (input->nbits != output->nbits) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); // TODO: this restriction might be relaxed by a more + // accurate configuration of the DMAs?!? + } + + if ((input->nbits < 8) || (input->nbits > 32)) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if (input->ndims != output->ndims) + { + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + + if ((input->ndims != 4) && (input->ndims != 3)) + { + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + + uint8_t nbytes = LL_LIB_NBYTES(input->nbits); + + /* prepare epoch */ + /* the input DMA goes just sequential with non batched input */ + LL_Streng_TensorInitTypeDef _dma_in = { + .dir = 0, + .raw = 1, + .addr_base.i = input->addr_base.i, + .offset_start = input->offset_start, + .offset_end = input->offset_end, + .offset_limit = input->offset_limit, + .frame_tot_cnt = 1, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = 0, + }; + + /* save input DMA configuration */ + __ll_lib_params_t *params = __ll_lib_get_params(); + params->g_dma_in = _dma_in; + + /* this DMA performs the optimized `Transpose` */ + switch (input->ndims) + { + case 4: + { + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .addr_base.i = output->addr_base.i, + .offset_start = output->offset_start, + .raw = 0, + .batch_depth = (nbytes == 4) ? 2 : 1, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = 0, + .fwidth = input->shape[3], + .batch_offset = output_axes_offsets[target_pos[3]], + .fheight = input->shape[2], + .line_offset = output_axes_offsets[target_pos[2]], + .frame_loop_cnt = input->shape[1], + .frame_offset = output_axes_offsets[target_pos[1]], + .loop_offset = output_axes_offsets[target_pos[0]], + .frame_tot_cnt = input->shape[0] * input->shape[1], + }; + + /* save output DMA configuration */ + params->g_dma_out = _dma_out; + } + break; + + case 3: + { + LL_Streng_TensorInitTypeDef _dma_out = { + .dir = 1, // output + .addr_base.i = output->addr_base.i, + .offset_start = output->offset_start, + .raw = 0, + .batch_depth = (nbytes == 4) ? 2 : 1, + .nbits_in = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_out = (nbytes == 4) ? 16 : (nbytes * 8), + .nbits_unsigned = 0, + .fwidth = input->shape[2], + .batch_offset = output_axes_offsets[target_pos[2]], + .fheight = input->shape[1], + .line_offset = output_axes_offsets[target_pos[1]], + .frame_loop_cnt = input->shape[0], + .frame_offset = output_axes_offsets[target_pos[0]], + .loop_offset = 0, + .frame_tot_cnt = input->shape[0], + }; + + /* save output DMA configuration */ + params->g_dma_out = _dma_out; + } + break; + + default: + LL_ATON_ASSERT(0); // can never happen + } + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _dma_transpose_epoch_block_array); + + /* schedule epoch block */ + LL_ATON_RT_Insert_LibEpochBlockArray(_dma_transpose_epoch_block_array); + + return LL_ATON_OK; +} + +#ifndef _LL_LIB_Concat_Cast_USE_ATON_HW +#define _LL_LIB_Concat_Cast_USE_ATON_HW 1 +#endif + +/** + * @brief performs a concat operation according to ONNX semantics + * @param list of input tensor info structures + * @param number of inputs + * @param output tensor info structure + * @param axis for concatenation + * @retval Error code + */ +int LL_ATON_LIB_Concat(const LL_Buffer_InfoTypeDef *inputs, unsigned int ninputs, const LL_Buffer_InfoTypeDef *output, + unsigned int axis, int dma_in, int dma_out) +{ + int i, k; + + // LL_ATON_PRINTF("Concat ------ axis=%d\n", axis); + if (ninputs == 0) + __LL_LIB_ERROR(_ERR_NINPUTS, LL_ATON_INVALID_PARAM); + + int in_ndims = inputs[0].ndims; + + if (in_ndims < 4) + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + + int in_batch = inputs[0].batch; + // int in_fwidth = inputs[0].shape[(in_ndims - 4) + TDIM_FWIDTH]; + int in_fheight = inputs[0].shape[(in_ndims - 4) + TDIM_FHEIGHT]; + int in_nchannels = inputs[0].shape[(in_ndims - 4) + TDIM_NCHANNELS]; + int out_batch = output->batch; + int out_fwidth = output->shape[(in_ndims - 4) + TDIM_FWIDTH]; + // int out_fheight = output->shape[(in_ndims - 4) + TDIM_FHEIGHT]; + int out_nchannels = output->shape[(in_ndims - 4) + TDIM_NCHANNELS]; + + int in_canonical = (in_batch == in_nchannels); + int out_canonical = (out_batch == out_nchannels); + + // convert axis from ...CHW -> ...HWC + int axis_lut[] = {TDIM_NKERNELS, TDIM_NCHANNELS, TDIM_FHEIGHT, TDIM_FWIDTH}; // 0, 3, 1, 2 +#define LUT_AXIS(x) ((x >= (in_ndims - 4)) ? (in_ndims - 4) + axis_lut[x - (in_ndims - 4)] : x) + + /* +LL_ATON_PRINTF("axis: %d\n",axis); +LL_ATON_PRINTF("in: b=%d w=%d g=%d c=%d\n",in_batches,in_fwidth,in_fheight,in_nchannels); +LL_ATON_PRINTF("out: b=%d w=%d g=%d c=%d ndims=%d\n",out_batches,out_fwidth,out_fheight,out_nchannels,output->ndims); + */ + + if (output->ndims != in_ndims) + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + + /* patch up axis to 4 dimensions */ + axis = in_ndims < 4 ? (axis + (4 - in_ndims)) : axis; + /* we can move left axis if dimensions are == 1 */ + /* this should be more efficient (larger chunks) */ + /* except if formats are batched */ + + int nbits = inputs[0].nbits; + int nbytes = (inputs[0].nbits + 7) >> 3; + + if (nbits & 0x7) + __LL_LIB_ERROR(_ERR_FRACTIONAL, LL_ATON_INVALID_PARAM); // for now can't handle fractional bytes + + int tot_size = 0; + int tot_axis_dim = 0; + int atonn_axis = LUT_AXIS(axis); + + for (i = 0; i < ninputs; i++) + { + tot_size += LL_Buffer_len(inputs + i); + if (!(((inputs[i].shape[(in_ndims - 4) + TDIM_NCHANNELS] == inputs[i].batch) && in_canonical) || + (in_batch == inputs[i].batch))) + { + // LL_ATON_PRINTF("name=%s inb=%d inb(i)=%d chan(i)=%d\n", inputs[i].name, in_batch, inputs[i].batch, + // inputs[i].shape[TDIM_NCHANNELS]); + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + } + if (inputs[i].ndims != in_ndims) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + if (inputs[i].nbits != nbits) + __LL_LIB_ERROR(_ERR_NBITS_IN, LL_ATON_INVALID_PARAM); + + tot_axis_dim += inputs[i].shape[atonn_axis]; + + for (k = 0; k < in_ndims; k++) + { + if (k != atonn_axis && inputs[0].shape[k] != inputs[i].shape[k]) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + } + } + + for (k = 0; k < in_ndims; k++) + { + if (k != atonn_axis && output->shape[k] != inputs[0].shape[k]) + { + // LL_ATON_PRINTF("k=%d axis=%d %d != %d\n", k, atonn_axis, output->shape[k], inputs[0].shape[k]); + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + } + + if (output->shape[atonn_axis] != tot_axis_dim) + __LL_LIB_ERROR(_ERR_AXIS, LL_ATON_INVALID_PARAM); + + // LL_ATON_PRINTF("tot: size=%d b=%d w=%d g=%d c=%d\n",tot_size,tot_batches,tot_fwidth,tot_fheight,tot_nchannels); + + if (nbits != output->nbits) // perhaps this could be relaxed later on FIXME !!! + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + + if (tot_size > LL_Buffer_len(output)) + { + // LL_ATON_PRINTF("tot_size=%d out size=%ld\n", tot_size, LL_Buffer_len(output)); + __LL_LIB_ERROR(_ERR_BUFFER, LL_ATON_INVALID_PARAM); + } + +#if 1 // 0/1 + int axis_is_leftmost = 1; + + for (i = 0; i < axis; i++) + axis_is_leftmost &= (output->shape[i] == 1); + + // 0-> >= 3 anything + // 2-> >= 3 H = 1 + // 1->2 C + // 3 -> 0 W + + if (nbits > 24) // assumes that inputs & output have the same number of bits (`nbits`), see above `__LL_LIB_ERROR`s + axis_is_leftmost = 0; + + if (axis_is_leftmost) + { + switch ((in_ndims - 1) - axis) // count from right CHW, W=0,H=1,C=2, anything else >= 3 + { + default: // any dimension left of onnx channels (they should all be == 1) + if (in_batch != out_batch) + { // it's unclear for now what it means to concatenate if different batches or non canonical + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } +#if _LL_LIB_Concat_Cast_USE_ATON_HW + __LL_ATON_LIB_DMA_Inputs_Memcpy(inputs, ninputs, LL_Buffer_addr_start(output), -1, dma_in, dma_out); +#else // !_LL_LIB_Concat_Cast_USE_ATON_HW + { + /* case when concatenation is on ONNX dim before channels or height */ + unsigned char *start = LL_Buffer_addr_start(output); + for (i = 0; i < ninputs; i++) + { + // LL_ATON_PRINTF("in[%d]\n",i); + memcpy((void *)start, (void *)LL_Buffer_addr_start(inputs + i), LL_Buffer_len(inputs + i)); + start += LL_Buffer_len(inputs + i); + } + } +#endif // !_LL_LIB_Concat_Cast_USE_ATON_HW + return LL_ATON_OK; + case 2: // Channels + { + if (in_batch == out_batch) + { + __LL_ATON_LIB_DMA_Inputs_Memcpy(inputs, ninputs, LL_Buffer_addr_start(output), -1, dma_in, dma_out); + } + else + { + __LL_ATON_LIB_DMA_Inputs_Batched_Memcpy(inputs, ninputs, LL_Buffer_addr_start(output), dma_in, dma_out); + } + } + return LL_ATON_OK; + case 0: // Width + { + if (in_batch != out_batch) + { // it's unclear for now what it means to concatenate if different batches or non canonical + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + // we need to scan raster scan input tensors and copy each line data onto output + unsigned int out_pix_size = nbytes * out_nchannels; + unsigned int out_line_size = out_pix_size * out_fwidth; + unsigned char *out_start = LL_Buffer_addr_start(output); + +#if _LL_LIB_Concat_Cast_USE_ATON_HW + { + unsigned int pix_size = nbytes * inputs[0].shape[(in_ndims - 4) + TDIM_NCHANNELS]; + unsigned int line_size = pix_size * inputs[0].shape[(in_ndims - 4) + TDIM_FWIDTH]; + + __ll_lib_params_t *params = __ll_lib_get_params(); + params->special.concat_case3.outer_idx = 0; + params->special.concat_case3.in_fheight = in_fheight; + params->special.concat_case3.nbytes = nbytes; + params->special.concat_case3.out_line_size = out_line_size; + params->special.concat_case3.in_curr = LL_Buffer_addr_start((LL_LIB_TensorInfo_TypeDef *)params->g_tensors); + + /* start epoch block sequence */ + if ((ninputs > 0) && (in_fheight > 0)) + { + /* prepare epoch */ + __ll_lib_prepare_inputs_epoch(inputs, ninputs, &_static_const_dma_in, &_static_const_dma_out, + (void *)out_start, line_size); + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _concat_case3_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_concat_case3_epoch_block_array); + } + else + { + /* proceed to next epoch block */ + } + } +#else // !_LL_LIB_Concat_Cast_USE_ATON_HW + { + for (i = 0; i < ninputs; i++) + { + // LL_ATON_PRINTF("in[%d]\n",i); + unsigned int pix_size = nbytes * inputs[i].nchannels; + unsigned int line_size = pix_size * inputs[i].fwidth; + unsigned char *out_curr = out_start; + unsigned char *in_curr = LL_Buffer_addr_start(inputs + i); + unsigned int row; + for (row = 0; row < in_fheight; row++) + { + memcpy((void *)out_curr, (void *)(in_curr), line_size); + out_curr += out_line_size; + in_curr += line_size; + } + out_start += line_size; + } + } +#endif //_!LL_LIB_USE_ATON_HW + } + return LL_ATON_OK; + } + } +#endif // 0/1 + /* python example + stop = Z.size + jump = 1 + for i in range(axis+1,len(X.shape)): + jump = jump*X.shape[i] + jump = jump*Z1.shape[axis] + + start = 0 + for i in range(0,len(Ins)): + W = Ins[i] + if (verbose): print("W:",W) + copy_val = 1 + for k in range(axis+1,len(Ins_orig[i].shape)): + copy_val = copy_val*Ins_orig[i].shape[k] + copy_val = copy_val*Ins_orig[i].shape[axis] + src = 0 + for dst in range(start,stop,jump): + if (verbose): print("start:",start) + if (verbose): print("Z tmp:",Z[dst:dst+copy_val]) + if (verbose): print(Z[dst:dst+copy_val].shape) + if (verbose): print("W tmp:",W[src:src+copy_val]) + if (verbose): print(W[src:src+copy_val].shape) + Z[dst:dst+copy_val] = W[src:src+copy_val] + src = src + copy_val + start = start + copy_val + */ + if (in_canonical == 0) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + if (out_canonical == 0) + __LL_LIB_ERROR(_ERR_SHAPE_OUT, LL_ATON_INVALID_PARAM); +#if 0 + // it's unclear for now what it means to concatenate if different batches or non canonical + if (in_batch != out_batch) + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); +#endif + + uint32_t start = 0; + // convert axis from ...CHW -> ...HWC + // LL_ATON_PRINTF("axis =%d\n", axis); + // LL_ATON_PRINTF("atonn axis=%d\n", atonn_axis); + + uint32_t stop = tot_size; + uint32_t jump_base = 1; + for (i = atonn_axis + 1; i < output->ndims; i++) + jump_base *= output->shape[i]; + jump_base *= nbytes; + uint32_t jump = jump_base * output->shape[atonn_axis]; + // LL_ATON_PRINTF("jump_base=%d, jump=%d\n", jump_base, jump); + + for (i = 0; i < ninputs; i++) + { + uint32_t copy_val = inputs[i].shape[atonn_axis] * jump_base; + // LL_ATON_PRINTF("i=%d copy_val=%d\n", i, copy_val); + + int dst; + int src = 0; + for (dst = start; dst < stop; dst += jump, src += copy_val) + { + // LL_ATON_PRINTF("i =%d dst = %d src = %d\n", i, dst, src); + memcpy(LL_Buffer_addr_start(output) + dst, LL_Buffer_addr_start(inputs + i) + src, copy_val); + } + start += copy_val; + } + + return LL_ATON_OK; +} + +/* replace these with ARM ISA instructions and assembly intrinsics */ + +static int floating_to_Q(float f, int Qm, int Qn) +{ + float tmp; + if (Qn >= 0) + tmp = (f * ((int)1 << Qn) + (f > (float)0 ? (float)0.5 : (float)-0.5)); + if (Qn < 0) + tmp = (f * (float)1 / ((int)1 << -Qn)); + if (tmp > (float)(((int)1 << (Qm + Qn)) - 1)) + tmp = (float)(((int)1 << (Qm + Qn)) - 1); + if (tmp < -(float)((int)1 << (Qm + Qn))) + tmp = -(float)((int)1 << (Qm + Qn)); + return (int)tmp; +} + +static float Q_to_floating(int i, int Qm, int Qn) +{ + if (Qn >= 0) + return ((float)i / (float)((int)1 << Qn)); + if (Qn < 0) + return ((float)i * (float)((int)1 << -Qn)); + return 0.f; +} + +static int floating_to_scale_offset(float f, int Qm, int Qn, float scale, int offset) +{ + float fval = ((f / scale) + offset); + return floating_to_Q(fval, Qm, Qn); +} + +static float scale_offset_to_floating(int f, int Qm, int Qn, float scale, int offset) +{ + float fval = Q_to_floating(f, Qm, Qn); + float val = (fval - offset) * scale; + return val; +} + +static int Q_to_scale_offset(int f, int Qm_in, int Qn_in, int Qm_out, int Qn_out, float scale, int offset) +{ + float fval = Q_to_floating(f, Qm_in, Qn_in); + return floating_to_scale_offset(fval, Qm_out, Qn_out, scale, offset); +} + +static int scale_offset_to_Q(int f, int Qm_in, int Qn_in, float scale, int offset, int Qm_out, int Qn_out) +{ + float fval = scale_offset_to_floating(f, Qm_in, Qn_in, scale, offset); + return floating_to_Q(fval, Qm_out, Qn_out); +} + +static void dtype_convert_to_QMN(int *dtype, int *Qm, int *Qn, int nbits) +{ + switch (*dtype) + { + // case TENSORINFO_DATATYPE_FLOAT: already taken care of above + case DataType_UINT8: + case DataType_INT8: + case DataType_UINT16: + case DataType_INT16: + case DataType_BOOL: + { + *dtype = DataType_FXP; + *Qm = nbits; + *Qn = 0; + break; + } + // for the following we don't support casting yet FIXME !!! + case DataType_INT32: + case DataType_DOUBLE: + case DataType_UINT32: + case DataType_FLOAT16: + case DataType_BFLOAT16: + case DataType_INT64: + case DataType_UINT64: + case DataType_COMPLEX64: + case DataType_COMPLEX128: + case DataType_UNDEFINED: + case DataType_STRING: + // case TENSORINFO_DATATYPE_QMN=100, // ATONN specific + default:; + } +} + +/** + * @brief performs a cast operation to/from Qmn and float + * @param input tensor info structure + * @param output tensor info structure + * @retval Error code + */ +int LL_ATON_LIB_Cast(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, int dma_in, + int dma_out) +{ + int Qm_in = input->Qm; + int Qm_out = output->Qm; + int Qn_in = input->Qn; + int Qn_out = output->Qn; + int Qunsigned_in = input->Qunsigned; + int Qunsigned_out = output->Qunsigned; + int dtype_in = input->type; + int dtype_out = output->type; + int nbits_in = input->nbits; + int nbits_out = output->nbits; + int in_elements = LL_LIB_TENSOR_ELEMENTS(input); + int out_elements = LL_LIB_TENSOR_ELEMENTS(output); + int in_bit_size = (input->nbits == 0 ? sizeof(float) * 8 : input->nbits); + int out_bit_size = (output->nbits == 0 ? sizeof(float) * 8 : output->nbits); + int in_byte_size = (in_bit_size * in_elements + 7) >> 3; + int out_byte_size = (out_bit_size * out_elements + 7) >> 3; + int in_scaleoffset = (input->scale != NULL); + int out_scaleoffset = (output->scale != NULL); + float in_scale = in_scaleoffset ? input->scale[0] : 0; + int8_t in_offset = in_scaleoffset ? input->offset[0] : 0; + float out_scale = out_scaleoffset ? output->scale[0] : 0; + int8_t out_offset = out_scaleoffset ? output->offset[0] : 0; + + // LL_ATON_PRINTF("in: type=%d Qm=%d Qn=%d nb=%d\n",dtype_in,Qm_in,Qn_in,nbits_in); + // LL_ATON_PRINTF("out: type=%d Qm=%d Qn=%d nb=%d\n",dtype_out,Qm_out,Qn_out,nbits_out); + // we convert integer types to QMN to use the same (inefficient) code + dtype_convert_to_QMN(&dtype_in, &Qm_in, &Qn_in, nbits_in); + dtype_convert_to_QMN(&dtype_out, &Qm_out, &Qn_out, nbits_out); + // LL_ATON_PRINTF("after:\n"); + // LL_ATON_PRINTF("in: type=%d Qm=%d Qn=%d nb=%d\n",dtype_in,Qm_in,Qn_in,nbits_in); + // LL_ATON_PRINTF("out: type=%d Qm=%d Qn=%d nb=%d\n",dtype_out,Qm_out,Qn_out,nbits_out); + + if (in_elements != out_elements) + __LL_LIB_ERROR(_ERR_BUFFER, LL_ATON_INVALID_PARAM); + + if (in_byte_size > LL_Buffer_len(input)) + __LL_LIB_ERROR(_ERR_BUFFER_IN, LL_ATON_INVALID_PARAM); + + if (out_byte_size > LL_Buffer_len(output)) + __LL_LIB_ERROR(_ERR_BUFFER_OUT, LL_ATON_INVALID_PARAM); + + if (input->per_channel || output->per_channel) + __LL_LIB_ERROR(_ERR_BUFFER_OUT, LL_ATON_INVALID_PARAM); + + if (dtype_in == dtype_out && + (dtype_in != DataType_FXP || + ((Qm_in == Qm_out) && (Qn_in == Qn_out) && + (Qunsigned_in == Qunsigned_out)))) // nothing to do here except perhaps copying the input into the output + { + if (LL_Buffer_addr_start(input) != LL_Buffer_addr_start(output)) + { + // LL_ATON_PRINTF("Cast: Just a memcpy\n"); +#if _LL_LIB_Concat_Cast_USE_ATON_HW + __LL_ATON_LIB_DMA_Inputs_Memcpy(input, 1, (void *)LL_Buffer_addr_start(output), in_byte_size, dma_in, dma_out); +#else // !_LL_LIB_Concat_Cast_USE_ATON_HW + memcpy((void *)LL_Buffer_addr_start(output), (void *)LL_Buffer_addr_start(input), in_byte_size); +#endif // !_LL_LIB_Concat_Cast_USE_ATON_HW + } + // else LL_ATON_PRINTF("Cast: nothing to do\n"); + return LL_ATON_OK; + } + + if (dtype_in == DataType_FXP && dtype_out == DataType_FLOAT) + { // from to Qmn and/or scale/offset to float + int i; + /* going backward to prevent input clobbering if input buffer=output buffer */ + switch (input->nbits) + { + case 8: + { + float *out = (float *)LL_Buffer_addr_end(output) - 1; + int8_t *in = (int8_t *)LL_Buffer_addr_end(input) - 1; + // LL_ATON_PRINTF("q2f nbits=%d 8: out=%p in=%p in_el=%d\n", input->nbits, out, in, in_elements); + for (i = 0; i < in_elements; i++) + { + int t = (int)*in; + float f = in_scaleoffset ? scale_offset_to_floating(t, Qm_in, Qn_in, in_scale, in_offset) + : Q_to_floating(t, Qm_in, Qn_in); + // LL_ATON_PRINTF("i=%d f=%0.2f t=%d out=%p in=%p\n", i, f, t, out, in); + *out-- = f; + --in; + } + } + break; + case 16: + { + float *out = (float *)LL_Buffer_addr_end(output) - 1; + int16_t *in = (int16_t *)LL_Buffer_addr_end(input) - 1; + // LL_ATON_PRINTF("q2f nbits=%d 16: out=%p in=%p in_el=%d\n", input->nbits, out, in, in_elements); + for (i = 0; i < in_elements; i++) + { + int t = (int)*in; + float f = in_scaleoffset ? scale_offset_to_floating(t, Qm_in, Qn_in, in_scale, in_offset) + : Q_to_floating(t, Qm_in, Qn_in); + // LL_ATON_PRINTF("i=%d f=%0.2f t=%d \n", i, f, t); + *out-- = f; + --in; + } + } + break; + default: + { + int nbits = input->nbits; + int bitcnt = in_bit_size * (in_elements - 1); + float *out = (float *)LL_Buffer_addr_end(output) - 1; + uint32_t *in = (uint32_t *)LL_Buffer_addr_start(input); + // LL_ATON_PRINTF("q2f nbits=%d def: out=%p in=%p in_el=%d\n", input->nbits, out, in, in_elements); + for (i = 0; i < in_elements; i++) + { + int t = LL_ATON_getbits(in, bitcnt, nbits); + float f = in_scaleoffset ? scale_offset_to_floating(t, Qm_in, Qn_in, in_scale, in_offset) + : Q_to_floating(t, Qm_in, Qn_in); + // LL_ATON_PRINTF("i=%d f=%0.2f t=%d \n", i, f, t); + *out-- = f; + bitcnt -= nbits; + } + } + } + } + else if (dtype_in == DataType_FLOAT && dtype_out == DataType_FXP) + { // from to float to Qmn and/or scale offset + int i; + /* going forward to prevent input clobbering if input buffer=output buffer */ + switch (output->nbits) + { + case 8: + { + int8_t *out = (int8_t *)LL_Buffer_addr_start(output); + float *in = (float *)LL_Buffer_addr_start(input); + // LL_ATON_PRINTF("f2q 8: nbits=%d out=%p in=%p in_el=%d\n", output->nbits, out, in, in_elements); + for (i = 0; i < in_elements; i++) + { + float f = *in; + int t = out_scaleoffset ? floating_to_scale_offset(f, Qm_out, Qn_out, out_scale, out_offset) + : floating_to_Q(f, Qm_out, Qn_out); + // LL_ATON_PRINTF("i=%d f=%0.2f t=%d \n", i, f, t); + *out++ = (int8_t)t; + ++in; + } + } + break; + case 16: + { + int16_t *out = (int16_t *)LL_Buffer_addr_start(output); + float *in = (float *)LL_Buffer_addr_start(input); + // LL_ATON_PRINTF("f2q 16: nbits=%d out=%p in=%p in_el=%d\n", output->nbits, out, in, in_elements); + for (i = 0; i < in_elements; i++) + { + float f = *in; + int t = out_scaleoffset ? floating_to_scale_offset(f, Qm_out, Qn_out, out_scale, out_offset) + : floating_to_Q(f, Qm_out, Qn_out); + // LL_ATON_PRINTF("i=%d f=%0.2f t=%d \n", i, f, t); + *out++ = (int16_t)t; + ++in; + } + } + break; + default: + { + int nbits = input->nbits; + int bitcnt = 0; + uint32_t *out = (uint32_t *)LL_Buffer_addr_start(output); + float *in = (float *)LL_Buffer_addr_start(input); + // LL_ATON_PRINTF("f2q def: nbits=%d out=%p in=%p in_el=%d\n", output->nbits, out, in, in_elements); + for (i = 0; i < in_elements; i++) + { + float f = *in; + int t = out_scaleoffset ? floating_to_scale_offset(f, Qm_out, Qn_out, out_scale, out_offset) + : floating_to_Q(f, Qm_out, Qn_out); + // LL_ATON_PRINTF("i=%d f=%0.2f t=%d \n", i, f, t); + LL_ATON_setbits(out, bitcnt, nbits, t); + bitcnt += nbits; + } + } + } + } + else + { + // the following code is very inefficient for integer types, specific code should be implemented for those FIXME !!! + + if (dtype_in == DataType_FXP && dtype_out == DataType_FXP) + { // from to Qmn to Qmn assumes max in/out bits = 16 + int fwd = (nbits_in >= nbits_out); // forward + int in_bitsinc = fwd ? nbits_in : -nbits_in; + int out_bitsinc = fwd ? nbits_out : -nbits_out; + int in_bitcnt = fwd ? 0 : in_bit_size * (in_elements - 1); + int out_bitcnt = fwd ? 0 : out_bit_size * (out_elements - 1); + uint32_t *in = (uint32_t *)LL_Buffer_addr_start(input); + uint32_t *out = (uint32_t *)LL_Buffer_addr_start(output); + uint32_t tmask = (~(-1 << nbits_out)); // create a mask with output precision + int i; + for (i = 0; i < in_elements; i++) + { + int t = LL_ATON_getbits(in, in_bitcnt, nbits_in); // note t is sign extended to int + int tM = 0; + if (!in_scaleoffset && !out_scaleoffset) + tM = (Qn_out >= Qn_in ? (t << (Qn_out - Qn_in)) : (t << (Qn_in - Qn_out))); // align to output mantissa + if (in_scaleoffset && !out_scaleoffset) + tM = scale_offset_to_Q(t, Qm_in, Qn_in, in_scale, in_offset, Qm_out, Qn_out); + if (!in_scaleoffset && out_scaleoffset) + tM = Q_to_scale_offset(t, Qm_in, Qn_in, Qm_out, Qn_out, out_scale, out_offset); + if (in_scaleoffset && out_scaleoffset) + { + // very inefficient, FIXME + float fval = in_scaleoffset ? scale_offset_to_floating(t, Qm_in, Qn_in, in_scale, in_offset) : t; + tM = out_scaleoffset ? floating_to_scale_offset(fval, Qm_out, Qn_out, out_scale, out_offset) : (int)fval; + } + // extract bits least significant guard bits (if Qm_out < Qm_in) and most significant mantissa + int tout = (tM & tmask); + LL_ATON_setbits(out, out_bitcnt, nbits_out, tout); + in_bitcnt += in_bitsinc; + out_bitcnt += out_bitsinc; + } + } + else + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + return LL_ATON_OK; +} + +/** + * @brief performs a float Softmax (oonx opset >=13) operation on float inputs and output operands according to ONNX + * semantics + * @brief Softmax(input, axis) = Exp(input) / ReduceSum(Exp(input), axis=axis, keepdims=1) + * @param input tensor info structure + * @param output tensor info structure + * @param axis for coalescing of shape into a 2D matrix + * @retval Error code + */ +static int LL_ATON_LIB_Softmax_float(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, + unsigned int axis) +{ + // int in_batches = input->shape[TDIM_NKERNELS]; + // int in_fwidth = input->shape[TDIM_FWIDTH]; + // int in_fheight = input->shape[TDIM_FHEIGHT]; + // int in_nchannels = input->shape[TDIM_NCHANNELS]; + float *exps = (float *)LL_Buffer_addr_start(output + 1); + LL_ATON_ASSERT(LL_Buffer_len(output + 1) >= input->shape[axis] * 4); + + int b, o, hw; + int outer_elem = 1, inner_elem = 1; + int axis_elem = input->shape[axis]; + + for (int i = 0; i < axis; i++) + outer_elem *= input->shape[i]; + for (int i = axis + 1; i < input->ndims; i++) + inner_elem *= input->shape[i]; + + // LL_ATON_PRINTF("outer_elem=%d inner_eleme=%d axis_elem=%d\n", outer_elem, inner_elem, axis_elem); + + for (b = 0; b < outer_elem; b++) + { + int stride = b * inner_elem * axis_elem; + float *in = (float *)LL_Buffer_addr_start(input) + stride; + float *out = (float *)LL_Buffer_addr_start(output) + stride; + + for (hw = 0; hw < inner_elem; hw++) + { + float exp_sum = 0.f; + // compute max + float maxf = in[0]; + for (o = 0; o < axis_elem * inner_elem; o += inner_elem) + maxf = (maxf < in[o] ? in[o] : maxf); + // compute sum of exps + int oi = 0; + for (o = 0; o < axis_elem * inner_elem; o += inner_elem, oi++) + { + float f = expf(in[o] - maxf); + exps[oi] = f; + exp_sum += f; + } + exp_sum = 1.0f / exp_sum; + // exp_sum = maxf + log(exp_sum); + // normalize + oi = 0; + for (o = 0; o < axis_elem * inner_elem; o += inner_elem, oi++) + { + // out[o] = exp(in[o] - exp_sum); + out[o] = exps[oi] * exp_sum; + // LL_ATON_PRINTF("%g %x", out[o],out+o); + } + // in += axis_elem * inner_elem; + // out += axis_elem * inner_elem; + in++; + out++; + } + } + + return LL_ATON_OK; +} + +/** + * @brief performs an INT8 (scale/offset) Softmax (oonx opset >=13) operation inputs and output operands according to + * ONNX semantics + * @brief Softmax(input, axis) = Exp(input) / ReduceSum(Exp(input), axis=axis, keepdims=1) + * @param input tensor info structure + * @param output tensor info structure + * @param axis for coalescing of shape into a 2D matrix + * @retval Error code + */ +static int LL_ATON_LIB_Softmax_INT8(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, + unsigned int axis) +{ + int b, o, hw; + + int outer_elem = 1, inner_elem = 1; + int axis_elem = input->shape[axis]; + + for (int i = 0; i < axis; i++) + outer_elem *= input->shape[i]; + for (int i = axis + 1; i < input->ndims; i++) + inner_elem *= input->shape[i]; + + double scalein = (double)input->scale[0]; + float scaleout = output->scale[0]; + int off = output->offset[0]; + float *exps = (float *)LL_Buffer_addr_start(output + 1); + LL_ATON_ASSERT(LL_Buffer_len(output + 1) >= 512 * 4); + + for (b = -256; b <= 255; b++) + { + float f; + f = exp(b * scalein); +#if 0 // is this necessary ? + if (isnanf(f) || isinff(f)) { + f = b < 0 ? 0 : (b > 0 ? FLT_MAX : b); + } +#endif + exps[b + 256] = f; // encoding 0:127 -> 0:127 and -128:-1 -> 128-255 to save one addition later on + // LL_ATON_PRINTF("b=%d f=%g\n", b + 256, f); + } + + for (b = 0; b < outer_elem; b++) + { + int stride = b * inner_elem * axis_elem; + int8_t *in = (int8_t *)LL_Buffer_addr_start(input) + stride; + int8_t *out = (int8_t *)LL_Buffer_addr_start(output) + stride; + + for (hw = 0; hw < inner_elem; hw++) + { + float exp_sum = 0.f; + + int maxb = -128; + for (o = 0; o < axis_elem * inner_elem; o += inner_elem) + maxb = (maxb < in[o] ? in[o] : maxb); + maxb -= 256; + // LL_ATON_PRINTF("maxb = %d\n", maxb); + + for (o = 0; o < axis_elem * inner_elem; o += inner_elem) + { + exp_sum += exps[in[o] - maxb]; + // LL_ATON_PRINTF("in[o]=%d idx=%d val=%g exp_sum=%g\n", in[o], in[o] - maxb + 256, exps[in[o] - maxb + 256], + // exp_sum); + } + // LL_ATON_PRINTF("exp_sum=%g\n", exp_sum); + + exp_sum *= scaleout; + float inv_exp_sum = 1.0f / exp_sum; + + for (o = 0; o < axis_elem * inner_elem; o += inner_elem) + { + float t = exps[in[o] - maxb]; + t = (t * inv_exp_sum + off); + int ti = (t > 0 ? (int)(t + 0.5f) : (int)(t - 0.5f)); + ti = (t > 127 ? 127 : (t < -128 ? -128 : ti)); + out[o] = (int8_t)ti; + // LL_ATON_PRINTF("%g %x", out[o],out+o); + } + in++; + out++; + } + } + + return LL_ATON_OK; +} +/** + * @brief performs a float Softmax (oonx opset < 13) operation on float inputs and output operands according to ONNX + * semantics + * @brief Softmax(input, axis) = Exp(input) / ReduceSum(Exp(input), axis=axis, keepdims=1) with input tensor coerced to + * 2D by collapsing dimensions before and after axis + * @param input tensor info structure + * @param output tensor info structure + * @param axis for coalescing of shape into a 2D matrix + * @retval Error code + */ +static int LL_ATON_LIB_Softmax_float_legacy(const LL_LIB_TensorInfo_TypeDef *input, + const LL_LIB_TensorInfo_TypeDef *output, unsigned int axis) +{ + // this function must assume shape to be described as an BCHW for the purpose of computing the softmax + // while actual memory storage is BHWC + // note that ndim MUST be always >= 4 when invoking the function (for dims < 4 must be adding extra dimensions = 1) + int start_dim = input->ndims - 4; + // int in_batches = input->shape[start_dim + TDIM_NKERNELS]; + int in_fwidth = input->shape[start_dim + TDIM_FWIDTH]; + int in_fheight = input->shape[start_dim + TDIM_FHEIGHT]; + int in_nchannels = input->shape[start_dim + TDIM_NCHANNELS]; + + int b, o, left; + int outer_elem = 1, inner_elem = 1, left_elem = 1; + int dim_lut[3] = {1, 2, 0}; // HWC -> CHW (1,2,0) + + int alternate_axis = -1; + if (axis > start_dim) + alternate_axis = 1 + dim_lut[(axis - start_dim - 1)]; + // alternate_axis = 1 C inn = H*W*C, left = 1 + // alternate_axis = 2 H inn = H*W, left = C + // alternate_axis = 3 W inn = W, left = C + switch (alternate_axis) + { + case 1: + inner_elem = in_nchannels * in_fheight * in_fwidth; + left_elem = 1; + break; + case 2: + inner_elem = in_fheight * in_fwidth; + left_elem = in_nchannels; + break; + case 3: + inner_elem = in_fwidth; + left_elem = in_nchannels; + break; + default: + for (int i = axis; i < input->ndims; i++) + inner_elem *= input->shape[i]; + } + + // LL_ATON_PRINTF("start_dim=%d axis=%d altern_axis=%d\n", start_dim, axis, alternate_axis); + + for (int i = 0; i < input->ndims; i++) + outer_elem *= input->shape[i]; + outer_elem /= inner_elem * left_elem; + + // LL_ATON_PRINTF("inner elem=%d outer_elem=%d left_elem=%d\n", inner_elem, outer_elem, left_elem); + + for (left = 0; left < left_elem; left++) + for (b = 0; b < outer_elem; b++) + { + int stride = b * inner_elem * left_elem + left; + float *in = (float *)LL_Buffer_addr_start(input) + stride; + float *out = (float *)LL_Buffer_addr_start(output) + stride; + + float exp_sum = 0.f; + // compute max + float maxf = in[0]; + for (o = 0; o < left_elem * inner_elem; o += left_elem) + { + // LL_ATON_PRINTF("in: %g %p\n", in[o], (in + o)); + maxf = (maxf < in[o] ? in[o] : maxf); + } + // LL_ATON_PRINTF("maxf=%g\n", maxf); + // compute sum of exps + for (o = 0; o < left_elem * inner_elem; o += left_elem) + { + float f = expf(in[o] - maxf); + exp_sum += f; + } + // LL_ATON_PRINTF("exp_sum=%g\n", exp_sum); + exp_sum = maxf + logf(exp_sum); + // LL_ATON_PRINTF("exp_sum=%g\n", exp_sum); + // normalize + for (o = 0; o < left_elem * inner_elem; o += left_elem) + { + out[o] = expf(in[o] - exp_sum); + // LL_ATON_PRINTF("out:%g %g %p\n", in[o], out[o], (out + o)); + } + in += left_elem; + out += left_elem; + } + + return LL_ATON_OK; +} + +/** + * @brief performs an INT8 (scale/offset) Softmax (oonx opset >=13) operation inputs and output operands according to + * ONNX semantics + * @brief Softmax(input, axis) = Exp(input) / ReduceSum(Exp(input), axis=axis, keepdims=1) with input tensor coerced to + * 2D by collapsing dimensions before and after axis + * @param input tensor info structure + * @param output tensor info structure + * @param axis for coalescing of shape into a 2D matrix + * @retval Error code + */ +static int LL_ATON_LIB_Softmax_INT8_legacy(const LL_LIB_TensorInfo_TypeDef *input, + const LL_LIB_TensorInfo_TypeDef *output, unsigned int axis) +{ + int start_dim = input->ndims - 4; + int in_fwidth = input->shape[start_dim + TDIM_FWIDTH]; + int in_fheight = input->shape[start_dim + TDIM_FHEIGHT]; + int in_nchannels = input->shape[start_dim + TDIM_NCHANNELS]; + + int b, o, left; + int outer_elem = 1, inner_elem = 1, left_elem = 1; + int dim_lut[3] = {1, 2, 0}; + + int alternate_axis = -1; + if (axis > start_dim) + alternate_axis = 1 + dim_lut[(axis - start_dim - 1)]; + // alternate_axis = 1 C inn = H*W*C, left = 1 + // alternate_axis = 2 H inn = H*W, left = C + // alternate_axis = 3 W inn = W, left = C + switch (alternate_axis) + { + case 1: + inner_elem = in_nchannels * in_fheight * in_fwidth; + left_elem = 1; + break; + case 2: + inner_elem = in_fheight * in_fwidth; + left_elem = in_nchannels; + break; + case 3: + inner_elem = in_fwidth; + left_elem = in_nchannels; + break; + default: + for (int i = axis; i < input->ndims; i++) + inner_elem *= input->shape[i]; + } + + // LL_ATON_PRINTF("start_dim=%d axis=%d altern_axis=%d\n", start_dim, axis, alternate_axis); + + for (int i = 0; i < input->ndims; i++) + outer_elem *= input->shape[i]; + outer_elem /= inner_elem * left_elem; + + // LL_ATON_PRINTF("inner elem=%d outer_elem=%d left_elem=%d\n", inner_elem, outer_elem, left_elem); + + double scalein = (double)input->scale[0]; + float scaleout = output->scale[0]; + int off = output->offset[0]; + float *exps = (float *)LL_Buffer_addr_start(output + 1); + LL_ATON_ASSERT(LL_Buffer_len(output + 1) >= 512 * 4); + + for (b = -256; b <= 255; b++) + { + float f; + f = exp(b * scalein); +#if 0 // is this necessary ? + if (isnanf(f) || isinff(f)) { + f = b < 0 ? 0 : (b > 0 ? FLT_MAX : b); + } +#endif + exps[b + 256] = f; // encoding 0:127 -> 0:127 and -128:-1 -> 128-255 to save one addition later on + // LL_ATON_PRINTF("b=%d f=%g\n", b + 256, f); + } + + for (left = 0; left < left_elem; left++) + for (b = 0; b < outer_elem; b++) + { + int stride = b * inner_elem * left_elem + left; + int8_t *in = (int8_t *)LL_Buffer_addr_start(input) + stride; + int8_t *out = (int8_t *)LL_Buffer_addr_start(output) + stride; + + float exp_sum = 0.f; + + int maxb = -128; + for (o = 0; o < left_elem * inner_elem; o += left_elem) + maxb = (maxb < in[o] ? in[o] : maxb); + maxb -= 256; + // LL_ATON_PRINTF("maxb = %d\n", maxb); + + for (o = 0; o < left_elem * inner_elem; o += left_elem) + { + exp_sum += exps[in[o] - maxb]; + // LL_ATON_PRINTF("in[o]=%d idx=%d val=%g exp_sum=%g\n", in[o], in[o] - maxb + 256, exps[in[o] - maxb + 256], + // exp_sum); + } + // LL_ATON_PRINTF("exp_sum=%g\n", exp_sum); + + exp_sum *= scaleout; + float inv_exp_sum = 1.0f / exp_sum; + + for (o = 0; o < left_elem * inner_elem; o += left_elem) + { + float t = exps[in[o] - maxb]; + t = (t * inv_exp_sum + off); + int ti = (t > 0 ? (int)(t + 0.5f) : (int)(t - 0.5f)); + ti = (t > 127 ? 127 : (t < -128 ? -128 : ti)); + out[o] = (int8_t)ti; + // LL_ATON_PRINTF("out:%d %d %p\n", in[o], out[o], (out + o)); + // LL_ATON_PRINTF("%g %x", out[o],out+o); + } + in += left_elem; + out += left_elem; + } + + return LL_ATON_OK; +} + +int LL_ATON_LIB_Softmax(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, + unsigned int axis, int legacy) +{ + int in_elements = LL_LIB_TENSOR_ELEMENTS(input); + int out_elements = LL_LIB_TENSOR_ELEMENTS(output); + int el_size = input->type == DataType_FLOAT ? 4 : 1; + int in_byte_size = (in_elements * el_size * 8) >> 3; + int out_byte_size = (out_elements * el_size * 8) >> 3; + + // if (axis != 1) // for now we only support axis = 1 FIXME !!! + // __LL_LIB_ERROR(_ERR_AXIS, LL_ATON_INVALID_PARAM); + + if (in_elements != out_elements) + __LL_LIB_ERROR(_ERR_BUFFER, LL_ATON_INVALID_PARAM); + +#if 0 + if ((input->Qm + input->Qn) != 0 || (output->Qm + output->Qn) != 0) // must be float + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); +#else + if (input->type != output->type || + (input->type != DataType_FLOAT && input->type != DataType_INT8)) // must be float or INT8 + __LL_LIB_ERROR(_ERR_DATATYPE, LL_ATON_INVALID_PARAM); +#endif + + if (in_byte_size > LL_Buffer_len(input)) + __LL_LIB_ERROR(_ERR_BUFFER_IN, LL_ATON_INVALID_PARAM); + + if (out_byte_size > LL_Buffer_len(output)) + __LL_LIB_ERROR(_ERR_BUFFER_OUT, LL_ATON_INVALID_PARAM); + + if (input->ndims < 4) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + + if (output->ndims < 4) + __LL_LIB_ERROR(_ERR_SHAPE_OUT, LL_ATON_INVALID_PARAM); + + if (input->type == DataType_INT8) + { + if (input->per_channel) + __LL_LIB_ERROR(_ERR_DATATYPE, LL_ATON_INVALID_PARAM); + return legacy ? LL_ATON_LIB_Softmax_INT8_legacy(input, output, axis) + : LL_ATON_LIB_Softmax_INT8(input, output, axis); + } + if (input->type == DataType_FLOAT) + { + return legacy ? LL_ATON_LIB_Softmax_float_legacy(input, output, axis) + : LL_ATON_LIB_Softmax_float(input, output, axis); + } + + return LL_ATON_INVALID_PARAM; +} + +/** + * @brief performs flat copy operation on an input and several outputs using DMA + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param nr_of_outputs number of output tensors + * @param dma_in DMA number of DMA reading from memory + * @param dma_in DMA number of DMA writing to memory + * @retval Error code + */ +int LL_ATON_LIB_DMA_Outputs_Flat_Copy(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, int dma_in, + int dma_out) +{ +#ifndef NDEBUG + // LL_ATON_PRINTF("%s() line %d\n", __func__, __LINE__); + + int input_size = LL_Buffer_len(input); + int output_size = 0; + + for (unsigned i = 0; i < nr_of_outputs; i++) + { + output_size += LL_Buffer_len(outputs + i); + } + + if (input_size < output_size) + { // should never happen + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } +#endif // !NDEBUG + + if (nr_of_outputs <= 0) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + if (nr_of_outputs > __LL_MAX_TENSORS) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + __LL_ATON_LIB_DMA_Outputs_Memcpy(input, outputs, nr_of_outputs, dma_in, dma_out); + + return LL_ATON_OK; +} + +/** + * @brief perform split-like slice operation using DMAs + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param tot_out_size size of output buffer + * @param width_in_bytes number of bytes per `memcpy` + * @param fheight DMA `fheight` field + * @param line_offset DMA `line_offset` field + * @param n_bits DMA channel size + * @param dma_in DMA number of DMA reading from memory + * @param dma_in DMA number of DMA writing to memory + * @return Error code + */ +int LL_ATON_LIB_DMA_Outputs_Slice_SplitLike(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *output, int32_t tot_out_size, + int32_t width_in_bytes, int32_t fheight, int32_t line_offset, int8_t n_bits, + int dma_in, int dma_out) +{ + // Do actual copy + if (tot_out_size < __LL_DMA_MIN_BUFF_LEN) + { + for (unsigned source = 0, dest = 0; dest < tot_out_size; source += line_offset, dest += width_in_bytes) + { + // LL_ATON_PRINTF("dest=%d, source=%d\n", dest, source); + memcpy(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start(output) + dest), + ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start(input) + source), width_in_bytes); + } + } + else + { + /* prepare epoch */ + LL_ATON_ASSERT((tot_out_size % width_in_bytes) == 0); + + LL_Streng_TensorInitTypeDef _dma_in = {.addr_base.i = input->addr_base.i, + .offset_start = input->offset_start, + .offset_end = input->offset_start + width_in_bytes, + .offset_limit = input->offset_limit, + + .dir = 0, + .raw = 1, + + .nbits_in = n_bits, + .nbits_out = n_bits, + + .frame_offset = line_offset, + + .frame_tot_cnt = fheight, + .frame_loop_cnt = 0}; + + LL_Streng_TensorInitTypeDef _dma_out = {.addr_base.i = output->addr_base.i, + .offset_start = output->offset_start, + .offset_end = output->offset_end, + + .dir = 1, + .raw = 1, + + .nbits_in = n_bits, + .nbits_out = n_bits, + + .frame_tot_cnt = 1, + .frame_loop_cnt = 0}; + + /* save DMA configurations */ + __ll_lib_params_t *params = __ll_lib_get_params(); + params->g_dma_in = _dma_in; + params->g_dma_out = _dma_out; + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(dma_in, dma_out, _slice_split_like_epoch_block_array); + + LL_ATON_RT_Insert_LibEpochBlockArray(_slice_split_like_epoch_block_array); + } + + return LL_ATON_OK; +} + +/** + * @brief performs channel-split copy operation on an input and several outputs (both in ATON canonical format) using + * DMA + * @param input tensor shape structure + * @param outputs tensor shape structures + * @param nr_of_outputs number of output tensors + * @retval Error code + */ +int LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, + unsigned int leading_dims, int dma_in, int dma_out) +{ +#ifndef NDEBUG + // LL_ATON_PRINTF("%s() line %d\n", __func__, __LINE__); + + int input_size = LL_Buffer_len(input); + int output_size = 0; + + for (unsigned i = 0; i < nr_of_outputs; i++) + { + output_size += LL_Buffer_len(outputs + i); + } + + if (input_size != output_size) + { // should never happen + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } +#endif // !NDEBUG + + if (nr_of_outputs <= 0) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + if (nr_of_outputs > __LL_MAX_TENSORS) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + __LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton(input, outputs, nr_of_outputs, leading_dims, dma_in, dma_out); + + return LL_ATON_OK; +} + +/** + * @brief performs a channel-split memory copy operation from one input (ATON canonical) to `noutputs` + * non-ATON-canonical outputs using stream engines `dma_in` and `dma_out` + * @param src source address + * @param outputs list of output tensor shape structures + * @param noutputs number of outputs + * @retval Error code + */ +int LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, + int dma_in, int dma_out) +{ +#ifndef NDEBUG + // LL_ATON_PRINTF("%s() line %d\n", __func__, __LINE__); + + int input_size = LL_Buffer_len(input); + int output_size = 0; + + for (unsigned i = 0; i < nr_of_outputs; i++) + { + output_size += LL_Buffer_len(outputs + i); + } + + if (input_size != output_size) + { // should never happen + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } +#endif // !NDEBUG + + if (nr_of_outputs <= 0) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + if (nr_of_outputs > __LL_MAX_TENSORS) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + __LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched(input, outputs, nr_of_outputs, dma_in, dma_out); + + return LL_ATON_OK; +} + +/* `memset` helper functions */ +#define __LL_DMA_INTERNAL_BUSPORT_WIDTH 8 // MUST correspond to value of `BUSPORT_DATA_W` in Verilog file `ipu_def.vpp` + +static inline uint32_t __ll_lib_match_preload_with_busport(size_t size, uint8_t nbytes, uint32_t *min_bytes_to_preload) +{ + uint32_t _min_bytes_to_preload = *min_bytes_to_preload; + uint32_t max_nr_preloads_in_busport = (__LL_DMA_INTERNAL_BUSPORT_WIDTH / _min_bytes_to_preload); + + unsigned nr_of_samples = 2; + uint32_t last_aligned_size = size % _min_bytes_to_preload; + for (; nr_of_samples <= max_nr_preloads_in_busport; nr_of_samples++) + { + uint32_t copy_samples_in_bytes = (nr_of_samples * _min_bytes_to_preload); + uint32_t aligned_size = size % copy_samples_in_bytes; + LL_ATON_ASSERT((aligned_size % nbytes) == 0); + + if ((aligned_size + copy_samples_in_bytes) > __LL_DMA_INTERNAL_BUSPORT_WIDTH) + { + break; + } + + last_aligned_size = aligned_size; + } + nr_of_samples--; + + uint32_t samples_to_copy_from_in_bytes = (nr_of_samples * _min_bytes_to_preload); + uint32_t bytes_to_preload = (last_aligned_size + samples_to_copy_from_in_bytes); + + LL_ATON_ASSERT(bytes_to_preload <= __LL_DMA_INTERNAL_BUSPORT_WIDTH); + /* LL_ATON_ASSERT(bytes_to_preload <= size); */ // always guaranteed as `size >= __LL_DMA_INTERNAL_BUSPORT_WIDTH`) + LL_ATON_ASSERT((bytes_to_preload % nbytes) == 0); + + *min_bytes_to_preload = samples_to_copy_from_in_bytes; + + // return number of bytes to pre-load + return bytes_to_preload; +} + +static inline void __ll_lib_load_const_val(void **dst, int32_t constant_value, size_t size, uint8_t nbytes) +{ + uint8_t *_dst_orig = *dst; + + switch (nbytes) + { + case 1: + { // 8-bit + int8_t **_dst = (int8_t **)dst; + int i = 0; + for (; i < size; i++) + { + **_dst = (int8_t)constant_value; + (*_dst)++; + } + } + break; + case 2: + { // 16-bit + int16_t **_dst = (int16_t **)dst; + int i = 0; + for (; i < size; i += 2) + { + **_dst = (int16_t)constant_value; + (*_dst)++; + } + } + break; + case 3: + { // 24-bit + int8_t **_dst = (int8_t **)dst; + for (int i = 0; i < size; i += 3) + { + **_dst = constant_value & 0xFF; + (*_dst)++; + **_dst = (constant_value >> 8) & 0xFF; + (*_dst)++; + **_dst = (constant_value >> 16) & 0xFF; + (*_dst)++; + } + } + break; + case 4: + { // 32-bit + int32_t **_dst = (int32_t **)dst; + int i = 0; + for (; i < size; i += 4) + { + **_dst = (int32_t)constant_value; + (*_dst)++; + } + } + break; + default: + LL_ATON_ASSERT(0); // should never happen!!! + return; + } + + if (size > 0) + { + /* *** MCU cache clean & invalidate operation (SW) *** */ + LL_ATON_Cache_MCU_Clean_Invalidate_Range(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR((uintptr_t)_dst_orig), size); + } +} + +/* NOTE: function assumes that `size`, `*dst`, & `min_bytes_to_preload` are correctly aligned */ +static inline size_t __ll_lib_memset_prolog(void **dst, int32_t constant_value, size_t size, uint8_t nbytes, + uint32_t *min_bytes_to_preload) +{ +#if (__LL_DMA_INTERNAL_BUSPORT_WIDTH < 6) + /* `6` comes from the worst case scenario of 16bits samples with minimum of 4 bytes preload (`4 bytes + 2 bytes` of + * max rest) */ +#error "`__LL_DMA_INTERNAL_BUSPORT_WIDTH` is too small for current (slightly optimized) version of DMA-based `memset`!" +#endif + + if (size < (__LL_DMA_MIN_BUFF_LEN + __LL_DMA_INTERNAL_BUSPORT_WIDTH)) + { + /* it's not worth it ... */ + __ll_lib_load_const_val(dst, constant_value, size, nbytes); + + return 0; + } + else + { + uint32_t nr_of_bytes_to_pre_load = __ll_lib_match_preload_with_busport(size, nbytes, min_bytes_to_preload); + /* pre-load first samples */ + __ll_lib_load_const_val(dst, constant_value, nr_of_bytes_to_pre_load, nbytes); + size -= nr_of_bytes_to_pre_load; + + return size; + } +} + +static bool __ll_lib_memset(void *dst, void *dst_limit, int32_t constant_value, uint8_t nbytes, size_t size) +{ + unsigned char *dst_orig = (unsigned char *)dst; + uint32_t samples_in_bytes_preloaded = 0; + int nbits = 0; + + LL_ATON_ASSERT((size % nbytes) == 0); + + switch (nbytes) + { + case 1: + case 3: + samples_in_bytes_preloaded = 3; // max `nbytes` & equal to nr of channels used (`#channels_used == 3` + nbits = 24; // `#channels_used * 8` + break; + case 2: + case 4: + LL_ATON_ASSERT((((intptr_t)dst) % nbytes) == 0); + samples_in_bytes_preloaded = 4; // max `nbytes` & multiple of nr of channels used (`#channels_used == 2`) + nbits = 16; // `#channels_used * 8` + break; + default: + LL_ATON_ASSERT(0); // should never happen!!! + return false; + } + + /* pre-load destination & align `dst` to value of `samples_in_bytes_preloaded` */ + size = __ll_lib_memset_prolog(&dst, constant_value, size, nbytes, &samples_in_bytes_preloaded); + if (size == 0) + { + return false; // we are done + } + + /* setup configuration for DMAs */ + LL_ATON_ASSERT((size % samples_in_bytes_preloaded) == 0); + int frame_tot_cnt = (size / samples_in_bytes_preloaded); + + LL_Streng_TensorInitTypeDef _dma_in = {.dir = 0, + .addr_base = {dst_orig}, + .offset_start = 0, + .offset_end = samples_in_bytes_preloaded, + .offset_limit = + (unsigned char *)dst_limit - dst_orig, /* awful FIXME Francesco */ + .raw = 1, + .noinc = 1, + .frame_tot_cnt = frame_tot_cnt, + .nbits_in = nbits, + .nbits_out = nbits, + .nbits_unsigned = 0}; + + LL_Streng_TensorInitTypeDef _dma_out = {.dir = 1, + .addr_base = {dst}, + .offset_start = 0, + .offset_end = size, + .raw = 1, + .frame_tot_cnt = 1, + .nbits_in = nbits, + .nbits_out = nbits, + .nbits_unsigned = 0}; + + /* save DMA configurations */ + __ll_lib_params_t *params = __ll_lib_get_params(); + params->g_dma_in = _dma_in; + params->g_dma_out = _dma_out; + + return true; +} + +static inline void __ll_lib_pad_save_params(__ll_pad_sw_params_t *common_params) +{ + __ll_lib_params_t *params = __ll_lib_get_params(); + void *lower_heap = __ll_lib_get_lower_heap(); + + /* flat copy of params */ + params->special.pad = *common_params; + + /* prepare for deep copy of vectors */ + uint32_t *min_shape = (uint32_t *)lower_heap; + int32_t *pad_in_offsets_start = (int32_t *)(min_shape + common_params->tensor_rank); + int32_t *pad_in_offsets_end = (int32_t *)(pad_in_offsets_start + common_params->tensor_rank); + int32_t *pad_out_offsets_start = (int32_t *)(pad_in_offsets_end + common_params->tensor_rank); + int32_t *pad_out_offsets_end = (int32_t *)(pad_out_offsets_start + common_params->tensor_rank); + int32_t *out_shape = (int32_t *)(pad_out_offsets_end + common_params->tensor_rank); + int32_t *out_offsets = (int32_t *)(out_shape + common_params->tensor_rank); + uint32_t *indexes = (uint32_t *)(out_offsets + common_params->tensor_rank); + + /* copy vectors to lower heap & overwrite pointers */ + for (uint32_t i = 0; i < common_params->tensor_rank; i++) + { + min_shape[i] = common_params->min_shape[i]; + pad_in_offsets_start[i] = common_params->pad_in_offsets_start[i]; + pad_in_offsets_end[i] = common_params->pad_in_offsets_end[i]; + pad_out_offsets_start[i] = common_params->pad_out_offsets_start[i]; + pad_out_offsets_end[i] = common_params->pad_out_offsets_end[i]; + out_shape[i] = common_params->out_shape[i]; + out_offsets[i] = common_params->out_offsets[i]; + indexes[i] = 0; + } + params->special.pad.min_shape = min_shape; + params->special.pad.pad_in_offsets_start = pad_in_offsets_start; + params->special.pad.pad_in_offsets_end = pad_in_offsets_end; + params->special.pad.pad_out_offsets_start = pad_out_offsets_start; + params->special.pad.pad_out_offsets_end = pad_out_offsets_end; + params->special.pad.out_shape = out_shape; + params->special.pad.out_offsets = out_offsets; + params->special.pad.indexes = indexes; +} + +/** + * @brief performs an optimized `memset` for the `Pad` operator using DMA (aka Framing) + * @param output destination address of `memset` operation + * @param constant_value constant value to be set + * @param out_size number of bytes to output + * @param common_params parameters needed to setup DMAs and to forward to eventual callback function + * @retval Error code + */ +int LL_ATON_LIB_DMA_Pad_Memset(void *output, int32_t constant_value, size_t out_size, + __ll_pad_sw_params_t *common_params) +{ + /* save common parameters */ + __ll_lib_pad_save_params(common_params); + + /* start operation */ + bool ret = __ll_lib_memset(output, common_params->out_limit, constant_value, common_params->nbytes, out_size); + + if (ret) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): performing DMA based `memset`\n", __func__, __LINE__); +#endif + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(common_params->dma_in, common_params->dma_out, _dma_Pad_memset_epoch_block_array); + + /* start DMAs for `memset` & run `LL_ATON_LIB_Pad_Filling()` */ + LL_ATON_RT_Insert_LibEpochBlockArray(_dma_Pad_memset_epoch_block_array); + } + else + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): performing pure SW `memset`\n", __func__, __LINE__); +#endif + + __ll_lib_params_t *params = __ll_lib_get_params(); + + /* `memset` already done => run callback function (if any) */ + if (params->special.pad.callback_function != NULL) + { + /* call follow-up function */ + return (*params->special.pad.callback_function)(¶ms->special.pad); + } + } + + return LL_ATON_OK; +} + +/** + * @brief performs HW accelerated filling operation for `Pad` operator (aka Filling) + * @retval Error code + */ +int LL_ATON_LIB_DMA_Pad_Filling(__ll_pad_sw_params_t *init_common_params) +{ + /* save common parameters */ + if (init_common_params != NULL) + { + __ll_lib_pad_save_params(init_common_params); + } + + /* get common parameters */ + __ll_lib_params_t *params = __ll_lib_get_params(); + __ll_pad_sw_params_t *common_params = ¶ms->special.pad; + + /* prepare epoch */ + params->g_dma_in = _static_const_dma_in; + params->g_dma_out = _static_const_dma_out; + + /* `__ll_lib_inputs_memcpy_start()` requires use of generic `size` parameter */ + params->g_size = common_params->consecutive_bytes; + + for (params->g_idx = 0; params->g_idx <= common_params->consecutive_axis; params->g_idx++) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): in=%lx, out=%lx, curr_axis=%u, min_dim=%u, in_start=%d, out_start=%d\n", __func__, __LINE__, + (uintptr_t)common_params->in_target, (uintptr_t)common_params->out_target, params->g_idx, + common_params->min_shape[params->g_idx], common_params->pad_in_offsets_start[params->g_idx], + common_params->pad_out_offsets_start[params->g_idx]); +#endif + + if (common_params->pad_out_offsets_start[params->g_idx] > 0) + { + common_params->out_target += common_params->pad_out_offsets_start[params->g_idx]; + } + + if (common_params->pad_in_offsets_start[params->g_idx] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_start[params->g_idx]; + } + } + + params->g_idx = common_params->consecutive_axis; + + /* configure stream switch */ + __ll_lib_strswitch_set_dmas(common_params->dma_in, common_params->dma_out, _dma_Pad_filling_epoch_block_array); + + /* start DMAs for filling `consecutive bytes` */ + LL_ATON_RT_Insert_LibEpochBlockArray(_dma_Pad_filling_epoch_block_array); + + return LL_ATON_OK; +} diff --git a/lib/stai/libstai/ll_aton/ll_aton_lib_sw_operators.c b/lib/stai/libstai/ll_aton/ll_aton_lib_sw_operators.c new file mode 100644 index 000000000..4151fb749 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_lib_sw_operators.c @@ -0,0 +1,2143 @@ +/** + ****************************************************************************** + * @file ll_aton_lib_sw_operators.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON library for pure SW operators + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include + +#include "ll_aton_util.h" // Leave blank line after the include + +#include "ll_aton_lib.h" +#include "ll_aton_lib_sw_operators.h" +#include "ll_aton_runtime.h" + +/* Common data structure(s) */ +typedef struct __ll_stack_lnklst +{ + struct __ll_stack_lnklst *back_link; + uint32_t axis; + uint32_t index; +} __ll_stack_lnklst_t; + +/* Helper Functions */ +static inline void __ll_aton_lib_copy_element(uint8_t nbytes, int32_t index, int8_t *out_target, int8_t *in_target) +{ + LL_ATON_LIB_UNUSED(index); + + switch (nbytes) + { + case 1: +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("[%d]\t%d\t@ out: 0x%lx, in: 0x%lx\n", index, *in_target, (uintptr_t)out_target, + (uintptr_t)in_target); +#endif + *out_target = *in_target; + return; + + case 2: +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("[%d]\t%d\t@ out: 0x%lx, in: 0x%lx\n", index, *((int16_t *)in_target), (uintptr_t)out_target, + (uintptr_t)in_target); +#endif + LL_ATON_ASSERT((((uintptr_t)in_target) % 2) == 0); + LL_ATON_ASSERT((((uintptr_t)out_target) % 2) == 0); + + *((int16_t *)out_target) = *((int16_t *)in_target); + return; + + case 3: // NOTE: assuming no alignment + *out_target++ = *in_target++; + *out_target++ = *in_target++; + *out_target++ = *in_target++; + return; + + case 4: +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("[%d]\t%d\t@ out: 0x%lx, in: 0x%lx\n", index, *((int32_t *)in_target), (uintptr_t)out_target, + (uintptr_t)in_target); +#endif + LL_ATON_ASSERT((((uintptr_t)in_target) % 4) == 0); + LL_ATON_ASSERT((((uintptr_t)out_target) % 4) == 0); + + *((int32_t *)out_target) = *((int32_t *)in_target); + return; + + default: + LL_ATON_ASSERT(false); + return; + } +} + +static inline uint32_t __ll_aton_lib_calc_offset(uint32_t n, uint32_t c, uint32_t h, uint32_t w, uint32_t offset_0, + uint32_t offset_1, uint32_t offset_2, uint32_t offset_3) +{ + uint32_t result = 0; + + result += (n * offset_0); + result += (c * offset_1); + result += (h * offset_2); + result += (w * offset_3); + + return result; +} + +/** + * @brief performs a slice operation on a (multi-dimensional) matrix + * @param input tensor shape structure + * @param output tensor shape structure + * @param slice_rank rank of slice operation's input matrix + * @param slice_starts 1-D tensor of starting indices of corresponding axis from 0 to rank-1 + * @param slice_ends 1-D tensor of ending indices (exclusive) of corresponding axis from 0 to rank-1 + * @param slice_steps 1-D tensor of slice step of corresponding axis from 0 to rank-1 + * @retval Error code + */ +typedef const struct +{ + const LL_LIB_TensorShape_TypeDef *input; + const uint32_t *input_axes_offsets; + const LL_LIB_TensorShape_TypeDef *output; + const uint32_t *output_axes_offsets; + uint32_t slice_rank; + const int32_t *slice_starts; + const int32_t *slice_ends; + const int32_t *slice_steps; +} __ll_slice_params_t; + +static inline int32_t __ll_aton_lib_is_in_slice(const __ll_slice_params_t *common_params, __ll_stack_lnklst_t *elem) +{ + uint32_t index = elem->index; + uint32_t axis = elem->axis; + + uint8_t slice_forwards = (common_params->slice_steps[axis] < 0) ? 0 : 1; + + int32_t ret_numerator; + int32_t ret_denominator = abs(common_params->slice_steps[axis]); + + int32_t min; + int32_t max; + + if (slice_forwards) + { + ret_numerator = (index - common_params->slice_starts[axis]); + min = common_params->slice_starts[axis]; + max = common_params->slice_ends[axis]; + } + else + { + ret_numerator = (common_params->slice_starts[axis] - index); + max = common_params->slice_starts[axis] + 1; + min = common_params->slice_ends[axis] + 1; + } + + if (((index >= min) && (index < max)) && (ret_numerator % ret_denominator == 0)) + { + LL_ATON_ASSERT(ret_numerator >= 0); + LL_ATON_ASSERT(ret_denominator > 0); + + return (ret_numerator / ret_denominator); + } + else + { + return -1; + } +} + +static int8_t *__ll_slice_get_input_and_output_base_pos(const __ll_slice_params_t *common_params, + __ll_stack_lnklst_t *linked_stack_list, int8_t **base_in_target) +{ + LL_ATON_ASSERT(linked_stack_list != NULL); + + int8_t *in_target = (int8_t *)LL_Buffer_addr_start(common_params->input); + int8_t *out_target = (int8_t *)LL_Buffer_addr_start(common_params->output); + + LL_ATON_ASSERT(linked_stack_list->axis == (common_params->slice_rank - 1)); + + for (__ll_stack_lnklst_t *elem = linked_stack_list->back_link; elem != NULL; elem = elem->back_link) + { + LL_ATON_ASSERT(elem->axis < (common_params->slice_rank - 1)); + uint32_t axis = elem->axis; + + /* input */ + int32_t in_axis_size = common_params->input_axes_offsets[axis]; + in_target += (elem->index * in_axis_size); + + int32_t out_index; + if ((out_index = __ll_aton_lib_is_in_slice(common_params, elem)) >= 0) + { + /* output */ + int32_t out_axis_size = common_params->output_axes_offsets[axis]; + out_target += (out_index * out_axis_size); + } + else + { + return NULL; + } + } + + *base_in_target = in_target; + return out_target; +} + +static inline void __ll_slice_copy_elem(const __ll_slice_params_t *common_params, + __ll_stack_lnklst_t *linked_stack_list, uint32_t in_offset, uint32_t out_offset, + int8_t *base_in_target, int8_t *base_out_target) +{ + const uint8_t byte_size = LL_LIB_NBYTES(common_params->input->nbits); + + int32_t out_index; + if ((out_index = __ll_aton_lib_is_in_slice(common_params, linked_stack_list)) >= 0) + { + /* determine input/output position */ + int8_t *in_target = base_in_target + (linked_stack_list->index * in_offset); + int8_t *out_target = base_out_target + (out_index * out_offset); + + __ll_aton_lib_copy_element(byte_size, out_index, out_target, in_target); + } +} + +static void __ll_aton_lib_slice(uint32_t curr_in_axis, __ll_stack_lnklst_t *back_link, + const __ll_slice_params_t *common_params) +{ + uint8_t slice_forwards = (common_params->slice_steps[curr_in_axis] < 0) ? 0 : 1; + __ll_stack_lnklst_t linked_stack_list = { + .back_link = back_link, .axis = curr_in_axis, .index = common_params->slice_starts[curr_in_axis]}; + + const uint32_t index_end = common_params->slice_ends[curr_in_axis]; + + if (curr_in_axis < (common_params->slice_rank - 1)) + { // intermediate axis + if (slice_forwards) + { // slicing forwards + for (; linked_stack_list.index < index_end; linked_stack_list.index++) + { + __ll_aton_lib_slice(curr_in_axis + 1, &linked_stack_list, common_params); + } + } + else + { // slicing backwards + do + { + __ll_aton_lib_slice(curr_in_axis + 1, &linked_stack_list, common_params); + linked_stack_list.index--; + } while (linked_stack_list.index > index_end); + } + } + else + { // last axis + LL_ATON_ASSERT(curr_in_axis == (common_params->slice_rank - 1)); + + /* Calculate input base positions */ + int8_t *base_in_target; + int8_t *base_out_target = + __ll_slice_get_input_and_output_base_pos(common_params, &linked_stack_list, &base_in_target); + + if (base_out_target == NULL) + return; + + uint32_t curr_in_axis_input_offset = common_params->input_axes_offsets[curr_in_axis]; + uint32_t curr_in_axis_output_offset = common_params->output_axes_offsets[curr_in_axis]; + + if (slice_forwards) + { // slicing forwards + for (; linked_stack_list.index < index_end; linked_stack_list.index++) + { + __ll_slice_copy_elem(common_params, &linked_stack_list, curr_in_axis_input_offset, curr_in_axis_output_offset, + base_in_target, base_out_target); + } + } + else + { // slicing backwards + do + { + __ll_slice_copy_elem(common_params, &linked_stack_list, curr_in_axis_input_offset, curr_in_axis_output_offset, + base_in_target, base_out_target); + linked_stack_list.index--; + } while (linked_stack_list.index > index_end); + } + } +} + +int LL_ATON_LIB_Slice(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + uint32_t slice_rank, const int32_t *slice_starts, const int32_t *slice_ends, + const int32_t *slice_steps) +{ + if (slice_rank != input->ndims) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->ndims != output->ndims) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->nbits != output->nbits) + { // TODO: should we support this? + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if ((input->nbits < 8) || (input->nbits > 32)) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + const __ll_slice_params_t common_params = {.input = input, + .input_axes_offsets = input_axes_offsets, + .output = output, + .output_axes_offsets = output_axes_offsets, + .slice_rank = slice_rank, + .slice_starts = slice_starts, + .slice_ends = slice_ends, + .slice_steps = slice_steps}; + + __ll_aton_lib_slice(0, NULL, &common_params); + + return LL_ATON_OK; // TODO +} + +static int __ll_aton_lib_sw_outputs_flat_copy(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef (*outputs)[], unsigned nr_of_outputs) +{ +#ifndef NDEBUG + // LL_ATON_PRINTF("%s() line %d\n", __func__, __LINE__); + + int input_size = LL_Buffer_len(input); + int output_size = 0; + + for (unsigned i = 0; i < nr_of_outputs; i++) + { + output_size += LL_Buffer_len((*outputs) + i); + } + + if (input_size != output_size) + { // should never happen + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + + uint8_t nbits = LL_LIB_NBYTES(input->nbits); + for (unsigned i = 0; i < nr_of_outputs; i++) + { + if ((*outputs)[i].nbits != nbits) + { + __LL_LIB_ERROR(_ERR_NBITS_OUT, LL_ATON_INVALID_PARAM); + } + } +#endif // !NDEBUG + + if (nr_of_outputs <= 0) + { // should never happen + __LL_LIB_ERROR(_ERR_NOUTPUTS, LL_ATON_INVALID_PARAM); + } + + unsigned char *curr_in_addr = ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start(input)); + for (int i = 0; i < nr_of_outputs; i++) + { + unsigned char *out_addr = ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start((*outputs) + i)); + unsigned out_size = LL_Buffer_len((*outputs) + i); + + memcpy(out_addr, curr_in_addr, out_size); + + curr_in_addr += out_size; + } + + return LL_ATON_OK; +} + +// convert axis from ...CHW -> ...HWC +static const int aton_lut[] = {TDIM_NKERNELS, TDIM_NCHANNELS, TDIM_FHEIGHT, TDIM_FWIDTH}; +#define LUT_ATON(x) (((x >= (rank - 4)) && (rank > 2)) ? (rank - 4) + aton_lut[x - (rank - 4)] : x) + +// convert axis from ...HWC -> ...CHW +static const int onnx_lut[] = {TDIM_ONNX_NKERNELS, TDIM_ONNX_FHEIGHT, TDIM_ONNX_FWIDTH, TDIM_ONNX_NCHANNELS}; +#define LUT_ONNX(x) (((x >= (rank - 4)) && (rank > 2)) ? (rank - 4) + onnx_lut[x - (rank - 4)] : x) + +/* beyond function assumes that input and output tensors are ATON canonical */ +static void __ll_aton_lib_split_aton_canonical(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef (*outputs)[], int nr_of_outputs, + int rank, int split_onnx_axis) +{ + int aton_axis = LUT_ATON(split_onnx_axis); + int tot_size = LL_Buffer_len(input); + + int start = 0; + int stop = tot_size; + int jump_base = 1; + for (int i = aton_axis + 1; i < rank; i++) + jump_base *= input->shape[LUT_ONNX(i)]; + jump_base *= LL_LIB_NBYTES(input->nbits); + int jump = jump_base * input->shape[split_onnx_axis]; + // LL_ATON_PRINTF("onnx_axis=%d, aton_axis=%d, jump_base=%d, jump=%d\n", split_onnx_axis, aton_axis, jump_base, jump); + + for (int i = 0; i < nr_of_outputs; i++) + { + int copy_val = (*outputs)[i].shape[split_onnx_axis] * jump_base; + // LL_ATON_PRINTF("i=%d copy_val=%d\n", i, copy_val); + + int source; + int dest = 0; + for (source = start; source < stop; source += jump, dest += copy_val) + { + // LL_ATON_PRINTF("i=%d, dest=%d, source=%d\n", i, dest, source); + memcpy(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start((*outputs) + i) + dest), + ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start(input) + source), copy_val); + } + start += copy_val; + } +} + +/* beyond function assumes that input and output tensors are ONNX canonical */ +static void __ll_aton_lib_split_onnx_canonical(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef (*outputs)[], int nr_of_outputs, + int rank, int split_onnx_axis) +{ + int tot_size = LL_Buffer_len(input); + + int start = 0; + int stop = tot_size; + int jump_base = 1; + for (int i = split_onnx_axis + 1; i < rank; i++) + jump_base *= input->shape[i]; + jump_base *= LL_LIB_NBYTES(input->nbits); + int jump = jump_base * input->shape[split_onnx_axis]; + // LL_ATON_PRINTF("onnx_axis=%d, aton_axis=%d, jump_base=%d, jump=%d\n", split_onnx_axis, aton_axis, jump_base, jump); + + for (int i = 0; i < nr_of_outputs; i++) + { + int copy_val = (*outputs)[i].shape[split_onnx_axis] * jump_base; + // LL_ATON_PRINTF("i=%d copy_val=%d\n", i, copy_val); + + int source; + int dest = 0; + for (source = start; source < stop; source += jump, dest += copy_val) + { + // LL_ATON_PRINTF("i=%d, dest=%d, source=%d\n", i, dest, source); + memcpy(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start((*outputs) + i) + dest), + ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start(input) + source), copy_val); + } + start += copy_val; + } +} + +/* beyond function assumes that adapted rank is equal to 3, that input tensor is ATON canonical, and that split axis + * is channel */ +static void __ll_aton_lib_split_channel_batched(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef (*outputs)[], uint32_t nr_of_outputs, + uint32_t rank, uint32_t split_onnx_axis) +{ + LL_ATON_ASSERT(rank >= 3); // input shape is at least 3-dimensional + LL_ATON_ASSERT((input->batch == 0) || + (input->batch == input->shape[split_onnx_axis])); // input tensor is ATON canonical + LL_ATON_ASSERT(split_onnx_axis == (rank - 3)); // split axis is channel + + uint32_t nbytes = LL_LIB_NBYTES(input->nbits); + uint32_t fheight = input->shape[rank - 2]; + uint32_t fwidth = input->shape[rank - 1]; + uint32_t in_nchannels = input->shape[split_onnx_axis]; + uint32_t batch_offset = in_nchannels * nbytes; + + // assuming that all leading dimensions up to channel are equal to 1! + + unsigned char *outer_addr = ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start(input)); + for (int i = 0; i < nr_of_outputs; i++) + { + uint16_t out_batch = (*outputs)[i].batch; + uint32_t batch_depth_bytes = out_batch * nbytes; + uint32_t line_offset = in_nchannels * fwidth * nbytes; + uint32_t loop_offset = out_batch * nbytes; + uint32_t out_nchannels = (*outputs)[i].shape[split_onnx_axis]; + + LL_ATON_ASSERT((out_nchannels % out_batch) == 0); + uint32_t frame_tot_cnt = out_nchannels / out_batch; + + unsigned char *output_addr = ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(LL_Buffer_addr_start((*outputs) + i)); + + /* main loop */ + unsigned char *addr_main_loop = outer_addr; + for (int j = 0; j < frame_tot_cnt; j++) + { + /* repetition loop (just a single iteration => removed) */ + unsigned char *repetition_addr = addr_main_loop; + + /* line loop */ + unsigned char *line_addr = repetition_addr; + for (int x = 0; x < fheight; x++) + { + /* batch loop */ + unsigned char *batch_addr = line_addr; + for (int y = 0; y < fwidth; y++) + { + memcpy(output_addr, batch_addr, batch_depth_bytes); + + output_addr += batch_depth_bytes; + batch_addr += batch_offset; + } + line_addr += line_offset; + } + addr_main_loop += loop_offset; + } + outer_addr += out_nchannels * nbytes; + } +} + +typedef enum +{ // MUST be the same as in the AtoNN compiler (file: `code_gen_info.h`) + SW_PURE_CANONICAL = 0, + HYBRID_CHANNEL_ATON = 1, + SW_CHANNEL_ATON = 2, + HYBRID_CHANNEL_BATCHED = 3, + SW_CHANNEL_BATCHED = 4, + DMA_CHANNEL_UNIFORM = 5, + SW_CHANNEL_UNIFORM = 6, + DMA_FLAT_CANONICAL = 7, + SW_FLAT_CANONICAL = 8, + DMA_FLAT_BATCHED = 9, + SW_FLAT_BATCHED = 10, +} _split_cases_t; + +int LL_ATON_LIB_Split(const LL_LIB_TensorShape_TypeDef *input, bool aton_canonical, + const LL_LIB_TensorShape_TypeDef (*outputs)[], uint32_t noutputs, uint32_t rank, + uint32_t split_onnx_axis, uint32_t leading_dims, int split_case, int dma_in, int dma_out) +{ + if (split_onnx_axis >= rank) + { + __LL_LIB_ERROR(_ERR_AXIS, LL_ATON_INVALID_PARAM); + } + + if (input->ndims != rank) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->ndims != (*outputs)[0].ndims) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->nbits != (*outputs)[0].nbits) + { // TODO: should we support this? + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if ((input->nbits < 8) || (input->nbits > 32)) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if ((rank == 0) || (noutputs < 1)) + return LL_ATON_OK; // in case ONNX was out of specs + + switch (split_case) + { + case SW_PURE_CANONICAL: + { + LL_ATON_ASSERT(dma_in == -1); + LL_ATON_ASSERT(dma_out == -1); + + if (aton_canonical) + { + __ll_aton_lib_split_aton_canonical(input, outputs, noutputs, rank, split_onnx_axis); + } + else + { + __ll_aton_lib_split_onnx_canonical(input, outputs, noutputs, rank, split_onnx_axis); + } + } + break; + case SW_CHANNEL_ATON: + LL_ATON_ASSERT(dma_in == -1); + LL_ATON_ASSERT(dma_out == -1); + case HYBRID_CHANNEL_ATON: + { + if (!aton_canonical) + { + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + + if ((noutputs > __LL_MAX_TENSORS) || (split_case == SW_CHANNEL_ATON)) + { + __ll_aton_lib_split_aton_canonical(input, outputs, noutputs, rank, split_onnx_axis); + } + else + { + LL_ATON_ASSERT(dma_in != -1); + LL_ATON_ASSERT(dma_out != -1); + + LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton(input, (const LL_LIB_TensorShape_TypeDef *)outputs, noutputs, + leading_dims, dma_in, dma_out); + } + } + break; + case SW_CHANNEL_BATCHED: + LL_ATON_ASSERT(dma_in == -1); + LL_ATON_ASSERT(dma_out == -1); + case HYBRID_CHANNEL_BATCHED: + { + if (!aton_canonical) + { + __LL_LIB_ERROR(_ERR_SHAPE, LL_ATON_INVALID_PARAM); + } + + if ((noutputs > __LL_MAX_TENSORS) || (split_case == SW_CHANNEL_BATCHED)) + { + __ll_aton_lib_split_channel_batched(input, outputs, noutputs, rank, split_onnx_axis); + } + else + { + LL_ATON_ASSERT(dma_in != -1); + LL_ATON_ASSERT(dma_out != -1); + + LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched(input, (const LL_LIB_TensorShape_TypeDef *)outputs, noutputs, + dma_in, dma_out); + } + } + break; + case SW_FLAT_CANONICAL: + case SW_FLAT_BATCHED: + case SW_CHANNEL_UNIFORM: + LL_ATON_ASSERT(dma_in == -1); + LL_ATON_ASSERT(dma_out == -1); + case DMA_FLAT_CANONICAL: + case DMA_FLAT_BATCHED: + case DMA_CHANNEL_UNIFORM: + { + if ((noutputs > __LL_MAX_TENSORS) || (split_case == SW_FLAT_CANONICAL) || (split_case == SW_FLAT_BATCHED) || + (split_case == SW_CHANNEL_UNIFORM)) + { + return __ll_aton_lib_sw_outputs_flat_copy(input, outputs, noutputs); + } + else + { + LL_ATON_ASSERT(dma_in != -1); + LL_ATON_ASSERT(dma_out != -1); + + LL_ATON_LIB_DMA_Outputs_Flat_Copy(input, (const LL_LIB_TensorShape_TypeDef *)outputs, noutputs, dma_in, dma_out); + } + } + break; + default: + LL_ATON_ASSERT(false); + break; + } + + return LL_ATON_OK; +} + +int LL_ATON_LIB_SW_SpaceToDepth(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + uint32_t bs_h, uint32_t bs_w) +{ + if (input->ndims != 4) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (output->ndims != 4) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->nbits != output->nbits) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if ((input->nbits < 8) || (input->nbits > 32)) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + uint32_t N = input->shape[0]; + uint32_t C = input->shape[1]; + uint32_t H = input->shape[2]; + uint32_t W = input->shape[3]; + + int8_t *in_base = (int8_t *)LL_Buffer_addr_start(input); + int8_t *out_base = (int8_t *)LL_Buffer_addr_start(output); + + uint32_t output_tensor_offset_0 = output_axes_offsets[0]; + uint32_t output_tensor_offset_1 = output_axes_offsets[1]; + uint32_t output_tensor_offset_2 = output_axes_offsets[2]; + uint32_t output_tensor_offset_3 = output_axes_offsets[3]; + + uint32_t input_tensor_offset_0 = input_axes_offsets[0]; + uint32_t input_tensor_offset_1 = input_axes_offsets[1]; + uint32_t input_tensor_offset_2 = input_axes_offsets[2]; + uint32_t input_tensor_offset_3 = input_axes_offsets[3]; + + for (uint32_t n = 0; n < N; n++) + { + for (uint32_t c = 0; c < C; c++) + { + for (uint32_t h = 0; h < H; h++) + { + for (uint32_t w = 0; w < W; w++) + { + uint32_t h_rem = h % bs_h; + uint32_t w_rem = w % bs_w; + uint32_t out_c = c + (((h_rem * bs_w) + w_rem) * C); + uint32_t out_h = (h / bs_h); + uint32_t out_w = (w / bs_w); + + int8_t *out_target = out_base + __ll_aton_lib_calc_offset(n, out_c, out_h, out_w, output_tensor_offset_0, + output_tensor_offset_1, output_tensor_offset_2, + output_tensor_offset_3); + int8_t *in_target = + in_base + __ll_aton_lib_calc_offset(n, c, h, w, input_tensor_offset_0, input_tensor_offset_1, + input_tensor_offset_2, input_tensor_offset_3); + + __ll_aton_lib_copy_element(LL_LIB_NBYTES(input->nbits), -1, out_target, in_target); + } + } + } + } + + return LL_ATON_OK; +} + +int LL_ATON_LIB_SW_DepthToSpace(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + uint32_t bs_h, uint32_t bs_w, uint32_t mode) +{ + if (input->ndims != 4) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (output->ndims != 4) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->nbits != output->nbits) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if ((input->nbits < 8) || (input->nbits > 32)) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + uint32_t N = input->shape[0]; + uint32_t C = input->shape[1]; + uint32_t H = input->shape[2]; + uint32_t W = input->shape[3]; + + uint32_t bs_hw = (bs_h * bs_w); + uint32_t max_c = (C / bs_hw); + + int8_t *in_base = (int8_t *)LL_Buffer_addr_start(input); + int8_t *out_base = (int8_t *)LL_Buffer_addr_start(output); + + uint32_t output_tensor_offset_0 = output_axes_offsets[0]; + uint32_t output_tensor_offset_1 = output_axes_offsets[1]; + uint32_t output_tensor_offset_2 = output_axes_offsets[2]; + uint32_t output_tensor_offset_3 = output_axes_offsets[3]; + + uint32_t input_tensor_offset_0 = input_axes_offsets[0]; + uint32_t input_tensor_offset_1 = input_axes_offsets[1]; + uint32_t input_tensor_offset_2 = input_axes_offsets[2]; + uint32_t input_tensor_offset_3 = input_axes_offsets[3]; + + if (mode == 0) + { // `DCR` + for (uint32_t n = 0; n < N; n++) + { + for (uint32_t c = 0; c < C; c++) + { + for (uint32_t h = 0; h < H; h++) + { + for (uint32_t w = 0; w < W; w++) + { + uint32_t off_h = (h * bs_h); + uint32_t off_w = (w * bs_w); + uint32_t out_c = c % max_c; + uint32_t out_h = off_h + (c / (max_c * bs_w)); + uint32_t out_w = off_w + ((c / max_c) % bs_w); + + int8_t *out_target = out_base + __ll_aton_lib_calc_offset(n, out_c, out_h, out_w, output_tensor_offset_0, + output_tensor_offset_1, output_tensor_offset_2, + output_tensor_offset_3); + int8_t *in_target = + in_base + __ll_aton_lib_calc_offset(n, c, h, w, input_tensor_offset_0, input_tensor_offset_1, + input_tensor_offset_2, input_tensor_offset_3); + + __ll_aton_lib_copy_element(LL_LIB_NBYTES(input->nbits), -1, out_target, in_target); + } + } + } + } + } + else + { // `CRD` + for (uint32_t n = 0; n < N; n++) + { + for (uint32_t out_c = 0; out_c < max_c; out_c++) + { + for (uint32_t c_rem_bs_2_div_bs = 0; c_rem_bs_2_div_bs < bs_h; c_rem_bs_2_div_bs++) + { + for (uint32_t c_rem_bs = 0; c_rem_bs < bs_w; c_rem_bs++) + { + uint32_t c = c_rem_bs + (c_rem_bs_2_div_bs * bs_w) + (out_c * bs_hw); + + for (uint32_t h = 0; h < H; h++) + { + for (uint32_t w = 0; w < W; w++) + { + uint32_t off_h = (h * bs_h); + uint32_t off_w = (w * bs_w); + uint32_t out_h = off_h + c_rem_bs_2_div_bs; + uint32_t out_w = off_w + c_rem_bs; + + int8_t *out_target = + out_base + __ll_aton_lib_calc_offset(n, out_c, out_h, out_w, output_tensor_offset_0, + output_tensor_offset_1, output_tensor_offset_2, + output_tensor_offset_3); + int8_t *in_target = + in_base + __ll_aton_lib_calc_offset(n, c, h, w, input_tensor_offset_0, input_tensor_offset_1, + input_tensor_offset_2, input_tensor_offset_3); + + __ll_aton_lib_copy_element(LL_LIB_NBYTES(input->nbits), -1, out_target, in_target); + } + } + } + } + } + } + } + return LL_ATON_OK; +} + +/** + * @brief performs a transpose operation on a (multi-dimensional) matrix + * @param input tensor shape structure + * @param output tensor shape structure + * @param perm permutation to apply + * @retval Error code + */ +typedef const struct +{ + uint32_t rank; + const uint8_t *perm; + const uint32_t *in_shape_aton; + const uint32_t *in_axis_off; + const uint32_t *out_axis_off; + const uint8_t byte_size; + const int8_t *in_tensor; + int8_t *out_tensor; +} __ll_transp_params_t; + +static inline uint32_t __ll_transp_find_input_index(__ll_stack_lnklst_t *elem, const uint8_t *perm, + uint32_t output_axis) +{ + uint32_t input_axis = (uint32_t)perm[output_axis]; + for (; elem != NULL; elem = elem->back_link) + { + if (elem->axis == input_axis) + { + return elem->index; + } + } + LL_ATON_ASSERT(false); // should never be reached + return 0; +} + +static inline int8_t *__ll_transp_get_output_base_pos(uint32_t inner_out_axis, + const __ll_transp_params_t *common_params, + __ll_stack_lnklst_t *linked_stack_list) +{ + LL_ATON_ASSERT(linked_stack_list != NULL); + int8_t *target = common_params->out_tensor; + + for (uint32_t output_axis = 0; output_axis < common_params->rank; output_axis++) + { + if (output_axis == inner_out_axis) + continue; + + uint32_t axis_size = common_params->out_axis_off[output_axis]; + uint32_t input_index = __ll_transp_find_input_index(linked_stack_list, common_params->perm, output_axis); + target += (input_index * axis_size); + } + + return target; +} + +static int8_t *__ll_transp_get_input_base_pos(const __ll_transp_params_t *common_params, + __ll_stack_lnklst_t *linked_stack_list) +{ + LL_ATON_ASSERT(linked_stack_list != NULL); + + const int8_t *target = common_params->in_tensor; + + LL_ATON_ASSERT(linked_stack_list->axis == (common_params->rank - 1)); + + for (__ll_stack_lnklst_t *elem = linked_stack_list->back_link; elem != NULL; elem = elem->back_link) + { + LL_ATON_ASSERT(elem->axis < (common_params->rank - 1)); + uint32_t axis_size = common_params->in_axis_off[elem->axis]; + target += (elem->index * axis_size); + } + + return (int8_t *)target; +} + +static void __ll_aton_lib_transpose(uint32_t curr_in_axis, uint32_t inner_out_axis, __ll_stack_lnklst_t *back_link, + const __ll_transp_params_t *common_params) +{ + __ll_stack_lnklst_t linked_stack_list = {.back_link = back_link, .axis = curr_in_axis, .index = 0}; + + if (curr_in_axis < (common_params->rank - 1)) + { // intermediate axis + for (; linked_stack_list.index < common_params->in_shape_aton[linked_stack_list.axis]; linked_stack_list.index++) + { + __ll_aton_lib_transpose(curr_in_axis + 1, inner_out_axis, &linked_stack_list, common_params); + } + } + else + { // last axis + LL_ATON_ASSERT(curr_in_axis == (common_params->rank - 1)); + + /* Calculate input/output base positions */ + int8_t *base_out_target = __ll_transp_get_output_base_pos(inner_out_axis, common_params, &linked_stack_list); + int8_t *base_in_target = __ll_transp_get_input_base_pos(common_params, &linked_stack_list); + uint32_t out_axes_offset = common_params->out_axis_off[inner_out_axis]; + + const uint32_t end_index = common_params->in_shape_aton[(common_params->rank - 1)]; + const uint8_t byte_size = common_params->byte_size; + + if (byte_size != out_axes_offset) + { + for (; linked_stack_list.index < end_index; linked_stack_list.index++) + { + /* determine input/output position */ + int8_t *in_target = base_in_target + (linked_stack_list.index * byte_size); + int8_t *out_target = base_out_target + (linked_stack_list.index * out_axes_offset); + + __ll_aton_lib_copy_element(byte_size, linked_stack_list.index, out_target, in_target); + } + } + else + { + uint32_t size_in_bytes = (end_index - linked_stack_list.index) * byte_size; // `byte_size == out_axes_offset` + + int8_t *in_target = base_in_target + (linked_stack_list.index * byte_size); + int8_t *out_target = + base_out_target + (linked_stack_list.index * out_axes_offset); // `byte_size == out_axes_offset` + + memcpy(out_target, in_target, size_in_bytes); + } + } +} + +static inline uint32_t __ll_transp_find_input_index_3or4(uint32_t *indexes, const uint8_t *perm, uint32_t output_axis) +{ + uint32_t input_axis = (uint32_t)perm[output_axis]; + return indexes[input_axis]; +} + +static inline int8_t *__ll_transp_get_output_base_pos_3or4(uint32_t inner_out_axis, + const __ll_transp_params_t *common_params, uint32_t *indexes) +{ + int8_t *target = common_params->out_tensor; + + for (uint32_t output_axis = 0; output_axis < common_params->rank; output_axis++) + { + if (output_axis == inner_out_axis) + continue; + + LL_ATON_ASSERT((uint32_t)common_params->perm[output_axis] < (common_params->rank - 1)); + + uint32_t input_index = __ll_transp_find_input_index_3or4(indexes, common_params->perm, output_axis); + uint32_t axis_size = common_params->out_axis_off[output_axis]; + target += (input_index * axis_size); + } + + return target; +} + +static int8_t *__ll_transp_get_input_base_pos_3or4(const __ll_transp_params_t *common_params, uint32_t *indexes) +{ + const int8_t *target = common_params->in_tensor; + + for (uint32_t axis = 0; axis < (common_params->rank - 1); axis++) + { + uint32_t axis_size = common_params->in_axis_off[axis]; + target += (indexes[axis] * axis_size); + } + + return (int8_t *)target; +} + +static inline uint32_t __ll_transp_get_inner_out_axis(const __ll_transp_params_t *common_params) +{ + for (unsigned int i = 0; i < common_params->rank; i++) + { + if (((uint32_t)common_params->perm[i]) == (common_params->rank - 1)) + return i; + } + LL_ATON_ASSERT(false); + return common_params->rank; // make compiler happy +} + +static void __ll_aton_lib_transpose_3or4(const __ll_transp_params_t *common_params) +{ + LL_ATON_ASSERT((common_params->rank == 4) || ((common_params->rank == 3))); + uint32_t inner_out_axis = __ll_transp_get_inner_out_axis(common_params); + uint32_t out_axes_offset = common_params->out_axis_off[inner_out_axis]; + const uint8_t byte_size = common_params->byte_size; + + uint32_t size_n = (common_params->rank == 4) ? common_params->in_shape_aton[0] : 1; + uint32_t size_c = (common_params->rank == 4) ? common_params->in_shape_aton[1] : common_params->in_shape_aton[0]; + uint32_t size_h = (common_params->rank == 4) ? common_params->in_shape_aton[2] : common_params->in_shape_aton[1]; + uint32_t size_w = (common_params->rank == 4) ? common_params->in_shape_aton[3] : common_params->in_shape_aton[2]; + + for (uint32_t index_n = 0; index_n < size_n; index_n++) + { + for (uint32_t index_c = 0; index_c < size_c; index_c++) + { + for (uint32_t index_h = 0; index_h < size_h; index_h++) + { + uint32_t indexes_array[] = {index_n, index_c, index_h}; + uint32_t *indexes = (common_params->rank == 4) ? &indexes_array[0] : &indexes_array[1]; + + int8_t *base_out_target = __ll_transp_get_output_base_pos_3or4(inner_out_axis, common_params, indexes); + int8_t *base_in_target = __ll_transp_get_input_base_pos_3or4(common_params, indexes); + + if (byte_size != out_axes_offset) + { + for (uint32_t index_w = 0; index_w < size_w; index_w++) + { + /* determine input/output position */ + int8_t *in_target = base_in_target + (index_w * byte_size); + int8_t *out_target = base_out_target + (index_w * out_axes_offset); + + __ll_aton_lib_copy_element(byte_size, index_w, out_target, in_target); + } + } + else + { + uint32_t size_in_bytes = size_w * byte_size; // `byte_size == out_axes_offset` + memcpy(base_out_target, base_in_target, size_in_bytes); + } + } + } + } +} + +int LL_ATON_LIB_Transpose(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + const uint8_t *perm) +{ + if (input->ndims <= 2) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->ndims != output->ndims) + { + __LL_LIB_ERROR(_ERR_RANK, LL_ATON_INVALID_PARAM); + } + + if (input->nbits != output->nbits) + { // TODO: should we support this? + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + if ((input->nbits < 8) || (input->nbits > 32)) + { + __LL_LIB_ERROR(_ERR_NBITS, LL_ATON_INVALID_PARAM); + } + + const __ll_transp_params_t common_params = {.perm = perm, + .rank = input->ndims, + .in_shape_aton = input->shape, + .in_axis_off = input_axes_offsets, + .out_axis_off = output_axes_offsets, + .byte_size = LL_LIB_NBYTES(input->nbits), + .in_tensor = (int8_t *)LL_Buffer_addr_start(input), + .out_tensor = (int8_t *)LL_Buffer_addr_start(output)}; + + if (input->ndims <= 4) + { + __ll_aton_lib_transpose_3or4(&common_params); + } + else + { + uint32_t inner_out_axis = __ll_transp_get_inner_out_axis(&common_params); + __ll_aton_lib_transpose(0, inner_out_axis, NULL, &common_params); + } + + return LL_ATON_OK; +} + +/** + * @brief performs a `Pad` operation on a (multi-dimensional) matrix + * @param input start address of input tensor + * @param output start address of output tensor + * @param min_shape shape obtained by performing element-wise `min` on each axis of reduced input vs output tensor + * @param mode where 0 == `constant`, 1 == `reflect`, 2 ==`edge` + * @param nbytes 8-bit or 16-bit mode + * @param out_elems number of output elements + * @param constant_value constant value to be `memset` + * @param consecutive_axis last input axis with all zero start/end paddings and whose following axes also have all + * zero paddings (or last axis) + * @param consecutive_elems number of consecutive elements to copy in each repetition + * @param pad_in_offsets_start vector containing amount (in bytes) of input padding data added at beginning of each + * axis + * @param pad_in_offsets_end vector containing amount (in bytes) of input padding data added at and of each axis + * @param pad_out_offsets_start vector containing amount (in bytes) of output padding data added at beginning of each + * axis + * @param pad_out_offsets_end vector containing amount (in bytes) of output padding data added at and of each axis + * @retval Error code + */ +static void *__ll_aton_lib_memset16(void *dst, int16_t c, size_t n) +{ + uintptr_t rest_addr = ((uintptr_t)dst) % 4; + int8_t *_dst = (int8_t *)dst; + + LL_ATON_ASSERT((rest_addr == 0) || (rest_addr == 2)); + if (rest_addr != 0) + { + *((int16_t *)dst) = (int16_t)c; + n -= 2; + _dst += 2; + } + + uint32_t rest_dim = n % 4; + LL_ATON_ASSERT((rest_dim == 0) || (rest_dim == 2)); + if (rest_dim != 0) + { + *((int16_t *)(_dst + n - 2)) = (int16_t)c; + n -= 2; + } + + LL_ATON_ASSERT((n % 4) == 0); + LL_ATON_ASSERT((n == 0) || ((((uintptr_t)_dst) % 4) == 0)); + + if (n > 0) + { + int32_t repetition_constant = (c << 16) | (0xFFFF & c); + for (unsigned int i = 0; i < n; i += 4) + { + *((int32_t *)(_dst + i)) = (int32_t)repetition_constant; + } + } + + return dst; +} + +static void *__ll_aton_lib_memset24(void *dst, int32_t c, size_t n) // NOTE: assuming no alignment +{ + int8_t *_dst = (int8_t *)dst; + int32_t num_elems = (n / 3); + LL_ATON_ASSERT((n % 3) == 0); + + for (int i = 0; i < num_elems; i++) + { + *_dst++ = c & 0xFF; + *_dst++ = (c >> 8) & 0xFF; + *_dst++ = (c >> 16) & 0xFF; + } + + return dst; +} + +static void *__ll_aton_lib_memset32(void *dst, int32_t c, size_t n) +{ + int32_t *_dst = (int32_t *)dst; + int32_t num_elems = (n / 4); + + LL_ATON_ASSERT((((uintptr_t)dst) % 4) == 0); + LL_ATON_ASSERT((n % 4) == 0); + + for (int i = 0; i < num_elems; i++) + { + *_dst++ = c; + } + + return dst; +} + +static inline void *__ll_aton_lib_memset(uint8_t nbytes, void *dst, int32_t c, size_t n) +{ + if (n > 0) + { + switch (nbytes) + { + case 1: + return memset(dst, c, n); + case 2: + return __ll_aton_lib_memset16(dst, c, n); + case 3: + return __ll_aton_lib_memset24(dst, c, n); + case 4: + return __ll_aton_lib_memset32(dst, c, n); + default: + LL_ATON_ASSERT(false); + return dst; + } + } + else + { + return dst; + } +} + +static inline uint32_t zero_neg(int32_t value) +{ + uint32_t ret = 0; + if (value > 0) + { + ret = value; + } + return ret; +} + +static inline void __ll_aton_lib_reflect_inner_framing_sw(uint32_t curr_axis, uint8_t nbytes, int8_t *dst, int8_t *src, + int32_t n_elems, int32_t length, bool start) +{ + LL_ATON_ASSERT(n_elems > 0); + if (nbytes == 2) + { + LL_ATON_ASSERT((((uintptr_t)src) % 2) == 0); + } + if (nbytes == 4) + { + LL_ATON_ASSERT((((uintptr_t)src) % 4) == 0); + } + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): reflect, curr_axis=%d, dst=%p, src=%p, min_shape_elems=%d, bytes=%d\n", __func__, __LINE__, + curr_axis, dst, src, n_elems, length); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + + bool forward = start; + + if (start) + { + int8_t *dst_ptr = dst + length - nbytes; + int32_t src_idx = (n_elems > 1) ? 1 : 0; + + for (; length > 0; length -= nbytes) + { + LL_ATON_ASSERT(dst_ptr >= dst); + LL_ATON_ASSERT(src_idx < n_elems); + LL_ATON_ASSERT(src_idx >= 0); + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): reflect, curr_axis=%d, dst=%p, src=%p, src_idx=%d, nbytes=%d\n", __func__, __LINE__, + curr_axis, dst_ptr, src, src_idx, nbytes); +#endif + + int8_t *src_ptr = (int8_t *)(&((int8_t *)src)[src_idx * nbytes]); + __ll_aton_lib_copy_element(nbytes, src_idx, dst_ptr, src_ptr); + + dst_ptr -= nbytes; + if (forward) + { + if (src_idx >= (n_elems - 1)) + { + forward = false; + src_idx = (n_elems > 1) ? (src_idx - 1) : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx + 1) : 0; + } + } + else + { + if (src_idx <= 0) + { + forward = true; + src_idx = (n_elems > 1) ? 1 : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx - 1) : 0; + } + } + } + } + else + { + int8_t *dst_ptr = dst; +#ifndef NDEBUG + int8_t *last_ptr = dst + length; +#endif + + int32_t src_idx = (n_elems > 1) ? -1 : 0; + for (; length > 0; length -= nbytes) + { + LL_ATON_ASSERT(dst_ptr < last_ptr); + LL_ATON_ASSERT((-src_idx) < n_elems); + LL_ATON_ASSERT(src_idx <= 0); + + int8_t *src_ptr = (int8_t *)(&((int8_t *)src)[src_idx * nbytes]); + __ll_aton_lib_copy_element(nbytes, src_idx, dst_ptr, src_ptr); + + dst_ptr += nbytes; + if (forward) + { + if (src_idx >= 0) + { + forward = false; + src_idx = (n_elems > 1) ? -1 : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx + 1) : 0; + } + } + else + { + if ((-src_idx) >= (n_elems - 1)) + { + forward = true; + src_idx = (n_elems > 1) ? (src_idx + 1) : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx - 1) : 0; + } + } + } + } +} + +static inline void __ll_aton_lib_edge_framing_sw(uint32_t curr_axis, uint8_t nbytes, void *dst, void *src, + int32_t length) +{ +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memset, curr_axis=%d, dst=%p, src=%p, bytes=%d\n", __func__, __LINE__, curr_axis, dst, src, + length); +#endif + __ll_aton_lib_memset(nbytes, dst, *((int32_t *)src), length); +} + +static void __ll_aton_lib_pad_filling_sw(uint32_t curr_axis, __ll_pad_sw_params_t *common_params) +{ + LL_ATON_ASSERT(curr_axis <= common_params->consecutive_axis); + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): in=%lx, out=%lx, curr_axis=%u, min_dim=%u, in_start=%d, out_start=%d\n", __func__, __LINE__, + (uintptr_t)common_params->in_target, (uintptr_t)common_params->out_target, curr_axis, + common_params->min_shape[curr_axis], common_params->pad_in_offsets_start[curr_axis], + common_params->pad_out_offsets_start[curr_axis]); +#endif + + if (common_params->pad_in_offsets_start[curr_axis] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_start[curr_axis]; + } + + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + common_params->out_target += common_params->pad_out_offsets_start[curr_axis]; + } + + if (curr_axis == common_params->consecutive_axis) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): ASSIGN in=%lx, out=%lx, bytes=%u\n", __func__, __LINE__, + (uintptr_t)common_params->in_target, (uintptr_t)common_params->out_target, + common_params->consecutive_bytes); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + + memcpy(common_params->out_target, common_params->in_target, common_params->consecutive_bytes); + common_params->in_target += common_params->consecutive_bytes; + common_params->out_target += common_params->consecutive_bytes; + + LL_ATON_ASSERT(common_params->out_target <= common_params->end_out_target); + } + else + { + for (uint32_t i = 0; i < common_params->min_shape[curr_axis]; i++) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): i=%" PRIu32 "\n", __func__, __LINE__, i); +#endif + + __ll_aton_lib_pad_filling_sw(curr_axis + 1, common_params); + } + } + + if (common_params->pad_out_offsets_end[curr_axis] > 0) + { + common_params->out_target += common_params->pad_out_offsets_end[curr_axis]; + LL_ATON_ASSERT(common_params->out_target <= common_params->end_out_target); + } + + if (common_params->pad_in_offsets_end[curr_axis] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_end[curr_axis]; + } + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): curr_axis=%u, in_end=%d, out_end=%d\n", __func__, __LINE__, curr_axis, + common_params->pad_in_offsets_end[curr_axis], common_params->pad_out_offsets_end[curr_axis]); +#endif +} + +static void __ll_aton_lib_pad_reflect_sw(uint32_t curr_axis, __ll_pad_sw_params_t *common_params, bool fill) +{ + LL_ATON_ASSERT(curr_axis <= (common_params->tensor_rank - 1)); + LL_ATON_ASSERT(common_params->pad_in_offsets_start[curr_axis] >= 0); + + int8_t *curr_out_ptr = common_params->out_target; + + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + common_params->out_target += common_params->pad_out_offsets_start[curr_axis]; + } + + if (curr_axis == (common_params->tensor_rank - 1)) + { + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + __ll_aton_lib_reflect_inner_framing_sw(curr_axis, common_params->nbytes, curr_out_ptr, common_params->in_target, + common_params->min_shape[curr_axis], + common_params->pad_out_offsets_start[curr_axis], true); + } + + int32_t filling_bytes = common_params->min_shape[curr_axis] * common_params->nbytes; + + if (fill) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memcpy, curr_axis=%d, dst=%p, src=%p, bytes=%d\n", __func__, __LINE__, curr_axis, + (int8_t *)common_params->out_target, (int8_t *)common_params->in_target, filling_bytes); +#endif + + memcpy(common_params->out_target, common_params->in_target, filling_bytes); + } + + common_params->in_target += filling_bytes; + common_params->out_target += filling_bytes; + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): out=%p, end=%p\n", __func__, __LINE__, (int8_t *)common_params->out_target, + (int8_t *)common_params->end_out_target); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + LL_ATON_ASSERT(common_params->out_target <= common_params->end_out_target); + } + else + { + for (int i = 0; i < common_params->min_shape[curr_axis]; i++) + { + __ll_aton_lib_pad_reflect_sw(curr_axis + 1, common_params, fill); + } + + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + int32_t pad_start = common_params->pad_out_offsets_start[curr_axis] / + common_params->out_offsets[curr_axis]; // i.e.: pads_start[curr_axis]; + int32_t pad_end = common_params->pad_out_offsets_end[curr_axis] / + common_params->out_offsets[curr_axis]; // i.e.: pads_end[curr_axis]; + + LL_ATON_ASSERT(pad_end >= 0); + + int32_t nr_loops = pad_start; + int32_t n_elems = common_params->out_shape[curr_axis] - pad_start - pad_end; + int32_t padding_bytes = common_params->out_offsets[curr_axis]; + + int8_t *dst_ptr = curr_out_ptr + common_params->pad_out_offsets_start[curr_axis] - padding_bytes; + int8_t *src_ptr = curr_out_ptr + common_params->pad_out_offsets_start[curr_axis]; + + int32_t src_idx = (n_elems > 1) ? 1 : 0; + + bool forward = true; + for (int i = 0; i < nr_loops; i++) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memcpy, curr_axis=%d, dst=%p, src=%p, src_idx=%d, bytes=%d, n_elems=%d, times=%d/%d\n", + __func__, __LINE__, curr_axis, (int8_t *)dst_ptr, (int8_t *)src_ptr + (src_idx * padding_bytes), + src_idx, padding_bytes, n_elems, i + 1, nr_loops); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + LL_ATON_ASSERT(dst_ptr >= curr_out_ptr); + LL_ATON_ASSERT(src_idx < n_elems); + LL_ATON_ASSERT(src_idx >= 0); + + memcpy(dst_ptr, src_ptr + (src_idx * padding_bytes), padding_bytes); + + dst_ptr -= padding_bytes; + + if (forward) + { + if (src_idx >= (n_elems - 1)) + { + forward = false; + src_idx = (n_elems > 1) ? (src_idx - 1) : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx + 1) : 0; + } + } + else + { + if (src_idx <= 0) + { + forward = true; + src_idx = (n_elems > 1) ? 1 : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx - 1) : 0; + } + } + } + } + } + + if (common_params->pad_out_offsets_end[curr_axis] > 0) + { + if (curr_axis == (common_params->tensor_rank - 1)) + { + int8_t *src_ptr = common_params->out_target - common_params->nbytes; + __ll_aton_lib_reflect_inner_framing_sw(curr_axis, common_params->nbytes, common_params->out_target, src_ptr, + common_params->min_shape[curr_axis], + common_params->pad_out_offsets_end[curr_axis], false); + } + else + { + int32_t pad_start = common_params->pad_out_offsets_start[curr_axis] / + common_params->out_offsets[curr_axis]; // i.e.: pads_start[curr_axis]; + int32_t pad_end = common_params->pad_out_offsets_end[curr_axis] / + common_params->out_offsets[curr_axis]; // i.e.: pads_end[curr_axis]; + + int32_t nr_loops = pad_end; + + int32_t padding_bytes = common_params->out_offsets[curr_axis]; + int32_t n_elems = common_params->out_shape[curr_axis] - zero_neg(pad_start) - zero_neg(pad_end); + + int8_t *dst_ptr = common_params->out_target; + int8_t *src_ptr = common_params->out_target - padding_bytes; + + int32_t src_idx = (n_elems > 1) ? -1 : 0; + + bool forward = false; + for (int i = 0; i < nr_loops; i++) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memcpy, curr_axis=%d, dst=%p, src=%p, src_idx=%d, bytes=%d, n_elems=%d, times=%d/%d\n", + __func__, __LINE__, curr_axis, (int8_t *)dst_ptr, (int8_t *)src_ptr + (src_idx * padding_bytes), + src_idx, padding_bytes, n_elems, i + 1, nr_loops); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + LL_ATON_ASSERT(dst_ptr < (dst_ptr + common_params->pad_out_offsets_end[curr_axis])); + LL_ATON_ASSERT((-src_idx) < n_elems); + LL_ATON_ASSERT(src_idx <= 0); + + memcpy(dst_ptr, src_ptr + (src_idx * padding_bytes), padding_bytes); + + dst_ptr += padding_bytes; + if (forward) + { + if (src_idx >= 0) + { + forward = false; + src_idx = (n_elems > 1) ? -1 : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx + 1) : 0; + } + } + else + { + if ((-src_idx) >= (n_elems - 1)) + { + forward = true; + src_idx = (n_elems > 1) ? (src_idx + 1) : 0; + } + else + { + src_idx = (n_elems > 1) ? (src_idx - 1) : 0; + } + } + } + } + + common_params->out_target += common_params->pad_out_offsets_end[curr_axis]; + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): out=%p, end=%p\n", __func__, __LINE__, (int8_t *)common_params->out_target, + (int8_t *)common_params->end_out_target); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + LL_ATON_ASSERT(common_params->out_target <= common_params->end_out_target); + } + + LL_ATON_ASSERT(common_params->pad_in_offsets_end[curr_axis] >= 0); +} + +static void __ll_aton_lib_pad_edge_sw(uint32_t curr_axis, __ll_pad_sw_params_t *common_params, bool fill) +{ + LL_ATON_ASSERT(curr_axis <= (common_params->tensor_rank - 1)); + + if (common_params->pad_in_offsets_start[curr_axis] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_start[curr_axis]; + } + + int8_t *curr_out_ptr = common_params->out_target; + + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + common_params->out_target += common_params->pad_out_offsets_start[curr_axis]; + } + + if (curr_axis == (common_params->tensor_rank - 1)) + { + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + __ll_aton_lib_edge_framing_sw(curr_axis, common_params->nbytes, curr_out_ptr, common_params->in_target, + common_params->pad_out_offsets_start[curr_axis]); + } + + int32_t filling_bytes = common_params->min_shape[curr_axis] * common_params->nbytes; + + if (fill) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memcpy, curr_axis=%d, dst=%p, src=%p, bytes=%d\n", __func__, __LINE__, curr_axis, + (int8_t *)common_params->out_target, (int8_t *)common_params->in_target, filling_bytes); +#endif + + memcpy(common_params->out_target, common_params->in_target, filling_bytes); + } + + common_params->in_target += filling_bytes; + common_params->out_target += filling_bytes; + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): out=%p, end=%p\n", __func__, __LINE__, (int8_t *)common_params->out_target, + (int8_t *)common_params->end_out_target); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + LL_ATON_ASSERT(common_params->out_target <= common_params->end_out_target); + } + else + { + for (int i = 0; i < common_params->min_shape[curr_axis]; i++) + { + __ll_aton_lib_pad_edge_sw(curr_axis + 1, common_params, fill); + } + + if (common_params->pad_out_offsets_start[curr_axis] > 0) + { + int32_t nr_loops = common_params->pad_out_offsets_start[curr_axis] / + common_params->out_offsets[curr_axis]; // i.e.: pads_start[curr_axis]; + int32_t padding_bytes = common_params->pad_out_offsets_start[curr_axis] / nr_loops; + + int8_t *dst_ptr = curr_out_ptr; + int8_t *src_ptr = curr_out_ptr + common_params->pad_out_offsets_start[curr_axis]; + + for (int i = 0; i < nr_loops; i++) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memcpy, curr_axis=%d, dst=%p, src=%p, bytes=%d, times=%d/%d\n", __func__, __LINE__, + curr_axis, (int8_t *)dst_ptr, (int8_t *)src_ptr, padding_bytes, i + 1, nr_loops); +#endif + memcpy(dst_ptr, src_ptr, padding_bytes); + dst_ptr += padding_bytes; + } + } + } + + if (common_params->pad_out_offsets_end[curr_axis] > 0) + { + if (curr_axis == (common_params->tensor_rank - 1)) + { + __ll_aton_lib_edge_framing_sw(curr_axis, common_params->nbytes, common_params->out_target, + (common_params->out_target - common_params->nbytes), + common_params->pad_out_offsets_end[curr_axis]); + } + else + { + int32_t nr_loops = common_params->pad_out_offsets_end[curr_axis] / + common_params->out_offsets[curr_axis]; // i.e. pads_end[curr_axis]; + int32_t padding_bytes = common_params->pad_out_offsets_end[curr_axis] / nr_loops; + + int8_t *dst_ptr = common_params->out_target; + int8_t *src_ptr = common_params->out_target - (common_params->pad_out_offsets_end[curr_axis] / nr_loops); + + for (int i = 0; i < nr_loops; i++) + { +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): memcpy, curr_axis=%d, dst=%p, src=%p, bytes=%d, times=%d/%d\n", __func__, __LINE__, + curr_axis, (int8_t *)dst_ptr, (int8_t *)src_ptr, padding_bytes, i + 1, nr_loops); +#endif + memcpy(dst_ptr, src_ptr, padding_bytes); + dst_ptr += padding_bytes; + } + } + + common_params->out_target += common_params->pad_out_offsets_end[curr_axis]; + +#if defined(DUMP_DEBUG_SW_OPS) + LL_ATON_PRINTF("%s(%d): out=%p, end=%p\n", __func__, __LINE__, (int8_t *)common_params->out_target, + (int8_t *)common_params->end_out_target); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif +#endif + LL_ATON_ASSERT(common_params->out_target <= common_params->end_out_target); + } + + if (common_params->pad_in_offsets_end[curr_axis] < 0) + { + common_params->in_target -= common_params->pad_in_offsets_end[curr_axis]; + } +} + +static int __ll_aton_lib_pad_filling(__ll_pad_sw_params_t *common_params) +{ +#ifndef NDEBUG + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); +#endif // NDEBUG + +#if defined(DUMP_RESULTS_PAD_OP) + int8_t *out_target = common_params->out_target; +#endif // DUMP_RESULTS_PAD_OP + + /* check if there is something to do */ + if (common_params->consecutive_bytes == 0) + { + goto dump_results; // nothing needs to be copied/filled in (just `memset`), so we are done! + } + + /* fill with content */ + if ((common_params->consecutive_bytes < __LL_PAD_FILLING_DMA_MIN_BUFF_LEN) || + (common_params->tensor_rank > __LL_DMA_PAD_MAX_DIMS)) + { // do it without HW support + __ll_aton_lib_pad_filling_sw(0, common_params); + + if (common_params->callback_function != NULL) /* take this as indication for "called as callback" */ + { + if ((common_params->end_out_target - common_params->saved_out_target) > 0) + { + /* *** MCU cache clean operation (SW) *** */ + uint32_t size = (uintptr_t)(common_params->end_out_target) - (uintptr_t)(common_params->saved_out_target); + LL_ATON_Cache_MCU_Clean_Range(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR((uintptr_t)common_params->saved_out_target), + size); + } + } + + dump_results: +#if defined(DUMP_RESULTS_PAD_OP) + /* debug output print */ + switch (common_params->nbytes) + { + case 1: + { + int8_t *ptr = (int8_t *)out_target; + for (uint32_t i = 0; i < common_params->out_size; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 2: + { + int16_t *ptr = (int16_t *)(int8_t *)out_target; + for (uint32_t i = 0; i < common_params->out_size / 2; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 3: // NOTE: assuming no alignment + { + /* check endianess */ + const int32_t _const_val = 0x01020304; + const int8_t *_const_val_ptr = (int8_t *)&_const_val; + bool is_little_endian = (_const_val_ptr[0] == 0x04); + + int8_t *ptr = (int8_t *)out_target; + if (is_little_endian) + { + for (uint32_t i = 0; i < common_params->out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i]; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2] << 16; + + LL_ATON_PRINTF("%d\n", value); + } + } + else + { + for (uint32_t i = 0; i < common_params->out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i] << 16; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2]; + + LL_ATON_PRINTF("%d\n", value); + } + } + } + break; + case 4: + { + int32_t *ptr = (int32_t *)(int8_t *)out_target; + for (uint32_t i = 0; i < common_params->out_size / 4; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + default: + LL_ATON_ASSERT(false); + break; + } +#endif // DUMP_RESULTS_PAD_OP + + return LL_ATON_OK; + } + else + { // perform second phase in HW + if (common_params->callback_function != NULL) /* take this as indication for "called as callback" */ + { + common_params->callback_function = NULL; + return LL_ATON_LIB_DMA_Pad_Filling(NULL); + } + else + { // not a callback => `memset` (i.e. `framing`) has been executed in SW + if ((common_params->end_out_target - common_params->saved_out_target) > 0) + { + /* *** MCU cache clean & invalidate operation (SW) *** */ + uint32_t size = (uintptr_t)(common_params->end_out_target) - (uintptr_t)(common_params->saved_out_target); + LL_ATON_Cache_MCU_Clean_Invalidate_Range( + ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR((uintptr_t)common_params->saved_out_target), size); + } + + return LL_ATON_LIB_DMA_Pad_Filling(common_params); + } + } +} + +static int __ll_aton_lib_pad_framing_sw(__ll_pad_sw_params_t *common_params) +{ +#ifndef NDEBUG + extern NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner; + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); +#endif // NDEBUG + + /* reset input/output target pointers */ + common_params->in_target = common_params->saved_in_target; + common_params->out_target = common_params->saved_out_target; + +#if defined(DUMP_RESULTS_PAD_OP) + int8_t *out_target = common_params->out_target; +#endif // DUMP_RESULTS_PAD_OP + + switch (common_params->mode) + { + case 1: // `reflect` mode + __ll_aton_lib_pad_reflect_sw(0, common_params, false); + break; + + case 2: // `edge` mode + __ll_aton_lib_pad_edge_sw(0, common_params, false); + break; + + default: + __LL_LIB_ERROR(_ERR_MODE, LL_ATON_INVALID_PARAM) + } + + LL_ATON_ASSERT(common_params->callback_function != NULL); /* always "called as callback" */ + if ((common_params->end_out_target - common_params->saved_out_target) > 0) + { + /* *** MCU cache clean operation (SW) *** */ + uint32_t size = (uintptr_t)(common_params->end_out_target) - (uintptr_t)(common_params->saved_out_target); + LL_ATON_Cache_MCU_Clean_Range(ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR((uintptr_t)common_params->saved_out_target), size); + } + +#if defined(DUMP_RESULTS_PAD_OP) + /* debug output print */ + switch (common_params->nbytes) + { + case 1: + { + int8_t *ptr = (int8_t *)out_target; + for (uint32_t i = 0; i < common_params->out_size; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 2: + { + int16_t *ptr = (int16_t *)(int8_t *)out_target; + for (uint32_t i = 0; i < common_params->out_size / 2; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 3: // NOTE: assuming no alignment + { + /* check endianess */ + const int32_t _const_val = 0x01020304; + const int8_t *_const_val_ptr = (int8_t *)&_const_val; + bool is_little_endian = (_const_val_ptr[0] == 0x04); + + int8_t *ptr = (int8_t *)out_target; + if (is_little_endian) + { + for (uint32_t i = 0; i < common_params->out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i]; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2] << 16; + + LL_ATON_PRINTF("%d\n", value); + } + } + else + { + for (uint32_t i = 0; i < common_params->out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i] << 16; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2]; + + LL_ATON_PRINTF("%d\n", value); + } + } + } + break; + case 4: + { + int32_t *ptr = (int32_t *)(int8_t *)out_target; + for (uint32_t i = 0; i < common_params->out_size / 4; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + default: + LL_ATON_ASSERT(false); + break; + } +#endif // DUMP_RESULTS_PAD_OP + + return LL_ATON_OK; +} + +int LL_ATON_LIB_Pad(unsigned char *input, unsigned char *output, unsigned char *input_limit, + unsigned char *output_limit, const uint32_t *min_shape, uint8_t mode, uint8_t nbytes, + uint32_t out_elems, int32_t constant_value, uint32_t consecutive_axis, uint32_t consecutive_elems, + const int32_t *pad_in_offsets_start, const int32_t *pad_in_offsets_end, + const int32_t *pad_out_offsets_start, const int32_t *pad_out_offsets_end, const int32_t *out_shape, + const int32_t *out_offsets, size_t tensor_rank, int dma_in, int dma_out) +{ + LL_ATON_ASSERT(dma_in >= 0); + LL_ATON_ASSERT(dma_out >= 0); + + size_t out_size = out_elems * nbytes; + uint32_t consecutive_bytes = consecutive_elems * nbytes; + + __ll_pad_sw_params_t common_params = { + .in_target = (int8_t *)input, + .out_target = (int8_t *)output, + .in_limit = (int8_t *)input_limit, + .out_limit = (int8_t *)output_limit, + .nbytes = nbytes, + .mode = mode, + .tensor_rank = tensor_rank, + .saved_in_target = (int8_t *)input, + .saved_out_target = (int8_t *)output, + .end_out_target = (int8_t *)output + out_size, + .callback_function = NULL, + .consecutive_axis = consecutive_axis, + .consecutive_bytes = consecutive_bytes, + .dma_in = dma_in, + .dma_out = dma_out, +#if defined(DUMP_RESULTS_PAD_OP) + .out_size = out_size, +#endif + + .min_shape = min_shape, + .pad_in_offsets_start = pad_in_offsets_start, + .pad_in_offsets_end = pad_in_offsets_end, + .pad_out_offsets_start = pad_out_offsets_start, + .pad_out_offsets_end = pad_out_offsets_end, + .out_shape = out_shape, + .out_offsets = out_offsets, + }; + + if (consecutive_bytes == 0) + { + // corner case: nothing needs to be copied/filled in (just `memset`), align with `onnxruntime (v1.2.0)` + // reference implementation + constant_value = 0; + } + + switch (mode) + { + case 0: // `constant` mode + /* fill output with constant value + (TODO: trade-off between one shot and multiple single short shots - without overwriting non constant value + ranges - still to be evaluated) */ + if ((out_size < __LL_PAD_FRAMING_DMA_MIN_BUFF_LEN) || (tensor_rank > __LL_DMA_PAD_MAX_DIMS)) + { + __ll_aton_lib_memset(nbytes, (int8_t *)output, constant_value, out_size); + return __ll_aton_lib_pad_filling(&common_params); + } + else + { + common_params.callback_function = (pad_callback_func_t)&__ll_aton_lib_pad_filling; + return LL_ATON_LIB_DMA_Pad_Memset((int8_t *)output, constant_value, out_size, + &common_params); // first phase (in this case `framing`) is made in HW + } + + case 1: // `reflect` mode + if ((consecutive_bytes < __LL_PAD_FILLING_DMA_MIN_BUFF_LEN) || (tensor_rank > __LL_DMA_PAD_MAX_DIMS)) + { // do it without HW support + __ll_aton_lib_pad_reflect_sw(0, &common_params, true); // all (i.e. `filling` & `framing`) is done in SW + } + else + { + common_params.callback_function = (pad_callback_func_t)&__ll_aton_lib_pad_framing_sw; + return LL_ATON_LIB_DMA_Pad_Filling(&common_params); // first phase (in this case `filling`) is made in HW + } + break; + + case 2: // `edge` mode + if ((consecutive_bytes < __LL_PAD_FILLING_DMA_MIN_BUFF_LEN) || (tensor_rank > __LL_DMA_PAD_MAX_DIMS)) + { // do it without HW support + __ll_aton_lib_pad_edge_sw(0, &common_params, true); // all is done in SW + } + else + { + common_params.callback_function = (pad_callback_func_t)&__ll_aton_lib_pad_framing_sw; + return LL_ATON_LIB_DMA_Pad_Filling(&common_params); // first phase (in this case `filling`) is made in HW + } + break; + + default: + __LL_LIB_ERROR(_ERR_MODE, LL_ATON_INVALID_PARAM) + } + +#if defined(DUMP_RESULTS_PAD_OP) + /* debug output print */ + switch (common_params.nbytes) + { + case 1: + { + int8_t *ptr = (int8_t *)output; + for (uint32_t i = 0; i < common_params.out_size; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 2: + { + int16_t *ptr = (int16_t *)(int8_t *)output; + for (uint32_t i = 0; i < common_params.out_size / 2; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + case 3: // NOTE: assuming no alignment + { + /* check endianess */ + const int32_t _const_val = 0x01020304; + const int8_t *_const_val_ptr = (int8_t *)&_const_val; + bool is_little_endian = (_const_val_ptr[0] == 0x04); + + int8_t *ptr = (int8_t *)output; + if (is_little_endian) + { + for (uint32_t i = 0; i < common_params.out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i]; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2] << 16; + + LL_ATON_PRINTF("%d\n", value); + } + } + else + { + for (uint32_t i = 0; i < common_params.out_size / 3; i += 3) + { + int32_t value = 0; + + value |= ptr[i] << 16; + value |= ptr[i + 1] << 8; + value |= ptr[i + 2]; + + LL_ATON_PRINTF("%d\n", value); + } + } + } + break; + case 4: + { + int32_t *ptr = (int32_t *)(int8_t *)output; + for (uint32_t i = 0; i < common_params.out_size / 4; i++) + { + LL_ATON_PRINTF("%d\n", ptr[i]); + } + } + break; + default: + LL_ATON_ASSERT(false); + break; + } +#endif // DUMP_RESULTS_PAD_OP + + return LL_ATON_OK; +} diff --git a/lib/stai/libstai/ll_aton/ll_aton_osal_freertos.c b/lib/stai/libstai/ll_aton/ll_aton_osal_freertos.c new file mode 100644 index 000000000..be6b8bce5 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_osal_freertos.c @@ -0,0 +1,39 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_freertos.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface to FreeRTOS as the underlying OS/platform for ATON + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_config.h" + +#if (LL_ATON_OSAL == LL_ATON_OSAL_FREERTOS) + +#include +#include +#include + +/* FreeRTOS include */ +#include "ll_aton_osal_freertos.h" + +/*** FreeRTOS dependent static variables ***/ +static StaticSemaphore_t _dao_mutex_buffer; // buffer for `_dao_mutex` which holds its state +static StaticSemaphore_t _dao_wait_queue_buffer; // buffer for `_dao_wait_queue` which holds its state +static StaticSemaphore_t _wfe_sem_buffer; // buffer for `_wfe_sem` which holds its state +static StaticSemaphore_t _cache_mutex_buffer; // buffer for `_cache_mutex` which holds its state + +/* Include common RTOS `.c` template */ +#include "ll_aton_osal_rtos_template.c" + +#endif // (LL_ATON_OSAL == LL_ATON_OSAL_FREERTOS) diff --git a/lib/stai/libstai/ll_aton/ll_aton_osal_rtos_template.c b/lib/stai/libstai/ll_aton/ll_aton_osal_rtos_template.c new file mode 100644 index 000000000..94efac5af --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_osal_rtos_template.c @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_rtos_template.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Generic template implementation of DAO mutex mechanism + * (underlying OS/platform agnostic) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/************************* +The beyond "Deferred ATON Owner" (aka "DAO") mutex mechanism implements a mutex which on unlock does +not immediately assign a new owner to the mutex but forces waiters to try to re-acquire the mutex again. +This allows a higher priority thread to re-acquire the mutex again before a lower priority thread, which +is waiting. +It comes together with a "hand-made" priority inheritance mechanism, which requires that the +priority of a network/inference task is not changed during the execution of an epoch(-block)! +*************************/ + +/* Static variables on the basis of this locking mechanism */ +static _DaoMutexNoWaitersType_ _dao_mutex; // handle for main FIFO mutex of the "deferred ATON owner" mechanism +static _DaoWaitQueueType_ _dao_wait_queue; // semaphore for threads waiting for `_dao_mutex` + +#if APP_HAS_PARALLEL_NETWORKS + +// current owner of ATON +static _TaskHandleType_ _current_aton_owner = _NullHandle_; +// original priority of current ATON owner (assuming that `_PriorityType_` is a regular integer type) +static _PriorityType_ _current_aton_owner_orig_priority = 0; +// number of threads waiting on `_dao_wait_queue` +volatile static uint32_t _nr_dao_waiters = 0; + +#endif // APP_HAS_PARALLEL_NETWORKS + +static _WfeSemaphoreType_ _wfe_sem; // for WFE blocking and IRQ signalling +static _CacheMutexType_ _cache_mutex; // for non deferred locking/unlocking (e.g. NPU/MCU cache operation protection) + +/*** API functions ***/ + +/** + * @brief Initialize RTOS OSAL implementation + */ +void LL_ATON_OSAL_INIT() +{ + _InitNonDao_(); // initialize non DAO part + + /* create main "deferred ATON owner" mechanism mutex */ + _ReturnType_ ret = _CreateDaoMutexNoWaiters_( + _dao_mutex, + _dao_mutex_buffer); // no thread will ever wait on this "conceptional" mutex + // (so priority inheritance - as would come with a "real" mutex - is not needed) + assert(ret == _OsTrue_); + _MakeDaoMutexNoWaitersAvailable_(_dao_mutex); // make it available + + /* create "deferred ATON owner" mechanism semaphore */ + ret = _CreateDaoWaitQueue_(_dao_wait_queue, _dao_wait_queue_buffer); + assert(ret == _OsTrue_); + _MakeDaoWaitQueueUnavailable_(_dao_wait_queue); // make it un-available + + /* create WFE semaphore */ + ret = _CreateWfeSemaphore_(_wfe_sem, _wfe_sem_buffer); + assert(ret == _OsTrue_); + _MakeWfeSemaphoreUnavailable_(_wfe_sem); // make it un-available + + /* create cache mutex */ + ret = _CreateCacheMutex_(_cache_mutex, _cache_mutex_buffer); + assert(ret == _OsTrue_); + _MakeCacheMutexAvailable_(_cache_mutex); // make it available + + /* Finalize IRQ handling (e.g. priority) */ + _FinalizeIRQHandling_(); +} + +/** + * @brief De-initialize RTOS OSAL implementation + */ +void LL_ATON_OSAL_DEINIT() +{ + _DeInitNonDao_(); // de-initialize non DAO part +} + +#if APP_HAS_PARALLEL_NETWORKS +/** + * @brief Lock priority base mutex + */ +void LL_ATON_OSAL_LOCK_ATON() +{ + _ReturnType_ ret; + + // disable preemption + _DisablePreemption_(); + + // Get current thread + _TaskHandleType_ current_thread = _GetCurrentTaskHandle_(); + assert(current_thread != _NullHandle_); // there should be a current thread + + do + { + ret = _GetDaoMutexNoWaiters_(_dao_mutex); // never block + + _PriorityType_ current_thread_priority = _GetTaskPriority_( + current_thread); // get current thread's priority (might have change while waiting on `_dao_wait_queue`) + + if (ret == _OsTrue_) + { // we have gotten the mutex + // perform current owner housekeeping + assert(_current_aton_owner == _NullHandle_); // there should be no current owner + _current_aton_owner = current_thread; + _current_aton_owner_orig_priority = current_thread_priority; + + // enable preemption + _EnablePreemption_(); + + return; // we are done + } + else + { // didn't get mutex + // increase current owner's priority if necessary + assert(_current_aton_owner != _NullHandle_); // there should be a current owner + + // check for necessity for priority inheritance + if (_FirstPrioHigherThanScnd_(current_thread_priority, _GetTaskPriority_(_current_aton_owner))) + { + // increase owner's priority + assert(_current_aton_owner != current_thread); + _SetTaskPriority_(_current_aton_owner, current_thread_priority); + } + + // increment waiters counter + _nr_dao_waiters++; + + // enable preemption + _EnablePreemption_(); + + /* wait on wait queue semaphore */ + ret = _GetDaoWaitQueue_(_dao_wait_queue); // block on wait queue + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); + + // disable preemption + _DisablePreemption_(); + + // decrement waiters counter + assert(_nr_dao_waiters > 0); + _nr_dao_waiters--; + + // re-try to get the mutex + } + } while (1); +} + +/** + * @brief Unlock "deferred ATON owner" mutex + */ +void LL_ATON_OSAL_UNLOCK_ATON() +{ + _ReturnType_ ret; + bool do_yield = false; + + // disable preemption + _DisablePreemption_(); + + /* release `_dao_mutex` */ + ret = _ReleaseDaoMutexNoWaiters_(_dao_mutex); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); + + // check if priority has changed while having been the ATON owner + assert(_current_aton_owner == _GetCurrentTaskHandle_()); + if (_current_aton_owner_orig_priority != _GetTaskPriority_(_current_aton_owner)) + { + _SetTaskPriority_(_current_aton_owner, _current_aton_owner_orig_priority); // restore original priority + } + _current_aton_owner = _NullHandle_; + _current_aton_owner_orig_priority = 0; + + // assert that `_dao_wait_queue`'s value is 0 or 1 + _DaoWaitQueueValueType_ dao_wait_queue_val = _GetDaoWaitQueueValue_(_dao_wait_queue); + assert(dao_wait_queue_val <= 1); // assuming that `_DaoWaitQueueValueType_` is a regular integer type + + // in case of waiters release `_dao_wait_queue` semaphore (if not already available) + if (_nr_dao_waiters > 0) + { + // force a yield after enableing preemption + do_yield = true; + + // increment semaphore + if (dao_wait_queue_val == 0) + { + ret = _ReleaseDaoWaitQueue_(_dao_wait_queue); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); + } + } + + // enable preemption + _EnablePreemption_(); + + if (do_yield) + { + /* give other tasks of same priority a better chance to run + and do not wait for the next timer tick or time-slice end */ + _YieldCurrentTask_(); + } +} +#endif // APP_HAS_PARALLEL_NETWORKS + +#ifndef LL_HAS_NO_ATON_OSAL_LOCK_NPU_CACHE +/** + * @brief Lock cache mutex + */ +void LL_ATON_OSAL_LOCK_NPU_CACHE() +{ + _ReturnType_ ret; + + ret = _GetCacheMutex_(_cache_mutex); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); +} + +/** + * @brief Unlock cache mutex + */ +void LL_ATON_OSAL_UNLOCK_NPU_CACHE() +{ + _ReturnType_ ret; + + ret = _ReleaseCacheMutex_(_cache_mutex); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); +} +#endif // LL_HAS_NO_ATON_OSAL_LOCK_NPU_CACHE + +#ifndef LL_HAS_NO_ATON_OSAL_LOCK_MCU_CACHE +/** + * @brief Lock cache mutex + */ +void LL_ATON_OSAL_LOCK_MCU_CACHE() +{ + _ReturnType_ ret; + + ret = _GetCacheMutex_(_cache_mutex); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); +} + +/** + * @brief Unlock cache mutex + */ +void LL_ATON_OSAL_UNLOCK_MCU_CACHE() +{ + _ReturnType_ ret; + + ret = _ReleaseCacheMutex_(_cache_mutex); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); +} +#endif // LL_HAS_NO_ATON_OSAL_LOCK_MCU_CACHE + +/** + * @brief Wait for event + */ +void LL_ATON_OSAL_WFE() +{ + _ReturnType_ ret; + + ret = _GetWfeSemaphore_(_wfe_sem); + assert(ret == _OsTrue_); + LL_ATON_LIB_UNUSED(ret); +} + +/** + * @brief Signal event + * @note Define macro `RTOS_HAS_NO_ISR_SIGNAL` if signalling is not performed from an interrupt handler. + * Calling this function within the same application from both ISR and normal contexts is currently not + * supported! + */ +void LL_ATON_OSAL_SIGNAL_EVENT() +{ + _ReturnType_ ret; + +#ifdef RTOS_HAS_NO_ISR_SIGNAL + ret = _ReleaseWfeSemaphore_(_wfe_sem); // assuming that this function gets NOT called from within an interrupt handler + assert(ret == _OsTrue_); +#else // !RTOS_HAS_NO_ISR_SIGNAL + _ReturnType_ task_woken; + + _HeadIsrCode_(); + ret = _ReleaseWfeSemaphoreISR_( + _wfe_sem, &task_woken); // assuming that this function gets called from within an interrupt handler + assert(ret == _OsTrue_); + _TailIsrCode_(task_woken); + + LL_ATON_LIB_UNUSED(task_woken); +#endif // !RTOS_HAS_NO_ISR_SIGNAL + + LL_ATON_LIB_UNUSED(ret); +} diff --git a/lib/stai/libstai/ll_aton/ll_aton_osal_threadx.c b/lib/stai/libstai/ll_aton/ll_aton_osal_threadx.c new file mode 100644 index 000000000..e70c1f59b --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_osal_threadx.c @@ -0,0 +1,33 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_threadx.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface to ThreadX as the underlying OS/platform for ATON + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_config.h" + +#if (LL_ATON_OSAL == LL_ATON_OSAL_THREADX) + +#include +#include +#include + +/* ThreadX include */ +#include "ll_aton_osal_threadx.h" + +/* Include common RTOS `.c` template */ +#include "ll_aton_osal_rtos_template.c" + +#endif // (LL_ATON_OSAL == LL_ATON_OSAL_THREADX) diff --git a/lib/stai/libstai/ll_aton/ll_aton_osal_zephyr.c b/lib/stai/libstai/ll_aton/ll_aton_osal_zephyr.c new file mode 100644 index 000000000..bc60be93f --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_osal_zephyr.c @@ -0,0 +1,143 @@ +/** + ****************************************************************************** + * @file ll_aton_osal_zephyr.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Interface to Zephyr as the underlying OS/platform for ATON + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_config.h" + +#if (LL_ATON_OSAL == LL_ATON_OSAL_ZEPHYR) + +#include +#include +#include + +/* Zephyr include */ +#include "ll_aton_osal_zephyr.h" + +/* IRQ OSAL handling */ +static void (*aton_irq_handler)(void) = NULL; +static int aton_irq_number = -1; + +static inline int _zephyr_get_irq_nr_from_aton_line_number(int aton_line_number) +{ + switch (aton_line_number) + { + case 0: + return CDNN0_IRQn; + case 1: + return CDNN1_IRQn; + case 2: + return CDNN2_IRQn; + case 3: + return CDNN3_IRQn; + default: + assert(0); + return -1; + } +} + +/** + * @brief + * @param arg + */ +static void aton_osal_zephyr_isr(const void *arg) +{ + LL_ATON_LIB_UNUSED(arg); + assert(aton_irq_handler != NULL); + assert(aton_irq_number >= 0); + + aton_irq_handler(); +} + +/** + * @brief install IRQ handler + * @param aton_line_number interrupt for which to install `handler` + * @param handler interrupt handler + */ +void aton_osal_zephyr_install_irq(int aton_line_number, void (*handler)(void)) +{ + assert(aton_irq_handler == NULL); + assert(aton_irq_number < 0); + + aton_irq_handler = handler; + aton_irq_number = _zephyr_get_irq_nr_from_aton_line_number(aton_line_number); + + irq_connect_dynamic(aton_irq_number, 0, aton_osal_zephyr_isr, NULL, 0); +} + +/** + * @brief + * @param aton_line_number + */ +void aton_osal_zephyr_uninstall_irq(int aton_line_number) +{ + assert(aton_irq_handler != NULL); + assert(aton_irq_number >= 0); + + irq_disable(_zephyr_get_irq_nr_from_aton_line_number(aton_line_number)); + // irq_disconnect_dynamic(_zephyr_get_irq_nr_from_aton_line_number(aton_line_number), 0, aton_osal_zephyr_isr, NULL, + // 0); // betzw: seems not be available for STM32N6 + + aton_irq_handler = NULL; + aton_irq_number = -1; +} + +/** + * @brief + * @param aton_line_number + */ +void aton_osal_zephyr_enable_irq(int aton_line_number) +{ + irq_enable(_zephyr_get_irq_nr_from_aton_line_number(aton_line_number)); +} + +/** + * @brief + * @param aton_line_number + */ +void aton_osal_zephyr_disable_irq(int aton_line_number) +{ + irq_disable(_zephyr_get_irq_nr_from_aton_line_number(aton_line_number)); +} + +/** + * @brief + * @param + */ +void aton_osal_zephyr_enter_cs(void) +{ + assert(aton_irq_handler != NULL); + assert(aton_irq_number >= 0); + + irq_disable(aton_irq_number); +} + +/** + * @brief + * @param + */ +void aton_osal_zephyr_exit_cs(void) +{ + assert(aton_irq_handler != NULL); + assert(aton_irq_number >= 0); + + irq_enable(aton_irq_number); +} + +/* Include common RTOS `.c` template */ +#include "ll_aton_osal_rtos_template.c" + +#endif // (LL_ATON_OSAL == LL_ATON_OSAL_ZEPHYR) diff --git a/lib/stai/libstai/ll_aton/ll_aton_profiler.c b/lib/stai/libstai/ll_aton/ll_aton_profiler.c new file mode 100644 index 000000000..039755041 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_profiler.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file ll_aton_profiler.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL library for basic kernels making use of HW blocks driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ll_aton_util.h" // Leave blank line after the include + +#include "ll_aton_profiler.h" +#include "ll_aton_runtime.h" + +#if _LL_LIB_DEBUG +#include +#endif + +int LL_ATON_LIB_ConvInteger(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output) +{ + int in_elements = LL_LIB_TENSOR_ELEMENTS(&inputs[0]); + int kern_elements = LL_LIB_TENSOR_ELEMENTS(&inputs[1]); + // int bias_elements = ninputs > 2 ? LL_LIB_TENSOR_ELEMENTS(&inputs[2]) : 0; + int out_elements = LL_LIB_TENSOR_ELEMENTS(output); + int el_size = inputs[0].type == DataType_INT8 || inputs[0].type == DataType_UINT8 ? 1 : -1; + int el_out_size = output[0].type == DataType_INT32 ? 4 : -1; + int in_byte_size = (in_elements * el_size * 8) >> 3; + int out_byte_size = (out_elements * el_out_size * 8) >> 3; + int kern_byte_size = (kern_elements * el_size * 8) >> 3; + + // if (axis != 1) // for now we only support axis = 1 FIXME !!! + // __LL_LIB_ERROR(_ERR_AXIS, LL_ATON_INVALID_PARAM); + + // if (in_elements != out_elements) + // __LL_LIB_ERROR(_ERR_BUFFER, LL_ATON_INVALID_PARAM); + + if ((el_out_size != 4 || output->type != DataType_INT32)) + __LL_LIB_ERROR(_ERR_DATATYPE, LL_ATON_INVALID_PARAM); + + if (in_byte_size > LL_Buffer_len(inputs + 0)) + __LL_LIB_ERROR(_ERR_BUFFER_IN, LL_ATON_INVALID_PARAM); + + if (out_byte_size > LL_Buffer_len(output + 0)) + __LL_LIB_ERROR(_ERR_BUFFER_OUT, LL_ATON_INVALID_PARAM); + + if (kern_byte_size > LL_Buffer_len(inputs + 1)) + __LL_LIB_ERROR(_ERR_BUFFER_IN, LL_ATON_INVALID_PARAM); + + if (inputs[0].ndims < 4 || inputs[1].ndims < 4) + __LL_LIB_ERROR(_ERR_SHAPE_IN, LL_ATON_INVALID_PARAM); + + if (output->ndims < 4) + __LL_LIB_ERROR(_ERR_SHAPE_OUT, LL_ATON_INVALID_PARAM); + + if (inputs[0].per_channel) + __LL_LIB_ERROR(_ERR_DATATYPE, LL_ATON_INVALID_PARAM); + + // if (inputs[0].type == DataType_INT8) + + const LL_LIB_TensorInfo_TypeDef *feat = &inputs[0]; + const LL_LIB_TensorInfo_TypeDef *kern = &inputs[1]; + const LL_LIB_TensorInfo_TypeDef *out = &output[0]; + int in_ndims = feat->ndims; + int k_ndims = kern->ndims; + + // int in_batch = feat->batch; + + int N = feat->shape[(in_ndims - 4) + TDIM_NKERNELS]; + int C = feat->shape[(in_ndims - 4) + TDIM_NCHANNELS]; + int H = feat->shape[(in_ndims - 4) + TDIM_FHEIGHT]; + int W = feat->shape[(in_ndims - 4) + TDIM_FWIDTH]; + + int K = kern->shape[(k_ndims - 4) + TDIM_NKERNELS]; + int R = kern->shape[(k_ndims - 4) + TDIM_FHEIGHT]; + int S = kern->shape[(k_ndims - 4) + TDIM_FWIDTH]; + + int pad_top = 2; + int pad_bottom = 2; + int pad_left = 2; + int pad_right = 2; + int stride_h = 1; + int stride_w = 1; + int8_t pad_value = -128; + + int8_t *in_data = (int8_t *)LL_Buffer_addr_start(feat); + int32_t *out_data = (int32_t *)LL_Buffer_addr_start(out); + int8_t *w_data = (int8_t *)LL_Buffer_addr_start(kern); + + int out_H = (H + pad_top + pad_bottom - R) / stride_h + 1; + int out_W = (W + pad_left + pad_right - S) / stride_w + 1; + + int32_t maxmax = 0; + for (int n = 0; n < N; ++n) + { + for (int k = 0; k < K; ++k) + { + for (int oh = 0; oh < out_H; ++oh) + { + for (int ow = 0; ow < out_W; ++ow) + { + int32_t sum = 0; + int32_t max = 0; + for (int r = 0; r < R; ++r) + { + for (int s = 0; s < S; ++s) + { + for (int c = 0; c < C; ++c) + { + int ih = oh * stride_h - pad_top + r; + int iw = ow * stride_w - pad_left + s; + int32_t input_value; + if (ih >= 0 && ih < H && iw >= 0 && iw < W) + { + int input_idx = ((n * H + ih) * W + iw) * C + c; // HWC + // int input_idx = ((n * C + c) * H + ih) * W + iw;A // CHW + input_value = in_data[input_idx]; + } + else + { + input_value = pad_value; + } + // LL_ATON_PROFILER_PRINTF("%d %d %d=%d\n", c, r, s, input_value); + int weight_idx = ((k * R + r) * S + s) * C + c; // HWC + // int weight_idx = ((k * C + c) * R + r) * S + s; + sum += input_value * w_data[weight_idx]; + max = sum > max ? sum : max; + // LL_ATON_PROFILER_PRINTF("%d %d %d=%d %d %d\n", c, r, s, input_value, w_data[weight_idx], sum); + } + } + } + int output_idx = ((n * out_H + oh) * out_W + ow) * K + k; // HWC + // int output_idx = ((n * K + k) * out_H + oh) * out_W + ow; + out_data[output_idx] = sum; + LL_ATON_PROFILER_PRINTF("oidx=%d = %d max=%d\n", output_idx, sum, max); + maxmax = max > maxmax ? max : maxmax; + } + } + } + } + LL_ATON_PROFILER_PRINTF("tot max=%d %f", maxmax, log((float)maxmax) / log(2.0)); + + if (inputs[0].type == DataType_UINT8) + { + } + + return LL_ATON_INVALID_PARAM; +} diff --git a/lib/stai/libstai/ll_aton/ll_aton_reloc_callbacks.c b/lib/stai/libstai/ll_aton/ll_aton_reloc_callbacks.c new file mode 100644 index 000000000..77a6692f2 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_reloc_callbacks.c @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file ll_aton_reloc_callbacks.c + * @author GPM/AIS Team + * @brief Relocatable network support + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024,2025 STMicroelectronics. + * All rights reserved.

+ * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include +#include +#include + +#if defined(LL_ATON_RT_RELOC) + +#if defined(BUILD_AI_NETWORK_RELOC) + +#include "ll_aton_caches_interface.h" + +#undef BUILD_AI_NETWORK_RELOC +#include "ll_aton_reloc_network.h" + +#include "ll_aton_lib.h" + +extern struct ai_reloc_rt_ctx _network_rt_ctx; + +void __assert_func(const char *filename, int line, const char *assert_func, const char *expr) +{ + volatile uint32_t _saved_r9; + const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->assert_func) + { + __asm volatile("mov %0, r9\n\t" : "=r"(_saved_r9)); + cbs->assert_func(filename, line, assert_func, expr); + __asm volatile("mov r9, %0\n\t" ::"r"(_saved_r9)); + } + while (1) + ; +} + +void __ll_lib_error(int err_code, int line, const char *func) +{ + volatile uint32_t _saved_r9; + const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->assert_func) + { + __asm volatile("mov %0, r9\n\t" : "=r"(_saved_r9)); + cbs->ll_lib_error(err_code, line, func); + __asm volatile("mov r9, %0\n\t" ::"r"(_saved_r9)); + } +} + +void LL_ATON_Cache_MCU_Clean_Range(uintptr_t virtual_addr, uint32_t size) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->ll_aton_cache_mcu_clean_range) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + cbs->ll_aton_cache_mcu_clean_range(virtual_addr, size); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; +} + +void LL_ATON_Cache_MCU_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->ll_aton_cache_mcu_invalidate_range) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + cbs->ll_aton_cache_mcu_invalidate_range(virtual_addr, size); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; +} + +void LL_ATON_Cache_MCU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->ll_aton_cache_mcu_clean_invalidate_range) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + cbs->ll_aton_cache_mcu_clean_invalidate_range(virtual_addr, size); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; +} + +void LL_ATON_Cache_NPU_Clean_Range(uintptr_t virtual_addr, uint32_t size) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->ll_aton_cache_npu_clean_range) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + cbs->ll_aton_cache_npu_clean_range(virtual_addr, size); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; +} + +void LL_ATON_Cache_NPU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->ll_aton_cache_npu_clean_invalidate_range) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + cbs->ll_aton_cache_npu_clean_invalidate_range(virtual_addr, size); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; +} + +#if 0 +bool ec_copy_program(const uint8_t *file_ptr, ECInstr *program, unsigned int *program_size) +{ + register uint32_t _saved_r9; + register const struct ai_reloc_callback *cbs = _network_rt_ctx.cbs; + if (cbs && cbs->ec_copy_program) { + __asm volatile( "MOV %0, R9\n\t" :"=r"(_saved_r9)); + cbs->ec_copy_program(file_ptr, program, program_size); + __asm volatile( "MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; +} +#endif + +/* + * LL_ATON_LIB_ functions (see ll_lib_aton.h) + */ + +int LL_ATON_LIB_Concat(const LL_Buffer_InfoTypeDef *inputs, unsigned int ninputs, const LL_Buffer_InfoTypeDef *output, + unsigned int axis, int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_concat) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_concat(inputs, ninputs, output, axis, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_ImageToRow(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + unsigned stride_h, unsigned stride_w, int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_imagetorow) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_imagetorow(inputs, ninputs, output, blocksize_h, blocksize_w, stride_h, stride_w, dma_in, + dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_SpaceToDepth(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_spacetodepth) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_spacetodepth(inputs, ninputs, output, blocksize_h, blocksize_w, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_RowToImage(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + unsigned stride_h, unsigned stride_w, int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_rowtoimage) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_rowtoimage(inputs, ninputs, output, blocksize_h, blocksize_w, stride_h, stride_w, dma_in, + dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_DepthToSpace(const LL_LIB_TensorInfo_TypeDef *inputs, unsigned int ninputs, + const LL_LIB_TensorInfo_TypeDef *output, unsigned blocksize_h, unsigned blocksize_w, + int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_depthtospace) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_depthtospace(inputs, ninputs, output, blocksize_h, blocksize_w, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Transpose(const LL_LIB_TensorShape_TypeDef *input, const uint32_t *input_axes_offsets, + const LL_LIB_TensorShape_TypeDef *output, const uint32_t *output_axes_offsets, + const uint8_t *target_pos, const uint8_t *perm_to_use, int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_transpose) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_transpose(input, input_axes_offsets, output, output_axes_offsets, target_pos, + perm_to_use, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_Cast(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, int dma_in, + int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_cast) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_cast(input, output, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_Softmax(const LL_LIB_TensorInfo_TypeDef *input, const LL_LIB_TensorInfo_TypeDef *output, + unsigned int axis, int legacy) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_softmax) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_softmax(input, output, axis, legacy); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Outputs_Flat_Copy(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, int dma_in, + int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_outputs_flat_copy) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_outputs_flat_copy(input, outputs, nr_of_outputs, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Outputs_Slice_SplitLike(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *output, int32_t tot_out_size, + int32_t width_in_bytes, int32_t fheight, int32_t line_offset, int8_t n_bits, + int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_outputs_slice_splitlike) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_outputs_slice_splitlike(input, output, tot_out_size, width_in_bytes, fheight, + line_offset, n_bits, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, + unsigned int leading_dims, int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_outputs_channel_split_aton) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_outputs_channel_split_aton(input, outputs, nr_of_outputs, leading_dims, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched(const LL_LIB_TensorShape_TypeDef *input, + const LL_LIB_TensorShape_TypeDef *outputs, unsigned int nr_of_outputs, + int dma_in, int dma_out) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_outputs_channel_split_batched) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_outputs_channel_split_batched(input, outputs, nr_of_outputs, dma_in, dma_out); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Pad_Memset(void *output, int32_t constant_value, size_t c, __ll_pad_sw_params_t *common_params) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_pad_memset) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_pad_memset(output, constant_value, constant_value, common_params); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +int LL_ATON_LIB_DMA_Pad_Filling(__ll_pad_sw_params_t *init_common_params) +{ + register uint32_t _saved_r9; + register const struct ll_aton_reloc_callback *cbs = _network_rt_ctx.cbs; + int res = -1; + if (cbs && cbs->ll_aton_lib_dma_pad_filling) + { + __asm volatile("MOV %0, R9\n\t" : "=r"(_saved_r9)); + res = cbs->ll_aton_lib_dma_pad_filling(init_common_params); + __asm volatile("MOV R9, %0\n\t" ::"r"(_saved_r9)); + }; + return res; +} + +#else + +#error "This file should be only used to build a relocatable model (BUILD_AI_NETWORK_RELOC)" + +#endif + +#endif /* LL_ATON_RT_RELOC */ diff --git a/lib/stai/libstai/ll_aton/ll_aton_reloc_network.c b/lib/stai/libstai/ll_aton/ll_aton_reloc_network.c new file mode 100644 index 000000000..0ae52031f --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_reloc_network.c @@ -0,0 +1,1323 @@ +/** + ****************************************************************************** + * @file ll_aton_reloc_network.c + * @author MCD/AIS Team + * @brief Implementation of the ATON LL module for relocatable model support + ****************************************************************************** + * @attention + * + * Copyright (c) 2024, 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include +#include + +#if defined(LL_ATON_RT_RELOC) + +#include "ll_aton_lib.h" +#include "ll_aton_reloc_network.h" +#include "ll_aton_version.h" + +/* ----------------------------------------------------------------------------- + * GlOBAL definitions + * ----------------------------------------------------------------------------- + */ + +#if !defined(AI_RELOC_LOG_ENABLE) +#define AI_RELOC_LOG_ENABLE 1 /* 1: enable debug trace support (printf-based) */ +#endif + +#ifndef NDEBUG +#if defined(AI_RELOC_LOG_ENABLE) && AI_RELOC_LOG_ENABLE == 1 +#define AI_RELOC_LOG(...) printf(__VA_ARGS__) +#else +#define AI_RELOC_LOG(...) \ + do \ + { \ + } while (0) +#endif +#else +#define AI_RELOC_LOG(...) \ + do \ + { \ + } while (0) +#endif + +#if !defined(LL_ATON_PLATFORM) || (LL_ATON_PLATFORM != LL_ATON_PLAT_STM32N6) +#error "Model Relocatable mode is only supported for LL_ATON_PLAT_STM32N6 platform" +#if !defined(STM32N6) +#error "STM32N6 should be defined" +#endif +#endif + +#define AI_RELOC_NPU_EXTERNAL_ADDR (0x60000000UL) + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32N6) +#define RELOC_MCU_CLEAN_INVALIDATE(_addr, _size) \ + LL_ATON_Cache_MCU_Clean_Invalidate_Range((uintptr_t)(_addr), (uint32_t)(_size)) +#else +#define RELOC_MCU_CLEAN_INVALIDATE(_addr, _size) \ + do \ + { \ + } while (0) +#endif + +#if defined(STM32N6) +#define RELOC_NPU_INVALIDATE() LL_ATON_Cache_NPU_Invalidate() // npu_cache_invalidate() +#else +#define RELOC_NPU_INVALIDATE() \ + do \ + { \ + } while (0) +#endif + +/* + * Implementation of the call-backs fcts + */ +static void _assert_func(const char *filename, int line, const char *assert_func, const char *expr) +{ + AI_RELOC_LOG("-> assert_func called from reloc code : %d %s : %s %s\n", line, filename, assert_func, expr); + assert(1 != 1); +} + +static void _ll_lib_error(int err_code, int line, const char *func) +{ + AI_RELOC_LOG("-> ll_lib_error called from reloc code : %d %d : %s\n", line, err_code, func); + assert(1 != 1); +} + +static void _LL_ATON_Cache_MCU_Clean_Range(uintptr_t virtual_addr, uint32_t size) +{ + LL_ATON_Cache_MCU_Clean_Range(virtual_addr, size); +} + +static void _LL_ATON_Cache_MCU_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ + LL_ATON_Cache_MCU_Invalidate_Range(virtual_addr, size); +} + +static void _LL_ATON_Cache_MCU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ + LL_ATON_Cache_MCU_Clean_Invalidate_Range(virtual_addr, size); +} + +static void _LL_ATON_Cache_NPU_Clean_Range(uintptr_t virtual_addr, uint32_t size) +{ + LL_ATON_Cache_NPU_Clean_Range(virtual_addr, size); +} + +static void _LL_ATON_Cache_NPU_Clean_Invalidate_Range(uintptr_t virtual_addr, uint32_t size) +{ + LL_ATON_Cache_NPU_Clean_Invalidate_Range(virtual_addr, size); +} + +/* ----------------------------------------------------------------------------- + * Callbacks structure + * ----------------------------------------------------------------------------- + */ +static struct ll_aton_reloc_callback _network_reloc_callback = { + .assert_func = &_assert_func, + .ll_lib_error = &_ll_lib_error, + + .ll_aton_cache_mcu_clean_range = &_LL_ATON_Cache_MCU_Clean_Range, + .ll_aton_cache_mcu_invalidate_range = &_LL_ATON_Cache_MCU_Invalidate_Range, + .ll_aton_cache_mcu_clean_invalidate_range = &_LL_ATON_Cache_MCU_Clean_Invalidate_Range, + .ll_aton_cache_npu_clean_range = &_LL_ATON_Cache_NPU_Clean_Range, + .ll_aton_cache_npu_clean_invalidate_range = &_LL_ATON_Cache_NPU_Clean_Invalidate_Range, + + .ll_aton_lib_concat = &LL_ATON_LIB_Concat, + .ll_aton_lib_cast = &LL_ATON_LIB_Cast, + .ll_aton_lib_softmax = &LL_ATON_LIB_Softmax, + .ll_aton_lib_dma_imagetorow = &LL_ATON_LIB_DMA_ImageToRow, + .ll_aton_lib_dma_spacetodepth = &LL_ATON_LIB_DMA_SpaceToDepth, + .ll_aton_lib_dma_rowtoimage = &LL_ATON_LIB_DMA_RowToImage, + .ll_aton_lib_dma_depthtospace = &LL_ATON_LIB_DMA_DepthToSpace, + .ll_aton_lib_dma_outputs_flat_copy = &LL_ATON_LIB_DMA_Outputs_Flat_Copy, + .ll_aton_lib_dma_outputs_slice_splitlike = &LL_ATON_LIB_DMA_Outputs_Slice_SplitLike, + .ll_aton_lib_dma_outputs_channel_split_aton = &LL_ATON_LIB_DMA_Outputs_Channel_Split_Aton, + .ll_aton_lib_dma_outputs_channel_split_batched = &LL_ATON_LIB_DMA_Outputs_Channel_Split_Batched, + .ll_aton_lib_dma_pad_memset = &LL_ATON_LIB_DMA_Pad_Memset, + .ll_aton_lib_dma_pad_filling = &LL_ATON_LIB_DMA_Pad_Filling, + .ll_aton_lib_dma_transpose = &LL_ATON_LIB_DMA_Transpose, +}; + +/* ----------------------------------------------------------------------------- + * AI RELOC definitions to manage the relocatable binary image + * ----------------------------------------------------------------------------- + */ + +#define AI_RELOC_FLASH_BASE (0x20000000UL) +#define AI_RELOC_RAM_BASE (0x40000000UL) +#define AI_RELOC_PARAM_0_BASE (0x80000000UL) +#define AI_RELOC_PARAM_1_BASE (0x90000000UL) + +#define AI_RELOC_MASK_ID (0xF0000000UL) +#define AI_RELOC_MASK_OFFSET (0x0FFFFFFFUL) + +static inline uint32_t _ai_reloc_get_offset(const uint32_t laddr) +{ + return (uint32_t)((laddr)&AI_RELOC_MASK_OFFSET); +} + +static inline uint32_t _ai_reloc_get_addr(uint32_t base, uint32_t offset) +{ + return base + _ai_reloc_get_offset(offset); +} + +static inline uint32_t _ai_reloc_get_val(uint32_t base, uint32_t offset) +{ + return base + _ai_reloc_get_offset(offset); +} + +#define AI_RELOC_GET_OFFSET(_laddr) (uintptr_t)(_ai_reloc_get_offset(_laddr)) +#define AI_RELOC_GET_ADDR(_base, _off) (uintptr_t)(_ai_reloc_get_addr((uint32_t)_base, _off)) +#define AI_RELOC_GET_VAL(_base, _off) (uintptr_t)(_ai_reloc_get_val((uint32_t)_base, _off)) + +#define AI_RELOC_IN_RAM(_val) (((_val)&0xF0000000) == AI_RELOC_RAM_BASE) + +#define AI_RELOC_IN_FLASH(_val) (((_val)&0xF0000000) == AI_RELOC_FLASH_BASE) + +#define AI_RELOC_IN_PARAM_0(_val) (((_val)&0xF0000000) == AI_RELOC_PARAM_0_BASE) + +#define AI_RELOC_IN_PARAM_1(_val) (((_val)&0xF0000000) == AI_RELOC_PARAM_1_BASE) + +#define AI_RELOC_ROUND_UP(_v) (((_v) + 7) & ~7) /* 8-Bytes aligned */ + +#define AI_RELOC_IS_ALIGNED(_v) (((_v)&0x3) == 0) /* 8-Bytes aligned */ + +/* ! should be aligned with definition in linker script (see reloc_network.lkr) */ +struct bin_hdr +{ + uint32_t magic; /* magic number of the RELOC binary object */ + uint32_t flags; /* configuration (see (see ll_aton_reloc_network.h) */ +}; + +/* ! should be aligned with definition in linker script (see reloc_network.lkr) */ +struct sec_info +{ + uint32_t data_start; /* start of the data section */ + uint32_t data_end; /* end of the data section */ + uint32_t data_data; /* .. */ + uint32_t bss_start; + uint32_t bss_end; + uint32_t got_start; + uint32_t got_end; + uint32_t rel_start; + uint32_t rel_end; + uint32_t params_start; + uint32_t params_offset; +}; + +/* ! should be aligned with struct ai_reloc_network_entries (see ll_aton_reloc_network.h) */ +struct net_entries +{ + uint32_t ec_network_init; + uint32_t ec_inference_init; + uint32_t input_setter; + uint32_t input_getter; + uint32_t output_setter; + uint32_t output_getter; + uint32_t get_epoch_items; + uint32_t get_output_buffers; + uint32_t get_input_buffers; + uint32_t get_internal_buffers; + uint32_t ctx; +}; + +/* Header of the binary file */ +struct ai_reloc_bin_hdr +{ + struct bin_hdr hdr; + struct sec_info sect; + struct net_entries vec; +}; + +/* + * Naked function to set the R9 value and to call the entry point + * without a "prolog" and "epilog". + * + * r0 = ROM base address + * r1 = offset of the function + * r2 = RAM base address (used for R9) + * r3 = arg1 -> r0 + * sp[0] = arg2 -> r1 + * sp[0+4] = arg3 -> r2 + * + */ + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* GNU compiler */ + +static uintptr_t __attribute__((naked)) +call_with_r9(const void *base, uint32_t offset, void *data, uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + __asm__ volatile("add r12, r0, r1 \n" + "mov r0, r3 \n" + "ldr r1, [sp] \n" + "push {r9, lr} \n" + "mov r9, r2 \n" + "ldr r2, [sp, #12] \n" + "blx r12 \n" + "pop {r9, pc} \n"); + + return 0; // dummy to fool gcc +} + +#elif defined(__ICCARM__) /* IAR compiler */ + +__task __irq uintptr_t call_with_r9(const void *base, uint32_t offset, void *data, uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3); +__task __irq uintptr_t call_with_r9(const void *base, uint32_t offset, void *data, uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3) +{ + asm volatile("add r12, r0, r1 \n" + "mov r0, r3 \n" + "ldr r1, [sp] \n" + "push {r9, lr} \n" + "mov r9, r2 \n" + "ldr r2, [sp, #12] \n" + "blx r12 \n" + "pop {r9, pc} \n"); + + return 0; // dummy to fool gcc +} + +#elif defined(__CC_ARM) /* Arm compiler 4/5 */ + +// clang-format off +__asm uintptr_t call_with_r9(const void *base, + uint32_t offset, void *data, + uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + add r12, r0, r1 + mov r0, r3 + ldr r1, [sp] + push {r9, lr} + mov r9, r2 + ldr r2, [sp, #12] + blx r12 + pop {r9, pc} +} +// clang-format on + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* Arm Compiler 6 */ + +static uintptr_t __attribute__((naked)) +call_with_r9(const void *base, uint32_t offset, void *data, uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + __asm("add r12, r0, r1 \n" + "mov r0, r3 \n" + "ldr r1, [sp] \n" + "push {r9, lr} \n" + "mov r9, r2 \n" + "ldr r2, [sp, #12] \n" + "blx r12 \n" + "pop {r9, pc} \n"); +} + +#else + +#error Unknown compiler. + +#endif + +/** + * Return the size of the ro region (hdr, text & rodata sections) - 8-Bytes aligned + */ +static uint32_t _npu_reloc_code_size(const uintptr_t file_ptr) +{ + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)file_ptr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0)) + return 0; + + uint32_t ro_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(bin->sect.data_data)); + + return ro_sz; +} + +/** + * Return the minimum requested size (in bytes) of the exec ram region - 8-Bytes aligned + * according the expected mode - COPY or XIP + */ +static uint32_t _npu_reloc_requested_ram_size(const uintptr_t file_ptr, uint32_t mode) +{ + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)file_ptr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (((uintptr_t)bin & 0x3) != 0)) + return 0; + + const uint32_t rw_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(bin->sect.bss_end)); + const uint32_t ro_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(bin->sect.data_data)); + + if ((mode & AI_RELOC_RT_LOAD_MODE_XIP) == AI_RELOC_RT_LOAD_MODE_XIP) + return rw_sz; + else + return rw_sz + ro_sz; +} + +#define _CPUID *(volatile uint32_t *)(0xE000ED00) +#define _CPACR *(volatile uint32_t *)(0xE000ED88) + +#define _CPUID_PART_NUMBER (0xFFF << 4) /* Part Number */ +#define _CPACR_CPx (0xF << 20) /* CP1 & CP0 bits */ + +#define _GET_PART_NUMBER() (int)((_CPUID & _CPUID_PART_NUMBER) >> 4) +#define _GET_FPU_CPX() (int)((_CPACR & _CPACR_CPx) >> 20) + +static int _ai_reloc_rt_checking(const struct ai_reloc_bin_hdr *bin) +{ + const uint32_t flags = bin->hdr.flags; + const uint32_t cpuid = _GET_PART_NUMBER(); + + /* Binary header/context */ + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (!AI_RELOC_IS_ALIGNED((uintptr_t)bin))) + { + AI_RELOC_LOG("AI RELOC ERROR: Invalid binary header\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + if ((AI_RELOC_RT_GET_MAJOR(flags) != AI_RELOC_RT_VERSION_MAJOR) && + (AI_RELOC_RT_GET_MINOR(flags) != AI_RELOC_RT_VERSION_MINOR)) + { + AI_RELOC_LOG("AI RELOC ERROR: Binary header - invalid version\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + if (cpuid != AI_RELOC_RT_GET_CPUID(flags)) + { + AI_RELOC_LOG("AI RELOC ERROR: CPUID is invalid 0x%03X (expected 0x%03X)\r\n", (int)cpuid, + (int)AI_RELOC_RT_GET_CPUID(flags)); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + if (AI_RELOC_RT_FPU_USED(flags)) + { + if (!_GET_FPU_CPX()) + { + AI_RELOC_LOG("AI RELOC ERROR: FPU is not enabled\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + } + + /* Extra flags */ +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (!AI_RELOC_RT_SECURE(flags)) + { + return AI_RELOC_RT_ERR_INVALID_BIN; + } +#else + if (AI_RELOC_RT_SECURE(flags)) + { + AI_RELOC_LOG("AI RELOC ERROR: Not compiled with secure options\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } +#endif + +#if defined(LL_ATON_EB_DBG_INFO) + if (!AI_RELOC_RT_DBG_INFO(flags)) + { + AI_RELOC_LOG("AI RELOC ERROR: Not compiled with LL_ATON_EB_DBG_INFO\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } +#else + if (AI_RELOC_RT_DBG_INFO(flags)) + { + AI_RELOC_LOG("AI RELOC ERROR: Compiled with LL_ATON_EB_DBG_INFO\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } +#endif + +#if defined(LL_ATON_RT_MODE) && (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + if (!AI_RELOC_RT_ASYNC_MODE(flags)) + { + AI_RELOC_LOG("AI RELOC ERROR: Not compiled with LL_ATON_RT_ASYNC\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } +#else + if (AI_RELOC_RT_ASYNC_MODE(flags)) + { + AI_RELOC_LOG("AI RELOC ERROR: Compiled with LL_ATON_RT_ASYNC\r\n"); + return AI_RELOC_RT_ERR_INVALID_BIN; + } +#endif + + /* Runtime version */ + struct ai_reloc_rt_ctx *rt_ctx = + (struct ai_reloc_rt_ctx *)AI_RELOC_GET_ADDR(bin + AI_RELOC_GET_OFFSET(bin->sect.data_data), bin->vec.ctx); + + uint32_t rt_vers_ = LL_ATON_VERSION_MAJOR << 24 | LL_ATON_VERSION_MINOR << 16 | LL_ATON_VERSION_MICRO << 8; + + if (rt_vers_ != (rt_ctx->rt_version & 0xFFFFFF00UL)) + { + AI_RELOC_LOG("AI RELOC ERROR: RT version is invalid, firmware version = 0x%03X (expected 0x%03X)\r\n", + (int)rt_vers_, (int)rt_ctx->rt_version); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + return AI_RELOC_RT_ERR_NONE; +} + +/* + * Low level functions to install/create a relocatable binary model + */ + +struct id_mpool_mapping +{ + uintptr_t addr_0; + uint32_t sz_0; + uintptr_t addr_1; + uint32_t sz_1; +}; + +static int _ai_reloc_prepare_mpools(const uintptr_t file_ptr, struct id_mpool_mapping *id_map, uint32_t mode) +{ + const struct ai_reloc_bin_hdr *header = (struct ai_reloc_bin_hdr *)file_ptr; + uint32_t params_start = AI_RELOC_GET_OFFSET(header->sect.params_start); + params_start += AI_RELOC_GET_OFFSET(header->sect.data_data); + uintptr_t addr_0 = 0; + bool invalidate_npu_cache = false; + + ll_aton_reloc_mem_pool_desc *cur_mem_c_desc; + + /* Set/check base param addr - user addr is used in priority */ + if ((id_map->addr_0 == 0) && (header->sect.params_offset == 0)) + return AI_RELOC_RT_ERR_PARAM_ADDR; + + if (id_map->addr_0 == 0) + id_map->addr_0 = file_ptr + AI_RELOC_GET_OFFSET(header->sect.params_offset); + + if (!AI_RELOC_IS_ALIGNED(id_map->addr_0)) + return AI_RELOC_RT_ERR_PARAM_ADDR; + + int cur_index = 0; + cur_mem_c_desc = (ll_aton_reloc_mem_pool_desc *)AI_RELOC_GET_ADDR(header, params_start); + + while ((cur_index < 10) && (cur_mem_c_desc->flags) && (cur_mem_c_desc->name)) + { + const uint32_t flags = cur_mem_c_desc->flags; + const uintptr_t dst = cur_mem_c_desc->dst; + const uint32_t sz = AI_RELOC_ROUND_UP(cur_mem_c_desc->size); + const uint32_t foff = cur_mem_c_desc->foff; + const uintptr_t src = id_map->addr_0 + foff; + + if (AI_RELOC_MPOOL_IS_CACHEABLE(flags)) + { + invalidate_npu_cache = true; + } + + if (AI_RELOC_MPOOL_IS_RELOC(flags)) /* Relocated mempool */ + { + const uint32_t id = AI_RELOC_MPOOL_GET_ID(flags); + if (id == 0) /* Parameters/weights section */ + { + if ((AI_RELOC_MPOOL_IS_CACHEABLE(flags) && id_map->addr_0 <= AI_RELOC_NPU_EXTERNAL_ADDR)) + { + return AI_RELOC_RT_ERR_PARAM_ADDR; + } + if (AI_RELOC_MPOOL_IS_MIXED(flags) || AI_RELOC_MPOOL_IS_WRITE(flags)) + { + return AI_RELOC_RT_ERR_PARAM_DESC; + } + if ((AI_RELOC_MPOOL_IS_PARAM(flags)) && (!AI_RELOC_MPOOL_IS_ACTIV(flags))) + { + addr_0 = src; + } + } + else if (id == 1) /* external RAM section */ + { + if ((AI_RELOC_MPOOL_IS_CACHEABLE(flags) && id_map->addr_1 <= AI_RELOC_NPU_EXTERNAL_ADDR)) + { + return AI_RELOC_RT_ERR_PARAM_ADDR; + } + if (((id_map->addr_1 == 0) || (id_map->sz_1 < sz))) + { + return AI_RELOC_RT_ERR_PARAM_ADDR; + } + if (AI_RELOC_MPOOL_IS_MIXED(flags)) + { + memcpy((void *)id_map->addr_1, (void const *)(src), sz); + RELOC_MCU_CLEAN_INVALIDATE(id_map->addr_1, sz); + } + else if ((AI_RELOC_MPOOL_IS_ACTIV(flags)) && (mode & AI_RELOC_RT_LOAD_MODE_CLEAR)) + { + memset((void *)id_map->addr_1, 0, sz); + RELOC_MCU_CLEAN_INVALIDATE(id_map->addr_1, sz); + } + } + else + { + return AI_RELOC_RT_ERR_PARAM_DESC; + } + } + else /* !AI_RELOC_MPOOL_IS_RELOC */ + { + if (AI_RELOC_MPOOL_IS_COPY(flags)) + { + memcpy((void *)dst, (void const *)(src), sz); + RELOC_MCU_CLEAN_INVALIDATE(dst, sz); + } + if (AI_RELOC_MPOOL_IS_RESET(flags) && (mode & AI_RELOC_RT_LOAD_MODE_CLEAR)) + { + memset((void *)dst, 0, sz); + RELOC_MCU_CLEAN_INVALIDATE(dst, sz); + } + } + + cur_mem_c_desc++; + cur_index++; + } + + if (invalidate_npu_cache) + RELOC_NPU_INVALIDATE(); + + if (addr_0) /* Update the param_0 base address */ + id_map->addr_0 = addr_0; + + if (cur_index == 10) + return AI_RELOC_RT_ERR_INVALID_BIN; + + return AI_RELOC_RT_ERR_NONE; +} + +static int _ai_reloc_got_update(const struct ai_reloc_bin_hdr *bin, uintptr_t ram_addr, uintptr_t param_0_addr, + uintptr_t param_1_addr) +{ + uint32_t *got_start = (uint32_t *)AI_RELOC_GET_ADDR(ram_addr, bin->sect.got_start); + uint32_t *got_end = (uint32_t *)AI_RELOC_GET_ADDR(ram_addr, bin->sect.got_end); + + for (uint32_t *p = got_start; p < got_end; p++) + { + uint32_t val = *p; + if AI_RELOC_IN_RAM (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(ram_addr, val); + } + else if AI_RELOC_IN_FLASH (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(bin, val); + } + else if AI_RELOC_IN_PARAM_0 (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(param_0_addr, val); + } + else if AI_RELOC_IN_PARAM_1 (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(param_1_addr, val); + } + else if (val != 0) + { + AI_RELOC_LOG("AI RELOC ERROR: GOT update - unsupported value: %08x\r\n", (int)val); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + *p = val; + } + return AI_RELOC_RT_ERR_NONE; +} + +/* + * Low level function to update the DATA section in RAM. + */ +int _ai_reloc_ram_update(const struct ai_reloc_bin_hdr *bin, uintptr_t ram_addr, uintptr_t param_0_addr, + uintptr_t param_1_addr, const uintptr_t obj) +{ + uint32_t *rel_start = (uint32_t *)AI_RELOC_GET_ADDR(obj, bin->sect.rel_start); + uint32_t *rel_end = (uint32_t *)AI_RELOC_GET_ADDR(obj, bin->sect.rel_end); + + for (uint32_t *p = rel_start; p < rel_end; p++) + { + uint32_t add = *p; + uint32_t val = *(uint32_t *)AI_RELOC_GET_VAL(ram_addr, add); + if AI_RELOC_IN_RAM (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(ram_addr, val); + } + else if AI_RELOC_IN_FLASH (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(bin, val); + } + else if AI_RELOC_IN_PARAM_0 (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(param_0_addr, val); + } + else if AI_RELOC_IN_PARAM_1 (val) + { + val = (uint32_t)AI_RELOC_GET_VAL(param_1_addr, val); + } + else if (val != 0) + { + AI_RELOC_LOG("AI RELOC ERROR: REL update - unsupported value: %08x\r\n", (int)val); + return AI_RELOC_RT_ERR_INVALID_BIN; + } + uint32_t *dest = (uint32_t *)AI_RELOC_GET_ADDR(ram_addr, add); + *dest = val; + } + return AI_RELOC_RT_ERR_NONE; +} + +/* + * Low level function to install the relocatable code. + * + * - 'obj' address of the memory-mapped binary object. + * - ram_addr/ram_size indicates the location (and the size) + * of the buffer destination to install and to update the data/got + * and bss sections for XIP mode or including the hdr/text and + * rodata sections for COPY mode. rel section is only used + * at init time. + * - 'mode' indicates the load mode: XIP or COPY. + * - if successful, 0 is returned and the 'hdl' parameter is + * updated with the address of an internal opaque structure. This + * handle should be used for the other function ai_reloc_XX. + * + * Loading mode: + * + * XIP mode - only the RW and got sections are copied in RAM + * data/got section is updated according the ram/rom@ + * and the info from the rel section. + * code (text/rodata section) is executed-in-place + * COPY mode - code is also copied in RAM + * + * + * obj@ ram_addr@ -> should be aligned 8-bytes + * ----------- rom_addr@ ----------- + * [ hdr ] [ data ] + * [ text ] [ got ] + * [ rodata ] -- XIP mode -> [ bss ] + * ----------- ----------- + * [ data ] + * [ got ] + * [ rel ] + * ----------- + * ram_addr@ -> rom_addr@ + * ----------- + * [ hdr ] + * -- COPY mode --> [ text ] + * [ rodata ] + * pad.. if requested to align (8-bytes) the new ram addr + * ----------- new ram_addr@ + * [ data ] + * [ got ] + * [ bss ] + * ----------- + * + */ +static int _ai_reloc_install(const uintptr_t file_ptr, uintptr_t ram_addr, size_t ram_size, uint32_t ext_ram_addr, + size_t ext_ram_size, uintptr_t param_addr, uint32_t mode, NN_Instance_TypeDef *nn_instance) +{ + int res; + uint32_t state = AI_RELOC_RT_STATE_NOT_INITIALIZED; + struct ai_reloc_bin_hdr *rom_addr = (struct ai_reloc_bin_hdr *)file_ptr; + const uint32_t req_ram_size = _npu_reloc_requested_ram_size(file_ptr, mode); + struct id_mpool_mapping id_map = {param_addr, 0, ext_ram_addr, ext_ram_size}; + + /* Parameter check */ + if (!req_ram_size) + return AI_RELOC_RT_ERR_INVALID_BIN; + + if (((!(mode & AI_RELOC_RT_LOAD_MODE_XIP)) && (!(mode & AI_RELOC_RT_LOAD_MODE_COPY))) || (!nn_instance)) + return AI_RELOC_RT_ERR_ARG; + + if (!ram_addr || !ram_size || (req_ram_size > ram_size)) + return AI_RELOC_RT_ERR_MEMORY; + + if (ext_ram_addr && !AI_RELOC_IS_ALIGNED(ext_ram_addr)) + return AI_RELOC_RT_ERR_PARAM_ADDR; + + if (ram_addr && ram_size && !AI_RELOC_IS_ALIGNED(ram_addr)) + return AI_RELOC_RT_ERR_MEMORY; + + res = _ai_reloc_prepare_mpools(file_ptr, &id_map, mode); + if (res) + return res; + + /* Copy hrd, txt and rodata sections in RAM */ + if (mode & AI_RELOC_RT_LOAD_MODE_COPY) + { + const uint32_t ro_sz = AI_RELOC_ROUND_UP(AI_RELOC_GET_OFFSET(rom_addr->sect.data_data)); + memcpy((void *)ram_addr, (void const *)file_ptr, ro_sz); + + RELOC_MCU_CLEAN_INVALIDATE(ram_addr, ro_sz); + + /* Update the rom_addr/ram_addr pointers */ + rom_addr = (struct ai_reloc_bin_hdr *)(ram_addr); + ram_addr = (uintptr_t)(ram_addr + ro_sz); + } + else + { + state |= AI_RELOC_RT_STATE_XIP_MODE; + } + + const uintptr_t bss_start = AI_RELOC_GET_ADDR(ram_addr, rom_addr->sect.bss_start); + const uint32_t bss_size = rom_addr->sect.bss_end - rom_addr->sect.bss_start; + const uintptr_t src_data = AI_RELOC_GET_ADDR(file_ptr, rom_addr->sect.data_data); + const uint32_t rw_sz = AI_RELOC_GET_OFFSET(rom_addr->sect.bss_end); + + /* Copy the data section, including the got section */ + memcpy((void *)ram_addr, (const void *)src_data, rw_sz - bss_size); + + /* Clear the bss section */ + memset((void *)bss_start, 0, bss_size); + + /* Update the relocation table and data */ + /* R_ARM_GOT_BREL type */ + if (_ai_reloc_got_update(rom_addr, ram_addr, id_map.addr_0, id_map.addr_1)) + return AI_RELOC_RT_ERR_INVALID_BIN; + + /* R_ARM_ABS32 type */ + if (_ai_reloc_ram_update(rom_addr, ram_addr, id_map.addr_0, id_map.addr_1, file_ptr)) + return AI_RELOC_RT_ERR_INVALID_BIN; + + RELOC_MCU_CLEAN_INVALIDATE(ram_addr, rw_sz); + + /* Update the RT context */ + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)AI_RELOC_GET_ADDR(ram_addr, rom_addr->vec.ctx); + + rt_ctx->rom_addr = (uint32_t)rom_addr; + rt_ctx->ram_addr = (uint32_t)ram_addr; + rt_ctx->file_addr = (uint32_t)file_ptr; + rt_ctx->state = (state | AI_RELOC_RT_STATE_INITIALIZED); + rt_ctx->ll_instance = nn_instance; + + /* fill the handler */ + nn_instance->network = rt_ctx->itf_network; + memset(&nn_instance->exec_state, 0, sizeof(NN_Execution_State_TypeDef)); + nn_instance->exec_state.inst_reloc = (uint32_t)rt_ctx; + + return AI_RELOC_RT_ERR_NONE; +} + +static int _ai_rel_check_handler(uintptr_t hdl) +{ + if (!hdl) + return AI_RELOC_RT_ERR_INVALID_HDL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || !(rt_ctx->state & AI_RELOC_RT_STATE_INITIALIZED)) + return AI_RELOC_RT_ERR_INVALID_BIN; + + return AI_RELOC_RT_ERR_NONE; +} + +/* ----------------------------------------------------------------------------- + * Public API implementation + * ----------------------------------------------------------------------------- + */ + +ll_aton_reloc_mem_pool_desc *ll_aton_reloc_get_mem_pool_desc(const uintptr_t file_ptr, int index) +{ + const struct ai_reloc_bin_hdr *bin = (struct ai_reloc_bin_hdr *)file_ptr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (!AI_RELOC_IN_RAM(bin->sect.params_start))) + { + return NULL; + } + + ll_aton_reloc_mem_pool_desc *cur_mem_c_desc; + int cur_index = 0; + + uint32_t off_params = AI_RELOC_GET_OFFSET(bin->sect.params_start); + off_params += AI_RELOC_GET_OFFSET(bin->sect.data_data); + cur_mem_c_desc = (ll_aton_reloc_mem_pool_desc *)AI_RELOC_GET_ADDR(bin, off_params); + + while ((cur_index < 10) && (cur_mem_c_desc->flags) && (cur_mem_c_desc->name)) + { + if (cur_index == index) + return cur_mem_c_desc; + cur_mem_c_desc++; + cur_index++; + } + + return NULL; +} + +int ll_aton_reloc_get_info(const uintptr_t file_ptr, ll_aton_reloc_info *rt) +{ + const struct ai_reloc_bin_hdr *bin = (struct ai_reloc_bin_hdr *)file_ptr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (!AI_RELOC_IS_ALIGNED((uintptr_t)bin)) || (!rt)) + { + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + struct ai_reloc_rt_ctx *rt_ctx = + (struct ai_reloc_rt_ctx *)AI_RELOC_GET_ADDR(bin + AI_RELOC_GET_OFFSET(bin->sect.data_data), bin->vec.ctx); + + rt->c_name = (const char *)AI_RELOC_GET_ADDR(bin, AI_RELOC_GET_OFFSET((int)rt_ctx->c_name)); + rt->variant = (uint32_t)bin->hdr.flags; + rt->params_off = (uint32_t)AI_RELOC_GET_OFFSET(bin->sect.params_offset); + rt->params_sz = (uint32_t)rt_ctx->params_sz; + rt->acts_sz = (uint32_t)rt_ctx->acts_sz; + rt->ext_ram_sz = (uint32_t)AI_RELOC_ROUND_UP(rt_ctx->ext_ram_sz); + rt->rt_ram_xip = _npu_reloc_requested_ram_size(file_ptr, AI_RELOC_RT_LOAD_MODE_XIP); + rt->rt_ram_copy = _npu_reloc_requested_ram_size(file_ptr, AI_RELOC_RT_LOAD_MODE_COPY); + rt->code_sz = _npu_reloc_code_size(file_ptr); + rt->rt_version = rt_ctx->rt_version; + rt->rt_version_extra = rt_ctx->rt_version_extra; + rt->rt_version_desc = (const char *)AI_RELOC_GET_ADDR(bin, AI_RELOC_GET_OFFSET((int)rt_ctx->rt_version_desc)); + + return AI_RELOC_RT_ERR_NONE; +} + +#if defined(AI_RELOC_LOG_ENABLE) && (AI_RELOC_LOG_ENABLE == 1) && !defined(NDEBUG) +static char *_magic_to_str(uint32_t val) +{ + static char res[5]; + res[3] = val >> 24; + res[2] = val >> 16; + res[1] = val >> 8; + res[0] = val >> 0; + return res; +} +#endif + +void ll_aton_reloc_log_info(const uintptr_t file_ptr) +{ +#if defined(AI_RELOC_LOG_ENABLE) && AI_RELOC_LOG_ENABLE == 1 + ll_aton_reloc_info rt_info; + + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)file_ptr; + + if (!bin || (bin->hdr.magic != AI_RELOC_MAGIC) || (!AI_RELOC_IS_ALIGNED((uintptr_t)bin))) + { + AI_RELOC_LOG("\r\nai_rel_log_header: ERR invalid file_ptr: %x\r\n", (unsigned int)file_ptr); + return; + } + + ll_aton_reloc_get_info(file_ptr, &rt_info); + + AI_RELOC_LOG("\r\nBinary model image (@0x%08x)\r\n", (int)bin); + AI_RELOC_LOG("----------------------------------------------------------------\n"); + AI_RELOC_LOG(" c-name : \"%s\"\r\n", rt_info.c_name); + AI_RELOC_LOG(" act sz : %d\r\n", (int)rt_info.acts_sz); + AI_RELOC_LOG(" params sz : %d\r\n", (int)rt_info.params_sz); + AI_RELOC_LOG(" params off : %d\r\n", (int)rt_info.params_off); + AI_RELOC_LOG(" ext ram sz : %d\r\n", (int)rt_info.ext_ram_sz); + AI_RELOC_LOG(" exec ram xip : %d for XIP mode\r\n", (int)rt_info.rt_ram_xip); + AI_RELOC_LOG(" exec ram copy : %d for COPY mode\r\n", (int)rt_info.rt_ram_copy); + AI_RELOC_LOG(" rt_desc : \"%s\"\r\n", rt_info.rt_version_desc); + AI_RELOC_LOG(" rt_version : %d.%d.%d-%d\r\n", (int)(rt_info.rt_version >> 24 & 0xFF), + (int)(rt_info.rt_version >> 16 & 0xFF), (int)(rt_info.rt_version >> 8 & 0xFF), + (int)(rt_info.rt_version_extra)); + + AI_RELOC_LOG("\n C-mempool descriptors\n"); + AI_RELOC_LOG(" --------------------------------------------------------------\n"); + + ll_aton_reloc_mem_pool_desc *mem_c_desc; + int index = 0; + + while ((mem_c_desc = ll_aton_reloc_get_mem_pool_desc((uintptr_t)bin, index))) + { + AI_RELOC_LOG(" %d: flags=%x foff=%d dst=%x s=%d %s\n", index, mem_c_desc->flags, mem_c_desc->foff, mem_c_desc->dst, + mem_c_desc->size, (char *)AI_RELOC_GET_ADDR(bin, (uint32_t)mem_c_desc->name)); + index++; + } + +#ifndef NDEBUG + int fpu_is_enabled = _GET_FPU_CPX(); +#endif + + AI_RELOC_LOG("\r\n Binary header\r\n"); + AI_RELOC_LOG(" magic : 0x%08X (%s)\r\n", (int)bin->hdr.magic, _magic_to_str(bin->hdr.magic)); + AI_RELOC_LOG(" flags : v%d.%d compil=%d feabi=%d (0x%08X)\r\n", (int)AI_RELOC_RT_GET_MAJOR(rt_info.variant), + (int)AI_RELOC_RT_GET_MINOR(rt_info.variant), (int)AI_RELOC_RT_GET_COMPILER(rt_info.variant), + (int)AI_RELOC_RT_GET_FPEABI(rt_info.variant), (int)rt_info.variant); + AI_RELOC_LOG(" fpu=%d (is_enabled:%d)\r\n", (int)AI_RELOC_RT_FPU_USED(rt_info.variant), + fpu_is_enabled); + AI_RELOC_LOG(" cpuid=0x%03x (0x%03x)\r\n", AI_RELOC_RT_GET_CPUID(rt_info.variant), + _GET_PART_NUMBER()); + AI_RELOC_LOG(" extra : dbg=%d async=%d secure=%d\r\n", (int)AI_RELOC_RT_DBG_INFO(rt_info.variant), + (int)AI_RELOC_RT_ASYNC_MODE(rt_info.variant), (int)AI_RELOC_RT_SECURE(rt_info.variant)); + AI_RELOC_LOG(" size : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.rel_end)); + AI_RELOC_LOG(" .txt/.rodata : %d\r\n", (int)AI_RELOC_GET_OFFSET(bin->sect.data_data)); + AI_RELOC_LOG(" .data : %d\r\n", + (int)AI_RELOC_GET_OFFSET(bin->sect.data_end) - (int)AI_RELOC_GET_OFFSET(bin->sect.data_start)); + AI_RELOC_LOG(" .got : %d\r\n", + (int)AI_RELOC_GET_OFFSET(bin->sect.got_end) - (int)AI_RELOC_GET_OFFSET(bin->sect.got_start)); + AI_RELOC_LOG(" .rel : %d\r\n", + (int)AI_RELOC_GET_OFFSET(bin->sect.rel_end) - (int)AI_RELOC_GET_OFFSET(bin->sect.rel_start)); + AI_RELOC_LOG(" .bss : %d\r\n", + (int)AI_RELOC_GET_OFFSET(bin->sect.bss_end) - (int)AI_RELOC_GET_OFFSET(bin->sect.bss_start)); + + AI_RELOC_LOG("\r\n"); +#endif /* AI_RELOC_LOG_ENABLE == 1 */ +} + +int ll_aton_reloc_install(const uintptr_t file_ptr, const ll_aton_reloc_config *config, + NN_Instance_TypeDef *nn_instance) +{ + if (!nn_instance || !file_ptr) + { + return AI_RELOC_RT_ERR_INVALID_BIN; + } + + const struct ai_reloc_bin_hdr *rom_addr = (struct ai_reloc_bin_hdr *)file_ptr; + + /* Binary/header & RT environment checking */ + if (_ai_reloc_rt_checking(rom_addr)) + return AI_RELOC_RT_ERR_INVALID_BIN; + + if (!config) + return AI_RELOC_RT_ERR_ARG; + + int res; + res = _ai_reloc_install(file_ptr, config->exec_ram_addr, config->exec_ram_size, config->ext_ram_addr, + config->ext_ram_size, config->ext_param_addr, config->mode, nn_instance); + + if (!res) + res = ll_aton_reloc_set_callbacks(nn_instance, &_network_reloc_callback); + + return res; +} + +int ll_aton_reloc_set_callbacks(const NN_Instance_TypeDef *nn_instance, const struct ll_aton_reloc_callback *cbs) +{ + if (!nn_instance || !cbs || !nn_instance->exec_state.inst_reloc) + { + return AI_RELOC_RT_ERR_INVALID_BIN; + } + if (_ai_rel_check_handler(nn_instance->exec_state.inst_reloc)) + return 0; + + struct ai_reloc_rt_ctx *rt_ctx = (struct ai_reloc_rt_ctx *)nn_instance->exec_state.inst_reloc; + rt_ctx->cbs = (void *)cbs; + + return AI_RELOC_RT_ERR_NONE; +} + +/* + * Indicate if the associated model is a relocatable installed model + */ +int ll_aton_reloc_is_valid(const NN_Instance_TypeDef *nn_inst) +{ + if (!nn_inst) + { + return AI_RELOC_RT_ERR_INVALID_HDL; + } + + int res = _ai_rel_check_handler(nn_inst->exec_state.inst_reloc); + + if (res == AI_RELOC_RT_ERR_NONE) + return 1; + + return res; +} + +/* ----------------------------------------------------------------------------- + * Entry points of the relocatable model + * ----------------------------------------------------------------------------- */ + +bool ai_rel_network_ec_network_init(uintptr_t hdl) +{ + if (_ai_rel_check_handler(hdl)) + return 0; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.ec_network_init), + (void *)rt_ctx->ram_addr, 0, 0, 0); + + return (bool)res; +} + +bool ai_rel_network_ec_inference_init(uintptr_t hdl) +{ + if (_ai_rel_check_handler(hdl)) + return 0; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)hdl; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.ec_inference_init), + (void *)rt_ctx->ram_addr, 0, 0, 0); + + return (bool)res; +} + +LL_ATON_User_IO_Result_t ai_rel_network_set_input(uintptr_t inst, uint32_t num, void *buffer, uint32_t size) +{ + if (_ai_rel_check_handler(inst)) + return LL_ATON_User_IO_WRONG_INDEX; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.input_setter), + (void *)rt_ctx->ram_addr, num, (uintptr_t)buffer, size); + + return (LL_ATON_User_IO_Result_t)res; +} + +void *ai_rel_network_get_input(uintptr_t inst, uint32_t num) +{ + if (_ai_rel_check_handler(inst)) + return NULL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.input_getter), + (void *)rt_ctx->ram_addr, num, 0, 0); + + return (void *)res; +} + +LL_ATON_User_IO_Result_t ai_rel_network_set_output(uintptr_t inst, uint32_t num, void *buffer, uint32_t size) +{ + if (_ai_rel_check_handler(inst)) + return LL_ATON_User_IO_WRONG_INDEX; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.output_setter), + (void *)rt_ctx->ram_addr, num, (uintptr_t)buffer, size); + + return (LL_ATON_User_IO_Result_t)res; +} + +void *ai_rel_network_get_output(uintptr_t inst, uint32_t num) +{ + if (_ai_rel_check_handler(inst)) + return NULL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.output_getter), + (void *)rt_ctx->ram_addr, num, 0, 0); + + return (void *)res; +} + +const EpochBlock_ItemTypeDef *ai_rel_network_get_epoch_items(uintptr_t inst) +{ + if (_ai_rel_check_handler(inst)) + return NULL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + const EpochBlock_ItemTypeDef *blocks; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.get_epoch_items), + (void *)rt_ctx->ram_addr, 0, 0, 0); + + blocks = (const EpochBlock_ItemTypeDef *)res; + + return blocks; +} + +const LL_Buffer_InfoTypeDef *ai_rel_network_get_output_buffers_info(uintptr_t inst) +{ + if (_ai_rel_check_handler(inst)) + return NULL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + const LL_Buffer_InfoTypeDef *buff_infos; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.get_output_buffers), + (void *)rt_ctx->ram_addr, 0, 0, 0); + + buff_infos = (const LL_Buffer_InfoTypeDef *)res; + + return buff_infos; +} + +const LL_Buffer_InfoTypeDef *ai_rel_network_get_input_buffers_info(uintptr_t inst) +{ + if (_ai_rel_check_handler(inst)) + return NULL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + const LL_Buffer_InfoTypeDef *buff_infos; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.get_input_buffers), + (void *)rt_ctx->ram_addr, 0, 0, 0); + + buff_infos = (const LL_Buffer_InfoTypeDef *)res; + + return buff_infos; +} + +const LL_Buffer_InfoTypeDef *ai_rel_network_get_internal_buffers_info(uintptr_t inst) +{ + if (_ai_rel_check_handler(inst)) + return NULL; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)inst; + const struct ai_reloc_bin_hdr *bin = (const struct ai_reloc_bin_hdr *)rt_ctx->rom_addr; + const LL_Buffer_InfoTypeDef *buff_infos; + + uintptr_t res = call_with_r9((void *)rt_ctx->rom_addr, AI_RELOC_GET_OFFSET(bin->vec.get_internal_buffers), + (void *)rt_ctx->ram_addr, 0, 0, 0); + + buff_infos = (const LL_Buffer_InfoTypeDef *)res; + + return buff_infos; +} + +void ai_rel_call_start_end_function(uintptr_t inst, start_end_func_ptr fct, const void *epoch_block) +{ + register uint32_t _saved_r9; + register uint32_t _r9 = ((struct ai_reloc_rt_ctx *)inst)->ram_addr; + __asm volatile("mov %0, r9\n\t" : "=r"(_saved_r9)); + __asm volatile("mov r9, %0\n\t" ::"r"(_r9)); + fct(epoch_block); + __asm volatile("mov r9, %0\n\t" ::"r"(_saved_r9)); +} + +int ll_aton_reloc_get_file_ptr(const NN_Instance_TypeDef *nn_inst, uintptr_t *file_ptr) +{ + if (!nn_inst || !file_ptr || !nn_inst->exec_state.inst_reloc) + { + return AI_RELOC_RT_ERR_INVALID_HDL; + } + + int res = _ai_rel_check_handler(nn_inst->exec_state.inst_reloc); + if (res) + return res; + + const struct ai_reloc_rt_ctx *rt_ctx = (const struct ai_reloc_rt_ctx *)nn_inst->exec_state.inst_reloc; + + *file_ptr = (uintptr_t)rt_ctx->file_addr; + + return AI_RELOC_RT_ERR_NONE; +} + +const EpochBlock_ItemTypeDef *ll_aton_reloc_get_epoch_items(const NN_Instance_TypeDef *nn_inst) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return NULL; + } + + const EpochBlock_ItemTypeDef *epochs = ai_rel_network_get_epoch_items(nn_inst->exec_state.inst_reloc); + return epochs; +} + +const LL_Buffer_InfoTypeDef *ll_aton_reloc_get_input_buffers_info(const NN_Instance_TypeDef *nn_inst, int32_t num) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return NULL; + } + + const LL_Buffer_InfoTypeDef *buffs = ai_rel_network_get_input_buffers_info(nn_inst->exec_state.inst_reloc); + if ((num < 0) || (!buffs)) + return buffs; + + int32_t idx = 0; + while (buffs) + { + if (!buffs->is_param) + { + if (idx == num) + return buffs; + } + else + { + return NULL; + } + buffs++; + idx++; + } + + return NULL; +} + +const LL_Buffer_InfoTypeDef *ll_aton_reloc_get_output_buffers_info(const NN_Instance_TypeDef *nn_inst, int32_t num) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return NULL; + } + + const LL_Buffer_InfoTypeDef *buffs = ai_rel_network_get_output_buffers_info(nn_inst->exec_state.inst_reloc); + if ((num < 0) || (!buffs)) + return buffs; + + int32_t idx = 0; + while (buffs) + { + if (!buffs->is_param) + { + if (idx == num) + return buffs; + } + else + { + return NULL; + } + buffs++; + idx++; + } + + return NULL; +} + +const LL_Buffer_InfoTypeDef *ll_aton_reloc_get_internal_buffers_info(const NN_Instance_TypeDef *nn_inst) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return NULL; + } + + const LL_Buffer_InfoTypeDef *buffs = ai_rel_network_get_internal_buffers_info(nn_inst->exec_state.inst_reloc); + return buffs; +} + +LL_ATON_User_IO_Result_t ll_aton_reloc_set_input(const NN_Instance_TypeDef *nn_inst, uint32_t num, void *buffer, + uint32_t size) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return LL_ATON_User_IO_WRONG_INDEX; + } + + return ai_rel_network_set_input(nn_inst->exec_state.inst_reloc, num, buffer, size); +} + +void *ll_aton_reloc_get_input(const NN_Instance_TypeDef *nn_inst, uint32_t num) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return NULL; + } + + return ai_rel_network_get_input(nn_inst->exec_state.inst_reloc, num); +} + +LL_ATON_User_IO_Result_t ll_aton_reloc_set_output(const NN_Instance_TypeDef *nn_inst, uint32_t num, void *buffer, + uint32_t size) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return LL_ATON_User_IO_WRONG_INDEX; + } + + return ai_rel_network_set_output(nn_inst->exec_state.inst_reloc, num, buffer, size); +} + +void *ll_aton_reloc_get_output(const NN_Instance_TypeDef *nn_inst, uint32_t num) +{ + if (!nn_inst || !nn_inst->exec_state.inst_reloc) + { + return NULL; + } + + return ai_rel_network_get_output(nn_inst->exec_state.inst_reloc, num); +} + +#endif /* defined(LL_ATON_RT_RELOC) */ diff --git a/lib/stai/libstai/ll_aton/ll_aton_rt_main.c b/lib/stai/libstai/ll_aton/ll_aton_rt_main.c new file mode 100644 index 000000000..804180a3d --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_rt_main.c @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file ll_aton_rt_main.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Template `main()` function (named `LL_ATON_RT_Main()`) for + * Cube.AI/ATON integration in a RTOS-less application. + * @note This file is intended to be just a template and is limited to run the + * ATON LL runtime with a single network instance for a single inference! + * Please, generate your own embodiment of this file and customize it + * so to fit the needs of your application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_runtime.h" +#include "ll_aton_util.h" + +/*** Main Template ***/ + +/** + * @brief Template for synchronously executing a single inference of a single network instance (e.g. regression tests) + * @param network_instance pointer to the network instance representing the network and execution instance to execute. + * The instance object MUST have already set a valid link to a network interface. + * The user may declare/instantiate such an object by using either macro + * `LL_ATON_DECLARE_NAMED_NN_INSTANCE_AND_INTERFACE()` to create both the execution instance + * and the network interface, or macros + * `LL_ATON_DECLARE_NAMED_NN_INTERFACE()` & `LL_ATON_DECLARE_NAMED_NN_INSTANCE()` to + * create/instantiate the objects separately. + */ +void LL_ATON_RT_Main(NN_Instance_TypeDef *network_instance) +{ + LL_ATON_RT_RetValues_t ll_aton_rt_ret; + + /*** Start of user initialization code ***/ + + /*** End of user initialization code ***/ + + LL_ATON_ASSERT(network_instance != NULL); + LL_ATON_ASSERT(network_instance->network != NULL); + LL_ATON_RT_RuntimeInit(); // Initialize runtime + LL_ATON_RT_Init_Network(network_instance); // Initialize passed network instance object + + do + { + /* Execute first/next step of Cube.AI/ATON runtime */ + ll_aton_rt_ret = LL_ATON_RT_RunEpochBlock(network_instance); + + /*** Start of user event handling code ***/ + + /*** End of user event handling code ***/ + + /* Wait for next event */ + if (ll_aton_rt_ret == LL_ATON_RT_WFE) + { /*** subject to change to fit also user code requirements ***/ + LL_ATON_OSAL_WFE(); + } + } while (ll_aton_rt_ret != LL_ATON_RT_DONE); /*** subject to change to fit also user code requirements ***/ + + LL_ATON_RT_DeInit_Network(network_instance); // De-initialize the network instance object + LL_ATON_RT_RuntimeDeInit(); // De-initialize runtime + + /*** Start of user de-initialization code ***/ + + /*** End of user de-initialization code ***/ +} diff --git a/lib/stai/libstai/ll_aton/ll_aton_runtime.c b/lib/stai/libstai/ll_aton/ll_aton_runtime.c new file mode 100644 index 000000000..2d0137374 --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_runtime.c @@ -0,0 +1,1016 @@ +/** + ****************************************************************************** + * @file ll_aton_runtime.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL runtime. + * @note ATON LL runtime currently assumes a single network run + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include +#include + +#include "ll_aton_util.h" // Leave blank line after the include + +#include "ll_aton.h" +#include "ll_aton_runtime.h" + +#if defined(LL_ATON_RT_RELOC) +#include "ll_aton_reloc_network.h" +#endif + +/*** ATON RT Variables ***/ + +/* Check if current runtime is prepared for underlying ATON IP instance */ +#if !defined(ATON_INTCTRL_INTS) || !defined(ATON_STRENG_NUM) +#error macros `ATON_INTCTRL_INTS` & `ATON_STRENG_NUM` MUST be defined but at least one is not! +#else // `ATON_INTCTRL_INTS` and `ATON_STRENG_NUM` are defined + +#if (ATON_INTCTRL_INTS(0) > 64) || ((ATON_STRENG_NUM + ATON_STRENG_INT(0)) > 32) +#error current ATON runtime supports only up to 64 ATON interrupts and up to 32 streaming engines (with IRQ numbers lower than 32)! +#endif // (ATON_INTCTRL_INTS(0) > 64) || ((ATON_STRENG_NUM + ATON_STRENG_INT(0)) > 32) + +#if defined(ATON_EPOCHCTRL_NUM) && (ATON_EPOCHCTRL_NUM > 32) +#error current ATON runtime supports only up to 32 epoch controllers! +#endif // (ATON_EPOCHCTRL_NUM > 32) + +#endif // `ATON_INT_NR` and `ATON_STRENG_NUM` are defined + +LL_ATON_WEAK void dump_dma_state(void){}; + +/* Global variable for the current ATON IP owner */ +NN_Instance_TypeDef *volatile __ll_current_aton_ip_owner = NULL; +#ifndef NDEBUG +/* Current wait mask set */ +uint32_t volatile __ll_current_wait_mask = 0; +#endif // NDEBUG + +/* Trace runtime callback */ +static TraceRuntime_FuncPtr_t ll_aton_init_deinit_trace = NULL; + +/* Forward declaration */ +void ATON_STD_IRQHandler(void); + +#define LL_ATON_DISABLE_ALL_IRQs() \ + do \ + { \ + LL_ATON_OSAL_DISABLE_IRQ(0); \ + LL_ATON_OSAL_DISABLE_IRQ(1); \ + LL_ATON_OSAL_DISABLE_IRQ(2); \ + LL_ATON_OSAL_DISABLE_IRQ(3); \ + } while (0) + +/*** Helper Functions ***/ + +#ifndef NDEBUG +static uint32_t __LL_ATON_RT_CntEpochBlocks(const LL_ATON_RT_EpochBlockItem_t *list) +{ + int i = 0; + + if (list != NULL) + { + for (i = 1; !EpochBlock_IsLastEpochBlock(list); i++) + { // Note: also terminating empty epoch block is counted + list++; + } + } + + return i; +} +#endif + +static inline void __LL_ATON_RT_ExecStartEpochBlock(const LL_ATON_RT_EpochBlockItem_t *eb, + NN_Instance_TypeDef *nn_instance) +{ + LL_ATON_ASSERT(nn_instance->exec_state.next_epoch_block == NULL); + + if (nn_instance->exec_state.epoch_callback_function != NULL) + nn_instance->exec_state.epoch_callback_function(LL_ATON_RT_Callbacktype_PRE_START, nn_instance, eb); + + /* Is it the first epoch block in an AtoNN epoch? */ + if (EpochBlock_IsEpochStart(eb)) + { + __LL_ATON_RT_Start_AtoNN_Epoch(nn_instance); + } + + /* Grab ATON IP lock in case not a pure SW or internal epoch */ + if (EpochBlock_IsEpochPureHW(eb) || + EpochBlock_IsEpochHybrid(eb)) // epoch blobs are flagged as pure HW, so checking for epoch blob is not necessary + { + __ll_set_aton_owner(nn_instance); + } + + if (!EpochBlock_IsEpochBlob(eb)) + { // standard epoch block handling based on streaming engines + /* set wait mask(s) in interrupt controller */ + if (EpochBlock_IsEpochPureHW(eb) || EpochBlock_IsEpochInternal(eb)) + { + LL_ATON_ASSERT(__ll_current_aton_ip_owner == nn_instance); + __LL_ATON_RT_SetWaitMask(eb->wait_mask); + } + } + else + { // epoch blob handling based on epoch controller +#if defined(ATON_EPOCHCTRL_NUM) && \ + (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) // Polling mode is not allowed/supported when using the epoch controller + /* reset wait mask(s) in interrupt controller, but ignore stream engine completion event interrupts */ + __LL_ATON_RT_SetWaitMask(ATON_STRENG_INT_MASK(ATON_STRENG_NUM, 0, 0)); +#else // !ATON_EPOCHCTRL_NUM || LL_ATON_RT_POLLING + LL_ATON_PRINTF("Trying to execute an epoch blob, but\n\t" + "- either ATON machine configuration does not contain an epoch controller unit or\n\t" + "- ATON runtime is configured for polling mode execution which does not support the usage of epoch " + "controllers\n"); +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif // ATON_PLAT_HAS_FFLUSH + LL_ATON_ASSERT(false); // may never happen +#endif // !ATON_EPOCHCTRL_NUM || LL_ATON_RT_POLLING + } + + if (eb->start_epoch_block != NULL) + { + /* start epoch block */ +#if defined(LL_ATON_RT_RELOC) + if (nn_instance->exec_state.inst_reloc != 0) + { + ai_rel_call_start_end_function(nn_instance->exec_state.inst_reloc, eb->start_epoch_block, (const void *)eb); + } + else + { + eb->start_epoch_block((const void *)eb); + } +#else + eb->start_epoch_block((const void *)eb); +#endif + } + + if (EpochBlock_IsEpochBlob(eb)) + { +#if defined(ATON_EPOCHCTRL_NUM) + /* configure epoch controller */ + uint32_t ecId = EpochBlock_EpochControllerUnit(eb); + LL_ATON_ASSERT(ecId < ATON_EPOCHCTRL_NUM); // may never happen + + LL_EpochCtrl_InitTypeDef conf; + conf.stepmode = 0; + conf.blobaddr = EpochBlock_EpochBlobAddr(eb); + + LL_EpochCtrl_Init(ecId, &conf); + + /* start/enable epoch controller */ + ATON_ENABLE(EPOCHCTRL, ecId); +#else // !ATON_EPOCHCTRL_NUM + LL_ATON_ASSERT(false); // may never happen +#endif // !ATON_EPOCHCTRL_NUM + } + + if (nn_instance->exec_state.epoch_callback_function != NULL) + nn_instance->exec_state.epoch_callback_function(LL_ATON_RT_Callbacktype_POST_START, nn_instance, eb); +} + +static inline void __LL_ATON_RT_ExecEndEpochBlock(const LL_ATON_RT_EpochBlockItem_t *eb, + NN_Instance_TypeDef *nn_instance) +{ + if (nn_instance->exec_state.epoch_callback_function != NULL) + nn_instance->exec_state.epoch_callback_function(LL_ATON_RT_Callbacktype_PRE_END, nn_instance, eb); + + if (EpochBlock_IsEpochBlob(eb)) + { +#if defined(ATON_EPOCHCTRL_NUM) + /* stop/disable epoch controller */ + uint32_t ecId = EpochBlock_EpochControllerUnit(eb); + LL_ATON_ASSERT(ecId < ATON_EPOCHCTRL_NUM); // may never happen + uint32_t t; + ATON_DISABLE_CLR_CONFCLR(EPOCHCTRL, ecId); + + /* disable epoch controller clock */ + LL_ATON_DisableClock(ATON_EPOCHCTRL_CLKB_CLK(ecId)); +#else // !ATON_EPOCHCTRL_NUM + LL_ATON_ASSERT(false); // may never happen +#endif // !ATON_EPOCHCTRL_NUM + } + + if (eb->end_epoch_block != NULL) + { +#if defined(LL_ATON_RT_RELOC) + if (nn_instance->exec_state.inst_reloc != 0) + { + ai_rel_call_start_end_function(nn_instance->exec_state.inst_reloc, eb->end_epoch_block, eb); + } + else + { + eb->end_epoch_block((const void *)eb); + } +#else + eb->end_epoch_block((const void *)eb); +#endif + } + + /* Reset wait mask */ + if (EpochBlock_IsEpochPureHW(eb) || + EpochBlock_IsEpochInternal(eb)) // epoch blobs are flagged as pure HW, so checking for epoch blob is not necessary + { + LL_ATON_ASSERT(nn_instance == __ll_current_aton_ip_owner); + __LL_ATON_RT_SetWaitMask(0); + } + + /* Release ATON IP unlock in case it's a pure HW epoch */ + if (EpochBlock_IsEpochPureHW(eb) || ((EpochBlock_IsEpochHybrid(eb) || EpochBlock_IsEpochInternal(eb)) && + (nn_instance->exec_state.saved_current_epoch_block == NULL) && + (nn_instance->exec_state.next_epoch_block == + NULL))) /* hybrid has finished after that last part has been executed in SW */ + { + __ll_clear_aton_owner(nn_instance); + } + LL_ATON_ASSERT(EpochBlock_IsEpochInternal(eb) || EpochBlock_IsEpochHybrid(eb) || + (__ll_current_aton_ip_owner != nn_instance)); + + if (nn_instance->exec_state.epoch_callback_function != NULL) + { + nn_instance->exec_state.epoch_callback_function(LL_ATON_RT_Callbacktype_POST_END, nn_instance, eb); + } +} + +static void __LL_ATON_RT_DetermineNextEpochBlock(NN_Instance_TypeDef *nn_instance) +{ + LL_ATON_ASSERT(nn_instance != NULL); +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + LL_ATON_ASSERT(nn_instance->exec_state.triggered_events == + 0x0); // with the removal of parallel SW/HW epochs execution all triggered events must have been + // cleared at this point in time! +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + + /* Determine if there is a new inserted epoch block array */ + if ((nn_instance->exec_state.next_epoch_block != NULL)) + { + LL_ATON_ASSERT(nn_instance->exec_state.saved_current_epoch_block == NULL); + + /* save current context */ + nn_instance->exec_state.saved_current_epoch_block = nn_instance->exec_state.current_epoch_block; + nn_instance->exec_state.saved_first_epoch_block = nn_instance->exec_state.first_epoch_block; +#ifndef NDEBUG + nn_instance->exec_state.saved_nr_of_epoch_blocks = nn_instance->exec_state.nr_of_epoch_blocks; +#endif + + /* set new context */ + nn_instance->exec_state.current_epoch_block = nn_instance->exec_state.next_epoch_block; + nn_instance->exec_state.first_epoch_block = nn_instance->exec_state.next_epoch_block; +#ifndef NDEBUG + nn_instance->exec_state.nr_of_epoch_blocks = __LL_ATON_RT_CntEpochBlocks(nn_instance->exec_state.first_epoch_block); +#endif + + /* reset next epoch block */ + nn_instance->exec_state.next_epoch_block = NULL; + } + else + { + nn_instance->exec_state.current_epoch_block++; + } + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + nn_instance->exec_state.current_epoch_block_started = false; +#endif +} + +static inline uint32_t __LL_ATON_RT_GetWaitMask(const LL_ATON_RT_EpochBlockItem_t *eb) +{ + if (EpochBlock_IsEpochBlob(eb)) + { + // in case of epoch blob `wait_mask` contains unit number of epoch controller to use + return (1 << EpochBlock_EpochControllerUnit(eb)); + } + else + { + return eb->wait_mask; // in case of "normal" epoch block `wait_mask` contains bitmask of (output) stream engines to + // wait for + } +} + +static inline void __LL_ATON_RT_Init_Network(NN_Instance_TypeDef *nn_instance) +{ + /** Exit if `nn_instance` is equal to NULL **/ + if (nn_instance == NULL) + { + return; + } + + /** Exit if `nn_instance->network` is equal to NULL **/ + if (nn_instance->network == NULL) + { + return; + } + + /** Initialize static variables **/ + /* set context */ +#if defined(LL_ATON_RT_RELOC) + const LL_ATON_RT_EpochBlockItem_t *eb_list; + if (nn_instance->exec_state.inst_reloc != 0) + { + eb_list = ai_rel_network_get_epoch_items(nn_instance->exec_state.inst_reloc); + } + else + { + eb_list = nn_instance->network->epoch_block_items(); + } +#else + const LL_ATON_RT_EpochBlockItem_t *eb_list = nn_instance->network->epoch_block_items(); +#endif + nn_instance->exec_state.current_epoch_block = eb_list; + nn_instance->exec_state.first_epoch_block = eb_list; + nn_instance->exec_state.next_epoch_block = NULL; + + /* set saved context */ + nn_instance->exec_state.saved_current_epoch_block = NULL; + nn_instance->exec_state.saved_first_epoch_block = NULL; +#ifndef NDEBUG + nn_instance->exec_state.nr_of_epoch_blocks = __LL_ATON_RT_CntEpochBlocks(nn_instance->exec_state.current_epoch_block); + nn_instance->exec_state.saved_nr_of_epoch_blocks = 0; +#endif + + /* set information about running inference */ + nn_instance->exec_state.inference_started = false; + + /* set asynchronous status variables */ +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + nn_instance->exec_state.triggered_events = 0x0; + nn_instance->exec_state.current_epoch_block_started = false; +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + + /** Call epoch callback with callback type `LL_ATON_RT_Callbacktype_NN_Init` and network instance **/ + if (nn_instance->exec_state.epoch_callback_function != NULL) + { + nn_instance->exec_state.epoch_callback_function(LL_ATON_RT_Callbacktype_NN_Init, nn_instance, NULL); + } +} + +/*** User API Functions ***/ + +/** + * @brief Registers callbacks for ATON runtime related events (e.g. initialization/deinitialization, see + * `LL_ATON_RT_Callbacktype_t`) + * @param rt_callback Function pointer to callback function (set to `NULL` to disable epoch tracing) + * + * @note This function must only be called when no network is currently executing! + */ +void LL_ATON_RT_SetRuntimeCallback(TraceRuntime_FuncPtr_t rt_callback) +{ + ll_aton_init_deinit_trace = rt_callback; +} + +/** + * @brief Register callback for tracing epoch/network related events (see `LL_ATON_RT_Callbacktype_t`) + * @param nn_instance Pointer to network instance for which to set the callback + */ + +/** + * @brief Register callback for tracing epoch/network related events (see `LL_ATON_RT_Callbacktype_t`) + * @param epoch_block_callback Function pointer to callback function (set to `NULL` to disable epoch tracing) + * @param nn_instance Pointer to network instance for which to set the callback (may not be `NULL`) + * + * @note This function must only be called while the passed network instance is not executing + * and should be called before `LL_ATON_RT_Init_Network()`! + */ +void LL_ATON_RT_SetEpochCallback(TraceEpochBlock_FuncPtr_t epoch_block_callback, NN_Instance_TypeDef *nn_instance) +{ + LL_ATON_ASSERT(nn_instance != NULL); + nn_instance->exec_state.epoch_callback_function = epoch_block_callback; +} + +/** + * @brief Initialize a network instance + * @param nn_instance Pointer to network instance to initialize + */ +void LL_ATON_RT_Init_Network(NN_Instance_TypeDef *nn_instance) +{ + /** Exit if `nn_instance` is equal to NULL **/ + if (nn_instance == NULL) + { + return; + } + + /** Exit if `nn_instance->network` is equal to NULL **/ + if (nn_instance->network == NULL) + { + return; + } + + /* Care about epoch controller blobs relocation */ +#if defined(LL_ATON_RT_RELOC) + bool ret = false; + if (nn_instance->exec_state.inst_reloc != 0) + { + ret = ai_rel_network_ec_network_init(nn_instance->exec_state.inst_reloc); + } + else + { + LL_ATON_ASSERT(nn_instance->network->ec_network_init != NULL); + ret = nn_instance->network->ec_network_init(); + } +#else + LL_ATON_ASSERT(nn_instance->network->ec_network_init != NULL); + bool ret = nn_instance->network->ec_network_init(); +#endif + LL_ATON_ASSERT(ret == true); + LL_ATON_LIB_UNUSED(ret); + + /* Call actual network instance initialization */ + __LL_ATON_RT_Init_Network(nn_instance); +} + +/** + * @brief De-initialize a network instance + * @param nn_instance Pointer to network instance to de-initialize + */ +void LL_ATON_RT_DeInit_Network(NN_Instance_TypeDef *nn_instance) +{ + /** Exit if `nn_instance` is equal to NULL **/ + if (nn_instance == NULL) + { + return; + } + + /** Call epoch callback with callback type `LL_ATON_RT_Callbacktype_NN_DeInit` and network instance **/ + if (nn_instance->exec_state.epoch_callback_function != NULL) + { + nn_instance->exec_state.epoch_callback_function(LL_ATON_RT_Callbacktype_NN_DeInit, nn_instance, NULL); + } + + /** Re-set ATON IP owner */ + if (nn_instance == __ll_current_aton_ip_owner) + { // In case this function gets called while an ATON lib internal EpochBlock (used to implement hybrid epochs) is + // under execution we might still be owner of the ATON IP + __ll_clear_aton_owner(nn_instance); + } + + /** De-initialize static variables **/ + /* re-set context */ + const LL_ATON_RT_EpochBlockItem_t *eb_list = NULL; + nn_instance->exec_state.current_epoch_block = eb_list; + nn_instance->exec_state.first_epoch_block = eb_list; + nn_instance->exec_state.next_epoch_block = NULL; + + /* re-set saved context */ + nn_instance->exec_state.saved_current_epoch_block = NULL; + nn_instance->exec_state.saved_first_epoch_block = NULL; +#ifndef NDEBUG + nn_instance->exec_state.nr_of_epoch_blocks = 0; + nn_instance->exec_state.saved_nr_of_epoch_blocks = 0; +#endif + + /* intentional do not re-set information about running inference `nn_instance->exec_state.inference_started` */ + + /* re-set asynchronous status variables */ +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + nn_instance->exec_state.triggered_events = 0x0; + nn_instance->exec_state.current_epoch_block_started = false; +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) +} + +/** + * @brief Reset network instance for getting ready for a new inference + * @param nn_instance Pointer to network instance to initialize + */ +void LL_ATON_RT_Reset_Network(NN_Instance_TypeDef *nn_instance) +{ + LL_ATON_RT_DeInit_Network(nn_instance); + __LL_ATON_RT_Init_Network(nn_instance); +} + +/** + * @brief Initialize the ATON runtime + */ +void LL_ATON_RT_RuntimeInit(void) +{ + /** Initialize ATON IPs **/ + LL_ATON_Init(); + + /** Initialize IRQ Context **/ + { + uint32_t t; + + /* Disable & Clear interrupt controller */ + ATON_DISABLE_CLR_CONFCLR(INTCTRL, 0); + + /* Preset Interrupt Controller masks */ + ATON_INTCTRL_STD_INTORMSK_SET(ATON_STRENG_INT_MASK( + ATON_STRENG_NUM, 0, 0)); // OR-mask: disable all streaming engine events and enable all other events & errors + ATON_INTCTRL_STD_INTANDMSK_SET(0xFFFFFFFF); // AND-mask: disable all events & errors + +#if (ATON_INT_NR > 32) + ATON_INTCTRL_STD_INTORMSK_H_SET(0); // OR-mask: enable all events & errors + ATON_INTCTRL_STD_INTANDMSK_H_SET(0xFFFFFFFF); // AND-mask: disable all events & errors +#endif + + /* Enable Interrupt Controller (again) */ + ATON_ENABLE(INTCTRL, 0); + } + + /** Initialize OSAL layer **/ + LL_ATON_OSAL_INIT(); + + /** Disable all four ATON interrupts **/ + LL_ATON_DISABLE_ALL_IRQs(); + + /** Install IRQ handler **/ + LL_ATON_OSAL_INSTALL_IRQ(ATON_STD_IRQ_LINE, ATON_STD_IRQHandler); + + /** Enable ATON `ATON_STD_IRQ_LINE` interrupt **/ + LL_ATON_OSAL_ENABLE_IRQ(ATON_STD_IRQ_LINE); + + /** After having initialized ATON call callback (which among others might initialize further subsystems) */ + if (ll_aton_init_deinit_trace) + ll_aton_init_deinit_trace(LL_ATON_RT_Callbacktype_RT_Init); +} + +/** + * @brief De-initialize the ATON runtime + * @param nn_instance Pointer to network instance to de-initialize (optional - i.e. may be `NULL`, see + * `LL_ATON_RT_DeInit_Network()`) + */ +void LL_ATON_RT_RuntimeDeInit(void) +{ + /* Call runtime de-init callback */ + if (ll_aton_init_deinit_trace) + ll_aton_init_deinit_trace(LL_ATON_RT_Callbacktype_RT_Deinit); + + /* Disable all four ATON interrupts */ + LL_ATON_DISABLE_ALL_IRQs(); + + /* Remove IRQ handler */ + LL_ATON_OSAL_REMOVE_IRQ(ATON_STD_IRQ_LINE); + + /* De-initialize OSAL layer */ + LL_ATON_OSAL_DEINIT(); + + /* De-initialize ATON IPs */ + LL_ATON_DeInit(); +} + +/** + * @brief Checks status of previously started epoch block and + * starts execution of next epoch block of the NN provided the previous epoch block has terminated + * @param nn_instance Pointer to network instance to run/continue (may not be `NULL`) + * @retval LL_ATON_RT_NO_WFE Next epoch block may be started, NN execution not finished, do not call + * `LL_ATON_OSAL_WFE()` + * @retval LL_ATON_RT_WFE Epoch block is still running, NN execution not finished, you may call + * `LL_ATON_OSAL_WFE()`. + * NOTE, that in this case no other network instance may be run/continued from within the + * same thread! + * It is entirely the user's responsibility to comply with this restriction! + * @retval LL_ATON_RT_DONE NN execution finished + */ +LL_ATON_RT_RetValues_t LL_ATON_RT_RunEpochBlock(NN_Instance_TypeDef *nn_instance) +{ + LL_ATON_ASSERT(nn_instance != NULL); + + /* Test for wrong/missing initialization */ + LL_ATON_ASSERT(nn_instance->exec_state.current_epoch_block != NULL); // should never happen + + /* Check if network is starting a new inference */ + if (nn_instance->exec_state.inference_started == false) + { + /* Perform epoch controller blob relocation updates */ +#if defined(LL_ATON_RT_RELOC) + bool ret = false; + if (nn_instance->exec_state.inst_reloc != 0) + { + ret = ai_rel_network_ec_inference_init(nn_instance->exec_state.inst_reloc); + } + else + { + LL_ATON_ASSERT((nn_instance->network != NULL) && (nn_instance->network->ec_inference_init != NULL)); + ret = nn_instance->network->ec_inference_init(); + } +#else + LL_ATON_ASSERT((nn_instance->network != NULL) && (nn_instance->network->ec_inference_init != NULL)); + bool ret = nn_instance->network->ec_inference_init(); +#endif + + LL_ATON_ASSERT(ret == true); + LL_ATON_LIB_UNUSED(ret); + + /* Set inference started flag to `true` */ + nn_instance->exec_state.inference_started = true; + + /* Placeholder for things which need to be done before starting an inference */ + /* ==> here <== */ + } + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + bool this_run_executed_end_epoch = false; +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + + while (true) + { +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + /* wait for current epoch block to finish */ + uint32_t _wait_mask = __LL_ATON_RT_GetWaitMask(nn_instance->exec_state.current_epoch_block); + if (nn_instance->exec_state.current_epoch_block_started && (_wait_mask != 0)) + { + if ((nn_instance->exec_state.triggered_events & _wait_mask) == _wait_mask) + { + /* Enter critical section */ + LL_ATON_ASSERT(__ll_current_aton_ip_owner == + nn_instance); // when entering a critical section we MUST hold the ATON IP lock + LL_ATON_OSAL_ENTER_CS(); + + /* reset triggered events */ + nn_instance->exec_state.triggered_events &= ~_wait_mask; + + /* Exit critical section */ + LL_ATON_OSAL_EXIT_CS(); + + /* end/clean-up epoch block */ + __LL_ATON_RT_ExecEndEpochBlock(nn_instance->exec_state.current_epoch_block, nn_instance); + this_run_executed_end_epoch = true; + + /* advance epoch block */ + __LL_ATON_RT_DetermineNextEpochBlock(nn_instance); + } + else + { + /* Return to main loop */ + return LL_ATON_RT_WFE; + } + } +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + + /* test for last epoch block */ + if (EpochBlock_IsLastEpochBlock(nn_instance->exec_state.current_epoch_block)) + { + if (nn_instance->exec_state.saved_current_epoch_block != NULL) + { + /* return from inserted epoch block */ + __LL_ATON_RT_RetFromLibEpochBlockArray(true, nn_instance); + + /* advance epoch block */ + nn_instance->exec_state.current_epoch_block++; + + /* Return to main loop (but do NOT call `LL_ATON_OSAL_WFE())`) */ + return LL_ATON_RT_NO_WFE; + } + else + { + /* Reached end of execution */ + return LL_ATON_RT_DONE; + } + } + + /* run/start current epoch block */ +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + if (this_run_executed_end_epoch) + { // alow reset of network (see function `LL_ATON_RT_Reset_Network()`) + /* Return to main loop (but do NOT call `LL_ATON_OSAL_WFE())`) */ + return LL_ATON_RT_NO_WFE; + } + + if (!nn_instance->exec_state.current_epoch_block_started) + { + nn_instance->exec_state.current_epoch_block_started = true; + + __LL_ATON_RT_ExecStartEpochBlock(nn_instance->exec_state.current_epoch_block, nn_instance); + } + + /* End epoch block and advance to next one */ + if (__LL_ATON_RT_GetWaitMask(nn_instance->exec_state.current_epoch_block) == 0x0) + { + /* end/clean-up epoch block */ + __LL_ATON_RT_ExecEndEpochBlock(nn_instance->exec_state.current_epoch_block, nn_instance); + this_run_executed_end_epoch = true; // has no effect (just for cosmetics) + + /* advance epoch block */ + __LL_ATON_RT_DetermineNextEpochBlock(nn_instance); + + /* Return to main loop (but do NOT call `LL_ATON_OSAL_WFE())`) */ + return LL_ATON_RT_NO_WFE; + } + else + { + /* Return to main loop */ + return LL_ATON_RT_WFE; + } + +#else // (LL_ATON_RT_MODE == LL_ATON_RT_POLLING) + + __LL_ATON_RT_ExecStartEpochBlock(nn_instance->exec_state.current_epoch_block, nn_instance); + + /* wait for end of epoch block */ + uint32_t _wait_mask = __LL_ATON_RT_GetWaitMask(nn_instance->exec_state.current_epoch_block); + if (_wait_mask != 0) + { + /* Perform polling wait */ + if (EpochBlock_IsEpochBlob(nn_instance->exec_state.current_epoch_block)) + { +#if defined(ATON_EPOCHCTRL_NUM) + LL_EpochCtrl_Wait(_wait_mask); +#else // !ATON_EPOCHCTRL_NUM + LL_ATON_ASSERT(false); // may never happen +#endif // !ATON_EPOCHCTRL_NUM + } + else + { + LL_Streng_Wait(_wait_mask); + } + } + + /* End epoch block and advance to next one */ + __LL_ATON_RT_ExecEndEpochBlock(nn_instance->exec_state.current_epoch_block, nn_instance); + + /* advance epoch block */ + __LL_ATON_RT_DetermineNextEpochBlock(nn_instance); + + /* Return to main loop (but do NOT call `LL_ATON_OSAL_WFE())`) */ + return LL_ATON_RT_NO_WFE; + +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_POLLING) + } +} + +/*** ATON Irq Handler ***/ +#define IRQ_ERR_MSG() LL_ATON_PRINTF("ATON_STD_IRQHandler()@%d: irqs=0x%" PRIx64 "\n", __LINE__, (uint64_t)irqs) + +// REMEMBER: mask out all interrupt from parameter `irqs` you do NOT want to be handled in beyond function +#if (ATON_INT_NR > 32) +static void __LL_ATON_RT_IrqErr(uint64_t irqs) +#else //(ATON_INT_NR <= 32) +static void __LL_ATON_RT_IrqErr(uint32_t irqs) +#endif //(ATON_INT_NR <= 32) +{ + extern void dump_dma_state(void); + int32_t i; + + if (!irqs) + return; + +#ifdef ATON_STRENG_NUM + /* Streaming Engine Error interrupts */ + if (irqs & ATON_INT_GET_MASK(ATON_STRENG_ERR_INT_MASK, ATON_STRENG_NUM)) + { +#if (ATON_INT_NR > 32) + int64_t masked_irqs; // must be signed for two's compliment `(-masked_irqs)` +#else //(ATON_INT_NR <= 32) + int32_t masked_irqs; // must be signed for two's compliment `(-masked_irqs)` +#endif //(ATON_INT_NR <= 32) + + masked_irqs = (irqs & ATON_INT_GET_MASK(ATON_STRENG_ERR_INT_MASK, ATON_STRENG_NUM)); + + // assumes that stream engine interrupts are assigned in the order of their engine number and to consecutive bits + // within the `INTREG` register + uint32_t streaming_engine_nr = (uint32_t)(masked_irqs & (-masked_irqs)); + streaming_engine_nr -= ATON_STRENG_INT(0); + +#ifndef NDEBUG + uint32_t streng_err = ATON_STRENG_IRQ_GET(streaming_engine_nr); + LL_ATON_PRINTF("Streaming engine #%u error interrupt: 0x%" PRIx32 "\n", streaming_engine_nr, streng_err); +#endif // NDEBUG + } + /* Streaming Engine interrupts */ + if (irqs & ATON_STRENG_INT_MASK(ATON_STRENG_NUM, 0, 0)) + { + LL_ATON_PRINTF("Streaming engine completion interrupt\n"); + } +#endif // ATON_STRENG_NUM + +#ifdef ATON_CONVACC_NUM + /* Convolutional accelerators interrupts */ + if (irqs & ATON_INT_GET_MASK(ATON_CONVACC_INT_MASK, ATON_CONVACC_NUM)) + { + LL_ATON_PRINTF("Convolutional accelerator interrupt\n"); + } +#endif // ATON_CONVACC_NUM + +#if defined(ATON_RECBUF_NUM) + /* Reconfigurable buffer interrupts */ + if (irqs & ATON_INT_GET_MASK(ATON_RECBUF_INT_MASK, ATON_RECBUF_NUM)) + { + LL_ATON_PRINTF("Reconfigurable buffer interrupt\n"); + } +#endif // ATON_RECBUF_NUM + +#ifdef ATON_BUSIF_NUM + /* Bus interface interrupts */ + if (irqs & ATON_INT_GET_MASK(ATON_BUSIF_INT_MASK, ATON_BUSIF_NUM)) + { + LL_ATON_PRINTF("Bus interface interrupt\n"); + + /* Report offending stream engine */ + for (i = 0; i < ATON_BUSIF_NUM; i++) + LL_ATON_PRINTF("BUSIF%" PRId32 " ERR: 0x%" PRIx32 "\n", i, ATON_BUSIF_ERR_GET(i)); + } +#endif // ATON_BUSIF_NUM + +#if defined(ATON_STRSWITCH_NUM) + /* Stream switch interrupts */ + if (irqs & ATON_INT_GET_MASK(ATON_STRSWITCH_INT_MASK, ATON_STRSWITCH_NUM)) + { + LL_ATON_PRINTF("Stream switch interrupt\n"); + } +#endif // ATON_STRSWITCH_NUM + +#if defined(ATON_EPOCHCTRL_NUM) + /* Epoch Controller interrupts */ + if (irqs & ATON_INT_GET_MASK(ATON_EPOCHCTRL_ERR_INT_MASK, ATON_EPOCHCTRL_NUM)) + { + LL_ATON_PRINTF("Epoch Controller ERROR interrupt: EC_IRQ = 0x%08" PRIx32 "\n", ATON_EPOCHCTRL_IRQ_GET(0)); + LL_ATON_PRINTF("Epoch Controller opcode counter: 0x%08" PRIx32 "\n", ATON_EPOCHCTRL_BC_GET(0)); + LL_ATON_PRINTF("Epoch Controller label: 0x%08" PRIx32 "\n", ATON_EPOCHCTRL_LABEL_GET(0)); + } + if (irqs & ATON_INT_GET_MASK(ATON_EPOCHCTRL_NOACK_INT_MASK, ATON_EPOCHCTRL_NUM)) + { + LL_ATON_PRINTF("Epoch Controller NOACK interrupt\n"); + } + if (irqs & ATON_INT_GET_MASK(ATON_EPOCHCTRL_INT_MASK, ATON_EPOCHCTRL_NUM)) + { + LL_ATON_PRINTF("Epoch Controller interrupt\n"); + } +#endif // ATON_EPOCHCTRL_NUM + + /* default error handling */ + dump_dma_state(); + IRQ_ERR_MSG(); // just for debug +#if (ATON_PLAT_HAS_FFLUSH) + LL_ATON_FFLUSH(stdout); +#endif + LL_ATON_ASSERT(false); // may never happen + + // TODO: Treat as error! + // All of the above not handled interrupts should be changed in a way that allows both a return from + // this IRQ handler (w/o immediate re-entry) and to return control back to the user's main loop e.g. by using an + // internal flag/variable to signal the error, then performing a `LL_ATON_RT_RuntimeDeInit()`, and returning with a + // respective (new) return value (of type `LL_ATON_RT_RetValues_t`), reporting about the error, from the latest + // call to `LL_ATON_RT_RunEpochBlock()` +} + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) +#if (ATON_INT_NR > 32) +static inline void __LL_ATON_RT_IrqEpochBlock(uint64_t irqs) +#else //(ATON_INT_NR <= 32) +static inline void __LL_ATON_RT_IrqEpochBlock(uint32_t irqs) +#endif //(ATON_INT_NR <= 32) +{ + int32_t i; + + /** AND-mask interrupts MUST be handled here **/ + /* Deal with Streaming Engine interrupts */ +#if (ATON_INT_NR > 32) + uint64_t wait_irqs; +#else //(ATON_INT_NR <= 32) + uint32_t wait_irqs; +#endif //(ATON_INT_NR <= 32) + + /* Beyond code assumes that stream engine interrupts are assigned in the order of their engine number and to + * consecutive bits within the `INTREG` register (and within all other interrupt controller registers, like e.g. + * status/mask/clear)! */ + irqs >>= ATON_STRENG_INT(0); + wait_irqs = + irqs & + __ll_current_aton_ip_owner->exec_state.current_epoch_block + ->wait_mask; /* treat only IRQs we are currently waiting for + (Note: we might be running in a hybrid function which uses DMAs in parallel with a "normal" + ATON execution and we must not clear the IRQs of this "normal" ATON execution here) */ + if (wait_irqs) + { + uint32_t _tmp_triggered_events = __ll_current_aton_ip_owner->exec_state.triggered_events; + for (i = 0; i < ATON_STRENG_NUM; i++) + { + /* Handle event interrupts */ + if ((wait_irqs >> i) & 1) + { /* more future-proofed but less efficient alternative: + `if (wait_irqs & ATON_STRENG_INT_MASK(i, 0, 0))` + */ + uint32_t strengIrqs = ATON_STRENG_IRQ_GET(i); + ATON_STRENG_IRQ_SET( + i, strengIrqs); /* Acknowledge ATON interrupt source (i.e. stream engine #i) - could be more fine grain */ + + /* Handle RT integration */ + _tmp_triggered_events |= (1 << i); + } + } + __ll_current_aton_ip_owner->exec_state.triggered_events = _tmp_triggered_events; + } +} + +#if defined(ATON_EPOCHCTRL_NUM) +#if (ATON_INT_NR > 32) +static inline void __LL_ATON_RT_IrqEpochBlob(uint64_t irqs) +#else //(ATON_INT_NR <= 32) +static inline void __LL_ATON_RT_IrqEpochBlob(uint32_t irqs) +#endif //(ATON_INT_NR <= 32) +{ + uint32_t ecId = EpochBlock_EpochControllerUnit(__ll_current_aton_ip_owner->exec_state.current_epoch_block); + LL_ATON_ASSERT(ecId < ATON_EPOCHCTRL_NUM); // may never happen + if (irqs & ATON_INT_GET_MASK(ATON_EPOCHCTRL_INT_MASK, ecId)) + { + /* Acknowledge interrupts in active epoch controller unit - could be more fine grain */ + uint32_t ecIrqs = ATON_EPOCHCTRL_IRQ_GET(ecId); + ATON_EPOCHCTRL_IRQ_SET(ecId, ecIrqs); + + /* Handle RT integration */ + uint32_t _tmp_triggered_events = __ll_current_aton_ip_owner->exec_state.triggered_events; + _tmp_triggered_events |= (1 << ecId); + __ll_current_aton_ip_owner->exec_state.triggered_events = _tmp_triggered_events; + } +} +#endif // ATON_EPOCHCTRL_NUM +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + +/* ATON ISR + * ll_aton routes all interrupts to `ATON_STD_IRQ_LINE` interrupt line */ +void ATON_STD_IRQHandler(void) +{ + /** Figure out which interrupt(s) fired **/ +#if (ATON_INT_NR > 32) + uint32_t irqs_l = ATON_INTCTRL_INTREG_GET(0); + uint32_t irqs_h = ATON_INTCTRL_INTREG_H_GET(0); + uint64_t irqs = irqs_l | (irqs_h << 32); +#else //(ATON_INT_NR <= 32) + uint32_t irqs = ATON_INTCTRL_INTREG_GET(0); +#endif //(ATON_INT_NR <= 32) + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + if (__ll_current_aton_ip_owner != NULL) + { + LL_ATON_ASSERT(__ll_current_aton_ip_owner->exec_state.current_epoch_block != NULL); + + /** OR-mask interrupts MUST be handled first **/ + if (!EpochBlock_IsEpochBlob(__ll_current_aton_ip_owner->exec_state + .current_epoch_block)) // standard epoch block handling based on streaming engines + { + __LL_ATON_RT_IrqErr( + irqs & ~ATON_STRENG_INT_MASK(ATON_STRENG_NUM, 0, 0)); /* exclude all streaming engine completion interrupts */ + } + else // epoch blob handling based on epoch controller + { +#if defined(ATON_EPOCHCTRL_NUM) + uint32_t ecId = EpochBlock_EpochControllerUnit(__ll_current_aton_ip_owner->exec_state.current_epoch_block); + LL_ATON_ASSERT(ecId < ATON_EPOCHCTRL_NUM); // may never happen + + // epoch blob handling based on epoch controller interrupt + __LL_ATON_RT_IrqErr( + irqs & ~ATON_INT_GET_MASK(ATON_EPOCHCTRL_INT_MASK, + ecId)); /* exclude epoch controller interrupt for active epoch controller unit */ +#else // !ATON_EPOCHCTRL_NUM + LL_ATON_ASSERT(false); // may never happen +#endif // !ATON_EPOCHCTRL_NUM + } + } + else // `__ll_current_aton_ip_owner == NULL` + { + __LL_ATON_RT_IrqErr(irqs); /* treat all interrupts as errors */ + } +#else // (LL_ATON_RT_MODE == LL_ATON_RT_POLLING) + __LL_ATON_RT_IrqErr(irqs); /* treat all interrupts as errors */ +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_POLLING) + +#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + LL_ATON_ASSERT(__ll_current_aton_ip_owner != NULL); + + if (!EpochBlock_IsEpochBlob(__ll_current_aton_ip_owner->exec_state.current_epoch_block)) + { // standard epoch block handling based on streaming engines + __LL_ATON_RT_IrqEpochBlock(irqs); + } + else + { // epoch blob handling based on epoch controller +#if defined(ATON_EPOCHCTRL_NUM) + __LL_ATON_RT_IrqEpochBlob(irqs); +#else // !ATON_EPOCHCTRL_NUM + LL_ATON_ASSERT(false); // may never happen +#endif // !ATON_EPOCHCTRL_NUM + } + + /* Data Synchronization Barrier */ + LL_ATON_OSAL_DSB(); + + /* Clear all interrupts in interrupt controller. + * Note: this must be done *after* having cleared ATON interrupt sources otherwise + * interrupts will be re-latched. + */ +#if (ATON_INT_NR > 32) + ATON_INTCTRL_INTCLR_SET(0, irqs_l); + ATON_INTCTRL_INTCLR_H_SET(0, irqs_h); +#else //(ATON_INT_NR <= 32) + ATON_INTCTRL_INTCLR_SET(0, irqs); +#endif //(ATON_INT_NR <= 32) + + /* Data Synchronization Barrier */ + LL_ATON_OSAL_DSB(); + + /* Signal event */ + LL_ATON_OSAL_SIGNAL_EVENT(); + +#endif // (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC) + + return; +} diff --git a/lib/stai/libstai/ll_aton/ll_aton_util.c b/lib/stai/libstai/ll_aton/ll_aton_util.c new file mode 100644 index 000000000..1a27109ad --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_aton_util.c @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file ll_aton_util.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief ATON LL utility functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include +#include +#include + +#include "ll_aton_util.h" + +/** + * @brief Helper function. Extracts bitfield from a buffer + * @param bits Pointer of the buffer to extract bits from + * @param pos Global bit position of the bitfield to extract + * @param nbits Number of bits to extract + * @retval extracted bitfield + */ +uint32_t LL_ATON_getbits(uint32_t *bits, unsigned int pos, int nbits) +{ + unsigned int mask = (1ULL << nbits) - 1; + uint32_t value; + const int bitsperint = (sizeof(unsigned) * 8); + int index0 = pos / bitsperint; + int index1 = (pos + nbits) / bitsperint; + // Do the bits to extract cross a boundary? + if (index0 == index1) + { + value = (bits[index0] >> (pos % bitsperint)) & mask; + } + else + { + unsigned int lshift = ((pos + nbits) % bitsperint); + value = + (((bits[index0] >> (pos % bitsperint)) & mask) | ((bits[index1] & ((1ULL << lshift) - 1)) << (nbits - lshift))); + } + + // handle sign extension (not sure if this must be done in every use case) + if (nbits > 0) + { + unsigned int signed_mask = (1UL << (nbits - 1)); + if (value & signed_mask) + { + value = value | ~mask; + } + } + + return value; +} + +/** + * @brief Helper function. Packs bitfield into a buffer + * @param bits Pointer of the buffer to pack bits into + * @param pos Global position of the bitfield to pack + * @retval nbits Number of bits to extract + */ +void LL_ATON_setbits(uint32_t *bits, unsigned int pos, int nbits, unsigned int val) +{ + const int bitsperint = sizeof(unsigned int) * 8; + unsigned int smask = ((1ULL << nbits) - 1) << (pos % bitsperint); + unsigned int mask = ((1ULL << nbits) - 1); + int index0 = pos / bitsperint; + int index1 = (pos + nbits - 1) / bitsperint; + if (index0 == index1) + { + uint32_t tmp = (bits[index0] & ~smask) | ((val & mask) << (pos % bitsperint)); + bits[index0] = tmp; + } + else + { + unsigned int lshift = ((pos + nbits) % bitsperint); + uint32_t tmp = (bits[index0] & ~smask) | ((val & mask) << (pos % bitsperint)); + bits[index0] = tmp; + tmp = (bits[index1] & ((1ULL << lshift) - 1)) | ((val & mask) >> (nbits - lshift)); + bits[index1] = tmp; + } +} diff --git a/lib/stai/libstai/ll_aton/ll_sw_float.c b/lib/stai/libstai/ll_aton/ll_sw_float.c new file mode 100644 index 000000000..3d2f894ff --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_sw_float.c @@ -0,0 +1,1508 @@ +/** + ****************************************************************************** + * @file ll_sw_float.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Low Level Software library for Floating Point inference interfacing with EmbedNets(c) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_config.h" + +#if LL_ATON_SW_FALLBACK == 1 + +#include +#include +#include + +#include "ll_sw.h" +#include "ll_sw_float.h" + +#include "ai_datatypes_internal.h" +#include "ai_math_helpers.h" +#include "core_private.h" +#include "layers.h" +#include "ll_aton_util.h" + +#define FORMAT AI_ARRAY_FORMAT_FLOAT + +#define SHAPE_INIT(a_, b_, c_, d_) AI_SHAPE_INIT(4, (d_), (c_), (b_), (a_)) + +#define SHAPE_2D_INIT(h_, w_) AI_SHAPE_2D_INIT((w_), (h_)) + +#define STRIDE_INIT(a_, b_, c_, d_) AI_STRIDE_INIT(4, (d_), (c_), (b_), (a_)) + +#define TENSORS(...) __VA_ARGS__ + +/* Managing shape index to be consistent with the enum in embednets ai_platform.h */ +static int helper_emit_shape_index_axis(int onnx_axis) +{ + switch (onnx_axis) + { + case 0: + return AI_SHAPE_IN_CHANNEL; + case 1: + return AI_SHAPE_CHANNEL; + case 2: + return AI_SHAPE_HEIGHT; // note the switch required with case 3 + case 3: + return AI_SHAPE_WIDTH; // note the switch required with case 2 + default: +#ifdef LL_SW_ENABLE_ASSERTS + LL_ATON_ASSERT(0 && "axis index not supported"); +#endif + return -1; + } +} + +//########################################################################################## +/** Conv forward function */ +void ll_sw_forward_conv(/* int processor, */ void *sw_info_struct) +{ + Conv_sw_info *sw_info = (Conv_sw_info *)sw_info_struct; + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(conv_weights_array, FORMAT, sw_info->weights.mem.start_offset, sw_info->weights.mem.start_offset, + sw_info->weights.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(conv_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_TENSOR_OBJ_DECLARE(conv_weights, , 0x0, 4, + SHAPE_INIT(sw_info->weights.dim.tensor_b, sw_info->weights.dim.tensor_h, + sw_info->weights.dim.tensor_w, sw_info->weights.dim.tensor_c), + STRIDE_INIT(sw_info->weights.stride.h, sw_info->weights.stride.w, sw_info->weights.stride.b, + sw_info->weights.stride.b), + 1, &conv_weights_array, NULL); + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL); + AI_TENSOR_OBJ_DECLARE(conv_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &conv_output_array, NULL); + + if (sw_info->bias.mem.start_offset != NULL) + { + AI_ARRAY_OBJ_DECLARE(conv_bias_array, FORMAT, sw_info->bias.mem.start_offset, sw_info->bias.mem.start_offset, + sw_info->bias.dim.num_elem, ) + AI_TENSOR_OBJ_DECLARE( + conv_bias, , 0x0, 4, + SHAPE_INIT(sw_info->bias.dim.tensor_h, sw_info->bias.dim.tensor_w, sw_info->bias.dim.tensor_c, + sw_info->bias.dim.tensor_b), + STRIDE_INIT(sw_info->bias.stride.h, sw_info->bias.stride.w, sw_info->bias.stride.c, sw_info->bias.stride.b), 1, + &conv_bias_array, NULL); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(conv_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&conv_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&conv_weights, &conv_bias, NULL)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 2, TENSORS(NULL, NULL))) + // layer initialization + AI_LAYER_OBJ_DECLARE(conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_conv2d_if32of32wf32_group, &conv_chain, + NULL, NULL, , .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], + sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = + SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + else + { + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(conv_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&conv_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&conv_weights, NULL, NULL)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 2, TENSORS(NULL, NULL))) + // layer initialization + AI_LAYER_OBJ_DECLARE(conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_conv2d_if32of32wf32_group, &conv_chain, + NULL, NULL, , .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], + sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = + SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } +} + +//########################################################################################## +/** GEMM forward function */ +void ll_sw_forward_gemm(/* int processor, */ void *sw_info_struct) +{ + Gemm_sw_info *sw_info = (Gemm_sw_info *)sw_info_struct; + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(gemm_operand_b_array, FORMAT, sw_info->operand_b.mem.start_offset, + sw_info->operand_b.mem.start_offset, sw_info->operand_b.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(gemm_operand_c_array, FORMAT, sw_info->operand_c.mem.start_offset, + sw_info->operand_c.mem.start_offset, sw_info->operand_c.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(gemm_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL); + AI_TENSOR_OBJ_DECLARE(gemm_operand_b, , 0x0, 4, + SHAPE_INIT(sw_info->operand_b.dim.tensor_h, sw_info->operand_b.dim.tensor_w, + sw_info->operand_b.dim.tensor_c, sw_info->operand_b.dim.tensor_b), + STRIDE_INIT(sw_info->operand_b.stride.h, sw_info->operand_b.stride.w, + sw_info->operand_b.stride.c, sw_info->operand_b.stride.b), + 1, &gemm_operand_b_array, NULL); + AI_TENSOR_OBJ_DECLARE(gemm_operand_c, , 0x0, 4, + SHAPE_INIT(sw_info->operand_c.dim.tensor_h, sw_info->operand_c.dim.tensor_w, + sw_info->operand_c.dim.tensor_c, sw_info->operand_c.dim.tensor_b), + STRIDE_INIT(sw_info->operand_c.stride.h, sw_info->operand_c.stride.w, + sw_info->operand_c.stride.c, sw_info->operand_c.stride.b), + 1, &gemm_operand_c_array, NULL); + + AI_TENSOR_OBJ_DECLARE(gemm_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &gemm_output_array, NULL); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE( + gemm_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&input_output, &gemm_operand_b, &gemm_operand_c)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&gemm_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + // layer initialization + AI_LAYER_OBJ_DECLARE(gemm_layer, 1, GEMM_TYPE, 0x0, NULL, gemm, forward_gemm, &gemm_chain, NULL, NULL, , + .alpha = sw_info->alpha, .beta = sw_info->beta, .tA = sw_info->tA, .tB = sw_info->tB) + gemm_layer.forward(AI_LAYER_OBJ(&gemm_layer)); +} + +//########################################################################################## +/** MatMul forward function */ +void ll_sw_forward_matmul(/* int processor, */ void *sw_info_struct) +{ + Matmul_sw_info *sw_info = (Matmul_sw_info *)sw_info_struct; + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(matmul_operand_b_array, FORMAT, sw_info->operand_b.mem.start_offset, + sw_info->operand_b.mem.start_offset, sw_info->operand_b.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(matmul_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL); + AI_TENSOR_OBJ_DECLARE(matmul_operand_b, , 0x0, 4, + SHAPE_INIT(sw_info->operand_b.dim.tensor_h, sw_info->operand_b.dim.tensor_w, + sw_info->operand_b.dim.tensor_c, sw_info->operand_b.dim.tensor_b), + STRIDE_INIT(sw_info->operand_b.stride.h, sw_info->operand_b.stride.w, + sw_info->operand_b.stride.c, sw_info->operand_b.stride.b), + 1, &matmul_operand_b_array, NULL); + + AI_TENSOR_OBJ_DECLARE(matmul_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &matmul_output_array, NULL); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(matmul_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 2, TENSORS(&input_output, &matmul_operand_b)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&matmul_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + // layer initialization + AI_LAYER_OBJ_DECLARE(matmul_layer, 1, NL_TYPE, 0x0, NULL, nl, forward_matmul, &matmul_chain, NULL, NULL, , ) + matmul_layer.forward(AI_LAYER_OBJ(&matmul_layer)); +} + +//########################################################################################## +/** Resize forward function */ +void ll_sw_forward_resize(/* int processor, */ void *sw_info_struct) +{ + Resize_sw_info *sw_info = (Resize_sw_info *)sw_info_struct; + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(resize_scales_array, FORMAT, sw_info->scales.mem.start_offset, sw_info->scales.mem.start_offset, + sw_info->scales.dim.num_elem, ) + + ai_array *resize_roi_array_ptr = NULL; + ai_array resize_roi_array; + if (sw_info->roi.mem.start_offset != NULL) + { + resize_roi_array = (ai_array)AI_ARRAY_OBJ_INIT(FORMAT, sw_info->roi.mem.start_offset, sw_info->roi.mem.start_offset, + sw_info->roi.dim.num_elem); + resize_roi_array_ptr = &resize_roi_array; + } + + AI_ARRAY_OBJ_DECLARE(resize_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL); + AI_TENSOR_OBJ_DECLARE(resize_scales, , 0x0, 4, + SHAPE_INIT(sw_info->scales.dim.tensor_h, sw_info->scales.dim.tensor_w, + sw_info->scales.dim.tensor_c, sw_info->scales.dim.tensor_b), + STRIDE_INIT(sw_info->scales.stride.h, sw_info->scales.stride.w, sw_info->scales.stride.c, + sw_info->scales.stride.b), + 1, &resize_scales_array, NULL); + + AI_TENSOR_OBJ_DECLARE(resize_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &resize_output_array, NULL); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(resize_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&resize_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + // extrapolating the scales values needed + const ai_tensor *p = &resize_scales; + const ai_float *s = AI_ARRAY_OBJ_DATA(p->data, ai_float); + AI_ARRAY_OBJ_DECLARE_STATIC(rs, ai_float, AI_ARRAY_FORMAT_FLOAT, AI_CONST, 2, s[2], s[3]) + + // layer initialization + if ((ai_resize_mode)sw_info->mode == AI_RESIZE_ZEROS) + { + AI_LAYER_OBJ_DECLARE(resize_layer, 1, UPSAMPLE_TYPE, 0x0, NULL, upsample, forward_upsample_zeros, &resize_chain, + NULL, NULL, , .mode = AI_UPSAMPLE_ZEROS, .center = false, .scales = AI_ARRAY_OBJ(&rs), + .nearest_mode = AI_ROUND_PREFER_FLOOR) + resize_layer.forward(AI_LAYER_OBJ(&resize_layer)); + } + else + { + AI_LAYER_OBJ_DECLARE(resize_layer, 1, RESIZE_TYPE, 0x0, NULL, resize, forward_resize, &resize_chain, NULL, NULL, , + .cubic_coeff_a = sw_info->cubic_coeff_a, .exclude_outside = sw_info->exclude_outside, + .extrapol_val = sw_info->extrapol_val, .mode = (ai_resize_mode)sw_info->mode, + .nearest_mode = (ai_nearest_mode)sw_info->nearest_mode, + .coord_transf_mode = (ai_coord_transf_mode)sw_info->coord_transf_mode, + .scales = AI_ARRAY_OBJ(&rs), .roi = resize_roi_array_ptr) + resize_layer.forward(AI_LAYER_OBJ(&resize_layer)); + } +} + +//########################################################################################## +/** Softmax forward function */ +void ll_sw_forward_softmax(/* int processor, */ void *sw_info_struct) +{ + Softmax_sw_info *sw_info = (Softmax_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(softmax_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(sm_scratch0_array, AI_ARRAY_FORMAT_S32, sw_info->scratch.mem.start_offset, + sw_info->scratch.mem.start_offset, sw_info->scratch.dim.num_elem, ) + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL); + + AI_TENSOR_OBJ_DECLARE(softmax_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &softmax_output_array, NULL); + + AI_TENSOR_OBJ_DECLARE(sm_scratch0, , 0x0, 4, + SHAPE_INIT(sw_info->scratch.dim.tensor_h, sw_info->scratch.dim.tensor_w, + sw_info->scratch.dim.tensor_c, sw_info->scratch.dim.tensor_b), + STRIDE_INIT(sw_info->scratch.stride.h, sw_info->scratch.stride.w, sw_info->scratch.stride.c, + sw_info->scratch.stride.b), + 1, &sm_scratch0_array, NULL); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(softmax_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&softmax_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&sm_scratch0))) + + AI_LAYER_OBJ_DECLARE(sm_layer, 1, SM_TYPE, 0x0, NULL, sm, forward_sm, &softmax_chain, NULL, NULL, , + .axis = helper_emit_shape_index_axis(sw_info->axis)) + sm_layer.forward(AI_LAYER_OBJ(&sm_layer)); +} + +//########################################################################################## +/** activ forward function */ +void ll_sw_forward_activ(/* int processor, */ void *sw_info_struct) +{ + Activ_sw_info *sw_info = (Activ_sw_info *)sw_info_struct; + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(activ_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(activ_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &activ_output_array, NULL) + // tensor chains init + AI_TENSOR_CHAIN_OBJ_DECLARE(activ_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + switch (sw_info->general.type) + { + case LL_SW_RELU: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_relu, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_CLIP: + { + AI_ARRAY_OBJ_DECLARE_STATIC(clip_layer_params, ai_float, AI_ARRAY_FORMAT_FLOAT, AI_CONST, 2, sw_info->min, + sw_info->max) + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_clip, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&clip_layer_params)) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_PRELU: + { + AI_ARRAY_OBJ_DECLARE(activ_operand_array, FORMAT, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + + AI_TENSOR_OBJ_DECLARE(activ_operand, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &activ_operand_array, NULL) + + // tensor chains init + AI_TENSOR_CHAIN_OBJ_DECLARE( + prelu_activ_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_operand)), AI_TENSOR_LIST_OBJ_EMPTY) + + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_prelu, &prelu_activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ELU: + { + // defining the array of params needed + AI_ARRAY_OBJ_DECLARE_STATIC(elu_layer_params, ai_float, FORMAT, , 1, sw_info->alpha) + + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_elu, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&elu_layer_params), ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_THRESHOLDEDRELU: + { + // defining the array of params needed + AI_ARRAY_OBJ_DECLARE_STATIC(thresholdedrelu_layer_params, ai_float, FORMAT, , 1, sw_info->alpha) + + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_relu_thresholded, &activ_chain, NULL, + NULL, , .nl_params = AI_ARRAY_OBJ(&thresholdedrelu_layer_params), ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SELU: + { + // defining the array of params needed + AI_ARRAY_OBJ_DECLARE_STATIC(selu_layer_params, ai_float, FORMAT, , 2, sw_info->alpha, sw_info->gamma) + + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_selu, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&selu_layer_params), ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_CEIL: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_ceil, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_FLOOR: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_floor, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_EXP: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_exp, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_LOG: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_log, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ACOS: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_acos, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ACOSH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_acosh, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ASIN: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_asin, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ASINH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_asinh, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ATAN: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_atan, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ATANH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_atanh, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_COS: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_cos, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_COSH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_cosh, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SIN: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_sin, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SINH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_sinh, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_TANH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_tanh, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_TAN: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_tan, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SIGMOID: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_sigmoid, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SQRT: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_sqrt, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ERF: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_erf, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SOFTPLUS: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_soft_plus, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SOFTSIGN: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_soft_sign, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_HARDSIGMOID: + { + AI_ARRAY_OBJ_DECLARE_STATIC(hard_sigmoid_layer_params, ai_float, AI_ARRAY_FORMAT_FLOAT, AI_CONST, 2, sw_info->alpha, + sw_info->beta) + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_hard_sigmoid, &activ_chain, NULL, NULL, + , .nl_params = AI_ARRAY_OBJ(&hard_sigmoid_layer_params), ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_SWISH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_swish, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_HARDSWISH: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_hard_swish, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_HARDMAX: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_hardmax, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ABS: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_abs, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_NEG: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_neg, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_RECIPROCAL: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_reciprocal, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + case LL_SW_ROUND: + { + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_round, &activ_chain, NULL, NULL, , + .nl_params = NULL, ) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + default: +#ifdef LL_SW_ENABLE_ASSERTS + LL_ATON_ASSERT(0 && "NL OPERATION NOT SUPPORTED"); +#endif + break; + } +} + +//########################################################################################## +/** activ forward function */ +void ll_sw_forward_arith(/* int processor, */ void *sw_info_struct) +{ + Arith_sw_info *sw_info = (Arith_sw_info *)sw_info_struct; + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(arith_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(arith_operand_array, FORMAT, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(arith_operand, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &arith_operand_array, NULL) + AI_TENSOR_OBJ_DECLARE(arith_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &arith_output_array, NULL) + + // layer initialization + func_binary op = ai_sum; /**< operation to apply elementwise */ + func_buffer_binary buffer_op = ai_sum_buffer; /**< operation to apply elementwise */ + + switch (sw_info->general.type) + { + case LL_SW_ARITHADD: + case LL_SW_ARITHSUM: + op = ((func_binary)(ai_sum)); + buffer_op = ((func_buffer_binary)(ai_sum_buffer)); + break; + case LL_SW_ARITHMUL: + op = ((func_binary)(ai_mul)); + buffer_op = ((func_buffer_binary)(ai_mul_buffer)); + break; + case LL_SW_ARITHDIV: + op = ((func_binary)(ai_div)); + buffer_op = ((func_buffer_binary)(ai_div_buffer)); + break; + case LL_SW_ARITHSUB: + op = ((func_binary)(ai_sub)); + buffer_op = ((func_buffer_binary)(ai_sub_buffer)); + break; + case LL_SW_POW: + op = ((func_binary)(ai_pow)); + buffer_op = ((func_buffer_binary)(ai_pow_buffer)); + break; + case LL_SW_GREATER: + op = ((func_binary)(ai_greater)); + buffer_op = ((func_buffer_binary)(ai_greater_buffer)); + break; + case LL_SW_GREATEROREQUAL: + op = ((func_binary)(ai_greater_or_equal)); + buffer_op = ((func_buffer_binary)(ai_greater_or_equal_buffer)); + break; + case LL_SW_LESS: + op = ((func_binary)(ai_less)); + buffer_op = ((func_buffer_binary)(ai_less_buffer)); + break; + case LL_SW_EQUAL: + op = ((func_binary)(ai_equal)); + buffer_op = ((func_buffer_binary)(ai_equal_buffer)); + break; + case LL_SW_LESSOREQUAL: + op = ((func_binary)(ai_less_or_equal)); + buffer_op = ((func_buffer_binary)(ai_less_or_equal_buffer)); + break; + case LL_SW_MIN: + op = ((func_binary)(ai_min)); + buffer_op = ((func_buffer_binary)(ai_min_buffer)); + break; + case LL_SW_MAX: + op = ((func_binary)(ai_max)); + buffer_op = ((func_buffer_binary)(ai_max_buffer)); + break; + case LL_SW_MOD: + op = ((func_binary)(ai_floor_mod)); + buffer_op = ((func_buffer_binary)(ai_floor_mod_buffer)); + break; + default: +#ifdef LL_SW_ENABLE_ASSERTS + LL_ATON_ASSERT(0 && "ELEMENT WISE OPERATION NOT SUPPORTED"); +#endif + break; + } + + if (sw_info->general.type == LL_SW_ARITHSUM && sw_info->num_of_inputs == 4) + { + AI_ARRAY_OBJ_DECLARE(arith_operand_array1, FORMAT, sw_info->operand1.mem.start_offset, + sw_info->operand1.mem.start_offset, sw_info->operand1.dim.num_elem, ); + AI_ARRAY_OBJ_DECLARE(arith_operand_array2, FORMAT, sw_info->operand2.mem.start_offset, + sw_info->operand2.mem.start_offset, sw_info->operand2.dim.num_elem, ); + AI_TENSOR_OBJ_DECLARE(arith_operand1, , 0x0, 4, + SHAPE_INIT(sw_info->operand1.dim.tensor_h, sw_info->operand1.dim.tensor_w, + sw_info->operand1.dim.tensor_c, sw_info->operand1.dim.tensor_b), + STRIDE_INIT(sw_info->operand1.stride.h, sw_info->operand1.stride.w, + sw_info->operand1.stride.c, sw_info->operand1.stride.b), + 1, &arith_operand_array1, NULL); + AI_TENSOR_OBJ_DECLARE(arith_operand2, , 0x0, 4, + SHAPE_INIT(sw_info->operand2.dim.tensor_h, sw_info->operand2.dim.tensor_w, + sw_info->operand2.dim.tensor_c, sw_info->operand2.dim.tensor_b), + STRIDE_INIT(sw_info->operand2.stride.h, sw_info->operand2.stride.w, + sw_info->operand2.stride.c, sw_info->operand2.stride.b), + 1, &arith_operand_array2, NULL); + + // LL_ATON_PRINTF("\n\n\n #################### 4 inputs\n\n\n"); + AI_TENSOR_CHAIN_OBJ_DECLARE( + arith_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 4, + TENSORS(&input_output, &arith_operand, &arith_operand1, &arith_operand2)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&arith_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY); + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_TYPE, 0x0, NULL, eltwise, forward_eltwise, &arith_chain, NULL, NULL, + , .operation = op, .buffer_operation = buffer_op) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + } + else if (sw_info->general.type == LL_SW_ARITHSUM && sw_info->num_of_inputs == 3) + { + AI_ARRAY_OBJ_DECLARE(arith_operand_array1, FORMAT, sw_info->operand1.mem.start_offset, + sw_info->operand1.mem.start_offset, sw_info->operand1.dim.num_elem, ); + AI_TENSOR_OBJ_DECLARE(arith_operand1, , 0x0, 4, + SHAPE_INIT(sw_info->operand1.dim.tensor_h, sw_info->operand1.dim.tensor_w, + sw_info->operand1.dim.tensor_c, sw_info->operand1.dim.tensor_b), + STRIDE_INIT(sw_info->operand1.stride.h, sw_info->operand1.stride.w, + sw_info->operand1.stride.c, sw_info->operand1.stride.b), + 1, &arith_operand_array1, NULL); + // LL_ATON_PRINTF("\n\n\n #################### 3 inputs\n\n\n"); + AI_TENSOR_CHAIN_OBJ_DECLARE( + arith_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&input_output, &arith_operand, &arith_operand1)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&arith_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY); + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_TYPE, 0x0, NULL, eltwise, forward_eltwise, &arith_chain, NULL, NULL, + , .operation = op, .buffer_operation = buffer_op) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + } + else + { + // LL_ATON_PRINTF("\n\n\n #################### 2 inputs\n\n\n"); + AI_TENSOR_CHAIN_OBJ_DECLARE(arith_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 2, TENSORS(&input_output, &arith_operand)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&arith_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY); + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_TYPE, 0x0, NULL, eltwise, forward_eltwise, &arith_chain, NULL, NULL, + , .operation = op, .buffer_operation = buffer_op) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + } +} + +//########################################################################################## +/** pool forward function */ +void ll_sw_forward_pool(/* int processor, */ void *sw_info_struct) +{ + Pool_sw_info *sw_info = (Pool_sw_info *)sw_info_struct; + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(pool_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensor init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(pool_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &pool_output_array, NULL) + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(pool_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&pool_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + + node_func func = NULL; + bool count_include_pad = 0; + switch (sw_info->general.type) + { + case LL_SW_AVGPOOL: + func = ((node_func)(forward_ap)); + count_include_pad = sw_info->count_include_pad; + break; + case LL_SW_MAXPOOL: + func = ((node_func)(forward_mp)); + break; + default: + break; + } + + AI_LAYER_OBJ_DECLARE(pool_layer, 1, POOL_TYPE, 0x0, NULL, pool, func, &pool_chain, NULL, NULL, , + .pool_size = SHAPE_2D_INIT(sw_info->k_shape[0], sw_info->k_shape[1]), + .pool_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), + .pool_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .count_include_pad = count_include_pad, ) + pool_layer.forward(AI_LAYER_OBJ(&pool_layer)); +} + +//########################################################################################## +/** Globalpool forward function */ +void ll_sw_forward_global_pool(/* int processor, */ void *sw_info_struct) +{ + Global_pool_sw_info *sw_info = (Global_pool_sw_info *)sw_info_struct; + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(pool_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensor init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(pool_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &pool_output_array, NULL) + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(pool_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&pool_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + + node_func func = NULL; + switch (sw_info->general.type) + { + case LL_SW_AVGPOOL: + func = ((node_func)(forward_ap)); + break; + case LL_SW_MAXPOOL: + func = ((node_func)(forward_mp)); + break; + default: + break; + } + + AI_LAYER_OBJ_DECLARE(pool_layer, 1, POOL_TYPE, 0x0, NULL, pool, func, &pool_chain, NULL, NULL, , + .pool_size = + SHAPE_2D_INIT(sw_info->general.input.dim.tensor_w, sw_info->general.input.dim.tensor_w), + .pool_stride = SHAPE_2D_INIT(1, 1), .pool_pad = SHAPE_INIT(0, 0, 0, 0), ) + pool_layer.forward(AI_LAYER_OBJ(&pool_layer)); +} + +//########################################################################################## +/** ArgMax forward function */ +void ll_sw_forward_argmax(/* int processor, */ void *sw_info_struct) +{ + Argmax_sw_info *sw_info = (Argmax_sw_info *)sw_info_struct; + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(argmax_output_array, AI_ARRAY_FORMAT_S32, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensor init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(argmax_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &argmax_output_array, NULL) + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(argmax_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&argmax_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + AI_LAYER_OBJ_DECLARE(argmax_layer, 1, ARGMINMAX_TYPE, 0x0, NULL, argminmax, forward_argmax, &argmax_chain, NULL, NULL, + , .axis = helper_emit_shape_index_axis(sw_info->axis), + .select_last_index = sw_info->select_last_index, ) + argmax_layer.forward(AI_LAYER_OBJ(&argmax_layer)); +} + +//########################################################################################## +/** Gather forward function */ +void ll_sw_forward_gather(/* int processor, */ void *sw_info_struct) +{ + Gather_sw_info *sw_info = (Gather_sw_info *)sw_info_struct; + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(indexes_array, AI_ARRAY_FORMAT_S32, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(gather_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensor init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(indexes, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &indexes_array, NULL) + AI_TENSOR_OBJ_DECLARE(gather_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &gather_output_array, NULL) + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(gather_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 2, TENSORS(&input_output), TENSORS(&indexes)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&gather_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + // LL_ATON_PRINTF("axis %d \n", sw_info->axis); + // LL_ATON_PRINTF("index %d \n", *(int32_t *)(sw_info->operand.mem.start_offset)); + // LL_ATON_FFLUSH(stdout); + AI_LAYER_OBJ_DECLARE(gather_layer, 1, GATHER_TYPE, 0x0, NULL, gather, forward_gather, &gather_chain, NULL, NULL, , + .axis = helper_emit_shape_index_axis(sw_info->axis), ) + gather_layer.forward(AI_LAYER_OBJ(&gather_layer)); +} + +//########################################################################################## +/** ArgMin forward function */ +void ll_sw_forward_argmin(/* int processor, */ void *sw_info_struct) +{ + Argmin_sw_info *sw_info = (Argmin_sw_info *)sw_info_struct; + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(argmin_output_array, AI_ARRAY_FORMAT_S32, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensor init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(argmin_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &argmin_output_array, NULL) + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(argmin_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&argmin_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + AI_LAYER_OBJ_DECLARE(argmin_layer, 1, ARGMINMAX_TYPE, 0x0, NULL, argminmax, forward_argmin, &argmin_chain, NULL, NULL, + , .axis = helper_emit_shape_index_axis(sw_info->axis), + .select_last_index = sw_info->select_last_index, ) + argmin_layer.forward(AI_LAYER_OBJ(&argmin_layer)); +} + +//########################################################################################## +/** Reduce forward function */ +void ll_sw_forward_reduce(/* int processor, */ void *sw_info_struct) +{ + Reduce_sw_info *sw_info = (Reduce_sw_info *)sw_info_struct; + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(reduce_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + // tensor init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(reduce_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &reduce_output_array, NULL) + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(reduce_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&reduce_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + if (sw_info->general.type == LL_SW_REDUCELOGSUMEXP) + { + AI_LAYER_OBJ_DECLARE(reduce_layer, 1, REDUCE_TYPE, 0x0, NULL, reduce_log_sum_exp, forward_reduce_log_sum_exp, + &reduce_chain, NULL, NULL, , .axis = helper_emit_shape_index_axis(sw_info->axis)) + reduce_layer.forward(AI_LAYER_OBJ(&reduce_layer)); + } + else + { + // element wise function to be applied to perform the reduction + func_binary func = NULL; + // Initialization value for operation + float value = 0.0f; + + switch (sw_info->general.type) + { + // case LL_SW_REDUCEMEAN: + // func = ai_mean + // break; + case LL_SW_REDUCESUM: + func = ai_sum; + value = 0.0f; + break; + case LL_SW_REDUCEMIN: + func = ai_min; + value = AI_FLT_MAX; + break; + case LL_SW_REDUCEMAX: + func = ai_max; + value = 0.0f; + break; + case LL_SW_REDUCEPROD: + func = ai_max; + value = 0.0f; + break; + default: +#ifdef LL_SW_ENABLE_ASSERTS + LL_ATON_ASSERT(0 && "REDUCTION OPERATIONS NOT SUPPORTED"); +#endif + break; + } + AI_ARRAY_OBJ_DECLARE_STATIC(value_f, ai_float, AI_ARRAY_FORMAT_FLOAT, AI_CONST, 1, value) + + AI_LAYER_OBJ_DECLARE(reduce_layer, 1, REDUCE_TYPE, 0x0, NULL, reduce, forward_reduce, &reduce_chain, NULL, NULL, , + .neutral_value = (&value_f), .operation = func) + + reduce_layer.forward(AI_LAYER_OBJ(&reduce_layer)); + } +} + +//########################################################################################## +/** Batch Norm forward function */ +void ll_sw_forward_bn(/* int processor, */ void *sw_info_struct) +{ + Bn_sw_info *sw_info = (Bn_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(bn_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(bn_bias_array, FORMAT, sw_info->bias.mem.start_offset, sw_info->bias.mem.start_offset, + sw_info->bias.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(bn_scale_array, FORMAT, sw_info->scale.mem.start_offset, sw_info->scale.mem.start_offset, + sw_info->scale.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(bn_mean_array, FORMAT, sw_info->mean.mem.start_offset, sw_info->mean.mem.start_offset, + sw_info->mean.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(bn_var_array, FORMAT, sw_info->var.mem.start_offset, sw_info->var.mem.start_offset, + sw_info->var.dim.num_elem, ) + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(bn_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &bn_output_array, NULL) + AI_TENSOR_OBJ_DECLARE( + bn_bias, , 0x0, 4, + SHAPE_INIT(sw_info->bias.dim.tensor_h, sw_info->bias.dim.tensor_w, sw_info->bias.dim.tensor_c, + sw_info->bias.dim.tensor_b), + STRIDE_INIT(sw_info->bias.stride.h, sw_info->bias.stride.w, sw_info->bias.stride.c, sw_info->bias.stride.b), 1, + &bn_bias_array, NULL); + AI_TENSOR_OBJ_DECLARE( + bn_scale, , 0x0, 4, + SHAPE_INIT(sw_info->scale.dim.tensor_h, sw_info->scale.dim.tensor_w, sw_info->scale.dim.tensor_c, + sw_info->scale.dim.tensor_b), + STRIDE_INIT(sw_info->scale.stride.h, sw_info->scale.stride.w, sw_info->scale.stride.c, sw_info->scale.stride.b), + 1, &bn_scale_array, NULL); + AI_TENSOR_OBJ_DECLARE( + bn_mean, , 0x0, 4, + SHAPE_INIT(sw_info->mean.dim.tensor_h, sw_info->mean.dim.tensor_w, sw_info->mean.dim.tensor_c, + sw_info->mean.dim.tensor_b), + STRIDE_INIT(sw_info->mean.stride.h, sw_info->mean.stride.w, sw_info->mean.stride.c, sw_info->mean.stride.b), 1, + &bn_mean_array, NULL); + AI_TENSOR_OBJ_DECLARE( + bn_var, , 0x0, 4, + SHAPE_INIT(sw_info->var.dim.tensor_h, sw_info->var.dim.tensor_w, sw_info->var.dim.tensor_c, + sw_info->var.dim.tensor_b), + STRIDE_INIT(sw_info->var.stride.h, sw_info->var.stride.w, sw_info->var.stride.c, sw_info->var.stride.b), 1, + &bn_var_array, NULL); + + const ai_tensor *t_in = &input_output; + const ai_tensor *t_out = &bn_output; + const ai_tensor *t_bias = &bn_bias; + const ai_tensor *t_scale = &bn_scale; + const ai_tensor *t_mean = &bn_mean; + const ai_tensor *t_var = &bn_var; + + const ai_size n_elements = ai_shape_get_size(AI_TENSOR_SHAPE(t_in)); + const ai_size n_channel_in = AI_SHAPE_CH(AI_TENSOR_SHAPE(t_in)); + const ai_float *in_data = AI_ARRAY_OBJ_DATA(t_in->data, ai_float); + ai_float *out_data = AI_ARRAY_OBJ_DATA(t_out->data, ai_float); + + AI_ASSERT(n_elements > 0 && n_channel_in > 0) + AI_ASSERT(n_channel_in == AI_SHAPE_CH(AI_TENSOR_SHAPE(t_scale))) + AI_ASSERT(!t_bias || n_channel_in == AI_SHAPE_CH(AI_TENSOR_SHAPE(t_bias))) + + const ai_float *scale = (const ai_float *)t_scale->data->data; + const ai_float *bias = (const ai_float *)t_bias->data->data; + const ai_float *mean = (const ai_float *)t_mean->data->data; + const ai_float *var = (const ai_float *)t_var->data->data; + const float epsilon = 0.00001f; + for (ai_size i = 0; i < n_elements; i += n_channel_in) + { + for (ai_size ch = i; ch < i + n_channel_in; ++ch) + { + // LL_ATON_PRINTF("%f %f %f %f %f \n", in_data[ch], mean[ch-i], sqrtf(var[ch-i]), scale[ch-i], bias[ch-i]); + out_data[ch] = ((in_data[ch] - mean[ch - i]) / (sqrtf(var[ch - i] + epsilon))) * scale[ch - i] + bias[ch - i]; + } + } +} + +//########################################################################################## +/** Instance Norm forward function */ +void ll_sw_forward_instance_normalization(/* int processor, */ void *sw_info_struct) +{ + Instance_normalization_sw_info *sw_info = (Instance_normalization_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(instanceNorm_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(instanceNorm_bias_array, FORMAT, sw_info->bias.mem.start_offset, sw_info->bias.mem.start_offset, + sw_info->bias.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(instanceNorm_scale_array, FORMAT, sw_info->scale.mem.start_offset, + sw_info->scale.mem.start_offset, sw_info->scale.dim.num_elem, ) + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(instanceNorm_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &instanceNorm_output_array, NULL) + AI_TENSOR_OBJ_DECLARE( + instanceNorm_bias, , 0x0, 4, + SHAPE_INIT(sw_info->bias.dim.tensor_h, sw_info->bias.dim.tensor_w, sw_info->bias.dim.tensor_c, + sw_info->bias.dim.tensor_b), + STRIDE_INIT(sw_info->bias.stride.h, sw_info->bias.stride.w, sw_info->bias.stride.c, sw_info->bias.stride.b), 1, + &instanceNorm_bias_array, NULL); + AI_TENSOR_OBJ_DECLARE( + instanceNorm_scale, , 0x0, 4, + SHAPE_INIT(sw_info->scale.dim.tensor_h, sw_info->scale.dim.tensor_w, sw_info->scale.dim.tensor_c, + sw_info->scale.dim.tensor_b), + STRIDE_INIT(sw_info->scale.stride.h, sw_info->scale.stride.w, sw_info->scale.stride.c, sw_info->scale.stride.b), + 1, &instanceNorm_scale_array, NULL); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE( + instanceNorm_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&instanceNorm_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&instanceNorm_scale, &instanceNorm_bias, NULL)), + AI_TENSOR_LIST_OBJ_EMPTY, ) + + // layer initialization + AI_LAYER_OBJ_DECLARE(instanceNorm_layer, 1, INSTANCENORMALIZATION_TYPE, 0x0, NULL, instanceNormalization, + forward_instanceNormalization, &instanceNorm_chain, NULL, NULL, , .eps = 0.00001f, ) + instanceNorm_layer.forward(AI_LAYER_OBJ(&instanceNorm_layer)); +} + +//########################################################################################## +/** Lp Norm forward function */ +void ll_sw_forward_lpnormalization(/* int processor, */ void *sw_info_struct) +{ + Lpnormalization_sw_info *sw_info = (Lpnormalization_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(lpNormm_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(lpNormm_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &lpNormm_output_array, NULL) + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(lpNormm_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&lpNormm_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY, ) + + // layer initialization + AI_LAYER_OBJ_DECLARE(lpNormm_layer, 1, NORM_TYPE, 0x0, NULL, norm, forward_norm, &lpNormm_chain, NULL, NULL, , + .axis = helper_emit_shape_index_axis(sw_info->axis), .exponent = sw_info->p, .scale = false) + lpNormm_layer.forward(AI_LAYER_OBJ(&lpNormm_layer)); +} + +//########################################################################################## +/** Sign forward function */ +void ll_sw_forward_sign(/* int processor, */ void *sw_info_struct) +{ + Sign_sw_info *sw_info = (Sign_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(sign_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(sign_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &sign_output_array, NULL) + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(sign_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&sign_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY, ) + + // layer initialization + AI_LAYER_OBJ_DECLARE(sign_layer, 1, NL_TYPE, 0x0, NULL, nl, forward_sign, &sign_chain, NULL, NULL, , ) + sign_layer.forward(AI_LAYER_OBJ(&sign_layer)); +} + +//########################################################################################## +/** LRN Local Response Normalization forward function */ +void ll_sw_forward_lrn(/* int processor, */ void *sw_info_struct) +{ + Lrn_sw_info *sw_info = (Lrn_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(LRN_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(LRN_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &LRN_output_array, NULL) + + // tensor chains init + AI_TENSOR_CHAIN_OBJ_DECLARE(LRN_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&LRN_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + // TODO//layer initialization + AI_LAYER_OBJ_DECLARE(LRN_layer, 2, LRN_TYPE, 0x0, NULL, lrn, forward_lrn, &LRN_chain, NULL, NULL, , + .local_size = sw_info->size, .k = sw_info->bias, .alpha = sw_info->alpha, .beta = sw_info->beta) + + // LL_ATON_PRINTF("beta %f \n", sw_info->beta); + // LL_ATON_PRINTF("bias %f \n", sw_info->bias); + // LL_ATON_PRINTF("alpha %f \n", sw_info->alpha); + // LL_ATON_PRINTF("local_size %d \n", sw_info->size); + + LRN_layer.forward(AI_LAYER_OBJ(&LRN_layer)); +} + +//########################################################################################## +/** Tile forward function */ +void ll_sw_forward_tile(/* int processor, */ void *sw_info_struct) +{ + Tile_sw_info *sw_info = (Tile_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(tile_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(tile_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &tile_output_array, NULL) + + // tensor chains init + AI_TENSOR_CHAIN_OBJ_DECLARE(tile_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&tile_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + + AI_ARRAY_OBJ_DECLARE_STATIC(repeats, ai_i16, AI_ARRAY_FORMAT_S16, AI_CONST, 5, sw_info->repeats[2], + sw_info->repeats[3], sw_info->repeats[1], sw_info->repeats[0], 1) + + // TODO//layer initialization + AI_LAYER_OBJ_DECLARE(Tile_layer, 2, TILE_TYPE, 0x0, NULL, tile, forward_tile, &tile_chain, NULL, NULL, , + .repeats = AI_ARRAY_OBJ(&repeats)) + + Tile_layer.forward(AI_LAYER_OBJ(&Tile_layer)); +} + +//########################################################################################## +/** concat forward function */ +void ll_sw_forward_concat(/* int processor, */ void *sw_info_struct) +{ + Concat_sw_info *sw_info = (Concat_sw_info *)sw_info_struct; + + AI_ARRAY_OBJ_DECLARE(input_output_array, FORMAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(concat_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(concat_operand_array, FORMAT, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + + ai_array concat_operand_array1; + ai_array *concat_operand_array1_ptr = NULL; + if (sw_info->num_of_inputs >= 3) + { + concat_operand_array1 = (ai_array)AI_ARRAY_OBJ_INIT( + FORMAT, sw_info->operand1.mem.start_offset, sw_info->operand1.mem.start_offset, sw_info->operand1.dim.num_elem); + concat_operand_array1_ptr = &concat_operand_array1; + } + + ai_array concat_operand_array2; + ai_array *concat_operand_array2_ptr = NULL; + if (sw_info->num_of_inputs >= 4) + { + concat_operand_array2 = (ai_array)AI_ARRAY_OBJ_INIT( + FORMAT, sw_info->operand2.mem.start_offset, sw_info->operand2.mem.start_offset, sw_info->operand2.dim.num_elem); + concat_operand_array2_ptr = &concat_operand_array2; + } + + // tensors init + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL) + AI_TENSOR_OBJ_DECLARE(concat_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &concat_output_array, NULL) + + AI_TENSOR_OBJ_DECLARE(concat_operand, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &concat_operand_array, NULL) + + ai_tensor concat_operand1; + ai_tensor *concat_operand1_ptr = NULL; + if (sw_info->num_of_inputs >= 3) + { + concat_operand1 = + (ai_tensor)AI_TENSOR_OBJ_INIT(0x0, 4, + SHAPE_INIT(sw_info->operand1.dim.tensor_h, sw_info->operand1.dim.tensor_w, + sw_info->operand1.dim.tensor_c, sw_info->operand1.dim.tensor_b), + STRIDE_INIT(sw_info->operand1.stride.h, sw_info->operand1.stride.w, + sw_info->operand1.stride.c, sw_info->operand1.stride.b), + 1, concat_operand_array1_ptr, NULL); + concat_operand1_ptr = &concat_operand1; + } + ai_tensor concat_operand2; + ai_tensor *concat_operand2_ptr = NULL; + if (sw_info->num_of_inputs >= 4) + { + concat_operand2 = + (ai_tensor)AI_TENSOR_OBJ_INIT(0x0, 4, + SHAPE_INIT(sw_info->operand2.dim.tensor_h, sw_info->operand2.dim.tensor_w, + sw_info->operand2.dim.tensor_c, sw_info->operand2.dim.tensor_b), + STRIDE_INIT(sw_info->operand2.stride.h, sw_info->operand2.stride.w, + sw_info->operand2.stride.c, sw_info->operand2.stride.b), + 1, concat_operand_array2_ptr, NULL); + concat_operand2_ptr = &concat_operand2; + } + + // tensor chains init + AI_TENSOR_CHAIN_OBJ_DECLARE( + concat_chain, , 4, + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 4, + TENSORS(&input_output, &concat_operand, concat_operand1_ptr, concat_operand2_ptr)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&concat_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + AI_LAYER_OBJ_DECLARE(concat_layer, 1, CONCAT_TYPE, 0x0, NULL, concat, forward_concat, &concat_chain, NULL, NULL, , + .axis = sw_info->concat_axis) + concat_layer.forward(AI_LAYER_OBJ(&concat_layer)); +} + +#endif // LL_ATON_SW_FALLBACK == 1 diff --git a/lib/stai/libstai/ll_aton/ll_sw_integer.c b/lib/stai/libstai/ll_aton/ll_sw_integer.c new file mode 100644 index 000000000..97c32807f --- /dev/null +++ b/lib/stai/libstai/ll_aton/ll_sw_integer.c @@ -0,0 +1,1240 @@ +/** + ****************************************************************************** + * @file ll_sw_integer.c + * @author SRA Artificial Intelligence & Embedded Architectures + * @brief Low Level Software library for Scale-Offset Integer Format inference interfacing with EmbedNets(c) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ll_aton_config.h" + +#if LL_ATON_SW_FALLBACK == 1 + +#include +#include + +#include "ll_sw.h" +#include "ll_sw_integer.h" + +#include "ai_datatypes_internal.h" +#include "ai_math_helpers.h" +#include "core_convert.h" +#include "core_private.h" +#include "layers.h" +#include "ll_aton_util.h" + +#define FORMAT AI_ARRAY_FORMAT_FLOAT + +#define SHAPE_INIT(a_, b_, c_, d_) AI_SHAPE_INIT(4, (d_), (c_), (b_), (a_)) + +#define SHAPE_2D_INIT(h_, w_) AI_SHAPE_2D_INIT((w_), (h_)) + +#define STRIDE_INIT(a_, b_, c_, d_) AI_STRIDE_INIT(4, (d_), (c_), (b_), (a_)) + +#define TENSORS(...) __VA_ARGS__ + +static int helper_emit_shape_index_axis(int onnx_axis) +{ + switch (onnx_axis) + { + case 0: + return AI_SHAPE_IN_CHANNEL; + case 1: + return AI_SHAPE_CHANNEL; + case 2: + return AI_SHAPE_HEIGHT; // note the switch required with case 3 + case 3: + return AI_SHAPE_WIDTH; // note the switch required with case 2 + default: +#ifdef LL_SW_ENABLE_ASSERTS + LL_ATON_ASSERT(0 && "axis index not supported"); +#endif + return -1; + } +} + +/** QLinearMatMul forward function */ +void ll_sw_forward_qlinearmatmul(/* int processor, */ void *sw_info_struct) +{ + Qlinearmatmul_sw_info *sw_info = (Qlinearmatmul_sw_info *)sw_info_struct; + + /* + 1. reshape of the weights from weights tensor -> weights_perm tensor + 2. map the matmul operation on the library dense_forward function. + this requires 1d input (on ch) and 2d weights (ch e chin). in particular: + - input: 1,1,NIN,1 + - weights already permuted: 1,1,NOUT,NIN + - bias 1,1,NOUT,1 + - scratch 1,1,NIN*2+NOUT*10 + - output 1,1,NOUT,1 + */ + + int32_t format; + // array init + format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + format = sw_info->weights.format.is_signed ? (AI_ARRAY_FORMAT_S8) : (AI_ARRAY_FORMAT_U8); + AI_ARRAY_OBJ_DECLARE(dense_weights_array, format, sw_info->weights.mem.start_offset, + sw_info->weights.mem.start_offset, sw_info->weights.dim.num_elem, ) + format = sw_info->scratch.format.is_signed ? (AI_ARRAY_FORMAT_S8) : (AI_ARRAY_FORMAT_U8); + AI_ARRAY_OBJ_DECLARE(dense_scratch0_array, format, sw_info->scratch.mem.start_offset, + sw_info->scratch.mem.start_offset, sw_info->scratch.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(dense_bias_array, AI_ARRAY_FORMAT_S32, sw_info->bias.mem.start_offset, + sw_info->bias.mem.start_offset, sw_info->bias.dim.num_elem, ) + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(dense_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format; + uint16_t scale_format; + + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->izp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list input_intq = {.flags = (scale_format | offset_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->wzp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list weights_intq = {.flags = (scale_format | offset_format), + .size = sw_info->ws.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->ws.mem.start_offset), + .zeropoint = ((void *)sw_info->wzp.mem.start_offset), + }}}; + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->ozp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list output_intq = {.flags = (scale_format | offset_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(dense_weights, , 0x0, 4, + SHAPE_INIT(sw_info->weights.dim.tensor_h, sw_info->weights.dim.tensor_w, + sw_info->weights.dim.tensor_c, sw_info->weights.dim.tensor_b), + // ,0x0, 4, SHAPE_INIT(sw_info->weights.dim.tensor_b, sw_info->weights.dim.tensor_c, + // sw_info->weights.dim.tensor_h, sw_info->weights.dim.tensor_w), + STRIDE_INIT(sw_info->weights.stride.h, sw_info->weights.stride.w, sw_info->weights.stride.c, + sw_info->weights.stride.b), + 1, &dense_weights_array, &weights_intq); + AI_TENSOR_OBJ_DECLARE(dense_scratch0, , 0x0, 4, + SHAPE_INIT(sw_info->scratch.dim.tensor_h, sw_info->scratch.dim.tensor_w, + sw_info->scratch.dim.tensor_c, sw_info->scratch.dim.tensor_b), + STRIDE_INIT(sw_info->scratch.stride.h, sw_info->scratch.stride.w, sw_info->scratch.stride.c, + sw_info->scratch.stride.b), + 1, &dense_scratch0_array, NULL); + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + AI_TENSOR_OBJ_DECLARE( + dense_bias, , 0x0, 4, + SHAPE_INIT(sw_info->bias.dim.tensor_h, sw_info->bias.dim.tensor_c, sw_info->bias.dim.tensor_w, + sw_info->bias.dim.tensor_b), + STRIDE_INIT(sw_info->bias.stride.h, sw_info->bias.stride.w, sw_info->bias.stride.c, sw_info->bias.stride.b), 1, + &dense_bias_array, NULL); + AI_TENSOR_OBJ_DECLARE(dense_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &dense_output_array, &output_intq); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(dense_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&dense_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&dense_weights, &dense_bias, NULL)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&dense_scratch0))) + + memset(sw_info->bias.mem.start_offset, 0x0, sw_info->bias.dim.num_elem * 4); + + // layer initialization + AI_LAYER_OBJ_DECLARE(dense_layer, 1, DENSE_TYPE, 0x0, NULL, dense, forward_dense_integer /*_fixed*/, &dense_chain, + NULL, NULL, , ) + + dense_layer.forward(AI_LAYER_OBJ(&dense_layer)); +} + +//########################################################################################## +/** QLinearMatMul forward function */ +void ll_sw_forward_gemm_integer(/* int processor, */ void *sw_info_struct) +{ + Gemm_integer_sw_info *sw_info = (Gemm_integer_sw_info *)sw_info_struct; + + /* + 1. reshape of the weights from weights tensor -> weights_perm tensor + 2. map the matmul operation on the library dense_forward function. + this requires 1d input (on ch) and 2d weights (ch e chin). in particular: + - input: 1,1,NIN,1 + - weights already permuted: 1,1,NOUT,NIN + - bias 1,1,NOUT,1 + - scratch 1,1,NIN*2+NOUT*10 + - output 1,1,NOUT,1 + */ + + int32_t format; + // array init + format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + format = sw_info->weights.format.is_signed ? (AI_ARRAY_FORMAT_S8) : (AI_ARRAY_FORMAT_U8); + AI_ARRAY_OBJ_DECLARE(dense_weights_array, format, sw_info->weights.mem.start_offset, + sw_info->weights.mem.start_offset, sw_info->weights.dim.num_elem, ) + format = sw_info->scratch.format.is_signed ? (AI_ARRAY_FORMAT_S8) : (AI_ARRAY_FORMAT_U8); + AI_ARRAY_OBJ_DECLARE(dense_scratch0_array, format, sw_info->scratch.mem.start_offset, + sw_info->scratch.mem.start_offset, sw_info->scratch.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(dense_bias_array, AI_ARRAY_FORMAT_S32, sw_info->bias.mem.start_offset, + sw_info->bias.mem.start_offset, sw_info->bias.dim.num_elem, ) + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(dense_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format; + uint16_t scale_format; + + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->izp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list input_intq = {.flags = (scale_format | offset_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->wzp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list weights_intq = {.flags = (scale_format | offset_format), + .size = sw_info->ws.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->ws.mem.start_offset), + .zeropoint = ((void *)sw_info->wzp.mem.start_offset), + }}}; + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->ozp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list output_intq = {.flags = (scale_format | offset_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(dense_weights, , 0x0, 4, + SHAPE_INIT(sw_info->weights.dim.tensor_h, sw_info->weights.dim.tensor_w, + sw_info->weights.dim.tensor_c, sw_info->weights.dim.tensor_b), + STRIDE_INIT(sw_info->weights.stride.h, sw_info->weights.stride.w, sw_info->weights.stride.c, + sw_info->weights.stride.b), + 1, &dense_weights_array, &weights_intq); + AI_TENSOR_OBJ_DECLARE(dense_scratch0, , 0x0, 4, + SHAPE_INIT(sw_info->scratch.dim.tensor_h, sw_info->scratch.dim.tensor_w, + sw_info->scratch.dim.tensor_c, sw_info->scratch.dim.tensor_b), + STRIDE_INIT(sw_info->scratch.stride.h, sw_info->scratch.stride.w, sw_info->scratch.stride.c, + sw_info->scratch.stride.b), + 1, &dense_scratch0_array, NULL); + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + AI_TENSOR_OBJ_DECLARE( + dense_bias, , 0x0, 4, + SHAPE_INIT(sw_info->bias.dim.tensor_h, sw_info->bias.dim.tensor_c, sw_info->bias.dim.tensor_w, + sw_info->bias.dim.tensor_b), + STRIDE_INIT(sw_info->bias.stride.h, sw_info->bias.stride.w, sw_info->bias.stride.c, sw_info->bias.stride.b), 1, + &dense_bias_array, NULL); + AI_TENSOR_OBJ_DECLARE(dense_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &dense_output_array, &output_intq); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(dense_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&dense_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&dense_weights, &dense_bias, NULL)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&dense_scratch0))) + + // layer initialization + AI_LAYER_OBJ_DECLARE(dense_layer, 1, DENSE_TYPE, 0x0, NULL, dense, forward_dense_integer /*_fixed*/, &dense_chain, + NULL, NULL, , ) + + dense_layer.forward(AI_LAYER_OBJ(&dense_layer)); +} + +//########################################################################################## +/** QuantizeLinear forward function */ +void ll_sw_forward_quantizelinear(/* int processor, */ void *sw_info_struct) +{ + Quantizelinear_sw_info *sw_info = (Quantizelinear_sw_info *)sw_info_struct; + + // array init + AI_ARRAY_OBJ_DECLARE(input_output_array, AI_ARRAY_FORMAT_FLOAT, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + int32_t format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(quantize_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->os.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, NULL); + AI_TENSOR_OBJ_DECLARE(quantize_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &quantize_output_array, &output_intq); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(quantize_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&quantize_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + AI_LAYER_OBJ_DECLARE(quantize_layer, 1, NL_TYPE, 0x0, NULL, nl, node_convert /*_fixed*/, &quantize_chain, NULL, + NULL, ) + quantize_layer.forward(AI_LAYER_OBJ(&quantize_layer)); +} + +//########################################################################################## +/** Dequantizelinear forward function */ +void ll_sw_forward_dequantizelinear(/* int processor, */ void *sw_info_struct) +{ + Dequantizelinear_sw_info *sw_info = (Dequantizelinear_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(dequantize_output_array, FORMAT, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->is.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(dequantize_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &dequantize_output_array, NULL); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(dequantize_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&dequantize_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + AI_LAYER_OBJ_DECLARE(dequantize_layer, 1, NL_TYPE, 0x0, NULL, nl, node_convert /*_fixed*/, &dequantize_chain, NULL, + NULL, ) + dequantize_layer.forward(AI_LAYER_OBJ(&dequantize_layer)); +} + +//########################################################################################## +/** QuantizeLinear forward function */ +void ll_sw_forward_requantizelinear(/* int processor, */ void *sw_info_struct) +{ + Requantizelinear_sw_info *sw_info = (Requantizelinear_sw_info *)sw_info_struct; + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(requantize_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->is.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->os.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(requantize_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &requantize_output_array, &output_intq); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(requantize_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&requantize_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + AI_LAYER_OBJ_DECLARE(requantize_layer, 1, NL_TYPE, 0x0, NULL, nl, node_convert_integer /*_fixed*/, &requantize_chain, + NULL, NULL, ) + requantize_layer.forward(AI_LAYER_OBJ(&requantize_layer)); +} + +//########################################################################################## +/** Conv integer forward function */ +void ll_sw_forward_conv_integer(/* int processor, */ void *sw_info_struct) +{ + Conv_integer_sw_info *sw_info = (Conv_integer_sw_info *)sw_info_struct; + + int32_t format; + // array init + format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + format = sw_info->weights.format.is_signed ? (AI_ARRAY_FORMAT_S8) : (AI_ARRAY_FORMAT_U8); + AI_ARRAY_OBJ_DECLARE(conv_weights_array, format, sw_info->weights.mem.start_offset, sw_info->weights.mem.start_offset, + sw_info->weights.dim.num_elem, ) + format = sw_info->scratch.format.is_signed ? (AI_ARRAY_FORMAT_S8) : (AI_ARRAY_FORMAT_U8); + AI_ARRAY_OBJ_DECLARE(conv_scratch0_array, format, sw_info->scratch.mem.start_offset, + sw_info->scratch.mem.start_offset, sw_info->scratch.dim.num_elem, ) + AI_ARRAY_OBJ_DECLARE(conv_bias_array, AI_ARRAY_FORMAT_S32, sw_info->bias.mem.start_offset, + sw_info->bias.mem.start_offset, sw_info->bias.dim.num_elem, ) + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(conv_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format; + uint16_t scale_format; + + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->izp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list input_intq = {.flags = (scale_format | offset_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->wzp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list weights_intq = {.flags = (scale_format | offset_format), + .size = sw_info->ws.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->ws.mem.start_offset), + .zeropoint = ((void *)sw_info->wzp.mem.start_offset), + }}}; + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + offset_format = + sw_info->ozp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + ai_intq_info_list output_intq = {.flags = (scale_format | offset_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(conv_weights, , 0x0, 4, + SHAPE_INIT(sw_info->weights.dim.tensor_b, sw_info->weights.dim.tensor_h, + sw_info->weights.dim.tensor_w, sw_info->weights.dim.tensor_c), + STRIDE_INIT(sw_info->weights.stride.h, sw_info->weights.stride.w, sw_info->weights.stride.b, + sw_info->weights.stride.b), + 1, &conv_weights_array, &weights_intq); + AI_TENSOR_OBJ_DECLARE(conv_scratch0, , 0x0, 4, + SHAPE_INIT(sw_info->scratch.dim.tensor_h, sw_info->scratch.dim.tensor_w, + sw_info->scratch.dim.tensor_c, sw_info->scratch.dim.tensor_b), + STRIDE_INIT(sw_info->scratch.stride.h, sw_info->scratch.stride.w, sw_info->scratch.stride.c, + sw_info->scratch.stride.b), + 1, &conv_scratch0_array, NULL); + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + AI_TENSOR_OBJ_DECLARE( + conv_bias, , 0x0, 4, + SHAPE_INIT(sw_info->bias.dim.tensor_h, sw_info->bias.dim.tensor_w, sw_info->bias.dim.tensor_c, + sw_info->bias.dim.tensor_b), + STRIDE_INIT(sw_info->bias.stride.h, sw_info->bias.stride.w, sw_info->bias.stride.c, sw_info->bias.stride.b), 1, + &conv_bias_array, NULL); + AI_TENSOR_OBJ_DECLARE(conv_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &conv_output_array, &output_intq); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(conv_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&conv_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 3, TENSORS(&conv_weights, &conv_bias, NULL)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&conv_scratch0))) + + switch (sw_info->fwd_func) + { + case LL_SW_SSSA_PW_CONV: + { +#ifdef LL_SW_DUMP_DEBUG + LL_ATON_PRINTF("POINTWISE"); +#endif + AI_LAYER_OBJ_DECLARE( + conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_pw_sssa8_ch /*_fixed*/, &conv_chain, NULL, NULL, , + .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + break; + case LL_SW_SSSA_RGB_CONV: + { +#ifdef LL_SW_DUMP_DEBUG + LL_ATON_PRINTF("RGB"); +#endif + AI_LAYER_OBJ_DECLARE( + conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_conv2d_rgb_sssa8_ch /*_fixed*/, &conv_chain, NULL, NULL, + , .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + break; + case LL_SW_SSSA_DW_CONV: + { +#ifdef LL_SW_DUMP_DEBUG + LL_ATON_PRINTF("GROUP"); +#endif + AI_LAYER_OBJ_DECLARE( + conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_dw_dm_sssa8_ch /*_fixed*/, &conv_chain, NULL, NULL, , + .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + break; + case LL_SW_SSSA_DILATED_CONV: + { +#ifdef LL_SW_DUMP_DEBUG + LL_ATON_PRINTF("DILATION"); +#endif + AI_LAYER_OBJ_DECLARE( + conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_conv2d_dilated_sssa8_ch /*_fixed*/, &conv_chain, NULL, + NULL, , .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + break; + case LL_SW_SSSA_GENERIC_CONV: + { +#ifdef LL_SW_DUMP_DEBUG + LL_ATON_PRINTF("GENERAL CH"); +#endif + AI_LAYER_OBJ_DECLARE( + conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_conv2d_sssa8_ch /*_fixed*/, &conv_chain, NULL, NULL, , + .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + break; + case LL_SW_GENERIC_CONV: + { +#ifdef LL_SW_DUMP_DEBUG + LL_ATON_PRINTF("GENERAL UNSIGEND per CHANNEL"); +#endif + AI_LAYER_OBJ_DECLARE( + conv_layer, 1, CONV2D_TYPE, 0x0, NULL, conv2d, forward_conv2d_integer /*_fixed*/, &conv_chain, NULL, NULL, , + .groups = sw_info->ngroup, .nl_params = NULL, .nl_func = NULL, + .filter_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), // controlla perche' non mi convince + .filter_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .dilation = SHAPE_2D_INIT(sw_info->dilations[0], sw_info->dilations[1]), ) + conv_layer.forward(AI_LAYER_OBJ(&conv_layer)); + } + break; + default: + break; + } +} + +//########################################################################################## +/** Element Wise forward function */ +void ll_sw_forward_eltwise_integer(/* int processor, */ void *sw_info_struct) +{ + Eltwise_integer_sw_info *sw_info = (Eltwise_integer_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + format = sw_info->operand.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(eltwise_operand_array, format, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(eltwise_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->is.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->os.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + offset_format = + sw_info->operand_s.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list operand_intq = {.flags = (offset_format | scale_format), + .size = sw_info->operand_s.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->operand_s.mem.start_offset), + .zeropoint = ((void *)sw_info->operand_zp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(eltwise_operand, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &eltwise_operand_array, &operand_intq); + + AI_TENSOR_OBJ_DECLARE(eltwise_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &eltwise_output_array, &output_intq); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE( + eltwise_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 2, TENSORS(&input_output), TENSORS(&eltwise_operand)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&eltwise_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + switch (sw_info->general.type) + { + case LL_SW_ARITHSUM: + { + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_INTEGER_TYPE, 0x0, NULL, eltwise_integer, forward_eltwise_integer, + &eltwise_chain, NULL, NULL, , .operation = ai_sum, + .buffer_operation = + ((sw_info->general.input.format.is_signed) ? ai_sum_buffer_INT8 : ai_sum_buffer_UINT8)) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + } + break; + case LL_SW_ARITHMUL: + { + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_INTEGER_TYPE, 0x0, NULL, eltwise_integer, forward_eltwise_integer, + &eltwise_chain, NULL, NULL, , .operation = ai_mul, + .buffer_operation = + ((sw_info->general.input.format.is_signed) ? ai_mul_buffer_INT8 : ai_mul_buffer_UINT8)) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + break; + } + case LL_SW_ARITHDIV: + { + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_INTEGER_TYPE, 0x0, NULL, eltwise_integer, forward_eltwise_integer, + &eltwise_chain, NULL, NULL, , .operation = ai_div, + .buffer_operation = + ((sw_info->general.input.format.is_signed) ? ai_div_buffer_INT8 : ai_div_buffer_UINT8)) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + } + break; + case LL_SW_ARITHSUB: + { + AI_LAYER_OBJ_DECLARE(eltwise_layer, 2, ELTWISE_INTEGER_TYPE, 0x0, NULL, eltwise_integer, forward_eltwise_integer, + &eltwise_chain, NULL, NULL, , .operation = ai_sub, + .buffer_operation = + ((sw_info->general.input.format.is_signed) ? ai_sub_buffer_INT8 : ai_sub_buffer_UINT8)) + eltwise_layer.forward(AI_LAYER_OBJ(&eltwise_layer)); + } + break; + default: + break; + } +} + +//########################################################################################## +/** Pool forward function */ +void ll_sw_forward_pool_integer(/* int processor, */ void *sw_info_struct) +{ + Pool_integer_sw_info *sw_info = (Pool_integer_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(pool_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->is.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->os.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(pool_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &pool_output_array, &output_intq); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(pool_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&pool_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + switch (sw_info->general.type) + { + case LL_SW_AVGPOOL: + { + AI_LAYER_OBJ_DECLARE(pool_layer, 1, POOL_TYPE, 0x0, NULL, pool, forward_ap_integer, &pool_chain, NULL, NULL, , + .pool_size = SHAPE_2D_INIT(sw_info->k_shape[0], sw_info->k_shape[1]), + .pool_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), + .pool_pad = SHAPE_INIT(sw_info->pads[0], sw_info->pads[1], sw_info->pads[2], sw_info->pads[3]), + .count_include_pad = sw_info->count_include_pad, ) + pool_layer.forward(AI_LAYER_OBJ(&pool_layer)); + } + break; + case LL_SW_MAXPOOL: + { + AI_LAYER_OBJ_DECLARE(pool_layer, 1, POOL_TYPE, 0x0, NULL, pool, forward_mp_integer, &pool_chain, NULL, NULL, , + .pool_size = SHAPE_2D_INIT(sw_info->k_shape[0], sw_info->k_shape[1]), + .pool_stride = SHAPE_2D_INIT(sw_info->strides[0], sw_info->strides[1]), + .pool_pad = SHAPE_INIT(sw_info->pads[3], sw_info->pads[2], sw_info->pads[1], sw_info->pads[0]), + .count_include_pad = 0, ) + pool_layer.forward(AI_LAYER_OBJ(&pool_layer)); + } + break; + default: + break; + } +} + +//########################################################################################## +/** Pool forward function */ +void ll_sw_forward_global_pool_integer(/* int processor, */ void *sw_info_struct) +{ + Global_pool_integer_sw_info *sw_info = (Global_pool_integer_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(pool_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->is.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->os.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(pool_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &pool_output_array, &output_intq); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(pool_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&pool_output)), AI_TENSOR_LIST_OBJ_EMPTY, + AI_TENSOR_LIST_OBJ_EMPTY) + + // layer initialization + switch (sw_info->general.type) + { + case LL_SW_AVGPOOL: + { + AI_LAYER_OBJ_DECLARE(pool_layer, 1, POOL_TYPE, 0x0, NULL, pool, forward_ap_integer, &pool_chain, NULL, NULL, , + .pool_size = + SHAPE_2D_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w), + .pool_stride = SHAPE_2D_INIT(1, 1), .pool_pad = SHAPE_INIT(0, 0, 0, 0), ) + pool_layer.forward(AI_LAYER_OBJ(&pool_layer)); + } + break; + case LL_SW_MAXPOOL: + { + AI_LAYER_OBJ_DECLARE(pool_layer, 1, POOL_TYPE, 0x0, NULL, pool, forward_mp_integer, &pool_chain, NULL, NULL, , + .pool_size = + SHAPE_2D_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w), + .pool_stride = SHAPE_2D_INIT(1, 1), .pool_pad = SHAPE_INIT(0, 0, 0, 0), ) + pool_layer.forward(AI_LAYER_OBJ(&pool_layer)); + } + break; + default: + break; + } +} + +//########################################################################################## +/** Softmax forward function */ +void ll_sw_forward_softmax_integer(/* int processor, */ void *sw_info_struct) +{ + Softmax_integer_sw_info *sw_info = (Softmax_integer_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(softmax_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + AI_ARRAY_OBJ_DECLARE(sm_scratch0_array, AI_ARRAY_FORMAT_S32, sw_info->scratch.mem.start_offset, + sw_info->scratch.mem.start_offset, sw_info->scratch.dim.num_elem, ) + + uint16_t offset_format = + sw_info->izp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->ozp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(softmax_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &softmax_output_array, &output_intq); + + AI_TENSOR_OBJ_DECLARE(sm_scratch0, , 0x0, 4, + SHAPE_INIT(sw_info->scratch.dim.tensor_h, sw_info->scratch.dim.tensor_w, + sw_info->scratch.dim.tensor_c, sw_info->scratch.dim.tensor_b), + STRIDE_INIT(sw_info->scratch.stride.h, sw_info->scratch.stride.w, sw_info->scratch.stride.c, + sw_info->scratch.stride.b), + 1, &sm_scratch0_array, NULL); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(softmax_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&softmax_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&sm_scratch0))) + + AI_ARRAY_OBJ_DECLARE_STATIC(sm_integer_params, ai_i32, AI_ARRAY_FORMAT_S32, AI_CONST, 3, + sw_info->quantized_multiplier, sw_info->left_shift, sw_info->diff_min) + + AI_LAYER_OBJ_DECLARE(sm_integer_layer, 1, SM_TYPE, 0x0, NULL, sm, forward_sm_integer, &softmax_chain, NULL, NULL, , + .nl_params = &sm_integer_params, .axis = helper_emit_shape_index_axis(sw_info->axis)) + sm_integer_layer.forward(AI_LAYER_OBJ(&sm_integer_layer)); +} + +//########################################################################################## +/** Activ forward function */ +void ll_sw_forward_activ_integer(/* int processor, */ void *sw_info_struct) +{ + Activ_integer_sw_info *sw_info = (Activ_integer_sw_info *)sw_info_struct; + + // array init + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(activ_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->izp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->ozp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(activ_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &activ_output_array, &output_intq); + + // layer initialization + switch (sw_info->general.type) + { + case LL_SW_RELU: + { + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(activ_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + AI_ARRAY_OBJ_DECLARE_STATIC(relu_params, ai_u8, AI_ARRAY_FORMAT_U8, AI_CONST, 1, sw_info->ozp.mem.start_offset[0]) + AI_LAYER_OBJ_DECLARE(activ_layer, 1, NL_TYPE, 0x0, NULL, nl, forward_relu_integer, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&relu_params), ) + activ_layer.forward(AI_LAYER_OBJ(&activ_layer)); + } + break; + case LL_SW_PRELU: + { + if (sw_info->operand_s.mem.start_offset != NULL) + { + AI_ARRAY_OBJ_DECLARE(slope_tensor_array, format, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + offset_format = + sw_info->operand.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list slope_intq = {.flags = (offset_format | scale_format), + .size = sw_info->operand_s.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->operand_s.mem.start_offset), + .zeropoint = ((void *)sw_info->operand_zp.mem.start_offset), + }}}; + + AI_TENSOR_OBJ_DECLARE(slope_tensor, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &slope_tensor_array, &slope_intq); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(activ_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&slope_tensor)), + AI_TENSOR_LIST_OBJ_EMPTY) + AI_ARRAY_OBJ_DECLARE_STATIC(relu_params, ai_u8, AI_ARRAY_FORMAT_U8, AI_CONST, 1, sw_info->ozp.mem.start_offset[0]) + AI_LAYER_OBJ_DECLARE(activ_layer, 1, NL_TYPE, 0x0, NULL, nl, forward_prelu_integer, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&relu_params), ) + activ_layer.forward(AI_LAYER_OBJ(&activ_layer)); + } + else + { + AI_ARRAY_OBJ_DECLARE(slope_tensor_array, FORMAT, sw_info->operand.mem.start_offset, + sw_info->operand.mem.start_offset, sw_info->operand.dim.num_elem, ) + AI_TENSOR_OBJ_DECLARE(slope_tensor, , 0x0, 4, + SHAPE_INIT(sw_info->operand.dim.tensor_h, sw_info->operand.dim.tensor_w, + sw_info->operand.dim.tensor_c, sw_info->operand.dim.tensor_b), + STRIDE_INIT(sw_info->operand.stride.h, sw_info->operand.stride.w, sw_info->operand.stride.c, + sw_info->operand.stride.b), + 1, &slope_tensor_array, NULL); + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(activ_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&slope_tensor)), + AI_TENSOR_LIST_OBJ_EMPTY) + AI_ARRAY_OBJ_DECLARE_STATIC(relu_params, ai_u8, AI_ARRAY_FORMAT_U8, AI_CONST, 1, sw_info->ozp.mem.start_offset[0]) + AI_LAYER_OBJ_DECLARE(activ_layer, 1, NL_TYPE, 0x0, NULL, nl, forward_prelu_integer, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&relu_params), ) + activ_layer.forward(AI_LAYER_OBJ(&activ_layer)); + } + } + break; + case LL_SW_CLIP: + { + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(activ_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&activ_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + AI_ARRAY_OBJ_DECLARE_STATIC(clip_layer_params, ai_float, AI_ARRAY_FORMAT_FLOAT, AI_CONST, 2, sw_info->min, + sw_info->max) + AI_LAYER_OBJ_DECLARE(nonlinearity_layer, 2, NL_TYPE, 0x0, NULL, nl, forward_clip, &activ_chain, NULL, NULL, , + .nl_params = AI_ARRAY_OBJ(&clip_layer_params)) + nonlinearity_layer.forward(AI_LAYER_OBJ(&nonlinearity_layer)); + } + break; + default: + break; + } +} + +//########################################################################################## +/** Resize forward function */ +void ll_sw_forward_resize_integer(/* int processor, */ void *sw_info_struct) +{ + Resize_integer_sw_info *sw_info = (Resize_integer_sw_info *)sw_info_struct; + // array init + + int32_t format = sw_info->general.input.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + + AI_ARRAY_OBJ_DECLARE(input_output_array, format, sw_info->general.input.mem.start_offset, + sw_info->general.input.mem.start_offset, sw_info->general.input.dim.num_elem, ) + + format = sw_info->general.output.format.is_signed ? (AI_ARRAY_FORMAT_S8 | AI_FMT_FLAG_IS_IO) + : (AI_ARRAY_FORMAT_U8 | AI_FMT_FLAG_IS_IO); + AI_ARRAY_OBJ_DECLARE(resize_output_array, format, sw_info->general.output.mem.start_offset, + sw_info->general.output.mem.start_offset, sw_info->general.output.dim.num_elem, ) + + uint16_t offset_format = + sw_info->izp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + uint16_t scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list input_intq = {.flags = (offset_format | scale_format), + .size = sw_info->is.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->is.mem.start_offset), + .zeropoint = ((void *)sw_info->izp.mem.start_offset), + }}}; + + offset_format = + sw_info->ozp.format.is_signed ? (AI_BUFFER_META_FLAG_ZEROPOINT_S8) : (AI_BUFFER_META_FLAG_ZEROPOINT_U8); + scale_format = AI_BUFFER_META_FLAG_SCALE_FLOAT; + ai_intq_info_list output_intq = {.flags = (offset_format | scale_format), + .size = sw_info->os.dim.num_elem, + .info = (const ai_intq_info[1]){{ + .scale = ((float *)sw_info->os.mem.start_offset), + .zeropoint = ((void *)sw_info->ozp.mem.start_offset), + }}}; + + AI_ARRAY_OBJ_DECLARE(resize_scales_array, FORMAT, sw_info->scales.mem.start_offset, sw_info->scales.mem.start_offset, + sw_info->scales.dim.num_elem, ) + + ai_array *resize_roi_array_ptr = NULL; + ai_array resize_roi_array; + if (sw_info->roi.mem.start_offset != NULL) + { + resize_roi_array = (ai_array)AI_ARRAY_OBJ_INIT(FORMAT, sw_info->roi.mem.start_offset, sw_info->roi.mem.start_offset, + sw_info->roi.dim.num_elem); + resize_roi_array_ptr = &resize_roi_array; + } + + AI_TENSOR_OBJ_DECLARE(input_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.input.dim.tensor_h, sw_info->general.input.dim.tensor_w, + sw_info->general.input.dim.tensor_c, sw_info->general.input.dim.tensor_b), + STRIDE_INIT(sw_info->general.input.stride.h, sw_info->general.input.stride.w, + sw_info->general.input.stride.c, sw_info->general.input.stride.b), + 1, &input_output_array, &input_intq); + + AI_TENSOR_OBJ_DECLARE(resize_output, , 0x0, 4, + SHAPE_INIT(sw_info->general.output.dim.tensor_h, sw_info->general.output.dim.tensor_w, + sw_info->general.output.dim.tensor_c, sw_info->general.output.dim.tensor_b), + STRIDE_INIT(sw_info->general.output.stride.h, sw_info->general.output.stride.w, + sw_info->general.output.stride.c, sw_info->general.output.stride.b), + 1, &resize_output_array, &output_intq); + + AI_TENSOR_OBJ_DECLARE(resize_scales, , 0x0, 4, + SHAPE_INIT(sw_info->scales.dim.tensor_h, sw_info->scales.dim.tensor_w, + sw_info->scales.dim.tensor_c, sw_info->scales.dim.tensor_b), + STRIDE_INIT(sw_info->scales.stride.h, sw_info->scales.stride.w, sw_info->scales.stride.c, + sw_info->scales.stride.b), + 1, &resize_scales_array, NULL); + + // tensor chain initialization + AI_TENSOR_CHAIN_OBJ_DECLARE(resize_chain, , 4, AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&input_output)), + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, 1, TENSORS(&resize_output)), + AI_TENSOR_LIST_OBJ_EMPTY, AI_TENSOR_LIST_OBJ_EMPTY) + + // extrapolating the scales values needed + const ai_tensor *p = &resize_scales; + const ai_float *s = AI_ARRAY_OBJ_DATA(p->data, ai_float); + AI_ARRAY_OBJ_DECLARE_STATIC(rs, ai_float, AI_ARRAY_FORMAT_FLOAT, AI_CONST, 2, s[2], s[3]) + + // layer initialization + if ((ai_resize_mode)sw_info->mode == AI_RESIZE_NEAREST) + { + AI_LAYER_OBJ_DECLARE(resize_layer, 1, RESIZE_TYPE, 0x0, NULL, resize, forward_resize_nearest_is8os8, &resize_chain, + NULL, NULL, , .cubic_coeff_a = sw_info->cubic_coeff_a, + .exclude_outside = sw_info->exclude_outside, .extrapol_val = sw_info->extrapol_val, + .mode = (ai_resize_mode)sw_info->mode, .nearest_mode = (ai_nearest_mode)sw_info->nearest_mode, + .coord_transf_mode = (ai_coord_transf_mode)sw_info->coord_transf_mode, + .scales = AI_ARRAY_OBJ(&rs), .roi = resize_roi_array_ptr) + resize_layer.forward(AI_LAYER_OBJ(&resize_layer)); + } + else if ((ai_resize_mode)sw_info->mode == AI_RESIZE_LINEAR) + { + AI_LAYER_OBJ_DECLARE(resize_layer, 1, RESIZE_TYPE, 0x0, NULL, resize, forward_resize_bilinear_is8os8, &resize_chain, + NULL, NULL, , .cubic_coeff_a = sw_info->cubic_coeff_a, + .exclude_outside = sw_info->exclude_outside, .extrapol_val = sw_info->extrapol_val, + .mode = (ai_resize_mode)sw_info->mode, .nearest_mode = (ai_nearest_mode)sw_info->nearest_mode, + .coord_transf_mode = (ai_coord_transf_mode)sw_info->coord_transf_mode, + .scales = AI_ARRAY_OBJ(&rs), .roi = resize_roi_array_ptr) + resize_layer.forward(AI_LAYER_OBJ(&resize_layer)); + } + else if ((ai_resize_mode)sw_info->mode == AI_RESIZE_ZEROS) + { + AI_LAYER_OBJ_DECLARE(resize_layer, 1, UPSAMPLE_TYPE, 0x0, NULL, upsample, forward_upsample_zeros, &resize_chain, + NULL, NULL, , .mode = AI_UPSAMPLE_ZEROS, .center = false, .scales = AI_ARRAY_OBJ(&rs), + .nearest_mode = AI_ROUND_PREFER_FLOOR) + resize_layer.forward(AI_LAYER_OBJ(&resize_layer)); + } +} + +#endif // LL_ATON_SW_FALLBACK == 1 diff --git a/lib/stai/libstai/ll_aton/mcu_cache.c b/lib/stai/libstai/ll_aton/mcu_cache.c new file mode 100755 index 000000000..cc0bf8579 --- /dev/null +++ b/lib/stai/libstai/ll_aton/mcu_cache.c @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file mcu_cache.c + * @brief Implementation of MCU cache-handling functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "mcu_cache.h" + +int mcu_cache_enable(void) +{ + SCB_EnableDCache(); + return 0; +} + +int mcu_cache_disable(void) +{ + SCB_DisableDCache(); + return 0; +} + +int mcu_cache_invalidate(void) +{ + if(mcu_cache_enabled()) { + SCB_InvalidateDCache(); + } + return 0; +} + +int mcu_cache_clean(void) +{ + if(mcu_cache_enabled()) { + SCB_CleanDCache(); + } + return 0; +} + +int mcu_cache_clean_invalidate(void) +{ + if(mcu_cache_enabled()) { + SCB_CleanInvalidateDCache(); + } + return 0; +} + +int mcu_cache_invalidate_range(uint32_t start_addr, uint32_t end_addr) +{ + if(mcu_cache_enabled()) { + SCB_InvalidateDCache_by_Addr((volatile void *)start_addr, (int32_t)(end_addr - start_addr)); + } + return 0; +} + +int mcu_cache_clean_range(uint32_t start_addr, uint32_t end_addr) { + if(mcu_cache_enabled()) { + SCB_CleanDCache_by_Addr((volatile void *)start_addr, (int32_t)(end_addr - start_addr)); + } + return 0; +} + int mcu_cache_clean_invalidate_range(uint32_t start_addr, uint32_t end_addr) { + if(mcu_cache_enabled()) { + SCB_CleanInvalidateDCache_by_Addr((volatile void *)start_addr, (int32_t)(end_addr - start_addr)); + } + return 0; +} diff --git a/lib/stai/libstai/ll_aton/npu_cache.c b/lib/stai/libstai/ll_aton/npu_cache.c new file mode 100755 index 000000000..946458a4e --- /dev/null +++ b/lib/stai/libstai/ll_aton/npu_cache.c @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file npu_cache.c + * @brief Implementation of NPU-cache-handling functions (CACHEAXI) + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "npu_cache.h" +#include "stm32n6xx_hal_cacheaxi.h" + +static CACHEAXI_HandleTypeDef hcacheaxi_s; + +void npu_cache_init(void) +{ + hcacheaxi_s.Instance = CACHEAXI; + HAL_CACHEAXI_Init(&hcacheaxi_s); // Side effect: cacheaxi should be enabled (but one should call npu_enable_cache to be sure) +} + +void npu_cache_enable(void) +{ + HAL_StatusTypeDef status; + // Enable is wrapped in a loop because most of times, the first call returns + // HAL_BUSY, resulting in a cache not enabled. + do + { + status = HAL_CACHEAXI_Enable(&hcacheaxi_s); + } while (status == HAL_BUSY); +} + +void npu_cache_disable(void) +{ + HAL_StatusTypeDef status; + do + { + status = HAL_CACHEAXI_Disable(&hcacheaxi_s); + } while (status == HAL_BUSY); +} + +void npu_cache_invalidate(void) +{ + HAL_CACHEAXI_Invalidate(&hcacheaxi_s); +} + +void npu_cache_clean_range(uint32_t start_addr, uint32_t end_addr) +{ + HAL_CACHEAXI_CleanByAddr(&hcacheaxi_s, (uint32_t*)start_addr, end_addr-start_addr); +} + +void npu_cache_clean_invalidate_range(uint32_t start_addr, uint32_t end_addr) +{ + HAL_CACHEAXI_CleanInvalidByAddr(&hcacheaxi_s, (uint32_t*)start_addr, end_addr-start_addr); +} + +void NPU_CACHE_IRQHandler(void) +{ + __NOP(); +} diff --git a/lib/stai/stai.mk b/lib/stai/stai.mk new file mode 100644 index 000000000..46db868a8 --- /dev/null +++ b/lib/stai/stai.mk @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (C) 2025 OpenMV, LLC. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. +# +# STAI Makefile + +ifeq ($(MICROPY_PY_ML_STAI), 1) +STAI_SRC_C += \ + stai_backend.c \ + libstai/ll_aton/ai_reloc_network.c \ + libstai/ll_aton/ecloader.c \ + libstai/ll_aton/ll_aton.c \ + libstai/ll_aton/ll_aton_cipher.c \ + libstai/ll_aton/ll_aton_dbgtrc.c \ + libstai/ll_aton/ll_aton_debug.c \ + libstai/ll_aton/ll_aton_lib.c \ + libstai/ll_aton/ll_aton_lib_sw_operators.c \ + libstai/ll_aton/ll_aton_profiler.c \ + libstai/ll_aton/ll_aton_reloc_network.c \ + libstai/ll_aton/ll_aton_rt_main.c \ + libstai/ll_aton/ll_aton_runtime.c \ + libstai/ll_aton/ll_aton_util.c \ + libstai/ll_aton/ll_sw_float.c \ + libstai/ll_aton/ll_sw_integer.c \ + libstai/ll_aton/mcu_cache.c \ + libstai/ll_aton/npu_cache.c \ + +STAI_CFLAGS += \ + -DSTM32N657xx \ + -DLL_ATON_PLATFORM=LL_ATON_PLAT_STM32N6 \ + -DLL_ATON_OSAL=LL_ATON_OSAL_BARE_METAL \ + -DLL_ATON_RT_MODE=LL_ATON_RT_ASYNC \ + -DLL_ATON_SW_FALLBACK \ + -DLL_ATON_RT_RELOC \ + -DLL_ATON_EB_DBG_INFO \ + -DLL_ATON_DBG_BUFFER_INFO_EXCLUDED=1 \ + -DLL_ATON_DUMP_DEBUG_API + +STAI_CFLAGS += \ + -std=gnu99 \ + -mno-thumb-interwork \ + -ffast-math \ + -fsingle-precision-constant \ + -fvisibility=hidden \ + -fno-unwind-tables \ + -fstack-reuse=all \ + -ffunction-sections \ + -fdata-sections \ + -fno-math-errno \ + -fomit-frame-pointer + +$(BUILD)/lib/stai/%.o: override CFLAGS += \ + $(STAI_CFLAGS) + +$(BUILD)/lib/stai/libstai/ll_aton/%.o: override CFLAGS += \ + -Wno-format \ + -Wno-unused-variable \ + -Wno-dangling-pointer \ + -Wno-incompatible-pointer-types \ + -Wno-double-promotion \ + $(STAI_CFLAGS) \ + +OMV_CFLAGS += -I$(TOP_DIR)/lib/stai/libstai/include +OMV_FIRM_OBJ += $(addprefix $(BUILD)/lib/stai/, $(STAI_SRC_C:.c=.o)) +endif + diff --git a/lib/stai/stai_backend.c b/lib/stai/stai_backend.c new file mode 100644 index 000000000..bd090288c --- /dev/null +++ b/lib/stai/stai_backend.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2023-2024 OpenMV, LLC. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Any redistribution, use, or modification in source or binary form + * is done solely for personal benefit and not for any commercial + * purpose or for monetary gain. For commercial licensing options, + * please contact openmv@openmv.io + * + * THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT + * OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * STAI ML backend. + */ +#include +#include +#include "imlib_config.h" +#include STM32_HAL_H + +#include "py/runtime.h" +#include "py/obj.h" +#include "py/objlist.h" +#include "py/objtuple.h" +#include "py/binary.h" +#include "py/gc.h" +#include "py_ml.h" + +#include "ll_aton_runtime.h" +#include "ll_aton_platform.h" +#include "ll_aton_caches_interface.h" +#include "ll_aton_reloc_network.h" + +#define AI_RELOC_ALIGNMENT (32 - 1) +#define AI_RELOC_ALIGN(x) (((x) + (AI_RELOC_ALIGNMENT)) & ~(AI_RELOC_ALIGNMENT)) + +typedef struct ml_backend_state { + void *exec_ram_addr; + uint32_t exec_ram_size; + + void *ext_ram_addr; + uintptr_t ext_ram_size; + + NN_Instance_TypeDef nn_inst; + NN_Interface_TypeDef nn_iface; +} ml_backend_state_t; + +static bool ml_backend_valid_dataype(Buffer_DataType_TypeDef type) { + return (type == DataType_UINT8 || + type == DataType_INT8 || + type == DataType_UINT16 || + type == DataType_INT16 || + type == DataType_FLOAT); +} + +static char ml_backend_map_dtype(Buffer_DataType_TypeDef type) { + if (type == DataType_UINT8) { + return 'B'; + } else if (type == DataType_INT8) { + return 'b'; + } else if (type == DataType_UINT16) { + return 'H'; + } else if (type == DataType_INT16) { + return 'h'; + } else { + return 'f'; + } +} + +static int ml_backend_npu_init() { + static int npu_initialized = false; + + if (!npu_initialized) { + // Enable NPU clocks. + __HAL_RCC_NPU_CLK_ENABLE(); + __HAL_RCC_NPU_CLK_SLEEP_ENABLE(); + + // Reset NPU. + __HAL_RCC_NPU_FORCE_RESET(); + __HAL_RCC_NPU_RELEASE_RESET(); + + // Enable NPU cache clocks. + __HAL_RCC_CACHEAXI_CLK_ENABLE(); + __HAL_RCC_CACHEAXI_CLK_SLEEP_ENABLE(); + + // Reset NPU cache. + __HAL_RCC_CACHEAXI_FORCE_RESET(); + __HAL_RCC_CACHEAXI_RELEASE_RESET(); + + // Initialize NPU cache. + npu_cache_init(); + npu_cache_enable(); + + npu_initialized = true; + } + + return 0; +} + +int ml_backend_init_model(py_ml_model_obj_t *model) { + if (ml_backend_npu_init() != 0) { + mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("Failed to initialize NPU")); + return -1; + } + + // Allocate the persistent model state. + ml_backend_state_t *state = m_new0(ml_backend_state_t, 1); + state->nn_iface.network_name = "Default"; + state->nn_inst.network = &state->nn_iface; + + // Retrieve the info from the relocatable model. + ll_aton_reloc_info rt; + if (ll_aton_reloc_get_info((uintptr_t) model->data, &rt)) { + mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("Failed to load network")); + return -1; + } + + // Allocate executable memory. + state->exec_ram_size = AI_RELOC_ALIGN(rt.rt_ram_xip); + state->exec_ram_addr = m_new(uint8_t, state->exec_ram_size + AI_RELOC_ALIGNMENT); + + // Allocate external memory. + state->ext_ram_size = AI_RELOC_ALIGN(rt.ext_ram_sz); + state->ext_ram_addr = m_new(uint8_t, state->ext_ram_size + AI_RELOC_ALIGNMENT); + + // Create and install the relocatable model. + ll_aton_reloc_config config = { + .ext_ram_size = state->ext_ram_size, + .ext_ram_addr = AI_RELOC_ALIGN((uintptr_t) state->ext_ram_addr), + .exec_ram_size = state->exec_ram_size, + .exec_ram_addr = AI_RELOC_ALIGN((uintptr_t) state->exec_ram_addr), + .ext_param_addr = (uintptr_t) NULL, + // For COPY mode - XIP region is expected, else only RW region is requested. + // In the case where the HW epoch blob is embedded in the binary image, this + // memory region should be also memory-mapped and accessible by the NPU (ATON IP). + .mode = AI_RELOC_RT_LOAD_MODE_XIP, + }; + + // Invalidate DCache before installing the model's data. + SCB_InvalidateDCache_by_Addr((void *) config.exec_ram_addr, config.exec_ram_size); + + if (ll_aton_reloc_install((uintptr_t) model->data, &config, &state->nn_inst)) { + mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("Failed to load network")); + return -1; + } + + // Clean DCache after installing the model's data. + SCB_CleanDCache_by_Addr((void *) config.exec_ram_addr, config.exec_ram_size); + + // Invalidate ICache in copy mode (executing code from ram). + if (config.mode == AI_RELOC_RT_LOAD_MODE_COPY) { + SCB_InvalidateICache_by_Addr((void *) config.exec_ram_addr, config.exec_ram_size); + } + + // Initialize the model's state. + model->state = state; + model->memory_addr = config.exec_ram_addr; + model->memory_size = config.exec_ram_size + config.ext_ram_size; + + const LL_Buffer_InfoTypeDef *model_inputs = ll_aton_reloc_get_input_buffers_info(&state->nn_inst, -1); + const LL_Buffer_InfoTypeDef *model_outputs = ll_aton_reloc_get_output_buffers_info(&state->nn_inst, -1); + + // Initialize the model's inputs. + model->inputs_size = 1; + model->input_shape = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->inputs_size, NULL)); + model->input_scale = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->inputs_size, NULL)); + model->input_zero_point = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->inputs_size, NULL)); + model->input_dtype = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->inputs_size, NULL)); + + for (size_t i=0; iinputs_size; i++) { + const LL_Buffer_InfoTypeDef *input = &model_inputs[i]; + + // Check input data type. + if (!ml_backend_valid_dataype(input->type)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Unsupported input data type %d"), input->type); + } + + mp_obj_tuple_t *o = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(input->mem_ndims, NULL)); + for (int j=0; jmem_ndims; j++) { + o->items[j] = mp_obj_new_int(input->mem_shape[j]); + } + + float input_scale = input->scale[0]; + model->input_shape->items[i] = MP_OBJ_FROM_PTR(o); + model->input_scale->items[i] = mp_obj_new_float((input_scale == 0.0f) ? 1.0f : input_scale); + model->input_zero_point->items[i] = mp_obj_new_int(input->offset[0]); + model->input_dtype->items[i] = mp_obj_new_int(ml_backend_map_dtype(input->type)); + } + + // Initialize the model's outputs. + model->outputs_size = 1; + model->output_shape = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->outputs_size, NULL)); + model->output_scale = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->outputs_size, NULL)); + model->output_zero_point = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->outputs_size, NULL)); + model->output_dtype = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(model->outputs_size, NULL)); + + for (size_t i=0; ioutputs_size; i++) { + const LL_Buffer_InfoTypeDef *output = &model_outputs[i]; + + // Check output data type. + if (!ml_backend_valid_dataype(output->type)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Unsupported output data type %d"), output->type); + } + + mp_obj_tuple_t *o = (mp_obj_tuple_t *) MP_OBJ_TO_PTR(mp_obj_new_tuple(output->mem_ndims, NULL)); + for (int j=0; jmem_ndims; j++) { + o->items[j] = mp_obj_new_int(output->mem_shape[j]); + } + + model->output_shape->items[i] = MP_OBJ_FROM_PTR(o); + model->output_scale->items[i] = mp_obj_new_float((output->type == DataType_FLOAT) ? 1.0f : output->scale[0]); + model->output_zero_point->items[i] = mp_obj_new_int((output->type == DataType_FLOAT) ? 0 : output->offset[0]); + model->output_dtype->items[i] = mp_obj_new_int(ml_backend_map_dtype(output->type)); + } + + return 0; +} + +int ml_backend_run_inference(py_ml_model_obj_t *model) { + ml_backend_state_t *state = (ml_backend_state_t *) model->state; + + // Flush input buffers. + for (size_t i=0; i< model->inputs_size; i++) { + const LL_Buffer_InfoTypeDef *buf = ll_aton_reloc_get_input_buffers_info(&state->nn_inst, i); + SCB_CleanDCache_by_Addr(LL_Buffer_addr_start(buf), LL_Buffer_len(buf)); + } + + LL_ATON_RT_Main(&state->nn_inst); + return 0; +} + +void *ml_backend_get_input(py_ml_model_obj_t *model, size_t index) { + ml_backend_state_t *state = (ml_backend_state_t *) model->state; + + if (index < model->inputs_size) { + const LL_Buffer_InfoTypeDef *buf = ll_aton_reloc_get_input_buffers_info(&state->nn_inst, index); + return LL_Buffer_addr_start(buf); + } + + mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("invalid input tensor index")); +} + +void *ml_backend_get_output(py_ml_model_obj_t *model, size_t index) { + ml_backend_state_t *state = (ml_backend_state_t *) model->state; + + if (index < model->outputs_size) { + const LL_Buffer_InfoTypeDef *buf = ll_aton_reloc_get_output_buffers_info(&state->nn_inst, index); + SCB_InvalidateDCache_by_Addr(LL_Buffer_addr_start(buf), LL_Buffer_len(buf)); + return LL_Buffer_addr_start(buf); + } + + mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("Invalid output tensor index")); +}