From 4a1a1441c7c7f525a083e9efcd4adf7532bb618e Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Thu, 20 Jun 2019 22:01:13 +0200 Subject: [PATCH] Add OPENMV4R board files. --- src/micropython | 2 +- src/omv/boards/OPENMV4R/imlib_config.h | 151 +++++++++++++ src/omv/boards/OPENMV4R/omv_boardconfig.h | 236 +++++++++++++++++++++ src/omv/boards/OPENMV4R/omv_boardconfig.mk | 10 + 4 files changed, 398 insertions(+), 1 deletion(-) create mode 100644 src/omv/boards/OPENMV4R/imlib_config.h create mode 100644 src/omv/boards/OPENMV4R/omv_boardconfig.h create mode 100755 src/omv/boards/OPENMV4R/omv_boardconfig.mk diff --git a/src/micropython b/src/micropython index 258d92e36..ede6e0c04 160000 --- a/src/micropython +++ b/src/micropython @@ -1 +1 @@ -Subproject commit 258d92e36458990585931399c5b8bf0375513113 +Subproject commit ede6e0c04c5ea7550b34dcdbcd959c72881f3c88 diff --git a/src/omv/boards/OPENMV4R/imlib_config.h b/src/omv/boards/OPENMV4R/imlib_config.h new file mode 100644 index 000000000..d46ce6e11 --- /dev/null +++ b/src/omv/boards/OPENMV4R/imlib_config.h @@ -0,0 +1,151 @@ +/* + * This file is part of the OpenMV project. + * Copyright (c) 2013/2014 Ibrahim Abdelkader + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * Image library configuration. + * + */ +#ifndef __IMLIB_CONFIG_H__ +#define __IMLIB_CONFIG_H__ + +// Enable LAB LUT +#define IMLIB_ENABLE_LAB_LUT + +// Enable YUV LUT +#define IMLIB_ENABLE_YUV_LUT + +// Enable mean pooling +#define IMLIB_ENABLE_MEAN_POOLING + +// Enable midpoint pooling +#define IMLIB_ENABLE_MIDPOINT_POOLING + +// Enable binary ops +#define IMLIB_ENABLE_BINARY_OPS + +// Enable math ops +#define IMLIB_ENABLE_MATH_OPS + +// Enable flood_fill() +#define IMLIB_ENABLE_FLOOD_FILL + +// Enable mean() +#define IMLIB_ENABLE_MEAN + +// Enable median() +#define IMLIB_ENABLE_MEDIAN + +// Enable mode() +#define IMLIB_ENABLE_MODE + +// Enable midpoint() +#define IMLIB_ENABLE_MIDPOINT + +// Enable morph() +#define IMLIB_ENABLE_MORPH + +// Enable Gaussian +#define IMLIB_ENABLE_GAUSSIAN + +// Enable Laplacian +#define IMLIB_ENABLE_LAPLACIAN + +// Enable bilateral() +#define IMLIB_ENABLE_BILATERAL + +// Enable cartoon() +#define IMLIB_ENABLE_CARTOON + +// Enable remove_shadows() +#define IMLIB_ENABLE_REMOVE_SHADOWS + +// Enable linpolar() +#define IMLIB_ENABLE_LINPOLAR + +// Enable logpolar() +#define IMLIB_ENABLE_LOGPOLAR + +// Enable chrominvar() +#define IMLIB_ENABLE_CHROMINVAR + +// Enable illuminvar() +#define IMLIB_ENABLE_ILLUMINVAR + +// Enable invariant table +//#define IMLIB_ENABLE_INVARIANT_TABLE + +// Enable rotation_corr() +#define IMLIB_ENABLE_ROTATION_CORR + +// Enable phasecorrelate() +#define IMLIB_ENABLE_FIND_DISPLACEMENT + +// rotation_corr() is required by phasecorrelate() +#if defined(IMLIB_ENABLE_FIND_DISPLACEMENT)\ + && !defined(IMLIB_ENABLE_ROTATION_CORR) + #define IMLIB_ENABLE_ROTATION_CORR +#endif + +// Enable get_similarity() +#define IMLIB_ENABLE_GET_SIMILARITY + +// Enable find_lines() +#define IMLIB_ENABLE_FIND_LINES + +// Enable find_line_segments() +#define IMLIB_ENABLE_FIND_LINE_SEGMENTS + +// find_lines() is required by the old find_line_segments() +#if defined(IMLIB_ENABLE_FIND_LINE_SEGMENTS)\ + && !defined(IMLIB_ENABLE_FIND_LINES) + #define IMLIB_ENABLE_FIND_LINES +#endif + +// Enable find_circles() +#define IMLIB_ENABLE_FIND_CIRCLES + +// Enable find_rects() +#define IMLIB_ENABLE_FIND_RECTS + +// Enable find_qrcodes() (14 KB) +#define IMLIB_ENABLE_QRCODES + +// Enable find_apriltags() (64 KB) +#define IMLIB_ENABLE_APRILTAGS + +// Enable find_datamatrices() (26 KB) +#define IMLIB_ENABLE_DATAMATRICES + +// Enable find_barcodes() (42 KB) +#define IMLIB_ENABLE_BARCODES + +// Enable LENET (200+ KB). +#define IMLIB_ENABLE_LENET + +// Enable CMSIS NN +#define IMLIB_ENABLE_CNN + +// Enable FAST (20+ KBs). +#define IMLIB_ENABLE_FAST + +// Enable find_template() +#define IMLIB_FIND_TEMPLATE + +// Enable find_lbp() +#define IMLIB_ENABLE_FIND_LBP + +// Enable find_keypoints() +#define IMLIB_ENABLE_FIND_KEYPOINTS + +#if defined(IMLIB_ENABLE_FIND_LBP) || defined(IMLIB_ENABLE_FIND_KEYPOINTS) + #define IMLIB_ENABLE_DESCRIPTOR +#endif + +// Enable find_hog() +#define IMLIB_ENABLE_HOG + +// Enable selective_search() +#define IMLIB_ENABLE_SELECTIVE_SEARCH + +#endif //__IMLIB_CONFIG_H__ diff --git a/src/omv/boards/OPENMV4R/omv_boardconfig.h b/src/omv/boards/OPENMV4R/omv_boardconfig.h new file mode 100644 index 000000000..52b2929cd --- /dev/null +++ b/src/omv/boards/OPENMV4R/omv_boardconfig.h @@ -0,0 +1,236 @@ +/* + * This file is part of the OpenMV project. + * Copyright (c) 2013/2014 Ibrahim Abdelkader + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * Board configuration and pin definitions. + * + */ +#ifndef __OMV_BOARDCONFIG_H__ +#define __OMV_BOARDCONFIG_H__ + +// Architecture info +#define OMV_ARCH_STR "OMV4R H7 16384 SDRAM" // 33 chars max +#define OMV_BOARD_TYPE "H7" +#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 + +// Flash sectors for the bootloader. +// Flash FS sector, main FW sector, max sector. +#define OMV_FLASH_LAYOUT {1, 2, 15} + +#define OMV_XCLK_MCO (0U) +#define OMV_XCLK_TIM (1U) + +// Sensor external clock source. +#define OMV_XCLK_SOURCE (OMV_XCLK_TIM) + +// Sensor external clock timer frequency. +#define OMV_XCLK_FREQUENCY (12000000) + +// Sensor PLL register value. +#define OMV_OV7725_PLL_CONFIG (0x41) // x4 + +// Sensor Banding Filter Value +#define OMV_OV7725_BANDING (0x7F) + +// Bootloader LED GPIO port/pin +#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_1) +#define OMV_BOOTLDR_LED_PORT (GPIOC) + +// RAW buffer size +#define OMV_RAW_BUF_SIZE (409600) + +// Enable hardware JPEG +#define OMV_HARDWARE_JPEG (1) + +// Enable MT9V034 and LEPTON sensors +#define OMV_ENABLE_MT9V034 (1) +#define OMV_ENABLE_LEPTON (1) + +// If buffer size is bigger than this threshold, the quality is reduced. +// This is only used for JPEG images sent to the IDE not normal compression. +#define JPEG_QUALITY_THRESH (320*240*2) + +// Low and high JPEG QS. +#define JPEG_QUALITY_LOW 50 +#define JPEG_QUALITY_HIGH 90 + +// Linker script constants (see the linker script template stm32fxxx.ld.S). +// Note: fb_alloc is a stack-based, dynamically allocated memory on FB. +// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp). +#define OMV_FFS_MEMORY CCM // Flash filesystem cache memory +#define OMV_MAIN_MEMORY SRAM1 // data, bss, stack and heap +#define OMV_DMA_MEMORY AXI_SRAM // DMA buffers memory. +#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc +#define OMV_JPEG_MEMORY SRAM3 // JPEG buffer memory. +#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory. + +#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image +#define OMV_FB_ALLOC_SIZE (96K) // minimum fb alloc size +#define OMV_STACK_SIZE (7K) +#define OMV_HEAP_SIZE (240K) + +#define OMV_LINE_BUF_SIZE (3K) // Image line buffer round(640 * 2BPP * 2 buffers). +#define OMV_MSC_BUF_SIZE (12K) // USB MSC bot data +#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes) +#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data). + +#define OMV_BOOT_ORIGIN 0x08000000 +#define OMV_BOOT_LENGTH 128K +#define OMV_TEXT_ORIGIN 0x08040000 +#define OMV_TEXT_LENGTH 1792K +#define OMV_CCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only. +#define OMV_CCM_LENGTH 128K +#define OMV_SRAM1_ORIGIN 0x30000000 +#define OMV_SRAM1_LENGTH 256K +#define OMV_SRAM3_ORIGIN 0x30040000 +#define OMV_SRAM3_LENGTH 32K +#define OMV_SRAM4_ORIGIN 0x38000000 +#define OMV_SRAM4_LENGTH 64K +#define OMV_AXI_SRAM_ORIGIN 0x24000000 +#define OMV_AXI_SRAM_LENGTH 512K + +// Use the MPU to set an uncacheable memory region. +#define OMV_DMA_REGION_BASE (OMV_AXI_SRAM_ORIGIN+(496*1024)) +#define OMV_DMA_REGION_SIZE MPU_REGION_SIZE_16KB + +/* SCCB/I2C */ +#define SCCB_I2C (I2C1) +#define SCCB_AF (GPIO_AF4_I2C1) +#define SCCB_CLK_ENABLE() __I2C1_CLK_ENABLE() +#define SCCB_CLK_DISABLE() __I2C1_CLK_DISABLE() +#define SCCB_PORT (GPIOB) +#define SCCB_SCL_PIN (GPIO_PIN_8) +#define SCCB_SDA_PIN (GPIO_PIN_9) +#define SCCB_TIMING (0x20D09DE7) // Frequency: 100KHz Rise Time: 100ns Fall Time: 20ns + +/* DCMI */ +#define DCMI_TIM (TIM1) +#define DCMI_TIM_PIN (GPIO_PIN_8) +#define DCMI_TIM_PORT (GPIOA) +#define DCMI_TIM_AF (GPIO_AF1_TIM1) +#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1) +#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE() +#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE() +#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq() + +#define DCMI_RESET_PIN (GPIO_PIN_10) +#define DCMI_RESET_PORT (GPIOA) + +#define DCMI_PWDN_PIN (GPIO_PIN_7) +#define DCMI_PWDN_PORT (GPIOD) + +#define DCMI_FSIN_PIN (GPIO_PIN_5) +#define DCMI_FSIN_PORT (GPIOB) + +#define DCMI_D0_PIN (GPIO_PIN_6) +#define DCMI_D1_PIN (GPIO_PIN_7) +#define DCMI_D2_PIN (GPIO_PIN_10) +#define DCMI_D3_PIN (GPIO_PIN_11) +#define DCMI_D4_PIN (GPIO_PIN_4) +#define DCMI_D5_PIN (GPIO_PIN_6) +#define DCMI_D6_PIN (GPIO_PIN_5) +#define DCMI_D7_PIN (GPIO_PIN_6) + +#define DCMI_D0_PORT (GPIOC) +#define DCMI_D1_PORT (GPIOC) +#define DCMI_D2_PORT (GPIOG) +#define DCMI_D3_PORT (GPIOG) +#define DCMI_D4_PORT (GPIOE) +#define DCMI_D5_PORT (GPIOB) +#define DCMI_D6_PORT (GPIOE) +#define DCMI_D7_PORT (GPIOE) + +#define DCMI_HSYNC_PIN (GPIO_PIN_4) +#define DCMI_VSYNC_PIN (GPIO_PIN_7) +#define DCMI_PXCLK_PIN (GPIO_PIN_6) + +#define DCMI_HSYNC_PORT (GPIOA) +#define DCMI_VSYNC_PORT (GPIOB) +#define DCMI_PXCLK_PORT (GPIOA) + +#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET) +#define DCMI_RESET_HIGH() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_SET) + +#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET) +#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET) + +#define DCMI_FSIN_LOW() HAL_GPIO_WritePin(DCMI_FSIN_PORT, DCMI_FSIN_PIN, GPIO_PIN_RESET) +#define DCMI_FSIN_HIGH() HAL_GPIO_WritePin(DCMI_FSIN_PORT, DCMI_FSIN_PIN, GPIO_PIN_SET) + +#define DCMI_VSYNC_IRQN EXTI9_5_IRQn +#define DCMI_VSYNC_IRQ_LINE (7) + +#define WINC_SPI (SPI2) +#define WINC_SPI_AF (GPIO_AF5_SPI2) +#define WINC_SPI_TIMEOUT (1000) +// SPI1/2/3 clock source is PLL2 (160MHz/4 == 40MHz). +#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4) +#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE() + +#define WINC_SPI_SCLK_PIN (GPIO_PIN_13) +#define WINC_SPI_MISO_PIN (GPIO_PIN_14) +#define WINC_SPI_MOSI_PIN (GPIO_PIN_15) + +#define WINC_SPI_SCLK_PORT (GPIOB) +#define WINC_SPI_MISO_PORT (GPIOB) +#define WINC_SPI_MOSI_PORT (GPIOB) + +#define WINC_EN_PIN (GPIO_PIN_5) +#define WINC_CS_PIN (GPIO_PIN_12) +#define WINC_RST_PIN (GPIO_PIN_12) +#define WINC_IRQ_PIN (pin_D13) + +#define WINC_EN_PORT (GPIOA) +#define WINC_CS_PORT (GPIOB) +#define WINC_RST_PORT (GPIOD) + +#define WINC_CS_LOW() HAL_GPIO_WritePin(WINC_CS_PORT, WINC_CS_PIN, GPIO_PIN_RESET) +#define WINC_CS_HIGH() HAL_GPIO_WritePin(WINC_CS_PORT, WINC_CS_PIN, GPIO_PIN_SET) + +#define I2C_PORT GPIOB +#define I2C_SIOC_PIN GPIO_PIN_10 +#define I2C_SIOD_PIN GPIO_PIN_11 + +#define I2C_SIOC_H() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOC_PIN, GPIO_PIN_SET) +#define I2C_SIOC_L() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOC_PIN, GPIO_PIN_RESET) + +#define I2C_SIOD_H() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOD_PIN, GPIO_PIN_SET) +#define I2C_SIOD_L() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOD_PIN, GPIO_PIN_RESET) + +#define I2C_SIOD_READ() HAL_GPIO_ReadPin(I2C_PORT, I2C_SIOD_PIN) +#define I2C_SIOD_WRITE(bit) HAL_GPIO_WritePin(I2C_PORT, I2C_SIOD_PIN, bit); + +#define I2C_SPIN_DELAY 32 + +#define LEPTON_SPI (SPI3) +#define LEPTON_SPI_AF (GPIO_AF6_SPI3) +// SPI1/2/3 clock source is PLL2 (160MHz/8 == 20MHz). +#define LEPTON_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_8) + +#define LEPTON_SPI_IRQn (SPI3_IRQn) +#define LEPTON_SPI_IRQHandler (SPI3_IRQHandler) + +#define LEPTON_SPI_DMA_IRQn (DMA1_Stream0_IRQn) +#define LEPTON_SPI_DMA_STREAM (DMA1_Stream0) + +#define LEPTON_SPI_DMA_REQUEST (DMA_REQUEST_SPI3_RX) +#define LEPTON_SPI_DMA_IRQHandler (DMA1_Stream0_IRQHandler) + +#define LEPTON_SPI_RESET() __HAL_RCC_SPI3_FORCE_RESET() +#define LEPTON_SPI_RELEASE() __HAL_RCC_SPI3_RELEASE_RESET() + +#define LEPTON_SPI_CLK_ENABLE() __HAL_RCC_SPI3_CLK_ENABLE() +#define LEPTON_SPI_CLK_DISABLE() __HAL_RCC_SPI3_CLK_DISABLE() + +#define LEPTON_SPI_SCLK_PIN (GPIO_PIN_3) +#define LEPTON_SPI_MISO_PIN (GPIO_PIN_4) +#define LEPTON_SPI_MOSI_PIN (GPIO_PIN_5) +#define LEPTON_SPI_SSEL_PIN (GPIO_PIN_15) + +#define LEPTON_SPI_SCLK_PORT (GPIOB) +#define LEPTON_SPI_MISO_PORT (GPIOB) +#define LEPTON_SPI_MOSI_PORT (GPIOB) +#define LEPTON_SPI_SSEL_PORT (GPIOA) + +#endif //__OMV_BOARDCONFIG_H__ diff --git a/src/omv/boards/OPENMV4R/omv_boardconfig.mk b/src/omv/boards/OPENMV4R/omv_boardconfig.mk new file mode 100755 index 000000000..a77bd18f0 --- /dev/null +++ b/src/omv/boards/OPENMV4R/omv_boardconfig.mk @@ -0,0 +1,10 @@ +MCU=STM32H743xx +CPU=cortex-m7 +FPU=fpv5-sp-d16 +STHAL_DIR=sthal/h7 +ARM_MATH=ARM_MATH_CM7 +HAL_INC='' +CFLAGS_MCU=MCU_SERIES_H7 +STARTUP=startup_stm32h743xx +VECT_TAB_OFFSET=0x40000 +MAIN_APP_ADDR=0x08040000