ports/stm32: Add support for Nema GPUs.

Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
iabdalkader 2024-12-22 15:03:00 +01:00
parent a4daf58ef5
commit ecaec5c0b2
4 changed files with 308 additions and 11 deletions

View File

@ -26,19 +26,114 @@
#include "omv_boardconfig.h"
#if (OMV_GPU_ENABLE == 1)
#include STM32_HAL_H
#include "py/mphal.h"
#include "py/runtime.h"
#include "imlib.h"
#include "dma.h"
#if OMV_GPU_NEMA
#include "nema_core.h"
#include "nema_vg.h"
#include "nema_error.h"
#endif
#if OMV_GPU_NEMA_MM_STATIC
uint8_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(NEMA_BUFFER[OMV_GPU_NEMA_BUFFER_SIZE], 32), ".dma_buffer");
#endif
int omv_gpu_init() {
return 0;
int error = 0;
#if OMV_GPU_NEMA
nema_init();
error = nema_get_error();
#endif
return error;
}
void omv_gpu_deinit() {
DMA2D_HandleTypeDef dma2d = {};
dma2d.Instance = DMA2D;
HAL_DMA2D_DeInit(&dma2d);
}
#if OMV_GPU_NEMA
static nema_tex_format_t omv_gpu_pixfmt(uint32_t omv_pixfmt) {
switch (omv_pixfmt) {
case PIXFORMAT_BINARY:
return NEMA_L1; // source only
case PIXFORMAT_BAYER_ANY:
case PIXFORMAT_GRAYSCALE:
return NEMA_L8;
case PIXFORMAT_RGB565:
return NEMA_RGB565;
}
mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("Pixel format is not supported"));
}
int omv_gpu_draw_image(image_t *src_img,
rectangle_t *src_rect,
image_t *dst_img,
rectangle_t *dst_rect,
int alpha,
const uint16_t *color_palette,
const uint8_t *alpha_palette,
image_hint_t hint) {
OMV_PROFILE_START();
if ((dst_rect->w != src_rect->w) || (dst_rect->h != src_rect->h)) {
// Create command list.
#if OMV_GPU_NEMA_MM_STATIC
nema_buffer_t bo = {
.size = sizeof(NEMA_BUFFER),
.base_virt = NEMA_BUFFER,
.base_phys = (uint32_t) NEMA_BUFFER,
};
nema_cmdlist_t cl = nema_cl_create_prealloc(&bo);
#else
nema_cmdlist_t cl = nema_cl_create_sized(OMV_GPU_NEMA_BUFFER_SIZE);
#endif
// Bind command list.
nema_cl_bind_circular(&cl);
nema_tex_mode_t blit_mode;
if (hint & IMAGE_HINT_BILINEAR) {
blit_mode = NEMA_FILTER_BL;
} else {
blit_mode = NEMA_FILTER_PS;
}
// Set up destination texture.
nema_tex_format_t dst_pixfmt = omv_gpu_pixfmt(dst_img->pixfmt);
nema_bind_dst_tex((uintptr_t) dst_img->data, dst_rect->w, dst_rect->h, dst_pixfmt, -1);
// Set up source texture.
nema_tex_format_t src_pixfmt = omv_gpu_pixfmt(src_img->pixfmt);
nema_bind_src_tex((uintptr_t) src_img->data, src_rect->w, src_rect->h, src_pixfmt, -1, blit_mode);
// Configure operations.
nema_set_blend_blit(NEMA_BL_SRC);
nema_set_clip(0, 0, dst_rect->w, dst_rect->h);
nema_blit_rect_fit(0, 0, dst_rect->w, dst_rect->h);
// Flush source image
SCB_CleanDCache_by_Addr(src_img->data, image_size(src_img));
nema_cl_submit(&cl);
nema_cl_wait(&cl);
#if !OMV_GPU_NEMA_MM_STATIC
nema_cl_destroy(&cl);
#endif
// Invalidate the destination image.
SCB_InvalidateDCache_by_Addr(dst_img->data, image_size(dst_img));
} else {
return -1;
}
OMV_PROFILE_PRINT();
return 0;
}
#else
int omv_gpu_draw_image(image_t *src_img,
rectangle_t *src_rect,
image_t *dst_img,
@ -79,9 +174,11 @@ int omv_gpu_draw_image(image_t *src_img,
}
#endif
DMA2D_HandleTypeDef dma2d = {};
dma2d.Instance = DMA2D;
DMA2D_HandleTypeDef dma2d = {
.Instance = DMA2D,
.Init.ColorMode = DMA2D_OUTPUT_RGB565,
.Init.OutputOffset = dst_img->w - dst_rect->w,
};
if (dst_img->pixfmt != src_img->pixfmt) {
dma2d.Init.Mode = DMA2D_M2M_PFC;
@ -97,9 +194,6 @@ int omv_gpu_draw_image(image_t *src_img,
}
#endif
dma2d.Init.ColorMode = DMA2D_OUTPUT_RGB565;
dma2d.Init.OutputOffset = dst_img->w - dst_rect->w;
HAL_DMA2D_Init(&dma2d);
dma2d.LayerCfg[0].InputOffset = dst_img->w - dst_rect->w;
@ -245,4 +339,5 @@ int omv_gpu_draw_image(image_t *src_img,
OMV_PROFILE_PRINT();
return 0;
}
#endif // (OMV_GPU_ENABLE == 1)
#endif // OMV_GPU_NEMA
#endif // OMV_GPU_ENABLE

View File

@ -58,6 +58,7 @@ CFLAGS += -D$(MCU) \
-DHSE_VALUE=$(OMV_HSE_VALUE)\
-DOMV_VTOR_BASE=$(OMV_FIRM_ADDR) \
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
-DOMV_NOSYS_STUBS_ENABLE=1 \
-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
$(OMV_BOARD_CFLAGS)
@ -125,6 +126,7 @@ OMV_CFLAGS += -I$(TOP_DIR)/$(MLX90641_DIR)/include/
OMV_CFLAGS += -I$(TOP_DIR)/$(PIXART_DIR)/include/
OMV_CFLAGS += -I$(TOP_DIR)/$(DISPLAY_DIR)/include/
OMV_CFLAGS += -I$(TOP_DIR)/$(LIBPDM_DIR)/
OMV_CFLAGS += -I$(TOP_DIR)/$(NEMA_DIR)/include
ifeq ($(OMV_ENABLE_UVC), 1)
UVC_CFLAGS := $(CFLAGS) $(HAL_CFLAGS)
@ -189,6 +191,7 @@ FIRM_OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/common/, \
file_utils.o \
mp_utils.o \
omv_csi.o \
nosys_stubs.o \
)
FIRM_OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/sensors/, \
@ -652,6 +655,10 @@ ifeq ($(MICROPY_PY_AUDIO), 1)
LIBS += $(TOP_DIR)/$(LIBPDM_DIR)/libPDMFilter_CM7_GCC_wc32.a
endif
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),n6))
LIBS += $(TOP_DIR)/$(NEMA_DIR)/lib/libnemagfx-$(CPU)+fp.a
endif
#------------- ML libraries ----------------#
ifeq ($(MICROPY_PY_ML_TFLM), 1)
OMV_CFLAGS += -I$(BUILD)/$(TENSORFLOW_DIR)/

View File

@ -640,8 +640,36 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) {
__HAL_RCC_DMA2D_FORCE_RESET();
__HAL_RCC_DMA2D_RELEASE_RESET();
__HAL_RCC_DMA2D_CLK_DISABLE();
__HAL_RCC_DMA2D_CLK_SLEEP_DISABLE();
}
#if defined(GPU2D)
void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d) {
__HAL_RCC_GPU2D_FORCE_RESET();
__HAL_RCC_GPU2D_RELEASE_RESET();
__HAL_RCC_GPU2D_CLK_ENABLE();
__HAL_RCC_GPU2D_CLK_SLEEP_ENABLE();
}
void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d) {
__HAL_RCC_GPU2D_CLK_DISABLE();
__HAL_RCC_GPU2D_CLK_SLEEP_DISABLE();
}
#endif
#if defined(GFXMMU)
void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) {
__HAL_RCC_GFXMMU_CLK_ENABLE();
__HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE();
}
void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) {
__HAL_RCC_GFXMMU_CLK_DISABLE();
__HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE();
}
#endif
#if (OMV_JPEG_CODEC_ENABLE == 1)
void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) {
__HAL_RCC_JPEG_CLK_ENABLE();

View File

@ -0,0 +1,167 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* STM32 Nema HAL layer.
*/
#include <stdlib.h>
#include STM32_HAL_H
#include "omv_boardconfig.h"
#if (OMV_GPU_NEMA == 1)
#include "omv_common.h"
#include "nema_core.h"
#include "nema_sys_defs.h"
#ifndef OMV_GPU_NEMA_RING_SIZE
#define OMV_GPU_NEMA_RING_SIZE 1024
#endif
volatile static int last_cl_id;
static GPU2D_HandleTypeDef gpu2d = { 0 };
static nema_ringbuffer_t ring_buf = {{0}};
#if OMV_GPU_NEMA_MM_STATIC
uint8_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(RING_BUFFER[OMV_GPU_NEMA_RING_SIZE], 32), ".dma_buffer");
#endif
int32_t nema_sys_init(void) {
// Initialize GPU2D
gpu2d.Instance = GPU2D;
HAL_GPU2D_Init(&gpu2d);
// Configure and enable texture cache
HAL_ICACHE_DeInit();
HAL_ICACHE_Disable();
HAL_ICACHE_ConfigAssociativityMode(ICACHE_4WAYS);
HAL_ICACHE_Enable();
// Allocate ring buffer.
#if OMV_GPU_NEMA_MM_STATIC
ring_buf.bo.fd = 0;
ring_buf.bo.size = sizeof(RING_BUFFER);
ring_buf.bo.base_virt = RING_BUFFER;
ring_buf.bo.base_phys = (uint32_t) RING_BUFFER;
#else
ring_buf.bo = nema_buffer_create(OMV_GPU_NEMA_RING_SIZE);
#endif
// Initialize ring buffer.
if (nema_rb_init(&ring_buf, 1) != 0) {
return -1;
}
NVIC_SetPriority(GPU2D_IRQn, IRQ_PRI_GPU);
NVIC_EnableIRQ(GPU2D_IRQn);
NVIC_SetPriority(GPU2D_ER_IRQn, IRQ_PRI_GPU);
NVIC_EnableIRQ(GPU2D_ER_IRQn);
return 0;
}
int nema_wait_irq_cl(int cl_id) {
while (last_cl_id < cl_id) {
__WFI();
}
return 0;
}
int nema_wait_irq_brk(int brk_id) {
while (nema_reg_read(GPU2D_BREAKPOINT) == 0U) {
__WFI();
}
return 0;
}
uint32_t nema_reg_read(uint32_t reg) {
return HAL_GPU2D_ReadRegister(&gpu2d, reg);
}
void nema_reg_write(uint32_t reg, uint32_t value) {
HAL_GPU2D_WriteRegister(&gpu2d, reg, value);
}
nema_buffer_t nema_buffer_create(int size) {
nema_buffer_t bo = {
.base_virt = nema_host_malloc(size),
.base_phys = (uint32_t) bo.base_virt,
.size = size,
};
return bo;
}
nema_buffer_t nema_buffer_create_pool(int pool, int size) {
return nema_buffer_create(size);
}
void *nema_buffer_map(nema_buffer_t *bo) {
return bo->base_virt;
}
void nema_buffer_unmap(nema_buffer_t *bo) {
UNUSED(bo);
}
void nema_buffer_destroy(nema_buffer_t *bo) {
nema_host_free(bo->base_virt);
}
uintptr_t nema_buffer_phys(nema_buffer_t *bo) {
return bo->base_phys;
}
void nema_buffer_flush(nema_buffer_t *bo) {
#if !OMV_GPU_NEMA_MM_STATIC
SCB_CleanInvalidateDCache_by_Addr((uint32_t *) bo->base_virt, bo->size);
#endif
}
void nema_host_free(void *ptr) {
if (ptr) {
free(ptr);
}
}
void *nema_host_malloc(unsigned size) {
return malloc(size);
}
int nema_mutex_lock(int mutex_id) {
return 0;
}
int nema_mutex_unlock(int mutex_id) {
return 0;
}
void GPU2D_IRQHandler(void) {
HAL_GPU2D_IRQHandler(&gpu2d);
}
void GPU2D_ER_IRQHandler(void) {
HAL_GPU2D_ER_IRQHandler(&gpu2d);
}
void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *gpu2d, uint32_t CmdListID) {
last_cl_id = CmdListID;
}
#endif // OMV_GPU_NEMA