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ports/stm32: Add support for Nema GPUs.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
parent
a4daf58ef5
commit
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@ -26,19 +26,114 @@
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#include "omv_boardconfig.h"
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#if (OMV_GPU_ENABLE == 1)
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#include STM32_HAL_H
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#include "py/mphal.h"
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#include "py/runtime.h"
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#include "imlib.h"
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#include "dma.h"
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#if OMV_GPU_NEMA
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#include "nema_core.h"
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#include "nema_vg.h"
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#include "nema_error.h"
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#endif
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#if OMV_GPU_NEMA_MM_STATIC
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uint8_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(NEMA_BUFFER[OMV_GPU_NEMA_BUFFER_SIZE], 32), ".dma_buffer");
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#endif
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int omv_gpu_init() {
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return 0;
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int error = 0;
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#if OMV_GPU_NEMA
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nema_init();
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error = nema_get_error();
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#endif
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return error;
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}
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void omv_gpu_deinit() {
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DMA2D_HandleTypeDef dma2d = {};
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dma2d.Instance = DMA2D;
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HAL_DMA2D_DeInit(&dma2d);
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}
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#if OMV_GPU_NEMA
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static nema_tex_format_t omv_gpu_pixfmt(uint32_t omv_pixfmt) {
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switch (omv_pixfmt) {
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case PIXFORMAT_BINARY:
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return NEMA_L1; // source only
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case PIXFORMAT_BAYER_ANY:
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case PIXFORMAT_GRAYSCALE:
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return NEMA_L8;
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case PIXFORMAT_RGB565:
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return NEMA_RGB565;
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}
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mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("Pixel format is not supported"));
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}
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int omv_gpu_draw_image(image_t *src_img,
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rectangle_t *src_rect,
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image_t *dst_img,
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rectangle_t *dst_rect,
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int alpha,
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const uint16_t *color_palette,
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const uint8_t *alpha_palette,
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image_hint_t hint) {
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OMV_PROFILE_START();
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if ((dst_rect->w != src_rect->w) || (dst_rect->h != src_rect->h)) {
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// Create command list.
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#if OMV_GPU_NEMA_MM_STATIC
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nema_buffer_t bo = {
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.size = sizeof(NEMA_BUFFER),
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.base_virt = NEMA_BUFFER,
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.base_phys = (uint32_t) NEMA_BUFFER,
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};
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nema_cmdlist_t cl = nema_cl_create_prealloc(&bo);
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#else
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nema_cmdlist_t cl = nema_cl_create_sized(OMV_GPU_NEMA_BUFFER_SIZE);
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#endif
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// Bind command list.
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nema_cl_bind_circular(&cl);
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nema_tex_mode_t blit_mode;
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if (hint & IMAGE_HINT_BILINEAR) {
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blit_mode = NEMA_FILTER_BL;
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} else {
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blit_mode = NEMA_FILTER_PS;
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}
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// Set up destination texture.
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nema_tex_format_t dst_pixfmt = omv_gpu_pixfmt(dst_img->pixfmt);
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nema_bind_dst_tex((uintptr_t) dst_img->data, dst_rect->w, dst_rect->h, dst_pixfmt, -1);
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// Set up source texture.
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nema_tex_format_t src_pixfmt = omv_gpu_pixfmt(src_img->pixfmt);
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nema_bind_src_tex((uintptr_t) src_img->data, src_rect->w, src_rect->h, src_pixfmt, -1, blit_mode);
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// Configure operations.
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nema_set_blend_blit(NEMA_BL_SRC);
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nema_set_clip(0, 0, dst_rect->w, dst_rect->h);
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nema_blit_rect_fit(0, 0, dst_rect->w, dst_rect->h);
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// Flush source image
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SCB_CleanDCache_by_Addr(src_img->data, image_size(src_img));
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nema_cl_submit(&cl);
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nema_cl_wait(&cl);
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#if !OMV_GPU_NEMA_MM_STATIC
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nema_cl_destroy(&cl);
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#endif
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// Invalidate the destination image.
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SCB_InvalidateDCache_by_Addr(dst_img->data, image_size(dst_img));
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} else {
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return -1;
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}
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OMV_PROFILE_PRINT();
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return 0;
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}
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#else
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int omv_gpu_draw_image(image_t *src_img,
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rectangle_t *src_rect,
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image_t *dst_img,
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@ -79,9 +174,11 @@ int omv_gpu_draw_image(image_t *src_img,
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}
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#endif
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DMA2D_HandleTypeDef dma2d = {};
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dma2d.Instance = DMA2D;
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DMA2D_HandleTypeDef dma2d = {
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.Instance = DMA2D,
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.Init.ColorMode = DMA2D_OUTPUT_RGB565,
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.Init.OutputOffset = dst_img->w - dst_rect->w,
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};
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if (dst_img->pixfmt != src_img->pixfmt) {
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dma2d.Init.Mode = DMA2D_M2M_PFC;
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@ -97,9 +194,6 @@ int omv_gpu_draw_image(image_t *src_img,
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}
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#endif
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dma2d.Init.ColorMode = DMA2D_OUTPUT_RGB565;
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dma2d.Init.OutputOffset = dst_img->w - dst_rect->w;
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HAL_DMA2D_Init(&dma2d);
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dma2d.LayerCfg[0].InputOffset = dst_img->w - dst_rect->w;
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@ -245,4 +339,5 @@ int omv_gpu_draw_image(image_t *src_img,
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OMV_PROFILE_PRINT();
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return 0;
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}
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#endif // (OMV_GPU_ENABLE == 1)
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#endif // OMV_GPU_NEMA
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#endif // OMV_GPU_ENABLE
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@ -58,6 +58,7 @@ CFLAGS += -D$(MCU) \
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-DHSE_VALUE=$(OMV_HSE_VALUE)\
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-DOMV_VTOR_BASE=$(OMV_FIRM_ADDR) \
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-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
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-DOMV_NOSYS_STUBS_ENABLE=1 \
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-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
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$(OMV_BOARD_CFLAGS)
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@ -125,6 +126,7 @@ OMV_CFLAGS += -I$(TOP_DIR)/$(MLX90641_DIR)/include/
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OMV_CFLAGS += -I$(TOP_DIR)/$(PIXART_DIR)/include/
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OMV_CFLAGS += -I$(TOP_DIR)/$(DISPLAY_DIR)/include/
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OMV_CFLAGS += -I$(TOP_DIR)/$(LIBPDM_DIR)/
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OMV_CFLAGS += -I$(TOP_DIR)/$(NEMA_DIR)/include
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ifeq ($(OMV_ENABLE_UVC), 1)
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UVC_CFLAGS := $(CFLAGS) $(HAL_CFLAGS)
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@ -189,6 +191,7 @@ FIRM_OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/common/, \
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file_utils.o \
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mp_utils.o \
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omv_csi.o \
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nosys_stubs.o \
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)
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FIRM_OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/sensors/, \
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@ -652,6 +655,10 @@ ifeq ($(MICROPY_PY_AUDIO), 1)
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LIBS += $(TOP_DIR)/$(LIBPDM_DIR)/libPDMFilter_CM7_GCC_wc32.a
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endif
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),n6))
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LIBS += $(TOP_DIR)/$(NEMA_DIR)/lib/libnemagfx-$(CPU)+fp.a
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endif
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#------------- ML libraries ----------------#
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ifeq ($(MICROPY_PY_ML_TFLM), 1)
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OMV_CFLAGS += -I$(BUILD)/$(TENSORFLOW_DIR)/
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@ -640,8 +640,36 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) {
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__HAL_RCC_DMA2D_FORCE_RESET();
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__HAL_RCC_DMA2D_RELEASE_RESET();
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__HAL_RCC_DMA2D_CLK_DISABLE();
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__HAL_RCC_DMA2D_CLK_SLEEP_DISABLE();
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}
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#if defined(GPU2D)
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void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d) {
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__HAL_RCC_GPU2D_FORCE_RESET();
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__HAL_RCC_GPU2D_RELEASE_RESET();
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__HAL_RCC_GPU2D_CLK_ENABLE();
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__HAL_RCC_GPU2D_CLK_SLEEP_ENABLE();
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}
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void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d) {
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__HAL_RCC_GPU2D_CLK_DISABLE();
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__HAL_RCC_GPU2D_CLK_SLEEP_DISABLE();
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}
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#endif
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#if defined(GFXMMU)
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void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) {
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__HAL_RCC_GFXMMU_CLK_ENABLE();
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__HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE();
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}
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void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) {
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__HAL_RCC_GFXMMU_CLK_DISABLE();
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__HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE();
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}
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#endif
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#if (OMV_JPEG_CODEC_ENABLE == 1)
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void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) {
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__HAL_RCC_JPEG_CLK_ENABLE();
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167
src/omv/ports/stm32/stm32_nema.c
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167
src/omv/ports/stm32/stm32_nema.c
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@ -0,0 +1,167 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* STM32 Nema HAL layer.
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*/
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#include <stdlib.h>
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#include STM32_HAL_H
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#include "omv_boardconfig.h"
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#if (OMV_GPU_NEMA == 1)
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#include "omv_common.h"
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#include "nema_core.h"
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#include "nema_sys_defs.h"
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#ifndef OMV_GPU_NEMA_RING_SIZE
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#define OMV_GPU_NEMA_RING_SIZE 1024
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#endif
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volatile static int last_cl_id;
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static GPU2D_HandleTypeDef gpu2d = { 0 };
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static nema_ringbuffer_t ring_buf = {{0}};
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#if OMV_GPU_NEMA_MM_STATIC
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uint8_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(RING_BUFFER[OMV_GPU_NEMA_RING_SIZE], 32), ".dma_buffer");
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#endif
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int32_t nema_sys_init(void) {
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// Initialize GPU2D
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gpu2d.Instance = GPU2D;
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HAL_GPU2D_Init(&gpu2d);
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// Configure and enable texture cache
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HAL_ICACHE_DeInit();
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HAL_ICACHE_Disable();
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HAL_ICACHE_ConfigAssociativityMode(ICACHE_4WAYS);
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HAL_ICACHE_Enable();
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// Allocate ring buffer.
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#if OMV_GPU_NEMA_MM_STATIC
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ring_buf.bo.fd = 0;
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ring_buf.bo.size = sizeof(RING_BUFFER);
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ring_buf.bo.base_virt = RING_BUFFER;
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ring_buf.bo.base_phys = (uint32_t) RING_BUFFER;
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#else
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ring_buf.bo = nema_buffer_create(OMV_GPU_NEMA_RING_SIZE);
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#endif
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// Initialize ring buffer.
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if (nema_rb_init(&ring_buf, 1) != 0) {
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return -1;
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}
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NVIC_SetPriority(GPU2D_IRQn, IRQ_PRI_GPU);
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NVIC_EnableIRQ(GPU2D_IRQn);
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NVIC_SetPriority(GPU2D_ER_IRQn, IRQ_PRI_GPU);
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NVIC_EnableIRQ(GPU2D_ER_IRQn);
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return 0;
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}
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int nema_wait_irq_cl(int cl_id) {
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while (last_cl_id < cl_id) {
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__WFI();
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}
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return 0;
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}
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int nema_wait_irq_brk(int brk_id) {
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while (nema_reg_read(GPU2D_BREAKPOINT) == 0U) {
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__WFI();
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}
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return 0;
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}
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uint32_t nema_reg_read(uint32_t reg) {
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return HAL_GPU2D_ReadRegister(&gpu2d, reg);
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}
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void nema_reg_write(uint32_t reg, uint32_t value) {
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HAL_GPU2D_WriteRegister(&gpu2d, reg, value);
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}
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nema_buffer_t nema_buffer_create(int size) {
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nema_buffer_t bo = {
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.base_virt = nema_host_malloc(size),
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.base_phys = (uint32_t) bo.base_virt,
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.size = size,
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};
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return bo;
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}
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nema_buffer_t nema_buffer_create_pool(int pool, int size) {
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return nema_buffer_create(size);
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}
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void *nema_buffer_map(nema_buffer_t *bo) {
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return bo->base_virt;
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}
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void nema_buffer_unmap(nema_buffer_t *bo) {
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UNUSED(bo);
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}
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void nema_buffer_destroy(nema_buffer_t *bo) {
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nema_host_free(bo->base_virt);
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}
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uintptr_t nema_buffer_phys(nema_buffer_t *bo) {
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return bo->base_phys;
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}
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void nema_buffer_flush(nema_buffer_t *bo) {
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#if !OMV_GPU_NEMA_MM_STATIC
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SCB_CleanInvalidateDCache_by_Addr((uint32_t *) bo->base_virt, bo->size);
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#endif
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}
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void nema_host_free(void *ptr) {
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if (ptr) {
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free(ptr);
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}
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}
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void *nema_host_malloc(unsigned size) {
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return malloc(size);
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}
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int nema_mutex_lock(int mutex_id) {
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return 0;
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}
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int nema_mutex_unlock(int mutex_id) {
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return 0;
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}
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void GPU2D_IRQHandler(void) {
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HAL_GPU2D_IRQHandler(&gpu2d);
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}
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void GPU2D_ER_IRQHandler(void) {
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HAL_GPU2D_ER_IRQHandler(&gpu2d);
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}
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void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *gpu2d, uint32_t CmdListID) {
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last_cl_id = CmdListID;
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}
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#endif // OMV_GPU_NEMA
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