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Merge pull request #725 from openmv/config_clock
Move clock config to board files.
This commit is contained in:
commit
f11daf34ac
@ -177,7 +177,6 @@ void SystemInit(void)
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void SystemClock_Config(void)
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{
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uint32_t flash_latency;
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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#if defined(MCU_SERIES_H7)
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@ -222,64 +221,51 @@ void SystemClock_Config(void)
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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#if defined (STM32F407xx) // 168MHz/48MHz
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flash_latency = FLASH_LATENCY_5;
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RCC_OscInitStruct.PLL.PLLM = 12;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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#elif defined (STM32F427xx)// 192MHz/48MHz
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flash_latency = FLASH_LATENCY_7;
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RCC_OscInitStruct.PLL.PLLM = 12;
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RCC_OscInitStruct.PLL.PLLN = 384;
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RCC_OscInitStruct.PLL.PLLQ = 8;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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#elif defined (STM32F765xx)// 216MHz/48MHz
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flash_latency = FLASH_LATENCY_7;
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RCC_OscInitStruct.PLL.PLLM = 12;
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RCC_OscInitStruct.PLL.PLLN = 432;
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RCC_OscInitStruct.PLL.PLLQ = 9;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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#elif defined (STM32H743xx)// 480MHz/48MHz
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//PLL1 48MHz for USB, SDMMC and FDCAN
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flash_latency = FLASH_LATENCY_2;
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RCC_OscInitStruct.PLL.PLLM = 3;
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RCC_OscInitStruct.PLL.PLLN = 240;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 20;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M;
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RCC_OscInitStruct.PLL.PLLN = OMV_OSC_PLL1N;
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RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;
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RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P;
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#if defined(OMV_OSC_PLL1R)
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RCC_OscInitStruct.PLL.PLLR = OMV_OSC_PLL1R;
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#endif
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#if defined(OMV_OSC_PLL1VCI)
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RCC_OscInitStruct.PLL.PLLRGE = OMV_OSC_PLL1VCI;
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#endif
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#if defined(OMV_OSC_PLL1VCO)
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RCC_OscInitStruct.PLL.PLLVCOSEL = OMV_OSC_PLL1VCO;
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#endif
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#if defined(OMV_OSC_PLL1FRAC)
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RCC_OscInitStruct.PLL.PLLFRACN = OMV_OSC_PLL1FRAC;
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#endif
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if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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// Initialization Error
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__fatal_error("HAL_RCC_OscConfig");
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}
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#if defined(STM32H743xx)
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// PLL2 200MHz for FMC and QSPI.
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PeriphClkInitStruct.PLL2.PLL2M = 3;
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PeriphClkInitStruct.PLL2.PLL2N = 100;
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PeriphClkInitStruct.PLL2.PLL2P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 2;
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PeriphClkInitStruct.PLL2.PLL2R = 2;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
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#if defined(OMV_OSC_PLL2M)
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PeriphClkInitStruct.PLL2.PLL2M = OMV_OSC_PLL2M;
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PeriphClkInitStruct.PLL2.PLL2N = OMV_OSC_PLL2N;
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PeriphClkInitStruct.PLL2.PLL2P = OMV_OSC_PLL2P;
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PeriphClkInitStruct.PLL2.PLL2Q = OMV_OSC_PLL2Q;
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PeriphClkInitStruct.PLL2.PLL2R = OMV_OSC_PLL2R;
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PeriphClkInitStruct.PLL2.PLL2RGE = OMV_OSC_PLL2VCI;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = OMV_OSC_PLL2VCO;
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PeriphClkInitStruct.PLL2.PLL2FRACN = OMV_OSC_PLL2FRAC;
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#endif
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// PLL3 160MHz for ADC and SPI123
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PeriphClkInitStruct.PLL3.PLL3M = 3;
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PeriphClkInitStruct.PLL3.PLL3N = 80;
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PeriphClkInitStruct.PLL3.PLL3P = 2;
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PeriphClkInitStruct.PLL3.PLL3Q = 2;
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PeriphClkInitStruct.PLL3.PLL3R = 2;
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PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2;
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PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
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PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
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#if defined(OMV_OSC_PLL3M)
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PeriphClkInitStruct.PLL3.PLL3M = OMV_OSC_PLL3M;
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PeriphClkInitStruct.PLL3.PLL3N = OMV_OSC_PLL3N;
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PeriphClkInitStruct.PLL3.PLL3P = OMV_OSC_PLL3P;
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PeriphClkInitStruct.PLL3.PLL3Q = OMV_OSC_PLL3Q;
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PeriphClkInitStruct.PLL3.PLL3R = OMV_OSC_PLL3R;
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PeriphClkInitStruct.PLL3.PLL3RGE = OMV_OSC_PLL3VCI;
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PeriphClkInitStruct.PLL3.PLL3VCOSEL = OMV_OSC_PLL3VCO;
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PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC;
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#endif
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#if defined(STM32H743xx) || defined(STM32H747xx)
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_FDCAN
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|RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2
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|RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2
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@ -327,7 +313,7 @@ void SystemClock_Config(void)
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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#endif
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if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK) {
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if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, OMV_FLASH_LATENCY) != HAL_OK) {
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// Initialization Error
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__fatal_error("HAL_RCC_ClockConfig");
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}
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@ -27,6 +27,13 @@
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#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_2)
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#define OMV_BOOTLDR_LED_PORT (GPIOC)
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//PLL1 168MHz/48MHz
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1N (336)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (7)
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_5)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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#define OMV_BOOT_ORIGIN 0x08000000
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#define OMV_BOOT_LENGTH 16K
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@ -53,6 +53,13 @@
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 16
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//PLL1 192MHz/48MHz
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1N (384)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (8)
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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@ -53,6 +53,14 @@
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 16
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//PLL1 216MHz/48MHz
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1N (432)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (9)
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#define OMV_OSC_PLL1R (2)
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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@ -66,6 +66,38 @@
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 16
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (3)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (3)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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@ -67,6 +67,38 @@
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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//PLL1 48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (3)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (3)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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