drivers/genx320: Add Prophesee genx320 stm32f7 driver.

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Kwabena W. Agyeman 2024-09-22 16:58:40 -07:00
parent 7736b0a4cf
commit fa00c38780
11 changed files with 19983 additions and 0 deletions

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To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "[]"
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Copyright Prophesee S.A.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
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###
# Copyright (c) Prophesee S.A.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
# Unless required by applicable law or agreed to in writing, software distributed under the License is distributed
# on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and limitations under the License.
###
SRCS = $(wildcard src/*.c)
OBJS = $(addprefix $(BUILD)/, $(SRCS:.c=.o))
OBJ_DIRS = $(sort $(dir $(OBJS)))
all: | $(OBJ_DIRS) $(OBJS)
$(OBJ_DIRS):
$(MKDIR) -p $@
$(BUILD)/%.o : %.c
$(ECHO) "CC $<"
$(CC) $(CFLAGS) -c -o $@ $<
$(BUILD)/%.o : %.s
$(ECHO) "AS $<"
$(AS) $(AFLAGS) $< -o $@
-include $(OBJS:%.o=%.d)

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/**
******************************************************************************
* @attention
* Copyright (c) Prophesee S.A.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and limitations under the License.
*
******************************************************************************
*/
#ifndef INC_AER_H_
#define INC_AER_H_
#define __AER_Y(__VAL__) ((__VAL__ ) & 0x1FFU)
#define __AER_X(__VAL__) ((__VAL__ >> 9) & 0x1FFU)
#define __AER_P(__VAL__) ((__VAL__ >> 18 ) & 0x1U)
#endif /* INC_AER_H_ */

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/**
******************************************************************************
* @attention
* Copyright (c) Prophesee S.A.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and limitations under the License.
*
******************************************************************************
*/
#ifndef INC_EVT_2_0_H_
#define INC_EVT_2_0_H_
#define __EVT20_TYPE(__VAL__) ((__VAL__ >> 28)& 0xFU)
#define __EVT20_TS(__VAL__) ((__VAL__ >> 22) & 0xF3U)
#define __EVT20_X(__VAL__) ((__VAL__ >> 11) & 0x7FFU)
#define __EVT20_Y(__VAL__) ((__VAL__ ) & 0x7FFU)
#define __EVT20_TIME_HIGH(__VAL__) ((__VAL__ ) & 0xFFFFFFFU)
#define TD_LOW 0x0U /*!< EVT2.0 TD Event, Decrease in illumination */
#define TD_HIGH 0x1U /*!< EVT2.0 TD Event, Increase in illumination */
#define EV_TIME_HIGH 0x8U /*!< Timer High bits */
#define EXT_TRIGGER 0xAU /*!< External triggers */
#define OTHERS 0xEU /*!< To be used in extension in the event types */
#define CONTINUED 0xFU /*!< Extra data to previous events */
#endif /* INC_EVT_2_0_H_ */

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/**
******************************************************************************
* @file firmware.h
* @author PSEE Applications Team
* @brief RISC-V Firmwares
*
******************************************************************************
* @attention
* Copyright (c) Prophesee S.A.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and limitations under the License.
*
******************************************************************************
*/
#ifndef APPLICATION_USER_FIRMWARE_H_
#define APPLICATION_USER_FIRMWARE_H_
/* Standard Includes */
#include <stdint.h>
/* User Includes */
#include "psee_genx320.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Low power wakeup application Firmware */
extern const size_t fw_esp_wakeup_size;
extern const Firmware fw_esp_wakeup[];
/* Led tracking application Firmware */
extern const size_t fw_led_tracking_size;
extern const Firmware fw_led_tracking[];
#ifdef __cplusplus
}
#endif
#endif /* APPLICATION_USER_FIRMWARE_H_ */

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/**********************************************************************************************************************
* Copyright (c) Prophesee S.A. *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 *
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed *
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and limitations under the License. *
**********************************************************************************************************************/
#ifndef __GENX320_H
#define __GENX320_H
/* Standard Includes */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <math.h>
/* User Includes*/
#include "genx320_all_pub_registers.h"
#include "psee_issd.h"
/* Sensor I2C Address */
#define I2C_ADDRESS 0x3C
/* Sensor Chip ID */
#define SAPHIR_CHIP_ID 0x0014
#define SAPHIR_ES_ID 0x30501C01
#define SAPHIR_MP_ID 0xB0602003
/* Memory Bank Defines */
#define IMEM_START (0x00200000UL)
#define DMEM_START (0x00300000UL)
#define MEM_BANK_SELECT (0x0000F800UL)
#define MEM_BANK_MEM0 (0x0000F900UL)
/* RISC-V Defines */
#define RISC_BOOT_DONE 0x0ABCDEF
/**
* @brief RISCV FW status structures definition
*/
typedef enum
{
fw_OK = 0U,
fw_Error_InvalidSize = 1U,
fw_Error_InvalidPointer = 2U,
fw_Flash_Error = 3U,
fw_Start_Error = 4U,
fw_Flashed_Already = 5U
} FW_StatusTypeDef;
/**
* @brief Shadow register status structures definition
*/
typedef enum
{
shadow_valid = 0U,
shadow_not_valid = 01
} Shadow_StatusTypeDef;
/**
* @brief Structure to hold the parameters for the bias
*/
typedef struct {
uint8_t pr;
uint8_t fo;
uint8_t fes;
uint8_t hpf;
uint8_t diff_on;
uint8_t diff;
uint8_t diff_off;
uint8_t inv;
uint8_t refr;
uint8_t invp;
uint8_t req_pu;
uint8_t sm_pdy;
}BIAS_Params_t;
/**
* @brief Structure to hold the border value for the Activity Map
*/
typedef struct {
uint16_t x0;
uint16_t x1;
uint16_t x2;
uint16_t x3;
uint16_t x4;
uint16_t y0;
uint16_t y1;
uint16_t y2;
uint16_t y3;
uint16_t y4;
}AM_Borders_t;
/**
* @brief Structure to hold the risc-v firmware
*/
typedef struct {
uint32_t address;
uint32_t value;
} Firmware;
/**
* @brief Structure to hold AFK Invalidation
*/
typedef struct {
uint32_t df_wait_time;
uint32_t df_timeout;
} Invalidation;
/**
* @brief Structure to hold the sensor clock frequencies
*/
typedef struct {
uint32_t in_freq;
uint32_t sys_freq;
uint32_t evt_icn_freq;
uint32_t cpu_ss_freq;
uint32_t pll_in_freq;
uint32_t pll_vco_freq;
uint32_t phy_freq;
uint32_t mipi_freq;
uint32_t esc_freq;
} clk_freq_dict;
/**
* @brief Sensor Boot mode structure definition
*/
typedef enum
{
ROM_BOOT = 0U,
IMEM_BOOT = 1U
} Boot_Mode;
/**
* @brief Enum to hold the parameters for the bias
*/
typedef enum {
PR,
FO,
FES,
HPF,
DIFF_ON,
DIFF,
DIFF_OFF,
INV,
REFR,
INVP,
REQ_PU,
SM_PDY,
} BIAS_Name_t;
/* Constants/Variables to hold default bias */
extern const BIAS_Params_t genx320es_default_biases;
extern const BIAS_Params_t genx320mp_default_biases;
extern BIAS_Params_t genx320_default_biases;
/* Variable to hold default borders for Activity map */
extern AM_Borders_t genx320mp_default_am_borders;
/* ISSD sequences. */
extern const struct issd dcmi_evt;
extern const struct issd dcmi_histo;
extern const struct issd *current_issd;
/* Variable to hold the current boot mode */
extern Boot_Mode genx320_boot_mode;
/* Sensor Register Manipulation Functions */
extern void psee_sensor_read(uint16_t register_address, uint32_t *buf);
extern void psee_sensor_write(uint16_t register_address, uint32_t register_data);
/* Sensor Bring Up Functions */
extern void psee_sensor_init(const struct issd *);
extern void psee_sensor_destroy(const struct issd *);
extern void psee_sensor_start(const struct issd *);
extern void psee_sensor_stop(const struct issd *);
extern Boot_Mode psee_detect_boot_mode();
extern const struct issd *psee_open_evt();
extern void psee_sensor_set_bias(BIAS_Name_t bias, uint32_t val);
extern void psee_sensor_set_biases(const BIAS_Params_t *bias);
extern void psee_sensor_set_CPI_EVT20();
extern void psee_sensor_set_CPI_HISTO();
extern void psee_sensor_set_flip(uint32_t flip_x, uint32_t flip_y);
extern void psee_sensor_powerdown();
/* Operating Mode Control Functions */
extern void psee_PM3C_config();
extern void psee_PM2_config();
/* Firmware flashing functions */
extern FW_StatusTypeDef psee_write_firmware(const Firmware *firmwareArray, uint32_t n_bytes);
extern FW_StatusTypeDef psee_start_firmware(Boot_Mode boot_mode);
extern FW_StatusTypeDef psee_reset_firmware(Boot_Mode boot_mode);
/* Mailbox Communication Functions */
extern uint32_t psee_get_mbx_cmd_ptr();
extern uint32_t psee_get_mbx_misc();
extern uint32_t psee_get_mbx_status_ptr();
extern void psee_set_mbx_cmd_ptr(uint32_t val);
extern void psee_set_mbx_misc(uint32_t val);
extern void psee_set_mbx_status_ptr(uint32_t val);
/* ROI Access Functions */
extern void psee_write_ROI_X(uint32_t offset, uint32_t val);
extern void psee_write_ROI_Y(uint32_t offset, uint32_t val);
extern void psee_write_ROI_CTRL(uint32_t val);
/* RISC-V Debugger Functions */
extern uint32_t psee_mbx_read_uint32();
extern void psee_decode_debugger();
extern uint32_t psee_sensor_read_dmem(uint32_t address);
extern uint32_t psee_sensor_read_imem(uint32_t address);
/* Statistics Register Read Functions */
extern void psee_read_ro_lp_evt_cnt(uint32_t *p_data);
extern uint32_t psee_read_ro_evt_cd_cnt();
extern uint32_t psee_read_afk_flicker_evt_cnt();
extern uint32_t psee_read_afk_total_evt_cnt();
/* Activity Map Configuration Functions */
extern void psee_configure_activity_map();
extern void psee_set_default_XY_borders(AM_Borders_t *border);
/* AFK Configuration Functions */
extern void psee_enable_afk(uint16_t min_freq, uint16_t max_freq);
extern void psee_disable_afk();
#endif

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/**********************************************************************************************************************
* Copyright (c) Prophesee S.A. *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 *
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed *
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and limitations under the License. *
**********************************************************************************************************************/
#ifndef __PSEE_ISSD_H
#define __PSEE_ISSD_H
#include <stdint.h>
#include <stddef.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
enum op_id {
READ,
WRITE,
DELAY
};
struct read_op {
uint16_t addr;
uint32_t data;
uint32_t mask;
};
struct write_op {
uint16_t addr;
uint32_t data;
};
struct delay_op {
uint32_t us;
};
struct reg_op {
enum op_id op;
union {
struct read_op read;
struct write_op write;
struct delay_op delay;
} args;
};
struct sequence {
const struct reg_op *ops;
size_t len;
};
struct issd {
const struct sequence init;
const struct sequence start;
const struct sequence stop;
const struct sequence destroy;
};
#endif

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/**********************************************************************************************************************
* Copyright (c) Prophesee S.A. *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 *
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed *
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and limitations under the License. *
* *
* This is an automatically generated file *
**********************************************************************************************************************/
#ifndef __ISSD_CPI_H
#define __ISSD_CPI_H
#include "psee_issd.h"
static const struct reg_op dcmi_init_seq[] = {
{.op = WRITE, .args = {.write = {0x9008UL, 0x00000320}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
{.op = WRITE, .args = {.write = {0x9008UL, 0x00010320}} }, // saphir/ro/time_base_ctrl Write fields: time_base_srst
{.op = WRITE, .args = {.write = {0x020CUL, 0x00000015}} }, // saphir/rtc_clk_ctrl Write fields: rtc_clk_en|rtc_clk_div
{.op = WRITE, .args = {.write = {0x0204UL, 0x00004D6C}} }, // saphir/sys_clk_ctrl Write fields: sys_clk_auto_mode
{.op = WRITE, .args = {.write = {0x0210UL, 0x00000C00}} }, // saphir/evt_icn_clk_ctrl Write fields: ro_clk_en|esp_clk_en
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A0}} }, // saphir/ro/time_base_ctrl Write fields: us_counter_max
{.op = WRITE, .args = {.write = {0x00B8UL, 0x00000040}} }, // saphir/sram_initn Write fields: cpi_initn
{.op = WRITE, .args = {.write = {0x00C0UL, 0x00000078}} }, // saphir/sram_pd1 Write fields: cpi_pd
{.op = WRITE, .args = {.write = {0x800CUL, 0x0001040A}} }, // saphir/cpi/packet_time_control Write fields: packet_period
{.op = WRITE, .args = {.write = {0x8008UL, 0x00000400}} }, // saphir/cpi/packet_size_control Write fields: packet_size
{.op = WRITE, .args = {.write = {0x8010UL, 0x00000140}} }, // saphir/cpi/frame_size_control Write fields: frame_size
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001EFA1}} }, // saphir/cpi/pipeline_control Write fields: enable|clk_out_en|clk_control_inversion|packet_fixed_size_enable|packet_fixed_rate_enable|frame_fixed_size_enable|output_if_mode|output_data_format|output_width|clk_out_gating_enable
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FFA1}} }, // saphir/cpi/pipeline_control Write fields: clk_out_gating_enable
{.op = WRITE, .args = {.write = {0xE000UL, 0x00000005}} }, // saphir/nfl/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0xC000UL, 0x00000005}} }, // saphir/afk/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0xD000UL, 0x00000005}} }, // saphir/stc/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0x6000UL, 0x00000005}} }, // saphir/erc/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0x60A0UL, 0x00000000}} }, // saphir/erc/delay_fifo_flush_and_bypass Write fields: en
{.op = WRITE, .args = {.write = {0x704CUL, 0x000007D0}} }, // saphir/edf/output_interface_control
{.op = WRITE, .args = {.write = {0x7100UL, 0x00010280}} }, // saphir/edf/external_output_adapter Write fields: qos_timeout|atomic_qos_mode
{.op = WRITE, .args = {.write = {0x7044UL, 0x00000002}} }, // saphir/edf/control Write fields: format|endianness
{.op = WRITE, .args = {.write = {0x7048UL, 0x00000000}} }, // saphir/edf/event_injection Write fields: sysmon_end_of_frame_en
{.op = WRITE, .args = {.write = {0x7000UL, 0x00000001}} }, // saphir/edf/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A4}} }, // saphir/ro/time_base_ctrl Write fields: time_base_mode|external_mode|external_mode_enable|us_counter_max
{.op = WRITE, .args = {.write = {0x9000UL, 0x00000200}} }, // saphir/ro/readout_ctrl Write fields: ro_digital_pipe_en
{.op = WRITE, .args = {.write = {0x001CUL, 0x00000004}} }, // saphir/dig_soft_reset Write fields: analog_rstn
{.op = WRITE, .args = {.write = {0xA000UL, 0x00000406}} }, // saphir/ldo/bg Write fields: bg_en|bg_buf_en|bg_bypass|bg_chk|bg_adj
{.op = WRITE, .args = {.write = {0xA01CUL, 0x0007641F}} }, // saphir/ldo/pmu Write fields: pmu_icgm_en|pmu_v2i_en|pmu_v2i_cal_en|mipi_v2i_en
{.op = WRITE, .args = {.write = {0xB030UL, 0x00000010}} }, // saphir/mipi_csi/power Write fields: cur_en
{.op = WRITE, .args = {.write = {0x004CUL, 0x00204E22}} }, // saphir/adc_control Write fields: adc_clk_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0xA01CUL, 0x0007E41F}} }, // saphir/ldo/pmu Write fields: pmu_v2i_en|pmu_v2i_adj|pmu_v2i_cal_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = READ, .args = {.read = {0xA01CUL, 0x0014E41F}} }, // saphir/ldo/pmu Read fields: pmu_v2i_cal_done_dyn
{.op = WRITE, .args = {.write = {0x004CUL, 0x00204E20}} }, // saphir/adc_control Write fields: adc_clk_en
{.op = WRITE, .args = {.write = {0x1218UL, 0x00000111}} }, // saphir/bias/bgen_cgm_sub Write fields: bias_cgm_sub_en
{.op = WRITE, .args = {.write = {0x1218UL, 0x00000111}} }, // saphir/bias/bgen_cgm_sub Write fields: bias_cgm_sub_trim
{.op = WRITE, .args = {.write = {0x1218UL, 0x00000111}} }, // saphir/bias/bgen_cgm_sub Write fields: bias_cgm_sub_slp_ctl
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1220UL, 0x00000001}} }, // saphir/bias/bgen_cc_en Write fields: bias_cc_hv_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0xA008UL, 0x00008085}} }, // saphir/ldo/ldo_lv Write fields: ldo_lv_en|ldo_lv_climit_en|ldo_lv_climit|ldo_lv_ind_en|ldo_lv_adj|ldo_lv_ind_vth_ok|ldo_lv_ind_vth_bo
{.op = WRITE, .args = {.write = {0xA004UL, 0x00008025}} }, // saphir/ldo/ldo_hv Write fields: ldo_hv_en|ldo_hv_climit_en|ldo_hv_climit|ldo_hv_ind_en|ldo_hv_adj|ldo_hv_ind_vth_ok|ldo_hv_ind_vth_bo
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x0070UL, 0x0000055F}} }, // saphir/cp_ctrl Write fields: cp_en|cp_clk_en|cp_adj|cp_cfly|cp_mphase|cp_clk_divider
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1220UL, 0x00000003}} }, // saphir/bias/bgen_cc_en Write fields: bias_cc_lv_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1208UL, 0x00000030}} }, // saphir/bias/bgen_ctrl Write fields: bias_rstn_hv|bias_rstn_lv
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000420}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000400}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn|px_roi_halt_programming
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000822}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x3000UL, 0x00000000}} }, // saphir/roi/td_roi_y00
{.op = WRITE, .args = {.write = {0x3004UL, 0x00000000}} }, // saphir/roi/td_roi_y01
{.op = WRITE, .args = {.write = {0x3008UL, 0x00000000}} }, // saphir/roi/td_roi_y02
{.op = WRITE, .args = {.write = {0x300CUL, 0x00000000}} }, // saphir/roi/td_roi_y03
{.op = WRITE, .args = {.write = {0x3010UL, 0x00000000}} }, // saphir/roi/td_roi_y04
{.op = WRITE, .args = {.write = {0x3014UL, 0x00000000}} }, // saphir/roi/td_roi_y05
{.op = WRITE, .args = {.write = {0x3018UL, 0x00000000}} }, // saphir/roi/td_roi_y06
{.op = WRITE, .args = {.write = {0x301CUL, 0x00000000}} }, // saphir/roi/td_roi_y07
{.op = WRITE, .args = {.write = {0x3020UL, 0x00000000}} }, // saphir/roi/td_roi_y08
{.op = WRITE, .args = {.write = {0x3024UL, 0x00000000}} }, // saphir/roi/td_roi_y09
{.op = WRITE, .args = {.write = {0x3028UL, 0x00000000}} }, // saphir/roi/td_roi_y10
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000822}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x2000UL, 0x00000000}} }, // saphir/roi/td_roi_x00 Write fields: effective
{.op = WRITE, .args = {.write = {0x2004UL, 0x00000000}} }, // saphir/roi/td_roi_x01 Write fields: effective
{.op = WRITE, .args = {.write = {0x2008UL, 0x00000000}} }, // saphir/roi/td_roi_x02 Write fields: effective
{.op = WRITE, .args = {.write = {0x200CUL, 0x00000000}} }, // saphir/roi/td_roi_x03 Write fields: effective
{.op = WRITE, .args = {.write = {0x2010UL, 0x00000000}} }, // saphir/roi/td_roi_x04 Write fields: effective
{.op = WRITE, .args = {.write = {0x2014UL, 0x00000000}} }, // saphir/roi/td_roi_x05 Write fields: effective
{.op = WRITE, .args = {.write = {0x2018UL, 0x00000000}} }, // saphir/roi/td_roi_x06 Write fields: effective
{.op = WRITE, .args = {.write = {0x201CUL, 0x00000000}} }, // saphir/roi/td_roi_x07 Write fields: effective
{.op = WRITE, .args = {.write = {0x2020UL, 0x00000000}} }, // saphir/roi/td_roi_x08 Write fields: effective
{.op = WRITE, .args = {.write = {0x2024UL, 0x00000000}} }, // saphir/roi/td_roi_x09 Write fields: effective
{.op = WRITE, .args = {.write = {0x3000UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y00 Write fields: effective
{.op = WRITE, .args = {.write = {0x3004UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y01 Write fields: effective
{.op = WRITE, .args = {.write = {0x3008UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y02 Write fields: effective
{.op = WRITE, .args = {.write = {0x300CUL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y03 Write fields: effective
{.op = WRITE, .args = {.write = {0x3010UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y04 Write fields: effective
{.op = WRITE, .args = {.write = {0x3014UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y05 Write fields: effective
{.op = WRITE, .args = {.write = {0x3018UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y06 Write fields: effective
{.op = WRITE, .args = {.write = {0x301CUL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y07 Write fields: effective
{.op = WRITE, .args = {.write = {0x3020UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y08 Write fields: effective
{.op = WRITE, .args = {.write = {0x3024UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y09 Write fields: effective
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000822}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1000UL, 0x0301003D}} }, // saphir/bias/bias_pr_hv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1004UL, 0x03010027}} }, // saphir/bias/bias_fo_hv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1008UL, 0x0101003F}} }, // saphir/bias/bias_fes_hv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1100UL, 0x03010000}} }, // saphir/bias/bias_hpf_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1104UL, 0x01090018}} }, // saphir/bias/bias_diff_on_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1108UL, 0x01010033}} }, // saphir/bias/bias_diff_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x110CUL, 0x01090013}} }, // saphir/bias/bias_diff_off_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1110UL, 0x01010039}} }, // saphir/bias/bias_inv_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1114UL, 0x03010052}} }, // saphir/bias/bias_refr_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1118UL, 0x03010042}} }, // saphir/bias/bias_invp_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x111CUL, 0x03000074}} }, // saphir/bias/bias_req_pu_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1120UL, 0x010000A4}} }, // saphir/bias/bias_sm_pdy_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1208UL, 0x00000035}} }, // saphir/bias/bgen_ctrl Write fields: burst_transfer_hv_bank_0|burst_transfer_lv_bank_0
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} } // saphir/roi_ctrl Write fields: roi_td_en
};
static const struct reg_op dcmi_start_seq[] = {
{.op = WRITE, .args = {.write = {0x9028UL, 0x00000000}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A5}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x002CUL, 0x0022C724}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000C02}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn
{.op = DELAY, .args = {.delay = {1000}} } // us
};
static const struct reg_op dcmi_stop_seq[] = {
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn
{.op = WRITE, .args = {.write = {0x002CUL, 0x00200624}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
{.op = WRITE, .args = {.write = {0x9028UL, 0x00000002}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable|lp_keep_th
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A4}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FFA2}} }, // saphir/cpi/pipeline_control Write fields: enable|drop_nbackpressure|hot_disable_enable
{.op = READ, .args = {.read = {0x8004UL, 0x00000002}} }, // saphir/cpi/pipeline_status Read fields: busy
{.op = DELAY, .args = {.delay = {1000}} } // us
};
static const struct reg_op dcmi_destroy_seq[] = {
};
const struct issd dcmi_evt = {
.init = {
.ops = dcmi_init_seq,
.len = ARRAY_SIZE(dcmi_init_seq)},
.start = {
.ops = dcmi_start_seq,
.len = ARRAY_SIZE(dcmi_start_seq)},
.stop = {
.ops = dcmi_stop_seq,
.len = ARRAY_SIZE(dcmi_stop_seq)},
.destroy = {
.ops = dcmi_destroy_seq,
.len = ARRAY_SIZE(dcmi_destroy_seq)},
};
#endif

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