The SPI fifo triggers a request when it has 4-bytes of data allowing
for more efficent bus usage. The same technique is used on the H7
to reduce system bus matrix resources.
On the STM32N6 the DMA memory meant to be used with the SPI bus is
in the low-performance memory domain. Moving the DMA buffers and
linked list buffers there reduces the AHB cycle time by the DMA
controller making it more stable.