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4 Commits

Author SHA1 Message Date
Kwabena W Agyeman
73a7ee1cf5
Merge 70136c4f32 into daf26f9fc8 2025-11-02 16:44:51 +01:00
Ibrahim Abdelkader
daf26f9fc8
Merge pull request #2909 from kwagyeman/kwabena/fix_nn_caching_issue
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lib/stai: Fix STAI NPU memory allocation.
2025-11-02 17:37:09 +02:00
Kwabena W. Agyeman
30da5a062f lib/stai: Fix STAI NPU memory allocation.
The ST Neural ART code generator marks the HyperRAM mpool as cacheable
(CACHEABLE_ON), which causes the NPU stream engines to issue cacheable
accesses. However, the N6 memory subsystem does not support cacheable
accesses to internal memories, only external ones. Because of this,
relocating the HyperRAM region to internal memory results in invalid
access behavior: only base addresses are updated during relocation, not
the cacheable attributes.

In short, buffers generated for HyperRAM must remain in external memory.
Marking HyperRAM as non-cacheable is a possible workaround, but may
reduce performance if buffers are placed in AXI RAM instead.

Forcing the ext_ram_sz allocation to 1MB ensures that the ext_ram_sz
is allocated in SDRAM.
2025-11-01 18:28:22 -07:00
Kwabena W. Agyeman
70136c4f32 ports/stm32: Enable N6 ethernet. 2025-10-28 23:19:55 -07:00
4 changed files with 13 additions and 1 deletions

View File

@ -102,6 +102,9 @@
#define OMV_RCC_IC10_CLKDIV (8)
// Used by MicroPython for slow peripherals.
#define OMV_RCC_IC12_SOURCE (RCC_ICCLKSOURCE_PLL1)
#define OMV_RCC_IC12_CLKDIV (8)
#define OMV_RCC_IC14_SOURCE (RCC_ICCLKSOURCE_PLL1)
#define OMV_RCC_IC14_CLKDIV (8)

View File

@ -49,6 +49,10 @@
#include "ll_aton_caches_interface.h"
#include "ll_aton_reloc_network.h"
// Due to limitations with the STM32N6 NPU design, the ext_ram_sz memory pool
// must be in external SDRAM and not in internal SRAM. Forcing a minimum of a
// 1MB allocation ensures that the ext_ram_sz buffer ends up in SDRAM.
#define AI_MIN_EXT_RAM_SZ (1048576)
#define AI_RELOC_ALIGNMENT (32)
typedef struct ml_backend_state {
@ -132,6 +136,10 @@ int ml_backend_init_model(py_ml_model_obj_t *model) {
return -1;
}
if (rt.ext_ram_sz) {
rt.ext_ram_sz = OMV_MAX(rt.ext_ram_sz, AI_MIN_EXT_RAM_SZ);
}
// Allocate executable memory.
state->exec_ram_size = OMV_ALIGN_TO(rt.rt_ram_xip, AI_RELOC_ALIGNMENT);
state->exec_ram_addr = m_new(uint8_t, state->exec_ram_size + AI_RELOC_ALIGNMENT);

View File

@ -37,7 +37,7 @@
#define MICROPY_BANNER_NAME_AND_VERSION "OpenMV " OPENMV_GIT_TAG "; MicroPython " MICROPY_GIT_TAG
#define MICROPY_BOARD_FATAL_ERROR __fatal_error
#define MICROPY_HW_DMA_ENABLE_AUTO_TURN_OFF (0)
#define MICROPY_HW_ETH_DMA_ATTRIBUTE __attribute__((aligned(16384), section(".dma_buffer")));
//#define MICROPY_HW_ETH_DMA_ATTRIBUTE __attribute__((aligned(16384), section(".dma_buffer")));
void __fatal_error(const char *);

View File

@ -288,6 +288,7 @@ void HAL_MspInit(void) {
{ RIF_MASTER_INDEX_SDMMC1, RIF_RISC_PERIPH_INDEX_SDMMC1 },
{ RIF_MASTER_INDEX_SDMMC2, RIF_RISC_PERIPH_INDEX_SDMMC2 },
{ RIF_MASTER_INDEX_DCMIPP, RIF_RISC_PERIPH_INDEX_DCMIPP },
{ RIF_MASTER_INDEX_ETH1, RIF_RISC_PERIPH_INDEX_ETH1 },
{ RIF_MASTER_INDEX_NONE, RIF_RISC_PERIPH_INDEX_CSI },
{ RIF_MASTER_INDEX_NONE, RIF_RISC_PERIPH_INDEX_ADC12 },
};