[System_Config.RTSS_HP_SRAM_MRAM] core_clock=400e6 axi0_port=Sram axi1_port=OffChipFlash Sram_clock_scale=0.762 Sram_burst_length=8 Sram_read_latency=29 Sram_write_latency=29 OffChipFlash_clock_scale=0.121 OffChipFlash_burst_length=16 OffChipFlash_read_latency=60 OffChipFlash_write_latency=60 [System_Config.RTSS_HP_SRAM_OSPI] core_clock=400e6 axi0_port=Sram axi1_port=OffChipFlash Sram_clock_scale=0.762 Sram_burst_length=8 Sram_read_latency=29 Sram_write_latency=29 OffChipFlash_clock_scale=0.052 OffChipFlash_burst_length=16 OffChipFlash_read_latency=108 OffChipFlash_write_latency=108 [System_Config.RTSS_HE_SRAM_MRAM] core_clock=160e6 axi0_port=Sram axi1_port=OffChipFlash Sram_clock_scale=1.0 Sram_burst_length=8 Sram_read_latency=13 Sram_write_latency=13 OffChipFlash_clock_scale=0.303 OffChipFlash_burst_length=16 OffChipFlash_read_latency=24 OffChipFlash_write_latency=24 [System_Config.RTSS_HE_SRAM_Only] core_clock=160e6 axi0_port=Sram axi1_port=OnChipFlash Sram_clock_scale=1.0 Sram_burst_length=8 Sram_read_latency=13 Sram_write_latency=13 OnChipFlash_clock_scale=1.0 OnChipFlash_burst_length=8 OnChipFlash_read_latency=13 OnChipFlash_write_latency=13 [System_Config.RTSS_HP_DTCM_Only] core_clock=400e6 axi0_port=Sram axi1_port=OnChipFlash Sram_clock_scale=0.889 Sram_burst_length=32 Sram_read_latency=5 Sram_write_latency=5 OnChipFlash_clock_scale=0.889 OnChipFlash_burst_length=32 OnChipFlash_read_latency=5 OnChipFlash_write_latency=5 [System_Config.RTSS_HE_DTCM_Only] core_clock=160e6 axi0_port=Sram axi1_port=OnChipFlash Sram_clock_scale=0.889 Sram_burst_length=32 Sram_read_latency=5 Sram_write_latency=5 OnChipFlash_clock_scale=0.889 OnChipFlash_burst_length=32 OnChipFlash_read_latency=5 OnChipFlash_write_latency=5 [System_Config.RTSS_HP_DTCM_MRAM] core_clock=400e6 axi0_port=Sram axi1_port=OffChipFlash Sram_clock_scale=0.889 Sram_burst_length=32 Sram_read_latency=5 Sram_write_latency=5 OffChipFlash_clock_scale=0.118 OffChipFlash_burst_length=64 OffChipFlash_read_latency=60 OffChipFlash_write_latency=60 [System_Config.RTSS_HP_DTCM_Modem] core_clock=400e6 axi0_port=Sram axi1_port=OffChipFlash Sram_clock_scale=0.889 Sram_burst_length=32 Sram_read_latency=5 Sram_write_latency=5 OffChipFlash_clock_scale=0.200 OffChipFlash_burst_length=64 OffChipFlash_read_latency=53 OffChipFlash_write_latency=53 [System_Config.RTSS_HP_DTCM_SRAM] core_clock=400e6 axi0_port=Sram axi1_port=Dram Sram_clock_scale=1.0 Sram_burst_length=16 Sram_read_latency=5 Sram_write_latency=5 Dram_clock_scale=0.762 Dram_burst_length=32 Dram_read_latency=29 Dram_write_latency=29 ; ----------------------------------------------------------------------------- ; Memory Mode ; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software ; The non-SRAM memory is assumed to be read-only ; This is appropriate for the SRAM_MRAM or DTCM_MRAM configs [Memory_Mode.Shared_Sram] const_mem_area=Axi1 arena_mem_area=Axi0 cache_mem_area=Axi0 ; DTCM Cache ; This is appropriate for the DTCM_SRAM configs [Memory_Mode.Dtcm_Cache] const_mem_area=Axi1 arena_mem_area=Axi1 cache_mem_area=Axi0