/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. * Use, distribution and modification of this code is permitted under the * terms stated in the Alif Semiconductor Software License Agreement * * You should have received a copy of the Alif Semiconductor Software * License Agreement with this file. If not, please write to: * contact@alifsemi.com, or visit: https://alifsemi.com/license * */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H // MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] // Configuration settings for Driver_MRAM in component ::Drivers:MRAM #define RTE_MRAM 1 #if RTE_MRAM #define RTE_MRAM_SIZE 0x00580000 #endif // MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] // CPI (Camera) [Driver_CPI] // Configuration settings for Driver_CPI in component ::Drivers:CPI #define RTE_CPI 1 #if RTE_CPI // CPI interrupt priority <0-255> // Defines CPI interrupt priority. // Default: 0 #define RTE_CPI_IRQ_PRI 0 // CPI CSI halt enable/disable // <0=> disable // <1=> enable // Defines CPI CSI halt enable/disable. // Default: 0 #define RTE_CPI_CSI_HALT 0 // CPI Row roundup // <0=> disable // <1=> enable // Defines CPI row roundup to 64 bit. // Default: 0 #define RTE_CPI_ROW_ROUNDUP 0 // CPI FIFO read watermark // Defines FIFO read watermark. // Default: 0x8 #define RTE_CPI_FIFO_READ_WATERMARK 0x8 // CPI FIFO write watermark // Defines CPI FIFO write watermark. // Default: 0x18 #define RTE_CPI_FIFO_WRITE_WATERMARK 0x18 // MT9M114 [Driver_MT9M114] // Enable/Disable MT9M114 camera sensor // <0=> disable // <1=> enable // define if to enable or disable MT9M114 camera sensor // default: disable #define RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE 0 #if (RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE) // Select camera MT9M114 pixel clock polarity // <0=> not invert camera pixclk // <1=> invert camera pixclk // Defines camera MT9M114 pixel clock polarity // Default: not invert camera pixclk #define RTE_MT9M114_CAMERA_SENSOR_CPI_PIXEL_CLK_POL 0 // Select camera MT9M114 HSYNC polarity // <0=> not invert HSYNC input // <1=> invert HSYNC input // Defines camera MT9M114 HSYNC polarity // Default: not invert HSYNC input #define RTE_MT9M114_CAMERA_SENSOR_CPI_HSYNC_POL 0 // Select camera MT9M114 VSYNC polarity // <0=> not invert VSYNC input // <1=> invert VSYNC input // Defines camera MT9M114 VSYNC polarity // Default: not invert VSYNC input #define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_POL 0 // Select camera MT9M114 VSYNC wait // <0=> vsync wait disable // <1=> vsync wait enable // Defines camera MT9M114 VSYNC wait // Default: vsync wait disable #define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_WAIT 0 // Select camera MT9M114 VSYNC mode // <0=> sync enable // <1=> data enable // Defines camera MT9M114 VSYNC mode // Default: sync enable #define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_MODE 0 // Select video data mode // <0=> 1 bit // <1=> 2 bit // <2=> 4 bit // <3=> 8 bit // <4=> 16 bit // Defines video data mode // Default: 8 bit #define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MODE 3 // Select Data Endianness // <0=> LSB First // <1=> MSB First // Select MSB/LSB // Default: LSB #define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_ENDIANNESS 0 // Select CODE10ON8 // <0=> Disable // <1=> Enable // Defines transfer 10-bit coding over 8-bit data bus. // Default: 8 bit #define RTE_MT9M114_CAMERA_SENSOR_CPI_CODE10ON8 0 // Select camera MT9M114 data mask // <0=> 16 bit // <1=> 10 bit // <2=> 12 bit // <3=> 14 bit // Defines camera MT9M114 data mask // Default: 10 bit #define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MASK 1 // select MT9M114 frame height // defines select MT9M114 frame height. // default: 480 #define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_HEIGHT 480 // select MT9M114 frame width // defines select MT9M114 frame width. // default: 640 #define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_WIDTH 640 // RTE_MT9M114_CAMERA_SENSOR_CPI_I2C_INSTANCE // Defines camera sensor MT9M114 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_CPI_I2C_INSTANCE 1 #endif // MT9M114 [Driver_MT9M114] #endif // CPI (Camera) [Driver_CPI] // LPCPI (Camera) [Driver_LPCPI] // Configuration settings for Driver_LPCPI in component ::Drivers:LPCPI #define RTE_LPCPI 0 #if RTE_LPCPI // LPCPI interrupt priority <0-255> // Defines LPCPI interrupt priority. // Default: 0 #define RTE_LPCPI_IRQ_PRI 0 // LPCPI Row roundup // <0=> disable // <1=> enable // Defines LPCPI row roundup to 64 bit. // Default: 0 #define RTE_LPCPI_ROW_ROUNDUP 0 // LPCPI FIFO read watermark // Defines LPCPI FIFO read watermark. // Default: 0x8 #define RTE_LPCPI_FIFO_READ_WATERMARK 0x8 // LPCPI FIFO write watermark // Defines LPCPI FIFO write watermark. // Default: 0x18 #define RTE_LPCPI_FIFO_WRITE_WATERMARK 0x18 // MT9M114 [Driver_MT9M114] // Enable/Disable MT9M114 camera sensor // <0=> disable // <1=> enable // define if to enable or disable MT9M114 camera sensor // default: disable #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE 1 #if (RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE) // Select camera MT9M114 pixel clock polarity // <0=> not invert camera pixclk // <1=> invert camera pixclk // Defines camera MT9M114 pixel clock polarity // Default: not invert camera pixclk #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_PIXEL_CLK_POL 0 // Select camera MT9M114 HSYNC polarity // <0=> not invert HSYNC input // <1=> invert HSYNC input // Defines camera MT9M114 HSYNC polarity // Default: not invert HSYNC input #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_HSYNC_POL 0 // Select camera MT9M114 VSYNC polarity // <0=> not invert VSYNC input // <1=> invert VSYNC input // Defines camera MT9M114 VSYNC polarity // Default: not invert VSYNC input #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_POL 0 // Select camera MT9M114 VSYNC wait // <0=> vsync wait disable // <1=> vsync wait enable // Defines camera MT9M114 VSYNC wait // Default: vsync wait disable #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_WAIT 0 // Select camera MT9M114 VSYNC mode // <0=> sync enable // <1=> data enable // Defines camera MT9M114 VSYNC mode // Default: sync enable #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_MODE 0 // Select video data mode // <0=> 1 bit // <1=> 2 bit // <2=> 4 bit // <3=> 8 bit // Defines video data mode // Default: 8 bit #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_MODE 3 // Select Data Endianness // <0=> LSB First // <1=> MSB First // Select MSB/LSB // Default: LSB #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_ENDIANNESS 0 // Select CODE10ON8 // <0=> Disable // <1=> Enable // Defines transfer 10-bit coding over 8-bit data bus. // Default: 8 bit #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_CODE10ON8 0 // select MT9M114 frame height // defines select MT9M114 frame height. // default: 480 #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_HEIGHT 480 // select MT9M114 frame width // defines select MT9M114 frame width. // default: 640 #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_WIDTH 640 // RTE_MT9M114_CAMERA_SENSOR_LPCPI_I2C_INSTANCE // Defines camera sensor MT9M114 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_LPCPI_I2C_INSTANCE 1 #endif // MT9M114 [Driver_MT9M114] #endif // LPCPI (Camera) [Driver_LPCPI] // MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] // Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 #define RTE_MIPI_CSI2 1 #if RTE_MIPI_CSI2 // CSI pixel clock select // <0=> 400 MHz clock source (PLL_CLK1/2) // <1=> 480 MHz clock source (PLL_CLK3) // Defines CSI pixel clock select // Default: 400 MHz clock source (PLL_CLK1/2) #define RTE_CSI2_PIX_CLK_SEL 0 // select IPI mode // <0=> camera mode // <1=> controller mode // defines select IPI mode // default: camera mode #define RTE_MIPI_CSI2_IPI_MODE 0 // select memory flush // <0=> manual // <1=> auto // defines select memory flush // default: auto #define RTE_MIPI_CSI2_MEMFLUSH 1 // select sync event mode // <0=> not trigger by frame start // <1=> trigger by frame start // defines select sync event mode // default : not trigger by frame start #define RTE_MIPI_CSI2_SYNC_ET_MODE 0 // select sync event select // <0=> auto // <1=> programmed // defines select sync event select // default : programmed #define RTE_MIPI_CSI2_SYNC_ET_SEL 1 // embedded packets for IPI synchronization events // <0=> disable // <1=> enable // define if want to use embedded packets for IPI synchronization events // default: disable #define RTE_MIPI_CSI2_EN_EMBEDDED 0 // blanking packets for IPI synchronization events // <0=> disable // <1=> enable // define if want to use blanking packets for IPI synchronization events // default: disable #define RTE_MIPI_CSI2_EN_BLANKING 0 // null packets for IPI synchronization events // <0=> disable // <1=> enable // define if want to use null packets for IPI synchronization events // default: disable #define RTE_MIPI_CSI2_EN_NULL 0 // line start packets for IPI synchronization events // <0=> disable // <1=> enable // define if want to use line start packets for IPI synchronization events // default: disable #define RTE_MIPI_CSI2_EN_LINE_START 0 // video packets for IPI synchronization events // <0=> disable // <1=> enable // define if want to use video packets for IPI synchronization events // default: enable #define RTE_MIPI_CSI2_EN_VIDEO 1 // datatype to overwrite // select CSI2 Data type to overwrite // <24=> YUV420_8 // <25=> YUV420_10 // <26=> YUV420_8_LEGACY // <28=> YUV420_8_SHIFT // <29=> YUV420_10_SHIFT // <30=> YUV422_8 // <31=> YUV422_10 // <32=> RGB444 // <33=> RGB555 // <34=> RGB565 // <35=> RGB666 // <36=> RGB888 // <40=> RAW6 // <41=> RAW7 // <42=> RAW8 // <43=> RAW10 // <44=> RAW12 // <45=> RAW14 // <46=> RAW16 // <48=> USER_DEFINED_1 // <49=> USER_DEFINED_2 // <50=> USER_DEFINED_3 // <51=> USER_DEFINED_4 // <52=> USER_DEFINED_5 // <53=> USER_DEFINED_6 // <54=> USER_DEFINED_7 // <55=> USER_DEFINED_8 // defines select CSI2 Data type to be overwrite // default: RAW10 #define RTE_MIPI_CSI2_EN_DT 43 // datatype to overwrite with programmed datatype // define if want to use programmed datatype ignoring datatype of the header // default: 0 #define RTE_MIPI_CSI2_EN_DT_OVERWRITE 0 // Horizontal Synchronism Active Time range <0-2047> // Defines possible range for selecting horizontal sync active time // Default: 0 #define RTE_MIPI_CSI2_IPI_HSA_TIME 5 // Horizontal Synchronism back porch Time range <0-2047> // Defines possible range for selecting horizontal sync back porch time // Default: 0 #define RTE_MIPI_CSI2_IPI_HBP_TIME 10 // Horizontal sync delay Time range <0-2047> // Defines possible range for selecting horizontal sync delay time // Default: 560 #define RTE_MIPI_CSI2_IPI_HSD_TIME 280 // Horizontal Active Time range <0-2047> // Defines possible range for selecting horizontal active time // Default: 560 #define RTE_MIPI_CSI2_IPI_HACTIVE_TIME 560 // Vertical sync active period range <0-511> // Defines possible range for selecting vertical sync active period // Default: 0 #define RTE_MIPI_CSI2_IPI_VSA_LINE 4 // Vertical back porch period range <0-511> // Defines possible range for selecting vertical back porch period // Default: 0 #define RTE_MIPI_CSI2_IPI_VBP_LINE 4 // Vertical front porch period range <0-511> // Defines possible range for selecting vertical front porch period // Default: 0 #define RTE_MIPI_CSI2_IPI_VFP_LINE 4 // Vertical active period range <0-8191> // Defines possible range for selecting vertical active period // Default: 560 #define RTE_MIPI_CSI2_IPI_VACTIVE_LINE 560 // CSI2 interrupt priority <0-255> // Defines CSI2 interrupt priority. // Default: 0 #define RTE_MIPI_CSI2_IRQ_PRI 0 // ARX3A0 [Driver_ARX3A0] // Enable/Disable ARX3A0 camera sensor // <0=> disable // <1=> enable // define if to enable or disable ARX3A0 camera sensor // default: enable #define RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE 1 #if (RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE) // Select camera ARX3A0 frame per second // <5=> 5 FPS // <40=> 40 FPS // <60=> 60 FPS // <90=> 90 FPS // Defines camera ARX3A0 frame per second // Default: 90 FPS #define RTE_ARX3A0_CAMERA_SENSOR_CSI_CFG_FPS 90 // Select camera ARX3A0 frequency // Defines camera ARX3A0 frequency // Default: 400000000 #define RTE_ARX3A0_CAMERA_SENSOR_CSI_FREQ 400000000 // select ARX3A0 CSI2 Data type // defines select CSI2 Data type // default: 43(RAW10) #define RTE_ARX3A0_CAMERA_SENSOR_CSI_DATA_TYPE 43 // select ARX3A0 number of lanes in DPHY // defines select ARX3A0 number of lanes in DPHY. // default: 2 two lane #define RTE_ARX3A0_CAMERA_SENSOR_CSI_N_LANES 2 // select ARX3A0 virtual channel ID // defines select ARX3A0 virtual channel ID. // default: 0 #define RTE_ARX3A0_CAMERA_SENSOR_CSI_VC_ID 0 // select ARX3A0 override CPI color mode // defines select ARX3A0 override CPI color mode. // default: 1 (Ensable) #define RTE_ARX3A0_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 // select ARX3A0 CPI color mode // defines select ARX3A0 CPI color mode. // default: 2 (IPI-16 RAW 8) #define RTE_ARX3A0_CAMERA_SENSOR_CPI_COLOR_MODE 2 // select ARX3A0 frame height // defines select ARX3A0 frame height. // default: 560 #define RTE_ARX3A0_CAMERA_SENSOR_FRAME_HEIGHT 560 // select ARX3A0 frame width // defines select ARX3A0 frame width. // default: 560 #define RTE_ARX3A0_CAMERA_SENSOR_FRAME_WIDTH 560 // Select camera sensor ARX3A0 CSI clock source division [Divisor] <2-511> // Defines camera sensor ARX3A0 CSI clock source division // Default: 20 #define RTE_ARX3A0_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 // Select camera sensor ARX3A0 reset pin number // Defines camera sensor ARX3A0 reset pin number // Default: 1 #define RTE_ARX3A0_CAMERA_SENSOR_RESET_PIN_NO 1 // Select camera sensor ARX3A0 reset GPIO port // Defines camera sensor ARX3A0 reset GPIO port // Default: 9 #define RTE_ARX3A0_CAMERA_SENSOR_RESET_GPIO_PORT 9 // Select camera sensor ARX3A0 power pin number // Defines camera sensor ARX3A0 power pin number // Default: 5 #define RTE_ARX3A0_CAMERA_SENSOR_POWER_PIN_NO 5 // Select camera sensor ARX3A0 power GPIO port // Defines camera sensor ARX3A0 power GPIO port // Default: 7 #define RTE_ARX3A0_CAMERA_SENSOR_POWER_GPIO_PORT 7 // RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE // Defines camera sensor ARX3A0 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE 1 #endif // ARX3A0 [Driver_ARX3A0] // AR0144 [Driver_AR0144] // Enable/Disable AR0144 camera sensor // <0=> disable // <1=> enable // define if to enable or disable AR0144 camera sensor // default: enable #define RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE 1 #if (RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE) // Select camera AR0144 frequency // Defines camera AR0144 frequency // Default: 225000000 #define RTE_AR0144_CAMERA_SENSOR_CSI_FREQ 225000000 // select AR0144 CSI2 Data type // defines select CSI2 Data type // default: 44(RAW12) #define RTE_AR0144_CAMERA_SENSOR_CSI_DATA_TYPE 44 // select AR0144 number of lanes in DPHY // defines select AR0144 number of lanes in DPHY. // default: 2 two lane #define RTE_AR0144_CAMERA_SENSOR_CSI_N_LANES 2 // select AR0144 virtual channel ID // defines select AR0144 virtual channel ID. // default: 0 #define RTE_AR0144_CAMERA_SENSOR_CSI_VC_ID 0 // select AR0144 override CPI color mode // defines select AR0144 override CPI color mode. // default: 1 (Ensable) #define RTE_AR0144_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 // select AR0144 CPI color mode // defines select AR0144 CPI color mode. // default: 2 (IPI-16 RAW 8) #define RTE_AR0144_CAMERA_SENSOR_CPI_COLOR_MODE 2 // select AR0144 frame height // defines select AR0144 frame height. // default: 560 #define RTE_AR0144_CAMERA_SENSOR_FRAME_HEIGHT 800 // select AR0144 frame width // defines select AR0144 frame width. // default: 560 #define RTE_AR0144_CAMERA_SENSOR_FRAME_WIDTH 1280 // Select camera sensor AR0144 CSI clock source division [Divisor] <2-511> // Defines camera sensor AR0144 CSI clock source division // Default: 20 #define RTE_AR0144_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 // Select camera sensor AR0144 reset pin number // Defines camera sensor AR0144 reset pin number // Default: 5 #define RTE_AR0144_CAMERA_SENSOR_RESET_PIN_NO 1 // Select camera sensor AR0144 reset GPIO port // Defines camera sensor AR0144 reset GPIO port // Default: 4 #define RTE_AR0144_CAMERA_SENSOR_RESET_GPIO_PORT 9 // Select camera sensor AR0144 power pin number // Defines camera sensor AR0144 power pin number // Default: 5 #define RTE_AR0144_CAMERA_SENSOR_POWER_PIN_NO 5 // Select camera sensor AR0144 power GPIO port // Defines camera sensor AR0144 power GPIO port // Default: 7 #define RTE_AR0144_CAMERA_SENSOR_POWER_GPIO_PORT 7 // RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE // Defines camera sensor AR0144 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE 1 #endif // AR0114 [Driver_AR0114] // AR0145 [Driver_AR0145] // Enable/Disable AR0145 camera sensor // <0=> disable // <1=> enable // define if to enable or disable AR0145 camera sensor // default: enable #define RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE 1 #if (RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE) // Select camera AR0145 frequency // Defines camera AR0145 frequency // Default: 400000000 #define RTE_AR0145_CAMERA_SENSOR_CSI_FREQ 400000000 // select AR0145 CSI2 Data type // defines select CSI2 Data type // default: 0x2A(RAW8) #define RTE_AR0145_CAMERA_SENSOR_CSI_DATA_TYPE 0x2A // select AR0145 number of lanes in DPHY // defines select AR0145 number of lanes in DPHY. // default: 2 two lane #define RTE_AR0145_CAMERA_SENSOR_CSI_N_LANES 2 // select AR0145 virtual channel ID // defines select AR0145 virtual channel ID. // default: 0 #define RTE_AR0145_CAMERA_SENSOR_CSI_VC_ID 0 // select AR0145 override CPI color mode // defines select AR0145 override CPI color mode. // default: 0 #define RTE_AR0145_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 // select AR0145 CPI color mode // defines select AR0145 CPI color mode. // default: 0 #define RTE_AR0145_CAMERA_SENSOR_CPI_COLOR_MODE 0 // select AR0145 Image configuration // Defines camera sensor AR0145 Image configuration // <0=> 1280x800_Full_1M // <1=> 640x400_YSum2_XBin2 // <2=> 640x400_YSkip2_XSkip2 // <3=> 320x200_YSkip2_XSkip2 // Default: 0 #define RTE_AR0145_CAMERA_SENSOR_IMAGE_CONFIG 0 // Select camera sensor AR0145 CSI clock source division [Divisor] <2-511> // Defines camera sensor AR0145 CSI clock source division // Default: 16 #define RTE_AR0145_CAMERA_SENSOR_CSI_CLK_SCR_DIV 16 // Select camera sensor AR0145 reset pin number // Defines camera sensor AR0145 reset pin number // Default: 1 #define RTE_AR0145_CAMERA_SENSOR_RESET_PIN_NO 1 // Select camera sensor AR0145 reset GPIO port // Defines camera sensor AR0145 reset GPIO port // Default: 9 #define RTE_AR0145_CAMERA_SENSOR_RESET_GPIO_PORT 9 // Select camera sensor AR0145 power pin number // Defines camera sensor AR0145 power pin number // Default: 5 #define RTE_AR0145_CAMERA_SENSOR_POWER_PIN_NO 5 // Select camera sensor AR0145 power GPIO port // Defines camera sensor AR0145 power GPIO port // Default: 7 #define RTE_AR0145_CAMERA_SENSOR_POWER_GPIO_PORT 7 // RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE // Defines camera sensor AR0145 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE 1 #endif // AR0145 [Driver_AR0145] // MT9M114_MIPI [Driver_MT9M114_MIPI] // Enable/Disable MT9M114 MIPI camera sensor // <0=> disable // <1=> enable // define if to enable or disable MT9M114 MIPI camera sensor // default: enable #define RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE 1 #if (RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE) // Select camera MT9M114 MIPI frequency // Defines camera MT9M114 MIPI frequency // Default: 296000000 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_FREQ 320000000 // select MT9M114 Image configuration // Defines camera sensor MT9M114 Image configuration // <0=> 1288x728_RAW10 // <1=> 1280x720_RAW8 // <2=> 1280x720_RGB565 // <3=> 640x480_RGB565 // <4=> 320x240_RGB565 // <5=> 320x320_RGB565 // Default: 0 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 2 // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane #define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_N_LANES 1 // select MT9M114 MIPI virtual channel ID // defines select MT9M114 MIPI virtual channel ID. // default: 0 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_VC_ID 0 // select MT9M114 MIPI override CPI color mode // defines select MT9M114 MIPI override CPI color mode. // default: 0 (Disable) #define RTE_MT9M114_CAMERA_SENSOR_MIPI_OVERRIDE_CPI_COLOR_MODE 0 // select MT9M114 MIPI CPI color mode // defines select MT9M114 MIPI CPI color mode. // default: 0 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_CPI_COLOR_MODE 0 // Select camera sensor MT9M114 MIPI CSI clock source division [Divisor] <2-511> // Defines camera sensor MT9M114 MIPI CSI clock source division // Default: 20 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 // Select camera sensor MT9M114 MIPI reset pin number // Defines camera sensor MT9M114 MIPI reset pin number // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_RESET_PIN_NO 1 // Select camera sensor MT9M114 MIPI reset GPIO port // Defines camera sensor MT9M114 MIPI reset GPIO port // Default: 9 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_RESET_GPIO_PORT 9 // Select camera sensor MT9M114 MIPI power pin number // Defines camera sensor MT9M114 MIPI power pin number // Default: 5 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_POWER_PIN_NO 5 // Select camera sensor MT9M114 MIPI power GPIO port // Defines camera sensor MT9M114 MIPI power GPIO port // Default: 7 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_POWER_GPIO_PORT 7 // RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE // Defines camera sensor MT9M114 MIPI i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE 1 #endif // MT9M114_MIPI [Driver_MT9M114_MIPI] // HM0360_MIPI [Driver_HM0360_MIPI] // Enable/Disable HM0360 MIPI camera sensor // <0=> disable // <1=> enable // define if to enable or disable HM0360 MIPI camera sensor // default: enable #define RTE_HM0360_CAMERA_SENSOR_ENABLE 1 #if (RTE_HM0360_CAMERA_SENSOR_ENABLE) // Select camera HM0360 frequency // Defines camera HM0360 frequency // Default: 176000000 #define RTE_HM0360_CAMERA_SENSOR_CSI_FREQ 176000000 // Select camera HM0360 frame per second // <30=> 30 FPS // <60=> 60 FPS // Defines camera HM0360 frame per second // Default: 60 FPS #define RTE_HM0360_CAMERA_SENSOR_CSI_CFG_FPS 60 // Select camera HM0360 context select // <0=> CONTEXT_A // <1=> CONTEXT_B // Defines camera HM0360 context select // Default: 0 #define RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL 0 // select HM0360 CSI2 Data type // defines select CSI2 Data type // default: 42(RAW8) #define RTE_HM0360_CAMERA_SENSOR_CSI_DATA_TYPE 42 // select HM0360 number of lanes in DPHY // defines select HM0360 number of lanes in DPHY. // default: 1 one lane #define RTE_HM0360_CAMERA_SENSOR_CSI_N_LANES 1 // select HM0360 virtual channel ID // defines select HM0360 virtual channel ID. // default: 0 #define RTE_HM0360_CAMERA_SENSOR_CSI_VC_ID 0 // select HM0360 override CPI color mode // defines select HM0360 override CPI color mode. // default: 0 #define RTE_HM0360_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 // select HM0360 CPI color mode // defines select HM0360 CPI color mode. // default: 0 #define RTE_HM0360_CAMERA_SENSOR_CPI_COLOR_MODE 0 #if (RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL == 0) // select HM0360 frame height // defines select HM0360 frame height. // default: 480 #define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 480 // select HM0360 frame width // defines select HM0360 frame width. // default: 640 #define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 640 #else // select HM0360 frame height // defines select HM0360 frame height. // default: 240 #define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 240 // select HM0360 frame width // defines select HM0360 frame width. // default: 320 #define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 320 #endif // Select camera sensor HM0360 reset pin number // Defines camera sensor HM0360 reset pin number // Default: 1 #define RTE_HM0360_CAMERA_SENSOR_RESET_PIN_NO 1 // Select camera sensor HM0360 reset GPIO port // Defines camera sensor HM0360 reset GPIO port // Default: 9 #define RTE_HM0360_CAMERA_SENSOR_RESET_GPIO_PORT 9 // Select camera sensor HM0360 power pin number // Defines camera sensor HM0360 power pin number // Default: 5 #define RTE_HM0360_CAMERA_SENSOR_POWER_PIN_NO 5 // Select camera sensor HM0360 power GPIO port // Defines camera sensor HM0360 power GPIO port // Default: 7 #define RTE_HM0360_CAMERA_SENSOR_POWER_GPIO_PORT 7 // Select camera sensor HM0360 xsleep pin number // Defines camera sensor HM0360 xsleep pin number // Default: 3 #define RTE_HM0360_CAMERA_SENSOR_XSLEEP_PIN_NO 3 // Select camera sensor HM0360 xsleep GPIO port // Defines camera sensor HM0360 xsleep GPIO port // Default: 6 #define RTE_HM0360_CAMERA_SENSOR_XSLEEP_GPIO_PORT 6 // RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE // Defines camera sensor HM0360 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE 1 #endif // HM0360_MIPI [Driver_HM0360_MIPI] // OV5647_MIPI [Driver_OV5647_MIPI] // Enable/Disable OV5647 MIPI camera sensor // <0=> disable // <1=> enable // define if to enable or disable OV5647 MIPI camera sensor // default: enable #define RTE_OV5647_CAMERA_SENSOR_ENABLE 1 #if (RTE_OV5647_CAMERA_SENSOR_ENABLE) // Select camera OV5647 frequency // Defines camera OV5647 frequency // Default: 158000000 #define RTE_OV5647_CAMERA_SENSOR_CSI_FREQ 158000000 // select OV5647 CSI2 Data type // defines select CSI2 Data type // default: 0x2B (RAW10) #define RTE_OV5647_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B // select OV5647 number of lanes in DPHY // defines select OV5647 number of lanes in DPHY. // default: 2 one lane #define RTE_OV5647_CAMERA_SENSOR_CSI_N_LANES 2 // select OV5647 virtual channel ID // defines select OV5647 virtual channel ID. // default: 0 #define RTE_OV5647_CAMERA_SENSOR_CSI_VC_ID 0 // select OV5647 override CPI color mode // defines select OV5647 override CPI color mode. // default: 1 #define RTE_OV5647_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 // select OV5647 CPI color mode // defines select OV5647 CPI color mode. // default: 2 (IPI-16 RAW 8) #define RTE_OV5647_CAMERA_SENSOR_CPI_COLOR_MODE 2 // select OV5647 frame height // defines select OV5647 frame height. // default: 480 #define RTE_OV5647_CAMERA_SENSOR_FRAME_HEIGHT 480 // select OV5647 frame width // defines select OV5647 frame width. // default: 640 #define RTE_OV5647_CAMERA_SENSOR_FRAME_WIDTH 640 // Select camera sensor OV5647 reset pin number // Defines camera sensor OV5647 reset pin number // Default: 1 #define RTE_OV5647_CAMERA_SENSOR_RESET_PIN_NO 1 // Select camera sensor OV5647 reset GPIO port // Defines camera sensor OV5647 reset GPIO port // Default: 9 #define RTE_OV5647_CAMERA_SENSOR_RESET_GPIO_PORT 9 // Select camera sensor OV5647 i2c instance // Defines camera sensor OV5647 i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // I2C OVER I3C // Default: 1 #define RTE_OV5647_CAMERA_SENSOR_I2C_INSTANCE 1 #endif // OV5647_MIPI [Driver_OV5647_MIPI] #endif // MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] // MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] // Configuration settings for Driver_MIPI_DSI in component ::Drivers:MIPI_DSI #define RTE_MIPI_DSI 1 #if RTE_MIPI_DSI // DPHY PLL input division factor // Defines DPHY PLL input division factor // Default: 3 #define RTE_MIPI_DSI_PLL_INPUT_DIV_FACTOR_N 3 // DSI TX escape clock division value. // Defines DSI TX escape clock division value. // Default: 2 #define RTE_MIPI_DSI_TX_ESC_CLK_DIVISION 2 // DPI Video Mode // <0=> NON_BURST SYNC_PULSES // <1=> NON_BURST SYNC_EVENTS // <2=> BURST MODE // Defines DPI Video Mode // Default:BURST MODE #define RTE_MIPI_DSI_VID_MODE_TYPE 2 // DSI Video number of Chunks // Defines Number of chunks used to transfer single video packet . // Default: 0 #define RTE_MIPI_DSI_VID_NUM_CHUNKS 0 // DSI Size of NULL packet // Defines Size of the NULL packet. // Default: 0 #define RTE_MIPI_DSI_VID_NULL_SIZE 0 // DSI IRQ priority <0-255> // Defines Interrupt priority. // Default: 0 #define RTE_MIPI_DSI_IRQ_PRI 0 // MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] // DSI ILI9806E LCD PANEL // <0=> DISABLE // <1=> ENABLE // Defines DSI ILI9806E LCD PANEL // Default: ENABLE #define RTE_MIPI_DSI_ILI9806E_PANEL 1 #if RTE_MIPI_DSI_ILI9806E_PANEL // DSI ILI9806E panel variant // <0=> E43RB_FW405 // <1=> E43GB_MW405 // <2=> E50RA_MW550 // Defines ILI9806E panel variant // Default: E43RB_FW405 #define RTE_ILI9806E_PANEL_VARIANT 1 #if (RTE_ILI9806E_PANEL_VARIANT == 0) #define RTE_ILI9806E_PANEL_E43RB_FW405_EN 1 #elif (RTE_ILI9806E_PANEL_VARIANT == 1) #define RTE_ILI9806E_PANEL_E43GB_MW405_EN 1 #elif (RTE_ILI9806E_PANEL_VARIANT == 2) #define RTE_ILI9806E_PANEL_E50RA_MW550_EN 1 #endif // ILI9806 LCD panel maximum bitrate in mbps // Defines ILI9806 LCD panel maximum bitrate in mbps. // Default: 500 #define RTE_ILI9806E_PANEL_MAX_BITRATE_MBPS 500 // DSI color mode // <1=> 16bit // <4=> 18bit // <5=> 24bit // Defines Color mode for display panel // Default: 24bit #define RTE_ILI9806E_PANEL_DSI_COLOR_MODE 1 // Number of data lanes // <1=> ONE // <2=> TWO // Defines Number of data lanes // Default: TWO #define RTE_ILI9806E_PANEL_DSI_N_LANES 0x2 // Virtual channel ID // Defines Virtual Channel ID // Default: 0 #define RTE_ILI9806E_PANEL_DSI_VC_ID 0 // ILI9806 LCD panel reset pin number // Defines ILI9806 LCD panel reset pin number. // Default: 5 #define RTE_ILI9806E_PANEL_RESET_PIN_NO 5 // ILI9806 LCD panel reset pin GPIO port number // Defines ILI9806 LCD panel reset pin GPIO port number. // Default: 15 #define RTE_ILI9806E_PANEL_RESET_GPIO_PORT 15 // ILI9806 LCD panel back light pin number // Defines ILI9806 LCD panel back light pin number. // Default: 1 #define RTE_ILI9806E_PANEL_BL_LED_PIN_NO 1 // ILI9806 LCD panel back light pin GPIO port number // Defines ILI9806 LCD panel back light pin GPIO port number. // Default: 6 #define RTE_ILI9806E_PANEL_BL_LED_GPIO_PORT 6 // MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] #if (RTE_ILI9806E_PANEL_E43RB_FW405_EN || RTE_ILI9806E_PANEL_E43GB_MW405_EN) // Panel hsync time in pixels // Defines ILI9806 LCD panel hsync time in pixels. // Default: 4 #define RTE_PANEL_HSYNC_TIME 4 // Panel FW405/MW405 hbp time in pixels // Defines ILI9806 LCD panel hbp time in pixels. // Default: 5 #define RTE_PANEL_HBP_TIME 5 // Panel FW405/MW405 hfp time in pixels // Defines ILI9806 LCD panel hfp time in pixels. // Default: 5 #define RTE_PANEL_HFP_TIME 5 // Panel FW405/MW405 hactive pixels // Defines ILI9806 LCD panel hactive pixels. // Default: 480 #define RTE_PANEL_HACTIVE_TIME 480 // Panel FW405/MW405 vsync time in lines // Defines ILI9806 LCD panel vsync time in lines. // Default: 2 #define RTE_PANEL_VSYNC_LINE 2 // Panel FW405/MW405 vbp time in lines // Defines ILI9806 LCD panel vbp time in lines. // Default: 10 #define RTE_PANEL_VBP_LINE 10 // Panel FW405/MW405 vfp time in lines // Defines ILI9806 LCD panel vfp time in lines. // Default: 10 #define RTE_PANEL_VFP_LINE 10 // Panel FW405/MW405 vactive lines // Defines ILI9806 LCD panel vactive lines. // Default: 800 #define RTE_PANEL_VACTIVE_LINE 800 // MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] // MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] #elif RTE_ILI9806E_PANEL_E50RA_MW550_EN // Panel MW550 hsync time in pixels // Defines ILI9806 LCD panel hsync time in pixels. // Default: 4 #define RTE_PANEL_HSYNC_TIME 4 // Panel MW550 hbp time in pixels // Defines ILI9806 LCD panel hbp time in pixels. // Default: 30 #define RTE_PANEL_HBP_TIME 30 // Panel MW550 hfp time in pixels // Defines ILI9806 LCD panel hfp time in pixels. // Default: 18 #define RTE_PANEL_HFP_TIME 18 // Panel MW550 hactive pixels // Defines ILI9806 LCD panel hactive pixels. // Default: 480 #define RTE_PANEL_HACTIVE_TIME 480 // Panel MW550 vsync time in lines // Defines ILI9806 LCD panel vsync time in lines. // Default: 4 #define RTE_PANEL_VSYNC_LINE 4 // Panel MW550 vbp time in lines // Defines ILI9806 LCD panel vbp time in lines. // Default: 30 #define RTE_PANEL_VBP_LINE 30 // Panel MW550 vfp time in lines // Defines ILI9806 LCD panel vfp time in lines. // Default: 20 #define RTE_PANEL_VFP_LINE 20 // Panel MW550 vactive lines // Defines ILI9806 LCD panel vactive lines. // Default: 854 #define RTE_PANEL_VACTIVE_LINE 854 #endif // MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] // MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] // DSI ILI9488 LCD PANEL // <0=> DISABLE // <1=> ENABLE // Defines DSI ILI9488 LCD PANEL // Default: ENABLE #define RTE_MIPI_DSI_ILI9488_PANEL 1 #if RTE_MIPI_DSI_ILI9488_PANEL // ILI9806 LCD panel maximum bitrate in mbps // Defines ILI9806 LCD panel maximum bitrate in mbps. // Default: 500 #define RTE_ILI9488_PANEL_MAX_BITRATE_MBPS 500 // DSI color mode // <1=> 16bit // <4=> 18bit // Defines Color mode for display panel // Default: 16bit #define RTE_ILI9488_PANEL_DSI_COLOR_MODE 1 // Virtual channel ID // Defines Virtual Channel ID // Default: 0 #define RTE_ILI9488_PANEL_DSI_VC_ID 0 // ILI9488 LCD panel reset pin number // Defines ILI9488 LCD panel reset pin number. // Default: 5 #define RTE_ILI9488_PANEL_RESET_PIN_NO 5 // ILI9488 LCD panel reset pin GPIO port number // Defines ILI9488 LCD panel reset pin GPIO port number. // Default: 15 #define RTE_ILI9488_PANEL_RESET_GPIO_PORT 15 // ILI9488 LCD panel back light pin number // Defines ILI9488 LCD panel back light pin number. // Default: 1 #define RTE_ILI9488_PANEL_BL_LED_PIN_NO 1 // ILI9488 LCD panel back light pin GPIO port number // Defines ILI9488 LCD panel back light pin GPIO port number. // Default: 6 #define RTE_ILI9488_PANEL_BL_LED_GPIO_PORT 6 // Panel hsync time in pixels // Defines ILI9488 LCD panel hsync time in pixels. // Default: 10 #define RTE_ILI9488_PANEL_HSYNC_TIME 10 // Panel ILI9488 hbp time in pixels // Defines ILI9488 LCD panel hbp time in pixels. // Default: 10 #define RTE_ILI9488_PANEL_HBP_TIME 10 // Panel ILI9488 hfp time in pixels // Defines ILI9488 LCD panel hfp time in pixels. // Default: 40 #define RTE_ILI9488_PANEL_HFP_TIME 40 // Panel ILI9488 hactive pixels // Defines ILI9488 LCD panel hactive pixels. // Default: 320 #define RTE_ILI9488_PANEL_HACTIVE_TIME 320 // Panel ILI9488 vsync time in lines // Defines ILI9488 LCD panel vsync time in lines. // Default: 2 #define RTE_ILI9488_PANEL_VSYNC_LINE 2 // Panel ILI9488 vbp time in lines // Defines ILI9488 LCD panel vbp time in lines. // Default: 16 #define RTE_ILI9488_PANEL_VBP_LINE 16 // Panel ILI9488 vfp time in lines // Defines ILI9488 LCD panel vfp time in lines. // Default: 10 #define RTE_ILI9488_PANEL_VFP_LINE 10 // Panel ILI9488 vactive lines // Defines ILI9488 LCD panel vactive lines. // Default: 480 #define RTE_ILI9488_PANEL_VACTIVE_LINE 480 #endif // MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] #endif // MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] #endif // MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] // TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] // Configuration settings for Driver_Touch_Screen in component ::Drivers:touch screen #define RTE_TOUCH_SCREEN 1 #if RTE_TOUCH_SCREEN // GT911 Touch screen // <0=> DISABLE // <1=> ENABLE // Defines GT911 Touch screen // Default: ENABLE #define RTE_GT911 1 #if RTE_GT911 // select active touch points // <1=> 1 // <2=> 2 // <3=> 3 // <4=> 4 // <5=> 5 // defines select active touch points // default: 5 #define RTE_ACTIVE_TOUCH_POINTS 5 // GT911 Touch screen reset pin GPIO port number range <0-15> // Defines GT911 Touch screen reset pin GPIO port number. // Default: 4 #define RTE_GT911_TOUCH_RESET_GPIO_PORT 4 // GT911 Touch screen reset pin number range <0-7> // Defines GT911 Touch screen reset pin number. // Default: 0 #define RTE_GT911_TOUCH_RESET_PIN_NO 0 // GT911 Touch screen INT pin GPIO port number range <0-15> // Defines GT911 Touch screen INT pin GPIO port number. // Default: 9 #define RTE_GT911_TOUCH_INT_GPIO_PORT 9 // GT911 Touch screen INT pin number range <0-7> // Defines GT911 Touch screen INT pin number. // Default: 4 #define RTE_GT911_TOUCH_INT_PIN_NO 4 // RTE_GT911_TOUCH_I2C_INSTANCE // Defines GT911 Touchscreen i2c instance // <0=> I2C0 // <1=> I2C1 // <2=> I2C2 // <3=> I2C3 // <4=> I2C OVER I3C // Default: 1 #define RTE_GT911_TOUCH_I2C_INSTANCE 1 // RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL // Defines GT911 Touchscreen i2c slave address selection // <0x14=> I2C_SLAVE_ADDRESS_HEX_14 // <0x5D=> I2C_SLAVE_ADDRESS_HEX_5D // Default: 0x14 #define RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL 0x14 #endif #endif // TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] // CDC200 (cdc200) [Driver_CDC200] // Configuration settings for Driver_CDC200 in component ::Drivers:CDC200 #define RTE_CDC200 1 #if RTE_CDC200 // CDC200 IRQ priority <0-255> // Defines Interrupt priority. // Default: 0 #define RTE_CDC200_IRQ_PRI 0 // CDC200 clock select // <0=> 400 MHz clock source (PLL_CLK1/2) // <1=> 480 MHz clock source (PLL_CLK3) // Defines CDC200 clock select // Default: 400 MHz clock source (PLL_CLK1/2) #define RTE_CDC200_CLK_SEL 0 // CDC200 background color red <0-255> // Defines CDC200 background color red. // Default: 0 #define RTE_CDC200_BGC_RED 0 // CDC200 background color green <0-255> // Defines CDC200 background color green. // Default: 0 #define RTE_CDC200_BGC_GREEN 0 // CDC200 background color blue <0-255> // Defines CDC200 background color blue. // Default: 0 #define RTE_CDC200_BGC_BLUE 0 // CDC200 pixel format // <0=> ARGB8888 // <1=> RGB888 // <2=> RGB565 //     <3=> RGBA8888 //     <6=> ARGB1555 //     <7=> ARGB4444 // Defines CDC200 pixel format // Default: RGB888 #define RTE_CDC200_PIXEL_FORMAT 2 // CDC200 Constant alpha <0-255> // Defines CDC200 constant alpha range from 0 (fully transparent) to 255 or 1.0 (fully opaque). // Default: 255 #define RTE_CDC200_CONSTANT_ALPHA 255 // CDC200 blending factor // <0=> CONST_ALPHA // <1=> PIXEL_ALPHA_X_CONST_ALPHA // Defines CDC200 blending factor selection. // Default: PIXEL_ALPHA_X_CONST_ALPHA #define RTE_CDC200_BLEND_FACTOR 1 // CDC200 DPI interface FPS // Defines CDC200 DPI interface Framrate per second. // Default: 60 #define RTE_CDC200_DPI_FPS 60 // Parallel ILI6122 LCD PANEL // <0=> DISABLE // <1=> ENABLE // Defines Parallel ILI6122 LCD PANEL // Default: ENABLE #define RTE_ILI6122_PANEL 0 #if RTE_ILI6122_PANEL // CDC HSYNC pin active state // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines CDC HSYNC pin active state // Default: ACTIVE LOW #define RTE_ILI6122_PANEL_CDC_HSYNC_ACTIVE_LOW 0 // CDC VSYNC pin active state // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines CDC VSYNC pin active state // Default: ACTIVE LOW #define RTE_ILI6122_PANEL_CDC_VSYNC_ACTIVE_LOW 0 // CDC Pixel Clock Output pin active state // <0=> FEED THROUGH // <1=> INVERTED // Defines CDC Pixel Clock pin active state // Default: FEED THROUGH #define RTE_ILI6122_PANEL_CDC_PIXCLK_FEED_THROUGH 0 // CDC BLANKING pin active state // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines CDC BLANKINg pin active state // Default: ACTIVE LOW #define RTE_ILI6122_PANEL_CDC_BLANK_ACTIVE_LOW 0 // Panel hsync time in pixels // Defines ILI6122 LCD panel hsync time in pixels. // Default: 1 #define RTE_PANEL_HSYNC_TIME 1 // Panel hbp time in pixels // Defines ILI6122 LCD panel hbp time in pixels. // Default: 46 #define RTE_PANEL_HBP_TIME 46 // Panel hfp time in pixels // Defines ILI6122 LCD panel hfp time in pixels. // Default: 210 #define RTE_PANEL_HFP_TIME 210 // Panel hactive pixels // Defines ILI6122 LCD panel hactive pixels. // Default: 800 #define RTE_PANEL_HACTIVE_TIME 800 // Panel vsync time in lines // Defines ILI6122 LCD panel vsync time in lines. // Default: 1 #define RTE_PANEL_VSYNC_LINE 1 // Panel vbp time in lines // Defines ILI6122 LCD panel vbp time in lines. // Default: 23 #define RTE_PANEL_VBP_LINE 23 // Panel vfp time in lines // Defines ILI6122 LCD panel vfp time in lines. // Default: 22 #define RTE_PANEL_VFP_LINE 22 // Panel vactive lines // Defines ILI6122 LCD panel vactive lines. // Default: 480 #define RTE_PANEL_VACTIVE_LINE 480 #endif #endif // CDC200 (cdc200) [Driver_CDC200] // I3C (Improved Inter-Integrated Circuit) [Driver_I3C] // Configuration settings for Driver_I3C in component ::Drivers:I3C #define RTE_I3C 1 #if RTE_I3C #define RTE_I3C_IRQ_PRI 0 // I2C (Inter Integrated Circuit) [Driver_I2CI3C] // Configuration settings for Driver_I2CI3C in component ::Drivers:I2CI3C #define RTE_I2CI3C 1 // I2C (Inter Integrated Circuit) [Driver_I2CI3C] // I3C DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for I3C // Default: DISABLE #define RTE_I3C_DMA_ENABLE 0 // I3C DMA Selection // <0=> DMA2(M55-HE) // <1=> DMA0 // Defines Select DMA0 for I3C. By default DMA0 will be considered // Default: DMA0 #define RTE_I3C_SELECT_DMA0 1 // I3C DMA IRQ priority <0-255> // Defines I3C DMA Interrupt priority // Default: 0 #define RTE_I3C_DMA_IRQ_PRI 0 // I3C blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for I3C // Default: DISABLE #define RTE_I3C_BLOCKING_MODE_ENABLE 0 // I3C Slave I2C/I3C Adaptive mode Enable // <0=> DISABLE // <1=> ENABLE // Defines whether I3C Slave starts with I2C mode or not. // It is for for enabling some features for I2C/I3C mode // Default: DISABLE #define RTE_I3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 #endif // I3C (Improved Inter-Integrated Circuit) [Driver_I3C] // SPI (Serial Peripheral Interface) // SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] // Configuration settings for Driver_SPI0 in component ::Drivers:SPI #define RTE_SPI0 1 #ifdef RTE_SPI0 // SPI0 IRQ priority <0-255> // Defines Interrupt priority for SPI0. // Default: 0 #define RTE_SPI0_IRQ_PRIORITY 0 // SPI0 TX FIFO Start level <0-15> // Defines TX FIFO transfer start level for SPI0. // Default: 0 #define RTE_SPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // SPI0 load dummy data // <0=> DISABLE // <1=> ENABLE // load dummy data to start transfer for SPI0. // Default: 0 #define RTE_SPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 // SPI0 TX FIFO threshold <0-15> // Defines TX FIFO threshold for SPI0. // Default: 0 #define RTE_SPI0_TX_FIFO_THRESHOLD 0 // SPI0 RX FIFO threshold <0-15> // Defines RX FIFO threshold for SPI0. // Default: 0 #define RTE_SPI0_RX_FIFO_THRESHOLD 0 // SPI0 slave selection // <0=> SS_0 // <1=> SS_1 // <2=> SS_2 // <3=> SS_3 // Defines slave selection for SPI0. // Default: 0 #define RTE_SPI0_CHIP_SELECTION_PIN 0 // SPI0 RX SAMPLE DELAY <0-4> // Defines RX SAMPLE DELAY for SPI0. // Default: 0 #define RTE_SPI0_RX_SAMPLE_DELAY 0 // SPI0 Slave Select Toggle Enable // <0=> DISABLE // <1=> ENABLE // Defines SS state after each data frame for SPI0. // Default: 1 #define RTE_SPI0_SSTE_ENABLE 1 // SPI0 Master SS SW // <0=> DISABLE // <1=> ENABLE // Defines use of SW control slave select. // Default: 0 #define RTE_SPI0_USE_MASTER_SS_SW 0 #if RTE_SPI0_USE_MASTER_SS_SW // SPI0 SW SS Port <0-15> // Defines SPI0 port of SS pin in software controlled mode. // Default: 0 #define RTE_SPI0_SW_SPI_PORT 0 // SPI0 SW SS Pin <0-7> // Defines SPI0 SS pin number in software controlled mode. // Default: 0 #define RTE_SPI0_SW_SPI_PIN 0 // SPI0 SW SS Polarity // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines SW controlled slave select polarity for SPI0. // Default: 0 #define RTE_SPI0_SW_SPI_SS_POLARITY 0 #endif //RTE_SPI0_USE_MASTER_SS_SW // SPI0 Enable MicroWire FRF // <0=> DISABLE // <1=> ENABLE // Defines use of SPI0 MicroWire frame format. // Default: 0 #define RTE_SPI0_MICROWIRE_FRF_ENABLE 0 #if RTE_SPI0_MICROWIRE_FRF_ENABLE // SPI0 MW Transfer Mode // <0=> NON-SEQUENTIAL MODE // <1=> SEQUENTIAL MODE // Defines SPI0 MicroWire transfer mode. // Default: 0 #define RTE_SPI0_MW_TRANSFER_MODE 0 // SPI0 MW Handshake Enable // <0=> DISABLE // <1=> ENABLE // Defines SPI0 MicroWire handshake enable. // Default: 0 #define RTE_SPI0_MW_HANDSAHKE_ENABLE 0 // SPI0 MW Control Frame Size // Defines MW Control Frame Size for SPI0. // Default: 0 #define RTE_SPI0_MW_CFS 16 #endif //RTE_SPI0_MICROWIRE_FRF_ENABLE // SPI0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for SPI0 // Default: DISABLE #define RTE_SPI0_DMA_ENABLE 0 // SPI0 DMA IRQ priority <0-255> // Defines SPI0 DMA Interrupt priority // Default: 0 #define RTE_SPI0_DMA_IRQ_PRI 0 // SPI0 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for SPI0 // Default: DISABLE #define RTE_SPI0_BLOCKING_MODE_ENABLE 0 #endif // SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] // SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] // Configuration settings for Driver_SPI1 in component ::Drivers:SPI #define RTE_SPI1 1 #ifdef RTE_SPI1 // SPI1 IRQ priority <0-255> // Defines Interrupt priority for SPI1. // Default: 0 #define RTE_SPI1_IRQ_PRIORITY 0 // SPI1 TX FIFO Start level <0-15> // Defines TX FIFO transfer start level for SPI1. // Default: 0 #define RTE_SPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // SPI1 load dummy data // <0=> DISABLE // <1=> ENABLE // load dummy data to start transfer for SPI1. // Default: 0 #define RTE_SPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 // SPI1 TX FIFO threshold <0-15> // Defines TX FIFO threshold for SPI1. // Default: 0 #define RTE_SPI1_TX_FIFO_THRESHOLD 0 // SPI1 RX FIFO threshold <0-15> // Defines RX FIFO threshold for SPI1. // Default: 0 #define RTE_SPI1_RX_FIFO_THRESHOLD 0 // SPI1 slave selection // <0=> SS_0 // <1=> SS_1 // <2=> SS_2 // <3=> SS_3 // Defines slave selection for SPI1. // Default: 0 #define RTE_SPI1_CHIP_SELECTION_PIN 0 // SPI1 RX SAMPLE DELAY <0-4> // Defines RX SAMPLE DELAY for SPI1. // Default: 0 #define RTE_SPI1_RX_SAMPLE_DELAY 0 // SPI1 Slave Select Toggle Enable // <0=> DISABLE // <1=> ENABLE // Defines SS state after each data frame for SPI1. // Default: 1 #define RTE_SPI1_SSTE_ENABLE 1 // SPI1 Master SS SW // <0=> DISABLE // <1=> ENABLE // Defines use of SW control slave select. // Default: 0 #define RTE_SPI1_USE_MASTER_SS_SW 0 #if RTE_SPI1_USE_MASTER_SS_SW // SPI1 SW SS Port <0-15> // Defines SPI1 port of SS pin in software controlled mode. // Default: 0 #define RTE_SPI1_SW_SPI_PORT 0 // SPI1 SW SS pin number <0-7> // Defines SPI1 SS pin number in software controlled mode. // Default: 0 #define RTE_SPI1_SW_SPI_PIN 0 // SPI1 SW SS Polarity // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines SW controlled slave select polarity for SPI1. // Default: 0 #define RTE_SPI1_SW_SPI_SS_POLARITY 0 #endif //RTE_SPI1_USE_MASTER_SS_SW // SPI1 Enable MicroWire FRF // <0=> DISABLE // <1=> ENABLE // Defines use of SPI1 MicroWire frame format. // Default: 0 #define RTE_SPI1_MICROWIRE_FRF_ENABLE 0 #if RTE_SPI1_MICROWIRE_FRF_ENABLE // SPI1 MW Transfer Mode // <0=> NON-SEQUENTIAL MODE // <1=> SEQUENTIAL MODE // Defines SPI1 MicroWire transfer mode. // Default: 0 #define RTE_SPI1_MW_TRANSFER_MODE 0 // SPI1 MW Handshake Enable // <0=> DISABLE // <1=> ENABLE // Defines SPI1 MicroWire handshake enable. // Default: 0 #define RTE_SPI1_MW_HANDSAHKE_ENABLE 0 // SPI1 MW Control Frame Size // Defines MW Control Frame Size for SPI1. // Default: 0 #define RTE_SPI1_MW_CFS 16 #endif //RTE_SPI1_MICROWIRE_FRF_ENABLE // SPI1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for SPI1 // Default: DISABLE #define RTE_SPI1_DMA_ENABLE 0 // SPI1 DMA IRQ priority <0-255> // Defines SPI1 DMA Interrupt priority // Default: 0 #define RTE_SPI1_DMA_IRQ_PRI 0 // SPI1 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for SPI1 // Default: DISABLE #define RTE_SPI1_BLOCKING_MODE_ENABLE 0 #endif // SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] // SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] // Configuration settings for Driver_SPI2 in component ::Drivers:SPI #define RTE_SPI2 1 #ifdef RTE_SPI2 // SPI2 IRQ priority <0-255> // Defines Interrupt priority for SPI2. // Default: 0 #define RTE_SPI2_IRQ_PRIORITY 0 // SPI2 TX FIFO Start level <0-15> // Defines TX FIFO transfer start level for SPI2. // Default: 0 #define RTE_SPI2_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // SPI2 load dummy data // <0=> DISABLE // <1=> ENABLE // load dummy data to start transfer for SPI2. // Default: 0 #define RTE_SPI2_TX_LOAD_DUMMY_TO_START_LEVEL 0 // SPI2 TX FIFO threshold <0-15> // Defines TX FIFO threshold for SPI2. // Default: 0 #define RTE_SPI2_TX_FIFO_THRESHOLD 0 // SPI2 RX FIFO threshold <0-15> // Defines RX FIFO threshold for SPI2. // Default: 0 #define RTE_SPI2_RX_FIFO_THRESHOLD 0 // SPI2 slave selection // <0=> SS_0 // <1=> SS_1 // <2=> SS_2 // <3=> SS_3 // Defines slave selection for SPI2. // Default: 0 #define RTE_SPI2_CHIP_SELECTION_PIN 0 // SPI2 RX SAMPLE DELAY <0-4> // Defines RX SAMPLE DELAY for SPI2. // Default: 0 #define RTE_SPI2_RX_SAMPLE_DELAY 0 // SPI2 Slave Select Toggle Enable // <0=> DISABLE // <1=> ENABLE // Defines SS state after each data frame for SPI2. // Default: 1 #define RTE_SPI2_SSTE_ENABLE 1 // SPI2 Master SS SW // <0=> DISABLE // <1=> ENABLE // Defines use of SW control slave select. // Default: 0 #define RTE_SPI2_USE_MASTER_SS_SW 0 #if RTE_SPI2_USE_MASTER_SS_SW // SPI2 SW SS Port <0-15> // Defines SPI2 port of SS pin in software controlled mode // Default: 0 #define RTE_SPI2_SW_SPI_PORT 0 // SPI2 SW SS pin number <0-7> // Defines SPI2 SS pin number in software controlled mode // Default: 0 #define RTE_SPI2_SW_SPI_PIN 0 // SPI2 SW SS Polarity // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines SW controlled slave select polarity for SPI2. // Default: 0 #define RTE_SPI2_SW_SPI_SS_POLARITY 0 #endif //RTE_SPI2_USE_MASTER_SS_SW // SPI2 Enable MicroWire FRF // <0=> DISABLE // <1=> ENABLE // Defines use of SPI2 MicroWire frame format. // Default: 0 #define RTE_SPI2_MICROWIRE_FRF_ENABLE 0 #if RTE_SPI2_MICROWIRE_FRF_ENABLE // SPI2 MW Transfer Mode // <0=> NON-SEQUENTIAL MODE // <1=> SEQUENTIAL MODE // Defines SPI2 MicroWire transfer mode. // Default: 0 #define RTE_SPI2_MW_TRANSFER_MODE 0 // SPI2 MW Handshake Enable // <0=> DISABLE // <1=> ENABLE // Defines SPI2 MicroWire handshake enable. // Default: 0 #define RTE_SPI2_MW_HANDSAHKE_ENABLE 0 // SPI2 MW Control Frame Size // Defines MW Control Frame Size for SPI2. // Default: 0 #define RTE_SPI2_MW_CFS 0 #endif //RTE_SPI2_MICROWIRE_FRF_ENABLE // SPI2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for SPI2 // Default: DISABLE #define RTE_SPI2_DMA_ENABLE 0 // SPI2 DMA IRQ priority <0-255> // Defines SPI2 DMA Interrupt priority // Default: 0 #define RTE_SPI2_DMA_IRQ_PRI 0 // SPI2 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for SPI2 // Default: DISABLE #define RTE_SPI2_BLOCKING_MODE_ENABLE 0 #endif // SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] // SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] // Configuration settings for Driver_SPI3 in component ::Drivers:SPI #define RTE_SPI3 1 #ifdef RTE_SPI3 // SPI3 IRQ priority <0-255> // Defines Interrupt priority for SPI3. // Default: 0 #define RTE_SPI3_IRQ_PRIORITY 0 // SPI3 TX FIFO Start level <0-15> // Defines TX FIFO transfer start level for SPI3. // Default: 0 #define RTE_SPI3_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // SPI3 load dummy data // <0=> DISABLE // <1=> ENABLE // load dummy data to start transfer for SPI3. // Default: 0 #define RTE_SPI3_TX_LOAD_DUMMY_TO_START_LEVEL 0 // SPI3 TX FIFO threshold <0-15> // Defines TX FIFO threshold for SPI3. // Default: 0 #define RTE_SPI3_TX_FIFO_THRESHOLD 0 // SPI3 RX FIFO threshold <0-15> // Defines RX FIFO threshold for SPI3. // Default: 0 #define RTE_SPI3_RX_FIFO_THRESHOLD 0 // SPI3 slave selection // <0=> SS_0 // <1=> SS_1 // <2=> SS_2 // <3=> SS_3 // Defines slave selection for SPI3. // Default: 0 #define RTE_SPI3_CHIP_SELECTION_PIN 1 // SPI3 RX SAMPLE DELAY <0-4> // Defines RX SAMPLE DELAY for SPI3. // Default: 0 #define RTE_SPI3_RX_SAMPLE_DELAY 0 // SPI3 Slave Select Toggle Enable // <0=> DISABLE // <1=> ENABLE // Defines SS state after each data frame for SPI3. // Default: 1 #define RTE_SPI3_SSTE_ENABLE 1 // SPI3 Master SS SW // <0=> DISABLE // <1=> ENABLE // Defines use of SW control slave select. // Default: 0 #define RTE_SPI3_USE_MASTER_SS_SW 0 #if RTE_SPI3_USE_MASTER_SS_SW // SPI3 SW SS Port <0-15> // Defines SPI3 port of SS pin in software controlled mode // Default: 0 #define RTE_SPI3_SW_SPI_PORT 0 // SPI3 SW SS pin number <0-7> // Defines SPI3 SS pin number in software controlled mode // Default: 0 #define RTE_SPI3_SW_SPI_PIN 0 // SPI3 SW SS Polarity // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines SW controlled slave select polarity for SPI3. // Default: 0 #define RTE_SPI3_SW_SPI_SS_POLARITY 0 #endif //RTE_SPI3_USE_MASTER_SS_SW // SPI3 Enable MicroWire FRF // <0=> DISABLE // <1=> ENABLE // Defines use of SPI3 MicroWire frame format. // Default: 0 #define RTE_SPI3_MICROWIRE_FRF_ENABLE 0 #if RTE_SPI3_MICROWIRE_FRF_ENABLE // SPI3 MW Transfer Mode // <0=> NON-SEQUENTIAL MODE // <1=> SEQUENTIAL MODE // Defines SPI3 MicroWire transfer mode. // Default: 0 #define RTE_SPI3_MW_TRANSFER_MODE 0 // SPI3 MW Handshake Enable // <0=> DISABLE // <1=> ENABLE // Defines SPI3 MicroWire handshake enable. // Default: 0 #define RTE_SPI3_MW_HANDSAHKE_ENABLE 0 // SPI3 MW Control Frame Size // Defines MW Control Frame Size for SPI3. // Default: 0 #define RTE_SPI3_MW_CFS 0 #endif //RTE_SPI3_MICROWIRE_FRF_ENABLE // SPI3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for SPI3 // Default: DISABLE #define RTE_SPI3_DMA_ENABLE 0 // SPI3 DMA IRQ priority <0-255> // Defines SPI3 DMA Interrupt priority // Default: 0 #define RTE_SPI3_DMA_IRQ_PRI 0 // SPI3 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for SPI3 // Default: DISABLE #define RTE_SPI3_BLOCKING_MODE_ENABLE 0 #endif // SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] // LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] // Configuration settings for Driver_LPSPI in component ::Drivers:SPI #if defined(M55_HE) #define RTE_LPSPI 1 #ifdef RTE_LPSPI // LPSPI IRQ priority <0-255> // Defines Interrupt priority for LPSPI. // Default: 0 #define RTE_LPSPI_IRQ_PRIORITY 0 // LPSPI TX FIFO Start level <0-15> // Defines TX FIFO transfer start level for LPSPI. // Default: 0 #define RTE_LPSPI_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // LPSPI load dummy data // <0=> DISABLE // <1=> ENABLE // load dummy data to start transfer for LPSPI. // Default: 0 #define RTE_LPSPI_TX_LOAD_DUMMY_TO_START_LEVEL 0 // LPSPI TX FIFO threshold <0-15> // Defines TX FIFO threshold for LPSPI. // Default: 0 #define RTE_LPSPI_TX_FIFO_THRESHOLD 0 // LPSPI RX FIFO threshold <0-15> // Defines RX FIFO threshold for LPSPI. // Default: 0 #define RTE_LPSPI_RX_FIFO_THRESHOLD 0 // LPSPI slave selection // <0=> SS_0 // Defines slave selection for LPSPI. // Default: 0 #define RTE_LPSPI_CHIP_SELECTION_PIN 0 // LPSPI Slave Select Toggle Enable // <0=> DISABLE // <1=> ENABLE // Defines SS state after each data frame for LPSPI. // Default: 1 #define RTE_LPSPI_SSTE_ENABLE 1 // LPSPI Master SS SW // <0=> DISABLE // <1=> ENABLE // Defines use of SW control slave select. // Default: 0 #define RTE_LPSPI_USE_MASTER_SS_SW 0 #if RTE_LPSPI_USE_MASTER_SS_SW // LPSPI SW SS Port <0-15> // Defines LPSPI port of SS pin in software controlled mode // Default: 0 #define RTE_LPSPI_SW_SPI_PORT 0 // LPSPI SW SS pin number <0-7> // Defines LPSPI SS pin number in software controlled mode // Default: 0 #define RTE_LPSPI_SW_SPI_PIN 0 // LPSPI SW SS Polarity // <0=> ACTIVE LOW // <1=> ACTIVE HIGH // Defines SW controlled slave select polarity for LPSPI. // Default: 0 #define RTE_LPSPI_SW_SPI_SS_POLARITY 0 #endif //RTE_LPSPI_USE_MASTER_SS_SW // LPSPI Enable MicroWire FRF // <0=> DISABLE // <1=> ENABLE // Defines use of LPSPI MicroWire frame format. // Default: 0 #define RTE_LPSPI_MICROWIRE_FRF_ENABLE 0 #if RTE_LPSPI_MICROWIRE_FRF_ENABLE // LPSPI MW Transfer Mode // <0=> NON-SEQUENTIAL MODE // <1=> SEQUENTIAL MODE // Defines LPSPI MicroWire transfer mode. // Default: 0 #define RTE_LPSPI_MW_TRANSFER_MODE 0 // LPSPI MW Handshake Enable // <0=> DISABLE // <1=> ENABLE // Defines LPSPI MicroWire handshake enable. // Default: 0 #define RTE_LPSPI_MW_HANDSAHKE_ENABLE 0 // LPSPI MW Control Frame Size // Defines MW Control Frame Size for LPSPI. // Default: 0 #define RTE_LPSPI_MW_CFS 8 #endif //RTE_LPSPI_MICROWIRE_FRF_ENABLE // LPSPI DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for LPSPI // Default: DISABLE #define RTE_LPSPI_DMA_ENABLE 0 #if RTE_LPSPI_DMA_ENABLE // LPSPI DMA Selection // <0=> DMA2 // <1=> DMA0 // Defines Select DMA0 for LPSPI. By default DMA2 will be considered // Default: DMA2 #define RTE_LPSPI_SELECT_DMA0 0 #if RTE_LPSPI_SELECT_DMA0 // LPSPI DMA0 Group Selection // <1=> DMA0_GROUP_1 // <2=> DMA0_GROUP_2 // Defines DMA0 Group for LPSPI. By default DMA0 Group 1 will be considered // Default: DMA0_GROUP_1 #define RTE_LPSPI_SELECT_DMA0_GROUP 1 #endif //RTE_LPSPI_SELECT_DMA0 #endif //RTE_LPSPI_DMA_ENABLE // LPSPI DMA IRQ priority <0-255> // Defines LPSPI DMA Interrupt priority // Default: 0 #define RTE_LPSPI_DMA_IRQ_PRI 0 #endif //RTE_LPSPI #endif //M55_HE // LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] // SPI (Serial Peripheral Interface) // OSPI (Octal Serial Peripheral Interface) // OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] // Configuration settings for Driver_OSPI in component ::Drivers:OSPI #define RTE_OSPI0 1 #if RTE_OSPI0 // OSPI0 IRQ priority <0-255> // Defines OSPI0 Interrupt priority // Default: 0 #define RTE_OSPI0_IRQ_PRIORITY 0 // OSPI0 Frame format // <0=> Standard // <1=> Dual // <2=> Quad // <3=> Octal // Defines OSPI0 Frame format // Default: Octal #define RTE_OSPI0_SPI_FRAME_FORMAT 3 // OSPI0 TX FIFO Start level <0-255> // Defines TX FIFO transfer start level for OSPI0 // Default: 0 #define RTE_OSPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // OSPI0 load dummy data // <0=> DISABLE // <1=> ENABLE // Load dummy data to start transfer for OSPI0 // Default: DISABLE #define RTE_OSPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 // OSPI0 TX FIFO threshold <0-255> // Defines TX FIFO threshold for OSPI0 // Default: 64 #define RTE_OSPI0_TX_FIFO_THRESHOLD 64 // OSPI0 RX FIFO threshold <0-255> // Defines RX FIFO threshold for OSPI0 // Default: 0 #define RTE_OSPI0_RX_FIFO_THRESHOLD 0 // OSPI0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Enable DMA for OSPI0 // Default: DISABLE #define RTE_OSPI0_DMA_ENABLE 0 #if RTE_OSPI0_DMA_ENABLE // OSPI0 TX DMA Data level // Defines TX DMA Data level for OSPI0 // Default: 64 #define RTE_OSPI0_TX_DMA_DATA_LEVEL 64 // OSPI0 RX DMA Data level // Defines RX DMA Data level for OSPI0 // Default: 15 #define RTE_OSPI0_RX_DMA_DATA_LEVEL 15 // OSPI0 DMA IRQ priority <0-255> // Defines OSPI0 DMA Interrupt priority // Default: 0 #define RTE_OSPI0_DMA_IRQ_PRIORITY 0 #endif // OSPI0 slave selection // <0=> SS_0 // <1=> SS_1 // Defines the slave select line for OSPI0 // Default: 0 #define RTE_OSPI0_CHIP_SELECTION_PIN 0 // OSPI0 RX SAMPLE DELAY // Defines RX SAMPLE DELAY for OSPI0 // Default: 0 #define RTE_OSPI0_RX_SAMPLE_DELAY 0 // OSPI0 DDR DRIVE EDGE // Defines DDR DRIVE EDGE for OSPI0 // Default: 0 #define RTE_OSPI0_DDR_DRIVE_EDGE 0 // OSPI0 RXDS Delay <0-16> // Defines the delay applied to the RXDS signal of OSPI0 // Default: 0 #define RTE_OSPI0_RXDS_DELAY 0 #endif // OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] // OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] // Configuration settings for Driver_OSPI in component ::Drivers:OSPI #define RTE_OSPI1 1 #if RTE_OSPI1 // OSPI1 IRQ priority <0-255> // Defines OSPI1 Interrupt priority // Default: 0 #define RTE_OSPI1_IRQ_PRIORITY 0 // OSPI1 Frame format // <0=> Standard // <1=> Dual // <2=> Quad // <3=> Octal // Defines OSPI0 Frame format // Default: Octal #define RTE_OSPI1_SPI_FRAME_FORMAT 3 // OSPI1 TX FIFO Start level <0-255> // Defines TX FIFO transfer start level for OSPI1 // Default: 0 #define RTE_OSPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 // OSPI1 load dummy data // <0=> DISABLE // <1=> ENABLE // Load dummy data to start transfer for OSPI1 // Default: DISABLE #define RTE_OSPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 // OSPI1 TX FIFO threshold <0-255> // Defines TX FIFO threshold for OSPI1 // Default: 64 #define RTE_OSPI1_TX_FIFO_THRESHOLD 64 // OSPI1 RX FIFO threshold <0-255> // Defines RX FIFO threshold for OSPI1 // Default: 0 #define RTE_OSPI1_RX_FIFO_THRESHOLD 0 // OSPI1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Enable DMA for OSPI1 // Default: DISABLE #define RTE_OSPI1_DMA_ENABLE 0 #if RTE_OSPI1_DMA_ENABLE // OSPI1 TX DMA Data level // Defines TX DMA Data level for OSPI1 // Default: 130 #define RTE_OSPI1_TX_DMA_DATA_LEVEL 130 // OSPI1 RX DMA Data level // Defines RX DMA Data level for OSPI1 // Default: 15 #define RTE_OSPI1_RX_DMA_DATA_LEVEL 15 // OSPI1 DMA IRQ priority <0-255> // Defines OSPI1 DMA Interrupt priority // Default: 0 #define RTE_OSPI1_DMA_IRQ_PRIORITY 0 #endif // OSPI1 slave selection // <0=> SS_0 // <1=> SS_1 // Defines the slave select line for OSPI1. // Default: 0 #define RTE_OSPI1_CHIP_SELECTION_PIN 0 // OSPI1 RX SAMPLE DELAY // Defines RX SAMPLE DELAY for OSPI1 // Default: 0 #define RTE_OSPI1_RX_SAMPLE_DELAY 0 // OSPI1 DDR DRIVE EDGE // Defines DDR DRIVE EDGE for OSPI1 // Default: 1 #define RTE_OSPI1_DDR_DRIVE_EDGE 1 // OSPI1 RXDS Delay <0-16> // Defines the delay applied to the RXDS signal of OSPI1 // Default: 11 #define RTE_OSPI1_RXDS_DELAY 11 #endif // OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] // // FLASH (ISSI FLASH) [Driver_Flash] // Configuration settings for Driver_Flash in component ::Drivers:Flash #define RTE_ISSI_FLASH 1 #if RTE_ISSI_FLASH // ISSI FLASH OSPI Instance // Defines the OSPI controller instance the ISSI flash is connected to // Default: 1 #define RTE_ISSI_FLASH_OSPI_DRV_NUM 1 // ISSI FLASH OSPI Bus speed // Defines the OSPI Bus speed // Default: 100000000 #define RTE_ISSI_FLASH_OSPI_BUS_SPEED 100000000 // ISSI FLASH Wait cycles // Defines the number of wait (dummy) cycles needed for fast read operations // Default: 16 #define RTE_ISSI_FLASH_WAIT_CYCLES 16 #endif // FLASH (ISSI FLASH) [Driver_Flash] // I2S (Integrated Interchip Sound) // I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] // Configuration settings for Driver_SAI0 in component ::Drivers:SAI #define RTE_I2S0 1 #if RTE_I2S0 // I2S0 WORD SELECT SIZE // <0=> WSS_CLOCK_CYCLES_16 // <1=> WSS_CLOCK_CYCLES_24 // <2=> WSS_CLOCK_CYCLES_32 // Defines I2S0 size of word // Default: WSS_CLOCK_CYCLES_32 #define RTE_I2S0_WSS_CLOCK_CYCLES 2 // I2S0 SCLK GATING // <0=> NO_CLOCK_GATING // <1=> SCLKG_CLOCK_CYCLES_12 // <2=> SCLKG_CLOCK_CYCLES_16 // <3=> SCLKG_CLOCK_CYCLES_20 // <4=> SCLKG_CLOCK_CYCLES_24 // Defines I2S0 SCLK Gating // Default: NO_CLOCK_GATING #define RTE_I2S0_SCLKG_CLOCK_CYCLES 0 // I2S0 RX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S0 receive fifo trigger level // Default: TRIGGER_LEVEL_8 #define RTE_I2S0_RX_TRIG_LVL 7 // I2S0 TX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S0 transfer fifo trigger level // Default: TRIGGER_LEVEL_9 #define RTE_I2S0_TX_TRIG_LVL 8 // I2S0 IRQ priority <0-255> // Defines I2S0 Interrupt priority // Default: 0 #define RTE_I2S0_IRQ_PRI 0 // I2S0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for I2S0 // Default: ENABLE #define RTE_I2S0_DMA_ENABLE 0 // I2S0 DMA IRQ priority <0-255> // Defines I2S0 DMA Interrupt priority // Default: 0 #define RTE_I2S0_DMA_IRQ_PRI 0 // I2S0 Blocking Mode // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for I2S0 // Default: DISABLE #define RTE_I2S0_BLOCKING_MODE_ENABLE 0 #endif // I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] // I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] // Configuration settings for Driver_SAI1 in component ::Drivers:SAI #define RTE_I2S1 1 #if RTE_I2S1 // I2S1 WORD SELECT SIZE // <0=> WSS_CLOCK_CYCLES_16 // <1=> WSS_CLOCK_CYCLES_24 // <2=> WSS_CLOCK_CYCLES_32 // Defines I2S1 size of word // Default: WSS_CLOCK_CYCLES_32 #define RTE_I2S1_WSS_CLOCK_CYCLES 2 // I2S1 SCLK GATING // <0=> NO_CLOCK_GATING // <1=> SCLKG_CLOCK_CYCLES_12 // <2=> SCLKG_CLOCK_CYCLES_16 // <3=> SCLKG_CLOCK_CYCLES_20 // <4=> SCLKG_CLOCK_CYCLES_24 // Defines I2S1 SCLK Gating // Default: NO_CLOCK_GATING #define RTE_I2S1_SCLKG_CLOCK_CYCLES 0 // I2S1 RX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S1 receive fifo trigger level // Default: TRIGGER_LEVEL_8 #define RTE_I2S1_RX_TRIG_LVL 7 // I2S1 TX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S1 transfer fifo trigger level // Default: TRIGGER_LEVEL_9 #define RTE_I2S1_TX_TRIG_LVL 8 // I2S1 IRQ priority <0-255> // Defines I2S1 Interrupt priority // Default: 1 #define RTE_I2S1_IRQ_PRI 1 // I2S1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for I2S1 // Default: ENABLE #define RTE_I2S1_DMA_ENABLE 0 // I2S1 DMA IRQ priority <0-255> // Defines I2S1 DMA Interrupt priority // Default: 0 #define RTE_I2S1_DMA_IRQ_PRI 0 // I2S1 Blocking Mode // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for I2S1 // Default: DISABLE #define RTE_I2S1_BLOCKING_MODE_ENABLE 0 #endif // I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] // I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] // Configuration settings for Driver_SAI2 in component ::Drivers:SAI #define RTE_I2S2 1 #if RTE_I2S2 // I2S2 WORD SELECT SIZE // <0=> WSS_CLOCK_CYCLES_16 // <1=> WSS_CLOCK_CYCLES_24 // <2=> WSS_CLOCK_CYCLES_32 // Defines I2S2 size of word // Default: WSS_CLOCK_CYCLES_32 #define RTE_I2S2_WSS_CLOCK_CYCLES 2 // I2S2 SCLK GATING // <0=> NO_CLOCK_GATING // <1=> SCLKG_CLOCK_CYCLES_12 // <2=> SCLKG_CLOCK_CYCLES_16 // <3=> SCLKG_CLOCK_CYCLES_20 // <4=> SCLKG_CLOCK_CYCLES_24 // Defines I2S2 SCLK Gating // Default: NO_CLOCK_GATING #define RTE_I2S2_SCLKG_CLOCK_CYCLES 0 // I2S2 RX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S2 receive fifo trigger level // Default: TRIGGER_LEVEL_8 #define RTE_I2S2_RX_TRIG_LVL 7 // I2S2 TX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S2 transfer fifo trigger level // Default: TRIGGER_LEVEL_9 #define RTE_I2S2_TX_TRIG_LVL 8 // I2S2 IRQ priority <0-255> // Defines I2S2 Interrupt priority // Default: 0 #define RTE_I2S2_IRQ_PRI 10 // I2S2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for I2S2 // Default: ENABLE #define RTE_I2S2_DMA_ENABLE 0 // I2S2 DMA IRQ priority <0-255> // Defines I2S2 DMA Interrupt priority // Default: 0 #define RTE_I2S2_DMA_IRQ_PRI 0 // I2S2 Blocking Mode // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for I2S2 // Default: DISABLE #define RTE_I2S2_BLOCKING_MODE_ENABLE 0 #endif // I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] // I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] // Configuration settings for Driver_SAI3 in component ::Drivers:SAI #define RTE_I2S3 1 #if RTE_I2S3 // I2S3 WORD SELECT SIZE // <0=> WSS_CLOCK_CYCLES_16 // <1=> WSS_CLOCK_CYCLES_24 // <2=> WSS_CLOCK_CYCLES_32 // Defines I2S3 size of word // Default: WSS_CLOCK_CYCLES_32 #define RTE_I2S3_WSS_CLOCK_CYCLES 2 // I2S3 SCLK GATING // <0=> NO_CLOCK_GATING // <1=> SCLKG_CLOCK_CYCLES_12 // <2=> SCLKG_CLOCK_CYCLES_16 // <3=> SCLKG_CLOCK_CYCLES_20 // <4=> SCLKG_CLOCK_CYCLES_24 // Defines I2S3 SCLK Gating // Default: NO_CLOCK_GATING #define RTE_I2S3_SCLKG_CLOCK_CYCLES 0 // I2S3 RX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S3 receive fifo trigger level // Default: TRIGGER_LEVEL_8 #define RTE_I2S3_RX_TRIG_LVL 7 // I2S3 TX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines I2S3 transfer fifo trigger level // Default: TRIGGER_LEVEL_9 #define RTE_I2S3_TX_TRIG_LVL 8 // I2S3 IRQ priority <0-255> // Defines I2S3 Interrupt priority // Default: 0 #define RTE_I2S3_IRQ_PRI 0 // I2S3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for I2S3 // Default: ENABLE #define RTE_I2S3_DMA_ENABLE 0 // I2S3 DMA IRQ priority <0-255> // Defines I2S3 DMA Interrupt priority // Default: 0 #define RTE_I2S3_DMA_IRQ_PRI 0 // I2S3 Blocking Mode // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for I2S3 // Default: DISABLE #define RTE_I2S3_BLOCKING_MODE_ENABLE 0 #endif // I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] // LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] // Configuration settings for Driver_SAILP in component ::Drivers:SAI #if defined(M55_HE) #define RTE_LPI2S 1 #if RTE_LPI2S // LPI2S WORD SELECT SIZE // <0=> WSS_CLOCK_CYCLES_16 // <1=> WSS_CLOCK_CYCLES_24 // <2=> WSS_CLOCK_CYCLES_32 // Defines LPI2S size of word // Default: WSS_CLOCK_CYCLES_32 #define RTE_LPI2S_WSS_CLOCK_CYCLES 2 // LPI2S SCLK GATING // <0=> NO_CLOCK_GATING // <1=> SCLKG_CLOCK_CYCLES_12 // <2=> SCLKG_CLOCK_CYCLES_16 // <3=> SCLKG_CLOCK_CYCLES_20 // <4=> SCLKG_CLOCK_CYCLES_24 // Defines LPI2S SCLK Gating // Default: NO_CLOCK_GATING #define RTE_LPI2S_SCLKG_CLOCK_CYCLES 0 // LPI2S RX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines LPI2S receive fifo trigger level // Default: TRIGGER_LEVEL_8 #define RTE_LPI2S_RX_TRIG_LVL 7 // LPI2S TX FIFO TRIGGER LEVEL // <0=> TRIGGER_LEVEL_1 // <1=> TRIGGER_LEVEL_2 // <2=> TRIGGER_LEVEL_3 // <3=> TRIGGER_LEVEL_4 // <4=> TRIGGER_LEVEL_5 // <5=> TRIGGER_LEVEL_6 // <6=> TRIGGER_LEVEL_7 // <7=> TRIGGER_LEVEL_8 // <8=> TRIGGER_LEVEL_9 // <9=> TRIGGER_LEVEL_10 // <10=> TRIGGER_LEVEL_11 // <11=> TRIGGER_LEVEL_12 // <12=> TRIGGER_LEVEL_13 // <13=> TRIGGER_LEVEL_14 // <14=> TRIGGER_LEVEL_15 // <15=> TRIGGER_LEVEL_16 // Defines LPI2S transfer fifo trigger level // Default: TRIGGER_LEVEL_9 #define RTE_LPI2S_TX_TRIG_LVL 8 // LPI2S IRQ priority <0-255> // Defines LPI2S Interrupt priority // Default: 1 #define RTE_LPI2S_IRQ_PRI 1 // LPI2S DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for LPI2S // Default: ENABLE #define RTE_LPI2S_DMA_ENABLE 0 #if RTE_LPI2S_DMA_ENABLE // LPI2S DMA Selection // <0=> DMA2 // <1=> DMA0 // Defines Select DMA0 for LPI2S. By default DMA2 will be considered // Default: DMA2 #define RTE_LPI2S_SELECT_DMA0 0 #endif // LPI2S DMA IRQ priority <0-255> // Defines LPI2S DMA Interrupt priority // Default: 0 #define RTE_LPI2S_DMA_IRQ_PRI 0 // LPI2S Blocking Mode // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for LPI2S // Default: DISABLE #define RTE_LPI2S_BLOCKING_MODE_ENABLE 0 #endif //RTE_LPI2S #endif //defined(M55_HE) // LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] // I2S (Integrated Interchip Sound) // UART (Universal asynchronous receiver transmitter) // UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::Drivers:USART #define RTE_UART0 1 #if RTE_UART0 // UART0 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART0 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART0_RX_TRIG_LVL 0 // UART0 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART0 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART0_TX_TRIG_LVL 0 // UART0 IRQ priority <0-255> // Defines Interrupt priority for UART0. // Default: 0 #define RTE_UART0_IRQ_PRI 0 // UART0 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART0 clock source. // Default: CLK_100MHz #define RTE_UART0_CLK_SOURCE 1 // UART0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART0 // Default: DISABLE #define RTE_UART0_DMA_ENABLE 0 // UART0 DMA IRQ priority <0-255> // Defines UART0 DMA Interrupt priority // Default: 0 #define RTE_UART0_DMA_IRQ_PRI 0 // UART0 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART0 // Default: DISABLE #define RTE_UART0_BLOCKING_MODE_ENABLE 0 #endif //UART0 // UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] // UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] // Configuration settings for Driver_USART1 in component ::Drivers:USART #define RTE_UART1 1 #if RTE_UART1 // UART1 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART1 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART1_RX_TRIG_LVL 0 // UART1 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART1 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART1_TX_TRIG_LVL 0 // UART1 IRQ priority <0-255> // Defines Interrupt priority for UART1. // Default: 0 #define RTE_UART1_IRQ_PRI 0 // UART1 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART1 clock source. // Default: CLK_100MHz #define RTE_UART1_CLK_SOURCE 1 // UART1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART1 // Default: DISABLE #define RTE_UART1_DMA_ENABLE 0 // UART1 DMA IRQ priority <0-255> // Defines UART1 DMA Interrupt priority // Default: 0 #define RTE_UART1_DMA_IRQ_PRI 0 // UART1 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART1 // Default: DISABLE #define RTE_UART1_BLOCKING_MODE_ENABLE 0 #endif //UART1 // UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] // UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] // Configuration settings for Driver_USART2 in component ::Drivers:USART #define RTE_UART2 1 #if RTE_UART2 // UART2 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART2 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART2_RX_TRIG_LVL 0 // UART2 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART2 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART2_TX_TRIG_LVL 0 // UART2 IRQ priority <0-255> // Defines Interrupt priority for UART2. // Default: 0 #define RTE_UART2_IRQ_PRI 0 // UART2 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART2 clock source. // Default: CLK_100MHz #define RTE_UART2_CLK_SOURCE 1 // UART2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART2 // Default: DISABLE #define RTE_UART2_DMA_ENABLE 0 // UART2 DMA IRQ priority <0-255> // Defines UART2 DMA Interrupt priority // Default: 0 #define RTE_UART2_DMA_IRQ_PRI 0 // UART2 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART2 // Default: DISABLE #define RTE_UART2_BLOCKING_MODE_ENABLE 0 #endif //UART2 // UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] // UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] // Configuration settings for Driver_USART3 in component ::Drivers:USART #define RTE_UART3 1 #if RTE_UART3 // UART3 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART3 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART3_RX_TRIG_LVL 0 // UART3 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART3 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART3_TX_TRIG_LVL 0 // UART3 IRQ priority <0-255> // Defines Interrupt priority for UART3. // Default: 0 #define RTE_UART3_IRQ_PRI 0 // UART3 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART3 clock source. // Default: CLK_100MHz #define RTE_UART3_CLK_SOURCE 1 // UART3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART3 // Default: DISABLE #define RTE_UART3_DMA_ENABLE 0 // UART3 DMA IRQ priority <0-255> // Defines UART3 DMA Interrupt priority // Default: 0 #define RTE_UART3_DMA_IRQ_PRI 0 // UART3 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART3 // Default: DISABLE #define RTE_UART3_BLOCKING_MODE_ENABLE 0 #endif //UART3 // UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] // UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] // Configuration settings for Driver_USART4 in component ::Drivers:USART #define RTE_UART4 1 #if RTE_UART4 // UART4 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART4 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART4_RX_TRIG_LVL 0 // UART4 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART4 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART4_TX_TRIG_LVL 0 // UART4 IRQ priority <0-255> // Defines Interrupt priority for UART4. // Default: 0 #define RTE_UART4_IRQ_PRI 0 // UART4 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART4 clock source. // Default: CLK_100MHz #define RTE_UART4_CLK_SOURCE 1 #define RTE_UART4_RS485_ENABLE 0 #if RTE_UART4_RS485_ENABLE #define RTE_UART4_RS485_TRANSFER_MODE 2 #define RTE_UART4_RS485_DE_ASSERTION_TIME_8BIT (0x01) #define RTE_UART4_RS485_DE_DEASSERTION_TIME_8BIT (0x01) #define RTE_UART4_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) #define RTE_UART4_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) #endif // UART4 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART4 // Default: DISABLE #define RTE_UART4_DMA_ENABLE 0 // UART4 DMA Selection // <0=> DMA1(M55-HP) // <1=> DMA0 // Defines Select DMA0 for UART4. By default DMA0 will be considered. // Default: DMA0 #define RTE_UART4_SELECT_DMA0 1 // UART4 DMA IRQ priority <0-255> // Defines UART4 DMA Interrupt priority // Default: 0 #define RTE_UART4_DMA_IRQ_PRI 0 // UART4 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART4 // Default: DISABLE #define RTE_UART4_BLOCKING_MODE_ENABLE 0 #endif //UART4 // UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] // UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] // Configuration settings for Driver_USART5 in component ::Drivers:USART #define RTE_UART5 1 #if RTE_UART5 // UART5 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART5 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART5_RX_TRIG_LVL 0 // UART5 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART5 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART5_TX_TRIG_LVL 0 // UART5 IRQ priority <0-255> // Defines Interrupt priority for UART5. // Default: 0 #define RTE_UART5_IRQ_PRI 0 // UART5 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART5 clock source. // Default: CLK_100MHz #define RTE_UART5_CLK_SOURCE 1 #define RTE_UART5_RS485_ENABLE 0 #if RTE_UART5_RS485_ENABLE #define RTE_UART5_RS485_TRANSFER_MODE 2 #define RTE_UART5_RS485_DE_ASSERTION_TIME_8BIT (0x01) #define RTE_UART5_RS485_DE_DEASSERTION_TIME_8BIT (0x01) #define RTE_UART5_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) #define RTE_UART5_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) #endif // UART5 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART5 // Default: DISABLE #define RTE_UART5_DMA_ENABLE 0 // UART5 DMA Selection // <0=> DMA1(M55-HP) // <1=> DMA0 // Defines Select DMA0 for UART5. By default DMA0 will be considered // Default: DMA0 #define RTE_UART5_SELECT_DMA0 1 // UART5 DMA IRQ priority <0-255> // Defines UART5 DMA Interrupt priority // Default: 0 #define RTE_UART5_DMA_IRQ_PRI 0 // UART5 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART5 // Default: DISABLE #define RTE_UART5_BLOCKING_MODE_ENABLE 0 #endif //UART5 // UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] // UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] // Configuration settings for Driver_USART6 in component ::Drivers:USART #define RTE_UART6 1 #if RTE_UART6 // UART6 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART6 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART6_RX_TRIG_LVL 0 // UART6 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART6 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART6_TX_TRIG_LVL 0 // UART6 IRQ priority <0-255> // Defines Interrupt priority for UART6. // Default: 0 #define RTE_UART6_IRQ_PRI 0 // UART6 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART6 clock source. // Default: CLK_100MHz #define RTE_UART6_CLK_SOURCE 1 #define RTE_UART6_RS485_ENABLE 0 #if RTE_UART6_RS485_ENABLE #define RTE_UART6_RS485_TRANSFER_MODE 2 #define RTE_UART6_RS485_DE_ASSERTION_TIME_8BIT (0x01) #define RTE_UART6_RS485_DE_DEASSERTION_TIME_8BIT (0x01) #define RTE_UART6_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) #define RTE_UART6_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) #endif // UART6 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART6 // Default: DISABLE #define RTE_UART6_DMA_ENABLE 0 // UART6 DMA Selection // <0=> DMA1(M55-HP) // <1=> DMA0 // Defines Select DMA0 for UART6. By default DMA0 will be considered // Default: DMA0 #define RTE_UART6_SELECT_DMA0 1 // UART6 DMA IRQ priority <0-255> // Defines UART6 DMA Interrupt priority // Default: 0 #define RTE_UART6_DMA_IRQ_PRI 0 // UART6 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART6 // Default: DISABLE #define RTE_UART6_BLOCKING_MODE_ENABLE 0 #endif //UART6 // UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] // UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] // Configuration settings for Driver_USART7 in component ::Drivers:USART #define RTE_UART7 1 #if RTE_UART7 // UART7 RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines UART7 receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_UART7_RX_TRIG_LVL 0 // UART7 TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines UART7 transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_UART7_TX_TRIG_LVL 0 // UART7 IRQ priority <0-255> // Defines Interrupt priority for UART7. // Default: 0 #define RTE_UART7_IRQ_PRI 0 // UART7 CLK SOURCE // <0=> CLK_38.4MHz // <1=> CLK_100MHz // Defines UART7 clock source. // Default: CLK_100MHz #define RTE_UART7_CLK_SOURCE 1 #define RTE_UART7_RS485_ENABLE 0 #if RTE_UART7_RS485_ENABLE #define RTE_UART7_RS485_TRANSFER_MODE 2 #define RTE_UART7_RS485_DE_ASSERTION_TIME_8BIT (0x01) #define RTE_UART7_RS485_DE_DEASSERTION_TIME_8BIT (0x01) #define RTE_UART7_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) #define RTE_UART7_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) #endif // UART7 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for UART7 // Default: DISABLE #define RTE_UART7_DMA_ENABLE 0 // UART7 DMA Selection // <0=> DMA1(M55-HP) // <1=> DMA0 // Defines Select DMA0 for UART7. By default DMA0 will be considered // Default: DMA0 #define RTE_UART7_SELECT_DMA0 1 // UART7 DMA IRQ priority <0-255> // Defines UART7 DMA Interrupt priority // Default: 0 #define RTE_UART7_DMA_IRQ_PRI 0 // UART7 blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for UART7 // Default: DISABLE #define RTE_UART7_BLOCKING_MODE_ENABLE 0 #endif //UART7 // UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] // LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] // Configuration settings for Driver_USARTLP in component ::Drivers:USART #if defined(M55_HE) #define RTE_LPUART 1 #endif #if RTE_LPUART // LPUART RX FIFO TRIGGER LEVEL // <0=> UART_RX_ONE_CHAR_IN_FIFO // <1=> UART_RX_FIFO_QUARTER_FULL // <2=> UART_RX_FIFO_HALF_FULL // <3=> UART_RX_FIFO_TWO_LESS_FULL // Defines LPUART receive fifo trigger level. // Default: UART_RX_ONE_CHAR_IN_FIFO #define RTE_LPUART_RX_TRIG_LVL 0 // LPUART TX FIFO TRIGGER LEVEL // <0=> UART_TX_FIFO_EMPTY // <1=> UART_TX_FIFO_CHAR_2 // <2=> UART_TX_FIFO_QUARTER_FULL // <3=> UART_TX_FIFO_HALF_FULL // Defines LPUART transmit fifo trigger level. // Default: UART_TX_FIFO_EMPTY #define RTE_LPUART_TX_TRIG_LVL 0 // LPUART IRQ priority <0-255> // Defines Interrupt priority for LPUART. // Default: 0 #define RTE_LPUART_IRQ_PRI 0 // LPUART DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for LPUART // Default: DISABLE #define RTE_LPUART_DMA_ENABLE 0 // LPUART DMA Selection // <0=> DMA2 // <1=> DMA0 // Defines Select DMA0 for LPUART. By default DMA0 will be considered // Default: DMA0 #define RTE_LPUART_SELECT_DMA0 1 // LPUART DMA IRQ priority <0-255> // Defines LPUART DMA Interrupt priority // Default: 0 #define RTE_LPUART_DMA_IRQ_PRI 0 // LPUART blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for LPUART // Default: DISABLE #define RTE_LPUART_BLOCKING_MODE_ENABLE 0 #endif //RTE_LPUART // LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] // UART (Universal asynchronous receiver transmitter) // LPTIMER (Low power timer) // LPTIMER (Low power timer) [Driver_LPTIMER] // Configuration settings for Driver_LPTIMER in component ::Drivers:LPTIMER #define RTE_LPTIMER 1 #if RTE_LPTIMER // LPTIMER CHANNEL 0 // Configuration settings for Driver_LPTIMER channel 0 in component ::Drivers:LPTIMER #define RTE_LPTIMER_CHANNEL0 1 // CHANNEL0 IRQ priority <0-255> // Defines Interrupt priority for LPTIMER channel 0. // Default: 0 #define RTE_LPTIMER_CHANNEL0_IRQ_PRIORITY (0) // CHANNEL0 FREE RUN feature // <0=> DISABLED // <1=> ENABLED // Defines whether free run feature is not enabled/disabled for channel0. // Default: DISABLED #define RTE_LPTIMER_CHANNEL0_FREE_RUN_MODE (0) // CHANNEL0 clock source // <0=> CLK_32768Hz // <1=> CLK_128KHz // <2=> EXT_CLK // Defines clock source for channel0. // Default: CLK_32768Hz #define RTE_LPTIMER_CHANNEL0_CLK_SRC (0) // LPTIMER CHANNEL 0 // LPTIMER CHANNEL 1 // Configuration settings for Driver_LPTIMER channel 1 in component ::Drivers:LPTIMER #define RTE_LPTIMER_CHANNEL1 1 // CHANNEL1 IRQ priority <0-255> // Defines Interrupt priority for LPTIMER channel 1. // Default: 0 #define RTE_LPTIMER_CHANNEL1_IRQ_PRIORITY (0) // CHANNEL1 FREE RUN feature // <0=> DISABLED // <1=> ENABLED // Defines whether free run feature is not enabled/disabled for channel1. // Default: DISABLED #define RTE_LPTIMER_CHANNEL1_FREE_RUN_MODE (0) // CHANNEL1 clock source // <0=> CLK_32768Hz // <1=> CLK_128KHz // <2=> EXT_CLK // <3=> CLK_CASCADE // Defines clock source for channel1. // Default: CLK_32768Hz #define RTE_LPTIMER_CHANNEL1_CLK_SRC (0) // LPTIMER CHANNEL 1 // LPTIMER CHANNEL 2 // Configuration settings for Driver_LPTIMER channel 2 in component ::Drivers:LPTIMER #define RTE_LPTIMER_CHANNEL2 1 // CHANNEL2 IRQ priority <0-255> // Defines Interrupt priority for LPTIMER channel 2. // Default: 0 #define RTE_LPTIMER_CHANNEL2_IRQ_PRIORITY (0) // CHANNEL2 FREE RUN feature // <0=> DISABLED // <1=> ENABLED // Defines whether free run feature is not enabled/disabled for channel2. // Default: DISABLED #define RTE_LPTIMER_CHANNEL2_FREE_RUN_MODE (0) // CHANNEL2 clock source // <0=> CLK_32768Hz // <1=> CLK_128KHz // <2=> EXT_CLK // Defines clock source for channel2. // Default: CLK_32768Hz #define RTE_LPTIMER_CHANNEL2_CLK_SRC (0) // LPTIMER CHANNEL 2 // LPTIMER CHANNEL 3 // Configuration settings for Driver_LPTIMER channel 3 in component ::Drivers:LPTIMER #define RTE_LPTIMER_CHANNEL3 1 // CHANNEL3 IRQ priority <0-255> // Defines Interrupt priority for LPTIMER channel 3. // Default: 0 #define RTE_LPTIMER_CHANNEL3_IRQ_PRIORITY (0) // CHANNEL3 FREE RUN feature // <0=> DISABLED // <1=> ENABLED // Defines whether free run feature is not enabled/disabled for channel3. // Default: DISABLED #define RTE_LPTIMER_CHANNEL3_FREE_RUN_MODE (0) // CHANNEL3 clock source // <0=> CLK_32768Hz // <1=> CLK_128KHz // <2=> EXT_CLK // <3=> CLK_CASCADE // Defines clock source for channel3. // Default: CLK_32768Hz #define RTE_LPTIMER_CHANNEL3_CLK_SRC (0) // LPTIMER CHANNEL 3 #endif /* RTE_LPTIMER */ // LPTIMER (Low power timer) [Driver_LPTIMER] // LPTIMER (Low power timer) // RTC (Real time clock) // RTC0 (Real time clock) [Driver_RTC0] // Configuration settings for Driver_RTC0 in component ::Drivers:RTC #define RTE_RTC0 1 #if RTE_RTC0 // RTC0 IRQ priority <0-255> // Defines Interrupt priority for RTC0. // Default: 0 #define RTE_RTC0_IRQ_PRI 0 #endif // RTC0 (Real time clock) [Driver_RTC0] // RTC (Real time clock) // WDT (Watchdog Timer) // WDT0 (Watchdog Timer) [Driver_WDT0] // Configuration settings for Driver_WDT0 in component ::Drivers:WDT #define RTE_WDT0 1 // WDT0 (Watchdog Timer) [Driver_WDT0] // WDT (Watchdog Timer) // UTIMER (Universal Timer) // UTIMER (Universal Timer) [Driver_UTIMER] // Configuration settings for Driver_UTIMER in component ::Drivers:UTIMER #define RTE_UTIMER 1 #if RTE_UTIMER // UTIMER CHANNEL 0 // Configuration settings for UTIMER channel 0 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL0 1 // CHANNEL0 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 0. // Default: DISABLED #define RTE_UTIMER_CHANNEL0_FIXED_BUFFER 0 // CHANNEL0 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 0. // Default: DISABLED #define RTE_UTIMER_CHANNEL0_DMA_CONTROL 0 // CHANNEL0 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 0. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL0_FAULT_TYPE 0 // CHANNEL0 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 0. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 // CHANNEL0 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 0. // Default: DISABLED #define RTE_UTIMER_CHANNEL0_DRIVER_A 1 // CHANNEL0 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 0. // Default: DISABLED #define RTE_UTIMER_CHANNEL0_DRIVER_B 0 // CHANNEL0 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 0. // Default: LOW #define RTE_UTIMER_CHANNEL0_DRV_A_START_STATE 0 // CHANNEL0 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 0. // Default: LOW #define RTE_UTIMER_CHANNEL0_DRV_A_STOP_STATE 0 // CHANNEL0 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 0. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL0 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 0. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL0 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 0. // Default: LOW #define RTE_UTIMER_CHANNEL0_DRV_B_START_STATE 0 // CHANNEL0 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 0. // Default: LOW #define RTE_UTIMER_CHANNEL0_DRV_B_STOP_STATE 0 // CHANNEL0 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 0. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL0 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 0. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL0 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 0. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL0_EVENT_AT_CREST 1 // CHANNEL0 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 0. // Default: DISABLE #define RTE_UTIMER_CHANNEL0_EVENT_AT_TROUGH 0 // CHANNEL0 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 0. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE 0 // CHANNEL0 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 0. // Default: ENABLE #define RTE_UTIMER_CHANNEL0_BUFFER_OPERATION 0 // CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 0 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_A 2 // CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 0 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_B 0 // CHANNEL0 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 0 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL0 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 0 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL0 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 0 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL0 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 0 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL0 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 0 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL0 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 0 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL0 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 0 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL0 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 0 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL0 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 0. // Default: DISABLE #define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 // CHANNEL0 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 0. // Default: DISABLE #define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 0 // UTIMER CHANNEL 1 // Configuration settings for UTIMER channel 1 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL1 1 // CHANNEL1 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 1. // Default: DISABLED #define RTE_UTIMER_CHANNEL1_FIXED_BUFFER 0 // CHANNEL1 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 1. // Default: DISABLED #define RTE_UTIMER_CHANNEL1_DMA_CONTROL 0 // CHANNEL1 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 1. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL1_FAULT_TYPE 0 // CHANNEL1 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 1. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 // CHANNEL1 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 1. // Default: DISABLED #define RTE_UTIMER_CHANNEL1_DRIVER_A 0 // CHANNEL1 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 1. // Default: DISABLED #define RTE_UTIMER_CHANNEL1_DRIVER_B 0 // CHANNEL1 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 1. // Default: LOW #define RTE_UTIMER_CHANNEL1_DRV_A_START_STATE 0 // CHANNEL1 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 1. // Default: LOW #define RTE_UTIMER_CHANNEL1_DRV_A_STOP_STATE 0 // CHANNEL1 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 1. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL1 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 1. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL1 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 1. // Default: LOW #define RTE_UTIMER_CHANNEL1_DRV_B_START_STATE 0 // CHANNEL1 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 1. // Default: LOW #define RTE_UTIMER_CHANNEL1_DRV_B_STOP_STATE 0 // CHANNEL1 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 1. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL1 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 1. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL1 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 1. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL1_EVENT_AT_CREST 1 // CHANNEL1 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 1. // Default: DISABLE #define RTE_UTIMER_CHANNEL1_EVENT_AT_TROUGH 0 // CHANNEL1 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 1. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE 1 // CHANNEL1 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 1. // Default: ENABLE #define RTE_UTIMER_CHANNEL1_BUFFER_OPERATION 1 // CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 1 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_A 0 // CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 1 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_B 0 // CHANNEL1 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 1 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL1_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL1 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 1 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL1_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL1 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 1 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL1_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL1 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 1 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL1_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL1 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 1 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL1_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL1 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 1 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL1_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL1 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 1 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL1_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL1 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 1 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL1_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL1 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 1. // Default: DISABLE #define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 // CHANNEL1 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 1. // Default: DISABLE #define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 1 // UTIMER CHANNEL 2 // Configuration settings for UTIMER channel 2 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL2 1 // CHANNEL2 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 2. // Default: DISABLED #define RTE_UTIMER_CHANNEL2_FIXED_BUFFER 0 // CHANNEL2 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 2. // Default: DISABLED #define RTE_UTIMER_CHANNEL2_DMA_CONTROL 0 // CHANNEL2 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 2. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL2_FAULT_TYPE 0 // CHANNEL2 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 2. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 // CHANNEL2 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 2. // Default: DISABLED #define RTE_UTIMER_CHANNEL2_DRIVER_A 0 // CHANNEL2 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 2. // Default: DISABLED #define RTE_UTIMER_CHANNEL2_DRIVER_B 0 // CHANNEL2 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 2. // Default: LOW #define RTE_UTIMER_CHANNEL2_DRV_A_START_STATE 0 // CHANNEL2 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 2. // Default: LOW #define RTE_UTIMER_CHANNEL2_DRV_A_STOP_STATE 0 // CHANNEL2 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 2. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL2 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 2. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL2 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 2. // Default: LOW #define RTE_UTIMER_CHANNEL2_DRV_B_START_STATE 0 // CHANNEL2 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 2. // Default: LOW #define RTE_UTIMER_CHANNEL2_DRV_B_STOP_STATE 0 // CHANNEL2 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 2. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL2 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 2. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL2 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 2. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL2_EVENT_AT_CREST 1 // CHANNEL2 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 2. // Default: DISABLE #define RTE_UTIMER_CHANNEL2_EVENT_AT_TROUGH 0 // CHANNEL2 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 2. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE 1 // CHANNEL2 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 2. // Default: ENABLE #define RTE_UTIMER_CHANNEL2_BUFFER_OPERATION 1 // CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 2 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_A 2 // CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 2 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_B 0 // CHANNEL2 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 2 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL2_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL2 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 2 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL2_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL2 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 2 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL2_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL2 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 2 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL2_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL2 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel2 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL2_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL2 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 2 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL2_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL2 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 2 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL2_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL2 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 2 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL2_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL2 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 2. // Default: DISABLE #define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 // CHANNEL2 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 2. // Default: DISABLE #define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 2 // UTIMER CHANNEL 3 // Configuration settings for UTIMER channel 3 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL3 1 // CHANNEL3 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 3. // Default: DISABLED #define RTE_UTIMER_CHANNEL3_FIXED_BUFFER 0 // CHANNEL3 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 0. // Default: DISABLED #define RTE_UTIMER_CHANNEL3_DMA_CONTROL 0 // CHANNEL3 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 3. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL3_FAULT_TYPE 0 // CHANNEL3 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 3. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL3_BUF_TROUGH_N_CREST 0 // CHANNEL3 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 3. // Default: DISABLED #define RTE_UTIMER_CHANNEL3_DRIVER_A 0 // CHANNEL3 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 3. // Default: DISABLED #define RTE_UTIMER_CHANNEL3_DRIVER_B 0 // CHANNEL3 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 3. // Default: LOW #define RTE_UTIMER_CHANNEL3_DRV_A_START_STATE 0 // CHANNEL3 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 3. // Default: LOW #define RTE_UTIMER_CHANNEL3_DRV_A_STOP_STATE 0 // CHANNEL3 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 3. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL3 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 3. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL3 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 3. // Default: LOW #define RTE_UTIMER_CHANNEL3_DRV_B_START_STATE 0 // CHANNEL3 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 3. // Default: LOW #define RTE_UTIMER_CHANNEL3_DRV_B_STOP_STATE 0 // CHANNEL3 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 3. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL3 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 3. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL3 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 3. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL3_EVENT_AT_CREST 1 // CHANNEL3 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 3. // Default: DISABLE #define RTE_UTIMER_CHANNEL3_EVENT_AT_TROUGH 0 // CHANNEL3 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 3. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE 0 // CHANNEL3 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 3. // Default: ENABLE #define RTE_UTIMER_CHANNEL3_BUFFER_OPERATION 0 // CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 3 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_A 0 // CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 3 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_B 0 // CHANNEL3 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 3 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL3_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL3 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 3 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL3_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL3 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 3 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL3_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL3 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 3 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL3_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL3 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 3 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL3_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL3 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 3 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL3_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL3 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 3 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL3_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL3 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 3 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL3_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL3 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 3. // Default: DISABLE #define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_ENABLE 0 // CHANNEL3 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 3. // Default: DISABLE #define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 3 // UTIMER CHANNEL 4 // Configuration settings for UTIMER channel 4 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL4 1 // CHANNEL4 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 4. // Default: DISABLED #define RTE_UTIMER_CHANNEL4_FIXED_BUFFER 0 // CHANNEL4 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 4. // Default: DISABLED #define RTE_UTIMER_CHANNEL4_DMA_CONTROL 0 // CHANNEL4 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 4. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL4_FAULT_TYPE 0 // CHANNEL4 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 1. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL4_BUF_TROUGH_N_CREST 0 // CHANNEL4 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 4. // Default: DISABLED #define RTE_UTIMER_CHANNEL4_DRIVER_A 1 // CHANNEL4 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 4. // Default: DISABLED #define RTE_UTIMER_CHANNEL4_DRIVER_B 0 // CHANNEL4 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 4. // Default: LOW #define RTE_UTIMER_CHANNEL4_DRV_A_START_STATE 0 // CHANNEL4 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 4. // Default: LOW #define RTE_UTIMER_CHANNEL4_DRV_A_STOP_STATE 0 // CHANNEL4 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 4. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL4 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 4. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL4 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 4. // Default: LOW #define RTE_UTIMER_CHANNEL4_DRV_B_START_STATE 0 // CHANNEL4 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 4. // Default: LOW #define RTE_UTIMER_CHANNEL4_DRV_B_STOP_STATE 0 // CHANNEL4 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 4. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL4 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 4. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL4 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 4. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL4_EVENT_AT_CREST 1 // CHANNEL4 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 4. // Default: DISABLE #define RTE_UTIMER_CHANNEL4_EVENT_AT_TROUGH 1 // CHANNEL4 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 4. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE 1 // CHANNEL4 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 4. // Default: ENABLE #define RTE_UTIMER_CHANNEL4_BUFFER_OPERATION 1 // CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 4 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_A 2 // CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 4 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_B 2 // CHANNEL4 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 4 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL4_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL4 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 4 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL4_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL4 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 4 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL4_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL4 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 4 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL4_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL4 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 4 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL4_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL4 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 4 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL4_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL4 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 4 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL4_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL4 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 4 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL4_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL4 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 4. // Default: DISABLE #define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_ENABLE 0 // CHANNEL4 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 4. // Default: DISABLE #define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 4 // UTIMER CHANNEL 5 // Configuration settings for UTIMER channel 5 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL5 1 // CHANNEL5 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 5. // Default: DISABLED #define RTE_UTIMER_CHANNEL5_FIXED_BUFFER 0 // CHANNEL5 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 4. // Default: DISABLED #define RTE_UTIMER_CHANNEL5_DMA_CONTROL 0 // CHANNEL5 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 5. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL5_FAULT_TYPE 0 // CHANNEL5 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 5. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL5_BUF_TROUGH_N_CREST 0 // CHANNEL5 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 5. // Default: DISABLED #define RTE_UTIMER_CHANNEL5_DRIVER_A 1 // CHANNEL5 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 5. // Default: DISABLED #define RTE_UTIMER_CHANNEL5_DRIVER_B 0 // CHANNEL5 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 5. // Default: LOW #define RTE_UTIMER_CHANNEL5_DRV_A_START_STATE 0 // CHANNEL5 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 5. // Default: LOW #define RTE_UTIMER_CHANNEL5_DRV_A_STOP_STATE 0 // CHANNEL5 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 5. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_MATCH_COUNT 3 // CHANNEL5 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 5. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_CYCLE_END 3 // CHANNEL5 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 5. // Default: LOW #define RTE_UTIMER_CHANNEL5_DRV_B_START_STATE 0 // CHANNEL5 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 5. // Default: LOW #define RTE_UTIMER_CHANNEL5_DRV_B_STOP_STATE 0 // CHANNEL5 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 5. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL5 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 5. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL5 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 5. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL5_EVENT_AT_CREST 1 // CHANNEL5 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 5. // Default: DISABLE #define RTE_UTIMER_CHANNEL5_EVENT_AT_TROUGH 0 // CHANNEL5 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 5. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE 1 // CHANNEL5 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 5. // Default: ENABLE #define RTE_UTIMER_CHANNEL5_BUFFER_OPERATION 1 // CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 5 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_A 2 // CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 5 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_B 0 // CHANNEL5 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 5 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL5_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL5 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 5 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL5_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL5 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 5 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL5_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL5 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 5 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL5_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL5 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 5 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL5_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL5 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 5 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL5_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL5 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 5 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL5_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL5 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 5 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL5_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL5 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 5. // Default: DISABLE #define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_ENABLE 0 // CHANNEL5 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 5. // Default: DISABLE #define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 5 // UTIMER CHANNEL 6 // Configuration settings for UTIMER channel 6 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL6 1 // CHANNEL6 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 6. // Default: DISABLED #define RTE_UTIMER_CHANNEL6_FIXED_BUFFER 0 // CHANNEL6 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 6. // Default: DISABLED #define RTE_UTIMER_CHANNEL6_DMA_CONTROL 0 // CHANNEL6 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 6. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL6_FAULT_TYPE 0 // CHANNEL6 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 6. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL6_BUF_TROUGH_N_CREST 0 // CHANNEL6 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 6. // Default: DISABLED #define RTE_UTIMER_CHANNEL6_DRIVER_A 1 // CHANNEL6 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 6. // Default: DISABLED #define RTE_UTIMER_CHANNEL6_DRIVER_B 0 // CHANNEL6 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 6. // Default: LOW #define RTE_UTIMER_CHANNEL6_DRV_A_START_STATE 0 // CHANNEL6 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 6. // Default: LOW #define RTE_UTIMER_CHANNEL6_DRV_A_STOP_STATE 0 // CHANNEL6 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 6. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_MATCH_COUNT 3 // CHANNEL6 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 6. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_CYCLE_END 3 // CHANNEL6 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 6. // Default: LOW #define RTE_UTIMER_CHANNEL6_DRV_B_START_STATE 0 // CHANNEL6 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 6. // Default: LOW #define RTE_UTIMER_CHANNEL6_DRV_B_STOP_STATE 0 // CHANNEL6 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 6. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL6 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 6. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL6 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 6. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL6_EVENT_AT_CREST 1 // CHANNEL6 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 6. // Default: DISABLE #define RTE_UTIMER_CHANNEL6_EVENT_AT_TROUGH 0 // CHANNEL6 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 6. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE 0 // CHANNEL6 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 6. // Default: ENABLE #define RTE_UTIMER_CHANNEL6_BUFFER_OPERATION 0 // CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 6 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_A 0 // CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 6 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_B 0 // CHANNEL6 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 6 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL6_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL6 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 6 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL6_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL6 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 6 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL6_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL6 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 6 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL6_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL6 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 6 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL6_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL6 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 6 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL6_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL6 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 6 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL6_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL6 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 6 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL6_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL6 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 6. // Default: DISABLE #define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_ENABLE 0 // CHANNEL6 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 6. // Default: DISABLE #define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 6 // UTIMER CHANNEL 7 // Configuration settings for UTIMER channel 7 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL7 1 // CHANNEL7 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 7. // Default: DISABLED #define RTE_UTIMER_CHANNEL7_FIXED_BUFFER 0 // CHANNEL7 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 7. // Default: DISABLED #define RTE_UTIMER_CHANNEL7_DMA_CONTROL 0 // CHANNEL7 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 7. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL7_FAULT_TYPE 0 // CHANNEL7 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 7. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL7_BUF_TROUGH_N_CREST 0 // CHANNEL7 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 7. // Default: DISABLED #define RTE_UTIMER_CHANNEL7_DRIVER_A 0 // CHANNEL7 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 7. // Default: DISABLED #define RTE_UTIMER_CHANNEL7_DRIVER_B 0 // CHANNEL7 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 7. // Default: LOW #define RTE_UTIMER_CHANNEL7_DRV_A_START_STATE 0 // CHANNEL7 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 7. // Default: LOW #define RTE_UTIMER_CHANNEL7_DRV_A_STOP_STATE 0 // CHANNEL7 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 7. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL7 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 7. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL7 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 7. // Default: LOW #define RTE_UTIMER_CHANNEL7_DRV_B_START_STATE 0 // CHANNEL7 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 7. // Default: LOW #define RTE_UTIMER_CHANNEL7_DRV_B_STOP_STATE 0 // CHANNEL7 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 7. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL7 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 7. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL7 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 7. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL7_EVENT_AT_CREST 1 // CHANNEL7 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 7. // Default: DISABLE #define RTE_UTIMER_CHANNEL7_EVENT_AT_TROUGH 0 // CHANNEL7 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 7. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE 1 // CHANNEL7 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 7. // Default: ENABLE #define RTE_UTIMER_CHANNEL7_BUFFER_OPERATION 1 // CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 7 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_A 2 // CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 7 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_B 0 // CHANNEL7 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 7 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL7_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL7 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 7 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL7_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL7 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 7 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL7_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL7 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 7 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL7_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL7 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 7 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL7_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL7 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 7 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL7_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL7 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 7 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL7_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL7 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 7 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL7_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL7 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 7. // Default: DISABLE #define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_ENABLE 0 // CHANNEL7 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 7. // Default: DISABLE #define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 7 // UTIMER CHANNEL 8 // Configuration settings for UTIMER channel 8 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL8 1 // CHANNEL8 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 8. // Default: DISABLED #define RTE_UTIMER_CHANNEL8_FIXED_BUFFER 0 // CHANNEL8 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 8. // Default: DISABLED #define RTE_UTIMER_CHANNEL8_DMA_CONTROL 0 // CHANNEL8 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 8. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL8_FAULT_TYPE 0 // CHANNEL8 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 8. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL8_BUF_TROUGH_N_CREST 0 // CHANNEL8 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 8. // Default: DISABLED #define RTE_UTIMER_CHANNEL8_DRIVER_A 1 // CHANNEL8 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 8. // Default: DISABLED #define RTE_UTIMER_CHANNEL8_DRIVER_B 0 // CHANNEL8 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 8. // Default: LOW #define RTE_UTIMER_CHANNEL8_DRV_A_START_STATE 0 // CHANNEL8 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 8. // Default: LOW #define RTE_UTIMER_CHANNEL8_DRV_A_STOP_STATE 0 // CHANNEL8 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 8. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_MATCH_COUNT 1 // CHANNEL8 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 8. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_CYCLE_END 2 // CHANNEL8 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 8. // Default: LOW #define RTE_UTIMER_CHANNEL8_DRV_B_START_STATE 0 // CHANNEL8 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 8. // Default: LOW #define RTE_UTIMER_CHANNEL8_DRV_B_STOP_STATE 0 // CHANNEL8 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 8. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL8 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 8. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL8 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 8. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL8_EVENT_AT_CREST 1 // CHANNEL8 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 8. // Default: DISABLE #define RTE_UTIMER_CHANNEL8_EVENT_AT_TROUGH 0 // CHANNEL8 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 8. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE 0 // CHANNEL8 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 8. // Default: ENABLE #define RTE_UTIMER_CHANNEL8_BUFFER_OPERATION 0 // CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 8 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_A 2 // CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 8 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_B 0 // CHANNEL8 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 8 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL8_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL8 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 8 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL8_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL8 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 8 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL8_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL8 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 8 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL8_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL8 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 8 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL8_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL8 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 8 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL8_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL8 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 8 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL8_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL8 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 8 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL8_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL8 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 8. // Default: DISABLE #define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_ENABLE 0 // CHANNEL8 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 8. // Default: DISABLE #define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 8 // UTIMER CHANNEL 9 // Configuration settings for UTIMER channel 9 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL9 1 // CHANNEL9 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 9. // Default: DISABLED #define RTE_UTIMER_CHANNEL9_FIXED_BUFFER 0 // CHANNEL9 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 9. // Default: DISABLED #define RTE_UTIMER_CHANNEL9_DMA_CONTROL 0 // CHANNEL9 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 9. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL9_FAULT_TYPE 0 // CHANNEL9 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 9. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL9_BUF_TROUGH_N_CREST 0 // CHANNEL9 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 9. // Default: DISABLED #define RTE_UTIMER_CHANNEL9_DRIVER_A 0 // CHANNEL9 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 9. // Default: DISABLED #define RTE_UTIMER_CHANNEL9_DRIVER_B 1 // CHANNEL9 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 9. // Default: LOW #define RTE_UTIMER_CHANNEL9_DRV_A_START_STATE 0 // CHANNEL9 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 9. // Default: LOW #define RTE_UTIMER_CHANNEL9_DRV_A_STOP_STATE 0 // CHANNEL9 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 9. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL9 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 9. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL9 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 9. // Default: LOW #define RTE_UTIMER_CHANNEL9_DRV_B_START_STATE 0 // CHANNEL9 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 9. // Default: LOW #define RTE_UTIMER_CHANNEL9_DRV_B_STOP_STATE 0 // CHANNEL9 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 9. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_MATCH_COUNT 1 // CHANNEL9 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 9. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_CYCLE_END 2 // CHANNEL9 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 9. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL9_EVENT_AT_CREST 1 // CHANNEL9 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 9. // Default: DISABLE #define RTE_UTIMER_CHANNEL9_EVENT_AT_TROUGH 0 // CHANNEL9 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 9. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE 0 // CHANNEL9 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 9. // Default: ENABLE #define RTE_UTIMER_CHANNEL9_BUFFER_OPERATION 0 // CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 9 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_A 0 // CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 9 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_B 0 // CHANNEL9 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 9 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL9_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL9 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 9 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL9_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL9 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 9 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL9_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL9 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 9 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL9_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL9 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 9 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL9_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL9 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 9 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL9_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL9 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 9 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL9_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL9 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 9 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL9_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL9 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 9. // Default: DISABLE #define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_ENABLE 0 // CHANNEL9 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 9. // Default: DISABLE #define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 9 // UTIMER CHANNEL 10 // Configuration settings for UTIMER channel 10 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL10 1 // CHANNEL10 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 10. // Default: DISABLED #define RTE_UTIMER_CHANNEL10_FIXED_BUFFER 0 // CHANNEL10 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 10. // Default: DISABLED #define RTE_UTIMER_CHANNEL10_DMA_CONTROL 0 // CHANNEL10 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 10. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL10_FAULT_TYPE 0 // CHANNEL10 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 10. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL10_BUF_TROUGH_N_CREST 0 // CHANNEL10 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 10. // Default: DISABLED #define RTE_UTIMER_CHANNEL10_DRIVER_A 1 // CHANNEL10 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 10. // Default: DISABLED #define RTE_UTIMER_CHANNEL10_DRIVER_B 0 // CHANNEL10 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 10. // Default: LOW #define RTE_UTIMER_CHANNEL10_DRV_A_START_STATE 0 // CHANNEL10 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 10. // Default: LOW #define RTE_UTIMER_CHANNEL10_DRV_A_STOP_STATE 0 // CHANNEL10 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 10. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_MATCH_COUNT 1 // CHANNEL10 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 10. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_CYCLE_END 2 // CHANNEL10 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 10. // Default: LOW #define RTE_UTIMER_CHANNEL10_DRV_B_START_STATE 0 // CHANNEL10 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 10. // Default: LOW #define RTE_UTIMER_CHANNEL10_DRV_B_STOP_STATE 0 // CHANNEL10 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 10. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL10 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 10. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL10 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 10. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL10_EVENT_AT_CREST 1 // CHANNEL10 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 10. // Default: DISABLE #define RTE_UTIMER_CHANNEL10_EVENT_AT_TROUGH 0 // CHANNEL10 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 10. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE 0 // CHANNEL10 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 10. // Default: ENABLE #define RTE_UTIMER_CHANNEL10_BUFFER_OPERATION 0 // CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 10 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_A 2 // CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 10 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_B 0 // CHANNEL10 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 10 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL10_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL10 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 10 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL10_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL10 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 10 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL10_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL10 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 10 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL10_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL10 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 10 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL10_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL10 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 10 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL10_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL10 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 10 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL10_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL10 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 10 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL10_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL10 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 10. // Default: DISABLE #define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_ENABLE 0 // CHANNEL10 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 10. // Default: DISABLE #define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 10 // UTIMER CHANNEL 11 // Configuration settings for UTIMER channel 11 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL11 1 // CHANNEL11 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 11. // Default: DISABLED #define RTE_UTIMER_CHANNEL11_FIXED_BUFFER 0 // CHANNEL11 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 11. // Default: DISABLED #define RTE_UTIMER_CHANNEL11_DMA_CONTROL 0 // CHANNEL11 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 11. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL11_FAULT_TYPE 0 // CHANNEL11 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 11. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL11_BUF_TROUGH_N_CREST 0 // CHANNEL11 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 11. // Default: DISABLED #define RTE_UTIMER_CHANNEL11_DRIVER_A 0 // CHANNEL11 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 11. // Default: DISABLED #define RTE_UTIMER_CHANNEL11_DRIVER_B 0 // CHANNEL11 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 11. // Default: LOW #define RTE_UTIMER_CHANNEL11_DRV_A_START_STATE 0 // CHANNEL11 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 11. // Default: LOW #define RTE_UTIMER_CHANNEL11_DRV_A_STOP_STATE 0 // CHANNEL11 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 11. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL11 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 11. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL11 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 11. // Default: LOW #define RTE_UTIMER_CHANNEL11_DRV_B_START_STATE 0 // CHANNEL11 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 11. // Default: LOW #define RTE_UTIMER_CHANNEL11_DRV_B_STOP_STATE 0 // CHANNEL11 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 11. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL11 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 11. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL11 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 11. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL11_EVENT_AT_CREST 1 // CHANNEL11 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 11. // Default: DISABLE #define RTE_UTIMER_CHANNEL11_EVENT_AT_TROUGH 0 // CHANNEL11 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 11. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE 1 // CHANNEL11 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 11. // Default: ENABLE #define RTE_UTIMER_CHANNEL11_BUFFER_OPERATION 1 // CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 11 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_A 2 // CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 11 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_B 0 // CHANNEL11 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 11 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL11_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL11 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 11 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL11_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL11 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 11 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL11_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL11 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 11 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL11_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL11 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 11 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL11_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL11 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 11 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL11_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL11 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 11 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL11_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL11 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 11 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL11_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL11 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 11. // Default: DISABLE #define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_ENABLE 0 // UTIMER CHANNEL 11 // UTIMER CHANNEL 12 // Configuration settings for UTIMER channel 12 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL12 1 // CHANNEL11 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 11. // Default: DISABLE #define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_VALUE 0 // CHANNEL12 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 12. // Default: DISABLED #define RTE_UTIMER_CHANNEL12_FIXED_BUFFER 0 // CHANNEL12 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 12. // Default: DISABLED #define RTE_UTIMER_CHANNEL12_DMA_CONTROL 0 // CHANNEL12 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 12. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL12_FAULT_TYPE 0 // CHANNEL12 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 12. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL12_BUF_TROUGH_N_CREST 0 // CHANNEL12 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 12. // Default: DISABLED #define RTE_UTIMER_CHANNEL12_DRIVER_A 1 // CHANNEL12 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 12. // Default: DISABLED #define RTE_UTIMER_CHANNEL12_DRIVER_B 0 // CHANNEL12 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 12. // Default: LOW #define RTE_UTIMER_CHANNEL12_DRV_A_START_STATE 0 // CHANNEL12 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 12. // Default: LOW #define RTE_UTIMER_CHANNEL12_DRV_A_STOP_STATE 0 // CHANNEL12 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 12. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL12 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 12. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL12 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 12. // Default: LOW #define RTE_UTIMER_CHANNEL12_DRV_B_START_STATE 0 // CHANNEL12 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 12. // Default: LOW #define RTE_UTIMER_CHANNEL12_DRV_B_STOP_STATE 0 // CHANNEL12 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 12. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL12 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 12. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL12 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 12. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL12_EVENT_AT_CREST 1 // CHANNEL12 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 12. // Default: DISABLE #define RTE_UTIMER_CHANNEL12_EVENT_AT_TROUGH 0 // CHANNEL12 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 12. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE 0 // CHANNEL12 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 12. // Default: ENABLE #define RTE_UTIMER_CHANNEL12_BUFFER_OPERATION 0 // CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 12 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_A 0 // CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 12 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_B 0 // CHANNEL12 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 12 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL12_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL12 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 12 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL12_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL12 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 12 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL12_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL12 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 12 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL12_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL12 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 12 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL12_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL12 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 12 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL12_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL12 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 12 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL12_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL12 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 12 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL12_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL12 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 12. // Default: DISABLE #define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_ENABLE 0 // CHANNEL12 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 12. // Default: DISABLE #define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 12 // UTIMER CHANNEL 13 // Configuration settings for UTIMER channel 13 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL13 1 // CHANNEL13 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 13. // Default: DISABLED #define RTE_UTIMER_CHANNEL13_FIXED_BUFFER 0 // CHANNEL13 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 13. // Default: DISABLED #define RTE_UTIMER_CHANNEL13_DMA_CONTROL 0 // CHANNEL13 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 13. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL13_FAULT_TYPE 0 // CHANNEL13 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 13. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL13_BUF_TROUGH_N_CREST 0 // CHANNEL13 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 13. // Default: DISABLED #define RTE_UTIMER_CHANNEL13_DRIVER_A 1 // CHANNEL13 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 13. // Default: DISABLED #define RTE_UTIMER_CHANNEL13_DRIVER_B 0 // CHANNEL13 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 13. // Default: LOW #define RTE_UTIMER_CHANNEL13_DRV_A_START_STATE 0 // CHANNEL13 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 13. // Default: LOW #define RTE_UTIMER_CHANNEL13_DRV_A_STOP_STATE 0 // CHANNEL13 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 13. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL13 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 13. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL13 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 13. // Default: LOW #define RTE_UTIMER_CHANNEL13_DRV_B_START_STATE 0 // CHANNEL13 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 13. // Default: LOW #define RTE_UTIMER_CHANNEL13_DRV_B_STOP_STATE 0 // CHANNEL13 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 13. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL13 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 13. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL13 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 13. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL13_EVENT_AT_CREST 1 // CHANNEL13 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 13. // Default: DISABLE #define RTE_UTIMER_CHANNEL13_EVENT_AT_TROUGH 0 // CHANNEL13 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 13. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE 0 // CHANNEL13 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 13. // Default: ENABLE #define RTE_UTIMER_CHANNEL13_BUFFER_OPERATION 0 // CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 13 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_A 0 // CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 13 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_B 0 // CHANNEL13 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 13 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL13_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL13 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 13 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL13_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL13 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 13 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL13_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL13 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 13 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL13_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL13 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 13 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL13_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL13 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 13 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL13_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL13 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 13 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL13_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL13 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 13 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL13_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL13 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 13. // Default: DISABLE #define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_ENABLE 0 // CHANNEL13 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 13. // Default: DISABLE #define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 13 // UTIMER CHANNEL 14 // Configuration settings for UTIMER channel 14 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL14 1 // CHANNEL14 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 14. // Default: DISABLED #define RTE_UTIMER_CHANNEL14_FIXED_BUFFER 0 // CHANNEL14 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 14. // Default: DISABLED #define RTE_UTIMER_CHANNEL14_DMA_CONTROL 0 // CHANNEL14 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 14. // Default: LOW_UNTIL_COUNTER_STOP #define RTE_UTIMER_CHANNEL14_FAULT_TYPE 0 // CHANNEL14 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 14. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL14_BUF_TROUGH_N_CREST 0 // CHANNEL14 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 14. // Default: DISABLED #define RTE_UTIMER_CHANNEL14_DRIVER_A 1 // CHANNEL14 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 14. // Default: DISABLED #define RTE_UTIMER_CHANNEL14_DRIVER_B 0 // CHANNEL14 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 14. // Default: LOW #define RTE_UTIMER_CHANNEL14_DRV_A_START_STATE 0 // CHANNEL14 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 14. // Default: LOW #define RTE_UTIMER_CHANNEL14_DRV_A_STOP_STATE 0 // CHANNEL14 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 14. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL14 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 14. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL14 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 14. // Default: LOW #define RTE_UTIMER_CHANNEL14_DRV_B_START_STATE 0 // CHANNEL14 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 14. // Default: LOW #define RTE_UTIMER_CHANNEL14_DRV_B_STOP_STATE 0 // CHANNEL14 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 14. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL14 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 14. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL14 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 14. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL14_EVENT_AT_CREST 1 // CHANNEL14 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 14. // Default: DISABLE #define RTE_UTIMER_CHANNEL14_EVENT_AT_TROUGH 0 // CHANNEL14 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 14. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE 0 // CHANNEL14 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 14. // Default: ENABLE #define RTE_UTIMER_CHANNEL14_BUFFER_OPERATION 0 // CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 14 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_A 0 // CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 14 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_B 0 // CHANNEL14 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 14 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL14_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL14 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 14 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL14_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL14 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 14 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL14_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL14 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 14 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL14_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL14 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 14 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL14_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL14 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 14 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL14_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL14 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 14 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL14_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL14 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 14 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL14_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL14 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 14. // Default: DISABLE #define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_ENABLE 0 // CHANNEL14 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 14. // Default: DISABLE #define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 14 // UTIMER CHANNEL 15 // Configuration settings for UTIMER channel 15 in component ::Drivers:UTIMER #define RTE_UTIMER_CHANNEL15 1 // CHANNEL15 FIXED BUFFER // <0=> DISABLED // <1=> ENABLED // Defines Fixed Buffer features for UT channel 15. // Default: DISABLED #define RTE_UTIMER_CHANNEL15_FIXED_BUFFER 0 // CHANNEL15 DMA CONTROL // <0=> DISABLED // <1=> ENABLED // Defines DMA feature control for UT channel 15. // Default: DISABLED #define RTE_UTIMER_CHANNEL15_DMA_CONTROL 0 // CHANNEL15 FAULT TYPE // <0=> LOW_UNTIL_CYCLE_END // <1=> LOW_UNTIL_COUNTER_STOP // Defines fault type for UT channel 15. // Default: LOW_UNTIL_CYCLE_END #define RTE_UTIMER_CHANNEL15_FAULT_TYPE 0 // CHANNEL15 TRIANGLE COUNTER BUFFER EVENT // <0=> BUF_AT_TROUGH // <1=> BUF_AT_TROUGH_N_CREST // Defines Buffer for triangle counter of UT channel 15. // Default: BUF_AT_TROUGH #define RTE_UTIMER_CHANNEL15_BUF_TROUGH_N_CREST 0 // CHANNEL15 DRIVER A // <0=> DISABLED // <1=> ENABLED // Defines Driver A state for UT channel 15. // Default: DISABLED #define RTE_UTIMER_CHANNEL15_DRIVER_A 1 // CHANNEL15 DRIVER B // <0=> DISABLED // <1=> ENABLED // Defines Driver B state for UT channel 15. // Default: DISABLED #define RTE_UTIMER_CHANNEL15_DRIVER_B 0 // CHANNEL15 DRIVER A START STATE // <0=> LOW // <1=> HIGH // Defines Driver A start state for UT channel 15. // Default: LOW #define RTE_UTIMER_CHANNEL15_DRV_A_START_STATE 0 // CHANNEL15 DRIVER A STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver A stop state for UT channel 15. // Default: LOW #define RTE_UTIMER_CHANNEL15_DRV_A_STOP_STATE 0 // CHANNEL15 DRIVER A AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at compare match for UT channel 15. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_MATCH_COUNT 0 // CHANNEL15 DRIVER A AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver A state at cycle end for UT channel 15. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_CYCLE_END 0 // CHANNEL15 DRIVER B START STATE // <0=> LOW // <1=> HIGH // Defines Driver B start state for UT channel 15. // Default: LOW #define RTE_UTIMER_CHANNEL15_DRV_B_START_STATE 0 // CHANNEL15 DRIVER B STOP STATE // <0=> LOW // <1=> HIGH // Defines Driver B stop state for UT channel 15. // Default: LOW #define RTE_UTIMER_CHANNEL15_DRV_B_STOP_STATE 0 // CHANNEL15 DRIVER B AT COMP MATCH // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at compare match for UT channel 15. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_MATCH_COUNT 0 // CHANNEL15 DRIVER B AT CYCLE END // <0=> NO CHANGE // <1=> LOW // <2=> HIGH // <3=> TOGGLE // Defines Driver B state at cycle end for UT channel 15. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_CYCLE_END 0 // CHANNEL15 BUFFER TRANSFER AT CREST // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at crest for UT channel 15. // Default: NO CHANGE #define RTE_UTIMER_CHANNEL15_EVENT_AT_CREST 1 // CHANNEL15 BUFFER TRANSFER AT TROUGH // <0=> DISABLE // <1=> ENABLE // Defines buffer transfer at trough for UT channel 15. // Default: DISABLE #define RTE_UTIMER_CHANNEL15_EVENT_AT_TROUGH 0 // CHANNEL15 BUFFERING TYPE // <0=> SINGLE BUFFER // <1=> DOUBLE BUFFER // Defines buffer type for UT channel 15. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE 0 // CHANNEL15 BUFFER OPERATION // <0=> DISABLE // <1=> ENABLE // Defines buffer operation for UT channel 15. // Default: ENABLE #define RTE_UTIMER_CHANNEL15_BUFFER_OPERATION 0 // CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER A // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 15 capture mode. // Default: DOUBLE BUFFER #define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_A 0 // CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER B // <0=> NO BUFFER // <1=> SINGLE BUFFER // <2=> DOUBLE BUFFER // Defines buffer operation for UT channel 15 capture mode. // Default: NO BUFFER #define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_B 0 // CHANNEL15 CAPTURE A IRQ priority <0-255> // Defines Interrupt priority for channel 15 capture A. // Default: 0 #define RTE_UTIMER_CHANNEL15_CAPTURE_A_IRQ_PRIORITY 0 // CHANNEL15 CAPTURE B IRQ priority <0-255> // Defines Interrupt priority for channel 15 capture B. // Default: 0 #define RTE_UTIMER_CHANNEL15_CAPTURE_B_IRQ_PRIORITY 0 // CHANNEL15 CAPTURE C IRQ priority <0-255> // Defines Interrupt priority for channel 15 capture C. // Default: 0 #define RTE_UTIMER_CHANNEL15_CAPTURE_C_IRQ_PRIORITY 0 // CHANNEL15 CAPTURE D IRQ priority <0-255> // Defines Interrupt priority for channel 15 capture D. // Default: 0 #define RTE_UTIMER_CHANNEL15_CAPTURE_D_IRQ_PRIORITY 0 // CHANNEL15 CAPTURE E IRQ priority <0-255> // Defines Interrupt priority for channel 15 capture E. // Default: 0 #define RTE_UTIMER_CHANNEL15_CAPTURE_E_IRQ_PRIORITY 0 // CHANNEL15 CAPTURE F IRQ priority <0-255> // Defines Interrupt priority for channel 15 capture F. // Default: 0 #define RTE_UTIMER_CHANNEL15_CAPTURE_F_IRQ_PRIORITY 0 // CHANNEL15 OVERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 15 overflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL15_OVER_FLOW_IRQ_PRIORITY 0 // CHANNEL15 UNDERFLOW IRQ priority <0-255> // Defines Interrupt priority for channel 15 underflow interrupt. // Default: 0 #define RTE_UTIMER_CHANNEL15_UNDER_FLOW_IRQ_PRIORITY 0 // CHANNEL15 DUTY CYCLE // <0=> DISABLE // <1=> ENABLE // Defines duty cycle for UT channel 15. // Default: DISABLE #define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_ENABLE 0 // CHANNEL15 DUTY CYCLE VALUE // <0=> COMP MATCH // <1=> COMP MATCH // <2=> 0 PERCENT // <3=> 100 PERCENT // Defines duty cycle value for UT channel 15. // Default: DISABLE #define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_VALUE 0 // UTIMER CHANNEL 15 #endif /*RTE_UTIMER*/ // UTIMER (Universal timer) [Driver_UTIMER] // UTIMER (Universal Timer) // Analog configuration [vbat analog register2 and comparator register2] #define RTE_ANALOG_CONFIG 1 #if RTE_ANALOG_CONFIG #define RTE_VBAT_ANA_REG2_VAL (0x388C4230) #define RTE_COMP_REG2_VAL (0x10200000 | 0x1C240100) #endif // Analog configuration [vbat analog register2 and comparator register2] // DAC (Digital to analog converter ) // DAC0 (Digital to analog converter ) [Driver_DAC0] // Configuration settings for Driver_DAC0 in component ::Drivers:DAC #define RTE_DAC0 1 #if RTE_DAC0 // DAC input through bypass mode // <0=> DISABLE (DAC input data source through DAC_IN reg) // <1=> ENABLE (DAC input data source through DAC_REG1 reg) // Default: DISABLE #define RTE_DAC0_INPUT_BYP_MUX_EN 0 // DAC converts two's complement to unsigned binary data // <0=> DISABLE(input will be positive) // DAC_out = (DAC_Input / 2^12) * Vref // DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v // 2^12 represents DAC supports 12 bit resolution. // <1=> ENABLE (Input can be positive or negative) // if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), // DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). // if dac_input > 2047 then, // DAC_out = ((dac_input - 2047) / 2^12) *vref // if dac_input < 2047 then, // DAC_out = ((dac_input + 2047) / 2^12) *vref // Default: DISABLE #define RTE_DAC0_TWOSCOMP_EN 0 #endif // DAC0 (Digital to analog converter) [Driver_DAC0] // DAC1 (Digital to analog converter ) [Driver_DAC1] // Configuration settings for Driver_DAC1 in component ::Drivers:DAC #define RTE_DAC1 1 #if RTE_DAC1 // DAC input through bypass mode // <0=> DISABLE (DAC input data source through DAC_IN reg) // <1=> ENABLE (DAC input data source through DAC_REG1 reg) // Default: DISABLE #define RTE_DAC1_INPUT_BYP_MUX_EN 0 // DAC converts two's complement to unsigned binary data // <0=> DISABLE(input will be positive) // DAC_out = (DAC_Input / 2^12) * Vref // DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v // 2^12 represents DAC supports 12 bit resolution. // <1=> ENABLE (Input can be positive or negative) // if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), // DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). // if dac_input > 2047 then, // DAC_out = ((dac_input - 2047) / 2^12) *vref // if dac_input < 2047 then, // DAC_out = ((dac_input + 2047) / 2^12) *vref // Default: DISABLE #define RTE_DAC1_TWOSCOMP_EN 0 #endif // DAC1 (Digital to Analog converter) [Driver_DAC1] // DAC(Digital to analog converter) // ADC (Analog to Digital Converter) // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] // Configuration settings for Driver_ADC120 in component ::Drivers:ADC12 #define RTE_ADC120 1 #if RTE_ADC120 #define RTE_ADC120_IRQ_PRIORITY 0 // ADC120 DONE0 IRQ PRIORITY <0-225> // defines ADC120 done0 interrupt priority // default: 0 #define RTE_ADC120_DONE0_IRQ_PRIORITY 0 // ADC120 DONE1 IRQ PRIORITY <0-225> // defines ADC120 interrupt priority // default: 0 #define RTE_ADC120_DONE1_IRQ_PRIORITY 0 // ADC120 CMPA IRQ PRIORITY <0-225> // defines ADC120 interrupt priority // default: 0 #define RTE_ADC120_CMPA_IRQ_PRIORITY 0 // ADC120 CMPB IRQ PRIORITY <0-225> // defines ADC120 interrupt priority // default: 0 #define RTE_ADC120_CMPB_IRQ_PRIORITY 0 // Input channel number <0-8> // Defines select input channel number. // Default: 0 #define RTE_ADC120_INPUT_NUM (0) // Clock Divider <2-16> // Defines Clock divider applied to main clock // Default: 2 #define RTE_ADC120_CLOCK_DIV (2) // Sample Width <2-32> // Defines Width in divided clocks of the sample output signal // Default: 16 #define RTE_ADC120_SAMPLE_WIDTH (16) // Number of average sample <0-256> // Defines Number of sample to be taken and it must be power of 2 // Default: 256 #define RTE_ADC120_AVG_SAMPLE_NUM (256) // Number of bits to shift <0-8> // Defines How much bit to shift before storing in sample register. // Default: 8 #define RTE_ADC120_SHIFT_N_BIT (0) // Left or Right shift // <0=> LEFT SHIFT // <1=> RIGHT SHIFT // Defines shift averaged value before loading in sample register. // Default: RIGHT SHIFT #define RTE_ADC120_SHIFT_LEFT_OR_RIGHT (1) // RTE_ADC120_DIFFERENTIAL_EN // Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all single ended #define RTE_ADC120_DIFFERENTIAL_EN 0 // Enable PGA // <0=> DISABLE // <1=> ENABLE // Defines Enable ADC120 PGA enable // Default: DISABLE #define RTE_ADC120_PGA_EN (0) // PGA gain value // <0=> 0 dB // <1=> 6 dB // <2=> 12 dB // <3=> 18 dB // <4=> 24 dB // <5=> 30 dB // <6=> 36 dB // <7=> 42 dB // Defines Select PGA gain value // Default: 0 #define RTE_ADC120_PGA_GAIN (0) // RTE_ADC121_DIFFERENTIAL_EN // Comparator mode enable // <0=> DISABLE // <1=> ENABLE // Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" // Default: ENABLE #define RTE_ADC120_COMPARATOR_EN 1 // Comparator bias enable // <0=> 0.5MS/s // <1=> 1MS/s // <2=> 2.5MS/s // <3=> 5MS/s // Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] // Configuration settings for Driver_ADC121 in component ::Drivers:ADC #define RTE_ADC121 1 #if RTE_ADC121 // ADC121 DONE0 IRQ PRIORITY <0-225> // defines ADC121 done0 interrupt priority // default: 0 #define RTE_ADC121_DONE0_IRQ_PRIORITY 0 // ADC121 DONE1 IRQ PRIORITY <0-225> // defines ADC121 interrupt priority // default: 0 #define RTE_ADC121_DONE1_IRQ_PRIORITY 0 // ADC121 CMPA IRQ PRIORITY <0-225> // defines ADC121 interrupt priority // default: 0 #define RTE_ADC121_CMPA_IRQ_PRIORITY 0 // ADC121 CMPB IRQ PRIORITY <0-225> // defines ADC121 interrupt priority // default: 0 #define RTE_ADC121_CMPB_IRQ_PRIORITY 0 // Input channel number <0-8> // Defines select input channel number. // Default: 0 #define RTE_ADC121_INPUT_NUM (0) // Clock Divider <2-16> // Defines Clock divider applied to main clock // Default: 2 #define RTE_ADC121_CLOCK_DIV (2) // Sample Width <2-32> // Defines Width in divided clocks of the sample output signal // Default: 16 #define RTE_ADC121_SAMPLE_WIDTH (16) // Number of average sample <0-256> // Defines Number of sample to be taken and it must be power of 2 // Default: 256 #define RTE_ADC121_AVG_SAMPLE_NUM (256) // Number of bits to shift <0-8> // Defines How much bit to shift before storing in sample register. // Default: 8 #define RTE_ADC121_SHIFT_N_BIT (8) // Left or Right shift // <0=> LEFT SHIFT // <1=> RIGHT SHIFT // Defines shift averaged value before loading in sample register. // Default: RIGHT SHIFT #define RTE_ADC121_SHIFT_LEFT_OR_RIGHT (1) // RTE_ADC121_DIFFERENTIAL_EN // Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all single ended #define RTE_ADC121_DIFFERENTIAL_EN 0 // Pga enable // <0=> DISABLE // <1=> ENABLE // Defines Enable ADC121 using PGA gain // Default: DISABLE #define RTE_ADC121_PGA_EN (0) // PGA gain value // <0=> 0 dB // <1=> 6 dB // <2=> 12 dB // <3=> 18 dB // <4=> 24 dB // <5=> 30 dB // <6=> 36 dB // <7=> 42 dB // Defines Select PGA gain value // Default: 0 #define RTE_ADC121_PGA_GAIN (0) // RTE_ADC121_DIFFERENTIAL_EN // Comparator mode enable // <0=> DISABLE // <1=> ENABLE // Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" // Default: ENABLE #define RTE_ADC121_COMPARATOR_EN 1 // Comparator bias enable // <0=> 0.5MS/s // <1=> 1MS/s // <2=> 2.5MS/s // <3=> 5MS/s // Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] // Configuration settings for Driver_ADC122 in component ::Drivers:ADC #define RTE_ADC122 1 #if RTE_ADC122 // ADC122 DONE0 IRQ PRIORITY <0-225> // defines ADC122 done0 interrupt priority // default: 0 #define RTE_ADC122_DONE0_IRQ_PRIORITY 0 // ADC122 DONE1 IRQ PRIORITY <0-225> // defines ADC122 interrupt priority // default: 0 #define RTE_ADC122_DONE1_IRQ_PRIORITY 0 // ADC122 CMPA IRQ PRIORITY <0-225> // defines ADC122 interrupt priority // default: 0 #define RTE_ADC122_CMPA_IRQ_PRIORITY 0 // ADC122 CMPB IRQ PRIORITY <0-225> // defines ADC122 interrupt priority // default: 0 #define RTE_ADC122_CMPB_IRQ_PRIORITY 0 // Input channel number <0-8> // Defines select input channel number. // Default: 0 #define RTE_ADC122_INPUT_NUM (0) // Clock Divider <2-16> // Defines Clock divider applied to main clock // Default: 2 #define RTE_ADC122_CLOCK_DIV (2) // Sample Width <2-32> // defines Width in divided clocks of the sample output signal // default: 16 #define RTE_ADC122_SAMPLE_WIDTH (16) // Number of average sample <0-256> // Defines Number of sample to be taken and it must be power of 2 // Default: 256 #define RTE_ADC122_AVG_SAMPLE_NUM (256) // Number of bits to shift <0-8> // Defines How much bit to shift before storing in sample register. // Default: 8 #define RTE_ADC122_SHIFT_N_BIT (8) // Left or Right shift // <0=> LEFT SHIFT // <1=> RIGHT SHIFT // Defines shift averaged value before loading in sample register. // Default: RIGHT SHIFT #define RTE_ADC122_SHIFT_LEFT_OR_RIGHT (1) // RTE_ADC122_DIFFERENTIAL_EN // Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all single ended #define RTE_ADC122_DIFFERENTIAL_EN 0 // Enable PGA ADC122 // <0=> DISABLE // <1=> ENABLE // Defines Enable ADC122 using PGA gain // Default: DISABLE #define RTE_ADC122_PGA_EN (0) // PGA gain value // <0=> 0 dB // <1=> 6 dB // <2=> 12 dB // <3=> 18 dB // <4=> 24 dB // <5=> 30 dB // <6=> 36 dB // <7=> 42 dB // Defines Select PGA gain value // Default: 0 #define RTE_ADC122_PGA_GAIN (0) // RTE_ADC122_DIFFERENTIAL_EN // Comparator mode enable // <0=> DISABLE // <1=> ENABLE // Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" // Default: ENABLE #define RTE_ADC122_COMPARATOR_EN 1 // Comparator bias enable // <0=> 0.5MS/s // <1=> 1MS/s // <2=> 2.5MS/s // <3=> 5MS/s // Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // Configuration settings for Driver_ADC24 in component ::Drivers:ADC #define RTE_ADC24 1 #if RTE_ADC24 // ADC24 DONE0 IRQ PRIORITY <0-225> // defines ADC24 done0 interrupt priority // default: 0 #define RTE_ADC24_DONE0_IRQ_PRIORITY 0 // ADC24 DONE1 IRQ PRIORITY <0-225> // defines ADC24 interrupt priority // default: 0 #define RTE_ADC24_DONE1_IRQ_PRIORITY 0 // ADC24 CMPA IRQ PRIORITY <0-225> // defines ADC24 interrupt priority // default: 0 #define RTE_ADC24_CMPA_IRQ_PRIORITY 0 // ADC24 CMPB IRQ PRIORITY <0-225> // defines ADC24 interrupt priority // default: 0 #define RTE_ADC24_CMPB_IRQ_PRIORITY 0 // Input channel number <0-4> // Defines select input channel number. // Default: 0 #define RTE_ADC24_INPUT_NUM (0) // Clock Divider <2-16> // Defines Clock divider applied to main clock // Default: 2 #define RTE_ADC24_CLOCK_DIV (2) // Number of average sample <0-256> // Defines Number of sample to be taken and it must be power of 2 // Default: 256 #define RTE_ADC24_AVG_SAMPLE_NUM (256) // Number of bits to shift <0-8> // Defines How much bit to shift before storing in sample register. // Default: 8 #define RTE_ADC24_SHIFT_N_BIT (8) // Left or Right shift // <0=> LEFT SHIFT // <1=> RIGHT SHIFT // Defines shift averaged value before loading in sample register. // Default: RIGHT SHIFT #define RTE_ADC24_SHIFT_LEFT_OR_RIGHT (1) // Ouput rate select // <0=> 1 KS/s // <1=> 2 KS/s // <2=> 4 KS/s // <3=> 8 KS/s // <4=> 16 KS/s // Defines Select adc24 output rate // Default: 0 #define RTE_ADC24_OUTPUT_RATE (0) // PGA enable // <0=> DISABLE // <1=> ENABLE // Defines Enable PGA to set PGA gain // Default: DISABLE #define RTE_ADC24_PGA_EN (0) // PGA gain value // <0=> 0 dB // <1=> 6 dB // <2=> 12 dB // <3=> 18 dB // <4=> 24 dB // <5=> 30 dB // <6=> 36 dB // <7=> 42 dB // Defines Select PGA gain value // Default: 0 #define RTE_ADC24_PGA_GAIN (0) // Bias Control // <0=> 5 uA // <1=> 6.25 uA // <3=> 7.5 uA // <7=> 8.75 uA // Defines Bias control // Default: 3 #define RTE_ADC24_BIAS (3) #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) // CRC (Cyclic Redundancy Check) // CRC0 (Cyclic Redundancy Check) [Driver_CRC0] // Configuration settings for Driver_CRC0 in component ::Drivers:CRC #define RTE_CRC0 1 #if RTE_CRC0 // CRC0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for CRC0 // Default: 0 #define RTE_CRC0_DMA_ENABLE 0 #if RTE_CRC0_DMA_ENABLE // CRC0 DMA Selection // <0=> DMA0 // <1=> DMA1 // <2=> DMA2 // Defines Select DMA for CRC0. By default DMA0 will be considered // Default: 0 #define RTE_CRC0_SELECT_DMA 0 #endif // CRC0 DMA IRQ priority <0-255> // Defines CRC0 DMA Interrupt priority // Default: 0 #define RTE_CRC0_DMA_IRQ_PRI 0 #endif // CRC0 (Cyclic Redundancy Check) [Driver_CRC0] // CRC1 (Cyclic Redundancy Check) [Driver_CRC1] // Configuration settings for Driver_CRC1 in component ::Drivers:CRC #define RTE_CRC1 1 #if RTE_CRC1 // CRC1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for CRC1 // Default: 0 #define RTE_CRC1_DMA_ENABLE 0 #if RTE_CRC1_DMA_ENABLE // CRC1 DMA Selection // <0=> DMA0 // <1=> DMA1 // <2=> DMA2 // Defines Select DMA for CRC1. By default DMA0 will be considered // Default: 0 #define RTE_CRC1_SELECT_DMA 0 #endif // CRC1 DMA IRQ priority <0-255> // Defines CRC1 DMA Interrupt priority // Default: 0 #define RTE_CRC1_DMA_IRQ_PRI 0 #endif // CRC1 (Cyclic Redundancy Check) [Driver_CRC1] // // HWSEM (Hardware Semaphore) // HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] // Configuration settings for Driver_HWSEM0 in component ::Drivers:HWSEM #define RTE_HWSEM0 1 #if RTE_HWSEM0 // HWSEM0 IRQ priority <0-255> // Defines HWSEM0 Interrupt priority // Default: 0 #define RTE_HWSEM0_IRQPRIORITY 0 #endif // HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] // HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] // Configuration settings for Driver_HWSEM1 in component ::Drivers:HWSEM #define RTE_HWSEM1 0 #if RTE_HWSEM1 // HWSEM1 IRQ priority <0-255> // Defines HWSEM1 Interrupt priority // Default: 0 #define RTE_HWSEM1_IRQPRIORITY 0 #endif // HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] // HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] // Configuration settings for Driver_HWSEM2 in component ::Drivers:HWSEM #define RTE_HWSEM2 0 #if RTE_HWSEM2 // HWSEM2 IRQ priority <0-255> // Defines HWSEM2 Interrupt priority // Default: 0 #define RTE_HWSEM2_IRQPRIORITY 0 #endif // HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] // HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] // Configuration settings for Driver_HWSEM3 in component ::Drivers:HWSEM #define RTE_HWSEM3 0 #if RTE_HWSEM3 // HWSEM3 IRQ priority <0-255> // Defines HWSEM3 Interrupt priority // Default: 0 #define RTE_HWSEM3_IRQPRIORITY 0 #endif // HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] // HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] // Configuration settings for Driver_HWSEM4 in component ::Drivers:HWSEM #define RTE_HWSEM4 0 #if RTE_HWSEM4 // HWSEM4 IRQ priority <0-255> // Defines HWSEM4 Interrupt priority // Default: 0 #define RTE_HWSEM4_IRQPRIORITY 0 #endif // HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] // HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] // Configuration settings for Driver_HWSEM5 in component ::Drivers:HWSEM #define RTE_HWSEM5 0 #if RTE_HWSEM5 // HWSEM5 IRQ priority <0-255> // Defines HWSEM5 Interrupt priority // Default: 0 #define RTE_HWSEM5_IRQPRIORITY 0 #endif // HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] // HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] // Configuration settings for Driver_HWSEM6 in component ::Drivers:HWSEM #define RTE_HWSEM6 0 #if RTE_HWSEM6 // HWSEM6 IRQ priority <0-255> // Defines HWSEM6 Interrupt priority // Default: 0 #define RTE_HWSEM6_IRQPRIORITY 0 #endif // HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] // HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] // Configuration settings for Driver_HWSEM7 in component ::Drivers:HWSEM #define RTE_HWSEM7 0 #if RTE_HWSEM7 // HWSEM7 IRQ priority <0-255> // Defines HWSEM7 Interrupt priority // Default: 0 #define RTE_HWSEM7_IRQPRIORITY 0 #endif // HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] // HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] // Configuration settings for Driver_HWSEM8 in component ::Drivers:HWSEM #define RTE_HWSEM8 0 #if RTE_HWSEM8 // HWSEM8 IRQ priority <0-255> // Defines HWSEM8 Interrupt priority // Default: 0 #define RTE_HWSEM8_IRQPRIORITY 0 #endif // HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] // HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] // Configuration settings for Driver_HWSEM9 in component ::Drivers:HWSEM #define RTE_HWSEM9 0 #if RTE_HWSEM9 // HWSEM9 IRQ priority <0-255> // Defines HWSEM9 Interrupt priority // Default: 0 #define RTE_HWSEM9_IRQPRIORITY 0 #endif // HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] // HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] // Configuration settings for Driver_HWSEM10 in component ::Drivers:HWSEM #define RTE_HWSEM10 0 #if RTE_HWSEM10 // HWSEM10 IRQ priority <0-255> // Defines HWSEM10 Interrupt priority // Default: 0 #define RTE_HWSEM10_IRQPRIORITY 0 #endif // HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] // HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] // Configuration settings for Driver_HWSEM11 in component ::Drivers:HWSEM #define RTE_HWSEM11 0 #if RTE_HWSEM11 // HWSEM11 IRQ priority <0-255> // Defines HWSEM11 Interrupt priority // Default: 0 #define RTE_HWSEM11_IRQPRIORITY 0 #endif // HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] // HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] // Configuration settings for Driver_HWSEM12 in component ::Drivers:HWSEM #define RTE_HWSEM12 0 #if RTE_HWSEM12 // HWSEM12 IRQ priority <0-255> // Defines HWSEM12 Interrupt priority // Default: 0 #define RTE_HWSEM12_IRQPRIORITY 0 #endif // HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] // HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] // Configuration settings for Driver_HWSEM13 in component ::Drivers:HWSEM #define RTE_HWSEM13 0 #if RTE_HWSEM13 // HWSEM13 IRQ priority <0-255> // Defines HWSEM13 Interrupt priority // Default: 0 #define RTE_HWSEM13_IRQPRIORITY 0 #endif // HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] // HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] // Configuration settings for Driver_HWSEM14 in component ::Drivers:HWSEM #define RTE_HWSEM14 0 #if RTE_HWSEM14 // HWSEM14 IRQ priority <0-255> // Defines HWSEM14 Interrupt priority // Default: 0 #define RTE_HWSEM14_IRQPRIORITY 0 #endif // HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] // HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] // Configuration settings for Driver_HWSEM15 in component ::Drivers:HWSEM #define RTE_HWSEM15 0 #if RTE_HWSEM15 // HWSEM15 IRQ priority <0-255> // Defines HWSEM15 Interrupt priority // Default: 0 #define RTE_HWSEM15_IRQPRIORITY 0 #endif // HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] // // High speed Analog Comparator // CMP0 (Analog Comparator ) [Driver_CMP0] // Configuration settings for Driver_CMP0 in component ::Drivers:Comparator #define RTE_HSCMP0 1 #if RTE_HSCMP0 // CMP0 IRQ priority <0-255> // Defines Interrupt priority for CMP0. // Default: 0 #define RTE_CMP0_IRQ_PRIORITY 0 // Select positive terminal // <0=> PIN_P0_0 // <1=> PIN_P0_6 // <2=> PIN_P1_4 // <3=> PIN_P0_4 // Defines:select input to the positive terminal of comparator; // 00 = P0_0; 01 = P0_6; 10 = P1_4; 11 = P0_4 // Default : 0 #define RTE_CMP0_SEL_POSITIVE 0 // Select negative terminal // <0=> PIN_P2_0 // <1=> PIN_P2_1 // <2=> PIN_INT_VREF // <3=> PIN_DAC6 // Defines: select input to the negative terminal of comparator; // 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 // Default : 3 #define RTE_CMP0_SEL_NEGATIVE 3 // Select Hysteresis level // <0=> 0mV // <1=> 6mV // <2=> 12mV // <3=> 18mV // <4=> 24mV // <5=> 30mV // <6=> 36mV // <7=> 42mV // Defines: Select comparator hysteresis level, step size is 6mv; // 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; // 110 = 36mv; 111 = 42mV // Default: 7 #define RTE_CMP0_SEL_HYSTERISIS 7 #endif // CMP0 (Analog Comparator) [Driver_CMP0] // CMP1 (Analog Comparator ) [Driver_CMP1] // Configuration settings for Driver_CMP1 in component ::Drivers:Comparator #define RTE_HSCMP1 1 #if RTE_HSCMP1 // CMP1 IRQ priority <0-255> // Defines Interrupt priority for CMP1. // Default: 0 #define RTE_CMP1_IRQ_PRIORITY 0 // Select positive terminal // <0=> PIN_P0_1 // <1=> PIN_P0_7 // <2=> PIN_P1_5 // <3=> PIN_P0_5 // Defines:select input to the positive terminal of comparator; // 00 = P0_1; 01 = P0_7; 10 = P1_5; 11 = P0_5 // Default : 0 #define RTE_CMP1_SEL_POSITIVE 0 // Select negative terminal // <0=> PIN_P2_0 // <1=> PIN_P2_1 // <2=> PIN_INT_VREF // <3=> PIN_DAC6 // Defines: select input to the negative terminal of comparator; // 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 // Default : 3 #define RTE_CMP1_SEL_NEGATIVE 3 // Select Hysteresis level // <0=> 0mV // <1=> 6mV // <2=> 12mV // <3=> 18mV // <4=> 24mV // <5=> 30mV // <6=> 36mV // <7=> 42mV // Defines: Select comparator hysteresis level, step size is 6mv; // 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; // 110 = 36mv; 111 = 42mV // Default: 7 #define RTE_CMP1_SEL_HYSTERISIS 7 #endif // CMP1 (Analog Comparator) [Driver_CMP1] // CMP2 (Analog Comparator ) [Driver_CMP2] // Configuration settings for Driver_CMP2 in component ::Drivers:Comparator #define RTE_HSCMP2 1 #if RTE_HSCMP2 // CMP2 IRQ priority <0-255> // Defines Interrupt priority for CMP2. // Default: 0 #define RTE_CMP2_IRQ_PRIORITY 0 // Select positive terminal // <0=> PIN_P0_2 // <1=> PIN_P1_0 // <2=> PIN_P1_6 // <3=> PIN_P1_2 // Defines:select input to the positive terminal of comparator; // 00 = P0_2; 01 = P1_0; 10 = P1_6; 11 = P1_2 // Default : 0 #define RTE_CMP2_SEL_POSITIVE 0 // Select negative terminal // <0=> PIN_P2_0 // <1=> PIN_P2_1 // <2=> PIN_INT_VREF // <3=> PIN_DAC6 // Defines: select input to the negative terminal of comparator; // 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 // Default : 3 #define RTE_CMP2_SEL_NEGATIVE 3 // Select Hysteresis level // <0=> 0mV // <1=> 6mV // <2=> 12mV // <3=> 18mV // <4=> 24mV // <5=> 30mV // <6=> 36mV // <7=> 42mV // Defines: Select comparator hysteresis level, step size is 6mv; // 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; // 110 = 36mv; 111 = 42mV // Default: 7 #define RTE_CMP2_SEL_HYSTERISIS 7 #endif // CMP2 (Analog Comparator) [Driver_CMP2] // CMP3 (Analog Comparator ) [Driver_CMP3] // Configuration settings for Driver_CMP3 in component ::Drivers:Comparator #define RTE_HSCMP3 1 #if RTE_HSCMP3 // CMP3 IRQ priority <0-255> // Defines Interrupt priority for CMP3. // Default: 0 #define RTE_CMP3_IRQ_PRIORITY 0 // Select positive terminal // <0=> PIN_P0_3 // <1=> PIN_P1_1 // <2=> PIN_P1_7 // <3=> PIN_P1_3 // Defines:select input to the positive terminal of comparator; // 00 = P0_3; 01 = P1_1; 10 = P1_7; 11 = P1_3 // Default : 0 #define RTE_CMP3_SEL_POSITIVE 0 // Select negative terminal // <0=> PIN_P2_0 // <1=> PIN_P2_1 // <2=> PIN_INT_VREF // <3=> PIN_DAC6 // Defines: select input to the negative terminal of comparator; // 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 // Default : 3 #define RTE_CMP3_SEL_NEGATIVE 3 // Select Hysteresis level // <0=> 0mV // <1=> 6mV // <2=> 12mV // <3=> 18mV // <4=> 24mV // <5=> 30mV // <6=> 36mV // <7=> 42mV // Defines: Select comparator hysteresis level, step size is 6mv; // 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; // 110 = 36mv; 111 = 42mV // Default: 7 #define RTE_CMP3_SEL_HYSTERISIS 7 #endif // CMP3 (Analog Comparator) [Driver_CMP3] #if defined(M55_HE) // LPCMP (Low Power Analog Comparator) [Driver_LPCMP] // Configuration settings for Driver_LPCMP in component ::Drivers:LPCMP #define RTE_LPCMP 1 #if RTE_LPCMP // LPCMP IRQ priority <0-255> // Defines Interrupt priority for LPCMP. // Default: 0 #define RTE_LPCMP_IRQ_PRIORITY 0 // Select positive terminal // <0=> PIN_P2_4 // <1=> PIN_P2_5 // <2=> PIN_P2_6 // <3=> PIN_P2_7 // Defines:select input to the positive terminal of LPCMP; // 00 = P2_4; 01 = P2_5; 10 = P2_6; 11 = P2_7 // Default : 0 #define RTE_LPCMP_SEL_POSITIVE 0 // Select negative terminal // <0=> AON_VREF // <1=> PIN_P2_0 // <2=> PIN_P2_1 // <3=> PIN_P2_2 // Defines: select input to the negative terminal of LPCMP; // 00 = AON Vref(0.8v); 01 = P2_0; 10 = P2_1 Vref; 11 = P2_2 // Default : 0 #define RTE_LPCMP_SEL_NEGATIVE 0 // Select Hysteresis level // <0=> 0mV // <1=> 6mV // <2=> 12mV // <3=> 18mV // <4=> 24mV // <5=> 30mV // <6=> 36mV // <7=> 42mV // Defines: Select LPCMP hysteresis level, step size is 6mv; // 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; // 110 = 36mv; 111 = 42mV // Default: 7 #define RTE_LPCMP_SEL_HYSTERISIS 7 #endif // LPCMP (Low Power Analog Comparator) [Driver_LPCMP] #endif //defined(M55_HE) // CMP (Analog Comparator) // I2C (Inter Integrated Circuit) // I2C (Inter Integrated Circuit) [Driver_I2C0] // Configuration settings for Driver_I2C0 in component ::Drivers:I2C #define RTE_I2C0 1 #if RTE_I2C0 // I2C0 IRQ priority <0-255> // Defines Interrupt priority for I2C0. // Default: 0 #define RTE_I2C0_IRQ_PRIORITY 0 // I2C0 TX FIFO threshold <0-31> // Defines TX FIFO threshold for I2C0. // Default: 16 #define RTE_I2C0_TX_FIFO_THRESHOLD 16 // I2C0 RX FIFO threshold <0-31> // Defines RX FIFO threshold for I2C0. // Default: 16 #define RTE_I2C0_RX_FIFO_THRESHOLD 16 #endif // I2C (Inter Integrated Circuit) [Driver_I2C0] // I2C (Inter Integrated Circuit) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C #define RTE_I2C1 1 #if RTE_I2C1 // I2C1 IRQ priority <0-255> // Defines Interrupt priority for I2C1. // Default: 0 #define RTE_I2C1_IRQ_PRIORITY 0 // I2C1 TX FIFO threshold <0-31> // Defines TX FIFO threshold for I2C1. // Default: 16 #define RTE_I2C1_TX_FIFO_THRESHOLD 16 // I2C1 RX FIFO threshold <0-31> // Defines RX FIFO threshold for I2C1. // Default: 16 #define RTE_I2C1_RX_FIFO_THRESHOLD 16 #endif // I2C (Inter Integrated Circuit) [Driver_I2C1] // I2C (Inter Integrated Circuit) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #if RTE_I2C2 // I2C2 IRQ priority <0-255> // Defines Interrupt priority for I2C2. // Default: 0 #define RTE_I2C2_IRQ_PRIORITY 0 // I2C2 TX FIFO threshold <0-31> // Defines TX FIFO threshold for I2C2. // Default: 16 #define RTE_I2C2_TX_FIFO_THRESHOLD 16 // I2C2 RX FIFO threshold <0-31> // Defines RX FIFO threshold for I2C2. // Default: 16 #define RTE_I2C2_RX_FIFO_THRESHOLD 16 #endif // I2C (Inter Integrated Circuit) [Driver_I2C2] // I2C (Inter Integrated Circuit) [Driver_I2C3] // Configuration settings for Driver_I2C3 in component ::Drivers:I2C #define RTE_I2C3 1 #if RTE_I2C3 // I2C3 IRQ priority <0-255> // Defines Interrupt priority for I2C3. // Default: 0 #define RTE_I2C3_IRQ_PRIORITY 0 // I2C3 TX FIFO threshold <0-31> // Defines TX FIFO threshold for I2C3. // Default: 16 #define RTE_I2C3_TX_FIFO_THRESHOLD 16 // I2C3 RX FIFO threshold <0-31> // Defines RX FIFO threshold for I2C3. // Default: 16 #define RTE_I2C3_RX_FIFO_THRESHOLD 16 #endif // I2C (Inter Integrated Circuit) [Driver_I2C3] // LPI2C (Low Power Inter-Integrated Circuit) [Driver_LPI2C] // Configuration settings for Driver_LPI2C in component ::Drivers:LPI2C #if defined(M55_HE) #define RTE_LPI2C 1 #if RTE_LPI2C // LPI2C IRQ PRIORITY <0-225> // defines LPI2C interrupt priority // default: 0 #define RTE_LPI2C_IRQ_PRIORITY 0 #endif // LPI2C (Low Power Inter-Integrated Circuit) [Driver_LPI2C] #endif //defined(M55_HE) // // DMA0 (Direct Memory Access Controller) [Driver_DMA0] // Configuration settings for Driver_DMA0 in component ::Drivers:DMA #define RTE_DMA0 1 #if RTE_DMA0 // DMA APB Interface to be used // <0=> Secure APB interface // <1=> Non-Secure // Default: 0 #define RTE_DMA0_APB_INTERFACE 0 // DMA0 Abort interrupt priority <0-255> // Defines DMA0 Abort interrupt priority. // Default: 0 #define RTE_DMA0_ABORT_IRQ_PRI 0 // DMA0 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> // Defines DMA0 Boot Event-IRQ Non-secure state // Default: 0 #define RTE_DMA0_BOOT_IRQ_NS_STATE 0 // DMA0 Boot Peripheral Non-secure state <0-0xFFFFFFFF> // Defines DMA0 Boot Peripheral Non-secure state // Default: 0 #define RTE_DMA0_BOOT_PERIPH_NS_STATE 0 #endif // DMA0 (Direct Memory Access Controller) [Driver_DMA0] // DMA1 (Direct Memory Access Controller) [Driver_DMA1] #if defined(M55_HP) // Configuration settings for Driver_DMA1 in component ::Drivers:DMA #define RTE_DMA1 1 #if RTE_DMA1 // DMA APB Interface to be used // <0=> Secure APB interface // <1=> Non-Secure // Default: 0 #define RTE_DMA1_APB_INTERFACE 0 // DMA1 Abort interrupt priority <0-255> // Defines DMA1 Abort interrupt priority. // Default: 0 #define RTE_DMA1_ABORT_IRQ_PRI 0 // DMA1 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> // Defines DMA1 Boot Event-IRQ Non-secure state // Default: 0 #define RTE_DMA1_BOOT_IRQ_NS_STATE 0 // DMA1 Boot Peripheral Non-secure state <0-0xFFFFFFFF> // Defines DMA1 Boot Peripheral Non-secure state // Default: 0 #define RTE_DMA1_BOOT_PERIPH_NS_STATE 0 #endif #endif // DMA1 (Direct Memory Access Controller) [Driver_DMA1] // DMA2 (Direct Memory Access Controller) [Driver_DMA2] // Configuration settings for Driver_DMA2 in component ::Drivers:DMA #if defined(M55_HE) #define RTE_DMA2 1 #if RTE_DMA2 // DMA APB Interface to be used // <0=> Secure APB interface // <1=> Non-Secure // Default: 0 #define RTE_DMA2_APB_INTERFACE 0 // DMA2 Abort interrupt priority <0-255> // Defines DMA2 Abort interrupt priority. // Default: 0 #define RTE_DMA2_ABORT_IRQ_PRI 0 // DMA2 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> // Defines DMA2 Boot Event-IRQ Non-secure state // Default: 0 #define RTE_DMA2_BOOT_IRQ_NS_STATE 0 // DMA2 Boot Peripheral Non-secure state <0-0xFFFFFFFF> // Defines DMA2 Boot Peripheral Non-secure state // Default: 0 #define RTE_DMA2_BOOT_PERIPH_NS_STATE 0 #endif #endif // DMA2 (Direct Memory Access Controller) [Driver_DMA2] // GPIO (general purpose input and output) // GPIO0 // Configuration settings for Driver_GPIO0 in component ::Drivers:GPIO #define RTE_GPIO0 1 #if RTE_GPIO0 // GPIO0 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO0. // Default: 0 #define RTE_GPIO0_DB_CLK_DIV 1 // GPIO0_PIN0 IRQ Priority // Defines Interrupt priority for GPIO0_PIN0. // Default: 0 #define RTE_GPIO0_PIN0_IRQ_PRIORITY 0 // GPIO0_PIN1 IRQ Priority // Defines Interrupt priority for GPIO0_PIN1. // Default: 0 #define RTE_GPIO0_PIN1_IRQ_PRIORITY 0 // GPIO0_PIN2 IRQ Priority // Defines Interrupt priority for GPIO0_PIN2. // Default: 0 #define RTE_GPIO0_PIN2_IRQ_PRIORITY 0 // GPIO0_PIN3 IRQ Priority // Defines Interrupt priority for GPIO0_PIN3. // Default: 0 #define RTE_GPIO0_PIN3_IRQ_PRIORITY 0 // GPIO0_PIN4 IRQ Priority // Defines Interrupt priority for GPIO0_PIN4. // Default: 0 #define RTE_GPIO0_PIN4_IRQ_PRIORITY 0 // GPIO0_PIN5 IRQ Priority // Defines Interrupt priority for GPIO0_PIN5. // Default: 0 #define RTE_GPIO0_PIN5_IRQ_PRIORITY 0 // GPIO0_PIN6 IRQ Priority // Defines Interrupt priority for GPIO0_PIN6. // Default: 0 #define RTE_GPIO0_PIN6_IRQ_PRIORITY 0 // GPIO0_PIN7 IRQ Priority // Defines Interrupt priority for GPIO0_PIN7. // Default: 0 #define RTE_GPIO0_PIN7_IRQ_PRIORITY 0 #endif // GPIO0 // GPIO1 // Configuration settings for Driver_GPIO1 in component ::Drivers:GPIO #define RTE_GPIO1 1 #if RTE_GPIO1 // GPIO1 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO1. // Default: 0 #define RTE_GPIO1_DB_CLK_DIV 1 // GPIO1_PIN0 IRQ Priority // Defines Interrupt priority for GPIO1_PIN0. // Default: 0 #define RTE_GPIO1_PIN0_IRQ_PRIORITY 0 // GPIO1_PIN1 IRQ Priority // Defines Interrupt priority for GPIO1_PIN1. // Default: 0 #define RTE_GPIO1_PIN1_IRQ_PRIORITY 0 // GPIO1_PIN2 IRQ Priority // Defines Interrupt priority for GPIO1_PIN2. // Default: 0 #define RTE_GPIO1_PIN2_IRQ_PRIORITY 0 // GPIO1_PIN3 IRQ Priority // Defines Interrupt priority for GPIO1_PIN3. // Default: 0 #define RTE_GPIO1_PIN3_IRQ_PRIORITY 0 // GPIO1_PIN4 IRQ Priority // Defines Interrupt priority for GPIO1_PIN4. // Default: 0 #define RTE_GPIO1_PIN4_IRQ_PRIORITY 0 // GPIO1_PIN5 IRQ Priority // Defines Interrupt priority for GPIO1_PIN5. // Default: 0 #define RTE_GPIO1_PIN5_IRQ_PRIORITY 0 // GPIO1_PIN6 IRQ Priority // Defines Interrupt priority for GPIO1_PIN6. // Default: 0 #define RTE_GPIO1_PIN6_IRQ_PRIORITY 0 // GPIO1_PIN7 IRQ Priority // Defines Interrupt priority for GPIO1_PIN7. // Default: 0 #define RTE_GPIO1_PIN7_IRQ_PRIORITY 0 #endif // GPIO1 // GPIO2 // Configuration settings for Driver_GPIO2 in component ::Drivers:GPIO #define RTE_GPIO2 1 #if RTE_GPIO2 // GPIO2 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO2. // Default: 0 #define RTE_GPIO2_DB_CLK_DIV 1 // GPIO2_PIN0 IRQ Priority // Defines Interrupt priority for GPIO2_PIN0. // Default: 0 #define RTE_GPIO2_PIN0_IRQ_PRIORITY 0 // GPIO2_PIN1 IRQ Priority // Defines Interrupt priority for GPIO2_PIN1. // Default: 0 #define RTE_GPIO2_PIN1_IRQ_PRIORITY 0 // GPIO2_PIN2 IRQ Priority // Defines Interrupt priority for GPIO2_PIN2. // Default: 0 #define RTE_GPIO2_PIN2_IRQ_PRIORITY 0 // GPIO2_PIN3 IRQ Priority // Defines Interrupt priority for GPIO1_PIN3. // Default: 0 #define RTE_GPIO2_PIN3_IRQ_PRIORITY 0 // GPIO2_PIN4 IRQ Priority // Defines Interrupt priority for GPIO2_PIN4. // Default: 0 #define RTE_GPIO2_PIN4_IRQ_PRIORITY 0 // GPIO2_PIN5 IRQ Priority // Defines Interrupt priority for GPIO2_PIN5. // Default: 0 #define RTE_GPIO2_PIN5_IRQ_PRIORITY 0 // GPIO2_PIN6 IRQ Priority // Defines Interrupt priority for GPIO2_PIN6. // Default: 0 #define RTE_GPIO2_PIN6_IRQ_PRIORITY 0 // GPIO2_PIN7 IRQ Priority // Defines Interrupt priority for GPIO2_PIN7. // Default: 0 #define RTE_GPIO2_PIN7_IRQ_PRIORITY 0 #endif // GPIO2 // GPIO3 // Configuration settings for Driver_GPIO3 in component ::Drivers:GPIO #define RTE_GPIO3 1 #if RTE_GPIO3 // GPIO3 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO3. // Default: 0 #define RTE_GPIO3_DB_CLK_DIV 1 // GPIO3_PIN0 IRQ Priority // Defines Interrupt priority for GPIO3_PIN0. // Default: 0 #define RTE_GPIO3_PIN0_IRQ_PRIORITY 0 // GPIO3_PIN0 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN0_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN1 IRQ Priority // Defines Interrupt priority for GPIO3_PIN1. // Default: 0 #define RTE_GPIO3_PIN1_IRQ_PRIORITY 0 // GPIO3_PIN1 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN1_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN2 IRQ Priority // Defines Interrupt priority for GPIO3_PIN2. // Default: 0 #define RTE_GPIO3_PIN2_IRQ_PRIORITY 0 // GPIO3_PIN2 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN2_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN3 IRQ Priority // Defines Interrupt priority for GPIO3_PIN3. // Default: 0 #define RTE_GPIO3_PIN3_IRQ_PRIORITY 0 // GPIO3_PIN3 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN3_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN4 IRQ Priority // Defines Interrupt priority for GPIO3_PIN4. // Default: 0 #define RTE_GPIO3_PIN4_IRQ_PRIORITY 0 // GPIO3_PIN4 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN4_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN5 IRQ Priority // Defines Interrupt priority for GPIO3_PIN5. // Default: 0 #define RTE_GPIO3_PIN5_IRQ_PRIORITY 0 // GPIO3_PIN5 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN5_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN6 IRQ Priority // Defines Interrupt priority for GPIO3_PIN6. // Default: 0 #define RTE_GPIO3_PIN6_IRQ_PRIORITY 0 // GPIO3_PIN6 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN6_DMA_GLITCH_FILTER_ENABLE 0 // GPIO3_PIN7 IRQ Priority // Defines Interrupt priority for GPIO3_PIN7. // Default: 0 #define RTE_GPIO3_PIN7_IRQ_PRIORITY 0 // GPIO3_PIN7 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO3_PIN7_DMA_GLITCH_FILTER_ENABLE 0 #endif // GPIO3 // GPIO4 // Configuration settings for Driver_GPIO4 in component ::Drivers:GPIO #define RTE_GPIO4 1 #if RTE_GPIO4 // GPIO4 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO4. // Default: 0 #define RTE_GPIO4_DB_CLK_DIV 1 // GPIO4_PIN0 IRQ Priority // Defines Interrupt priority for GPIO4_PIN0. // Default: 0 #define RTE_GPIO4_PIN0_IRQ_PRIORITY 0 // GPIO4_PIN0 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN0_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN1 IRQ Priority // Defines Interrupt priority for GPIO4_PIN1. // Default: 0 #define RTE_GPIO4_PIN1_IRQ_PRIORITY 0 // GPIO4_PIN1 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN1_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN2 IRQ Priority // Defines Interrupt priority for GPIO4_PIN2. // Default: 0 #define RTE_GPIO4_PIN2_IRQ_PRIORITY 0 // GPIO4_PIN2 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN2_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN3 IRQ Priority // Defines Interrupt priority for GPIO4_PIN3. // Default: 0 #define RTE_GPIO4_PIN3_IRQ_PRIORITY 0 // GPIO4_PIN3 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN3_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN4 IRQ Priority // Defines Interrupt priority for GPIO4_PIN4. // Default: 0 #define RTE_GPIO4_PIN4_IRQ_PRIORITY 0 // GPIO4_PIN4 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN4_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN5 IRQ Priority // Defines Interrupt priority for GPIO4_PIN5. // Default: 0 #define RTE_GPIO4_PIN5_IRQ_PRIORITY 0 // GPIO4_PIN5 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN5_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN6 IRQ Priority // Defines Interrupt priority for GPIO4_PIN6. // Default: 0 #define RTE_GPIO4_PIN6_IRQ_PRIORITY 0 // GPIO4_PIN6 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN6_DMA_GLITCH_FILTER_ENABLE 0 // GPIO4_PIN7 IRQ Priority // Defines Interrupt priority for GPIO4_PIN7. // Default: 0 #define RTE_GPIO4_PIN7_IRQ_PRIORITY 0 // GPIO4_PIN7 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO4_PIN7_DMA_GLITCH_FILTER_ENABLE 0 #endif // GPIO4 // GPIO5 // Configuration settings for Driver_GPIO5 in component ::Drivers:GPIO #define RTE_GPIO5 1 #if RTE_GPIO5 // GPIO5 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO5. // Default: 0 #define RTE_GPIO5_DB_CLK_DIV 1 // GPIO5_PIN0 IRQ Priority // Defines Interrupt priority for GPIO5_PIN0. // Default: 0 #define RTE_GPIO5_PIN0_IRQ_PRIORITY 0 // GPIO5_PIN1 IRQ Priority // Defines Interrupt priority for GPIO5_PIN1. // Default: 0 #define RTE_GPIO5_PIN1_IRQ_PRIORITY 0 // GPIO5_PIN2 IRQ Priority // Defines Interrupt priority for GPIO5_PIN2. // Default: 0 #define RTE_GPIO5_PIN2_IRQ_PRIORITY 0 // GPIO5_PIN3 IRQ Priority // Defines Interrupt priority for GPIO5_PIN3. // Default: 0 #define RTE_GPIO5_PIN3_IRQ_PRIORITY 0 // GPIO5_PIN4 IRQ Priority // Defines Interrupt priority for GPIO5_PIN4. // Default: 0 #define RTE_GPIO5_PIN4_IRQ_PRIORITY 0 // GPIO5_PIN5 IRQ Priority // Defines Interrupt priority for GPIO5_PIN5. // Default: 0 #define RTE_GPIO5_PIN5_IRQ_PRIORITY 0 // GPIO5_PIN6 IRQ Priority // Defines Interrupt priority for GPIO5_PIN6. // Default: 0 #define RTE_GPIO5_PIN6_IRQ_PRIORITY 0 // GPIO5_PIN7 IRQ Priority // Defines Interrupt priority for GPIO5_PIN7. // Default: 0 #define RTE_GPIO5_PIN7_IRQ_PRIORITY 0 #endif // GPIO5 // GPIO6 // Configuration settings for Driver_GPIO6 in component ::Drivers:GPIO #define RTE_GPIO6 1 #if RTE_GPIO6 // GPIO6 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO6. // Default: 0 #define RTE_GPIO6_DB_CLK_DIV 1 // GPIO6_PIN0 IRQ Priority // Defines Interrupt priority for GPIO6_PIN0. // Default: 0 #define RTE_GPIO6_PIN0_IRQ_PRIORITY 0 // GPIO6_PIN1 IRQ Priority // Defines Interrupt priority for GPIO6_PIN1. // Default: 0 #define RTE_GPIO6_PIN1_IRQ_PRIORITY 0 // GPIO6_PIN2 IRQ Priority // Defines Interrupt priority for GPIO6_PIN2. // Default: 0 #define RTE_GPIO6_PIN2_IRQ_PRIORITY 0 // GPIO6_PIN3 IRQ Priority // Defines Interrupt priority for GPIO6_PIN3. // Default: 0 #define RTE_GPIO6_PIN3_IRQ_PRIORITY 0 // GPIO6_PIN4 IRQ Priority // Defines Interrupt priority for GPIO6_PIN4. // Default: 0 #define RTE_GPIO6_PIN4_IRQ_PRIORITY 0 // GPIO6_PIN5 IRQ Priority // Defines Interrupt priority for GPIO6_PIN5. // Default: 0 #define RTE_GPIO6_PIN5_IRQ_PRIORITY 0 // GPIO6_PIN6 IRQ Priority // Defines Interrupt priority for GPIO6_PIN6. // Default: 0 #define RTE_GPIO6_PIN6_IRQ_PRIORITY 0 // GPIO6_PIN7 IRQ Priority // Defines Interrupt priority for GPIO6_PIN7. // Default: 0 #define RTE_GPIO6_PIN7_IRQ_PRIORITY 0 #endif // GPIO6 // GPIO7 // Configuration settings for Driver_GPIO7 in component ::Drivers:GPIO #define RTE_GPIO7 1 #if RTE_GPIO7 // GPIO7 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO7. // Default: 0 #define RTE_GPIO7_DB_CLK_DIV 1 // GPIO7_PIN0 IRQ Priority // Defines Interrupt priority for GPIO7_PIN0. // Default: 0 #define RTE_GPIO7_PIN0_IRQ_PRIORITY 0 // GPIO7_PIN0 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN0_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN1 IRQ Priority // Defines Interrupt priority for GPIO7_PIN1. // Default: 0 #define RTE_GPIO7_PIN1_IRQ_PRIORITY 0 // GPIO7_PIN1 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN1_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN2 IRQ Priority // Defines Interrupt priority for GPIO7_PIN2. // Default: 0 #define RTE_GPIO7_PIN2_IRQ_PRIORITY 0 // GPIO7_PIN2 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN2_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN3 IRQ Priority // Defines Interrupt priority for GPIO7_PIN3. // Default: 0 #define RTE_GPIO7_PIN3_IRQ_PRIORITY 0 // GPIO7_PIN3 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN3_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN4 IRQ Priority // Defines Interrupt priority for GPIO7_PIN4. // Default: 0 #define RTE_GPIO7_PIN4_IRQ_PRIORITY 0 // GPIO7_PIN4 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN4_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN5 IRQ Priority // Defines Interrupt priority for GPIO7_PIN5. // Default: 0 #define RTE_GPIO7_PIN5_IRQ_PRIORITY 0 // GPIO7_PIN5 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN5_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN6 IRQ Priority // Defines Interrupt priority for GPIO7_PIN6. // Default: 0 #define RTE_GPIO7_PIN6_IRQ_PRIORITY 0 // GPIO7_PIN6 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN6_DMA_GLITCH_FILTER_ENABLE 0 // GPIO7_PIN7 IRQ Priority // Defines Interrupt priority for GPIO7_PIN7. // Default: 0 #define RTE_GPIO7_PIN7_IRQ_PRIORITY 0 // GPIO7_PIN7 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO7_PIN7_DMA_GLITCH_FILTER_ENABLE 0 #endif // GPIO7 // GPIO8 // Configuration settings for Driver_GPIO8 in component ::Drivers:GPIO #define RTE_GPIO8 1 #if RTE_GPIO8 // GPIO8 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO8. // Default: 0 #define RTE_GPIO8_DB_CLK_DIV 1 // GPIO8_PIN0 IRQ Priority // Defines Interrupt priority for GPIO8_PIN0. // Default: 0 #define RTE_GPIO8_PIN0_IRQ_PRIORITY 0 // GPIO8_PIN0 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN0_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN1 IRQ Priority // Defines Interrupt priority for GPIO8_PIN1. // Default: 0 #define RTE_GPIO8_PIN1_IRQ_PRIORITY 0 // GPIO8_PIN1 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN1_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN2 IRQ Priority // Defines Interrupt priority for GPIO8_PIN2. // Default: 0 #define RTE_GPIO8_PIN2_IRQ_PRIORITY 0 // GPIO8_PIN2 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN2_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN3 IRQ Priority // Defines Interrupt priority for GPIO8_PIN3. // Default: 0 #define RTE_GPIO8_PIN3_IRQ_PRIORITY 0 // GPIO8_PIN3 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN3_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN4 IRQ Priority // Defines Interrupt priority for GPIO8_PIN4. // Default: 0 #define RTE_GPIO8_PIN4_IRQ_PRIORITY 0 // GPIO8_PIN4 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN4_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN5 IRQ Priority // Defines Interrupt priority for GPIO8_PIN5. // Default: 0 #define RTE_GPIO8_PIN5_IRQ_PRIORITY 0 // GPIO8_PIN5 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN5_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN6 IRQ Priority // Defines Interrupt priority for GPIO8_PIN6. // Default: 0 #define RTE_GPIO8_PIN6_IRQ_PRIORITY 0 // GPIO8_PIN6 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN6_DMA_GLITCH_FILTER_ENABLE 0 // GPIO8_PIN7 IRQ Priority // Defines Interrupt priority for GPIO8_PIN7. // Default: 0 #define RTE_GPIO8_PIN7_IRQ_PRIORITY 0 // GPIO8_PIN7 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO8_PIN7_DMA_GLITCH_FILTER_ENABLE 0 #endif // GPIO8 // GPIO9 // Configuration settings for Driver_GPIO9 in component ::Drivers:GPIO #define RTE_GPIO9 1 #if RTE_GPIO9 // GPIO9 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO9. // Default: 0 #define RTE_GPIO9_DB_CLK_DIV 1 // GPIO9_PIN0 IRQ Priority // Defines Interrupt priority for GPIO9_PIN0. // Default: 0 #define RTE_GPIO9_PIN0_IRQ_PRIORITY 0 // GPIO9_PIN0 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN0_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN1 IRQ Priority // Defines Interrupt priority for GPIO9_PIN1. // Default: 0 #define RTE_GPIO9_PIN1_IRQ_PRIORITY 0 // GPIO9_PIN1 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN1_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN2 IRQ Priority // Defines Interrupt priority for GPIO9_PIN2. // Default: 0 #define RTE_GPIO9_PIN2_IRQ_PRIORITY 0 // GPIO9_PIN2 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN2_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN3 IRQ Priority // Defines Interrupt priority for GPIO9_PIN3. // Default: 0 #define RTE_GPIO9_PIN3_IRQ_PRIORITY 0 // GPIO9_PIN3 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN3_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN4 IRQ Priority // Defines Interrupt priority for GPIO9_PIN4. // Default: 0 #define RTE_GPIO9_PIN4_IRQ_PRIORITY 0 // GPIO9_PIN4 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN4_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN5 IRQ Priority // Defines Interrupt priority for GPIO9_PIN5. // Default: 0 #define RTE_GPIO9_PIN5_IRQ_PRIORITY 0 // GPIO9_PIN5 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN5_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN6 IRQ Priority // Defines Interrupt priority for GPIO9_PIN6. // Default: 0 #define RTE_GPIO9_PIN6_IRQ_PRIORITY 0 // GPIO9_PIN6 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN6_DMA_GLITCH_FILTER_ENABLE 0 // GPIO9_PIN7 IRQ Priority // Defines Interrupt priority for GPIO9_PIN7. // Default: 0 #define RTE_GPIO9_PIN7_IRQ_PRIORITY 0 // GPIO9_PIN7 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_GPIO9_PIN7_DMA_GLITCH_FILTER_ENABLE 0 #endif // GPIO9 // GPIO10 // Configuration settings for Driver_GPIO10 in component ::Drivers:GPIO #define RTE_GPIO10 1 #if RTE_GPIO10 // GPIO10 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO10. // Default: 0 #define RTE_GPIO10_DB_CLK_DIV 1 // GPIO10_PIN0 IRQ Priority // Defines Interrupt priority for GPIO10_PIN0. // Default: 0 #define RTE_GPIO10_PIN0_IRQ_PRIORITY 0 // GPIO10_PIN1 IRQ Priority // Defines Interrupt priority for GPIO10_PIN1. // Default: 0 #define RTE_GPIO10_PIN1_IRQ_PRIORITY 0 // GPIO10_PIN2 IRQ Priority // Defines Interrupt priority for GPIO10_PIN2. // Default: 0 #define RTE_GPIO10_PIN2_IRQ_PRIORITY 0 // GPIO10_PIN3 IRQ Priority // Defines Interrupt priority for GPIO10_PIN3. // Default: 0 #define RTE_GPIO10_PIN3_IRQ_PRIORITY 0 // GPIO10_PIN4 IRQ Priority // Defines Interrupt priority for GPIO10_PIN4. // Default: 0 #define RTE_GPIO10_PIN4_IRQ_PRIORITY 0 // GPIO10_PIN5 IRQ Priority // Defines Interrupt priority for GPIO10_PIN5. // Default: 0 #define RTE_GPIO10_PIN5_IRQ_PRIORITY 0 // GPIO10_PIN6 IRQ Priority // Defines Interrupt priority for GPIO10_PIN6. // Default: 0 #define RTE_GPIO10_PIN6_IRQ_PRIORITY 0 // GPIO10_PIN7 IRQ Priority // Defines Interrupt priority for GPIO10_PIN7. // Default: 0 #define RTE_GPIO10_PIN7_IRQ_PRIORITY 0 #endif // GPIO10 // GPIO11 // Configuration settings for Driver_GPIO11 in component ::Drivers:GPIO #define RTE_GPIO11 1 #if RTE_GPIO11 // GPIO11 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO11. // Default: 0 #define RTE_GPIO11_DB_CLK_DIV 1 // GPIO11_PIN0 IRQ Priority // Defines Interrupt priority for GPIO11_PIN0. // Default: 0 #define RTE_GPIO11_PIN0_IRQ_PRIORITY 0 // GPIO11_PIN1 IRQ Priority // Defines Interrupt priority for GPIO11_PIN1. // Default: 0 #define RTE_GPIO11_PIN1_IRQ_PRIORITY 0 // GPIO11_PIN2 IRQ Priority // Defines Interrupt priority for GPIO11_PIN2. // Default: 0 #define RTE_GPIO11_PIN2_IRQ_PRIORITY 0 // GPIO11_PIN3 IRQ Priority // Defines Interrupt priority for GPIO11_PIN3. // Default: 0 #define RTE_GPIO11_PIN3_IRQ_PRIORITY 0 // GPIO11_PIN4 IRQ Priority // Defines Interrupt priority for GPIO11_PIN4. // Default: 0 #define RTE_GPIO11_PIN4_IRQ_PRIORITY 0 // GPIO11_PIN5 IRQ Priority // Defines Interrupt priority for GPIO11_PIN5. // Default: 0 #define RTE_GPIO11_PIN5_IRQ_PRIORITY 0 // GPIO11_PIN6 IRQ Priority // Defines Interrupt priority for GPIO11_PIN6. // Default: 0 #define RTE_GPIO11_PIN6_IRQ_PRIORITY 0 // GPIO11_PIN7 IRQ Priority // Defines Interrupt priority for GPIO11_PIN7. // Default: 0 #define RTE_GPIO11_PIN7_IRQ_PRIORITY 0 #endif // GPIO11 // GPIO12 // Configuration settings for Driver_GPIO12 in component ::Drivers:GPIO #define RTE_GPIO12 1 #if RTE_GPIO12 // GPIO12 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO12. // Default: 0 #define RTE_GPIO12_DB_CLK_DIV 1 // GPIO12_PIN0 IRQ Priority // Defines Interrupt priority for GPIO12_PIN0. // Default: 0 #define RTE_GPIO12_PIN0_IRQ_PRIORITY 0 // GPIO12_PIN1 IRQ Priority // Defines Interrupt priority for GPIO12_PIN1. // Default: 0 #define RTE_GPIO12_PIN1_IRQ_PRIORITY 0 // GPIO12_PIN2 IRQ Priority // Defines Interrupt priority for GPIO12_PIN2. // Default: 0 #define RTE_GPIO12_PIN2_IRQ_PRIORITY 0 // GPIO12_PIN3 IRQ Priority // Defines Interrupt priority for GPIO12_PIN3. // Default: 0 #define RTE_GPIO12_PIN3_IRQ_PRIORITY 0 // GPIO12_PIN4 IRQ Priority // Defines Interrupt priority for GPIO12_PIN4. // Default: 0 #define RTE_GPIO12_PIN4_IRQ_PRIORITY 0 // GPIO12_PIN5 IRQ Priority // Defines Interrupt priority for GPIO12_PIN5. // Default: 0 #define RTE_GPIO12_PIN5_IRQ_PRIORITY 0 // GPIO12_PIN6 IRQ Priority // Defines Interrupt priority for GPIO12_PIN6. // Default: 0 #define RTE_GPIO12_PIN6_IRQ_PRIORITY 0 // GPIO12_PIN7 IRQ Priority // Defines Interrupt priority for GPIO12_PIN7. // Default: 0 #define RTE_GPIO12_PIN7_IRQ_PRIORITY 0 #endif // GPIO12 // GPIO13 // Configuration settings for Driver_GPIO13 in component ::Drivers:GPIO #define RTE_GPIO13 1 #if RTE_GPIO13 // GPIO13 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO13. // Default: 0 #define RTE_GPIO13_DB_CLK_DIV 1 // GPIO13_PIN0 IRQ Priority // Defines Interrupt priority for GPIO13_PIN0. // Default: 0 #define RTE_GPIO13_PIN0_IRQ_PRIORITY 0 // GPIO13_PIN1 IRQ Priority // Defines Interrupt priority for GPIO13_PIN1. // Default: 0 #define RTE_GPIO13_PIN1_IRQ_PRIORITY 0 // GPIO13_PIN2 IRQ Priority // Defines Interrupt priority for GPIO13_PIN2. // Default: 0 #define RTE_GPIO13_PIN2_IRQ_PRIORITY 0 // GPIO13_PIN3 IRQ Priority // Defines Interrupt priority for GPIO13_PIN3. // Default: 0 #define RTE_GPIO13_PIN3_IRQ_PRIORITY 0 // GPIO13_PIN4 IRQ Priority // Defines Interrupt priority for GPIO13_PIN4. // Default: 0 #define RTE_GPIO13_PIN4_IRQ_PRIORITY 0 // GPIO13_PIN5 IRQ Priority // Defines Interrupt priority for GPIO13_PIN5. // Default: 0 #define RTE_GPIO13_PIN5_IRQ_PRIORITY 0 // GPIO13_PIN6 IRQ Priority // Defines Interrupt priority for GPIO13_PIN6. // Default: 0 #define RTE_GPIO13_PIN6_IRQ_PRIORITY 0 // GPIO13_PIN7 IRQ Priority // Defines Interrupt priority for GPIO13_PIN7. // Default: 0 #define RTE_GPIO13_PIN7_IRQ_PRIORITY 0 #endif // GPIO13 // GPIO14 // Configuration settings for Driver_GPIO14 in component ::Drivers:GPIO #define RTE_GPIO14 1 #if RTE_GPIO14 // GPIO14 Debounce Clock Divisor <0-1023> // Defines debounce clock divisor for GPIO14. // Default: 0 #define RTE_GPIO14_DB_CLK_DIV 1 // GPIO14_PIN0 IRQ Priority // Defines Interrupt priority for GPIO14_PIN0. // Default: 0 #define RTE_GPIO14_PIN0_IRQ_PRIORITY 0 // GPIO14_PIN1 IRQ Priority // Defines Interrupt priority for GPIO14_PIN1. // Default: 0 #define RTE_GPIO14_PIN1_IRQ_PRIORITY 0 // GPIO14_PIN2 IRQ Priority // Defines Interrupt priority for GPIO14_PIN2. // Default: 0 #define RTE_GPIO14_PIN2_IRQ_PRIORITY 0 // GPIO14_PIN3 IRQ Priority // Defines Interrupt priority for GPIO14_PIN3. // Default: 0 #define RTE_GPIO14_PIN3_IRQ_PRIORITY 0 // GPIO14_PIN4 IRQ Priority // Defines Interrupt priority for GPIO14_PIN4. // Default: 0 #define RTE_GPIO14_PIN4_IRQ_PRIORITY 0 // GPIO14_PIN5 IRQ Priority // Defines Interrupt priority for GPIO14_PIN5. // Default: 0 #define RTE_GPIO14_PIN5_IRQ_PRIORITY 0 // GPIO14_PIN6 IRQ Priority // Defines Interrupt priority for GPIO14_PIN6. // Default: 0 #define RTE_GPIO14_PIN6_IRQ_PRIORITY 0 // GPIO14_PIN7 IRQ Priority // Defines Interrupt priority for GPIO14_PIN7. // Default: 0 #define RTE_GPIO14_PIN7_IRQ_PRIORITY 0 #endif // GPIO14 // LPGPIO // Configuration settings for Driver_LPGPIO in component ::Drivers:GPIO #define RTE_LPGPIO 1 #if RTE_LPGPIO // LPGPIO_PIN0 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN0. // Default: 0 #define RTE_LPGPIO_PIN0_IRQ_PRIORITY 0 // LPGPIO_PIN0 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN0_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN1 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN1. // Default: 0 #define RTE_LPGPIO_PIN1_IRQ_PRIORITY 0 // LPGPIO_PIN1 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN1_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN2 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN2. // Default: 0 #define RTE_LPGPIO_PIN2_IRQ_PRIORITY 0 // LPGPIO_PIN2 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN2_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN3 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN3. // Default: 0 #define RTE_LPGPIO_PIN3_IRQ_PRIORITY 0 // LPGPIO_PIN3 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN3_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN4 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN4. // Default: 0 #define RTE_LPGPIO_PIN4_IRQ_PRIORITY 0 // LPGPIO_PIN4 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN4_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN5 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN5. // Default: 0 #define RTE_LPGPIO_PIN5_IRQ_PRIORITY 0 // LPGPIO_PIN5 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN5_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN6 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN6. // Default: 0 #define RTE_LPGPIO_PIN6_IRQ_PRIORITY 0 // LPGPIO_PIN6 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN6_DMA_GLITCH_FILTER_ENABLE 0 // LPGPIO_PIN7 IRQ Priority // Defines Interrupt priority for LPGPIO_PIN7. // Default: 0 #define RTE_LPGPIO_PIN7_IRQ_PRIORITY 0 // LPGPIO_PIN7 DMA Glitch Filter enable // <0=> DISABLE // <1=> ENABLE // Defines Enable Glitch Filter // Default: DISABLE #define RTE_LPGPIO_PIN7_DMA_GLITCH_FILTER_ENABLE 0 #endif // LPGPIO // GPIO (general purpose input and output) // PDM(Pulse Density Modulation) // PDM (Pulse density modulation) [Driver_PDM] // Configuration settings for Driver_PDM in component ::Drivers:PDM #define RTE_PDM 1 #if RTE_PDM // PDM DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for PDM // Default: ENABLE #define RTE_PDM_DMA_ENABLE 0 // PDM DMA IRQ priority <0-255> // Defines PDM DMA Interrupt priority // Default: 0 #define RTE_PDM_DMA_IRQ_PRIORITY 0 // PDM IRQ priority <0-255> // Defines Interrupt priority for PDM. // Default: 0 #define RTE_PDM_IRQ_PRIORITY 0 // PDM Fifo watermark <0-7> // Defines number of PCM samples in the internal FIFO // Default: 5 #define RTE_PDM_FIFO_WATERMARK 5 #endif // PDM (Pulse density modulation) [Driver_PDM] // PDM (Pulse density modulation) #if defined(M55_HE) // LPPDM(Low Power Pulse Density Modulation) // LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] // Configuration settings for Driver_LPPDM in component ::Drivers:LPPDM #define RTE_LPPDM 1 #if RTE_LPPDM // LPPDM IRQ priority <0-255> // Defines Interrupt priority for LPPDM. // Default: 0 #define RTE_LPPDM_IRQ_PRIORITY 0 // LPPDM Fifo watermark <0-7> // Defines number of PCM samples in the internal FIFO // Default: 5 #define RTE_LPPDM_FIFO_WATERMARK 5 // LPPDM DMA ENABLE // <0=> DISABLE // <1=> ENABLE // Defines DMA feature for LPPDM // Default: ENABLE #define RTE_LPPDM_DMA_ENABLE 0 #if RTE_LPPDM_DMA_ENABLE // LPPDM DMA Selection // <0=> DMA2 // <1=> DMA0 // Defines Select DMA0 for LPPDM. By default DMA2 will be considered // Default: DMA2 #define RTE_LPPDM_SELECT_DMA0 0 // PDM DMA IRQ priority <0-255> // Defines PDM DMA Interrupt priority // Default: 0 #define RTE_LPPDM_DMA_IRQ_PRIORITY 0 #endif #endif // LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] #endif //defined(M55_HE) // LPPDM (Low Power Pulse density modulation) // CANFD (Controller Area Network - Fast Mode) // CANFD (Controller Area Network - Fast Mode Interface) [Driver_CANFD] // Configuration settings for Driver_CANFD in component ::Drivers:CANFD #define RTE_CANFD 1 #ifdef RTE_CANFD // CANFD IRQ priority <0-255> // Defines Interrupt priority for CANFD. // Default: 0 #define RTE_CANFD_IRQ_PRIORITY 0 // CANFD Clock Source // <0=> 38.4 MHz Clock // <1=> 160 MHz Clock // Defines Clock Source for CANFD. // Default: 160 MHz #define RTE_CANFD_CLK_SOURCE 1 // CANFD Clock Speed (Hz) <160000-80000000> // Defines Clock Speed for CANFD. // Maximum Clock speed is 80MHz // Recommended speeds with 160MHz clock source: 20MHz, 40MHz, 80MHz // Default: 20MHz #define RTE_CANFD_CLK_SPEED 20000000 // CANFD blocking mode enable // <0=> DISABLE // <1=> ENABLE // Defines Blocking mode support for CANFD // Default: DISABLE #define RTE_CANFD_BLOCKING_MODE_ENABLE 0 #endif // CANFD (Controller Area Network - Fast Mode Interface) [Driver_CANFD] // CANFD (Controller Area Network - Fast Mode) // SDC (Secure Digital Controller) // SDC (Secure Digital Controller 0) [Driver_SDC0] // Configuration settings for Driver_SDC0 in component ::Drivers:SDC #define RTE_SDC 1 #if RTE_SDC // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 // SDC CLOCK SELECT // <0=> SDC_12_5MHz // <1=> SDC_25MHz // <2=> SDC_50MHz // Defines SDC0 Clock select // Default: 25MHz #define RTE_SDC_CLOCK_SELECT 1 // SDC DMA SELECT // <0=> SDMA // <1=> ADMA2 // Defines SDC0 DMA select // Default: ADMA2 #define RTE_SDC_DMA_SELECT 1 // SDC IRQ MODE SELECT // <0=> Polling Mode // <1=> IRQ Mode // Defines SDC IRQ MODE select // Default: IRQ MODE #define RTE_SDC_IRQ_MODE_SELECT 1 // SDC IRQ priority <0-255> // Defines SDC Interrupt priority // Default: 0 #define RTE_SDC_IRQ_PRI 0 // SDC WAKEUP IRQ priority <0-255> // Defines SDC Wakeup Interrupt priority // Default: 0 #define RTE_SDC_WAKEUP_IRQ_PRI 0 #endif // SDC0 (Secure Digital Controller 0) [Driver_SDC0] // SDC (Secure Digital Controller) // ETH_MAC (Ethernet MAC) // ETH_MAC (Ethernet MAC) [Driver_ETH_MAC0] // Configuration settings for Driver_ETH_MAC0 in component ::Drivers:ETH_MAC #define RTE_ETH_MAC 1 #if RTE_ETH_MAC // ETH MAC IRQ priority <0-255> // Defines ETH MAC Interrupt priority // Default: 0 #define RTE_ETH_MAC_IRQ_PRIORITY 0 #endif // ETH (Ethernet MAC) [Driver_ETH_MAC0] // ETH (Ethernet MAC) // Power Management (PM) // Handle Spurious Wakeup // <0=> Disable // <1=> Enable // define Handle Spurious Wakeup // default: Enable #define PM_HANDLE_SPURIOUS_WAKEUP 1 // Power Management (PM) #endif /* __RTE_DEVICE_H */