0x457 STMicroelectronics MCU Cortex-M0+ STM32L01x/L02x STM32L0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independent watchdog Software independent watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated nBOOT_SEL 0x1D 0x1 R BOOT0 signal is defined by BOOT0 pin value (default mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT0 When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode 0x1E 0x1 R nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area Main Flash memory is selected as boot area nBOOT1 0x1F 0x1 R Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x4 R Write protection not active Write protection active WRPOT0 0x0 0x4 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independent watchdog Software independent watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated nBOOT_SEL 0xD 0x1 W BOOT0 signal is defined by BOOT0 pin value (default mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT0 When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode 0xE 0x1 W Main Flash memory is selected as boot area nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area nBOOT1 0x0F 0x1 W Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x4 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independent watchdog Software independent watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT_SEL 0x0D 0x1 RW BOOT0 signal is defined by BOOT0 pin value (default mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT0 When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode 0x0E 0x1 RW Main Flash memory is selected as boot area nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area nBOOT1 0x0F 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x4 RW Write protection not active Write protection active WRPOT0 0x0 0x4 RW read/Write protection active read/Write protection not active