0x483 STMicroelectronics MCU Cortex-M7 STM32H72x/STM32H73x STM32H7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x20 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 R BOR OFF BOR level1: 2.1V BOR level2: 2.4 V BOR level3: 2.7 V BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 W reset level is set to 0.0 V reset level is set to 2.1 V reset level is set to 2.4 V reset level is set to 2.7 V User Configuration IWDG1_SW 0x4 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 R STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 R STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset IO_HSLV 0x1D 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 R Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 R Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 R Security feature disabled Security feature enabled IWDG1_SW 0x4 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 W STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 W STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset IO_HSLV 0x1D 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 W Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 W Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 W Security feature disabled Security feature enabled SWAP_BANK_OPT 0x1F 0x1 W after boot loading, no swap for user sectors after boot loading, user sectors swapped Boot address Option Bytes BOOT_CM7_ADD0 Define the boot address for Cortex-M7 when BOOT0=0 0x0 0x10 R BOOT_CM7_ADD1 Define the boot address for Cortex-M7 when BOOT0=1 0x10 0x10 R BOOT_CM7_ADD0 0x0 0x10 W BOOT_CM7_ADD1 0x10 0x10 W PCROP Protection PROT_AREA_START Flash Bank PCROP start address 0x0 0xC R PROT_AREA_END Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address. 0x10 0xC R DMEP 0x1F 0x1 R Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START Flash Bank PCROP start address 0x0 0xC W PROT_AREA_END Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP 0x1F 0x1 W Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs Secure Protection ST_RAM_SIZE 0x13 0x2 R 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code ST_RAM_SIZE 0x13 0x2 W 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code SEC_AREA_START Flash secure area start address 0x0 0xC R SEC_AREA_END Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory. 0x10 0xC R DMES 0x1F 0x1 R Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START Flash secure area start address 0x0 0xC W SEC_AREA_END Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory. 0x10 0xC W DMES 0x1F 0x1 W Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs Write Protection nWRP0 0x0 0x8 R Write protection active Write protection not active nWRP0 0x0 0x8 W Write protection active Write protection not active TCM_AXI Shared Configuration TCM_AXI_SHARED 0x0 0x2 R 64 KB ITCM : 320KB system AXI 128KB ITCM : 256KB system AXI 192KB ITCM : 192KB system AXI 256KB ITCM : 128KB system AXI CPU_FREQ_BOOST 0x2 0x1 R Feature disabled CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) TCM_AXI_SHARED 0x0 0x2 W 64KB ITCM : 320KB system AXI 128KB ITCM : 256KB system AXI 192KB ITCM : 192KB system AXI 256KB ITCM : 128KB system AXI CPU_FREQ_BOOST 0x2 0x1 W Feature disabled CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM)