0x445 STMicroelectronics MCU Cortex-M0 STM32F04x/F070x6 STM32F0 ARM 32-bit Cortex-M0 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x13 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system memory when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled BOOT_SEL 0x17 0x1 RW BOOT0 signal is defined by nBOOT0 option bit BOOT0 signal is defined by BOOT0 pin value User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 WRP_bit0 The following option byte protect the flash memory by sector of 4 kB (each bit protect 4kB). 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector