0x479 STMicroelectronics MCU Cortex-M4 STM32G491xC/E STM32G4 Category 3 devices, ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0xFF RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Dual 0x8 Single 0x8 Dual 0x8 Single 0x8 Dual 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, no debug BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM_PE SRAM1 and CCM SRAM parity check enable 0x18 0x1 RW SRAM1 and CCM SRAM parity check enable SRAM1 and CCM SRAM parity check disable CCMSRAM_RST CCM SRAM Erase when system reset 0x19 0x1 RW CCM SRAM erased when a system reset occurs CCM SRAM is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PB8/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 NRST_MODE 0x1C 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1E 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PB4_PUEN 0x16 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated PCROP Protection PCROP1_STRT Flash PCROP start address 0x0 0x10 RW PCROP1_END Flash PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of WRP first area 0x0 0x8 RW WRP1A_STRT The address of the first page of WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of WRP first area 0x10 0x8 RW WRP1A_END The address of the last page of WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of WRP second area 0x0 0x8 RW WRP1B_STRT The address of the first page of WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of WRP second area 0x10 0x8 RW WRP1B_END The address of the last page of WRP second area 0x10 0x8 RW Secure Protection SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 0x9 RW BOOT_LOCK Unique boot entry point 0x10 0x1 RW Boot based on the pad/option bit configuration Boot will be done from user flash only, whatever the RDP level Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, no debug BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM_PE SRAM1 and CCM SRAM parity check enable 0x18 0x1 RW SRAM1 and CCM SRAM parity check enable SRAM1 and CCM SRAM parity check disable CCMSRAM_RST CCM SRAM Erase when system reset 0x19 0x1 RW CCM SRAM erased when a system reset occurs CCM SRAM is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PB8/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 NRST_MODE 0x1C 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1E 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PB4_PUEN 0x16 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of WRP first area 0x0 0x8 RW WRP1A_STRT The address of the first page of WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of WRP first area 0x10 0x8 RW WRP1A_END The address of the last page of WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of WRP second area 0x0 0x8 RW WRP1B_STRT The address of the first page of WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of WRP second area 0x10 0x8 RW WRP1B_END The address of the last page of WRP second area 0x10 0x8 RW Secure Protection SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 0x9 RW BOOT_LOCK Unique boot entry point 0x10 0x1 RW Boot based on the pad/option bit configuration Boot will be done from user flash only, whatever the RDP level