0x460 STMicroelectronics MCU Cortex-M0+ STM32G07x/STM32G08x STM32G0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_EN 0x8 0x1 RW Configurable brown out reset disabled, power-on reset defined by POR/PDR levels Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account BORR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x2 RW BOR rising level 1 with threshold around 2.1 V BOR rising level 2 with threshold around 2.3 V BOR rising level 3 with threshold around 2.6 V BOR rising level 4 with threshold around 2.9 V BORF_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0xB 0x2 RW BOR falling level 1 with threshold around 2.0 V BOR falling level 2 with threshold around 2.2 V BOR falling level 3 with threshold around 2.5 V BOR falling level 4 with threshold around 2.8 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW SRAM parity check enable SRAM parity check disable nBOOT_SEL 0x18 0x1 RW BOOT0 signal is defined by BOOT0 pin value (legacy mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1A_STRT Flash Area A PCROP start address 0x0 0x9 RW PCROP1A_END Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Area B PCROP start address 0x0 0x9 RW PCROP1B_END Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW FLASH security BOOT_LOCK used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory SEC_SIZE Securable memory area size 0x0 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_EN 0x8 0x1 RW Configurable brown out reset disabled, power-on reset defined by POR/PDR levels Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account BORR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x2 RW BOR rising level 1 with threshold around 2.1 V BOR rising level 2 with threshold around 2.3 V BOR rising level 3 with threshold around 2.6 V BOR rising level 4 with threshold around 2.9 V BORF_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0xB 0x2 RW BOR falling level 1 with threshold around 2.0 V BOR falling level 2 with threshold around 2.2 V BOR falling level 3 with threshold around 2.5 V BOR falling level 4 with threshold around 2.8 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW SRAM parity check enable SRAM parity check disable nBOOT_SEL 0x18 0x1 RW BOOT0 signal is defined by BOOT0 pin value (legacy mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW FLASH security BOOT_LOCK used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory SEC_SIZE Securable memory area size 0x0 0x8 RW