0x482 STMicroelectronics MCU Cortex-M33 STM32U575/STM32U585 STM32U5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0xFF RWE Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Dual 0x10 Dual 0x10 Single 0x10 Dual 0x10 Dual 0x10 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0xFF RWE Single 0x4 Dual 0x4 Single 0x4 Single 0x4 Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration TZEN Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode SRAM134_RST SRAM1, SRAM3 and SRAM4 erase upon system reset 0xF 0x1 RW SRAM1, SRAM3 and SRAM4 erased when a system reset occurs SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x15 0x1 RW Single bank Flash with contiguous address in bank 1 Dual-bank Flash with contiguous addresses BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit 0x1D 0x1 RW High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x1E 0x1 RW High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK_1A Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK_1B Bank 1 WPR first area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW UNLOCK_2A Bank 2 WPR first area A unlock 0x1F 0x1 RW WRP2A start and end pages locked WRP2A start and end pages unlocked WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW UNLOCK_2B Bank 2 WPR first area B unlock 0x1F 0x1 RW WRP2B start and end pages locked WRP2B start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration TZEN Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode SRAM134_RST SRAM1, SRAM3 and SRAM4 erase upon system reset 0xF 0x1 RW SRAM1, SRAM3 and SRAM4 erased when a system reset occurs SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x15 0x1 RW Single bank Flash with contiguous address in bank 1 Dual-bank Flash with contiguous addresses SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit 0x1D 0x1 RW High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x1E 0x1 RW High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK_1A Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK_1B Bank 1 WPR first area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW UNLOCK_2A Bank 2 WPR first area A unlock 0x1F 0x1 RW WRP2A start and end pages locked WRP2A start and end pages unlocked WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW UNLOCK_2B Bank 2 WPR first area B unlock 0x1F 0x1 RW WRP2B start and end pages locked WRP2B start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration TZEN Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode SRAM134_RST SRAM1, SRAM3 and SRAM4 erase upon system reset 0xF 0x1 RW SRAM1, SRAM3 and SRAM4 erased when a system reset occurs SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x15 0x1 RW Single bank Flash with contiguous address in bank 1 Dual-bank Flash with contiguous addresses BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit 0x1D 0x1 RW High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x1E 0x1 RW High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK_1A Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK_1B Bank 1 WPR first area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW UNLOCK_2A Bank 2 WPR first area A unlock 0x1F 0x1 RW WRP2A start and end pages locked WRP2A start and end pages unlocked WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW UNLOCK_2B Bank 2 WPR first area B unlock 0x1F 0x1 RW WRP2B start and end pages locked WRP2B start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration TZEN Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x16 0x1 RW Single bank Flash with contiguous address in bank 1 Dual-bank Flash with contiguous addresses BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK_1A Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK_1B Bank 1 WPR second area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked Secure area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW UNLOCK_2A Bank 2 WPR first area A unlock 0x1F 0x1 RW WRP2A start and end pages locked WRP2A start and end pages unlocked WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW UNLOCK_2B Bank 2 WPR second area B unlock 0x1F 0x1 RW WRP2B start and end pages locked WRP2B start and end pages unlocked RDP Level 1 Password OEM1KEYR1 OEM1 least significant bytes key 0x0 0x20 RW OEM1KEYR2 OEM1 most significant bytes key 0x0 0x20 RW RDP Level 2 Password OEM2KEYR1 OEM2 least significant bytes key 0x0 0x20 RW OEM2KEYR2 OEM2 most significant bytes key 0x0 0x20 RW