0x497 STMicroelectronics MCU Cortex-M0+/M4 STM32WLxx STM32WL ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x8 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 nBOOT0=1 nBOOT1 Together with the BOOT0 pin or option bit nBOOT0, this bit selects boot mode from the user Flash memory, SRAM1 or system Flash memory . Refer to Reference Manual: Boot configuration Section. 0x17 0x1 RW nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM_RST 0x19 0x1 RW SRAM1 and SRAM2 are erased when a system reset occurs SRAM1 and SRAM2 are not erased when a system reset occurs SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_STDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDG_STOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog BOOT_LOCK 0x1E 0x1 RW CPU1 CM4 Boot lock disabled CPU1 CM4 Boot lock enabled C2BOOT_LOCK 0x1F 0x1 RW CPU2 CM0+ Boot lock disabled CPU2 CM0+ Boot lock enabled IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE ESE 0x8 0x1 RW Security disabled Security enabled PCROP Protection PCROP1A_STRT PCROP1A_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone A 0x0 0x8 RW PCROP1A_END PCROP1A_END[7:0] contain the last included 1kB page readout protected of the Flash area zone A 0x0 0x8 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT PCROP1B_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone B 0x0 0x8 RW PCROP1B_END PCROP1B_END[7:0] contain the last included 1kB page readout protected of the Flash area zone B 0x0 0x8 RW Write Protection WRP1A_STRT WRP1A_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone A. 0x0 0x7 RW WRP1A_END WRP1A_END[6:0] contain the last included 2kB page write protected of the Flash area zone A. 0x10 0x7 RW WRP1B_STRT WRP1B_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone B. 0x0 0x7 RW WRP1B_END WRP1B_END[6:0] contain the last included 2kB page write protected of the Flash area zone B. 0x10 0x7 RW Security Configuration Option bytes SFSA This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area. 0x0 0x7 RW FSD 0x7 0x1 RW System and Flash secure. This bit can only be accessed when HDPADIS = 0 System and Flash non-secure. This bit can only be accessed when HDPADIS = 0 DDS 0xC 0x1 RW CPU2 debug access enabled (when also enabled by C2SWDBGEN) CPU2 debug access disabled (when also enabled by C2SWDBGEN) HDPSA HDPSA[6:0] contain the start address of the first 2 kB page of the User Flash hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash hide protection area enabled. 0x10 0x7 RW HDPAD User Flash hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0 0x17 0x1 RW User Flash hide protection area access enabled. User Flash hide protection area access disabled. SUBGHZSPISD SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled 0x1F 0x1 RW FSD=0 and SUBGHZSPISD=0: SPI3 security enabled FSD=0 and SUBGHZSPISD=1: SPI3 security disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM1 or SRAM2, from start address 0x2000 0000 + SBRV. SBRV will address Flash memory, from start address 0x0800 0000 + SBRV. NBRSD 0x1E 0x1 RW SRAM1 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0 SRAM1 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 SNBRSA SNBRSA[4:0] contain the start address of the first 1 kB page of the secure "non-backup" SRAM1 area. To keep the tool working you have to set a value greater or equal to 0xC 0x19 0x5 RW BRSD 0x17 0x1 RW SRAM2 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0 SRAM2 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 SBRSA SBRSA[4:0] contain the start address of the first 1 kB page of the secure backup SRAM2 area. To keep the tool working you have to set a value less than 0x15 0x12 0x5 RW SBRV SBRV[15:0] contain the word (4B) aligned CPU2 boot reset start address offset within the selected memory area by C2OPT. 0x0 0x10 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 nBOOT0=1 nBOOT1 Together with the BOOT0 pin or option bit nBOOT0, this bit selects boot mode from the user Flash memory, SRAM1 or system Flash memory . Refer to Reference Manual: Boot configuration Section. 0x17 0x1 RW nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM_RST 0x19 0x1 RW SRAM1 and SRAM2 are erased when a system reset occurs SRAM1 and SRAM2 are not erased when a system reset occurs SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_STDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDG_STOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog BOOT_LOCK 0x1E 0x1 RW CPU1 CM4 Boot lock disabled CPU1 CM4 Boot lock enabled C2BOOT_LOCK 0x1F 0x1 RW CPU2 CM0+ Boot lock disabled CPU2 CM0+ Boot lock enabled IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW PCROP Protection PCROP1A_STRT PCROP1A_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone A 0x0 0x8 RW PCROP1A_END PCROP1A_END[7:0] contain the last included 1kB page readout protected of the Flash area zone A 0x0 0x8 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT PCROP1B_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone B 0x0 0x8 RW PCROP1B_END PCROP1B_END[7:0] contain the last included 1kB page readout protected of the Flash area zone B 0x0 0x8 RW Write Protection WRP1A_STRT WRP1A_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone A 0x0 0x7 RW WRP1A_END WRP1A_END[6:0] contain the last included 2kB page write protected of the Flash area zone A 0x10 0x7 RW WRP1B_STRT WRP1B_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone B 0x0 0x7 RW WRP1B_END WRP1B_END[6:0] contain the last included 2kB page write protected of the Flash area zone B 0x10 0x7 RW