0x485 STMicroelectronics MCU Cortex-M7 STM32H7RSxx STM32H7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x2 Option Bytes Configuration RW Product State PRODUCT_STATE Virtual Product State 0x0 0x8 RW Open Provisioning Closed Locked FLASH ROT programming IROT_SELECT iRoT selection 0x18 0x8 R OEM iRoT is selected at boot ST iRoT is selected at boot IROT_SELECT iRoT selection 0x18 0x8 W OEM iRoT is selected at boot ST iRoT is selected at boot OTP write protection OTPL OTP Lock 0x0 0x10 R OTPL OTP Lock 0x0 0x10 W Write Protection WRPS 0x0 0x8 R Write protection active Write protection not active WRPS 0x0 0x8 W Write protection active Write protection not active Flash HDP bank HDP_AREA_START This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. 0x0 0x9 R HDP_AREA_END This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. 0x10 0x9 R HDP_AREA_START This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. 0x0 0x9 W HDP_AREA_END This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. 0x10 0x9 W BOR Level BOR_LEV These bits reflects the power level that generates a system reset. 0x2 0x2 R BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV These bits reflects the power level that generates a system reset. 0x2 0x2 W BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration1 IWDG_HW 0x4 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP 0x6 0x1 R Independent WDG generates a reset if STOP mode is requested Independent WDG does not generate a reset if STOP mode is requested NRST_STBY 0x7 0x1 R Independent WDG generates a reset if STANDBY mode is requested Independent WDG does not generate a reset if STANDBY mode is requested XSPI1_HSLV 0x8 0x1 R I/O XSPIM_P1 High-Speed option disabled I/O XSPIM_P1 High-Speed option enabled XSPI2_HSLV 0x9 0x1 R I/O XSPIM_P2 High-Speed option disabled I/O XSPIM_P2 High-Speed option enabled IWDG_FZ_STOP 0x11 0x1 R Independent watchdog frozen in Stop mode Independent watchdog keep running in Stop mode IWDG_FZ_SDBY 0x12 0x1 R Independent watchdog frozen in Standby mode Independent watchdog keep running in Standby mode VDDIO_HSLV 0x1D 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_HW 0x4 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP 0x6 0x1 W Independent WDG generates a reset if STOP mode is requested Independent WDG does not generate a reset if STOP mode is requested NRST_STBY 0x7 0x1 W Independent WDG generates a reset if STANDBY mode is requested Independent WDG does not generate a reset if STANDBY mode is requested XSPI1_HSLV 0x8 0x1 W I/O XSPIM_P1 High-Speed option disabled I/O XSPIM_P1 High-Speed option enabled XSPI2_HSLV 0x9 0x1 W I/O XSPIM_P2 High-Speed option disabled I/O XSPIM_P2 High-Speed option enabled IWDG_FZ_STOP 0x11 0x1 W Independent watchdog frozen in Stop mode Independent watchdog keep running in Stop mode IWDG_FZ_SDBY 0x12 0x1 W Independent watchdog frozen in Standby mode Independent watchdog keep running in Standby mode VDDIO_HSLV 0x1D 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed ITCM RAM Protection ITCM_AXI_SHARE 0x0 0x3 R ITCM 64 Kbytes ITCM 128 Kbytes ITCM 192 Kbytes ITCM 64 Kbytes ITCM_AXI_SHARE 0x0 0x3 W ITCM 64 Kbytes ITCM 128 Kbytes ITCM 192 Kbytes ITCM 64 Kbytes DTCM RAM Protection DTCM_AXI_SHARE 0x4 0x3 R DTCM 64 Kbytes DTCM 128 Kbytes DTCM 192 Kbytes DTCM 64 Kbytes DTCM_AXI_SHARE 0x4 0x3 W DTCM 64 Kbytes DTCM 128 Kbytes DTCM 192 Kbytes DTCM 64 Kbytes User Configuration 2 ECC_ON_SRAM 0x8 0x1 R ECC_ON_SRAM disabled ECC_ON_SRAM enabled ECC_ON_SRAM 0x8 0x1 W ECC_ON_SRAM disabled ECC_ON_SRAM enabled I2C_NI3C 0x9 0x1 R I3C is selected I2C is selected I2C_NI3C 0x9 0x1 W I3C is selected I2C is selected Product State PRODUCT_STATE Virtual Product State 0x0 0x8 RW Open Provisioning Closed Locked FLASH ROT programming IROT_SELECT iRoT selection 0x18 0x8 R OEM iRoT is selected at boot ST iRoT is selected at boot IROT_SELECT iRoT selection 0x18 0x8 W OEM iRoT is selected at boot ST iRoT is selected at boot OTP write protection OTPL OTP Lock 0x0 0x10 R OTPL OTP Lock 0x0 0x10 W Write Protection WRPS 0x0 0x8 R Write protection active Write protection not active WRPS 0x0 0x8 W Write protection active Write protection not active Flash HDP bank HDP_AREA_START This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. 0x0 0x9 R HDP_AREA_END This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. 0x10 0x9 R HDP_AREA_START This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. 0x0 0x9 W HDP_AREA_END This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. 0x10 0x9 W BOR Level BOR_LEV These bits reflects the power level that generates a system reset. 0x2 0x2 R BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV These bits reflects the power level that generates a system reset. 0x2 0x2 W BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration1 IWDG_HW 0x4 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP 0x6 0x1 R Independent WDG generates a reset if STOP mode is requested Independent WDG does not generate a reset if STOP mode is requested NRST_STBY 0x7 0x1 R Independent WDG generates a reset if STANDBY mode is requested Independent WDG does not generate a reset if STANDBY mode is requested XSPI1_HSLV 0x8 0x1 R I/O XSPIM_P1 High-Speed option disabled I/O XSPIM_P1 High-Speed option enabled XSPI2_HSLV 0x9 0x1 R I/O XSPIM_P2 High-Speed option disabled I/O XSPIM_P2 High-Speed option enabled IWDG_FZ_STOP 0x11 0x1 R Independent watchdog frozen in Stop mode Independent watchdog keep running in Stop mode IWDG_FZ_SDBY 0x12 0x1 R Independent watchdog frozen in Standby mode Independent watchdog keep running in Standby mode VDDIO_HSLV 0x1D 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_HW 0x4 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP 0x6 0x1 W Independent WDG generates a reset if STOP mode is requested Independent WDG does not generate a reset if STOP mode is requested NRST_STBY 0x7 0x1 W Independent WDG generates a reset if STANDBY mode is requested Independent WDG does not generate a reset if STANDBY mode is requested XSPI1_HSLV 0x8 0x1 W I/O XSPIM_P1 High-Speed option disabled I/O XSPIM_P1 High-Speed option enabled XSPI2_HSLV 0x9 0x1 W I/O XSPIM_P2 High-Speed option disabled I/O XSPIM_P2 High-Speed option enabled IWDG_FZ_STOP 0x11 0x1 W Independent watchdog frozen in Stop mode Independent watchdog keep running in Stop mode IWDG_FZ_SDBY 0x12 0x1 W Independent watchdog frozen in Standby mode Independent watchdog keep running in Standby mode VDDIO_HSLV 0x1D 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed ITCM RAM Protection ITCM_AXI_SHARE 0x0 0x3 R ITCM 64 Kbytes ITCM 128 Kbytes ITCM 192 Kbytes ITCM 64 Kbytes ITCM_AXI_SHARE 0x0 0x3 W ITCM 64 Kbytes ITCM 128 Kbytes ITCM 192 Kbytes ITCM 64 Kbytes DTCM RAM Protection DTCM_AXI_SHARE 0x4 0x3 R DTCM 64 Kbytes DTCM 128 Kbytes DTCM 192 Kbytes DTCM 64 Kbytes DTCM_AXI_SHARE 0x4 0x3 W DTCM 64 Kbytes DTCM 128 Kbytes DTCM 192 Kbytes DTCM 64 Kbytes User Configuration 2 ECC_ON_SRAM 0x8 0x1 R ECC_ON_SRAM disabled ECC_ON_SRAM enabled ECC_ON_SRAM 0x8 0x1 W ECC_ON_SRAM disabled ECC_ON_SRAM enabled I2C_NI3C 0x9 0x1 R I3C is selected I2C is selected I2C_NI3C 0x9 0x1 W I3C is selected I2C is selected