0x450 STMicroelectronics MCU Cortex-M7 STM32H7xx STM32H7 ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x20 Single 0x20 ITCM Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x20 Single 0x20 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RSS BOR Level BOR_LEV These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. 0x2 0x2 R reset level is set to VBOR0 reset level is set to VBOR1 reset level is set to VBOR2 reset level is set to VBOR3 BOR_LEV These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. 0x2 0x2 W reset level is set to VBOR0 reset level is set to VBOR1 reset level is set to VBOR2 reset level is set to VBOR3 User Configuration IWDG1_SW 0x4 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software IWDG2_SW 0x5 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP_D1 0x6 0x1 R STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY_D1 0x7 0x1 R STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset FZ_IWDG_STOP 0x11 0x1 R Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 R Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 R Security feature disabled Security feature enabled BCM4 0x16 0x1 R CM4 boot disabled CM4 boot enabled BCM7 0x17 0x1 R CM7 boot disabled CM7 boot enabled NRST_STOP_D2 0x18 0x1 R STOP mode on Domain 2 is entering with reset STOP mode on Domain 2 is entering without reset NRST_STBY_D2 0x19 0x1 R STANDBY mode on Domain 2 is entering with reset STANDBY mode on Domain 2 is entering without reset SWAP_BANK 0x1F 0x1 R after boot loading, no swap for user sectors after boot loading, user sectors swapped IO_HSLV I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V 0x1D 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG1_SW 0x4 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software IWDG2_SW 0x5 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP_D1 0x6 0x1 W STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY_D1 0x7 0x1 W STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset FZ_IWDG_STOP 0x11 0x1 W Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 W Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 W Security feature disabled Security feature enabled IO_HSLV I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V 0x1D 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed BCM4 0x16 0x1 W CM4 boot disabled CM4 boot enabled BCM7 0x17 0x1 W CM7 boot disabled CM7 boot enabled NRST_STOP_D2 0x18 0x1 W STOP mode on Domain 2 is entering with reset STOP mode on Domain 2 is entering without reset NRST_STBY_D2 0x19 0x1 W STANDBY mode on Domain 2 is entering with reset STANDBY mode on Domain 2 is entering without reset SWAP_BANK 0x1F 0x1 W after boot loading, no swap for user sectors after boot loading, user sectors swapped Boot address Option Bytes BOOT_CM7_ADD0 Define the boot address for Cortex-M7 when BOOT0=0 0x0 0x10 R BOOT_CM7_ADD1 Define the boot address for Cortex-M7 when BOOT0=1 0x10 0x10 R BOOT_CM4_ADD0 Define the boot address for Cortex-M4 when BOOT0=0 0x0 0x10 R BOOT_CM4_ADD1 Define the boot address for Cortex-M4 when BOOT0=1 0x10 0x10 R BOOT_CM7_ADD0 0x0 0x10 W BOOT_CM7_ADD1 0x10 0x10 W BOOT_CM4_ADD0 0x0 0x10 W BOOT_CM4_ADD1 0x10 0x10 W PCROP Protection PROT_AREA_START1 Flash Bank 1 PCROP start address 0x0 0xC R PROT_AREA_END1 Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. 0x10 0xC R DMEP1 0x1F 0x1 R Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START1 Flash Bank 1 PCROP start address 0x0 0xC W PROT_AREA_END1 Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP1 0x1F 0x1 W Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START2 Flash Bank 2 PCROP start address 0x0 0xC R PROT_AREA_END2 Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC R DMEP2 0x1F 0x1 R Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START2 Flash Bank 2 PCROP start address 0x0 0xC W PROT_AREA_END2 Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP2 0x1F 0x1 W Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs Secure Protection SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC R SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC R DMES1 0x1F 0x1 R Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC W SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC W DMES1 0x1F 0x1 W Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC R SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC R DMES2 0x1F 0x1 R Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC W SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC W DMES2 0x1F 0x1 W Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs DTCM RAM Protection ST_RAM_SIZE 0x13 0x2 R 2 KB 4 KB 8 KB 16 KB ST_RAM_SIZE 0x13 0x2 W 2 KB 4 KB 8 KB 16 KB Write Protection nWRP0 0x0 0x8 R Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x1 R Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x1 W Write protection active on this sector Write protection not active on this sector nWRP8 0x0 0x8 R Write protection active on this sector Write protection not active on this sector nWRP8 0x0 0x8 W Write protection active on this sector Write protection not active on this sector