0x474 STMicroelectronics MCU Cortex-M33 STM32H50x STM32H5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0xFF RWE Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x10 Dual 0x10 Data EEPROM Storage Dummy config to support flash mapped at 0x0C000000 0xFF RWE Dual 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x2 Option Bytes Configuration RW Product state PRODUCT_STATE Life state code. 0x8 0x8 R Open Provisioning Provisioned Closed Locked PRODUCT_STATE Life state code. 0x8 0x8 W Open Provisioning Provisioned Closed Locked BOR Level BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R disabled enabled BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W disabled enabled BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. 0x11 0x1 R High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. 0x11 0x1 W High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V) IO_VDD_HSLV High-speed IO at low VDD voltage status bit. 0x10 0x1 R High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V) IO_VDD_HSLV High-speed IO at low VDD voltage status bit. 0x10 0x1 W High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V) IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 R Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 W Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW WWDG control mode option status bit. 0x4 0x1 R WWDG watchdog is controlled by hardware WWDG watchdog is controlled by software WWDG_SW WWDG control mode option status bit. 0x4 0x1 W WWDG watchdog is controlled by hardware WWDG watchdog is controlled by software NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 R a reset is generated when entering Stop mode on core domain no reset generated when entering Stop mode on core domain NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 W a reset is generated when entering Stop mode on core domain no reset generated when entering Stop mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain User Configuration 2 SRAM1_ECC ECC in SRAM1 region configuration bit 0xA 0x1 R SRAM1 ECC check enabled SRAM1 ECC check disabled SRAM1_RST SRAM1 erase upon system reset 0x9 0x1 R SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R SRAM2 ECC check enabled SRAM2 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 erase when system reset 0x3 0x1 R SRAM2 erase when system reset occurs SRAM2 not erased when a system reset occurs SRAM1_ECC ECC in SRAM1 region configuration bit 0xA 0x1 W SRAM1 ECC check enabled SRAM1 ECC check disabled SRAM1_RST SRAM1 erase upon system reset 0x9 0x1 W SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W SRAM2 ECC check enabled SRAM2 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 erase when system reset 0x3 0x1 W SRAM2 erase when system reset occurs SRAM2 not erased when a system reset occurs Boot Configuration NSBOOTADD Unique Boot Entry Address 0x8 0x18 R NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0x0 0x8 R The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD and SWAP_BANK are frozen. NSBOOTADD Unique Boot Entry Address 0x8 0x18 W NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0x0 0x8 W The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD and SWAP_BANK are frozen. Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x8 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x8 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x8 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x8 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash HDP bank 1 HDP1_STRT Bank 1 HDP barrier start set in number of 8kb sectors 0x0 0x3 R HDP1_END Bank 1 HDP barrier end set in number of 8kb sectors 0x10 0x3 R HDP1_STRT Bank 1 HDP barrier start set in number of 8kb sectors 0x0 0x3 W HDP1_END Bank 1 HDP barrier end set in number of 8kb sectors 0x10 0x3 W Flash HDP bank 2 HDP2_STRT Bank 2 HDP barrier start set in number of 8kb sectors 0x0 0x3 R HDP2_END Bank 2 HDP barrier end set in number of 8kb sectors 0x10 0x3 R HDP2_STRT Bank 2 HDP barrier start set in number of 8kb sectors 0x0 0x3 W HDP2_END Bank 2 HDP barrier end set in number of 8kb sectors 0x10 0x3 W Product state PRODUCT_STATE Life state code. 0x8 0x8 R Open Provisioning Provisioned Closed Locked PRODUCT_STATE Life state code. 0x8 0x8 W Open Provisioning Provisioned Closed Locked BOR Level BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R disabled enabled BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W disabled enabled BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. 0x11 0x1 R High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. 0x11 0x1 W High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V) IO_VDD_HSLV High-speed IO at low VDD voltage status bit. 0x10 0x1 R High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V) IO_VDD_HSLV High-speed IO at low VDD voltage status bit. 0x10 0x1 W High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V) IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 R Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 W Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW WWDG control mode option status bit. 0x4 0x1 R WWDG watchdog is controlled by hardware WWDG watchdog is controlled by software WWDG_SW WWDG control mode option status bit. 0x4 0x1 W WWDG watchdog is controlled by hardware WWDG watchdog is controlled by software NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 R a reset is generated when entering Stop mode on core domain no reset generated when entering Stop mode on core domain NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 W a reset is generated when entering Stop mode on core domain no reset generated when entering Stop mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain User Configuration 2 SRAM1_ECC ECC in SRAM1 region configuration bit 0xA 0x1 R SRAM1 ECC check enabled SRAM1 ECC check disabled SRAM1_RST SRAM1 erase upon system reset 0x9 0x1 R SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R SRAM2 ECC check enabled SRAM2 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 erase when system reset 0x3 0x1 R SRAM2 erase when system reset occurs SRAM2 not erased when a system reset occurs SRAM1_ECC ECC in SRAM1 region configuration bit 0xA 0x1 W SRAM1 ECC check enabled SRAM1 ECC check disabled SRAM1_RST SRAM1 erase upon system reset 0x9 0x1 W SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W SRAM2 ECC check enabled SRAM2 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 erase when system reset 0x3 0x1 W SRAM2 erase when system reset occurs SRAM2 not erased when a system reset occurs Boot Configuration NSBOOTADD Unique Boot Entry Address 0x8 0x18 R NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0x0 0x8 R The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD and SWAP_BANK are frozen. NSBOOTADD Unique Boot Entry Address 0x8 0x18 W NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0x0 0x8 W The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD and SWAP_BANK are frozen. Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x8 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x8 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x8 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x8 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash HDP bank 1 HDP1_STRT Bank 1 HDP barrier start set in number of 8kb sectors 0x0 0x3 R HDP1_END Bank 1 HDP barrier end set in number of 8kb sectors 0x10 0x3 R HDP1_STRT Bank 1 HDP barrier start set in number of 8kb sectors 0x0 0x3 W HDP1_END Bank 1 HDP barrier end set in number of 8kb sectors 0x10 0x3 W Flash HDP bank 2 HDP2_STRT Bank 2 HDP barrier start set in number of 8kb sectors 0x0 0x3 R HDP2_END Bank 2 HDP barrier end set in number of 8kb sectors 0x10 0x3 R HDP2_STRT Bank 2 HDP barrier start set in number of 8kb sectors 0x0 0x3 W HDP2_END Bank 2 HDP barrier end set in number of 8kb sectors 0x10 0x3 W Product state PRODUCT_STATE Life state code. 0x8 0x8 R Open Provisioning Provisioned Closed Locked PRODUCT_STATE Life state code. 0x8 0x8 W Open Provisioning Provisioned Closed Locked BOR Level BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R disabled enabled BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W disabled enabled BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. 0x11 0x1 R High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. 0x11 0x1 W High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V) IO_VDD_HSLV High-speed IO at low VDD voltage status bit. 0x10 0x1 R High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V) IO_VDD_HSLV High-speed IO at low VDD voltage status bit. 0x10 0x1 W High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V) IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 R Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 W Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW WWDG control mode option status bit. 0x4 0x1 R WWDG watchdog is controlled by hardware WWDG watchdog is controlled by software WWDG_SW WWDG control mode option status bit. 0x4 0x1 W WWDG watchdog is controlled by hardware WWDG watchdog is controlled by software NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 R a reset is generated when entering Stop mode on core domain no reset generated when entering Stop mode on core domain NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 W a reset is generated when entering Stop mode on core domain no reset generated when entering Stop mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain User Configuration 2 SRAM1_ECC ECC in SRAM1 region configuration bit 0xA 0x1 R SRAM1 ECC check enabled SRAM1 ECC check disabled SRAM1_RST SRAM1 erase upon system reset 0x9 0x1 R SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R SRAM2 ECC check enabled SRAM2 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 erase when system reset 0x3 0x1 R SRAM2 erase when system reset occurs SRAM2 not erased when a system reset occurs SRAM1_ECC ECC in SRAM1 region configuration bit 0xA 0x1 W SRAM1 ECC check enabled SRAM1 ECC check disabled SRAM1_RST SRAM1 erase upon system reset 0x9 0x1 W SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W SRAM2 ECC check enabled SRAM2 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 erase when system reset 0x3 0x1 W SRAM2 erase when system reset occurs SRAM2 not erased when a system reset occurs Boot Configuration NSBOOTADD Unique Boot Entry Address 0x8 0x18 R NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0x0 0x8 R The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD and SWAP_BANK are frozen. NSBOOTADD Unique Boot Entry Address 0x8 0x18 W NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0x0 0x8 W The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD and SWAP_BANK are frozen. OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x8 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x8 W Flash HDP bank 1 HDP1_STRT Bank 1 HDP barrier start set in number of 8kb sectors 0x0 0x3 R HDP1_END Bank 1 HDP barrier end set in number of 8kb sectors 0x10 0x3 R HDP1_STRT Bank 1 HDP barrier start set in number of 8kb sectors 0x0 0x3 W HDP1_END Bank 1 HDP barrier end set in number of 8kb sectors 0x10 0x3 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x8 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x8 W Flash HDP bank 2 HDP2_STRT Bank 2 HDP barrier start set in number of 8kb sectors 0x0 0x3 R HDP2_END Bank 2 HDP barrier end set in number of 8kb sectors 0x10 0x3 R HDP2_STRT Bank 2 HDP barrier start set in number of 8kb sectors 0x0 0x3 W HDP2_END Bank 2 HDP barrier end set in number of 8kb sectors 0x10 0x3 W