/** ****************************************************************************** * @file ATON.h * @brief Macros related to the Neural-Art embodiement found in STM32N6 ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #ifndef ATON_H #define ATON_H #ifdef __cplusplus extern "C" { #endif #include #include #include /* ********************************************************************************************************************************************************** */ /* */ /* HELPER MACROS */ /* */ /* ********************************************************************************************************************************************************** */ /** Mask for retrieving the content of a field of a register. */ #define ATON_FIELD_MASK(OFFSET, SIZE) ((uint32_t)(((1ULL << (SIZE)) - 1ULL) << (OFFSET))) /** Get the content of a field of a register. */ #define ATON_GET_FIELD(REG, OFFSET, SIZE) (((REG) & ATON_FIELD_MASK((OFFSET), (SIZE))) >> (OFFSET)) /** Set the content of a field of a register. */ #define ATON_SET_FIELD(REG, OFFSET, SIZE, DATA) (((REG) & (~ATON_FIELD_MASK((OFFSET), (SIZE)))) | (((DATA) << (OFFSET)) & ATON_FIELD_MASK((OFFSET), (SIZE)))) /* ********************************************************************************************************************************************************** */ /* */ /* ENUMERATED VALUES */ /* */ /* ********************************************************************************************************************************************************** */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* ACTIVTYPE set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Activation type: ReLU. */ #define ATON_ACTIVTYPE_RELU (0x0UL) /** Activation type: Parametric ReLU. */ #define ATON_ACTIVTYPE_PRELU (0x1UL) /** Activation type: Thresholded ReLU. */ #define ATON_ACTIVTYPE_TRELU (0x2UL) /** Activation type: Function evaluator. */ #define ATON_ACTIVTYPE_FUNCTION (0x3UL) /** Get the name of one of the values of the ACTIVTYPE set of enumerated values. */ #define ATON_ACTIVTYPE_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "RELU" : \ (((VALUE) == 1UL) ? "PRELU" : \ (((VALUE) == 2UL) ? "TRELU" : \ (((VALUE) == 3UL) ? "FUNCTION" : "")))) /** * Check if a value of the ACTIVTYPE set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the ACTIVTYPE set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_ACTIVTYPE_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_ACTIVTYPE_RELU: case ATON_ACTIVTYPE_PRELU: case ATON_ACTIVTYPE_TRELU: case ATON_ACTIVTYPE_FUNCTION: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the ACTIVTYPE set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the ACTIVTYPE set of enumerated values */ static inline const int8_t *ATON_ACTIVTYPE_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_ACTIVTYPE_RELU: str = (const int8_t *)"RELU"; break; case ATON_ACTIVTYPE_PRELU: str = (const int8_t *)"PRELU"; break; case ATON_ACTIVTYPE_TRELU: str = (const int8_t *)"TRELU"; break; case ATON_ACTIVTYPE_FUNCTION: str = (const int8_t *)"FUNCTION"; break; default: break; } return str; } /** * Get the description of one of the values of the ACTIVTYPE set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the ACTIVTYPE set of enumerated values */ static inline const int8_t *ATON_ACTIVTYPE_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_ACTIVTYPE_RELU: str = (const int8_t *)"ReLU"; break; case ATON_ACTIVTYPE_PRELU: str = (const int8_t *)"Parametric ReLU"; break; case ATON_ACTIVTYPE_TRELU: str = (const int8_t *)"Thresholded ReLU"; break; case ATON_ACTIVTYPE_FUNCTION: str = (const int8_t *)"Function evaluator"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* ACTIV_ROM set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Activation unit ROM offsets: Activation unit ROM 0 offset. */ #define ATON_ACTIV_ROM_OFFSET_0 (0x400UL) /** Activation unit ROM offsets: Activation unit ROM 1 offset. */ #define ATON_ACTIV_ROM_OFFSET_1 (0x800UL) /** Get the name of one of the values of the ACTIV_ROM set of enumerated values. */ #define ATON_ACTIV_ROM_GET_NAME(VALUE) \ (((VALUE) == 1024UL) ? "OFFSET_0" : \ (((VALUE) == 2048UL) ? "OFFSET_1" : "")) /** * Check if a value of the ACTIV_ROM set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the ACTIV_ROM set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_ACTIV_ROM_IsValid(uint32_t val) { bool retval = false; switch (val) { case ATON_ACTIV_ROM_OFFSET_0: case ATON_ACTIV_ROM_OFFSET_1: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the ACTIV_ROM set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the ACTIV_ROM set of enumerated values */ static inline const int8_t *ATON_ACTIV_ROM_GetName(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_ACTIV_ROM_OFFSET_0: str = (const int8_t *)"OFFSET_0"; break; case ATON_ACTIV_ROM_OFFSET_1: str = (const int8_t *)"OFFSET_1"; break; default: break; } return str; } /** * Get the description of one of the values of the ACTIV_ROM set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the ACTIV_ROM set of enumerated values */ static inline const int8_t *ATON_ACTIV_ROM_GetDesc(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_ACTIV_ROM_OFFSET_0: str = (const int8_t *)"Activation unit ROM 0 offset"; break; case ATON_ACTIV_ROM_OFFSET_1: str = (const int8_t *)"Activation unit ROM 1 offset"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* ARITHOP set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Arithmetic operation: Ax + By + C. */ #define ATON_ARITHOP_AX_BY_C (0x0UL) /** Arithmetic operation: min(X,Y). */ #define ATON_ARITHOP_MIN_X_Y (0x1UL) /** Arithmetic operation: max(X,Y). */ #define ATON_ARITHOP_MAX_X_Y (0x2UL) /** Arithmetic operation: X*Y. */ #define ATON_ARITHOP_XY (0x7UL) /** Arithmetic operation: X&Y. */ #define ATON_ARITHOP_X_AND_Y (0xbUL) /** Arithmetic operation: X|Y. */ #define ATON_ARITHOP_X_OR_Y (0xfUL) /** Arithmetic operation: !X. */ #define ATON_ARITHOP_NOT_X (0x13UL) /** Arithmetic operation: X^Y. */ #define ATON_ARITHOP_X_XOR_Y (0x17UL) /** Arithmetic operation: X==Y. */ #define ATON_ARITHOP_X_EQ_Y (0x1bUL) /** Arithmetic operation: XY. */ #define ATON_ARITHOP_X_GT_Y (0x27UL) /** Arithmetic operation: X>=Y. */ #define ATON_ARITHOP_X_GE_Y (0x2bUL) /** Arithmetic operation: ABS(X). */ #define ATON_ARITHOP_ABS_X (0x2fUL) /** Arithmetic operation: SIGN(X). */ #define ATON_ARITHOP_SIGN_X (0x33UL) /** Arithmetic operation: CLIP. */ #define ATON_ARITHOP_CLIP (0x37UL) /** Get the name of one of the values of the ARITHOP set of enumerated values. */ #define ATON_ARITHOP_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "AX_BY_C" : \ (((VALUE) == 1UL) ? "MIN_X_Y" : \ (((VALUE) == 2UL) ? "MAX_X_Y" : \ (((VALUE) == 7UL) ? "XY" : \ (((VALUE) == 11UL) ? "X_AND_Y" : \ (((VALUE) == 15UL) ? "X_OR_Y" : \ (((VALUE) == 19UL) ? "NOT_X" : \ (((VALUE) == 23UL) ? "X_XOR_Y" : \ (((VALUE) == 27UL) ? "X_EQ_Y" : \ (((VALUE) == 31UL) ? "X_LT_Y" : \ (((VALUE) == 35UL) ? "X_LE_Y" : \ (((VALUE) == 39UL) ? "X_GT_Y" : \ (((VALUE) == 43UL) ? "X_GE_Y" : \ (((VALUE) == 47UL) ? "ABS_X" : \ (((VALUE) == 51UL) ? "SIGN_X" : \ (((VALUE) == 55UL) ? "CLIP" : "")))))))))))))))) /** * Check if a value of the ARITHOP set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the ARITHOP set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_ARITHOP_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_ARITHOP_AX_BY_C: case ATON_ARITHOP_MIN_X_Y: case ATON_ARITHOP_MAX_X_Y: case ATON_ARITHOP_XY: case ATON_ARITHOP_X_AND_Y: case ATON_ARITHOP_X_OR_Y: case ATON_ARITHOP_NOT_X: case ATON_ARITHOP_X_XOR_Y: case ATON_ARITHOP_X_EQ_Y: case ATON_ARITHOP_X_LT_Y: case ATON_ARITHOP_X_LE_Y: case ATON_ARITHOP_X_GT_Y: case ATON_ARITHOP_X_GE_Y: case ATON_ARITHOP_ABS_X: case ATON_ARITHOP_SIGN_X: case ATON_ARITHOP_CLIP: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the ARITHOP set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the ARITHOP set of enumerated values */ static inline const int8_t *ATON_ARITHOP_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_ARITHOP_AX_BY_C: str = (const int8_t *)"AX_BY_C"; break; case ATON_ARITHOP_MIN_X_Y: str = (const int8_t *)"MIN_X_Y"; break; case ATON_ARITHOP_MAX_X_Y: str = (const int8_t *)"MAX_X_Y"; break; case ATON_ARITHOP_XY: str = (const int8_t *)"XY"; break; case ATON_ARITHOP_X_AND_Y: str = (const int8_t *)"X_AND_Y"; break; case ATON_ARITHOP_X_OR_Y: str = (const int8_t *)"X_OR_Y"; break; case ATON_ARITHOP_NOT_X: str = (const int8_t *)"NOT_X"; break; case ATON_ARITHOP_X_XOR_Y: str = (const int8_t *)"X_XOR_Y"; break; case ATON_ARITHOP_X_EQ_Y: str = (const int8_t *)"X_EQ_Y"; break; case ATON_ARITHOP_X_LT_Y: str = (const int8_t *)"X_LT_Y"; break; case ATON_ARITHOP_X_LE_Y: str = (const int8_t *)"X_LE_Y"; break; case ATON_ARITHOP_X_GT_Y: str = (const int8_t *)"X_GT_Y"; break; case ATON_ARITHOP_X_GE_Y: str = (const int8_t *)"X_GE_Y"; break; case ATON_ARITHOP_ABS_X: str = (const int8_t *)"ABS_X"; break; case ATON_ARITHOP_SIGN_X: str = (const int8_t *)"SIGN_X"; break; case ATON_ARITHOP_CLIP: str = (const int8_t *)"CLIP"; break; default: break; } return str; } /** * Get the description of one of the values of the ARITHOP set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the ARITHOP set of enumerated values */ static inline const int8_t *ATON_ARITHOP_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_ARITHOP_AX_BY_C: str = (const int8_t *)"Ax + By + C"; break; case ATON_ARITHOP_MIN_X_Y: str = (const int8_t *)"min(X,Y)"; break; case ATON_ARITHOP_MAX_X_Y: str = (const int8_t *)"max(X,Y)"; break; case ATON_ARITHOP_XY: str = (const int8_t *)"X*Y"; break; case ATON_ARITHOP_X_AND_Y: str = (const int8_t *)"X&Y"; break; case ATON_ARITHOP_X_OR_Y: str = (const int8_t *)"X|Y"; break; case ATON_ARITHOP_NOT_X: str = (const int8_t *)"!X"; break; case ATON_ARITHOP_X_XOR_Y: str = (const int8_t *)"X^Y"; break; case ATON_ARITHOP_X_EQ_Y: str = (const int8_t *)"X==Y"; break; case ATON_ARITHOP_X_LT_Y: str = (const int8_t *)"XY"; break; case ATON_ARITHOP_X_GE_Y: str = (const int8_t *)"X>=Y"; break; case ATON_ARITHOP_ABS_X: str = (const int8_t *)"ABS(X)"; break; case ATON_ARITHOP_SIGN_X: str = (const int8_t *)"SIGN(X)"; break; case ATON_ARITHOP_CLIP: str = (const int8_t *)"CLIP"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* ARITH_MEM set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Arithmethic unit MEM offset: Total 4K addressable. 3K starting from 0x000 to 0xbff addressable by setting translate_addr_en=1, top 1K addressable (0xc00-0xfff) by setting translate_addr_en=0. */ #define ATON_ARITH_MEM_OFFSET (0x400UL) /** Get the name of one of the values of the ARITH_MEM set of enumerated values. */ #define ATON_ARITH_MEM_GET_NAME(VALUE) \ (((VALUE) == 1024UL) ? "OFFSET" : "") /** * Check if a value of the ARITH_MEM set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the ARITH_MEM set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_ARITH_MEM_IsValid(uint32_t val) { bool retval = false; switch (val) { case ATON_ARITH_MEM_OFFSET: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the ARITH_MEM set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the ARITH_MEM set of enumerated values */ static inline const int8_t *ATON_ARITH_MEM_GetName(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_ARITH_MEM_OFFSET: str = (const int8_t *)"OFFSET"; break; default: break; } return str; } /** * Get the description of one of the values of the ARITH_MEM set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the ARITH_MEM set of enumerated values */ static inline const int8_t *ATON_ARITH_MEM_GetDesc(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_ARITH_MEM_OFFSET: str = (const int8_t *)"Total 4K addressable. 3K starting from 0x000 to 0xbff addressable by setting translate_addr_en=1, top 1K addressable (0xc00-0xfff) by setting translate_addr_en=0"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* BLOCKTYPE set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Block type: Stream Switch. */ #define ATON_BLOCKTYPE_STRSWITCH (0x0UL) /** Block type: Stream Engine. */ #define ATON_BLOCKTYPE_STRENG (0x1UL) /** Block type: Sensor Interface. */ #define ATON_BLOCKTYPE_SENSOR_IF (0x2UL) /** Block type: Video Output. */ #define ATON_BLOCKTYPE_VIDEO_OUT (0x3UL) /** Block type: IPU Interface. */ #define ATON_BLOCKTYPE_IPU_IF (0x4UL) /** Block type: ISP Interface. */ #define ATON_BLOCKTYPE_ISP_IF (0x5UL) /** Block type: Morph Filter. */ #define ATON_BLOCKTYPE_MORPH (0x6UL) /** Block type: Background Remove. */ #define ATON_BLOCKTYPE_BACKREMOVE (0x7UL) /** Block type: Reference Frame Update. */ #define ATON_BLOCKTYPE_REFUPDATE (0x8UL) /** Block type: ???. */ #define ATON_BLOCKTYPE_CONV (0x9UL) /** Block type: Cropper. */ #define ATON_BLOCKTYPE_CROP (0xaUL) /** Block type: Corner Detector. */ #define ATON_BLOCKTYPE_CORNER_DETECT (0xbUL) /** Block type: Census. */ #define ATON_BLOCKTYPE_CENSUS (0xcUL) /** Block type: Rect. */ #define ATON_BLOCKTYPE_RECT (0xeUL) /** Block type: JPEG Encoder. */ #define ATON_BLOCKTYPE_JPEG_ENC (0xfUL) /** Block type: JPEG Decoder. */ #define ATON_BLOCKTYPE_JPEG_DEC (0x10UL) /** Block type: Debug Controller. */ #define ATON_BLOCKTYPE_DEBUG_CTRL (0x11UL) /** Block type: GP Controller. */ #define ATON_BLOCKTYPE_GP_CTRL (0x12UL) /** Block type: SBDOG. */ #define ATON_BLOCKTYPE_SBDOG (0x13UL) /** Block type: H264 Decoder. */ #define ATON_BLOCKTYPE_H264 (0x14UL) /** Block type: ????. */ #define ATON_BLOCKTYPE_MATCH (0x15UL) /** Block type: ISP. */ #define ATON_BLOCKTYPE_ISP (0x16UL) /** Block type: Convolution Accelerator. */ #define ATON_BLOCKTYPE_CONVACC (0x17UL) /** Block type: I2C. */ #define ATON_BLOCKTYPE_I2C (0x18UL) /** Block type: Decompression Unit. */ #define ATON_BLOCKTYPE_DECUN (0x19UL) /** Block type: Arithmetic Unit. */ #define ATON_BLOCKTYPE_ARITH (0x1aUL) /** Block type: Activation Unit. */ #define ATON_BLOCKTYPE_ACTIV (0x1bUL) /** Block type: Pooling Accelerator. */ #define ATON_BLOCKTYPE_POOL (0x1cUL) /** Block type: Bus Interface. */ #define ATON_BLOCKTYPE_BUSIF (0x1dUL) /** Block type: Interrupt Controller. */ #define ATON_BLOCKTYPE_INTCTRL (0x1eUL) /** Block type: Clock Controller. */ #define ATON_BLOCKTYPE_CLKCTRL (0x1fUL) /** Block type: Reconfigurable Buffer. */ #define ATON_BLOCKTYPE_RECBUF (0x20UL) /** Block type: Epoch Controller. */ #define ATON_BLOCKTYPE_EPOCHCTRL (0x21UL) /** Block type: Debug Trace. */ #define ATON_BLOCKTYPE_DEBUG_TRACE (0x22UL) /** Get the name of one of the values of the BLOCKTYPE set of enumerated values. */ #define ATON_BLOCKTYPE_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "STRSWITCH" : \ (((VALUE) == 1UL) ? "STRENG" : \ (((VALUE) == 2UL) ? "SENSOR_IF" : \ (((VALUE) == 3UL) ? "VIDEO_OUT" : \ (((VALUE) == 4UL) ? "IPU_IF" : \ (((VALUE) == 5UL) ? "ISP_IF" : \ (((VALUE) == 6UL) ? "MORPH" : \ (((VALUE) == 7UL) ? "BACKREMOVE" : \ (((VALUE) == 8UL) ? "REFUPDATE" : \ (((VALUE) == 9UL) ? "CONV" : \ (((VALUE) == 10UL) ? "CROP" : \ (((VALUE) == 11UL) ? "CORNER_DETECT" : \ (((VALUE) == 12UL) ? "CENSUS" : \ (((VALUE) == 14UL) ? "RECT" : \ (((VALUE) == 15UL) ? "JPEG_ENC" : \ (((VALUE) == 16UL) ? "JPEG_DEC" : \ (((VALUE) == 17UL) ? "DEBUG_CTRL" : \ (((VALUE) == 18UL) ? "GP_CTRL" : \ (((VALUE) == 19UL) ? "SBDOG" : \ (((VALUE) == 20UL) ? "H264" : \ (((VALUE) == 21UL) ? "MATCH" : \ (((VALUE) == 22UL) ? "ISP" : \ (((VALUE) == 23UL) ? "CONVACC" : \ (((VALUE) == 24UL) ? "I2C" : \ (((VALUE) == 25UL) ? "DECUN" : \ (((VALUE) == 26UL) ? "ARITH" : \ (((VALUE) == 27UL) ? "ACTIV" : \ (((VALUE) == 28UL) ? "POOL" : \ (((VALUE) == 29UL) ? "BUSIF" : \ (((VALUE) == 30UL) ? "INTCTRL" : \ (((VALUE) == 31UL) ? "CLKCTRL" : \ (((VALUE) == 32UL) ? "RECBUF" : \ (((VALUE) == 33UL) ? "EPOCHCTRL" : \ (((VALUE) == 34UL) ? "DEBUG_TRACE" : "")))))))))))))))))))))))))))))))))) /** * Check if a value of the BLOCKTYPE set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the BLOCKTYPE set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_BLOCKTYPE_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_BLOCKTYPE_STRSWITCH: case ATON_BLOCKTYPE_STRENG: case ATON_BLOCKTYPE_SENSOR_IF: case ATON_BLOCKTYPE_VIDEO_OUT: case ATON_BLOCKTYPE_IPU_IF: case ATON_BLOCKTYPE_ISP_IF: case ATON_BLOCKTYPE_MORPH: case ATON_BLOCKTYPE_BACKREMOVE: case ATON_BLOCKTYPE_REFUPDATE: case ATON_BLOCKTYPE_CONV: case ATON_BLOCKTYPE_CROP: case ATON_BLOCKTYPE_CORNER_DETECT: case ATON_BLOCKTYPE_CENSUS: case ATON_BLOCKTYPE_RECT: case ATON_BLOCKTYPE_JPEG_ENC: case ATON_BLOCKTYPE_JPEG_DEC: case ATON_BLOCKTYPE_DEBUG_CTRL: case ATON_BLOCKTYPE_GP_CTRL: case ATON_BLOCKTYPE_SBDOG: case ATON_BLOCKTYPE_H264: case ATON_BLOCKTYPE_MATCH: case ATON_BLOCKTYPE_ISP: case ATON_BLOCKTYPE_CONVACC: case ATON_BLOCKTYPE_I2C: case ATON_BLOCKTYPE_DECUN: case ATON_BLOCKTYPE_ARITH: case ATON_BLOCKTYPE_ACTIV: case ATON_BLOCKTYPE_POOL: case ATON_BLOCKTYPE_BUSIF: case ATON_BLOCKTYPE_INTCTRL: case ATON_BLOCKTYPE_CLKCTRL: case ATON_BLOCKTYPE_RECBUF: case ATON_BLOCKTYPE_EPOCHCTRL: case ATON_BLOCKTYPE_DEBUG_TRACE: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the BLOCKTYPE set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the BLOCKTYPE set of enumerated values */ static inline const int8_t *ATON_BLOCKTYPE_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_BLOCKTYPE_STRSWITCH: str = (const int8_t *)"STRSWITCH"; break; case ATON_BLOCKTYPE_STRENG: str = (const int8_t *)"STRENG"; break; case ATON_BLOCKTYPE_SENSOR_IF: str = (const int8_t *)"SENSOR_IF"; break; case ATON_BLOCKTYPE_VIDEO_OUT: str = (const int8_t *)"VIDEO_OUT"; break; case ATON_BLOCKTYPE_IPU_IF: str = (const int8_t *)"IPU_IF"; break; case ATON_BLOCKTYPE_ISP_IF: str = (const int8_t *)"ISP_IF"; break; case ATON_BLOCKTYPE_MORPH: str = (const int8_t *)"MORPH"; break; case ATON_BLOCKTYPE_BACKREMOVE: str = (const int8_t *)"BACKREMOVE"; break; case ATON_BLOCKTYPE_REFUPDATE: str = (const int8_t *)"REFUPDATE"; break; case ATON_BLOCKTYPE_CONV: str = (const int8_t *)"CONV"; break; case ATON_BLOCKTYPE_CROP: str = (const int8_t *)"CROP"; break; case ATON_BLOCKTYPE_CORNER_DETECT: str = (const int8_t *)"CORNER_DETECT"; break; case ATON_BLOCKTYPE_CENSUS: str = (const int8_t *)"CENSUS"; break; case ATON_BLOCKTYPE_RECT: str = (const int8_t *)"RECT"; break; case ATON_BLOCKTYPE_JPEG_ENC: str = (const int8_t *)"JPEG_ENC"; break; case ATON_BLOCKTYPE_JPEG_DEC: str = (const int8_t *)"JPEG_DEC"; break; case ATON_BLOCKTYPE_DEBUG_CTRL: str = (const int8_t *)"DEBUG_CTRL"; break; case ATON_BLOCKTYPE_GP_CTRL: str = (const int8_t *)"GP_CTRL"; break; case ATON_BLOCKTYPE_SBDOG: str = (const int8_t *)"SBDOG"; break; case ATON_BLOCKTYPE_H264: str = (const int8_t *)"H264"; break; case ATON_BLOCKTYPE_MATCH: str = (const int8_t *)"MATCH"; break; case ATON_BLOCKTYPE_ISP: str = (const int8_t *)"ISP"; break; case ATON_BLOCKTYPE_CONVACC: str = (const int8_t *)"CONVACC"; break; case ATON_BLOCKTYPE_I2C: str = (const int8_t *)"I2C"; break; case ATON_BLOCKTYPE_DECUN: str = (const int8_t *)"DECUN"; break; case ATON_BLOCKTYPE_ARITH: str = (const int8_t *)"ARITH"; break; case ATON_BLOCKTYPE_ACTIV: str = (const int8_t *)"ACTIV"; break; case ATON_BLOCKTYPE_POOL: str = (const int8_t *)"POOL"; break; case ATON_BLOCKTYPE_BUSIF: str = (const int8_t *)"BUSIF"; break; case ATON_BLOCKTYPE_INTCTRL: str = (const int8_t *)"INTCTRL"; break; case ATON_BLOCKTYPE_CLKCTRL: str = (const int8_t *)"CLKCTRL"; break; case ATON_BLOCKTYPE_RECBUF: str = (const int8_t *)"RECBUF"; break; case ATON_BLOCKTYPE_EPOCHCTRL: str = (const int8_t *)"EPOCHCTRL"; break; case ATON_BLOCKTYPE_DEBUG_TRACE: str = (const int8_t *)"DEBUG_TRACE"; break; default: break; } return str; } /** * Get the description of one of the values of the BLOCKTYPE set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the BLOCKTYPE set of enumerated values */ static inline const int8_t *ATON_BLOCKTYPE_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_BLOCKTYPE_STRSWITCH: str = (const int8_t *)"Stream Switch"; break; case ATON_BLOCKTYPE_STRENG: str = (const int8_t *)"Stream Engine"; break; case ATON_BLOCKTYPE_SENSOR_IF: str = (const int8_t *)"Sensor Interface"; break; case ATON_BLOCKTYPE_VIDEO_OUT: str = (const int8_t *)"Video Output"; break; case ATON_BLOCKTYPE_IPU_IF: str = (const int8_t *)"IPU Interface"; break; case ATON_BLOCKTYPE_ISP_IF: str = (const int8_t *)"ISP Interface"; break; case ATON_BLOCKTYPE_MORPH: str = (const int8_t *)"Morph Filter"; break; case ATON_BLOCKTYPE_BACKREMOVE: str = (const int8_t *)"Background Remove"; break; case ATON_BLOCKTYPE_REFUPDATE: str = (const int8_t *)"Reference Frame Update"; break; case ATON_BLOCKTYPE_CONV: str = (const int8_t *)"???"; break; case ATON_BLOCKTYPE_CROP: str = (const int8_t *)"Cropper"; break; case ATON_BLOCKTYPE_CORNER_DETECT: str = (const int8_t *)"Corner Detector"; break; case ATON_BLOCKTYPE_CENSUS: str = (const int8_t *)"Census"; break; case ATON_BLOCKTYPE_RECT: str = (const int8_t *)"Rect"; break; case ATON_BLOCKTYPE_JPEG_ENC: str = (const int8_t *)"JPEG Encoder"; break; case ATON_BLOCKTYPE_JPEG_DEC: str = (const int8_t *)"JPEG Decoder"; break; case ATON_BLOCKTYPE_DEBUG_CTRL: str = (const int8_t *)"Debug Controller"; break; case ATON_BLOCKTYPE_GP_CTRL: str = (const int8_t *)"GP Controller"; break; case ATON_BLOCKTYPE_SBDOG: str = (const int8_t *)"SBDOG"; break; case ATON_BLOCKTYPE_H264: str = (const int8_t *)"H264 Decoder"; break; case ATON_BLOCKTYPE_MATCH: str = (const int8_t *)"????"; break; case ATON_BLOCKTYPE_ISP: str = (const int8_t *)"ISP"; break; case ATON_BLOCKTYPE_CONVACC: str = (const int8_t *)"Convolution Accelerator"; break; case ATON_BLOCKTYPE_I2C: str = (const int8_t *)"I2C"; break; case ATON_BLOCKTYPE_DECUN: str = (const int8_t *)"Decompression Unit"; break; case ATON_BLOCKTYPE_ARITH: str = (const int8_t *)"Arithmetic Unit"; break; case ATON_BLOCKTYPE_ACTIV: str = (const int8_t *)"Activation Unit"; break; case ATON_BLOCKTYPE_POOL: str = (const int8_t *)"Pooling Accelerator"; break; case ATON_BLOCKTYPE_BUSIF: str = (const int8_t *)"Bus Interface"; break; case ATON_BLOCKTYPE_INTCTRL: str = (const int8_t *)"Interrupt Controller"; break; case ATON_BLOCKTYPE_CLKCTRL: str = (const int8_t *)"Clock Controller"; break; case ATON_BLOCKTYPE_RECBUF: str = (const int8_t *)"Reconfigurable Buffer"; break; case ATON_BLOCKTYPE_EPOCHCTRL: str = (const int8_t *)"Epoch Controller"; break; case ATON_BLOCKTYPE_DEBUG_TRACE: str = (const int8_t *)"Debug Trace"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* CHS set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Channels: CH0 / Red / Y. */ #define ATON_CHS_RY (0x0UL) /** Channels: CH1 / Green / Cb. */ #define ATON_CHS_GCB (0x1UL) /** Channels: CH2 / Blue / Cr. */ #define ATON_CHS_BCR (0x2UL) /** Channels: Reserved / do not use. */ #define ATON_CHS_RES (0x3UL) /** Get the name of one of the values of the CHS set of enumerated values. */ #define ATON_CHS_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "RY" : \ (((VALUE) == 1UL) ? "GCB" : \ (((VALUE) == 2UL) ? "BCR" : \ (((VALUE) == 3UL) ? "RES" : "")))) /** * Check if a value of the CHS set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the CHS set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_CHS_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_CHS_RY: case ATON_CHS_GCB: case ATON_CHS_BCR: case ATON_CHS_RES: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the CHS set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the CHS set of enumerated values */ static inline const int8_t *ATON_CHS_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_CHS_RY: str = (const int8_t *)"RY"; break; case ATON_CHS_GCB: str = (const int8_t *)"GCB"; break; case ATON_CHS_BCR: str = (const int8_t *)"BCR"; break; case ATON_CHS_RES: str = (const int8_t *)"RES"; break; default: break; } return str; } /** * Get the description of one of the values of the CHS set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the CHS set of enumerated values */ static inline const int8_t *ATON_CHS_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_CHS_RY: str = (const int8_t *)"CH0 / Red / Y"; break; case ATON_CHS_GCB: str = (const int8_t *)"CH1 / Green / Cb"; break; case ATON_CHS_BCR: str = (const int8_t *)"CH2 / Blue / Cr"; break; case ATON_CHS_RES: str = (const int8_t *)"Reserved / do not use"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* COEFFTYPE set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Coefficient type: Scalar coefficient type. */ #define ATON_COEFFTYPE_SCALAR (0x0UL) /** Coefficient type: Vector coefficient type. */ #define ATON_COEFFTYPE_VECTOR (0x1UL) /** Get the name of one of the values of the COEFFTYPE set of enumerated values. */ #define ATON_COEFFTYPE_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "SCALAR" : \ (((VALUE) == 1UL) ? "VECTOR" : "")) /** * Check if a value of the COEFFTYPE set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the COEFFTYPE set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_COEFFTYPE_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_COEFFTYPE_SCALAR: case ATON_COEFFTYPE_VECTOR: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the COEFFTYPE set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the COEFFTYPE set of enumerated values */ static inline const int8_t *ATON_COEFFTYPE_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_COEFFTYPE_SCALAR: str = (const int8_t *)"SCALAR"; break; case ATON_COEFFTYPE_VECTOR: str = (const int8_t *)"VECTOR"; break; default: break; } return str; } /** * Get the description of one of the values of the COEFFTYPE set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the COEFFTYPE set of enumerated values */ static inline const int8_t *ATON_COEFFTYPE_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_COEFFTYPE_SCALAR: str = (const int8_t *)"Scalar coefficient type"; break; case ATON_COEFFTYPE_VECTOR: str = (const int8_t *)"Vector coefficient type"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* DECUN_BFMT set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** BFORMAT values: CV1CW1LAST0. */ #define ATON_DECUN_BFMT_CV1CW1LAST0 (0x0UL) /** BFORMAT values: CV1CW2LAST0. */ #define ATON_DECUN_BFMT_CV1CW2LAST0 (0x100UL) /** BFORMAT values: CV1CW3LAST0. */ #define ATON_DECUN_BFMT_CV1CW3LAST0 (0x200UL) /** BFORMAT values: CV1CW4LAST0. */ #define ATON_DECUN_BFMT_CV1CW4LAST0 (0x300UL) /** BFORMAT values: CV1CW5LAST0. */ #define ATON_DECUN_BFMT_CV1CW5LAST0 (0x400UL) /** BFORMAT values: CV1CW6LAST0. */ #define ATON_DECUN_BFMT_CV1CW6LAST0 (0x500UL) /** BFORMAT values: CV1CW7LAST0. */ #define ATON_DECUN_BFMT_CV1CW7LAST0 (0x600UL) /** BFORMAT values: CV1CW8LAST0. */ #define ATON_DECUN_BFMT_CV1CW8LAST0 (0x700UL) /** BFORMAT values: CV1CW2LAST1. */ #define ATON_DECUN_BFMT_CV1CW2LAST1 (0x1100UL) /** BFORMAT values: CV1CW3LAST1. */ #define ATON_DECUN_BFMT_CV1CW3LAST1 (0x1200UL) /** BFORMAT values: CV1CW4LAST1. */ #define ATON_DECUN_BFMT_CV1CW4LAST1 (0x1300UL) /** BFORMAT values: CV1CW5LAST1. */ #define ATON_DECUN_BFMT_CV1CW5LAST1 (0x1400UL) /** BFORMAT values: CV1CW6LAST1. */ #define ATON_DECUN_BFMT_CV1CW6LAST1 (0x1500UL) /** BFORMAT values: CV1CW7LAST1. */ #define ATON_DECUN_BFMT_CV1CW7LAST1 (0x1600UL) /** BFORMAT values: CV1CW8LAST1. */ #define ATON_DECUN_BFMT_CV1CW8LAST1 (0x1700UL) /** BFORMAT values: CV1CW3LAST2. */ #define ATON_DECUN_BFMT_CV1CW3LAST2 (0x2200UL) /** BFORMAT values: CV1CW4LAST2. */ #define ATON_DECUN_BFMT_CV1CW4LAST2 (0x2300UL) /** BFORMAT values: CV1CW5LAST2. */ #define ATON_DECUN_BFMT_CV1CW5LAST2 (0x2400UL) /** BFORMAT values: CV1CW6LAST2. */ #define ATON_DECUN_BFMT_CV1CW6LAST2 (0x2500UL) /** BFORMAT values: CV1CW7LAST2. */ #define ATON_DECUN_BFMT_CV1CW7LAST2 (0x2600UL) /** BFORMAT values: CV1CW8LAST2. */ #define ATON_DECUN_BFMT_CV1CW8LAST2 (0x2700UL) /** BFORMAT values: CV1CW4LAST3. */ #define ATON_DECUN_BFMT_CV1CW4LAST3 (0x3300UL) /** BFORMAT values: CV1CW5LAST3. */ #define ATON_DECUN_BFMT_CV1CW5LAST3 (0x3400UL) /** BFORMAT values: CV1CW6LAST3. */ #define ATON_DECUN_BFMT_CV1CW6LAST3 (0x3500UL) /** BFORMAT values: CV1CW7LAST3. */ #define ATON_DECUN_BFMT_CV1CW7LAST3 (0x3600UL) /** BFORMAT values: CV1CW8LAST3. */ #define ATON_DECUN_BFMT_CV1CW8LAST3 (0x3700UL) /** BFORMAT values: CV1CW5LAST4. */ #define ATON_DECUN_BFMT_CV1CW5LAST4 (0x4400UL) /** BFORMAT values: CV1CW6LAST4. */ #define ATON_DECUN_BFMT_CV1CW6LAST4 (0x4500UL) /** BFORMAT values: CV1CW7LAST4. */ #define ATON_DECUN_BFMT_CV1CW7LAST4 (0x4600UL) /** BFORMAT values: CV1CW8LAST4. */ #define ATON_DECUN_BFMT_CV1CW8LAST4 (0x4700UL) /** BFORMAT values: CV1CW6LAST5. */ #define ATON_DECUN_BFMT_CV1CW6LAST5 (0x5500UL) /** BFORMAT values: CV1CW7LAST5. */ #define ATON_DECUN_BFMT_CV1CW7LAST5 (0x5600UL) /** BFORMAT values: CV1CW8LAST5. */ #define ATON_DECUN_BFMT_CV1CW8LAST5 (0x5700UL) /** BFORMAT values: CV1CW7LAST6. */ #define ATON_DECUN_BFMT_CV1CW7LAST6 (0x6600UL) /** BFORMAT values: CV1CW8LAST6. */ #define ATON_DECUN_BFMT_CV1CW8LAST6 (0x6700UL) /** BFORMAT values: CV1CW8LAST7. */ #define ATON_DECUN_BFMT_CV1CW8LAST7 (0x7700UL) /** BFORMAT values: CV2CW1LAST0. */ #define ATON_DECUN_BFMT_CV2CW1LAST0 (0x1UL) /** BFORMAT values: CV2CW2LAST0. */ #define ATON_DECUN_BFMT_CV2CW2LAST0 (0x101UL) /** BFORMAT values: CV2CW3LAST0. */ #define ATON_DECUN_BFMT_CV2CW3LAST0 (0x201UL) /** BFORMAT values: CV2CW4LAST0. */ #define ATON_DECUN_BFMT_CV2CW4LAST0 (0x301UL) /** BFORMAT values: CV2CW5LAST0. */ #define ATON_DECUN_BFMT_CV2CW5LAST0 (0x401UL) /** BFORMAT values: CV2CW6LAST0. */ #define ATON_DECUN_BFMT_CV2CW6LAST0 (0x501UL) /** BFORMAT values: CV2CW7LAST0. */ #define ATON_DECUN_BFMT_CV2CW7LAST0 (0x601UL) /** BFORMAT values: CV2CW8LAST0. */ #define ATON_DECUN_BFMT_CV2CW8LAST0 (0x701UL) /** BFORMAT values: CV2CW2LAST1. */ #define ATON_DECUN_BFMT_CV2CW2LAST1 (0x1101UL) /** BFORMAT values: CV2CW3LAST1. */ #define ATON_DECUN_BFMT_CV2CW3LAST1 (0x1201UL) /** BFORMAT values: CV2CW4LAST1. */ #define ATON_DECUN_BFMT_CV2CW4LAST1 (0x1301UL) /** BFORMAT values: CV2CW5LAST1. */ #define ATON_DECUN_BFMT_CV2CW5LAST1 (0x1401UL) /** BFORMAT values: CV2CW6LAST1. */ #define ATON_DECUN_BFMT_CV2CW6LAST1 (0x1501UL) /** BFORMAT values: CV2CW7LAST1. */ #define ATON_DECUN_BFMT_CV2CW7LAST1 (0x1601UL) /** BFORMAT values: CV2CW8LAST1. */ #define ATON_DECUN_BFMT_CV2CW8LAST1 (0x1701UL) /** BFORMAT values: CV2CW3LAST2. */ #define ATON_DECUN_BFMT_CV2CW3LAST2 (0x2201UL) /** BFORMAT values: CV2CW4LAST2. */ #define ATON_DECUN_BFMT_CV2CW4LAST2 (0x2301UL) /** BFORMAT values: CV2CW5LAST2. */ #define ATON_DECUN_BFMT_CV2CW5LAST2 (0x2401UL) /** BFORMAT values: CV2CW6LAST2. */ #define ATON_DECUN_BFMT_CV2CW6LAST2 (0x2501UL) /** BFORMAT values: CV2CW7LAST2. */ #define ATON_DECUN_BFMT_CV2CW7LAST2 (0x2601UL) /** BFORMAT values: CV2CW8LAST2. */ #define ATON_DECUN_BFMT_CV2CW8LAST2 (0x2701UL) /** BFORMAT values: CV2CW4LAST3. */ #define ATON_DECUN_BFMT_CV2CW4LAST3 (0x3301UL) /** BFORMAT values: CV2CW5LAST3. */ #define ATON_DECUN_BFMT_CV2CW5LAST3 (0x3401UL) /** BFORMAT values: CV2CW6LAST3. */ #define ATON_DECUN_BFMT_CV2CW6LAST3 (0x3501UL) /** BFORMAT values: CV2CW7LAST3. */ #define ATON_DECUN_BFMT_CV2CW7LAST3 (0x3601UL) /** BFORMAT values: CV2CW8LAST3. */ #define ATON_DECUN_BFMT_CV2CW8LAST3 (0x3701UL) /** BFORMAT values: CV2CW5LAST4. */ #define ATON_DECUN_BFMT_CV2CW5LAST4 (0x4401UL) /** BFORMAT values: CV2CW6LAST4. */ #define ATON_DECUN_BFMT_CV2CW6LAST4 (0x4501UL) /** BFORMAT values: CV2CW7LAST4. */ #define ATON_DECUN_BFMT_CV2CW7LAST4 (0x4601UL) /** BFORMAT values: CV2CW8LAST4. */ #define ATON_DECUN_BFMT_CV2CW8LAST4 (0x4701UL) /** BFORMAT values: CV2CW6LAST5. */ #define ATON_DECUN_BFMT_CV2CW6LAST5 (0x5501UL) /** BFORMAT values: CV2CW7LAST5. */ #define ATON_DECUN_BFMT_CV2CW7LAST5 (0x5601UL) /** BFORMAT values: CV2CW8LAST5. */ #define ATON_DECUN_BFMT_CV2CW8LAST5 (0x5701UL) /** BFORMAT values: CV2CW7LAST6. */ #define ATON_DECUN_BFMT_CV2CW7LAST6 (0x6601UL) /** BFORMAT values: CV2CW8LAST6. */ #define ATON_DECUN_BFMT_CV2CW8LAST6 (0x6701UL) /** BFORMAT values: CV2CW8LAST7. */ #define ATON_DECUN_BFMT_CV2CW8LAST7 (0x7701UL) /** BFORMAT values: CV4CW1LAST0. */ #define ATON_DECUN_BFMT_CV4CW1LAST0 (0x3UL) /** BFORMAT values: CV4CW2LAST0. */ #define ATON_DECUN_BFMT_CV4CW2LAST0 (0x103UL) /** BFORMAT values: CV4CW3LAST0. */ #define ATON_DECUN_BFMT_CV4CW3LAST0 (0x203UL) /** BFORMAT values: CV4CW4LAST0. */ #define ATON_DECUN_BFMT_CV4CW4LAST0 (0x303UL) /** BFORMAT values: CV4CW5LAST0. */ #define ATON_DECUN_BFMT_CV4CW5LAST0 (0x403UL) /** BFORMAT values: CV4CW6LAST0. */ #define ATON_DECUN_BFMT_CV4CW6LAST0 (0x503UL) /** BFORMAT values: CV4CW7LAST0. */ #define ATON_DECUN_BFMT_CV4CW7LAST0 (0x603UL) /** BFORMAT values: CV4CW8LAST0. */ #define ATON_DECUN_BFMT_CV4CW8LAST0 (0x703UL) /** BFORMAT values: CV4CW2LAST1. */ #define ATON_DECUN_BFMT_CV4CW2LAST1 (0x1103UL) /** BFORMAT values: CV4CW3LAST1. */ #define ATON_DECUN_BFMT_CV4CW3LAST1 (0x1203UL) /** BFORMAT values: CV4CW4LAST1. */ #define ATON_DECUN_BFMT_CV4CW4LAST1 (0x1303UL) /** BFORMAT values: CV4CW5LAST1. */ #define ATON_DECUN_BFMT_CV4CW5LAST1 (0x1403UL) /** BFORMAT values: CV4CW6LAST1. */ #define ATON_DECUN_BFMT_CV4CW6LAST1 (0x1503UL) /** BFORMAT values: CV4CW7LAST1. */ #define ATON_DECUN_BFMT_CV4CW7LAST1 (0x1603UL) /** BFORMAT values: CV4CW8LAST1. */ #define ATON_DECUN_BFMT_CV4CW8LAST1 (0x1703UL) /** BFORMAT values: CV4CW3LAST2. */ #define ATON_DECUN_BFMT_CV4CW3LAST2 (0x2203UL) /** BFORMAT values: CV4CW4LAST2. */ #define ATON_DECUN_BFMT_CV4CW4LAST2 (0x2303UL) /** BFORMAT values: CV4CW5LAST2. */ #define ATON_DECUN_BFMT_CV4CW5LAST2 (0x2403UL) /** BFORMAT values: CV4CW6LAST2. */ #define ATON_DECUN_BFMT_CV4CW6LAST2 (0x2503UL) /** BFORMAT values: CV4CW7LAST2. */ #define ATON_DECUN_BFMT_CV4CW7LAST2 (0x2603UL) /** BFORMAT values: CV4CW8LAST2. */ #define ATON_DECUN_BFMT_CV4CW8LAST2 (0x2703UL) /** BFORMAT values: CV4CW4LAST3. */ #define ATON_DECUN_BFMT_CV4CW4LAST3 (0x3303UL) /** BFORMAT values: CV4CW5LAST3. */ #define ATON_DECUN_BFMT_CV4CW5LAST3 (0x3403UL) /** BFORMAT values: CV4CW6LAST3. */ #define ATON_DECUN_BFMT_CV4CW6LAST3 (0x3503UL) /** BFORMAT values: CV4CW7LAST3. */ #define ATON_DECUN_BFMT_CV4CW7LAST3 (0x3603UL) /** BFORMAT values: CV4CW8LAST3. */ #define ATON_DECUN_BFMT_CV4CW8LAST3 (0x3703UL) /** BFORMAT values: CV4CW5LAST4. */ #define ATON_DECUN_BFMT_CV4CW5LAST4 (0x4403UL) /** BFORMAT values: CV4CW6LAST4. */ #define ATON_DECUN_BFMT_CV4CW6LAST4 (0x4503UL) /** BFORMAT values: CV4CW7LAST4. */ #define ATON_DECUN_BFMT_CV4CW7LAST4 (0x4603UL) /** BFORMAT values: CV4CW8LAST4. */ #define ATON_DECUN_BFMT_CV4CW8LAST4 (0x4703UL) /** BFORMAT values: CV4CW6LAST5. */ #define ATON_DECUN_BFMT_CV4CW6LAST5 (0x5503UL) /** BFORMAT values: CV4CW7LAST5. */ #define ATON_DECUN_BFMT_CV4CW7LAST5 (0x5603UL) /** BFORMAT values: CV4CW8LAST5. */ #define ATON_DECUN_BFMT_CV4CW8LAST5 (0x5703UL) /** BFORMAT values: CV4CW7LAST6. */ #define ATON_DECUN_BFMT_CV4CW7LAST6 (0x6603UL) /** BFORMAT values: CV4CW8LAST6. */ #define ATON_DECUN_BFMT_CV4CW8LAST6 (0x6703UL) /** BFORMAT values: CV4CW8LAST7. */ #define ATON_DECUN_BFMT_CV4CW8LAST7 (0x7703UL) /** BFORMAT values: CV8CW1LAST0. */ #define ATON_DECUN_BFMT_CV8CW1LAST0 (0x7UL) /** BFORMAT values: CV8CW2LAST0. */ #define ATON_DECUN_BFMT_CV8CW2LAST0 (0x107UL) /** BFORMAT values: CV8CW3LAST0. */ #define ATON_DECUN_BFMT_CV8CW3LAST0 (0x207UL) /** BFORMAT values: CV8CW4LAST0. */ #define ATON_DECUN_BFMT_CV8CW4LAST0 (0x307UL) /** BFORMAT values: CV8CW5LAST0. */ #define ATON_DECUN_BFMT_CV8CW5LAST0 (0x407UL) /** BFORMAT values: CV8CW6LAST0. */ #define ATON_DECUN_BFMT_CV8CW6LAST0 (0x507UL) /** BFORMAT values: CV8CW7LAST0. */ #define ATON_DECUN_BFMT_CV8CW7LAST0 (0x607UL) /** BFORMAT values: CV8CW8LAST0. */ #define ATON_DECUN_BFMT_CV8CW8LAST0 (0x707UL) /** BFORMAT values: CV8CW2LAST1. */ #define ATON_DECUN_BFMT_CV8CW2LAST1 (0x1107UL) /** BFORMAT values: CV8CW3LAST1. */ #define ATON_DECUN_BFMT_CV8CW3LAST1 (0x1207UL) /** BFORMAT values: CV8CW4LAST1. */ #define ATON_DECUN_BFMT_CV8CW4LAST1 (0x1307UL) /** BFORMAT values: CV8CW5LAST1. */ #define ATON_DECUN_BFMT_CV8CW5LAST1 (0x1407UL) /** BFORMAT values: CV8CW6LAST1. */ #define ATON_DECUN_BFMT_CV8CW6LAST1 (0x1507UL) /** BFORMAT values: CV8CW7LAST1. */ #define ATON_DECUN_BFMT_CV8CW7LAST1 (0x1607UL) /** BFORMAT values: CV8CW8LAST1. */ #define ATON_DECUN_BFMT_CV8CW8LAST1 (0x1707UL) /** BFORMAT values: CV8CW3LAST2. */ #define ATON_DECUN_BFMT_CV8CW3LAST2 (0x2207UL) /** BFORMAT values: CV8CW4LAST2. */ #define ATON_DECUN_BFMT_CV8CW4LAST2 (0x2307UL) /** BFORMAT values: CV8CW5LAST2. */ #define ATON_DECUN_BFMT_CV8CW5LAST2 (0x2407UL) /** BFORMAT values: CV8CW6LAST2. */ #define ATON_DECUN_BFMT_CV8CW6LAST2 (0x2507UL) /** BFORMAT values: CV8CW7LAST2. */ #define ATON_DECUN_BFMT_CV8CW7LAST2 (0x2607UL) /** BFORMAT values: CV8CW8LAST2. */ #define ATON_DECUN_BFMT_CV8CW8LAST2 (0x2707UL) /** BFORMAT values: CV8CW4LAST3. */ #define ATON_DECUN_BFMT_CV8CW4LAST3 (0x3307UL) /** BFORMAT values: CV8CW5LAST3. */ #define ATON_DECUN_BFMT_CV8CW5LAST3 (0x3407UL) /** BFORMAT values: CV8CW6LAST3. */ #define ATON_DECUN_BFMT_CV8CW6LAST3 (0x3507UL) /** BFORMAT values: CV8CW7LAST3. */ #define ATON_DECUN_BFMT_CV8CW7LAST3 (0x3607UL) /** BFORMAT values: CV8CW8LAST3. */ #define ATON_DECUN_BFMT_CV8CW8LAST3 (0x3707UL) /** BFORMAT values: CV8CW5LAST4. */ #define ATON_DECUN_BFMT_CV8CW5LAST4 (0x4407UL) /** BFORMAT values: CV8CW6LAST4. */ #define ATON_DECUN_BFMT_CV8CW6LAST4 (0x4507UL) /** BFORMAT values: CV8CW7LAST4. */ #define ATON_DECUN_BFMT_CV8CW7LAST4 (0x4607UL) /** BFORMAT values: CV8CW8LAST4. */ #define ATON_DECUN_BFMT_CV8CW8LAST4 (0x4707UL) /** BFORMAT values: CV8CW6LAST5. */ #define ATON_DECUN_BFMT_CV8CW6LAST5 (0x5507UL) /** BFORMAT values: CV8CW7LAST5. */ #define ATON_DECUN_BFMT_CV8CW7LAST5 (0x5607UL) /** BFORMAT values: CV8CW8LAST5. */ #define ATON_DECUN_BFMT_CV8CW8LAST5 (0x5707UL) /** BFORMAT values: CV8CW7LAST6. */ #define ATON_DECUN_BFMT_CV8CW7LAST6 (0x6607UL) /** BFORMAT values: CV8CW8LAST6. */ #define ATON_DECUN_BFMT_CV8CW8LAST6 (0x6707UL) /** BFORMAT values: CV8CW8LAST7. */ #define ATON_DECUN_BFMT_CV8CW8LAST7 (0x7707UL) /** BFORMAT values: CV16CW1LAST0. */ #define ATON_DECUN_BFMT_CV16CW1LAST0 (0xfUL) /** BFORMAT values: CV16CW2LAST0. */ #define ATON_DECUN_BFMT_CV16CW2LAST0 (0x10fUL) /** BFORMAT values: CV16CW3LAST0. */ #define ATON_DECUN_BFMT_CV16CW3LAST0 (0x20fUL) /** BFORMAT values: CV16CW4LAST0. */ #define ATON_DECUN_BFMT_CV16CW4LAST0 (0x30fUL) /** BFORMAT values: CV16CW5LAST0. */ #define ATON_DECUN_BFMT_CV16CW5LAST0 (0x40fUL) /** BFORMAT values: CV16CW6LAST0. */ #define ATON_DECUN_BFMT_CV16CW6LAST0 (0x50fUL) /** BFORMAT values: CV16CW7LAST0. */ #define ATON_DECUN_BFMT_CV16CW7LAST0 (0x60fUL) /** BFORMAT values: CV16CW8LAST0. */ #define ATON_DECUN_BFMT_CV16CW8LAST0 (0x70fUL) /** BFORMAT values: CV32CW1LAST0. */ #define ATON_DECUN_BFMT_CV32CW1LAST0 (0x1fUL) /** BFORMAT values: CV32CW2LAST0. */ #define ATON_DECUN_BFMT_CV32CW2LAST0 (0x11fUL) /** BFORMAT values: CV32CW3LAST0. */ #define ATON_DECUN_BFMT_CV32CW3LAST0 (0x21fUL) /** BFORMAT values: CV32CW4LAST0. */ #define ATON_DECUN_BFMT_CV32CW4LAST0 (0x31fUL) /** BFORMAT values: CV32CW5LAST0. */ #define ATON_DECUN_BFMT_CV32CW5LAST0 (0x41fUL) /** BFORMAT values: CV32CW6LAST0. */ #define ATON_DECUN_BFMT_CV32CW6LAST0 (0x51fUL) /** BFORMAT values: CV32CW7LAST0. */ #define ATON_DECUN_BFMT_CV32CW7LAST0 (0x61fUL) /** BFORMAT values: CV32CW8LAST0. */ #define ATON_DECUN_BFMT_CV32CW8LAST0 (0x71fUL) /** BFORMAT values: CV64CW1LAST0. */ #define ATON_DECUN_BFMT_CV64CW1LAST0 (0x3fUL) /** BFORMAT values: CV64CW2LAST0. */ #define ATON_DECUN_BFMT_CV64CW2LAST0 (0x13fUL) /** BFORMAT values: CV64CW3LAST0. */ #define ATON_DECUN_BFMT_CV64CW3LAST0 (0x23fUL) /** BFORMAT values: CV64CW4LAST0. */ #define ATON_DECUN_BFMT_CV64CW4LAST0 (0x33fUL) /** BFORMAT values: CV64CW5LAST0. */ #define ATON_DECUN_BFMT_CV64CW5LAST0 (0x43fUL) /** BFORMAT values: CV64CW6LAST0. */ #define ATON_DECUN_BFMT_CV64CW6LAST0 (0x53fUL) /** BFORMAT values: CV64CW7LAST0. */ #define ATON_DECUN_BFMT_CV64CW7LAST0 (0x63fUL) /** BFORMAT values: CV64CW8LAST0. */ #define ATON_DECUN_BFMT_CV64CW8LAST0 (0x73fUL) /** BFORMAT values: CV128CW1LAST0. */ #define ATON_DECUN_BFMT_CV128CW1LAST0 (0x7fUL) /** BFORMAT values: CV128CW2LAST0. */ #define ATON_DECUN_BFMT_CV128CW2LAST0 (0x17fUL) /** BFORMAT values: CV128CW3LAST0. */ #define ATON_DECUN_BFMT_CV128CW3LAST0 (0x27fUL) /** BFORMAT values: CV128CW4LAST0. */ #define ATON_DECUN_BFMT_CV128CW4LAST0 (0x37fUL) /** BFORMAT values: CV128CW5LAST0. */ #define ATON_DECUN_BFMT_CV128CW5LAST0 (0x47fUL) /** BFORMAT values: CV128CW6LAST0. */ #define ATON_DECUN_BFMT_CV128CW6LAST0 (0x57fUL) /** BFORMAT values: CV128CW7LAST0. */ #define ATON_DECUN_BFMT_CV128CW7LAST0 (0x67fUL) /** BFORMAT values: CV128CW8LAST0. */ #define ATON_DECUN_BFMT_CV128CW8LAST0 (0x77fUL) /** BFORMAT values: CV256CW1LAST0. */ #define ATON_DECUN_BFMT_CV256CW1LAST0 (0xffUL) /** BFORMAT values: CV256CW2LAST0. */ #define ATON_DECUN_BFMT_CV256CW2LAST0 (0x1ffUL) /** BFORMAT values: CV256CW3LAST0. */ #define ATON_DECUN_BFMT_CV256CW3LAST0 (0x2ffUL) /** BFORMAT values: CV256CW4LAST0. */ #define ATON_DECUN_BFMT_CV256CW4LAST0 (0x3ffUL) /** BFORMAT values: CV256CW5LAST0. */ #define ATON_DECUN_BFMT_CV256CW5LAST0 (0x4ffUL) /** BFORMAT values: CV256CW6LAST0. */ #define ATON_DECUN_BFMT_CV256CW6LAST0 (0x5ffUL) /** BFORMAT values: CV256CW7LAST0. */ #define ATON_DECUN_BFMT_CV256CW7LAST0 (0x6ffUL) /** BFORMAT values: CV256CW8LAST0. */ #define ATON_DECUN_BFMT_CV256CW8LAST0 (0x7ffUL) /** BFORMAT values: CV16CW2LAST1. */ #define ATON_DECUN_BFMT_CV16CW2LAST1 (0x110fUL) /** BFORMAT values: CV16CW3LAST1. */ #define ATON_DECUN_BFMT_CV16CW3LAST1 (0x120fUL) /** BFORMAT values: CV16CW3LAST2. */ #define ATON_DECUN_BFMT_CV16CW3LAST2 (0x220fUL) /** BFORMAT values: CV16CW4LAST1. */ #define ATON_DECUN_BFMT_CV16CW4LAST1 (0x130fUL) /** BFORMAT values: CV16CW4LAST2. */ #define ATON_DECUN_BFMT_CV16CW4LAST2 (0x230fUL) /** BFORMAT values: CV16CW4LAST3. */ #define ATON_DECUN_BFMT_CV16CW4LAST3 (0x330fUL) /** BFORMAT values: CV16CW5LAST1. */ #define ATON_DECUN_BFMT_CV16CW5LAST1 (0x140fUL) /** BFORMAT values: CV16CW5LAST2. */ #define ATON_DECUN_BFMT_CV16CW5LAST2 (0x240fUL) /** BFORMAT values: CV16CW5LAST3. */ #define ATON_DECUN_BFMT_CV16CW5LAST3 (0x340fUL) /** BFORMAT values: CV16CW5LAST4. */ #define ATON_DECUN_BFMT_CV16CW5LAST4 (0x440fUL) /** BFORMAT values: CV16CW6LAST1. */ #define ATON_DECUN_BFMT_CV16CW6LAST1 (0x150fUL) /** BFORMAT values: CV16CW6LAST2. */ #define ATON_DECUN_BFMT_CV16CW6LAST2 (0x250fUL) /** BFORMAT values: CV16CW6LAST3. */ #define ATON_DECUN_BFMT_CV16CW6LAST3 (0x350fUL) /** BFORMAT values: CV16CW6LAST4. */ #define ATON_DECUN_BFMT_CV16CW6LAST4 (0x450fUL) /** BFORMAT values: CV16CW6LAST5. */ #define ATON_DECUN_BFMT_CV16CW6LAST5 (0x550fUL) /** BFORMAT values: CV16CW7LAST1. */ #define ATON_DECUN_BFMT_CV16CW7LAST1 (0x160fUL) /** BFORMAT values: CV16CW7LAST2. */ #define ATON_DECUN_BFMT_CV16CW7LAST2 (0x260fUL) /** BFORMAT values: CV16CW7LAST3. */ #define ATON_DECUN_BFMT_CV16CW7LAST3 (0x360fUL) /** BFORMAT values: CV16CW7LAST4. */ #define ATON_DECUN_BFMT_CV16CW7LAST4 (0x460fUL) /** BFORMAT values: CV16CW7LAST5. */ #define ATON_DECUN_BFMT_CV16CW7LAST5 (0x560fUL) /** BFORMAT values: CV16CW7LAST6. */ #define ATON_DECUN_BFMT_CV16CW7LAST6 (0x660fUL) /** BFORMAT values: CV16CW8LAST1. */ #define ATON_DECUN_BFMT_CV16CW8LAST1 (0x170fUL) /** BFORMAT values: CV16CW8LAST2. */ #define ATON_DECUN_BFMT_CV16CW8LAST2 (0x270fUL) /** BFORMAT values: CV16CW8LAST3. */ #define ATON_DECUN_BFMT_CV16CW8LAST3 (0x370fUL) /** BFORMAT values: CV16CW8LAST4. */ #define ATON_DECUN_BFMT_CV16CW8LAST4 (0x470fUL) /** BFORMAT values: CV16CW8LAST5. */ #define ATON_DECUN_BFMT_CV16CW8LAST5 (0x570fUL) /** BFORMAT values: CV16CW8LAST6. */ #define ATON_DECUN_BFMT_CV16CW8LAST6 (0x670fUL) /** BFORMAT values: CV16CW8LAST7. */ #define ATON_DECUN_BFMT_CV16CW8LAST7 (0x770fUL) /** BFORMAT values: CV32CW2LAST1. */ #define ATON_DECUN_BFMT_CV32CW2LAST1 (0x111fUL) /** BFORMAT values: CV32CW3LAST1. */ #define ATON_DECUN_BFMT_CV32CW3LAST1 (0x121fUL) /** BFORMAT values: CV32CW3LAST2. */ #define ATON_DECUN_BFMT_CV32CW3LAST2 (0x221fUL) /** BFORMAT values: CV32CW4LAST1. */ #define ATON_DECUN_BFMT_CV32CW4LAST1 (0x131fUL) /** BFORMAT values: CV32CW4LAST2. */ #define ATON_DECUN_BFMT_CV32CW4LAST2 (0x231fUL) /** BFORMAT values: CV32CW4LAST3. */ #define ATON_DECUN_BFMT_CV32CW4LAST3 (0x331fUL) /** BFORMAT values: CV32CW5LAST1. */ #define ATON_DECUN_BFMT_CV32CW5LAST1 (0x141fUL) /** BFORMAT values: CV32CW5LAST2. */ #define ATON_DECUN_BFMT_CV32CW5LAST2 (0x241fUL) /** BFORMAT values: CV32CW5LAST3. */ #define ATON_DECUN_BFMT_CV32CW5LAST3 (0x341fUL) /** BFORMAT values: CV32CW5LAST4. */ #define ATON_DECUN_BFMT_CV32CW5LAST4 (0x441fUL) /** BFORMAT values: CV32CW6LAST1. */ #define ATON_DECUN_BFMT_CV32CW6LAST1 (0x151fUL) /** BFORMAT values: CV32CW6LAST2. */ #define ATON_DECUN_BFMT_CV32CW6LAST2 (0x251fUL) /** BFORMAT values: CV32CW6LAST3. */ #define ATON_DECUN_BFMT_CV32CW6LAST3 (0x351fUL) /** BFORMAT values: CV32CW6LAST4. */ #define ATON_DECUN_BFMT_CV32CW6LAST4 (0x451fUL) /** BFORMAT values: CV32CW6LAST5. */ #define ATON_DECUN_BFMT_CV32CW6LAST5 (0x551fUL) /** BFORMAT values: CV32CW7LAST1. */ #define ATON_DECUN_BFMT_CV32CW7LAST1 (0x161fUL) /** BFORMAT values: CV32CW7LAST2. */ #define ATON_DECUN_BFMT_CV32CW7LAST2 (0x261fUL) /** BFORMAT values: CV32CW7LAST3. */ #define ATON_DECUN_BFMT_CV32CW7LAST3 (0x361fUL) /** BFORMAT values: CV32CW7LAST4. */ #define ATON_DECUN_BFMT_CV32CW7LAST4 (0x461fUL) /** BFORMAT values: CV32CW7LAST5. */ #define ATON_DECUN_BFMT_CV32CW7LAST5 (0x561fUL) /** BFORMAT values: CV32CW7LAST6. */ #define ATON_DECUN_BFMT_CV32CW7LAST6 (0x661fUL) /** BFORMAT values: CV32CW8LAST1. */ #define ATON_DECUN_BFMT_CV32CW8LAST1 (0x171fUL) /** BFORMAT values: CV32CW8LAST2. */ #define ATON_DECUN_BFMT_CV32CW8LAST2 (0x271fUL) /** BFORMAT values: CV32CW8LAST3. */ #define ATON_DECUN_BFMT_CV32CW8LAST3 (0x371fUL) /** BFORMAT values: CV32CW8LAST4. */ #define ATON_DECUN_BFMT_CV32CW8LAST4 (0x471fUL) /** BFORMAT values: CV32CW8LAST5. */ #define ATON_DECUN_BFMT_CV32CW8LAST5 (0x571fUL) /** BFORMAT values: CV32CW8LAST6. */ #define ATON_DECUN_BFMT_CV32CW8LAST6 (0x671fUL) /** BFORMAT values: CV32CW8LAST7. */ #define ATON_DECUN_BFMT_CV32CW8LAST7 (0x771fUL) /** BFORMAT values: CV64CW2LAST1. */ #define ATON_DECUN_BFMT_CV64CW2LAST1 (0x113fUL) /** BFORMAT values: CV64CW3LAST1. */ #define ATON_DECUN_BFMT_CV64CW3LAST1 (0x123fUL) /** BFORMAT values: CV64CW3LAST2. */ #define ATON_DECUN_BFMT_CV64CW3LAST2 (0x223fUL) /** BFORMAT values: CV64CW4LAST1. */ #define ATON_DECUN_BFMT_CV64CW4LAST1 (0x133fUL) /** BFORMAT values: CV64CW4LAST2. */ #define ATON_DECUN_BFMT_CV64CW4LAST2 (0x233fUL) /** BFORMAT values: CV64CW4LAST3. */ #define ATON_DECUN_BFMT_CV64CW4LAST3 (0x333fUL) /** BFORMAT values: CV64CW5LAST1. */ #define ATON_DECUN_BFMT_CV64CW5LAST1 (0x143fUL) /** BFORMAT values: CV64CW5LAST2. */ #define ATON_DECUN_BFMT_CV64CW5LAST2 (0x243fUL) /** BFORMAT values: CV64CW5LAST3. */ #define ATON_DECUN_BFMT_CV64CW5LAST3 (0x343fUL) /** BFORMAT values: CV64CW5LAST4. */ #define ATON_DECUN_BFMT_CV64CW5LAST4 (0x443fUL) /** BFORMAT values: CV64CW6LAST1. */ #define ATON_DECUN_BFMT_CV64CW6LAST1 (0x153fUL) /** BFORMAT values: CV64CW6LAST2. */ #define ATON_DECUN_BFMT_CV64CW6LAST2 (0x253fUL) /** BFORMAT values: CV64CW6LAST3. */ #define ATON_DECUN_BFMT_CV64CW6LAST3 (0x353fUL) /** BFORMAT values: CV64CW6LAST4. */ #define ATON_DECUN_BFMT_CV64CW6LAST4 (0x453fUL) /** BFORMAT values: CV64CW6LAST5. */ #define ATON_DECUN_BFMT_CV64CW6LAST5 (0x553fUL) /** BFORMAT values: CV64CW7LAST1. */ #define ATON_DECUN_BFMT_CV64CW7LAST1 (0x163fUL) /** BFORMAT values: CV64CW7LAST2. */ #define ATON_DECUN_BFMT_CV64CW7LAST2 (0x263fUL) /** BFORMAT values: CV64CW7LAST3. */ #define ATON_DECUN_BFMT_CV64CW7LAST3 (0x363fUL) /** BFORMAT values: CV64CW7LAST4. */ #define ATON_DECUN_BFMT_CV64CW7LAST4 (0x463fUL) /** BFORMAT values: CV64CW7LAST5. */ #define ATON_DECUN_BFMT_CV64CW7LAST5 (0x563fUL) /** BFORMAT values: CV64CW7LAST6. */ #define ATON_DECUN_BFMT_CV64CW7LAST6 (0x663fUL) /** BFORMAT values: CV64CW8LAST1. */ #define ATON_DECUN_BFMT_CV64CW8LAST1 (0x173fUL) /** BFORMAT values: CV64CW8LAST2. */ #define ATON_DECUN_BFMT_CV64CW8LAST2 (0x273fUL) /** BFORMAT values: CV64CW8LAST3. */ #define ATON_DECUN_BFMT_CV64CW8LAST3 (0x373fUL) /** BFORMAT values: CV64CW8LAST4. */ #define ATON_DECUN_BFMT_CV64CW8LAST4 (0x473fUL) /** BFORMAT values: CV64CW8LAST5. */ #define ATON_DECUN_BFMT_CV64CW8LAST5 (0x573fUL) /** BFORMAT values: CV64CW8LAST6. */ #define ATON_DECUN_BFMT_CV64CW8LAST6 (0x673fUL) /** BFORMAT values: CV64CW8LAST7. */ #define ATON_DECUN_BFMT_CV64CW8LAST7 (0x773fUL) /** BFORMAT values: CV128CW2LAST1. */ #define ATON_DECUN_BFMT_CV128CW2LAST1 (0x117fUL) /** BFORMAT values: CV128CW3LAST1. */ #define ATON_DECUN_BFMT_CV128CW3LAST1 (0x127fUL) /** BFORMAT values: CV128CW3LAST2. */ #define ATON_DECUN_BFMT_CV128CW3LAST2 (0x227fUL) /** BFORMAT values: CV128CW4LAST1. */ #define ATON_DECUN_BFMT_CV128CW4LAST1 (0x137fUL) /** BFORMAT values: CV128CW4LAST2. */ #define ATON_DECUN_BFMT_CV128CW4LAST2 (0x237fUL) /** BFORMAT values: CV128CW4LAST3. */ #define ATON_DECUN_BFMT_CV128CW4LAST3 (0x337fUL) /** BFORMAT values: CV128CW5LAST1. */ #define ATON_DECUN_BFMT_CV128CW5LAST1 (0x147fUL) /** BFORMAT values: CV128CW5LAST2. */ #define ATON_DECUN_BFMT_CV128CW5LAST2 (0x247fUL) /** BFORMAT values: CV128CW5LAST3. */ #define ATON_DECUN_BFMT_CV128CW5LAST3 (0x347fUL) /** BFORMAT values: CV128CW5LAST4. */ #define ATON_DECUN_BFMT_CV128CW5LAST4 (0x447fUL) /** BFORMAT values: CV128CW6LAST1. */ #define ATON_DECUN_BFMT_CV128CW6LAST1 (0x157fUL) /** BFORMAT values: CV128CW6LAST2. */ #define ATON_DECUN_BFMT_CV128CW6LAST2 (0x257fUL) /** BFORMAT values: CV128CW6LAST3. */ #define ATON_DECUN_BFMT_CV128CW6LAST3 (0x357fUL) /** BFORMAT values: CV128CW6LAST4. */ #define ATON_DECUN_BFMT_CV128CW6LAST4 (0x457fUL) /** BFORMAT values: CV128CW6LAST5. */ #define ATON_DECUN_BFMT_CV128CW6LAST5 (0x557fUL) /** BFORMAT values: CV128CW7LAST1. */ #define ATON_DECUN_BFMT_CV128CW7LAST1 (0x167fUL) /** BFORMAT values: CV128CW7LAST2. */ #define ATON_DECUN_BFMT_CV128CW7LAST2 (0x267fUL) /** BFORMAT values: CV128CW7LAST3. */ #define ATON_DECUN_BFMT_CV128CW7LAST3 (0x367fUL) /** BFORMAT values: CV128CW7LAST4. */ #define ATON_DECUN_BFMT_CV128CW7LAST4 (0x467fUL) /** BFORMAT values: CV128CW7LAST5. */ #define ATON_DECUN_BFMT_CV128CW7LAST5 (0x567fUL) /** BFORMAT values: CV128CW7LAST6. */ #define ATON_DECUN_BFMT_CV128CW7LAST6 (0x667fUL) /** BFORMAT values: CV128CW8LAST1. */ #define ATON_DECUN_BFMT_CV128CW8LAST1 (0x177fUL) /** BFORMAT values: CV128CW8LAST2. */ #define ATON_DECUN_BFMT_CV128CW8LAST2 (0x277fUL) /** BFORMAT values: CV128CW8LAST3. */ #define ATON_DECUN_BFMT_CV128CW8LAST3 (0x377fUL) /** BFORMAT values: CV128CW8LAST4. */ #define ATON_DECUN_BFMT_CV128CW8LAST4 (0x477fUL) /** BFORMAT values: CV128CW8LAST5. */ #define ATON_DECUN_BFMT_CV128CW8LAST5 (0x577fUL) /** BFORMAT values: CV128CW8LAST6. */ #define ATON_DECUN_BFMT_CV128CW8LAST6 (0x677fUL) /** BFORMAT values: CV128CW8LAST7. */ #define ATON_DECUN_BFMT_CV128CW8LAST7 (0x777fUL) /** BFORMAT values: CV256CW2LAST1. */ #define ATON_DECUN_BFMT_CV256CW2LAST1 (0x11ffUL) /** BFORMAT values: CV256CW3LAST1. */ #define ATON_DECUN_BFMT_CV256CW3LAST1 (0x12ffUL) /** BFORMAT values: CV256CW3LAST2. */ #define ATON_DECUN_BFMT_CV256CW3LAST2 (0x22ffUL) /** BFORMAT values: CV256CW4LAST1. */ #define ATON_DECUN_BFMT_CV256CW4LAST1 (0x13ffUL) /** BFORMAT values: CV256CW4LAST2. */ #define ATON_DECUN_BFMT_CV256CW4LAST2 (0x23ffUL) /** BFORMAT values: CV256CW4LAST3. */ #define ATON_DECUN_BFMT_CV256CW4LAST3 (0x33ffUL) /** BFORMAT values: CV256CW5LAST1. */ #define ATON_DECUN_BFMT_CV256CW5LAST1 (0x14ffUL) /** BFORMAT values: CV256CW5LAST2. */ #define ATON_DECUN_BFMT_CV256CW5LAST2 (0x24ffUL) /** BFORMAT values: CV256CW5LAST3. */ #define ATON_DECUN_BFMT_CV256CW5LAST3 (0x34ffUL) /** BFORMAT values: CV256CW5LAST4. */ #define ATON_DECUN_BFMT_CV256CW5LAST4 (0x44ffUL) /** BFORMAT values: CV256CW6LAST1. */ #define ATON_DECUN_BFMT_CV256CW6LAST1 (0x15ffUL) /** BFORMAT values: CV256CW6LAST2. */ #define ATON_DECUN_BFMT_CV256CW6LAST2 (0x25ffUL) /** BFORMAT values: CV256CW6LAST3. */ #define ATON_DECUN_BFMT_CV256CW6LAST3 (0x35ffUL) /** BFORMAT values: CV256CW6LAST4. */ #define ATON_DECUN_BFMT_CV256CW6LAST4 (0x45ffUL) /** BFORMAT values: CV256CW6LAST5. */ #define ATON_DECUN_BFMT_CV256CW6LAST5 (0x55ffUL) /** BFORMAT values: CV256CW7LAST1. */ #define ATON_DECUN_BFMT_CV256CW7LAST1 (0x16ffUL) /** BFORMAT values: CV256CW7LAST2. */ #define ATON_DECUN_BFMT_CV256CW7LAST2 (0x26ffUL) /** BFORMAT values: CV256CW7LAST3. */ #define ATON_DECUN_BFMT_CV256CW7LAST3 (0x36ffUL) /** BFORMAT values: CV256CW7LAST4. */ #define ATON_DECUN_BFMT_CV256CW7LAST4 (0x46ffUL) /** BFORMAT values: CV256CW7LAST5. */ #define ATON_DECUN_BFMT_CV256CW7LAST5 (0x56ffUL) /** BFORMAT values: CV256CW7LAST6. */ #define ATON_DECUN_BFMT_CV256CW7LAST6 (0x66ffUL) /** BFORMAT values: CV256CW8LAST1. */ #define ATON_DECUN_BFMT_CV256CW8LAST1 (0x17ffUL) /** BFORMAT values: CV256CW8LAST2. */ #define ATON_DECUN_BFMT_CV256CW8LAST2 (0x27ffUL) /** BFORMAT values: CV256CW8LAST3. */ #define ATON_DECUN_BFMT_CV256CW8LAST3 (0x37ffUL) /** BFORMAT values: CV256CW8LAST4. */ #define ATON_DECUN_BFMT_CV256CW8LAST4 (0x47ffUL) /** BFORMAT values: CV256CW8LAST5. */ #define ATON_DECUN_BFMT_CV256CW8LAST5 (0x57ffUL) /** BFORMAT values: CV256CW8LAST6. */ #define ATON_DECUN_BFMT_CV256CW8LAST6 (0x67ffUL) /** BFORMAT values: CV256CW8LAST7. */ #define ATON_DECUN_BFMT_CV256CW8LAST7 (0x77ffUL) /** Get the name of one of the values of the DECUN_BFMT set of enumerated values. */ #define ATON_DECUN_BFMT_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "CV1CW1LAST0" : \ (((VALUE) == 256UL) ? "CV1CW2LAST0" : \ (((VALUE) == 512UL) ? "CV1CW3LAST0" : \ (((VALUE) == 768UL) ? "CV1CW4LAST0" : \ (((VALUE) == 1024UL) ? "CV1CW5LAST0" : \ (((VALUE) == 1280UL) ? "CV1CW6LAST0" : \ (((VALUE) == 1536UL) ? "CV1CW7LAST0" : \ (((VALUE) == 1792UL) ? "CV1CW8LAST0" : \ (((VALUE) == 4352UL) ? "CV1CW2LAST1" : \ (((VALUE) == 4608UL) ? "CV1CW3LAST1" : \ (((VALUE) == 4864UL) ? "CV1CW4LAST1" : \ (((VALUE) == 5120UL) ? "CV1CW5LAST1" : \ (((VALUE) == 5376UL) ? "CV1CW6LAST1" : \ (((VALUE) == 5632UL) ? "CV1CW7LAST1" : \ (((VALUE) == 5888UL) ? "CV1CW8LAST1" : \ (((VALUE) == 8704UL) ? "CV1CW3LAST2" : \ (((VALUE) == 8960UL) ? "CV1CW4LAST2" : \ (((VALUE) == 9216UL) ? "CV1CW5LAST2" : \ (((VALUE) == 9472UL) ? "CV1CW6LAST2" : \ (((VALUE) == 9728UL) ? "CV1CW7LAST2" : \ (((VALUE) == 9984UL) ? "CV1CW8LAST2" : \ (((VALUE) == 13056UL) ? "CV1CW4LAST3" : \ (((VALUE) == 13312UL) ? "CV1CW5LAST3" : \ (((VALUE) == 13568UL) ? "CV1CW6LAST3" : \ (((VALUE) == 13824UL) ? "CV1CW7LAST3" : \ (((VALUE) == 14080UL) ? "CV1CW8LAST3" : \ (((VALUE) == 17408UL) ? "CV1CW5LAST4" : \ (((VALUE) == 17664UL) ? "CV1CW6LAST4" : \ (((VALUE) == 17920UL) ? "CV1CW7LAST4" : \ (((VALUE) == 18176UL) ? "CV1CW8LAST4" : \ (((VALUE) == 21760UL) ? "CV1CW6LAST5" : \ (((VALUE) == 22016UL) ? "CV1CW7LAST5" : \ (((VALUE) == 22272UL) ? "CV1CW8LAST5" : \ (((VALUE) == 26112UL) ? "CV1CW7LAST6" : \ (((VALUE) == 26368UL) ? "CV1CW8LAST6" : \ (((VALUE) == 30464UL) ? "CV1CW8LAST7" : \ (((VALUE) == 1UL) ? "CV2CW1LAST0" : \ (((VALUE) == 257UL) ? "CV2CW2LAST0" : \ (((VALUE) == 513UL) ? "CV2CW3LAST0" : \ (((VALUE) == 769UL) ? "CV2CW4LAST0" : \ (((VALUE) == 1025UL) ? "CV2CW5LAST0" : \ (((VALUE) == 1281UL) ? "CV2CW6LAST0" : \ (((VALUE) == 1537UL) ? "CV2CW7LAST0" : \ (((VALUE) == 1793UL) ? "CV2CW8LAST0" : \ (((VALUE) == 4353UL) ? "CV2CW2LAST1" : \ (((VALUE) == 4609UL) ? "CV2CW3LAST1" : \ (((VALUE) == 4865UL) ? "CV2CW4LAST1" : \ (((VALUE) == 5121UL) ? "CV2CW5LAST1" : \ (((VALUE) == 5377UL) ? "CV2CW6LAST1" : \ (((VALUE) == 5633UL) ? "CV2CW7LAST1" : \ (((VALUE) == 5889UL) ? "CV2CW8LAST1" : \ (((VALUE) == 8705UL) ? "CV2CW3LAST2" : \ (((VALUE) == 8961UL) ? "CV2CW4LAST2" : \ (((VALUE) == 9217UL) ? "CV2CW5LAST2" : \ (((VALUE) == 9473UL) ? "CV2CW6LAST2" : \ (((VALUE) == 9729UL) ? "CV2CW7LAST2" : \ (((VALUE) == 9985UL) ? "CV2CW8LAST2" : \ (((VALUE) == 13057UL) ? "CV2CW4LAST3" : \ (((VALUE) == 13313UL) ? "CV2CW5LAST3" : \ (((VALUE) == 13569UL) ? "CV2CW6LAST3" : \ (((VALUE) == 13825UL) ? "CV2CW7LAST3" : \ (((VALUE) == 14081UL) ? "CV2CW8LAST3" : \ (((VALUE) == 17409UL) ? "CV2CW5LAST4" : \ (((VALUE) == 17665UL) ? "CV2CW6LAST4" : \ (((VALUE) == 17921UL) ? "CV2CW7LAST4" : \ (((VALUE) == 18177UL) ? "CV2CW8LAST4" : \ (((VALUE) == 21761UL) ? "CV2CW6LAST5" : \ (((VALUE) == 22017UL) ? "CV2CW7LAST5" : \ (((VALUE) == 22273UL) ? "CV2CW8LAST5" : \ (((VALUE) == 26113UL) ? "CV2CW7LAST6" : \ (((VALUE) == 26369UL) ? "CV2CW8LAST6" : \ (((VALUE) == 30465UL) ? "CV2CW8LAST7" : \ (((VALUE) == 3UL) ? "CV4CW1LAST0" : \ (((VALUE) == 259UL) ? "CV4CW2LAST0" : \ (((VALUE) == 515UL) ? "CV4CW3LAST0" : \ (((VALUE) == 771UL) ? "CV4CW4LAST0" : \ (((VALUE) == 1027UL) ? "CV4CW5LAST0" : \ (((VALUE) == 1283UL) ? "CV4CW6LAST0" : \ (((VALUE) == 1539UL) ? "CV4CW7LAST0" : \ (((VALUE) == 1795UL) ? "CV4CW8LAST0" : \ (((VALUE) == 4355UL) ? "CV4CW2LAST1" : \ (((VALUE) == 4611UL) ? "CV4CW3LAST1" : \ (((VALUE) == 4867UL) ? "CV4CW4LAST1" : \ (((VALUE) == 5123UL) ? "CV4CW5LAST1" : \ (((VALUE) == 5379UL) ? "CV4CW6LAST1" : \ (((VALUE) == 5635UL) ? "CV4CW7LAST1" : \ (((VALUE) == 5891UL) ? "CV4CW8LAST1" : \ (((VALUE) == 8707UL) ? "CV4CW3LAST2" : \ (((VALUE) == 8963UL) ? "CV4CW4LAST2" : \ (((VALUE) == 9219UL) ? "CV4CW5LAST2" : \ (((VALUE) == 9475UL) ? "CV4CW6LAST2" : \ (((VALUE) == 9731UL) ? "CV4CW7LAST2" : \ (((VALUE) == 9987UL) ? "CV4CW8LAST2" : \ (((VALUE) == 13059UL) ? "CV4CW4LAST3" : \ (((VALUE) == 13315UL) ? "CV4CW5LAST3" : \ (((VALUE) == 13571UL) ? "CV4CW6LAST3" : \ (((VALUE) == 13827UL) ? "CV4CW7LAST3" : \ (((VALUE) == 14083UL) ? "CV4CW8LAST3" : \ (((VALUE) == 17411UL) ? "CV4CW5LAST4" : \ (((VALUE) == 17667UL) ? "CV4CW6LAST4" : \ (((VALUE) == 17923UL) ? "CV4CW7LAST4" : \ (((VALUE) == 18179UL) ? "CV4CW8LAST4" : \ (((VALUE) == 21763UL) ? "CV4CW6LAST5" : \ (((VALUE) == 22019UL) ? "CV4CW7LAST5" : \ (((VALUE) == 22275UL) ? "CV4CW8LAST5" : \ (((VALUE) == 26115UL) ? "CV4CW7LAST6" : \ (((VALUE) == 26371UL) ? "CV4CW8LAST6" : \ (((VALUE) == 30467UL) ? "CV4CW8LAST7" : \ (((VALUE) == 7UL) ? "CV8CW1LAST0" : \ (((VALUE) == 263UL) ? "CV8CW2LAST0" : \ (((VALUE) == 519UL) ? "CV8CW3LAST0" : \ (((VALUE) == 775UL) ? "CV8CW4LAST0" : \ (((VALUE) == 1031UL) ? "CV8CW5LAST0" : \ (((VALUE) == 1287UL) ? "CV8CW6LAST0" : \ (((VALUE) == 1543UL) ? "CV8CW7LAST0" : \ (((VALUE) == 1799UL) ? "CV8CW8LAST0" : \ (((VALUE) == 4359UL) ? "CV8CW2LAST1" : \ (((VALUE) == 4615UL) ? "CV8CW3LAST1" : \ (((VALUE) == 4871UL) ? "CV8CW4LAST1" : \ (((VALUE) == 5127UL) ? "CV8CW5LAST1" : \ (((VALUE) == 5383UL) ? "CV8CW6LAST1" : \ (((VALUE) == 5639UL) ? "CV8CW7LAST1" : \ (((VALUE) == 5895UL) ? "CV8CW8LAST1" : \ (((VALUE) == 8711UL) ? "CV8CW3LAST2" : \ (((VALUE) == 8967UL) ? "CV8CW4LAST2" : \ (((VALUE) == 9223UL) ? "CV8CW5LAST2" : \ (((VALUE) == 9479UL) ? "CV8CW6LAST2" : \ (((VALUE) == 9735UL) ? "CV8CW7LAST2" : \ (((VALUE) == 9991UL) ? "CV8CW8LAST2" : \ (((VALUE) == 13063UL) ? "CV8CW4LAST3" : \ (((VALUE) == 13319UL) ? "CV8CW5LAST3" : \ (((VALUE) == 13575UL) ? "CV8CW6LAST3" : \ (((VALUE) == 13831UL) ? "CV8CW7LAST3" : \ (((VALUE) == 14087UL) ? "CV8CW8LAST3" : \ (((VALUE) == 17415UL) ? "CV8CW5LAST4" : \ (((VALUE) == 17671UL) ? "CV8CW6LAST4" : \ (((VALUE) == 17927UL) ? "CV8CW7LAST4" : \ (((VALUE) == 18183UL) ? "CV8CW8LAST4" : \ (((VALUE) == 21767UL) ? "CV8CW6LAST5" : \ (((VALUE) == 22023UL) ? "CV8CW7LAST5" : \ (((VALUE) == 22279UL) ? "CV8CW8LAST5" : \ (((VALUE) == 26119UL) ? "CV8CW7LAST6" : \ (((VALUE) == 26375UL) ? "CV8CW8LAST6" : \ (((VALUE) == 30471UL) ? "CV8CW8LAST7" : \ (((VALUE) == 15UL) ? "CV16CW1LAST0" : \ (((VALUE) == 271UL) ? "CV16CW2LAST0" : \ (((VALUE) == 527UL) ? "CV16CW3LAST0" : \ (((VALUE) == 783UL) ? "CV16CW4LAST0" : \ (((VALUE) == 1039UL) ? "CV16CW5LAST0" : \ (((VALUE) == 1295UL) ? "CV16CW6LAST0" : \ (((VALUE) == 1551UL) ? "CV16CW7LAST0" : \ (((VALUE) == 1807UL) ? "CV16CW8LAST0" : \ (((VALUE) == 31UL) ? "CV32CW1LAST0" : \ (((VALUE) == 287UL) ? "CV32CW2LAST0" : \ (((VALUE) == 543UL) ? "CV32CW3LAST0" : \ (((VALUE) == 799UL) ? "CV32CW4LAST0" : \ (((VALUE) == 1055UL) ? "CV32CW5LAST0" : \ (((VALUE) == 1311UL) ? "CV32CW6LAST0" : \ (((VALUE) == 1567UL) ? "CV32CW7LAST0" : \ (((VALUE) == 1823UL) ? "CV32CW8LAST0" : \ (((VALUE) == 63UL) ? "CV64CW1LAST0" : \ (((VALUE) == 319UL) ? "CV64CW2LAST0" : \ (((VALUE) == 575UL) ? "CV64CW3LAST0" : \ (((VALUE) == 831UL) ? "CV64CW4LAST0" : \ (((VALUE) == 1087UL) ? "CV64CW5LAST0" : \ (((VALUE) == 1343UL) ? "CV64CW6LAST0" : \ (((VALUE) == 1599UL) ? "CV64CW7LAST0" : \ (((VALUE) == 1855UL) ? "CV64CW8LAST0" : \ (((VALUE) == 127UL) ? "CV128CW1LAST0" : \ (((VALUE) == 383UL) ? "CV128CW2LAST0" : \ (((VALUE) == 639UL) ? "CV128CW3LAST0" : \ (((VALUE) == 895UL) ? "CV128CW4LAST0" : \ (((VALUE) == 1151UL) ? "CV128CW5LAST0" : \ (((VALUE) == 1407UL) ? "CV128CW6LAST0" : \ (((VALUE) == 1663UL) ? "CV128CW7LAST0" : \ (((VALUE) == 1919UL) ? "CV128CW8LAST0" : \ (((VALUE) == 255UL) ? "CV256CW1LAST0" : \ (((VALUE) == 511UL) ? "CV256CW2LAST0" : \ (((VALUE) == 767UL) ? "CV256CW3LAST0" : \ (((VALUE) == 1023UL) ? "CV256CW4LAST0" : \ (((VALUE) == 1279UL) ? "CV256CW5LAST0" : \ (((VALUE) == 1535UL) ? "CV256CW6LAST0" : \ (((VALUE) == 1791UL) ? "CV256CW7LAST0" : \ (((VALUE) == 2047UL) ? "CV256CW8LAST0" : \ (((VALUE) == 4367UL) ? "CV16CW2LAST1" : \ (((VALUE) == 4623UL) ? "CV16CW3LAST1" : \ (((VALUE) == 8719UL) ? "CV16CW3LAST2" : \ (((VALUE) == 4879UL) ? "CV16CW4LAST1" : \ (((VALUE) == 8975UL) ? "CV16CW4LAST2" : \ (((VALUE) == 13071UL) ? "CV16CW4LAST3" : \ (((VALUE) == 5135UL) ? "CV16CW5LAST1" : \ (((VALUE) == 9231UL) ? "CV16CW5LAST2" : \ (((VALUE) == 13327UL) ? "CV16CW5LAST3" : \ (((VALUE) == 17423UL) ? "CV16CW5LAST4" : \ (((VALUE) == 5391UL) ? "CV16CW6LAST1" : \ (((VALUE) == 9487UL) ? "CV16CW6LAST2" : \ (((VALUE) == 13583UL) ? "CV16CW6LAST3" : \ (((VALUE) == 17679UL) ? "CV16CW6LAST4" : \ (((VALUE) == 21775UL) ? "CV16CW6LAST5" : \ (((VALUE) == 5647UL) ? "CV16CW7LAST1" : \ (((VALUE) == 9743UL) ? "CV16CW7LAST2" : \ (((VALUE) == 13839UL) ? "CV16CW7LAST3" : \ (((VALUE) == 17935UL) ? "CV16CW7LAST4" : \ (((VALUE) == 22031UL) ? "CV16CW7LAST5" : \ (((VALUE) == 26127UL) ? "CV16CW7LAST6" : \ (((VALUE) == 5903UL) ? "CV16CW8LAST1" : \ (((VALUE) == 9999UL) ? "CV16CW8LAST2" : \ (((VALUE) == 14095UL) ? "CV16CW8LAST3" : \ (((VALUE) == 18191UL) ? "CV16CW8LAST4" : \ (((VALUE) == 22287UL) ? "CV16CW8LAST5" : \ (((VALUE) == 26383UL) ? "CV16CW8LAST6" : \ (((VALUE) == 30479UL) ? "CV16CW8LAST7" : \ (((VALUE) == 4383UL) ? "CV32CW2LAST1" : \ (((VALUE) == 4639UL) ? "CV32CW3LAST1" : \ (((VALUE) == 8735UL) ? "CV32CW3LAST2" : \ (((VALUE) == 4895UL) ? "CV32CW4LAST1" : \ (((VALUE) == 8991UL) ? "CV32CW4LAST2" : \ (((VALUE) == 13087UL) ? "CV32CW4LAST3" : \ (((VALUE) == 5151UL) ? "CV32CW5LAST1" : \ (((VALUE) == 9247UL) ? "CV32CW5LAST2" : \ (((VALUE) == 13343UL) ? "CV32CW5LAST3" : \ (((VALUE) == 17439UL) ? "CV32CW5LAST4" : \ (((VALUE) == 5407UL) ? "CV32CW6LAST1" : \ (((VALUE) == 9503UL) ? "CV32CW6LAST2" : \ (((VALUE) == 13599UL) ? "CV32CW6LAST3" : \ (((VALUE) == 17695UL) ? "CV32CW6LAST4" : \ (((VALUE) == 21791UL) ? "CV32CW6LAST5" : \ (((VALUE) == 5663UL) ? "CV32CW7LAST1" : \ (((VALUE) == 9759UL) ? "CV32CW7LAST2" : \ (((VALUE) == 13855UL) ? "CV32CW7LAST3" : \ (((VALUE) == 17951UL) ? "CV32CW7LAST4" : \ (((VALUE) == 22047UL) ? "CV32CW7LAST5" : \ (((VALUE) == 26143UL) ? "CV32CW7LAST6" : \ (((VALUE) == 5919UL) ? "CV32CW8LAST1" : \ (((VALUE) == 10015UL) ? "CV32CW8LAST2" : \ (((VALUE) == 14111UL) ? "CV32CW8LAST3" : \ (((VALUE) == 18207UL) ? "CV32CW8LAST4" : \ (((VALUE) == 22303UL) ? "CV32CW8LAST5" : \ (((VALUE) == 26399UL) ? "CV32CW8LAST6" : \ (((VALUE) == 30495UL) ? "CV32CW8LAST7" : \ (((VALUE) == 4415UL) ? "CV64CW2LAST1" : \ (((VALUE) == 4671UL) ? "CV64CW3LAST1" : \ (((VALUE) == 8767UL) ? "CV64CW3LAST2" : \ (((VALUE) == 4927UL) ? "CV64CW4LAST1" : \ (((VALUE) == 9023UL) ? "CV64CW4LAST2" : \ (((VALUE) == 13119UL) ? "CV64CW4LAST3" : \ (((VALUE) == 5183UL) ? "CV64CW5LAST1" : \ (((VALUE) == 9279UL) ? "CV64CW5LAST2" : \ (((VALUE) == 13375UL) ? "CV64CW5LAST3" : \ (((VALUE) == 17471UL) ? "CV64CW5LAST4" : \ (((VALUE) == 5439UL) ? "CV64CW6LAST1" : \ (((VALUE) == 9535UL) ? "CV64CW6LAST2" : \ (((VALUE) == 13631UL) ? "CV64CW6LAST3" : \ (((VALUE) == 17727UL) ? "CV64CW6LAST4" : \ (((VALUE) == 21823UL) ? "CV64CW6LAST5" : \ (((VALUE) == 5695UL) ? "CV64CW7LAST1" : \ (((VALUE) == 9791UL) ? "CV64CW7LAST2" : \ (((VALUE) == 13887UL) ? "CV64CW7LAST3" : \ (((VALUE) == 17983UL) ? "CV64CW7LAST4" : \ (((VALUE) == 22079UL) ? "CV64CW7LAST5" : \ (((VALUE) == 26175UL) ? "CV64CW7LAST6" : \ (((VALUE) == 5951UL) ? "CV64CW8LAST1" : \ (((VALUE) == 10047UL) ? "CV64CW8LAST2" : \ (((VALUE) == 14143UL) ? "CV64CW8LAST3" : \ (((VALUE) == 18239UL) ? "CV64CW8LAST4" : \ (((VALUE) == 22335UL) ? "CV64CW8LAST5" : \ (((VALUE) == 26431UL) ? "CV64CW8LAST6" : \ (((VALUE) == 30527UL) ? "CV64CW8LAST7" : \ (((VALUE) == 4479UL) ? "CV128CW2LAST1" : \ (((VALUE) == 4735UL) ? "CV128CW3LAST1" : \ (((VALUE) == 8831UL) ? "CV128CW3LAST2" : \ (((VALUE) == 4991UL) ? "CV128CW4LAST1" : \ (((VALUE) == 9087UL) ? "CV128CW4LAST2" : \ (((VALUE) == 13183UL) ? "CV128CW4LAST3" : \ (((VALUE) == 5247UL) ? "CV128CW5LAST1" : \ (((VALUE) == 9343UL) ? "CV128CW5LAST2" : \ (((VALUE) == 13439UL) ? "CV128CW5LAST3" : \ (((VALUE) == 17535UL) ? "CV128CW5LAST4" : \ (((VALUE) == 5503UL) ? "CV128CW6LAST1" : \ (((VALUE) == 9599UL) ? "CV128CW6LAST2" : \ (((VALUE) == 13695UL) ? "CV128CW6LAST3" : \ (((VALUE) == 17791UL) ? "CV128CW6LAST4" : \ (((VALUE) == 21887UL) ? "CV128CW6LAST5" : \ (((VALUE) == 5759UL) ? "CV128CW7LAST1" : \ (((VALUE) == 9855UL) ? "CV128CW7LAST2" : \ (((VALUE) == 13951UL) ? "CV128CW7LAST3" : \ (((VALUE) == 18047UL) ? "CV128CW7LAST4" : \ (((VALUE) == 22143UL) ? "CV128CW7LAST5" : \ (((VALUE) == 26239UL) ? "CV128CW7LAST6" : \ (((VALUE) == 6015UL) ? "CV128CW8LAST1" : \ (((VALUE) == 10111UL) ? "CV128CW8LAST2" : \ (((VALUE) == 14207UL) ? "CV128CW8LAST3" : \ (((VALUE) == 18303UL) ? "CV128CW8LAST4" : \ (((VALUE) == 22399UL) ? "CV128CW8LAST5" : \ (((VALUE) == 26495UL) ? "CV128CW8LAST6" : \ (((VALUE) == 30591UL) ? "CV128CW8LAST7" : \ (((VALUE) == 4607UL) ? "CV256CW2LAST1" : \ (((VALUE) == 4863UL) ? "CV256CW3LAST1" : \ (((VALUE) == 8959UL) ? "CV256CW3LAST2" : \ (((VALUE) == 5119UL) ? "CV256CW4LAST1" : \ (((VALUE) == 9215UL) ? "CV256CW4LAST2" : \ (((VALUE) == 13311UL) ? "CV256CW4LAST3" : \ (((VALUE) == 5375UL) ? "CV256CW5LAST1" : \ (((VALUE) == 9471UL) ? "CV256CW5LAST2" : \ (((VALUE) == 13567UL) ? "CV256CW5LAST3" : \ (((VALUE) == 17663UL) ? "CV256CW5LAST4" : \ (((VALUE) == 5631UL) ? "CV256CW6LAST1" : \ (((VALUE) == 9727UL) ? "CV256CW6LAST2" : \ (((VALUE) == 13823UL) ? "CV256CW6LAST3" : \ (((VALUE) == 17919UL) ? "CV256CW6LAST4" : \ (((VALUE) == 22015UL) ? "CV256CW6LAST5" : \ (((VALUE) == 5887UL) ? "CV256CW7LAST1" : \ (((VALUE) == 9983UL) ? "CV256CW7LAST2" : \ (((VALUE) == 14079UL) ? "CV256CW7LAST3" : \ (((VALUE) == 18175UL) ? "CV256CW7LAST4" : \ (((VALUE) == 22271UL) ? "CV256CW7LAST5" : \ (((VALUE) == 26367UL) ? "CV256CW7LAST6" : \ (((VALUE) == 6143UL) ? "CV256CW8LAST1" : \ (((VALUE) == 10239UL) ? "CV256CW8LAST2" : \ (((VALUE) == 14335UL) ? "CV256CW8LAST3" : \ (((VALUE) == 18431UL) ? "CV256CW8LAST4" : \ (((VALUE) == 22527UL) ? "CV256CW8LAST5" : \ (((VALUE) == 26623UL) ? "CV256CW8LAST6" : \ (((VALUE) == 30719UL) ? "CV256CW8LAST7" : "")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) /** * Check if a value of the DECUN_BFMT set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the DECUN_BFMT set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_DECUN_BFMT_IsValid(uint32_t val) { bool retval = false; switch (val) { case ATON_DECUN_BFMT_CV1CW1LAST0: case ATON_DECUN_BFMT_CV1CW2LAST0: case ATON_DECUN_BFMT_CV1CW3LAST0: case ATON_DECUN_BFMT_CV1CW4LAST0: case ATON_DECUN_BFMT_CV1CW5LAST0: case ATON_DECUN_BFMT_CV1CW6LAST0: case ATON_DECUN_BFMT_CV1CW7LAST0: case ATON_DECUN_BFMT_CV1CW8LAST0: case ATON_DECUN_BFMT_CV1CW2LAST1: case ATON_DECUN_BFMT_CV1CW3LAST1: case ATON_DECUN_BFMT_CV1CW4LAST1: case ATON_DECUN_BFMT_CV1CW5LAST1: case ATON_DECUN_BFMT_CV1CW6LAST1: case ATON_DECUN_BFMT_CV1CW7LAST1: case ATON_DECUN_BFMT_CV1CW8LAST1: case ATON_DECUN_BFMT_CV1CW3LAST2: case ATON_DECUN_BFMT_CV1CW4LAST2: case ATON_DECUN_BFMT_CV1CW5LAST2: case ATON_DECUN_BFMT_CV1CW6LAST2: case ATON_DECUN_BFMT_CV1CW7LAST2: case ATON_DECUN_BFMT_CV1CW8LAST2: case ATON_DECUN_BFMT_CV1CW4LAST3: case ATON_DECUN_BFMT_CV1CW5LAST3: case ATON_DECUN_BFMT_CV1CW6LAST3: case ATON_DECUN_BFMT_CV1CW7LAST3: case ATON_DECUN_BFMT_CV1CW8LAST3: case ATON_DECUN_BFMT_CV1CW5LAST4: case ATON_DECUN_BFMT_CV1CW6LAST4: case ATON_DECUN_BFMT_CV1CW7LAST4: case ATON_DECUN_BFMT_CV1CW8LAST4: case ATON_DECUN_BFMT_CV1CW6LAST5: case ATON_DECUN_BFMT_CV1CW7LAST5: case ATON_DECUN_BFMT_CV1CW8LAST5: case ATON_DECUN_BFMT_CV1CW7LAST6: case ATON_DECUN_BFMT_CV1CW8LAST6: case ATON_DECUN_BFMT_CV1CW8LAST7: case ATON_DECUN_BFMT_CV2CW1LAST0: case ATON_DECUN_BFMT_CV2CW2LAST0: case ATON_DECUN_BFMT_CV2CW3LAST0: case ATON_DECUN_BFMT_CV2CW4LAST0: case ATON_DECUN_BFMT_CV2CW5LAST0: case ATON_DECUN_BFMT_CV2CW6LAST0: case ATON_DECUN_BFMT_CV2CW7LAST0: case ATON_DECUN_BFMT_CV2CW8LAST0: case ATON_DECUN_BFMT_CV2CW2LAST1: case ATON_DECUN_BFMT_CV2CW3LAST1: case ATON_DECUN_BFMT_CV2CW4LAST1: case ATON_DECUN_BFMT_CV2CW5LAST1: case ATON_DECUN_BFMT_CV2CW6LAST1: case ATON_DECUN_BFMT_CV2CW7LAST1: case ATON_DECUN_BFMT_CV2CW8LAST1: case ATON_DECUN_BFMT_CV2CW3LAST2: case ATON_DECUN_BFMT_CV2CW4LAST2: case ATON_DECUN_BFMT_CV2CW5LAST2: case ATON_DECUN_BFMT_CV2CW6LAST2: case ATON_DECUN_BFMT_CV2CW7LAST2: case ATON_DECUN_BFMT_CV2CW8LAST2: case ATON_DECUN_BFMT_CV2CW4LAST3: case ATON_DECUN_BFMT_CV2CW5LAST3: case ATON_DECUN_BFMT_CV2CW6LAST3: case ATON_DECUN_BFMT_CV2CW7LAST3: case ATON_DECUN_BFMT_CV2CW8LAST3: case ATON_DECUN_BFMT_CV2CW5LAST4: case ATON_DECUN_BFMT_CV2CW6LAST4: case ATON_DECUN_BFMT_CV2CW7LAST4: case ATON_DECUN_BFMT_CV2CW8LAST4: case ATON_DECUN_BFMT_CV2CW6LAST5: case ATON_DECUN_BFMT_CV2CW7LAST5: case ATON_DECUN_BFMT_CV2CW8LAST5: case ATON_DECUN_BFMT_CV2CW7LAST6: case ATON_DECUN_BFMT_CV2CW8LAST6: case ATON_DECUN_BFMT_CV2CW8LAST7: case ATON_DECUN_BFMT_CV4CW1LAST0: case ATON_DECUN_BFMT_CV4CW2LAST0: case ATON_DECUN_BFMT_CV4CW3LAST0: case ATON_DECUN_BFMT_CV4CW4LAST0: case ATON_DECUN_BFMT_CV4CW5LAST0: case ATON_DECUN_BFMT_CV4CW6LAST0: case ATON_DECUN_BFMT_CV4CW7LAST0: case ATON_DECUN_BFMT_CV4CW8LAST0: case ATON_DECUN_BFMT_CV4CW2LAST1: case ATON_DECUN_BFMT_CV4CW3LAST1: case ATON_DECUN_BFMT_CV4CW4LAST1: case ATON_DECUN_BFMT_CV4CW5LAST1: case ATON_DECUN_BFMT_CV4CW6LAST1: case ATON_DECUN_BFMT_CV4CW7LAST1: case ATON_DECUN_BFMT_CV4CW8LAST1: case ATON_DECUN_BFMT_CV4CW3LAST2: case ATON_DECUN_BFMT_CV4CW4LAST2: case ATON_DECUN_BFMT_CV4CW5LAST2: case ATON_DECUN_BFMT_CV4CW6LAST2: case ATON_DECUN_BFMT_CV4CW7LAST2: case ATON_DECUN_BFMT_CV4CW8LAST2: case ATON_DECUN_BFMT_CV4CW4LAST3: case ATON_DECUN_BFMT_CV4CW5LAST3: case ATON_DECUN_BFMT_CV4CW6LAST3: case ATON_DECUN_BFMT_CV4CW7LAST3: case ATON_DECUN_BFMT_CV4CW8LAST3: case ATON_DECUN_BFMT_CV4CW5LAST4: case ATON_DECUN_BFMT_CV4CW6LAST4: case ATON_DECUN_BFMT_CV4CW7LAST4: case ATON_DECUN_BFMT_CV4CW8LAST4: case ATON_DECUN_BFMT_CV4CW6LAST5: case ATON_DECUN_BFMT_CV4CW7LAST5: case ATON_DECUN_BFMT_CV4CW8LAST5: case ATON_DECUN_BFMT_CV4CW7LAST6: case ATON_DECUN_BFMT_CV4CW8LAST6: case ATON_DECUN_BFMT_CV4CW8LAST7: case ATON_DECUN_BFMT_CV8CW1LAST0: case ATON_DECUN_BFMT_CV8CW2LAST0: case ATON_DECUN_BFMT_CV8CW3LAST0: case ATON_DECUN_BFMT_CV8CW4LAST0: case ATON_DECUN_BFMT_CV8CW5LAST0: case ATON_DECUN_BFMT_CV8CW6LAST0: case ATON_DECUN_BFMT_CV8CW7LAST0: case ATON_DECUN_BFMT_CV8CW8LAST0: case ATON_DECUN_BFMT_CV8CW2LAST1: case ATON_DECUN_BFMT_CV8CW3LAST1: case ATON_DECUN_BFMT_CV8CW4LAST1: case ATON_DECUN_BFMT_CV8CW5LAST1: case ATON_DECUN_BFMT_CV8CW6LAST1: case ATON_DECUN_BFMT_CV8CW7LAST1: case ATON_DECUN_BFMT_CV8CW8LAST1: case ATON_DECUN_BFMT_CV8CW3LAST2: case ATON_DECUN_BFMT_CV8CW4LAST2: case ATON_DECUN_BFMT_CV8CW5LAST2: case ATON_DECUN_BFMT_CV8CW6LAST2: case ATON_DECUN_BFMT_CV8CW7LAST2: case ATON_DECUN_BFMT_CV8CW8LAST2: case ATON_DECUN_BFMT_CV8CW4LAST3: case ATON_DECUN_BFMT_CV8CW5LAST3: case ATON_DECUN_BFMT_CV8CW6LAST3: case ATON_DECUN_BFMT_CV8CW7LAST3: case ATON_DECUN_BFMT_CV8CW8LAST3: case ATON_DECUN_BFMT_CV8CW5LAST4: case ATON_DECUN_BFMT_CV8CW6LAST4: case ATON_DECUN_BFMT_CV8CW7LAST4: case ATON_DECUN_BFMT_CV8CW8LAST4: case ATON_DECUN_BFMT_CV8CW6LAST5: case ATON_DECUN_BFMT_CV8CW7LAST5: case ATON_DECUN_BFMT_CV8CW8LAST5: case ATON_DECUN_BFMT_CV8CW7LAST6: case ATON_DECUN_BFMT_CV8CW8LAST6: case ATON_DECUN_BFMT_CV8CW8LAST7: case ATON_DECUN_BFMT_CV16CW1LAST0: case ATON_DECUN_BFMT_CV16CW2LAST0: case ATON_DECUN_BFMT_CV16CW3LAST0: case ATON_DECUN_BFMT_CV16CW4LAST0: case ATON_DECUN_BFMT_CV16CW5LAST0: case ATON_DECUN_BFMT_CV16CW6LAST0: case ATON_DECUN_BFMT_CV16CW7LAST0: case ATON_DECUN_BFMT_CV16CW8LAST0: case ATON_DECUN_BFMT_CV32CW1LAST0: case ATON_DECUN_BFMT_CV32CW2LAST0: case ATON_DECUN_BFMT_CV32CW3LAST0: case ATON_DECUN_BFMT_CV32CW4LAST0: case ATON_DECUN_BFMT_CV32CW5LAST0: case ATON_DECUN_BFMT_CV32CW6LAST0: case ATON_DECUN_BFMT_CV32CW7LAST0: case ATON_DECUN_BFMT_CV32CW8LAST0: case ATON_DECUN_BFMT_CV64CW1LAST0: case ATON_DECUN_BFMT_CV64CW2LAST0: case ATON_DECUN_BFMT_CV64CW3LAST0: case ATON_DECUN_BFMT_CV64CW4LAST0: case ATON_DECUN_BFMT_CV64CW5LAST0: case ATON_DECUN_BFMT_CV64CW6LAST0: case ATON_DECUN_BFMT_CV64CW7LAST0: case ATON_DECUN_BFMT_CV64CW8LAST0: case ATON_DECUN_BFMT_CV128CW1LAST0: case ATON_DECUN_BFMT_CV128CW2LAST0: case ATON_DECUN_BFMT_CV128CW3LAST0: case ATON_DECUN_BFMT_CV128CW4LAST0: case ATON_DECUN_BFMT_CV128CW5LAST0: case ATON_DECUN_BFMT_CV128CW6LAST0: case ATON_DECUN_BFMT_CV128CW7LAST0: case ATON_DECUN_BFMT_CV128CW8LAST0: case ATON_DECUN_BFMT_CV256CW1LAST0: case ATON_DECUN_BFMT_CV256CW2LAST0: case ATON_DECUN_BFMT_CV256CW3LAST0: case ATON_DECUN_BFMT_CV256CW4LAST0: case ATON_DECUN_BFMT_CV256CW5LAST0: case ATON_DECUN_BFMT_CV256CW6LAST0: case ATON_DECUN_BFMT_CV256CW7LAST0: case ATON_DECUN_BFMT_CV256CW8LAST0: case ATON_DECUN_BFMT_CV16CW2LAST1: case ATON_DECUN_BFMT_CV16CW3LAST1: case ATON_DECUN_BFMT_CV16CW3LAST2: case ATON_DECUN_BFMT_CV16CW4LAST1: case ATON_DECUN_BFMT_CV16CW4LAST2: case ATON_DECUN_BFMT_CV16CW4LAST3: case ATON_DECUN_BFMT_CV16CW5LAST1: case ATON_DECUN_BFMT_CV16CW5LAST2: case ATON_DECUN_BFMT_CV16CW5LAST3: case ATON_DECUN_BFMT_CV16CW5LAST4: case ATON_DECUN_BFMT_CV16CW6LAST1: case ATON_DECUN_BFMT_CV16CW6LAST2: case ATON_DECUN_BFMT_CV16CW6LAST3: case ATON_DECUN_BFMT_CV16CW6LAST4: case ATON_DECUN_BFMT_CV16CW6LAST5: case ATON_DECUN_BFMT_CV16CW7LAST1: case ATON_DECUN_BFMT_CV16CW7LAST2: case ATON_DECUN_BFMT_CV16CW7LAST3: case ATON_DECUN_BFMT_CV16CW7LAST4: case ATON_DECUN_BFMT_CV16CW7LAST5: case ATON_DECUN_BFMT_CV16CW7LAST6: case ATON_DECUN_BFMT_CV16CW8LAST1: case ATON_DECUN_BFMT_CV16CW8LAST2: case ATON_DECUN_BFMT_CV16CW8LAST3: case ATON_DECUN_BFMT_CV16CW8LAST4: case ATON_DECUN_BFMT_CV16CW8LAST5: case ATON_DECUN_BFMT_CV16CW8LAST6: case ATON_DECUN_BFMT_CV16CW8LAST7: case ATON_DECUN_BFMT_CV32CW2LAST1: case ATON_DECUN_BFMT_CV32CW3LAST1: case ATON_DECUN_BFMT_CV32CW3LAST2: case ATON_DECUN_BFMT_CV32CW4LAST1: case ATON_DECUN_BFMT_CV32CW4LAST2: case ATON_DECUN_BFMT_CV32CW4LAST3: case ATON_DECUN_BFMT_CV32CW5LAST1: case ATON_DECUN_BFMT_CV32CW5LAST2: case ATON_DECUN_BFMT_CV32CW5LAST3: case ATON_DECUN_BFMT_CV32CW5LAST4: case ATON_DECUN_BFMT_CV32CW6LAST1: case ATON_DECUN_BFMT_CV32CW6LAST2: case ATON_DECUN_BFMT_CV32CW6LAST3: case ATON_DECUN_BFMT_CV32CW6LAST4: case ATON_DECUN_BFMT_CV32CW6LAST5: case ATON_DECUN_BFMT_CV32CW7LAST1: case ATON_DECUN_BFMT_CV32CW7LAST2: case ATON_DECUN_BFMT_CV32CW7LAST3: case ATON_DECUN_BFMT_CV32CW7LAST4: case ATON_DECUN_BFMT_CV32CW7LAST5: case ATON_DECUN_BFMT_CV32CW7LAST6: case ATON_DECUN_BFMT_CV32CW8LAST1: case ATON_DECUN_BFMT_CV32CW8LAST2: case ATON_DECUN_BFMT_CV32CW8LAST3: case ATON_DECUN_BFMT_CV32CW8LAST4: case ATON_DECUN_BFMT_CV32CW8LAST5: case ATON_DECUN_BFMT_CV32CW8LAST6: case ATON_DECUN_BFMT_CV32CW8LAST7: case ATON_DECUN_BFMT_CV64CW2LAST1: case ATON_DECUN_BFMT_CV64CW3LAST1: case ATON_DECUN_BFMT_CV64CW3LAST2: case ATON_DECUN_BFMT_CV64CW4LAST1: case ATON_DECUN_BFMT_CV64CW4LAST2: case ATON_DECUN_BFMT_CV64CW4LAST3: case ATON_DECUN_BFMT_CV64CW5LAST1: case ATON_DECUN_BFMT_CV64CW5LAST2: case ATON_DECUN_BFMT_CV64CW5LAST3: case ATON_DECUN_BFMT_CV64CW5LAST4: case ATON_DECUN_BFMT_CV64CW6LAST1: case ATON_DECUN_BFMT_CV64CW6LAST2: case ATON_DECUN_BFMT_CV64CW6LAST3: case ATON_DECUN_BFMT_CV64CW6LAST4: case ATON_DECUN_BFMT_CV64CW6LAST5: case ATON_DECUN_BFMT_CV64CW7LAST1: case ATON_DECUN_BFMT_CV64CW7LAST2: case ATON_DECUN_BFMT_CV64CW7LAST3: case ATON_DECUN_BFMT_CV64CW7LAST4: case ATON_DECUN_BFMT_CV64CW7LAST5: case ATON_DECUN_BFMT_CV64CW7LAST6: case ATON_DECUN_BFMT_CV64CW8LAST1: case ATON_DECUN_BFMT_CV64CW8LAST2: case ATON_DECUN_BFMT_CV64CW8LAST3: case ATON_DECUN_BFMT_CV64CW8LAST4: case ATON_DECUN_BFMT_CV64CW8LAST5: case ATON_DECUN_BFMT_CV64CW8LAST6: case ATON_DECUN_BFMT_CV64CW8LAST7: case ATON_DECUN_BFMT_CV128CW2LAST1: case ATON_DECUN_BFMT_CV128CW3LAST1: case ATON_DECUN_BFMT_CV128CW3LAST2: case ATON_DECUN_BFMT_CV128CW4LAST1: case ATON_DECUN_BFMT_CV128CW4LAST2: case ATON_DECUN_BFMT_CV128CW4LAST3: case ATON_DECUN_BFMT_CV128CW5LAST1: case ATON_DECUN_BFMT_CV128CW5LAST2: case ATON_DECUN_BFMT_CV128CW5LAST3: case ATON_DECUN_BFMT_CV128CW5LAST4: case ATON_DECUN_BFMT_CV128CW6LAST1: case ATON_DECUN_BFMT_CV128CW6LAST2: case ATON_DECUN_BFMT_CV128CW6LAST3: case ATON_DECUN_BFMT_CV128CW6LAST4: case ATON_DECUN_BFMT_CV128CW6LAST5: case ATON_DECUN_BFMT_CV128CW7LAST1: case ATON_DECUN_BFMT_CV128CW7LAST2: case ATON_DECUN_BFMT_CV128CW7LAST3: case ATON_DECUN_BFMT_CV128CW7LAST4: case ATON_DECUN_BFMT_CV128CW7LAST5: case ATON_DECUN_BFMT_CV128CW7LAST6: case ATON_DECUN_BFMT_CV128CW8LAST1: case ATON_DECUN_BFMT_CV128CW8LAST2: case ATON_DECUN_BFMT_CV128CW8LAST3: case ATON_DECUN_BFMT_CV128CW8LAST4: case ATON_DECUN_BFMT_CV128CW8LAST5: case ATON_DECUN_BFMT_CV128CW8LAST6: case ATON_DECUN_BFMT_CV128CW8LAST7: case ATON_DECUN_BFMT_CV256CW2LAST1: case ATON_DECUN_BFMT_CV256CW3LAST1: case ATON_DECUN_BFMT_CV256CW3LAST2: case ATON_DECUN_BFMT_CV256CW4LAST1: case ATON_DECUN_BFMT_CV256CW4LAST2: case ATON_DECUN_BFMT_CV256CW4LAST3: case ATON_DECUN_BFMT_CV256CW5LAST1: case ATON_DECUN_BFMT_CV256CW5LAST2: case ATON_DECUN_BFMT_CV256CW5LAST3: case ATON_DECUN_BFMT_CV256CW5LAST4: case ATON_DECUN_BFMT_CV256CW6LAST1: case ATON_DECUN_BFMT_CV256CW6LAST2: case ATON_DECUN_BFMT_CV256CW6LAST3: case ATON_DECUN_BFMT_CV256CW6LAST4: case ATON_DECUN_BFMT_CV256CW6LAST5: case ATON_DECUN_BFMT_CV256CW7LAST1: case ATON_DECUN_BFMT_CV256CW7LAST2: case ATON_DECUN_BFMT_CV256CW7LAST3: case ATON_DECUN_BFMT_CV256CW7LAST4: case ATON_DECUN_BFMT_CV256CW7LAST5: case ATON_DECUN_BFMT_CV256CW7LAST6: case ATON_DECUN_BFMT_CV256CW8LAST1: case ATON_DECUN_BFMT_CV256CW8LAST2: case ATON_DECUN_BFMT_CV256CW8LAST3: case ATON_DECUN_BFMT_CV256CW8LAST4: case ATON_DECUN_BFMT_CV256CW8LAST5: case ATON_DECUN_BFMT_CV256CW8LAST6: case ATON_DECUN_BFMT_CV256CW8LAST7: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the DECUN_BFMT set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the DECUN_BFMT set of enumerated values */ static inline const int8_t *ATON_DECUN_BFMT_GetName(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_DECUN_BFMT_CV1CW1LAST0: str = (const int8_t *)"CV1CW1LAST0"; break; case ATON_DECUN_BFMT_CV1CW2LAST0: str = (const int8_t *)"CV1CW2LAST0"; break; case ATON_DECUN_BFMT_CV1CW3LAST0: str = (const int8_t *)"CV1CW3LAST0"; break; case ATON_DECUN_BFMT_CV1CW4LAST0: str = (const int8_t *)"CV1CW4LAST0"; break; case ATON_DECUN_BFMT_CV1CW5LAST0: str = (const int8_t *)"CV1CW5LAST0"; break; case ATON_DECUN_BFMT_CV1CW6LAST0: str = (const int8_t *)"CV1CW6LAST0"; break; case ATON_DECUN_BFMT_CV1CW7LAST0: str = (const int8_t *)"CV1CW7LAST0"; break; case ATON_DECUN_BFMT_CV1CW8LAST0: str = (const int8_t *)"CV1CW8LAST0"; break; case ATON_DECUN_BFMT_CV1CW2LAST1: str = (const int8_t *)"CV1CW2LAST1"; break; case ATON_DECUN_BFMT_CV1CW3LAST1: str = (const int8_t *)"CV1CW3LAST1"; break; case ATON_DECUN_BFMT_CV1CW4LAST1: str = (const int8_t *)"CV1CW4LAST1"; break; case ATON_DECUN_BFMT_CV1CW5LAST1: str = (const int8_t *)"CV1CW5LAST1"; break; case ATON_DECUN_BFMT_CV1CW6LAST1: str = (const int8_t *)"CV1CW6LAST1"; break; case ATON_DECUN_BFMT_CV1CW7LAST1: str = (const int8_t *)"CV1CW7LAST1"; break; case ATON_DECUN_BFMT_CV1CW8LAST1: str = (const int8_t *)"CV1CW8LAST1"; break; case ATON_DECUN_BFMT_CV1CW3LAST2: str = (const int8_t *)"CV1CW3LAST2"; break; case ATON_DECUN_BFMT_CV1CW4LAST2: str = (const int8_t *)"CV1CW4LAST2"; break; case ATON_DECUN_BFMT_CV1CW5LAST2: str = (const int8_t *)"CV1CW5LAST2"; break; case ATON_DECUN_BFMT_CV1CW6LAST2: str = (const int8_t *)"CV1CW6LAST2"; break; case ATON_DECUN_BFMT_CV1CW7LAST2: str = (const int8_t *)"CV1CW7LAST2"; break; case ATON_DECUN_BFMT_CV1CW8LAST2: str = (const int8_t *)"CV1CW8LAST2"; break; case ATON_DECUN_BFMT_CV1CW4LAST3: str = (const int8_t *)"CV1CW4LAST3"; break; case ATON_DECUN_BFMT_CV1CW5LAST3: str = (const int8_t *)"CV1CW5LAST3"; break; case ATON_DECUN_BFMT_CV1CW6LAST3: str = (const int8_t *)"CV1CW6LAST3"; break; case ATON_DECUN_BFMT_CV1CW7LAST3: str = (const int8_t *)"CV1CW7LAST3"; break; case ATON_DECUN_BFMT_CV1CW8LAST3: str = (const int8_t *)"CV1CW8LAST3"; break; case ATON_DECUN_BFMT_CV1CW5LAST4: str = (const int8_t *)"CV1CW5LAST4"; break; case ATON_DECUN_BFMT_CV1CW6LAST4: str = (const int8_t *)"CV1CW6LAST4"; break; case ATON_DECUN_BFMT_CV1CW7LAST4: str = (const int8_t *)"CV1CW7LAST4"; break; case ATON_DECUN_BFMT_CV1CW8LAST4: str = (const int8_t *)"CV1CW8LAST4"; break; case ATON_DECUN_BFMT_CV1CW6LAST5: str = (const int8_t *)"CV1CW6LAST5"; break; case ATON_DECUN_BFMT_CV1CW7LAST5: str = (const int8_t *)"CV1CW7LAST5"; break; case ATON_DECUN_BFMT_CV1CW8LAST5: str = (const int8_t *)"CV1CW8LAST5"; break; case ATON_DECUN_BFMT_CV1CW7LAST6: str = (const int8_t *)"CV1CW7LAST6"; break; case ATON_DECUN_BFMT_CV1CW8LAST6: str = (const int8_t *)"CV1CW8LAST6"; break; case ATON_DECUN_BFMT_CV1CW8LAST7: str = (const int8_t *)"CV1CW8LAST7"; break; case ATON_DECUN_BFMT_CV2CW1LAST0: str = (const int8_t *)"CV2CW1LAST0"; break; case ATON_DECUN_BFMT_CV2CW2LAST0: str = (const int8_t *)"CV2CW2LAST0"; break; case ATON_DECUN_BFMT_CV2CW3LAST0: str = (const int8_t *)"CV2CW3LAST0"; break; case ATON_DECUN_BFMT_CV2CW4LAST0: str = (const int8_t *)"CV2CW4LAST0"; break; case ATON_DECUN_BFMT_CV2CW5LAST0: str = (const int8_t *)"CV2CW5LAST0"; break; case ATON_DECUN_BFMT_CV2CW6LAST0: str = (const int8_t *)"CV2CW6LAST0"; break; case ATON_DECUN_BFMT_CV2CW7LAST0: str = (const int8_t *)"CV2CW7LAST0"; break; case ATON_DECUN_BFMT_CV2CW8LAST0: str = (const int8_t *)"CV2CW8LAST0"; break; case ATON_DECUN_BFMT_CV2CW2LAST1: str = (const int8_t *)"CV2CW2LAST1"; break; case ATON_DECUN_BFMT_CV2CW3LAST1: str = (const int8_t *)"CV2CW3LAST1"; break; case ATON_DECUN_BFMT_CV2CW4LAST1: str = (const int8_t *)"CV2CW4LAST1"; break; case ATON_DECUN_BFMT_CV2CW5LAST1: str = (const int8_t *)"CV2CW5LAST1"; break; case ATON_DECUN_BFMT_CV2CW6LAST1: str = (const int8_t *)"CV2CW6LAST1"; break; case ATON_DECUN_BFMT_CV2CW7LAST1: str = (const int8_t *)"CV2CW7LAST1"; break; case ATON_DECUN_BFMT_CV2CW8LAST1: str = (const int8_t *)"CV2CW8LAST1"; break; case ATON_DECUN_BFMT_CV2CW3LAST2: str = (const int8_t *)"CV2CW3LAST2"; break; case ATON_DECUN_BFMT_CV2CW4LAST2: str = (const int8_t *)"CV2CW4LAST2"; break; case ATON_DECUN_BFMT_CV2CW5LAST2: str = (const int8_t *)"CV2CW5LAST2"; break; case ATON_DECUN_BFMT_CV2CW6LAST2: str = (const int8_t *)"CV2CW6LAST2"; break; case ATON_DECUN_BFMT_CV2CW7LAST2: str = (const int8_t *)"CV2CW7LAST2"; break; case ATON_DECUN_BFMT_CV2CW8LAST2: str = (const int8_t *)"CV2CW8LAST2"; break; case ATON_DECUN_BFMT_CV2CW4LAST3: str = (const int8_t *)"CV2CW4LAST3"; break; case ATON_DECUN_BFMT_CV2CW5LAST3: str = (const int8_t *)"CV2CW5LAST3"; break; case ATON_DECUN_BFMT_CV2CW6LAST3: str = (const int8_t *)"CV2CW6LAST3"; break; case ATON_DECUN_BFMT_CV2CW7LAST3: str = (const int8_t *)"CV2CW7LAST3"; break; case ATON_DECUN_BFMT_CV2CW8LAST3: str = (const int8_t *)"CV2CW8LAST3"; break; case ATON_DECUN_BFMT_CV2CW5LAST4: str = (const int8_t *)"CV2CW5LAST4"; break; case ATON_DECUN_BFMT_CV2CW6LAST4: str = (const int8_t *)"CV2CW6LAST4"; break; case ATON_DECUN_BFMT_CV2CW7LAST4: str = (const int8_t *)"CV2CW7LAST4"; break; case ATON_DECUN_BFMT_CV2CW8LAST4: str = (const int8_t *)"CV2CW8LAST4"; break; case ATON_DECUN_BFMT_CV2CW6LAST5: str = (const int8_t *)"CV2CW6LAST5"; break; case ATON_DECUN_BFMT_CV2CW7LAST5: str = (const int8_t *)"CV2CW7LAST5"; break; case ATON_DECUN_BFMT_CV2CW8LAST5: str = (const int8_t *)"CV2CW8LAST5"; break; case ATON_DECUN_BFMT_CV2CW7LAST6: str = (const int8_t *)"CV2CW7LAST6"; break; case ATON_DECUN_BFMT_CV2CW8LAST6: str = (const int8_t *)"CV2CW8LAST6"; break; case ATON_DECUN_BFMT_CV2CW8LAST7: str = (const int8_t *)"CV2CW8LAST7"; break; case ATON_DECUN_BFMT_CV4CW1LAST0: str = (const int8_t *)"CV4CW1LAST0"; break; case ATON_DECUN_BFMT_CV4CW2LAST0: str = (const int8_t *)"CV4CW2LAST0"; break; case ATON_DECUN_BFMT_CV4CW3LAST0: str = (const int8_t *)"CV4CW3LAST0"; break; case ATON_DECUN_BFMT_CV4CW4LAST0: str = (const int8_t *)"CV4CW4LAST0"; break; case ATON_DECUN_BFMT_CV4CW5LAST0: str = (const int8_t *)"CV4CW5LAST0"; break; case ATON_DECUN_BFMT_CV4CW6LAST0: str = (const int8_t *)"CV4CW6LAST0"; break; case ATON_DECUN_BFMT_CV4CW7LAST0: str = (const int8_t *)"CV4CW7LAST0"; break; case ATON_DECUN_BFMT_CV4CW8LAST0: str = (const int8_t *)"CV4CW8LAST0"; break; case ATON_DECUN_BFMT_CV4CW2LAST1: str = (const int8_t *)"CV4CW2LAST1"; break; case ATON_DECUN_BFMT_CV4CW3LAST1: str = (const int8_t *)"CV4CW3LAST1"; break; case ATON_DECUN_BFMT_CV4CW4LAST1: str = (const int8_t *)"CV4CW4LAST1"; break; case ATON_DECUN_BFMT_CV4CW5LAST1: str = (const int8_t *)"CV4CW5LAST1"; break; case ATON_DECUN_BFMT_CV4CW6LAST1: str = (const int8_t *)"CV4CW6LAST1"; break; case ATON_DECUN_BFMT_CV4CW7LAST1: str = (const int8_t *)"CV4CW7LAST1"; break; case ATON_DECUN_BFMT_CV4CW8LAST1: str = (const int8_t *)"CV4CW8LAST1"; break; case ATON_DECUN_BFMT_CV4CW3LAST2: str = (const int8_t *)"CV4CW3LAST2"; break; case ATON_DECUN_BFMT_CV4CW4LAST2: str = (const int8_t *)"CV4CW4LAST2"; break; case ATON_DECUN_BFMT_CV4CW5LAST2: str = (const int8_t *)"CV4CW5LAST2"; break; case ATON_DECUN_BFMT_CV4CW6LAST2: str = (const int8_t *)"CV4CW6LAST2"; break; case ATON_DECUN_BFMT_CV4CW7LAST2: str = (const int8_t *)"CV4CW7LAST2"; break; case ATON_DECUN_BFMT_CV4CW8LAST2: str = (const int8_t *)"CV4CW8LAST2"; break; case ATON_DECUN_BFMT_CV4CW4LAST3: str = (const int8_t *)"CV4CW4LAST3"; break; case ATON_DECUN_BFMT_CV4CW5LAST3: str = (const int8_t *)"CV4CW5LAST3"; break; case ATON_DECUN_BFMT_CV4CW6LAST3: str = (const int8_t *)"CV4CW6LAST3"; break; case ATON_DECUN_BFMT_CV4CW7LAST3: str = (const int8_t *)"CV4CW7LAST3"; break; case ATON_DECUN_BFMT_CV4CW8LAST3: str = (const int8_t *)"CV4CW8LAST3"; break; case ATON_DECUN_BFMT_CV4CW5LAST4: str = (const int8_t *)"CV4CW5LAST4"; break; case ATON_DECUN_BFMT_CV4CW6LAST4: str = (const int8_t *)"CV4CW6LAST4"; break; case ATON_DECUN_BFMT_CV4CW7LAST4: str = (const int8_t *)"CV4CW7LAST4"; break; case ATON_DECUN_BFMT_CV4CW8LAST4: str = (const int8_t *)"CV4CW8LAST4"; break; case ATON_DECUN_BFMT_CV4CW6LAST5: str = (const int8_t *)"CV4CW6LAST5"; break; case ATON_DECUN_BFMT_CV4CW7LAST5: str = (const int8_t *)"CV4CW7LAST5"; break; case ATON_DECUN_BFMT_CV4CW8LAST5: str = (const int8_t *)"CV4CW8LAST5"; break; case ATON_DECUN_BFMT_CV4CW7LAST6: str = (const int8_t *)"CV4CW7LAST6"; break; case ATON_DECUN_BFMT_CV4CW8LAST6: str = (const int8_t *)"CV4CW8LAST6"; break; case ATON_DECUN_BFMT_CV4CW8LAST7: str = (const int8_t *)"CV4CW8LAST7"; break; case ATON_DECUN_BFMT_CV8CW1LAST0: str = (const int8_t *)"CV8CW1LAST0"; break; case ATON_DECUN_BFMT_CV8CW2LAST0: str = (const int8_t *)"CV8CW2LAST0"; break; case ATON_DECUN_BFMT_CV8CW3LAST0: str = (const int8_t *)"CV8CW3LAST0"; break; case ATON_DECUN_BFMT_CV8CW4LAST0: str = (const int8_t *)"CV8CW4LAST0"; break; case ATON_DECUN_BFMT_CV8CW5LAST0: str = (const int8_t *)"CV8CW5LAST0"; break; case ATON_DECUN_BFMT_CV8CW6LAST0: str = (const int8_t *)"CV8CW6LAST0"; break; case ATON_DECUN_BFMT_CV8CW7LAST0: str = (const int8_t *)"CV8CW7LAST0"; break; case ATON_DECUN_BFMT_CV8CW8LAST0: str = (const int8_t *)"CV8CW8LAST0"; break; case ATON_DECUN_BFMT_CV8CW2LAST1: str = (const int8_t *)"CV8CW2LAST1"; break; case ATON_DECUN_BFMT_CV8CW3LAST1: str = (const int8_t *)"CV8CW3LAST1"; break; case ATON_DECUN_BFMT_CV8CW4LAST1: str = (const int8_t *)"CV8CW4LAST1"; break; case ATON_DECUN_BFMT_CV8CW5LAST1: str = (const int8_t *)"CV8CW5LAST1"; break; case ATON_DECUN_BFMT_CV8CW6LAST1: str = (const int8_t *)"CV8CW6LAST1"; break; case ATON_DECUN_BFMT_CV8CW7LAST1: str = (const int8_t *)"CV8CW7LAST1"; break; case ATON_DECUN_BFMT_CV8CW8LAST1: str = (const int8_t *)"CV8CW8LAST1"; break; case ATON_DECUN_BFMT_CV8CW3LAST2: str = (const int8_t *)"CV8CW3LAST2"; break; case ATON_DECUN_BFMT_CV8CW4LAST2: str = (const int8_t *)"CV8CW4LAST2"; break; case ATON_DECUN_BFMT_CV8CW5LAST2: str = (const int8_t *)"CV8CW5LAST2"; break; case ATON_DECUN_BFMT_CV8CW6LAST2: str = (const int8_t *)"CV8CW6LAST2"; break; case ATON_DECUN_BFMT_CV8CW7LAST2: str = (const int8_t *)"CV8CW7LAST2"; break; case ATON_DECUN_BFMT_CV8CW8LAST2: str = (const int8_t *)"CV8CW8LAST2"; break; case ATON_DECUN_BFMT_CV8CW4LAST3: str = (const int8_t *)"CV8CW4LAST3"; break; case ATON_DECUN_BFMT_CV8CW5LAST3: str = (const int8_t *)"CV8CW5LAST3"; break; case ATON_DECUN_BFMT_CV8CW6LAST3: str = (const int8_t *)"CV8CW6LAST3"; break; case ATON_DECUN_BFMT_CV8CW7LAST3: str = (const int8_t *)"CV8CW7LAST3"; break; case ATON_DECUN_BFMT_CV8CW8LAST3: str = (const int8_t *)"CV8CW8LAST3"; break; case ATON_DECUN_BFMT_CV8CW5LAST4: str = (const int8_t *)"CV8CW5LAST4"; break; case ATON_DECUN_BFMT_CV8CW6LAST4: str = (const int8_t *)"CV8CW6LAST4"; break; case ATON_DECUN_BFMT_CV8CW7LAST4: str = (const int8_t *)"CV8CW7LAST4"; break; case ATON_DECUN_BFMT_CV8CW8LAST4: str = (const int8_t *)"CV8CW8LAST4"; break; case ATON_DECUN_BFMT_CV8CW6LAST5: str = (const int8_t *)"CV8CW6LAST5"; break; case ATON_DECUN_BFMT_CV8CW7LAST5: str = (const int8_t *)"CV8CW7LAST5"; break; case ATON_DECUN_BFMT_CV8CW8LAST5: str = (const int8_t *)"CV8CW8LAST5"; break; case ATON_DECUN_BFMT_CV8CW7LAST6: str = (const int8_t *)"CV8CW7LAST6"; break; case ATON_DECUN_BFMT_CV8CW8LAST6: str = (const int8_t *)"CV8CW8LAST6"; break; case ATON_DECUN_BFMT_CV8CW8LAST7: str = (const int8_t *)"CV8CW8LAST7"; break; case ATON_DECUN_BFMT_CV16CW1LAST0: str = (const int8_t *)"CV16CW1LAST0"; break; case ATON_DECUN_BFMT_CV16CW2LAST0: str = (const int8_t *)"CV16CW2LAST0"; break; case ATON_DECUN_BFMT_CV16CW3LAST0: str = (const int8_t *)"CV16CW3LAST0"; break; case ATON_DECUN_BFMT_CV16CW4LAST0: str = (const int8_t *)"CV16CW4LAST0"; break; case ATON_DECUN_BFMT_CV16CW5LAST0: str = (const int8_t *)"CV16CW5LAST0"; break; case ATON_DECUN_BFMT_CV16CW6LAST0: str = (const int8_t *)"CV16CW6LAST0"; break; case ATON_DECUN_BFMT_CV16CW7LAST0: str = (const int8_t *)"CV16CW7LAST0"; break; case ATON_DECUN_BFMT_CV16CW8LAST0: str = (const int8_t *)"CV16CW8LAST0"; break; case ATON_DECUN_BFMT_CV32CW1LAST0: str = (const int8_t *)"CV32CW1LAST0"; break; case ATON_DECUN_BFMT_CV32CW2LAST0: str = (const int8_t *)"CV32CW2LAST0"; break; case ATON_DECUN_BFMT_CV32CW3LAST0: str = (const int8_t *)"CV32CW3LAST0"; break; case ATON_DECUN_BFMT_CV32CW4LAST0: str = (const int8_t *)"CV32CW4LAST0"; break; case ATON_DECUN_BFMT_CV32CW5LAST0: str = (const int8_t *)"CV32CW5LAST0"; break; case ATON_DECUN_BFMT_CV32CW6LAST0: str = (const int8_t *)"CV32CW6LAST0"; break; case ATON_DECUN_BFMT_CV32CW7LAST0: str = (const int8_t *)"CV32CW7LAST0"; break; case ATON_DECUN_BFMT_CV32CW8LAST0: str = (const int8_t *)"CV32CW8LAST0"; break; case ATON_DECUN_BFMT_CV64CW1LAST0: str = (const int8_t *)"CV64CW1LAST0"; break; case ATON_DECUN_BFMT_CV64CW2LAST0: str = (const int8_t *)"CV64CW2LAST0"; break; case ATON_DECUN_BFMT_CV64CW3LAST0: str = (const int8_t *)"CV64CW3LAST0"; break; case ATON_DECUN_BFMT_CV64CW4LAST0: str = (const int8_t *)"CV64CW4LAST0"; break; case ATON_DECUN_BFMT_CV64CW5LAST0: str = (const int8_t *)"CV64CW5LAST0"; break; case ATON_DECUN_BFMT_CV64CW6LAST0: str = (const int8_t *)"CV64CW6LAST0"; break; case ATON_DECUN_BFMT_CV64CW7LAST0: str = (const int8_t *)"CV64CW7LAST0"; break; case ATON_DECUN_BFMT_CV64CW8LAST0: str = (const int8_t *)"CV64CW8LAST0"; break; case ATON_DECUN_BFMT_CV128CW1LAST0: str = (const int8_t *)"CV128CW1LAST0"; break; case ATON_DECUN_BFMT_CV128CW2LAST0: str = (const int8_t *)"CV128CW2LAST0"; break; case ATON_DECUN_BFMT_CV128CW3LAST0: str = (const int8_t *)"CV128CW3LAST0"; break; case ATON_DECUN_BFMT_CV128CW4LAST0: str = (const int8_t *)"CV128CW4LAST0"; break; case ATON_DECUN_BFMT_CV128CW5LAST0: str = (const int8_t *)"CV128CW5LAST0"; break; case ATON_DECUN_BFMT_CV128CW6LAST0: str = (const int8_t *)"CV128CW6LAST0"; break; case ATON_DECUN_BFMT_CV128CW7LAST0: str = (const int8_t *)"CV128CW7LAST0"; break; case ATON_DECUN_BFMT_CV128CW8LAST0: str = (const int8_t *)"CV128CW8LAST0"; break; case ATON_DECUN_BFMT_CV256CW1LAST0: str = (const int8_t *)"CV256CW1LAST0"; break; case ATON_DECUN_BFMT_CV256CW2LAST0: str = (const int8_t *)"CV256CW2LAST0"; break; case ATON_DECUN_BFMT_CV256CW3LAST0: str = (const int8_t *)"CV256CW3LAST0"; break; case ATON_DECUN_BFMT_CV256CW4LAST0: str = (const int8_t *)"CV256CW4LAST0"; break; case ATON_DECUN_BFMT_CV256CW5LAST0: str = (const int8_t *)"CV256CW5LAST0"; break; case ATON_DECUN_BFMT_CV256CW6LAST0: str = (const int8_t *)"CV256CW6LAST0"; break; case ATON_DECUN_BFMT_CV256CW7LAST0: str = (const int8_t *)"CV256CW7LAST0"; break; case ATON_DECUN_BFMT_CV256CW8LAST0: str = (const int8_t *)"CV256CW8LAST0"; break; case ATON_DECUN_BFMT_CV16CW2LAST1: str = (const int8_t *)"CV16CW2LAST1"; break; case ATON_DECUN_BFMT_CV16CW3LAST1: str = (const int8_t *)"CV16CW3LAST1"; break; case ATON_DECUN_BFMT_CV16CW3LAST2: str = (const int8_t *)"CV16CW3LAST2"; break; case ATON_DECUN_BFMT_CV16CW4LAST1: str = (const int8_t *)"CV16CW4LAST1"; break; case ATON_DECUN_BFMT_CV16CW4LAST2: str = (const int8_t *)"CV16CW4LAST2"; break; case ATON_DECUN_BFMT_CV16CW4LAST3: str = (const int8_t *)"CV16CW4LAST3"; break; case ATON_DECUN_BFMT_CV16CW5LAST1: str = (const int8_t *)"CV16CW5LAST1"; break; case ATON_DECUN_BFMT_CV16CW5LAST2: str = (const int8_t *)"CV16CW5LAST2"; break; case ATON_DECUN_BFMT_CV16CW5LAST3: str = (const int8_t *)"CV16CW5LAST3"; break; case ATON_DECUN_BFMT_CV16CW5LAST4: str = (const int8_t *)"CV16CW5LAST4"; break; case ATON_DECUN_BFMT_CV16CW6LAST1: str = (const int8_t *)"CV16CW6LAST1"; break; case ATON_DECUN_BFMT_CV16CW6LAST2: str = (const int8_t *)"CV16CW6LAST2"; break; case ATON_DECUN_BFMT_CV16CW6LAST3: str = (const int8_t *)"CV16CW6LAST3"; break; case ATON_DECUN_BFMT_CV16CW6LAST4: str = (const int8_t *)"CV16CW6LAST4"; break; case ATON_DECUN_BFMT_CV16CW6LAST5: str = (const int8_t *)"CV16CW6LAST5"; break; case ATON_DECUN_BFMT_CV16CW7LAST1: str = (const int8_t *)"CV16CW7LAST1"; break; case ATON_DECUN_BFMT_CV16CW7LAST2: str = (const int8_t *)"CV16CW7LAST2"; break; case ATON_DECUN_BFMT_CV16CW7LAST3: str = (const int8_t *)"CV16CW7LAST3"; break; case ATON_DECUN_BFMT_CV16CW7LAST4: str = (const int8_t *)"CV16CW7LAST4"; break; case ATON_DECUN_BFMT_CV16CW7LAST5: str = (const int8_t *)"CV16CW7LAST5"; break; case ATON_DECUN_BFMT_CV16CW7LAST6: str = (const int8_t *)"CV16CW7LAST6"; break; case ATON_DECUN_BFMT_CV16CW8LAST1: str = (const int8_t *)"CV16CW8LAST1"; break; case ATON_DECUN_BFMT_CV16CW8LAST2: str = (const int8_t *)"CV16CW8LAST2"; break; case ATON_DECUN_BFMT_CV16CW8LAST3: str = (const int8_t *)"CV16CW8LAST3"; break; case ATON_DECUN_BFMT_CV16CW8LAST4: str = (const int8_t *)"CV16CW8LAST4"; break; case ATON_DECUN_BFMT_CV16CW8LAST5: str = (const int8_t *)"CV16CW8LAST5"; break; case ATON_DECUN_BFMT_CV16CW8LAST6: str = (const int8_t *)"CV16CW8LAST6"; break; case ATON_DECUN_BFMT_CV16CW8LAST7: str = (const int8_t *)"CV16CW8LAST7"; break; case ATON_DECUN_BFMT_CV32CW2LAST1: str = (const int8_t *)"CV32CW2LAST1"; break; case ATON_DECUN_BFMT_CV32CW3LAST1: str = (const int8_t *)"CV32CW3LAST1"; break; case ATON_DECUN_BFMT_CV32CW3LAST2: str = (const int8_t *)"CV32CW3LAST2"; break; case ATON_DECUN_BFMT_CV32CW4LAST1: str = (const int8_t *)"CV32CW4LAST1"; break; case ATON_DECUN_BFMT_CV32CW4LAST2: str = (const int8_t *)"CV32CW4LAST2"; break; case ATON_DECUN_BFMT_CV32CW4LAST3: str = (const int8_t *)"CV32CW4LAST3"; break; case ATON_DECUN_BFMT_CV32CW5LAST1: str = (const int8_t *)"CV32CW5LAST1"; break; case ATON_DECUN_BFMT_CV32CW5LAST2: str = (const int8_t *)"CV32CW5LAST2"; break; case ATON_DECUN_BFMT_CV32CW5LAST3: str = (const int8_t *)"CV32CW5LAST3"; break; case ATON_DECUN_BFMT_CV32CW5LAST4: str = (const int8_t *)"CV32CW5LAST4"; break; case ATON_DECUN_BFMT_CV32CW6LAST1: str = (const int8_t *)"CV32CW6LAST1"; break; case ATON_DECUN_BFMT_CV32CW6LAST2: str = (const int8_t *)"CV32CW6LAST2"; break; case ATON_DECUN_BFMT_CV32CW6LAST3: str = (const int8_t *)"CV32CW6LAST3"; break; case ATON_DECUN_BFMT_CV32CW6LAST4: str = (const int8_t *)"CV32CW6LAST4"; break; case ATON_DECUN_BFMT_CV32CW6LAST5: str = (const int8_t *)"CV32CW6LAST5"; break; case ATON_DECUN_BFMT_CV32CW7LAST1: str = (const int8_t *)"CV32CW7LAST1"; break; case ATON_DECUN_BFMT_CV32CW7LAST2: str = (const int8_t *)"CV32CW7LAST2"; break; case ATON_DECUN_BFMT_CV32CW7LAST3: str = (const int8_t *)"CV32CW7LAST3"; break; case ATON_DECUN_BFMT_CV32CW7LAST4: str = (const int8_t *)"CV32CW7LAST4"; break; case ATON_DECUN_BFMT_CV32CW7LAST5: str = (const int8_t *)"CV32CW7LAST5"; break; case ATON_DECUN_BFMT_CV32CW7LAST6: str = (const int8_t *)"CV32CW7LAST6"; break; case ATON_DECUN_BFMT_CV32CW8LAST1: str = (const int8_t *)"CV32CW8LAST1"; break; case ATON_DECUN_BFMT_CV32CW8LAST2: str = (const int8_t *)"CV32CW8LAST2"; break; case ATON_DECUN_BFMT_CV32CW8LAST3: str = (const int8_t *)"CV32CW8LAST3"; break; case ATON_DECUN_BFMT_CV32CW8LAST4: str = (const int8_t *)"CV32CW8LAST4"; break; case ATON_DECUN_BFMT_CV32CW8LAST5: str = (const int8_t *)"CV32CW8LAST5"; break; case ATON_DECUN_BFMT_CV32CW8LAST6: str = (const int8_t *)"CV32CW8LAST6"; break; case ATON_DECUN_BFMT_CV32CW8LAST7: str = (const int8_t *)"CV32CW8LAST7"; break; case ATON_DECUN_BFMT_CV64CW2LAST1: str = (const int8_t *)"CV64CW2LAST1"; break; case ATON_DECUN_BFMT_CV64CW3LAST1: str = (const int8_t *)"CV64CW3LAST1"; break; case ATON_DECUN_BFMT_CV64CW3LAST2: str = (const int8_t *)"CV64CW3LAST2"; break; case ATON_DECUN_BFMT_CV64CW4LAST1: str = (const int8_t *)"CV64CW4LAST1"; break; case ATON_DECUN_BFMT_CV64CW4LAST2: str = (const int8_t *)"CV64CW4LAST2"; break; case ATON_DECUN_BFMT_CV64CW4LAST3: str = (const int8_t *)"CV64CW4LAST3"; break; case ATON_DECUN_BFMT_CV64CW5LAST1: str = (const int8_t *)"CV64CW5LAST1"; break; case ATON_DECUN_BFMT_CV64CW5LAST2: str = (const int8_t *)"CV64CW5LAST2"; break; case ATON_DECUN_BFMT_CV64CW5LAST3: str = (const int8_t *)"CV64CW5LAST3"; break; case ATON_DECUN_BFMT_CV64CW5LAST4: str = (const int8_t *)"CV64CW5LAST4"; break; case ATON_DECUN_BFMT_CV64CW6LAST1: str = (const int8_t *)"CV64CW6LAST1"; break; case ATON_DECUN_BFMT_CV64CW6LAST2: str = (const int8_t *)"CV64CW6LAST2"; break; case ATON_DECUN_BFMT_CV64CW6LAST3: str = (const int8_t *)"CV64CW6LAST3"; break; case ATON_DECUN_BFMT_CV64CW6LAST4: str = (const int8_t *)"CV64CW6LAST4"; break; case ATON_DECUN_BFMT_CV64CW6LAST5: str = (const int8_t *)"CV64CW6LAST5"; break; case ATON_DECUN_BFMT_CV64CW7LAST1: str = (const int8_t *)"CV64CW7LAST1"; break; case ATON_DECUN_BFMT_CV64CW7LAST2: str = (const int8_t *)"CV64CW7LAST2"; break; case ATON_DECUN_BFMT_CV64CW7LAST3: str = (const int8_t *)"CV64CW7LAST3"; break; case ATON_DECUN_BFMT_CV64CW7LAST4: str = (const int8_t *)"CV64CW7LAST4"; break; case ATON_DECUN_BFMT_CV64CW7LAST5: str = (const int8_t *)"CV64CW7LAST5"; break; case ATON_DECUN_BFMT_CV64CW7LAST6: str = (const int8_t *)"CV64CW7LAST6"; break; case ATON_DECUN_BFMT_CV64CW8LAST1: str = (const int8_t *)"CV64CW8LAST1"; break; case ATON_DECUN_BFMT_CV64CW8LAST2: str = (const int8_t *)"CV64CW8LAST2"; break; case ATON_DECUN_BFMT_CV64CW8LAST3: str = (const int8_t *)"CV64CW8LAST3"; break; case ATON_DECUN_BFMT_CV64CW8LAST4: str = (const int8_t *)"CV64CW8LAST4"; break; case ATON_DECUN_BFMT_CV64CW8LAST5: str = (const int8_t *)"CV64CW8LAST5"; break; case ATON_DECUN_BFMT_CV64CW8LAST6: str = (const int8_t *)"CV64CW8LAST6"; break; case ATON_DECUN_BFMT_CV64CW8LAST7: str = (const int8_t *)"CV64CW8LAST7"; break; case ATON_DECUN_BFMT_CV128CW2LAST1: str = (const int8_t *)"CV128CW2LAST1"; break; case ATON_DECUN_BFMT_CV128CW3LAST1: str = (const int8_t *)"CV128CW3LAST1"; break; case ATON_DECUN_BFMT_CV128CW3LAST2: str = (const int8_t *)"CV128CW3LAST2"; break; case ATON_DECUN_BFMT_CV128CW4LAST1: str = (const int8_t *)"CV128CW4LAST1"; break; case ATON_DECUN_BFMT_CV128CW4LAST2: str = (const int8_t *)"CV128CW4LAST2"; break; case ATON_DECUN_BFMT_CV128CW4LAST3: str = (const int8_t *)"CV128CW4LAST3"; break; case ATON_DECUN_BFMT_CV128CW5LAST1: str = (const int8_t *)"CV128CW5LAST1"; break; case ATON_DECUN_BFMT_CV128CW5LAST2: str = (const int8_t *)"CV128CW5LAST2"; break; case ATON_DECUN_BFMT_CV128CW5LAST3: str = (const int8_t *)"CV128CW5LAST3"; break; case ATON_DECUN_BFMT_CV128CW5LAST4: str = (const int8_t *)"CV128CW5LAST4"; break; case ATON_DECUN_BFMT_CV128CW6LAST1: str = (const int8_t *)"CV128CW6LAST1"; break; case ATON_DECUN_BFMT_CV128CW6LAST2: str = (const int8_t *)"CV128CW6LAST2"; break; case ATON_DECUN_BFMT_CV128CW6LAST3: str = (const int8_t *)"CV128CW6LAST3"; break; case ATON_DECUN_BFMT_CV128CW6LAST4: str = (const int8_t *)"CV128CW6LAST4"; break; case ATON_DECUN_BFMT_CV128CW6LAST5: str = (const int8_t *)"CV128CW6LAST5"; break; case ATON_DECUN_BFMT_CV128CW7LAST1: str = (const int8_t *)"CV128CW7LAST1"; break; case ATON_DECUN_BFMT_CV128CW7LAST2: str = (const int8_t *)"CV128CW7LAST2"; break; case ATON_DECUN_BFMT_CV128CW7LAST3: str = (const int8_t *)"CV128CW7LAST3"; break; case ATON_DECUN_BFMT_CV128CW7LAST4: str = (const int8_t *)"CV128CW7LAST4"; break; case ATON_DECUN_BFMT_CV128CW7LAST5: str = (const int8_t *)"CV128CW7LAST5"; break; case ATON_DECUN_BFMT_CV128CW7LAST6: str = (const int8_t *)"CV128CW7LAST6"; break; case ATON_DECUN_BFMT_CV128CW8LAST1: str = (const int8_t *)"CV128CW8LAST1"; break; case ATON_DECUN_BFMT_CV128CW8LAST2: str = (const int8_t *)"CV128CW8LAST2"; break; case ATON_DECUN_BFMT_CV128CW8LAST3: str = (const int8_t *)"CV128CW8LAST3"; break; case ATON_DECUN_BFMT_CV128CW8LAST4: str = (const int8_t *)"CV128CW8LAST4"; break; case ATON_DECUN_BFMT_CV128CW8LAST5: str = (const int8_t *)"CV128CW8LAST5"; break; case ATON_DECUN_BFMT_CV128CW8LAST6: str = (const int8_t *)"CV128CW8LAST6"; break; case ATON_DECUN_BFMT_CV128CW8LAST7: str = (const int8_t *)"CV128CW8LAST7"; break; case ATON_DECUN_BFMT_CV256CW2LAST1: str = (const int8_t *)"CV256CW2LAST1"; break; case ATON_DECUN_BFMT_CV256CW3LAST1: str = (const int8_t *)"CV256CW3LAST1"; break; case ATON_DECUN_BFMT_CV256CW3LAST2: str = (const int8_t *)"CV256CW3LAST2"; break; case ATON_DECUN_BFMT_CV256CW4LAST1: str = (const int8_t *)"CV256CW4LAST1"; break; case ATON_DECUN_BFMT_CV256CW4LAST2: str = (const int8_t *)"CV256CW4LAST2"; break; case ATON_DECUN_BFMT_CV256CW4LAST3: str = (const int8_t *)"CV256CW4LAST3"; break; case ATON_DECUN_BFMT_CV256CW5LAST1: str = (const int8_t *)"CV256CW5LAST1"; break; case ATON_DECUN_BFMT_CV256CW5LAST2: str = (const int8_t *)"CV256CW5LAST2"; break; case ATON_DECUN_BFMT_CV256CW5LAST3: str = (const int8_t *)"CV256CW5LAST3"; break; case ATON_DECUN_BFMT_CV256CW5LAST4: str = (const int8_t *)"CV256CW5LAST4"; break; case ATON_DECUN_BFMT_CV256CW6LAST1: str = (const int8_t *)"CV256CW6LAST1"; break; case ATON_DECUN_BFMT_CV256CW6LAST2: str = (const int8_t *)"CV256CW6LAST2"; break; case ATON_DECUN_BFMT_CV256CW6LAST3: str = (const int8_t *)"CV256CW6LAST3"; break; case ATON_DECUN_BFMT_CV256CW6LAST4: str = (const int8_t *)"CV256CW6LAST4"; break; case ATON_DECUN_BFMT_CV256CW6LAST5: str = (const int8_t *)"CV256CW6LAST5"; break; case ATON_DECUN_BFMT_CV256CW7LAST1: str = (const int8_t *)"CV256CW7LAST1"; break; case ATON_DECUN_BFMT_CV256CW7LAST2: str = (const int8_t *)"CV256CW7LAST2"; break; case ATON_DECUN_BFMT_CV256CW7LAST3: str = (const int8_t *)"CV256CW7LAST3"; break; case ATON_DECUN_BFMT_CV256CW7LAST4: str = (const int8_t *)"CV256CW7LAST4"; break; case ATON_DECUN_BFMT_CV256CW7LAST5: str = (const int8_t *)"CV256CW7LAST5"; break; case ATON_DECUN_BFMT_CV256CW7LAST6: str = (const int8_t *)"CV256CW7LAST6"; break; case ATON_DECUN_BFMT_CV256CW8LAST1: str = (const int8_t *)"CV256CW8LAST1"; break; case ATON_DECUN_BFMT_CV256CW8LAST2: str = (const int8_t *)"CV256CW8LAST2"; break; case ATON_DECUN_BFMT_CV256CW8LAST3: str = (const int8_t *)"CV256CW8LAST3"; break; case ATON_DECUN_BFMT_CV256CW8LAST4: str = (const int8_t *)"CV256CW8LAST4"; break; case ATON_DECUN_BFMT_CV256CW8LAST5: str = (const int8_t *)"CV256CW8LAST5"; break; case ATON_DECUN_BFMT_CV256CW8LAST6: str = (const int8_t *)"CV256CW8LAST6"; break; case ATON_DECUN_BFMT_CV256CW8LAST7: str = (const int8_t *)"CV256CW8LAST7"; break; default: break; } return str; } /** * Get the description of one of the values of the DECUN_BFMT set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the DECUN_BFMT set of enumerated values */ static inline const int8_t *ATON_DECUN_BFMT_GetDesc(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_DECUN_BFMT_CV1CW1LAST0: str = (const int8_t *)"CV1CW1LAST0"; break; case ATON_DECUN_BFMT_CV1CW2LAST0: str = (const int8_t *)"CV1CW2LAST0"; break; case ATON_DECUN_BFMT_CV1CW3LAST0: str = (const int8_t *)"CV1CW3LAST0"; break; case ATON_DECUN_BFMT_CV1CW4LAST0: str = (const int8_t *)"CV1CW4LAST0"; break; case ATON_DECUN_BFMT_CV1CW5LAST0: str = (const int8_t *)"CV1CW5LAST0"; break; case ATON_DECUN_BFMT_CV1CW6LAST0: str = (const int8_t *)"CV1CW6LAST0"; break; case ATON_DECUN_BFMT_CV1CW7LAST0: str = (const int8_t *)"CV1CW7LAST0"; break; case ATON_DECUN_BFMT_CV1CW8LAST0: str = (const int8_t *)"CV1CW8LAST0"; break; case ATON_DECUN_BFMT_CV1CW2LAST1: str = (const int8_t *)"CV1CW2LAST1"; break; case ATON_DECUN_BFMT_CV1CW3LAST1: str = (const int8_t *)"CV1CW3LAST1"; break; case ATON_DECUN_BFMT_CV1CW4LAST1: str = (const int8_t *)"CV1CW4LAST1"; break; case ATON_DECUN_BFMT_CV1CW5LAST1: str = (const int8_t *)"CV1CW5LAST1"; break; case ATON_DECUN_BFMT_CV1CW6LAST1: str = (const int8_t *)"CV1CW6LAST1"; break; case ATON_DECUN_BFMT_CV1CW7LAST1: str = (const int8_t *)"CV1CW7LAST1"; break; case ATON_DECUN_BFMT_CV1CW8LAST1: str = (const int8_t *)"CV1CW8LAST1"; break; case ATON_DECUN_BFMT_CV1CW3LAST2: str = (const int8_t *)"CV1CW3LAST2"; break; case ATON_DECUN_BFMT_CV1CW4LAST2: str = (const int8_t *)"CV1CW4LAST2"; break; case ATON_DECUN_BFMT_CV1CW5LAST2: str = (const int8_t *)"CV1CW5LAST2"; break; case ATON_DECUN_BFMT_CV1CW6LAST2: str = (const int8_t *)"CV1CW6LAST2"; break; case ATON_DECUN_BFMT_CV1CW7LAST2: str = (const int8_t *)"CV1CW7LAST2"; break; case ATON_DECUN_BFMT_CV1CW8LAST2: str = (const int8_t *)"CV1CW8LAST2"; break; case ATON_DECUN_BFMT_CV1CW4LAST3: str = (const int8_t *)"CV1CW4LAST3"; break; case ATON_DECUN_BFMT_CV1CW5LAST3: str = (const int8_t *)"CV1CW5LAST3"; break; case ATON_DECUN_BFMT_CV1CW6LAST3: str = (const int8_t *)"CV1CW6LAST3"; break; case ATON_DECUN_BFMT_CV1CW7LAST3: str = (const int8_t *)"CV1CW7LAST3"; break; case ATON_DECUN_BFMT_CV1CW8LAST3: str = (const int8_t *)"CV1CW8LAST3"; break; case ATON_DECUN_BFMT_CV1CW5LAST4: str = (const int8_t *)"CV1CW5LAST4"; break; case ATON_DECUN_BFMT_CV1CW6LAST4: str = (const int8_t *)"CV1CW6LAST4"; break; case ATON_DECUN_BFMT_CV1CW7LAST4: str = (const int8_t *)"CV1CW7LAST4"; break; case ATON_DECUN_BFMT_CV1CW8LAST4: str = (const int8_t *)"CV1CW8LAST4"; break; case ATON_DECUN_BFMT_CV1CW6LAST5: str = (const int8_t *)"CV1CW6LAST5"; break; case ATON_DECUN_BFMT_CV1CW7LAST5: str = (const int8_t *)"CV1CW7LAST5"; break; case ATON_DECUN_BFMT_CV1CW8LAST5: str = (const int8_t *)"CV1CW8LAST5"; break; case ATON_DECUN_BFMT_CV1CW7LAST6: str = (const int8_t *)"CV1CW7LAST6"; break; case ATON_DECUN_BFMT_CV1CW8LAST6: str = (const int8_t *)"CV1CW8LAST6"; break; case ATON_DECUN_BFMT_CV1CW8LAST7: str = (const int8_t *)"CV1CW8LAST7"; break; case ATON_DECUN_BFMT_CV2CW1LAST0: str = (const int8_t *)"CV2CW1LAST0"; break; case ATON_DECUN_BFMT_CV2CW2LAST0: str = (const int8_t *)"CV2CW2LAST0"; break; case ATON_DECUN_BFMT_CV2CW3LAST0: str = (const int8_t *)"CV2CW3LAST0"; break; case ATON_DECUN_BFMT_CV2CW4LAST0: str = (const int8_t *)"CV2CW4LAST0"; break; case ATON_DECUN_BFMT_CV2CW5LAST0: str = (const int8_t *)"CV2CW5LAST0"; break; case ATON_DECUN_BFMT_CV2CW6LAST0: str = (const int8_t *)"CV2CW6LAST0"; break; case ATON_DECUN_BFMT_CV2CW7LAST0: str = (const int8_t *)"CV2CW7LAST0"; break; case ATON_DECUN_BFMT_CV2CW8LAST0: str = (const int8_t *)"CV2CW8LAST0"; break; case ATON_DECUN_BFMT_CV2CW2LAST1: str = (const int8_t *)"CV2CW2LAST1"; break; case ATON_DECUN_BFMT_CV2CW3LAST1: str = (const int8_t *)"CV2CW3LAST1"; break; case ATON_DECUN_BFMT_CV2CW4LAST1: str = (const int8_t *)"CV2CW4LAST1"; break; case ATON_DECUN_BFMT_CV2CW5LAST1: str = (const int8_t *)"CV2CW5LAST1"; break; case ATON_DECUN_BFMT_CV2CW6LAST1: str = (const int8_t *)"CV2CW6LAST1"; break; case ATON_DECUN_BFMT_CV2CW7LAST1: str = (const int8_t *)"CV2CW7LAST1"; break; case ATON_DECUN_BFMT_CV2CW8LAST1: str = (const int8_t *)"CV2CW8LAST1"; break; case ATON_DECUN_BFMT_CV2CW3LAST2: str = (const int8_t *)"CV2CW3LAST2"; break; case ATON_DECUN_BFMT_CV2CW4LAST2: str = (const int8_t *)"CV2CW4LAST2"; break; case ATON_DECUN_BFMT_CV2CW5LAST2: str = (const int8_t *)"CV2CW5LAST2"; break; case ATON_DECUN_BFMT_CV2CW6LAST2: str = (const int8_t *)"CV2CW6LAST2"; break; case ATON_DECUN_BFMT_CV2CW7LAST2: str = (const int8_t *)"CV2CW7LAST2"; break; case ATON_DECUN_BFMT_CV2CW8LAST2: str = (const int8_t *)"CV2CW8LAST2"; break; case ATON_DECUN_BFMT_CV2CW4LAST3: str = (const int8_t *)"CV2CW4LAST3"; break; case ATON_DECUN_BFMT_CV2CW5LAST3: str = (const int8_t *)"CV2CW5LAST3"; break; case ATON_DECUN_BFMT_CV2CW6LAST3: str = (const int8_t *)"CV2CW6LAST3"; break; case ATON_DECUN_BFMT_CV2CW7LAST3: str = (const int8_t *)"CV2CW7LAST3"; break; case ATON_DECUN_BFMT_CV2CW8LAST3: str = (const int8_t *)"CV2CW8LAST3"; break; case ATON_DECUN_BFMT_CV2CW5LAST4: str = (const int8_t *)"CV2CW5LAST4"; break; case ATON_DECUN_BFMT_CV2CW6LAST4: str = (const int8_t *)"CV2CW6LAST4"; break; case ATON_DECUN_BFMT_CV2CW7LAST4: str = (const int8_t *)"CV2CW7LAST4"; break; case ATON_DECUN_BFMT_CV2CW8LAST4: str = (const int8_t *)"CV2CW8LAST4"; break; case ATON_DECUN_BFMT_CV2CW6LAST5: str = (const int8_t *)"CV2CW6LAST5"; break; case ATON_DECUN_BFMT_CV2CW7LAST5: str = (const int8_t *)"CV2CW7LAST5"; break; case ATON_DECUN_BFMT_CV2CW8LAST5: str = (const int8_t *)"CV2CW8LAST5"; break; case ATON_DECUN_BFMT_CV2CW7LAST6: str = (const int8_t *)"CV2CW7LAST6"; break; case ATON_DECUN_BFMT_CV2CW8LAST6: str = (const int8_t *)"CV2CW8LAST6"; break; case ATON_DECUN_BFMT_CV2CW8LAST7: str = (const int8_t *)"CV2CW8LAST7"; break; case ATON_DECUN_BFMT_CV4CW1LAST0: str = (const int8_t *)"CV4CW1LAST0"; break; case ATON_DECUN_BFMT_CV4CW2LAST0: str = (const int8_t *)"CV4CW2LAST0"; break; case ATON_DECUN_BFMT_CV4CW3LAST0: str = (const int8_t *)"CV4CW3LAST0"; break; case ATON_DECUN_BFMT_CV4CW4LAST0: str = (const int8_t *)"CV4CW4LAST0"; break; case ATON_DECUN_BFMT_CV4CW5LAST0: str = (const int8_t *)"CV4CW5LAST0"; break; case ATON_DECUN_BFMT_CV4CW6LAST0: str = (const int8_t *)"CV4CW6LAST0"; break; case ATON_DECUN_BFMT_CV4CW7LAST0: str = (const int8_t *)"CV4CW7LAST0"; break; case ATON_DECUN_BFMT_CV4CW8LAST0: str = (const int8_t *)"CV4CW8LAST0"; break; case ATON_DECUN_BFMT_CV4CW2LAST1: str = (const int8_t *)"CV4CW2LAST1"; break; case ATON_DECUN_BFMT_CV4CW3LAST1: str = (const int8_t *)"CV4CW3LAST1"; break; case ATON_DECUN_BFMT_CV4CW4LAST1: str = (const int8_t *)"CV4CW4LAST1"; break; case ATON_DECUN_BFMT_CV4CW5LAST1: str = (const int8_t *)"CV4CW5LAST1"; break; case ATON_DECUN_BFMT_CV4CW6LAST1: str = (const int8_t *)"CV4CW6LAST1"; break; case ATON_DECUN_BFMT_CV4CW7LAST1: str = (const int8_t *)"CV4CW7LAST1"; break; case ATON_DECUN_BFMT_CV4CW8LAST1: str = (const int8_t *)"CV4CW8LAST1"; break; case ATON_DECUN_BFMT_CV4CW3LAST2: str = (const int8_t *)"CV4CW3LAST2"; break; case ATON_DECUN_BFMT_CV4CW4LAST2: str = (const int8_t *)"CV4CW4LAST2"; break; case ATON_DECUN_BFMT_CV4CW5LAST2: str = (const int8_t *)"CV4CW5LAST2"; break; case ATON_DECUN_BFMT_CV4CW6LAST2: str = (const int8_t *)"CV4CW6LAST2"; break; case ATON_DECUN_BFMT_CV4CW7LAST2: str = (const int8_t *)"CV4CW7LAST2"; break; case ATON_DECUN_BFMT_CV4CW8LAST2: str = (const int8_t *)"CV4CW8LAST2"; break; case ATON_DECUN_BFMT_CV4CW4LAST3: str = (const int8_t *)"CV4CW4LAST3"; break; case ATON_DECUN_BFMT_CV4CW5LAST3: str = (const int8_t *)"CV4CW5LAST3"; break; case ATON_DECUN_BFMT_CV4CW6LAST3: str = (const int8_t *)"CV4CW6LAST3"; break; case ATON_DECUN_BFMT_CV4CW7LAST3: str = (const int8_t *)"CV4CW7LAST3"; break; case ATON_DECUN_BFMT_CV4CW8LAST3: str = (const int8_t *)"CV4CW8LAST3"; break; case ATON_DECUN_BFMT_CV4CW5LAST4: str = (const int8_t *)"CV4CW5LAST4"; break; case ATON_DECUN_BFMT_CV4CW6LAST4: str = (const int8_t *)"CV4CW6LAST4"; break; case ATON_DECUN_BFMT_CV4CW7LAST4: str = (const int8_t *)"CV4CW7LAST4"; break; case ATON_DECUN_BFMT_CV4CW8LAST4: str = (const int8_t *)"CV4CW8LAST4"; break; case ATON_DECUN_BFMT_CV4CW6LAST5: str = (const int8_t *)"CV4CW6LAST5"; break; case ATON_DECUN_BFMT_CV4CW7LAST5: str = (const int8_t *)"CV4CW7LAST5"; break; case ATON_DECUN_BFMT_CV4CW8LAST5: str = (const int8_t *)"CV4CW8LAST5"; break; case ATON_DECUN_BFMT_CV4CW7LAST6: str = (const int8_t *)"CV4CW7LAST6"; break; case ATON_DECUN_BFMT_CV4CW8LAST6: str = (const int8_t *)"CV4CW8LAST6"; break; case ATON_DECUN_BFMT_CV4CW8LAST7: str = (const int8_t *)"CV4CW8LAST7"; break; case ATON_DECUN_BFMT_CV8CW1LAST0: str = (const int8_t *)"CV8CW1LAST0"; break; case ATON_DECUN_BFMT_CV8CW2LAST0: str = (const int8_t *)"CV8CW2LAST0"; break; case ATON_DECUN_BFMT_CV8CW3LAST0: str = (const int8_t *)"CV8CW3LAST0"; break; case ATON_DECUN_BFMT_CV8CW4LAST0: str = (const int8_t *)"CV8CW4LAST0"; break; case ATON_DECUN_BFMT_CV8CW5LAST0: str = (const int8_t *)"CV8CW5LAST0"; break; case ATON_DECUN_BFMT_CV8CW6LAST0: str = (const int8_t *)"CV8CW6LAST0"; break; case ATON_DECUN_BFMT_CV8CW7LAST0: str = (const int8_t *)"CV8CW7LAST0"; break; case ATON_DECUN_BFMT_CV8CW8LAST0: str = (const int8_t *)"CV8CW8LAST0"; break; case ATON_DECUN_BFMT_CV8CW2LAST1: str = (const int8_t *)"CV8CW2LAST1"; break; case ATON_DECUN_BFMT_CV8CW3LAST1: str = (const int8_t *)"CV8CW3LAST1"; break; case ATON_DECUN_BFMT_CV8CW4LAST1: str = (const int8_t *)"CV8CW4LAST1"; break; case ATON_DECUN_BFMT_CV8CW5LAST1: str = (const int8_t *)"CV8CW5LAST1"; break; case ATON_DECUN_BFMT_CV8CW6LAST1: str = (const int8_t *)"CV8CW6LAST1"; break; case ATON_DECUN_BFMT_CV8CW7LAST1: str = (const int8_t *)"CV8CW7LAST1"; break; case ATON_DECUN_BFMT_CV8CW8LAST1: str = (const int8_t *)"CV8CW8LAST1"; break; case ATON_DECUN_BFMT_CV8CW3LAST2: str = (const int8_t *)"CV8CW3LAST2"; break; case ATON_DECUN_BFMT_CV8CW4LAST2: str = (const int8_t *)"CV8CW4LAST2"; break; case ATON_DECUN_BFMT_CV8CW5LAST2: str = (const int8_t *)"CV8CW5LAST2"; break; case ATON_DECUN_BFMT_CV8CW6LAST2: str = (const int8_t *)"CV8CW6LAST2"; break; case ATON_DECUN_BFMT_CV8CW7LAST2: str = (const int8_t *)"CV8CW7LAST2"; break; case ATON_DECUN_BFMT_CV8CW8LAST2: str = (const int8_t *)"CV8CW8LAST2"; break; case ATON_DECUN_BFMT_CV8CW4LAST3: str = (const int8_t *)"CV8CW4LAST3"; break; case ATON_DECUN_BFMT_CV8CW5LAST3: str = (const int8_t *)"CV8CW5LAST3"; break; case ATON_DECUN_BFMT_CV8CW6LAST3: str = (const int8_t *)"CV8CW6LAST3"; break; case ATON_DECUN_BFMT_CV8CW7LAST3: str = (const int8_t *)"CV8CW7LAST3"; break; case ATON_DECUN_BFMT_CV8CW8LAST3: str = (const int8_t *)"CV8CW8LAST3"; break; case ATON_DECUN_BFMT_CV8CW5LAST4: str = (const int8_t *)"CV8CW5LAST4"; break; case ATON_DECUN_BFMT_CV8CW6LAST4: str = (const int8_t *)"CV8CW6LAST4"; break; case ATON_DECUN_BFMT_CV8CW7LAST4: str = (const int8_t *)"CV8CW7LAST4"; break; case ATON_DECUN_BFMT_CV8CW8LAST4: str = (const int8_t *)"CV8CW8LAST4"; break; case ATON_DECUN_BFMT_CV8CW6LAST5: str = (const int8_t *)"CV8CW6LAST5"; break; case ATON_DECUN_BFMT_CV8CW7LAST5: str = (const int8_t *)"CV8CW7LAST5"; break; case ATON_DECUN_BFMT_CV8CW8LAST5: str = (const int8_t *)"CV8CW8LAST5"; break; case ATON_DECUN_BFMT_CV8CW7LAST6: str = (const int8_t *)"CV8CW7LAST6"; break; case ATON_DECUN_BFMT_CV8CW8LAST6: str = (const int8_t *)"CV8CW8LAST6"; break; case ATON_DECUN_BFMT_CV8CW8LAST7: str = (const int8_t *)"CV8CW8LAST7"; break; case ATON_DECUN_BFMT_CV16CW1LAST0: str = (const int8_t *)"CV16CW1LAST0"; break; case ATON_DECUN_BFMT_CV16CW2LAST0: str = (const int8_t *)"CV16CW2LAST0"; break; case ATON_DECUN_BFMT_CV16CW3LAST0: str = (const int8_t *)"CV16CW3LAST0"; break; case ATON_DECUN_BFMT_CV16CW4LAST0: str = (const int8_t *)"CV16CW4LAST0"; break; case ATON_DECUN_BFMT_CV16CW5LAST0: str = (const int8_t *)"CV16CW5LAST0"; break; case ATON_DECUN_BFMT_CV16CW6LAST0: str = (const int8_t *)"CV16CW6LAST0"; break; case ATON_DECUN_BFMT_CV16CW7LAST0: str = (const int8_t *)"CV16CW7LAST0"; break; case ATON_DECUN_BFMT_CV16CW8LAST0: str = (const int8_t *)"CV16CW8LAST0"; break; case ATON_DECUN_BFMT_CV32CW1LAST0: str = (const int8_t *)"CV32CW1LAST0"; break; case ATON_DECUN_BFMT_CV32CW2LAST0: str = (const int8_t *)"CV32CW2LAST0"; break; case ATON_DECUN_BFMT_CV32CW3LAST0: str = (const int8_t *)"CV32CW3LAST0"; break; case ATON_DECUN_BFMT_CV32CW4LAST0: str = (const int8_t *)"CV32CW4LAST0"; break; case ATON_DECUN_BFMT_CV32CW5LAST0: str = (const int8_t *)"CV32CW5LAST0"; break; case ATON_DECUN_BFMT_CV32CW6LAST0: str = (const int8_t *)"CV32CW6LAST0"; break; case ATON_DECUN_BFMT_CV32CW7LAST0: str = (const int8_t *)"CV32CW7LAST0"; break; case ATON_DECUN_BFMT_CV32CW8LAST0: str = (const int8_t *)"CV32CW8LAST0"; break; case ATON_DECUN_BFMT_CV64CW1LAST0: str = (const int8_t *)"CV64CW1LAST0"; break; case ATON_DECUN_BFMT_CV64CW2LAST0: str = (const int8_t *)"CV64CW2LAST0"; break; case ATON_DECUN_BFMT_CV64CW3LAST0: str = (const int8_t *)"CV64CW3LAST0"; break; case ATON_DECUN_BFMT_CV64CW4LAST0: str = (const int8_t *)"CV64CW4LAST0"; break; case ATON_DECUN_BFMT_CV64CW5LAST0: str = (const int8_t *)"CV64CW5LAST0"; break; case ATON_DECUN_BFMT_CV64CW6LAST0: str = (const int8_t *)"CV64CW6LAST0"; break; case ATON_DECUN_BFMT_CV64CW7LAST0: str = (const int8_t *)"CV64CW7LAST0"; break; case ATON_DECUN_BFMT_CV64CW8LAST0: str = (const int8_t *)"CV64CW8LAST0"; break; case ATON_DECUN_BFMT_CV128CW1LAST0: str = (const int8_t *)"CV128CW1LAST0"; break; case ATON_DECUN_BFMT_CV128CW2LAST0: str = (const int8_t *)"CV128CW2LAST0"; break; case ATON_DECUN_BFMT_CV128CW3LAST0: str = (const int8_t *)"CV128CW3LAST0"; break; case ATON_DECUN_BFMT_CV128CW4LAST0: str = (const int8_t *)"CV128CW4LAST0"; break; case ATON_DECUN_BFMT_CV128CW5LAST0: str = (const int8_t *)"CV128CW5LAST0"; break; case ATON_DECUN_BFMT_CV128CW6LAST0: str = (const int8_t *)"CV128CW6LAST0"; break; case ATON_DECUN_BFMT_CV128CW7LAST0: str = (const int8_t *)"CV128CW7LAST0"; break; case ATON_DECUN_BFMT_CV128CW8LAST0: str = (const int8_t *)"CV128CW8LAST0"; break; case ATON_DECUN_BFMT_CV256CW1LAST0: str = (const int8_t *)"CV256CW1LAST0"; break; case ATON_DECUN_BFMT_CV256CW2LAST0: str = (const int8_t *)"CV256CW2LAST0"; break; case ATON_DECUN_BFMT_CV256CW3LAST0: str = (const int8_t *)"CV256CW3LAST0"; break; case ATON_DECUN_BFMT_CV256CW4LAST0: str = (const int8_t *)"CV256CW4LAST0"; break; case ATON_DECUN_BFMT_CV256CW5LAST0: str = (const int8_t *)"CV256CW5LAST0"; break; case ATON_DECUN_BFMT_CV256CW6LAST0: str = (const int8_t *)"CV256CW6LAST0"; break; case ATON_DECUN_BFMT_CV256CW7LAST0: str = (const int8_t *)"CV256CW7LAST0"; break; case ATON_DECUN_BFMT_CV256CW8LAST0: str = (const int8_t *)"CV256CW8LAST0"; break; case ATON_DECUN_BFMT_CV16CW2LAST1: str = (const int8_t *)"CV16CW2LAST1"; break; case ATON_DECUN_BFMT_CV16CW3LAST1: str = (const int8_t *)"CV16CW3LAST1"; break; case ATON_DECUN_BFMT_CV16CW3LAST2: str = (const int8_t *)"CV16CW3LAST2"; break; case ATON_DECUN_BFMT_CV16CW4LAST1: str = (const int8_t *)"CV16CW4LAST1"; break; case ATON_DECUN_BFMT_CV16CW4LAST2: str = (const int8_t *)"CV16CW4LAST2"; break; case ATON_DECUN_BFMT_CV16CW4LAST3: str = (const int8_t *)"CV16CW4LAST3"; break; case ATON_DECUN_BFMT_CV16CW5LAST1: str = (const int8_t *)"CV16CW5LAST1"; break; case ATON_DECUN_BFMT_CV16CW5LAST2: str = (const int8_t *)"CV16CW5LAST2"; break; case ATON_DECUN_BFMT_CV16CW5LAST3: str = (const int8_t *)"CV16CW5LAST3"; break; case ATON_DECUN_BFMT_CV16CW5LAST4: str = (const int8_t *)"CV16CW5LAST4"; break; case ATON_DECUN_BFMT_CV16CW6LAST1: str = (const int8_t *)"CV16CW6LAST1"; break; case ATON_DECUN_BFMT_CV16CW6LAST2: str = (const int8_t *)"CV16CW6LAST2"; break; case ATON_DECUN_BFMT_CV16CW6LAST3: str = (const int8_t *)"CV16CW6LAST3"; break; case ATON_DECUN_BFMT_CV16CW6LAST4: str = (const int8_t *)"CV16CW6LAST4"; break; case ATON_DECUN_BFMT_CV16CW6LAST5: str = (const int8_t *)"CV16CW6LAST5"; break; case ATON_DECUN_BFMT_CV16CW7LAST1: str = (const int8_t *)"CV16CW7LAST1"; break; case ATON_DECUN_BFMT_CV16CW7LAST2: str = (const int8_t *)"CV16CW7LAST2"; break; case ATON_DECUN_BFMT_CV16CW7LAST3: str = (const int8_t *)"CV16CW7LAST3"; break; case ATON_DECUN_BFMT_CV16CW7LAST4: str = (const int8_t *)"CV16CW7LAST4"; break; case ATON_DECUN_BFMT_CV16CW7LAST5: str = (const int8_t *)"CV16CW7LAST5"; break; case ATON_DECUN_BFMT_CV16CW7LAST6: str = (const int8_t *)"CV16CW7LAST6"; break; case ATON_DECUN_BFMT_CV16CW8LAST1: str = (const int8_t *)"CV16CW8LAST1"; break; case ATON_DECUN_BFMT_CV16CW8LAST2: str = (const int8_t *)"CV16CW8LAST2"; break; case ATON_DECUN_BFMT_CV16CW8LAST3: str = (const int8_t *)"CV16CW8LAST3"; break; case ATON_DECUN_BFMT_CV16CW8LAST4: str = (const int8_t *)"CV16CW8LAST4"; break; case ATON_DECUN_BFMT_CV16CW8LAST5: str = (const int8_t *)"CV16CW8LAST5"; break; case ATON_DECUN_BFMT_CV16CW8LAST6: str = (const int8_t *)"CV16CW8LAST6"; break; case ATON_DECUN_BFMT_CV16CW8LAST7: str = (const int8_t *)"CV16CW8LAST7"; break; case ATON_DECUN_BFMT_CV32CW2LAST1: str = (const int8_t *)"CV32CW2LAST1"; break; case ATON_DECUN_BFMT_CV32CW3LAST1: str = (const int8_t *)"CV32CW3LAST1"; break; case ATON_DECUN_BFMT_CV32CW3LAST2: str = (const int8_t *)"CV32CW3LAST2"; break; case ATON_DECUN_BFMT_CV32CW4LAST1: str = (const int8_t *)"CV32CW4LAST1"; break; case ATON_DECUN_BFMT_CV32CW4LAST2: str = (const int8_t *)"CV32CW4LAST2"; break; case ATON_DECUN_BFMT_CV32CW4LAST3: str = (const int8_t *)"CV32CW4LAST3"; break; case ATON_DECUN_BFMT_CV32CW5LAST1: str = (const int8_t *)"CV32CW5LAST1"; break; case ATON_DECUN_BFMT_CV32CW5LAST2: str = (const int8_t *)"CV32CW5LAST2"; break; case ATON_DECUN_BFMT_CV32CW5LAST3: str = (const int8_t *)"CV32CW5LAST3"; break; case ATON_DECUN_BFMT_CV32CW5LAST4: str = (const int8_t *)"CV32CW5LAST4"; break; case ATON_DECUN_BFMT_CV32CW6LAST1: str = (const int8_t *)"CV32CW6LAST1"; break; case ATON_DECUN_BFMT_CV32CW6LAST2: str = (const int8_t *)"CV32CW6LAST2"; break; case ATON_DECUN_BFMT_CV32CW6LAST3: str = (const int8_t *)"CV32CW6LAST3"; break; case ATON_DECUN_BFMT_CV32CW6LAST4: str = (const int8_t *)"CV32CW6LAST4"; break; case ATON_DECUN_BFMT_CV32CW6LAST5: str = (const int8_t *)"CV32CW6LAST5"; break; case ATON_DECUN_BFMT_CV32CW7LAST1: str = (const int8_t *)"CV32CW7LAST1"; break; case ATON_DECUN_BFMT_CV32CW7LAST2: str = (const int8_t *)"CV32CW7LAST2"; break; case ATON_DECUN_BFMT_CV32CW7LAST3: str = (const int8_t *)"CV32CW7LAST3"; break; case ATON_DECUN_BFMT_CV32CW7LAST4: str = (const int8_t *)"CV32CW7LAST4"; break; case ATON_DECUN_BFMT_CV32CW7LAST5: str = (const int8_t *)"CV32CW7LAST5"; break; case ATON_DECUN_BFMT_CV32CW7LAST6: str = (const int8_t *)"CV32CW7LAST6"; break; case ATON_DECUN_BFMT_CV32CW8LAST1: str = (const int8_t *)"CV32CW8LAST1"; break; case ATON_DECUN_BFMT_CV32CW8LAST2: str = (const int8_t *)"CV32CW8LAST2"; break; case ATON_DECUN_BFMT_CV32CW8LAST3: str = (const int8_t *)"CV32CW8LAST3"; break; case ATON_DECUN_BFMT_CV32CW8LAST4: str = (const int8_t *)"CV32CW8LAST4"; break; case ATON_DECUN_BFMT_CV32CW8LAST5: str = (const int8_t *)"CV32CW8LAST5"; break; case ATON_DECUN_BFMT_CV32CW8LAST6: str = (const int8_t *)"CV32CW8LAST6"; break; case ATON_DECUN_BFMT_CV32CW8LAST7: str = (const int8_t *)"CV32CW8LAST7"; break; case ATON_DECUN_BFMT_CV64CW2LAST1: str = (const int8_t *)"CV64CW2LAST1"; break; case ATON_DECUN_BFMT_CV64CW3LAST1: str = (const int8_t *)"CV64CW3LAST1"; break; case ATON_DECUN_BFMT_CV64CW3LAST2: str = (const int8_t *)"CV64CW3LAST2"; break; case ATON_DECUN_BFMT_CV64CW4LAST1: str = (const int8_t *)"CV64CW4LAST1"; break; case ATON_DECUN_BFMT_CV64CW4LAST2: str = (const int8_t *)"CV64CW4LAST2"; break; case ATON_DECUN_BFMT_CV64CW4LAST3: str = (const int8_t *)"CV64CW4LAST3"; break; case ATON_DECUN_BFMT_CV64CW5LAST1: str = (const int8_t *)"CV64CW5LAST1"; break; case ATON_DECUN_BFMT_CV64CW5LAST2: str = (const int8_t *)"CV64CW5LAST2"; break; case ATON_DECUN_BFMT_CV64CW5LAST3: str = (const int8_t *)"CV64CW5LAST3"; break; case ATON_DECUN_BFMT_CV64CW5LAST4: str = (const int8_t *)"CV64CW5LAST4"; break; case ATON_DECUN_BFMT_CV64CW6LAST1: str = (const int8_t *)"CV64CW6LAST1"; break; case ATON_DECUN_BFMT_CV64CW6LAST2: str = (const int8_t *)"CV64CW6LAST2"; break; case ATON_DECUN_BFMT_CV64CW6LAST3: str = (const int8_t *)"CV64CW6LAST3"; break; case ATON_DECUN_BFMT_CV64CW6LAST4: str = (const int8_t *)"CV64CW6LAST4"; break; case ATON_DECUN_BFMT_CV64CW6LAST5: str = (const int8_t *)"CV64CW6LAST5"; break; case ATON_DECUN_BFMT_CV64CW7LAST1: str = (const int8_t *)"CV64CW7LAST1"; break; case ATON_DECUN_BFMT_CV64CW7LAST2: str = (const int8_t *)"CV64CW7LAST2"; break; case ATON_DECUN_BFMT_CV64CW7LAST3: str = (const int8_t *)"CV64CW7LAST3"; break; case ATON_DECUN_BFMT_CV64CW7LAST4: str = (const int8_t *)"CV64CW7LAST4"; break; case ATON_DECUN_BFMT_CV64CW7LAST5: str = (const int8_t *)"CV64CW7LAST5"; break; case ATON_DECUN_BFMT_CV64CW7LAST6: str = (const int8_t *)"CV64CW7LAST6"; break; case ATON_DECUN_BFMT_CV64CW8LAST1: str = (const int8_t *)"CV64CW8LAST1"; break; case ATON_DECUN_BFMT_CV64CW8LAST2: str = (const int8_t *)"CV64CW8LAST2"; break; case ATON_DECUN_BFMT_CV64CW8LAST3: str = (const int8_t *)"CV64CW8LAST3"; break; case ATON_DECUN_BFMT_CV64CW8LAST4: str = (const int8_t *)"CV64CW8LAST4"; break; case ATON_DECUN_BFMT_CV64CW8LAST5: str = (const int8_t *)"CV64CW8LAST5"; break; case ATON_DECUN_BFMT_CV64CW8LAST6: str = (const int8_t *)"CV64CW8LAST6"; break; case ATON_DECUN_BFMT_CV64CW8LAST7: str = (const int8_t *)"CV64CW8LAST7"; break; case ATON_DECUN_BFMT_CV128CW2LAST1: str = (const int8_t *)"CV128CW2LAST1"; break; case ATON_DECUN_BFMT_CV128CW3LAST1: str = (const int8_t *)"CV128CW3LAST1"; break; case ATON_DECUN_BFMT_CV128CW3LAST2: str = (const int8_t *)"CV128CW3LAST2"; break; case ATON_DECUN_BFMT_CV128CW4LAST1: str = (const int8_t *)"CV128CW4LAST1"; break; case ATON_DECUN_BFMT_CV128CW4LAST2: str = (const int8_t *)"CV128CW4LAST2"; break; case ATON_DECUN_BFMT_CV128CW4LAST3: str = (const int8_t *)"CV128CW4LAST3"; break; case ATON_DECUN_BFMT_CV128CW5LAST1: str = (const int8_t *)"CV128CW5LAST1"; break; case ATON_DECUN_BFMT_CV128CW5LAST2: str = (const int8_t *)"CV128CW5LAST2"; break; case ATON_DECUN_BFMT_CV128CW5LAST3: str = (const int8_t *)"CV128CW5LAST3"; break; case ATON_DECUN_BFMT_CV128CW5LAST4: str = (const int8_t *)"CV128CW5LAST4"; break; case ATON_DECUN_BFMT_CV128CW6LAST1: str = (const int8_t *)"CV128CW6LAST1"; break; case ATON_DECUN_BFMT_CV128CW6LAST2: str = (const int8_t *)"CV128CW6LAST2"; break; case ATON_DECUN_BFMT_CV128CW6LAST3: str = (const int8_t *)"CV128CW6LAST3"; break; case ATON_DECUN_BFMT_CV128CW6LAST4: str = (const int8_t *)"CV128CW6LAST4"; break; case ATON_DECUN_BFMT_CV128CW6LAST5: str = (const int8_t *)"CV128CW6LAST5"; break; case ATON_DECUN_BFMT_CV128CW7LAST1: str = (const int8_t *)"CV128CW7LAST1"; break; case ATON_DECUN_BFMT_CV128CW7LAST2: str = (const int8_t *)"CV128CW7LAST2"; break; case ATON_DECUN_BFMT_CV128CW7LAST3: str = (const int8_t *)"CV128CW7LAST3"; break; case ATON_DECUN_BFMT_CV128CW7LAST4: str = (const int8_t *)"CV128CW7LAST4"; break; case ATON_DECUN_BFMT_CV128CW7LAST5: str = (const int8_t *)"CV128CW7LAST5"; break; case ATON_DECUN_BFMT_CV128CW7LAST6: str = (const int8_t *)"CV128CW7LAST6"; break; case ATON_DECUN_BFMT_CV128CW8LAST1: str = (const int8_t *)"CV128CW8LAST1"; break; case ATON_DECUN_BFMT_CV128CW8LAST2: str = (const int8_t *)"CV128CW8LAST2"; break; case ATON_DECUN_BFMT_CV128CW8LAST3: str = (const int8_t *)"CV128CW8LAST3"; break; case ATON_DECUN_BFMT_CV128CW8LAST4: str = (const int8_t *)"CV128CW8LAST4"; break; case ATON_DECUN_BFMT_CV128CW8LAST5: str = (const int8_t *)"CV128CW8LAST5"; break; case ATON_DECUN_BFMT_CV128CW8LAST6: str = (const int8_t *)"CV128CW8LAST6"; break; case ATON_DECUN_BFMT_CV128CW8LAST7: str = (const int8_t *)"CV128CW8LAST7"; break; case ATON_DECUN_BFMT_CV256CW2LAST1: str = (const int8_t *)"CV256CW2LAST1"; break; case ATON_DECUN_BFMT_CV256CW3LAST1: str = (const int8_t *)"CV256CW3LAST1"; break; case ATON_DECUN_BFMT_CV256CW3LAST2: str = (const int8_t *)"CV256CW3LAST2"; break; case ATON_DECUN_BFMT_CV256CW4LAST1: str = (const int8_t *)"CV256CW4LAST1"; break; case ATON_DECUN_BFMT_CV256CW4LAST2: str = (const int8_t *)"CV256CW4LAST2"; break; case ATON_DECUN_BFMT_CV256CW4LAST3: str = (const int8_t *)"CV256CW4LAST3"; break; case ATON_DECUN_BFMT_CV256CW5LAST1: str = (const int8_t *)"CV256CW5LAST1"; break; case ATON_DECUN_BFMT_CV256CW5LAST2: str = (const int8_t *)"CV256CW5LAST2"; break; case ATON_DECUN_BFMT_CV256CW5LAST3: str = (const int8_t *)"CV256CW5LAST3"; break; case ATON_DECUN_BFMT_CV256CW5LAST4: str = (const int8_t *)"CV256CW5LAST4"; break; case ATON_DECUN_BFMT_CV256CW6LAST1: str = (const int8_t *)"CV256CW6LAST1"; break; case ATON_DECUN_BFMT_CV256CW6LAST2: str = (const int8_t *)"CV256CW6LAST2"; break; case ATON_DECUN_BFMT_CV256CW6LAST3: str = (const int8_t *)"CV256CW6LAST3"; break; case ATON_DECUN_BFMT_CV256CW6LAST4: str = (const int8_t *)"CV256CW6LAST4"; break; case ATON_DECUN_BFMT_CV256CW6LAST5: str = (const int8_t *)"CV256CW6LAST5"; break; case ATON_DECUN_BFMT_CV256CW7LAST1: str = (const int8_t *)"CV256CW7LAST1"; break; case ATON_DECUN_BFMT_CV256CW7LAST2: str = (const int8_t *)"CV256CW7LAST2"; break; case ATON_DECUN_BFMT_CV256CW7LAST3: str = (const int8_t *)"CV256CW7LAST3"; break; case ATON_DECUN_BFMT_CV256CW7LAST4: str = (const int8_t *)"CV256CW7LAST4"; break; case ATON_DECUN_BFMT_CV256CW7LAST5: str = (const int8_t *)"CV256CW7LAST5"; break; case ATON_DECUN_BFMT_CV256CW7LAST6: str = (const int8_t *)"CV256CW7LAST6"; break; case ATON_DECUN_BFMT_CV256CW8LAST1: str = (const int8_t *)"CV256CW8LAST1"; break; case ATON_DECUN_BFMT_CV256CW8LAST2: str = (const int8_t *)"CV256CW8LAST2"; break; case ATON_DECUN_BFMT_CV256CW8LAST3: str = (const int8_t *)"CV256CW8LAST3"; break; case ATON_DECUN_BFMT_CV256CW8LAST4: str = (const int8_t *)"CV256CW8LAST4"; break; case ATON_DECUN_BFMT_CV256CW8LAST5: str = (const int8_t *)"CV256CW8LAST5"; break; case ATON_DECUN_BFMT_CV256CW8LAST6: str = (const int8_t *)"CV256CW8LAST6"; break; case ATON_DECUN_BFMT_CV256CW8LAST7: str = (const int8_t *)"CV256CW8LAST7"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* DECUN_DFMT set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** DFORMAT values: DATA16. */ #define ATON_DECUN_DFMT_DATA16 (0x0UL) /** DFORMAT values: DATA8. */ #define ATON_DECUN_DFMT_DATA8 (0x1UL) /** Get the name of one of the values of the DECUN_DFMT set of enumerated values. */ #define ATON_DECUN_DFMT_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "DATA16" : \ (((VALUE) == 1UL) ? "DATA8" : "")) /** * Check if a value of the DECUN_DFMT set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the DECUN_DFMT set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_DECUN_DFMT_IsValid(uint32_t val) { bool retval = false; switch (val) { case ATON_DECUN_DFMT_DATA16: case ATON_DECUN_DFMT_DATA8: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the DECUN_DFMT set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the DECUN_DFMT set of enumerated values */ static inline const int8_t *ATON_DECUN_DFMT_GetName(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_DECUN_DFMT_DATA16: str = (const int8_t *)"DATA16"; break; case ATON_DECUN_DFMT_DATA8: str = (const int8_t *)"DATA8"; break; default: break; } return str; } /** * Get the description of one of the values of the DECUN_DFMT set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the DECUN_DFMT set of enumerated values */ static inline const int8_t *ATON_DECUN_DFMT_GetDesc(uint32_t val) { const int8_t *str = NULL; switch (val) { case ATON_DECUN_DFMT_DATA16: str = (const int8_t *)"DATA16"; break; case ATON_DECUN_DFMT_DATA8: str = (const int8_t *)"DATA8"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* EVENTTYPE set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Event type: Pixels. */ #define ATON_EVENTTYPE_PIXELS (0x0UL) /** Event type: Lines. */ #define ATON_EVENTTYPE_LINES (0x1UL) /** Event type: Frames. */ #define ATON_EVENTTYPE_FRAMES (0x2UL) /** Get the name of one of the values of the EVENTTYPE set of enumerated values. */ #define ATON_EVENTTYPE_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "PIXELS" : \ (((VALUE) == 1UL) ? "LINES" : \ (((VALUE) == 2UL) ? "FRAMES" : ""))) /** * Check if a value of the EVENTTYPE set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the EVENTTYPE set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_EVENTTYPE_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_EVENTTYPE_PIXELS: case ATON_EVENTTYPE_LINES: case ATON_EVENTTYPE_FRAMES: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the EVENTTYPE set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the EVENTTYPE set of enumerated values */ static inline const int8_t *ATON_EVENTTYPE_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_EVENTTYPE_PIXELS: str = (const int8_t *)"PIXELS"; break; case ATON_EVENTTYPE_LINES: str = (const int8_t *)"LINES"; break; case ATON_EVENTTYPE_FRAMES: str = (const int8_t *)"FRAMES"; break; default: break; } return str; } /** * Get the description of one of the values of the EVENTTYPE set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the EVENTTYPE set of enumerated values */ static inline const int8_t *ATON_EVENTTYPE_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_EVENTTYPE_PIXELS: str = (const int8_t *)"Pixels"; break; case ATON_EVENTTYPE_LINES: str = (const int8_t *)"Lines"; break; case ATON_EVENTTYPE_FRAMES: str = (const int8_t *)"Frames"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* LINK set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Source port: Stream Engine 0. */ #define ATON_LINK_STRENG0 (0x0UL) /** Source port: Stream Engine 1. */ #define ATON_LINK_STRENG1 (0x1UL) /** Source port: Stream Engine 2. */ #define ATON_LINK_STRENG2 (0x2UL) /** Source port: Stream Engine 3. */ #define ATON_LINK_STRENG3 (0x3UL) /** Source port: Stream Engine 4. */ #define ATON_LINK_STRENG4 (0x4UL) /** Source port: Stream Engine 5. */ #define ATON_LINK_STRENG5 (0x5UL) /** Source port: Stream Engine 6. */ #define ATON_LINK_STRENG6 (0x6UL) /** Source port: Stream Engine 7. */ #define ATON_LINK_STRENG7 (0x7UL) /** Source port: Stream Engine 8. */ #define ATON_LINK_STRENG8 (0x8UL) /** Source port: Stream Engine 9. */ #define ATON_LINK_STRENG9 (0x9UL) /** Source port: Convolutional Accelerator 0. */ #define ATON_LINK_CONVACC0 (0xaUL) /** Source port: Convolutional Accelerator 1. */ #define ATON_LINK_CONVACC1 (0xbUL) /** Source port: Convolutional Accelerator 2. */ #define ATON_LINK_CONVACC2 (0xcUL) /** Source port: Convolutional Accelerator 3. */ #define ATON_LINK_CONVACC3 (0xdUL) /** Source port: Decompression Unit 0. */ #define ATON_LINK_DECUN0 (0xeUL) /** Source port: Decompression Unit 1. */ #define ATON_LINK_DECUN1 (0xfUL) /** Source port: Activation Accelerator 0. */ #define ATON_LINK_ACTIV0 (0x10UL) /** Source port: Activation Accelerator 1. */ #define ATON_LINK_ACTIV1 (0x11UL) /** Source port: Arithmetic Accelerator 0. */ #define ATON_LINK_ARITH0 (0x12UL) /** Source port: Arithmetic Accelerator 1. */ #define ATON_LINK_ARITH1 (0x13UL) /** Source port: Arithmetic Accelerator 2. */ #define ATON_LINK_ARITH2 (0x14UL) /** Source port: Arithmetic Accelerator 3. */ #define ATON_LINK_ARITH3 (0x15UL) /** Source port: Pooling Accelerator 0. */ #define ATON_LINK_POOL0 (0x16UL) /** Source port: Pooling Accelerator 1. */ #define ATON_LINK_POOL1 (0x17UL) /** Source port: Reconfigurable Buffer 0 port 0. */ #define ATON_LINK_RECBUF00 (0x18UL) /** Source port: Reconfigurable Buffer 0 port 1. */ #define ATON_LINK_RECBUF01 (0x19UL) /** Source port: Reconfigurable Buffer 0 port 2. */ #define ATON_LINK_RECBUF02 (0x1aUL) /** Get the name of one of the values of the LINK set of enumerated values. */ #define ATON_LINK_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "STRENG0" : \ (((VALUE) == 1UL) ? "STRENG1" : \ (((VALUE) == 2UL) ? "STRENG2" : \ (((VALUE) == 3UL) ? "STRENG3" : \ (((VALUE) == 4UL) ? "STRENG4" : \ (((VALUE) == 5UL) ? "STRENG5" : \ (((VALUE) == 6UL) ? "STRENG6" : \ (((VALUE) == 7UL) ? "STRENG7" : \ (((VALUE) == 8UL) ? "STRENG8" : \ (((VALUE) == 9UL) ? "STRENG9" : \ (((VALUE) == 10UL) ? "CONVACC0" : \ (((VALUE) == 11UL) ? "CONVACC1" : \ (((VALUE) == 12UL) ? "CONVACC2" : \ (((VALUE) == 13UL) ? "CONVACC3" : \ (((VALUE) == 14UL) ? "DECUN0" : \ (((VALUE) == 15UL) ? "DECUN1" : \ (((VALUE) == 16UL) ? "ACTIV0" : \ (((VALUE) == 17UL) ? "ACTIV1" : \ (((VALUE) == 18UL) ? "ARITH0" : \ (((VALUE) == 19UL) ? "ARITH1" : \ (((VALUE) == 20UL) ? "ARITH2" : \ (((VALUE) == 21UL) ? "ARITH3" : \ (((VALUE) == 22UL) ? "POOL0" : \ (((VALUE) == 23UL) ? "POOL1" : \ (((VALUE) == 24UL) ? "RECBUF00" : \ (((VALUE) == 25UL) ? "RECBUF01" : \ (((VALUE) == 26UL) ? "RECBUF02" : ""))))))))))))))))))))))))))) /** * Check if a value of the LINK set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the LINK set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_LINK_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_LINK_STRENG0: case ATON_LINK_STRENG1: case ATON_LINK_STRENG2: case ATON_LINK_STRENG3: case ATON_LINK_STRENG4: case ATON_LINK_STRENG5: case ATON_LINK_STRENG6: case ATON_LINK_STRENG7: case ATON_LINK_STRENG8: case ATON_LINK_STRENG9: case ATON_LINK_CONVACC0: case ATON_LINK_CONVACC1: case ATON_LINK_CONVACC2: case ATON_LINK_CONVACC3: case ATON_LINK_DECUN0: case ATON_LINK_DECUN1: case ATON_LINK_ACTIV0: case ATON_LINK_ACTIV1: case ATON_LINK_ARITH0: case ATON_LINK_ARITH1: case ATON_LINK_ARITH2: case ATON_LINK_ARITH3: case ATON_LINK_POOL0: case ATON_LINK_POOL1: case ATON_LINK_RECBUF00: case ATON_LINK_RECBUF01: case ATON_LINK_RECBUF02: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the LINK set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the LINK set of enumerated values */ static inline const int8_t *ATON_LINK_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_LINK_STRENG0: str = (const int8_t *)"STRENG0"; break; case ATON_LINK_STRENG1: str = (const int8_t *)"STRENG1"; break; case ATON_LINK_STRENG2: str = (const int8_t *)"STRENG2"; break; case ATON_LINK_STRENG3: str = (const int8_t *)"STRENG3"; break; case ATON_LINK_STRENG4: str = (const int8_t *)"STRENG4"; break; case ATON_LINK_STRENG5: str = (const int8_t *)"STRENG5"; break; case ATON_LINK_STRENG6: str = (const int8_t *)"STRENG6"; break; case ATON_LINK_STRENG7: str = (const int8_t *)"STRENG7"; break; case ATON_LINK_STRENG8: str = (const int8_t *)"STRENG8"; break; case ATON_LINK_STRENG9: str = (const int8_t *)"STRENG9"; break; case ATON_LINK_CONVACC0: str = (const int8_t *)"CONVACC0"; break; case ATON_LINK_CONVACC1: str = (const int8_t *)"CONVACC1"; break; case ATON_LINK_CONVACC2: str = (const int8_t *)"CONVACC2"; break; case ATON_LINK_CONVACC3: str = (const int8_t *)"CONVACC3"; break; case ATON_LINK_DECUN0: str = (const int8_t *)"DECUN0"; break; case ATON_LINK_DECUN1: str = (const int8_t *)"DECUN1"; break; case ATON_LINK_ACTIV0: str = (const int8_t *)"ACTIV0"; break; case ATON_LINK_ACTIV1: str = (const int8_t *)"ACTIV1"; break; case ATON_LINK_ARITH0: str = (const int8_t *)"ARITH0"; break; case ATON_LINK_ARITH1: str = (const int8_t *)"ARITH1"; break; case ATON_LINK_ARITH2: str = (const int8_t *)"ARITH2"; break; case ATON_LINK_ARITH3: str = (const int8_t *)"ARITH3"; break; case ATON_LINK_POOL0: str = (const int8_t *)"POOL0"; break; case ATON_LINK_POOL1: str = (const int8_t *)"POOL1"; break; case ATON_LINK_RECBUF00: str = (const int8_t *)"RECBUF00"; break; case ATON_LINK_RECBUF01: str = (const int8_t *)"RECBUF01"; break; case ATON_LINK_RECBUF02: str = (const int8_t *)"RECBUF02"; break; default: break; } return str; } /** * Get the description of one of the values of the LINK set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the LINK set of enumerated values */ static inline const int8_t *ATON_LINK_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_LINK_STRENG0: str = (const int8_t *)"Stream Engine 0"; break; case ATON_LINK_STRENG1: str = (const int8_t *)"Stream Engine 1"; break; case ATON_LINK_STRENG2: str = (const int8_t *)"Stream Engine 2"; break; case ATON_LINK_STRENG3: str = (const int8_t *)"Stream Engine 3"; break; case ATON_LINK_STRENG4: str = (const int8_t *)"Stream Engine 4"; break; case ATON_LINK_STRENG5: str = (const int8_t *)"Stream Engine 5"; break; case ATON_LINK_STRENG6: str = (const int8_t *)"Stream Engine 6"; break; case ATON_LINK_STRENG7: str = (const int8_t *)"Stream Engine 7"; break; case ATON_LINK_STRENG8: str = (const int8_t *)"Stream Engine 8"; break; case ATON_LINK_STRENG9: str = (const int8_t *)"Stream Engine 9"; break; case ATON_LINK_CONVACC0: str = (const int8_t *)"Convolutional Accelerator 0"; break; case ATON_LINK_CONVACC1: str = (const int8_t *)"Convolutional Accelerator 1"; break; case ATON_LINK_CONVACC2: str = (const int8_t *)"Convolutional Accelerator 2"; break; case ATON_LINK_CONVACC3: str = (const int8_t *)"Convolutional Accelerator 3"; break; case ATON_LINK_DECUN0: str = (const int8_t *)"Decompression Unit 0"; break; case ATON_LINK_DECUN1: str = (const int8_t *)"Decompression Unit 1"; break; case ATON_LINK_ACTIV0: str = (const int8_t *)"Activation Accelerator 0"; break; case ATON_LINK_ACTIV1: str = (const int8_t *)"Activation Accelerator 1"; break; case ATON_LINK_ARITH0: str = (const int8_t *)"Arithmetic Accelerator 0"; break; case ATON_LINK_ARITH1: str = (const int8_t *)"Arithmetic Accelerator 1"; break; case ATON_LINK_ARITH2: str = (const int8_t *)"Arithmetic Accelerator 2"; break; case ATON_LINK_ARITH3: str = (const int8_t *)"Arithmetic Accelerator 3"; break; case ATON_LINK_POOL0: str = (const int8_t *)"Pooling Accelerator 0"; break; case ATON_LINK_POOL1: str = (const int8_t *)"Pooling Accelerator 1"; break; case ATON_LINK_RECBUF00: str = (const int8_t *)"Reconfigurable Buffer 0 port 0"; break; case ATON_LINK_RECBUF01: str = (const int8_t *)"Reconfigurable Buffer 0 port 1"; break; case ATON_LINK_RECBUF02: str = (const int8_t *)"Reconfigurable Buffer 0 port 2"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* POOLTYPE set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Pool operation type: Max pooling. */ #define ATON_POOLTYPE_MAX_POOLING (0x0UL) /** Pool operation type: Min pooling. */ #define ATON_POOLTYPE_MIN_POOLING (0x1UL) /** Pool operation type: Average pooling. */ #define ATON_POOLTYPE_AVG_POOLING (0x2UL) /** Pool operation type: Global max pooling. */ #define ATON_POOLTYPE_GMAX_POOLING (0x8UL) /** Pool operation type: Global min pooling. */ #define ATON_POOLTYPE_GMIN_POOLING (0x9UL) /** Pool operation type: Global average pooling. */ #define ATON_POOLTYPE_GAVG_POOLING (0xaUL) /** Get the name of one of the values of the POOLTYPE set of enumerated values. */ #define ATON_POOLTYPE_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "MAX_POOLING" : \ (((VALUE) == 1UL) ? "MIN_POOLING" : \ (((VALUE) == 2UL) ? "AVG_POOLING" : \ (((VALUE) == 8UL) ? "GMAX_POOLING" : \ (((VALUE) == 9UL) ? "GMIN_POOLING" : \ (((VALUE) == 10UL) ? "GAVG_POOLING" : "")))))) /** * Check if a value of the POOLTYPE set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the POOLTYPE set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_POOLTYPE_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_POOLTYPE_MAX_POOLING: case ATON_POOLTYPE_MIN_POOLING: case ATON_POOLTYPE_AVG_POOLING: case ATON_POOLTYPE_GMAX_POOLING: case ATON_POOLTYPE_GMIN_POOLING: case ATON_POOLTYPE_GAVG_POOLING: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the POOLTYPE set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the POOLTYPE set of enumerated values */ static inline const int8_t *ATON_POOLTYPE_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_POOLTYPE_MAX_POOLING: str = (const int8_t *)"MAX_POOLING"; break; case ATON_POOLTYPE_MIN_POOLING: str = (const int8_t *)"MIN_POOLING"; break; case ATON_POOLTYPE_AVG_POOLING: str = (const int8_t *)"AVG_POOLING"; break; case ATON_POOLTYPE_GMAX_POOLING: str = (const int8_t *)"GMAX_POOLING"; break; case ATON_POOLTYPE_GMIN_POOLING: str = (const int8_t *)"GMIN_POOLING"; break; case ATON_POOLTYPE_GAVG_POOLING: str = (const int8_t *)"GAVG_POOLING"; break; default: break; } return str; } /** * Get the description of one of the values of the POOLTYPE set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the POOLTYPE set of enumerated values */ static inline const int8_t *ATON_POOLTYPE_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_POOLTYPE_MAX_POOLING: str = (const int8_t *)"Max pooling"; break; case ATON_POOLTYPE_MIN_POOLING: str = (const int8_t *)"Min pooling"; break; case ATON_POOLTYPE_AVG_POOLING: str = (const int8_t *)"Average pooling"; break; case ATON_POOLTYPE_GMAX_POOLING: str = (const int8_t *)"Global max pooling"; break; case ATON_POOLTYPE_GMIN_POOLING: str = (const int8_t *)"Global min pooling"; break; case ATON_POOLTYPE_GAVG_POOLING: str = (const int8_t *)"Global average pooling"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* SIGN set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Signed/unsigned activations: unsigned activations. */ #define ATON_SIGN_UNSIGNED (0x0UL) /** Signed/unsigned activations: signed activations. */ #define ATON_SIGN_SIGNED (0x1UL) /** Get the name of one of the values of the SIGN set of enumerated values. */ #define ATON_SIGN_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "UNSIGNED" : \ (((VALUE) == 1UL) ? "SIGNED" : "")) /** * Check if a value of the SIGN set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the SIGN set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_SIGN_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_SIGN_UNSIGNED: case ATON_SIGN_SIGNED: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the SIGN set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the SIGN set of enumerated values */ static inline const int8_t *ATON_SIGN_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_SIGN_UNSIGNED: str = (const int8_t *)"UNSIGNED"; break; case ATON_SIGN_SIGNED: str = (const int8_t *)"SIGNED"; break; default: break; } return str; } /** * Get the description of one of the values of the SIGN set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the SIGN set of enumerated values */ static inline const int8_t *ATON_SIGN_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_SIGN_UNSIGNED: str = (const int8_t *)"unsigned activations"; break; case ATON_SIGN_SIGNED: str = (const int8_t *)"signed activations"; break; default: break; } return str; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* STRENGDIR set of enumerated values */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Direction: Bus to Stream Engine direction. */ #define ATON_STRENGDIR_BUS2STR (0x0UL) /** Direction: Stream Engine to bus direction. */ #define ATON_STRENGDIR_STR2BUS (0x1UL) /** Get the name of one of the values of the STRENGDIR set of enumerated values. */ #define ATON_STRENGDIR_GET_NAME(VALUE) \ (((VALUE) == 0UL) ? "BUS2STR" : \ (((VALUE) == 1UL) ? "STR2BUS" : "")) /** * Check if a value of the STRENGDIR set of enumerated values is valid. * * \param[in] val is the numeric value that must be checked * * \retval \e true if \e val is a valid value of the STRENGDIR set of enumerated values is valid * \retval \e false otherwise */ static inline bool ATON_STRENGDIR_IsValid(uint8_t val) { bool retval = false; switch (val) { case ATON_STRENGDIR_BUS2STR: case ATON_STRENGDIR_STR2BUS: retval = true; break; default: break; } return retval; } /** * Get the name of one of the values of the STRENGDIR set of enumerated values. * * \param[in] val is the numeric value whose name must be returned * * \return the name of value \e val of the STRENGDIR set of enumerated values */ static inline const int8_t *ATON_STRENGDIR_GetName(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_STRENGDIR_BUS2STR: str = (const int8_t *)"BUS2STR"; break; case ATON_STRENGDIR_STR2BUS: str = (const int8_t *)"STR2BUS"; break; default: break; } return str; } /** * Get the description of one of the values of the STRENGDIR set of enumerated values. * * \param[in] val is the numeric value whose description must be returned * * \return the description of value \e val of the STRENGDIR set of enumerated values */ static inline const int8_t *ATON_STRENGDIR_GetDesc(uint8_t val) { const int8_t *str = NULL; switch (val) { case ATON_STRENGDIR_BUS2STR: str = (const int8_t *)"Bus to Stream Engine direction"; break; case ATON_STRENGDIR_STR2BUS: str = (const int8_t *)"Stream Engine to bus direction"; break; default: break; } return str; } /* ********************************************************************************************************************************************************** */ /* */ /* ATON */ /* */ /* ********************************************************************************************************************************************************** */ #ifndef ATON_BASE #warning "Using default value of ATON_BASE" /** Base address of the ATON address space (this will not be redefined if already defined). */ #define ATON_BASE 0x00010000UL #endif /** Size in bytes of the ATON address space. */ #define ATON_SIZE 0x20000UL /** * Get the base address of the ATON address space. */ static inline uint32_t ATON_GetBase(void) { return ATON_BASE; } /** * Get the size in bytes of the ATON address space. */ static inline uint32_t ATON_GetSize(void) { return ATON_SIZE; } /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* CLOCKS */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** * \name Clocks */ /*@{*/ #define ATON_CLK_CLKA_NR 4 #define ATON_INTCTRL_CLK_CLKA 0 #define ATON_BUSIF0_CLK_CLKA 1 #define ATON_BUSIF1_CLK_CLKA 2 #define ATON_STRSWITCH_CLK_CLKA 3 #define ATON_CLK_CLKB_NR 27 #define ATON_STRENG0_CLK_CLKB 0 #define ATON_STRENG1_CLK_CLKB 1 #define ATON_STRENG2_CLK_CLKB 2 #define ATON_STRENG3_CLK_CLKB 3 #define ATON_STRENG4_CLK_CLKB 4 #define ATON_STRENG5_CLK_CLKB 5 #define ATON_STRENG6_CLK_CLKB 6 #define ATON_STRENG7_CLK_CLKB 7 #define ATON_STRENG8_CLK_CLKB 8 #define ATON_STRENG9_CLK_CLKB 9 #define ATON_CONVACC0_CLK_CLKB 10 #define ATON_CONVACC1_CLK_CLKB 11 #define ATON_CONVACC2_CLK_CLKB 12 #define ATON_CONVACC3_CLK_CLKB 13 #define ATON_DECUN0_CLK_CLKB 14 #define ATON_DECUN1_CLK_CLKB 15 #define ATON_ACTIV0_CLK_CLKB 16 #define ATON_ACTIV1_CLK_CLKB 17 #define ATON_ARITH0_CLK_CLKB 18 #define ATON_ARITH1_CLK_CLKB 19 #define ATON_ARITH2_CLK_CLKB 20 #define ATON_ARITH3_CLK_CLKB 21 #define ATON_POOL0_CLK_CLKB 22 #define ATON_POOL1_CLK_CLKB 23 #define ATON_RECBUF0_CLK_CLKB 24 #define ATON_EPOCHCTRL0_CLK_CLKB 25 #define ATON_DEBUG_TRACE0_CLK_CLKB 26 /** * Return the mask of the CLKA clock of a CLKCTRL Unit. * * \param[in] UNIT if smaller than #ATON_CLKCTRL_NUM is the CLKCTRL instance index, otherwise if this value is equal to #ATON_CLKCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single CLKCTRL instance if \e UNIT is smaller than #ATON_CLKCTRL_NUM * \retval the mask of CLKA clock of all CLKCTRL instances if \e UNIT is equal to #ATON_CLKCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_CLKCTRL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a CLKCTRL Unit. * * \param[in] UNIT if smaller than #ATON_CLKCTRL_NUM is the CLKCTRL instance index, otherwise if this value is equal to #ATON_CLKCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single CLKCTRL instance if \e UNIT is smaller than #ATON_CLKCTRL_NUM * \retval the mask of CLKB clock of all CLKCTRL instances if \e UNIT is equal to #ATON_CLKCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_CLKCTRL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKA clock of a INTCTRL Unit. * * \param[in] UNIT if smaller than #ATON_INTCTRL_NUM is the INTCTRL instance index, otherwise if this value is equal to #ATON_INTCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single INTCTRL instance if \e UNIT is smaller than #ATON_INTCTRL_NUM * \retval the mask of CLKA clock of all INTCTRL instances if \e UNIT is equal to #ATON_INTCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_INTCTRL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000001UL : \ 0x00000000UL) /** * Return the mask of the CLKB clock of a INTCTRL Unit. * * \param[in] UNIT if smaller than #ATON_INTCTRL_NUM is the INTCTRL instance index, otherwise if this value is equal to #ATON_INTCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single INTCTRL instance if \e UNIT is smaller than #ATON_INTCTRL_NUM * \retval the mask of CLKB clock of all INTCTRL instances if \e UNIT is equal to #ATON_INTCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_INTCTRL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKA clock of a ACTIV Unit. * * \param[in] UNIT if smaller than #ATON_ACTIV_NUM is the ACTIV instance index, otherwise if this value is equal to #ATON_ACTIV_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single ACTIV instance if \e UNIT is smaller than #ATON_ACTIV_NUM * \retval the mask of CLKA clock of all ACTIV instances if \e UNIT is equal to #ATON_ACTIV_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_ACTIV_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a ACTIV Unit. * * \param[in] UNIT if smaller than #ATON_ACTIV_NUM is the ACTIV instance index, otherwise if this value is equal to #ATON_ACTIV_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single ACTIV instance if \e UNIT is smaller than #ATON_ACTIV_NUM * \retval the mask of CLKB clock of all ACTIV instances if \e UNIT is equal to #ATON_ACTIV_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_ACTIV_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00010000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00020000UL : \ 0x00000000UL)) /** * Return the mask of the CLKA clock of a ARITH Unit. * * \param[in] UNIT if smaller than #ATON_ARITH_NUM is the ARITH instance index, otherwise if this value is equal to #ATON_ARITH_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single ARITH instance if \e UNIT is smaller than #ATON_ARITH_NUM * \retval the mask of CLKA clock of all ARITH instances if \e UNIT is equal to #ATON_ARITH_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_ARITH_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a ARITH Unit. * * \param[in] UNIT if smaller than #ATON_ARITH_NUM is the ARITH instance index, otherwise if this value is equal to #ATON_ARITH_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single ARITH instance if \e UNIT is smaller than #ATON_ARITH_NUM * \retval the mask of CLKB clock of all ARITH instances if \e UNIT is equal to #ATON_ARITH_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_ARITH_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00040000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00080000UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x00100000UL : \ (((REG_IDX == 0) && (UNIT == 3)) ? 0x00200000UL : \ 0x00000000UL)))) /** * Return the mask of the CLKA clock of a POOL Unit. * * \param[in] UNIT if smaller than #ATON_POOL_NUM is the POOL instance index, otherwise if this value is equal to #ATON_POOL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single POOL instance if \e UNIT is smaller than #ATON_POOL_NUM * \retval the mask of CLKA clock of all POOL instances if \e UNIT is equal to #ATON_POOL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_POOL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a POOL Unit. * * \param[in] UNIT if smaller than #ATON_POOL_NUM is the POOL instance index, otherwise if this value is equal to #ATON_POOL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single POOL instance if \e UNIT is smaller than #ATON_POOL_NUM * \retval the mask of CLKB clock of all POOL instances if \e UNIT is equal to #ATON_POOL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_POOL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00400000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00800000UL : \ 0x00000000UL)) /** * Return the mask of the CLKA clock of a BUSIF Unit. * * \param[in] UNIT if smaller than #ATON_BUSIF_NUM is the BUSIF instance index, otherwise if this value is equal to #ATON_BUSIF_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single BUSIF instance if \e UNIT is smaller than #ATON_BUSIF_NUM * \retval the mask of CLKA clock of all BUSIF instances if \e UNIT is equal to #ATON_BUSIF_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_BUSIF_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000002UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000004UL : \ 0x00000000UL)) /** * Return the mask of the CLKB clock of a BUSIF Unit. * * \param[in] UNIT if smaller than #ATON_BUSIF_NUM is the BUSIF instance index, otherwise if this value is equal to #ATON_BUSIF_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single BUSIF instance if \e UNIT is smaller than #ATON_BUSIF_NUM * \retval the mask of CLKB clock of all BUSIF instances if \e UNIT is equal to #ATON_BUSIF_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_BUSIF_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKA clock of a STRENG Unit. * * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM * \retval the mask of CLKA clock of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRENG_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a STRENG Unit. * * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM * \retval the mask of CLKB clock of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRENG_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000001UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000002UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x00000004UL : \ (((REG_IDX == 0) && (UNIT == 3)) ? 0x00000008UL : \ (((REG_IDX == 0) && (UNIT == 4)) ? 0x00000010UL : \ (((REG_IDX == 0) && (UNIT == 5)) ? 0x00000020UL : \ (((REG_IDX == 0) && (UNIT == 6)) ? 0x00000040UL : \ (((REG_IDX == 0) && (UNIT == 7)) ? 0x00000080UL : \ (((REG_IDX == 0) && (UNIT == 8)) ? 0x00000100UL : \ (((REG_IDX == 0) && (UNIT == 9)) ? 0x00000200UL : \ 0x00000000UL)))))))))) /** * Return the mask of the CLKA clock of a STRSWITCH Unit. * * \param[in] UNIT if smaller than #ATON_STRSWITCH_NUM is the STRSWITCH instance index, otherwise if this value is equal to #ATON_STRSWITCH_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single STRSWITCH instance if \e UNIT is smaller than #ATON_STRSWITCH_NUM * \retval the mask of CLKA clock of all STRSWITCH instances if \e UNIT is equal to #ATON_STRSWITCH_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRSWITCH_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000008UL : \ 0x00000000UL) /** * Return the mask of the CLKB clock of a STRSWITCH Unit. * * \param[in] UNIT if smaller than #ATON_STRSWITCH_NUM is the STRSWITCH instance index, otherwise if this value is equal to #ATON_STRSWITCH_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single STRSWITCH instance if \e UNIT is smaller than #ATON_STRSWITCH_NUM * \retval the mask of CLKB clock of all STRSWITCH instances if \e UNIT is equal to #ATON_STRSWITCH_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRSWITCH_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKA clock of a CONVACC Unit. * * \param[in] UNIT if smaller than #ATON_CONVACC_NUM is the CONVACC instance index, otherwise if this value is equal to #ATON_CONVACC_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single CONVACC instance if \e UNIT is smaller than #ATON_CONVACC_NUM * \retval the mask of CLKA clock of all CONVACC instances if \e UNIT is equal to #ATON_CONVACC_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_CONVACC_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a CONVACC Unit. * * \param[in] UNIT if smaller than #ATON_CONVACC_NUM is the CONVACC instance index, otherwise if this value is equal to #ATON_CONVACC_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single CONVACC instance if \e UNIT is smaller than #ATON_CONVACC_NUM * \retval the mask of CLKB clock of all CONVACC instances if \e UNIT is equal to #ATON_CONVACC_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_CONVACC_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000400UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000800UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x00001000UL : \ (((REG_IDX == 0) && (UNIT == 3)) ? 0x00002000UL : \ 0x00000000UL)))) /** * Return the mask of the CLKA clock of a DECUN Unit. * * \param[in] UNIT if smaller than #ATON_DECUN_NUM is the DECUN instance index, otherwise if this value is equal to #ATON_DECUN_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single DECUN instance if \e UNIT is smaller than #ATON_DECUN_NUM * \retval the mask of CLKA clock of all DECUN instances if \e UNIT is equal to #ATON_DECUN_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_DECUN_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a DECUN Unit. * * \param[in] UNIT if smaller than #ATON_DECUN_NUM is the DECUN instance index, otherwise if this value is equal to #ATON_DECUN_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single DECUN instance if \e UNIT is smaller than #ATON_DECUN_NUM * \retval the mask of CLKB clock of all DECUN instances if \e UNIT is equal to #ATON_DECUN_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_DECUN_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00004000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00008000UL : \ 0x00000000UL)) /** * Return the mask of the CLKA clock of a RECBUF Unit. * * \param[in] UNIT if smaller than #ATON_RECBUF_NUM is the RECBUF instance index, otherwise if this value is equal to #ATON_RECBUF_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single RECBUF instance if \e UNIT is smaller than #ATON_RECBUF_NUM * \retval the mask of CLKA clock of all RECBUF instances if \e UNIT is equal to #ATON_RECBUF_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_RECBUF_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a RECBUF Unit. * * \param[in] UNIT if smaller than #ATON_RECBUF_NUM is the RECBUF instance index, otherwise if this value is equal to #ATON_RECBUF_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single RECBUF instance if \e UNIT is smaller than #ATON_RECBUF_NUM * \retval the mask of CLKB clock of all RECBUF instances if \e UNIT is equal to #ATON_RECBUF_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_RECBUF_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x01000000UL : \ 0x00000000UL) /** * Return the mask of the CLKA clock of a EPOCHCTRL Unit. * * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM * \retval the mask of CLKA clock of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_EPOCHCTRL_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a EPOCHCTRL Unit. * * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM * \retval the mask of CLKB clock of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_EPOCHCTRL_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x02000000UL : \ 0x00000000UL) /** * Return the mask of the CLKA clock of a DEBUG_TRACE Unit. * * \param[in] UNIT if smaller than #ATON_DEBUG_TRACE_NUM is the DEBUG_TRACE instance index, otherwise if this value is equal to #ATON_DEBUG_TRACE_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKA clock of a single DEBUG_TRACE instance if \e UNIT is smaller than #ATON_DEBUG_TRACE_NUM * \retval the mask of CLKA clock of all DEBUG_TRACE instances if \e UNIT is equal to #ATON_DEBUG_TRACE_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_DEBUG_TRACE_CLK_CLKA_GET_MASK(UNIT, REG_IDX) \ 0x00000000UL /** * Return the mask of the CLKB clock of a DEBUG_TRACE Unit. * * \param[in] UNIT if smaller than #ATON_DEBUG_TRACE_NUM is the DEBUG_TRACE instance index, otherwise if this value is equal to #ATON_DEBUG_TRACE_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the clock register index; its value must be smaller than 1 * * \retval the mask of CLKB clock of a single DEBUG_TRACE instance if \e UNIT is smaller than #ATON_DEBUG_TRACE_NUM * \retval the mask of CLKB clock of all DEBUG_TRACE instances if \e UNIT is equal to #ATON_DEBUG_TRACE_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_DEBUG_TRACE_CLK_CLKB_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x04000000UL : \ 0x00000000UL) /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* INTERRUPTS */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** * \name Interrupts */ /*@{*/ #define ATON_INT_NR 32 #define ATON_STRENG0_INT 0 #define ATON_STRENG1_INT 1 #define ATON_STRENG2_INT 2 #define ATON_STRENG3_INT 3 #define ATON_STRENG4_INT 4 #define ATON_STRENG5_INT 5 #define ATON_STRENG6_INT 6 #define ATON_STRENG7_INT 7 #define ATON_STRENG8_INT 8 #define ATON_STRENG9_INT 9 #define ATON_STRENG0_ERR_INT 10 #define ATON_STRENG1_ERR_INT 11 #define ATON_STRENG2_ERR_INT 12 #define ATON_STRENG3_ERR_INT 13 #define ATON_STRENG4_ERR_INT 14 #define ATON_STRENG5_ERR_INT 15 #define ATON_STRENG6_ERR_INT 16 #define ATON_STRENG7_ERR_INT 17 #define ATON_STRENG8_ERR_INT 18 #define ATON_STRENG9_ERR_INT 19 #define ATON_CONVACC0_INT 20 #define ATON_CONVACC1_INT 21 #define ATON_CONVACC2_INT 22 #define ATON_CONVACC3_INT 23 #define ATON_RECBUF0_INT 24 #define ATON_BUSIF0_INT 25 #define ATON_BUSIF1_INT 26 #define ATON_STRSWITCH_INT 27 #define ATON_EPOCHCTRL0_INT 28 #define ATON_EPOCHCTRL0_NOACK_INT 29 #define ATON_EPOCHCTRL0_ERR_INT 30 #define ATON_DEBUG_TRACE0_INT 31 /** * Return the interrupt mask of a BUSIF Unit. * * \param[in] UNIT if smaller than #ATON_BUSIF_NUM is the BUSIF instance index, otherwise if this value is equal to #ATON_BUSIF_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single BUSIF instance if \e UNIT is smaller than #ATON_BUSIF_NUM * \retval the interrupt mask of all BUSIF instances if \e UNIT is equal to #ATON_BUSIF_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_BUSIF_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x02000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x04000000UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x06000000UL : \ 0x00000000UL))) /** * Return the interrupt mask of a STRENG Unit. * * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM * \retval the interrupt mask of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRENG_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000001UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000002UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x00000004UL : \ (((REG_IDX == 0) && (UNIT == 3)) ? 0x00000008UL : \ (((REG_IDX == 0) && (UNIT == 4)) ? 0x00000010UL : \ (((REG_IDX == 0) && (UNIT == 5)) ? 0x00000020UL : \ (((REG_IDX == 0) && (UNIT == 6)) ? 0x00000040UL : \ (((REG_IDX == 0) && (UNIT == 7)) ? 0x00000080UL : \ (((REG_IDX == 0) && (UNIT == 8)) ? 0x00000100UL : \ (((REG_IDX == 0) && (UNIT == 9)) ? 0x00000200UL : \ (((REG_IDX == 0) && (UNIT == 10)) ? 0x000003ffUL : \ 0x00000000UL))))))))))) /** * Return the interrupt mask of a STRENG Unit. * * \param[in] UNIT if smaller than #ATON_STRENG_NUM is the STRENG instance index, otherwise if this value is equal to #ATON_STRENG_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single STRENG instance if \e UNIT is smaller than #ATON_STRENG_NUM * \retval the interrupt mask of all STRENG instances if \e UNIT is equal to #ATON_STRENG_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRENG_ERR_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00000400UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00000800UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x00001000UL : \ (((REG_IDX == 0) && (UNIT == 3)) ? 0x00002000UL : \ (((REG_IDX == 0) && (UNIT == 4)) ? 0x00004000UL : \ (((REG_IDX == 0) && (UNIT == 5)) ? 0x00008000UL : \ (((REG_IDX == 0) && (UNIT == 6)) ? 0x00010000UL : \ (((REG_IDX == 0) && (UNIT == 7)) ? 0x00020000UL : \ (((REG_IDX == 0) && (UNIT == 8)) ? 0x00040000UL : \ (((REG_IDX == 0) && (UNIT == 9)) ? 0x00080000UL : \ (((REG_IDX == 0) && (UNIT == 10)) ? 0x000ffc00UL : \ 0x00000000UL))))))))))) /** * Return the interrupt mask of a STRSWITCH Unit. * * \param[in] UNIT if smaller than #ATON_STRSWITCH_NUM is the STRSWITCH instance index, otherwise if this value is equal to #ATON_STRSWITCH_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single STRSWITCH instance if \e UNIT is smaller than #ATON_STRSWITCH_NUM * \retval the interrupt mask of all STRSWITCH instances if \e UNIT is equal to #ATON_STRSWITCH_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_STRSWITCH_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x08000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x08000000UL : \ 0x00000000UL)) /** * Return the interrupt mask of a CONVACC Unit. * * \param[in] UNIT if smaller than #ATON_CONVACC_NUM is the CONVACC instance index, otherwise if this value is equal to #ATON_CONVACC_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single CONVACC instance if \e UNIT is smaller than #ATON_CONVACC_NUM * \retval the interrupt mask of all CONVACC instances if \e UNIT is equal to #ATON_CONVACC_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_CONVACC_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x00100000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x00200000UL : \ (((REG_IDX == 0) && (UNIT == 2)) ? 0x00400000UL : \ (((REG_IDX == 0) && (UNIT == 3)) ? 0x00800000UL : \ (((REG_IDX == 0) && (UNIT == 4)) ? 0x00f00000UL : \ 0x00000000UL))))) /** * Return the interrupt mask of a RECBUF Unit. * * \param[in] UNIT if smaller than #ATON_RECBUF_NUM is the RECBUF instance index, otherwise if this value is equal to #ATON_RECBUF_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single RECBUF instance if \e UNIT is smaller than #ATON_RECBUF_NUM * \retval the interrupt mask of all RECBUF instances if \e UNIT is equal to #ATON_RECBUF_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_RECBUF_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x01000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x01000000UL : \ 0x00000000UL)) /** * Return the interrupt mask of a EPOCHCTRL Unit. * * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM * \retval the interrupt mask of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_EPOCHCTRL_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x10000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x10000000UL : \ 0x00000000UL)) /** * Return the interrupt mask of a EPOCHCTRL Unit. * * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM * \retval the interrupt mask of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_EPOCHCTRL_NOACK_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x20000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x20000000UL : \ 0x00000000UL)) /** * Return the interrupt mask of a EPOCHCTRL Unit. * * \param[in] UNIT if smaller than #ATON_EPOCHCTRL_NUM is the EPOCHCTRL instance index, otherwise if this value is equal to #ATON_EPOCHCTRL_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single EPOCHCTRL instance if \e UNIT is smaller than #ATON_EPOCHCTRL_NUM * \retval the interrupt mask of all EPOCHCTRL instances if \e UNIT is equal to #ATON_EPOCHCTRL_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_EPOCHCTRL_ERR_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x40000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x40000000UL : \ 0x00000000UL)) /** * Return the interrupt mask of a DEBUG_TRACE Unit. * * \param[in] UNIT if smaller than #ATON_DEBUG_TRACE_NUM is the DEBUG_TRACE instance index, otherwise if this value is equal to #ATON_DEBUG_TRACE_NUM it indicates * that all instances will be considered * \param[in] REG_IDX is the interrupt register index; its value must be smaller than 1 * * \retval the interrupt mask of a single DEBUG_TRACE instance if \e UNIT is smaller than #ATON_DEBUG_TRACE_NUM * \retval the interrupt mask of all DEBUG_TRACE instances if \e UNIT is equal to #ATON_DEBUG_TRACE_NUM * \retval \e 0 if the values of \e UNIT or \e REG_IDX are not allowed */ #define ATON_DEBUG_TRACE_INT_GET_MASK(UNIT, REG_IDX) \ (((REG_IDX == 0) && (UNIT == 0)) ? 0x80000000UL : \ (((REG_IDX == 0) && (UNIT == 1)) ? 0x80000000UL : \ 0x00000000UL)) /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* CLKCTRL Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of CLKCTRL Unit instances. */ #define ATON_CLKCTRL_NUM 1 /** * \name Structures, macros and functions of the CLKCTRL Units */ /*@{*/ /** * Registers of the CLKCTRL Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e AGATES0 register (Clock enable bits). */ uint32_t AGATES0; /** \e AGATES1 register (Copy of AGATES0 register). */ uint32_t AGATES1; /** \e BGATES register (Clock enable bits register for B clocks). */ uint32_t BGATES; } ATON_CLKCTRL_t; /** Return the pointer to one of the CLKCTRL Units. */ #define ATON_CLKCTRL(UNIT) ((ATON_CLKCTRL_t *)(intptr_t)ATON_CLKCTRL_BASE(UNIT)) /** Name of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_NAME(UNIT) \ (((UNIT) == 0) ? "CLKCTRL" : "") /** Version of the CLKCTRL Units. */ #define ATON_CLKCTRL_VERSION "1.2" /** Description of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_DESC(UNIT) \ (((UNIT) == 0) ? "Clock Controller" : "") /** Base address of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_BASE(UNIT) \ (ATON_BASE + 0x0UL + ((UNIT) * 0x0UL)) /** Size in bytes of the CLKCTRL Units. */ #define ATON_CLKCTRL_SIZE 0x1000UL /** * Get the name of one of the CLKCTRL Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) * * \return the name of Unit having index \e instance among the CLKCTRL Units */ static inline const int8_t *ATON_CLKCTRL_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"CLKCTRL"; break; default: break; } return str; } /** * Get the description of one of the CLKCTRL Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) * * \return the description of Unit having index \e instance among the CLKCTRL Units */ static inline const int8_t *ATON_CLKCTRL_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Clock Controller"; break; default: break; } return str; } /** * Get the version of the CLKCTRL Units. * * \return the version of the CLKCTRL Units */ static inline const int8_t *ATON_CLKCTRL_GetVersion(void) { return (const int8_t *)ATON_CLKCTRL_VERSION; } /** * Get the base address of one of the CLKCTRL Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) * * \return the base address of Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_GetBase(uint32_t instance) { return ATON_CLKCTRL_BASE(instance); } /** * Get the size in bytes of the CLKCTRL Units. * * \return the size in bytes of the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_GetSize(void) { return ATON_CLKCTRL_SIZE; } /* ******************************************************* CTRL register of one of the CLKCTRL Units ******************************************************** */ /** Offset of the CTRL register from the base address of the CLKCTRL Unit. */ #define ATON_CLKCTRL_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the CLKCTRL Unit. */ #define ATON_CLKCTRL_CTRL_DT \ (ATON_CLKCTRL_CTRL_EN_DT << ATON_CLKCTRL_CTRL_EN_LSB) | \ (ATON_CLKCTRL_CTRL_CLR_DT << ATON_CLKCTRL_CTRL_CLR_LSB) | \ (ATON_CLKCTRL_CTRL_FREEZEREQ_DT << ATON_CLKCTRL_CTRL_FREEZEREQ_LSB) | \ (ATON_CLKCTRL_CTRL_FREEZEGNT_DT << ATON_CLKCTRL_CTRL_FREEZEGNT_LSB) | \ (ATON_CLKCTRL_CTRL_CONFCLR_DT << ATON_CLKCTRL_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_CLKCTRL_CTRL_DESC "Control register" /** Address of the CTRL register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_CTRL_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_CTRL_OFFSET) /** Get the content of the CTRL register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_CLKCTRL_CTRL_GetDesc(void) { return (const int8_t *)ATON_CLKCTRL_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_GetOffset(void) { return ATON_CLKCTRL_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the CTRL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_CTRL_GetAddr(uint32_t instance) { return ATON_CLKCTRL_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_CTRL_Get(uint32_t instance) { return ATON_CLKCTRL_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the CTRL register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CLKCTRL_CTRL_Set(uint32_t instance, uint32_t data) { ATON_CLKCTRL_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_EN_DESC "Enable the Clock Control Unit" /** Offset of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_CLKCTRL_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_CLKCTRL_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_EN_LSB, ATON_CLKCTRL_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_EN_LSB, ATON_CLKCTRL_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_CLKCTRL_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Get_EN(uint32_t reg) { return ATON_CLKCTRL_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_CLKCTRL_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_CLKCTRL_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_CLR_LSB, ATON_CLKCTRL_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_CLR_LSB, ATON_CLKCTRL_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_CLKCTRL_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Get_CLR(uint32_t reg) { return ATON_CLKCTRL_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_CTRL_SET_CLR(reg, data); } /* ---------------------------------------------------------- FREEZEREQ field of the CTRL register ---------------------------------------------------------- */ /** Description of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_DESC "Request bus access freeze" /** Offset of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_LSB 2UL /** Size in bits of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_W (1UL) /** Mask for retrieving the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_DT 0x0UL /** Access rights of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_AC "RW" /** Check whether access to the FREEZEREQ field of the CTRL register is secured or not. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_S 0 /** Check whether access to the FREEZEREQ field of the CTRL register is privileged or not. */ #define ATON_CLKCTRL_CTRL_FREEZEREQ_P 0 /** Read the content of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_GET_FREEZEREQ(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_FREEZEREQ_LSB, ATON_CLKCTRL_CTRL_FREEZEREQ_W) /** Modify the content of the FREEZEREQ field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_SET_FREEZEREQ(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_FREEZEREQ_LSB, ATON_CLKCTRL_CTRL_FREEZEREQ_W, DATA) /** * Get the description of the FREEZEREQ field of CTRL register. * * \return the description of the FREEZEREQ field of CTRL register */ static inline const int8_t *ATON_CLKCTRL_CTRL_FREEZEREQ_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_CTRL_FREEZEREQ_DESC; } /** * Read the content of the FREEZEREQ field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FREEZEREQ field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Get_FREEZEREQ(uint32_t reg) { return ATON_CLKCTRL_CTRL_GET_FREEZEREQ(reg); } /** * Write the content of the FREEZEREQ field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FREEZEREQ field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Set_FREEZEREQ(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_CTRL_SET_FREEZEREQ(reg, data); } /* ---------------------------------------------------------- FREEZEGNT field of the CTRL register ---------------------------------------------------------- */ /** Description of the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_DESC "Freeze request grant" /** Offset of the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_LSB 3UL /** Size in bits of the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_W (1UL) /** Mask for retrieving the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_DT 0x0UL /** Access rights of the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_AC "R" /** Check whether access to the FREEZEGNT field of the CTRL register is secured or not. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_S 0 /** Check whether access to the FREEZEGNT field of the CTRL register is privileged or not. */ #define ATON_CLKCTRL_CTRL_FREEZEGNT_P 0 /** Read the content of the FREEZEGNT field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_GET_FREEZEGNT(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_FREEZEGNT_LSB, ATON_CLKCTRL_CTRL_FREEZEGNT_W) /** * Get the description of the FREEZEGNT field of CTRL register. * * \return the description of the FREEZEGNT field of CTRL register */ static inline const int8_t *ATON_CLKCTRL_CTRL_FREEZEGNT_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_CTRL_FREEZEGNT_DESC; } /** * Read the content of the FREEZEGNT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FREEZEGNT field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Get_FREEZEGNT(uint32_t reg) { return ATON_CLKCTRL_CTRL_GET_FREEZEGNT(reg); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_CLKCTRL_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_CLKCTRL_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_CTRL_CONFCLR_LSB, ATON_CLKCTRL_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_CLKCTRL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_CTRL_CONFCLR_LSB, ATON_CLKCTRL_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_CLKCTRL_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_CLKCTRL_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_CLKCTRL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_CTRL_SET_CONFCLR(reg, data); } /* ****************************************************** VERSION register of one of the CLKCTRL Units ****************************************************** */ /** Offset of the VERSION register from the base address of the CLKCTRL Unit. */ #define ATON_CLKCTRL_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the CLKCTRL Unit. */ #define ATON_CLKCTRL_VERSION_DT \ (ATON_CLKCTRL_VERSION_TYPE_DT << ATON_CLKCTRL_VERSION_TYPE_LSB) | \ (ATON_CLKCTRL_VERSION_MINOR_DT << ATON_CLKCTRL_VERSION_MINOR_LSB) | \ (ATON_CLKCTRL_VERSION_MAJOR_DT << ATON_CLKCTRL_VERSION_MAJOR_LSB) | \ (ATON_CLKCTRL_VERSION_AGATES_DT << ATON_CLKCTRL_VERSION_AGATES_LSB) | \ (ATON_CLKCTRL_VERSION_BGATES_DT << ATON_CLKCTRL_VERSION_BGATES_LSB) | \ (ATON_CLKCTRL_VERSION_CLKDIV_DT << ATON_CLKCTRL_VERSION_CLKDIV_LSB) /** Description of the VERSION register. */ #define ATON_CLKCTRL_VERSION_DESC "Version register" /** Address of the VERSION register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_VERSION_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_VERSION_OFFSET) /** Get the content of the VERSION register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_GetDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_GetOffset(void) { return ATON_CLKCTRL_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the VERSION register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_VERSION_GetAddr(uint32_t instance) { return ATON_CLKCTRL_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_VERSION_Get(uint32_t instance) { return ATON_CLKCTRL_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_TYPE_DT 0x1fUL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_CLKCTRL_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_CLKCTRL_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_TYPE_LSB, ATON_CLKCTRL_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_Get_TYPE(uint32_t reg) { return ATON_CLKCTRL_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MINOR_DT 0x2UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_CLKCTRL_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_CLKCTRL_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_MINOR_LSB, ATON_CLKCTRL_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_Get_MINOR(uint32_t reg) { return ATON_CLKCTRL_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_CLKCTRL_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_CLKCTRL_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_MAJOR_LSB, ATON_CLKCTRL_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_Get_MAJOR(uint32_t reg) { return ATON_CLKCTRL_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- AGATES field of the VERSION register ---------------------------------------------------------- */ /** Description of the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_AGATES_DESC "Number of A Clock gates (for system blocks)" /** Offset of the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_AGATES_LSB 16UL /** Size in bits of the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_AGATES_W (4UL) /** Mask for retrieving the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_AGATES_MASK ATON_FIELD_MASK(16UL, 4UL) /** Reset value of the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_AGATES_DT 0x4UL /** Access rights of the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_AGATES_AC "R" /** Check whether access to the AGATES field of the VERSION register is secured or not. */ #define ATON_CLKCTRL_VERSION_AGATES_S 0 /** Check whether access to the AGATES field of the VERSION register is privileged or not. */ #define ATON_CLKCTRL_VERSION_AGATES_P 0 /** Read the content of the AGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_GET_AGATES(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_AGATES_LSB, ATON_CLKCTRL_VERSION_AGATES_W) /** * Get the description of the AGATES field of VERSION register. * * \return the description of the AGATES field of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_AGATES_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_AGATES_DESC; } /** * Read the content of the AGATES field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the AGATES field belonging to VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_Get_AGATES(uint32_t reg) { return ATON_CLKCTRL_VERSION_GET_AGATES(reg); } /* ---------------------------------------------------------- BGATES field of the VERSION register ---------------------------------------------------------- */ /** Description of the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_BGATES_DESC "Number of B Clock gates (for functional units)" /** Offset of the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_BGATES_LSB 20UL /** Size in bits of the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_BGATES_W (8UL) /** Mask for retrieving the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_BGATES_MASK ATON_FIELD_MASK(20UL, 8UL) /** Reset value of the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_BGATES_DT 0x1bUL /** Access rights of the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_BGATES_AC "R" /** Check whether access to the BGATES field of the VERSION register is secured or not. */ #define ATON_CLKCTRL_VERSION_BGATES_S 0 /** Check whether access to the BGATES field of the VERSION register is privileged or not. */ #define ATON_CLKCTRL_VERSION_BGATES_P 0 /** Read the content of the BGATES field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_GET_BGATES(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_BGATES_LSB, ATON_CLKCTRL_VERSION_BGATES_W) /** * Get the description of the BGATES field of VERSION register. * * \return the description of the BGATES field of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_BGATES_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_BGATES_DESC; } /** * Read the content of the BGATES field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the BGATES field belonging to VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_Get_BGATES(uint32_t reg) { return ATON_CLKCTRL_VERSION_GET_BGATES(reg); } /* ---------------------------------------------------------- CLKDIV field of the VERSION register ---------------------------------------------------------- */ /** Description of the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_CLKDIV_DESC "Number of clock dividers" /** Offset of the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_CLKDIV_LSB 28UL /** Size in bits of the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_CLKDIV_W (4UL) /** Mask for retrieving the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_CLKDIV_MASK ATON_FIELD_MASK(28UL, 4UL) /** Reset value of the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_CLKDIV_DT 0x0UL /** Access rights of the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_CLKDIV_AC "R" /** Check whether access to the CLKDIV field of the VERSION register is secured or not. */ #define ATON_CLKCTRL_VERSION_CLKDIV_S 0 /** Check whether access to the CLKDIV field of the VERSION register is privileged or not. */ #define ATON_CLKCTRL_VERSION_CLKDIV_P 0 /** Read the content of the CLKDIV field of the VERSION register. */ #define ATON_CLKCTRL_VERSION_GET_CLKDIV(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_VERSION_CLKDIV_LSB, ATON_CLKCTRL_VERSION_CLKDIV_W) /** * Get the description of the CLKDIV field of VERSION register. * * \return the description of the CLKDIV field of VERSION register */ static inline const int8_t *ATON_CLKCTRL_VERSION_CLKDIV_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_VERSION_CLKDIV_DESC; } /** * Read the content of the CLKDIV field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the CLKDIV field belonging to VERSION register */ static inline uint32_t ATON_CLKCTRL_VERSION_Get_CLKDIV(uint32_t reg) { return ATON_CLKCTRL_VERSION_GET_CLKDIV(reg); } /* ****************************************************** AGATES0 register of one of the CLKCTRL Units ****************************************************** */ /** Offset of the AGATES0 register from the base address of the CLKCTRL Unit. */ #define ATON_CLKCTRL_AGATES0_OFFSET 0x8UL /** Reset value of the AGATES0 register of the CLKCTRL Unit. */ #define ATON_CLKCTRL_AGATES0_DT \ (ATON_CLKCTRL_AGATES0_INTCTRL_DT << ATON_CLKCTRL_AGATES0_INTCTRL_LSB) | \ (ATON_CLKCTRL_AGATES0_BUSIF0_DT << ATON_CLKCTRL_AGATES0_BUSIF0_LSB) | \ (ATON_CLKCTRL_AGATES0_BUSIF1_DT << ATON_CLKCTRL_AGATES0_BUSIF1_LSB) | \ (ATON_CLKCTRL_AGATES0_STRSWITCH_DT << ATON_CLKCTRL_AGATES0_STRSWITCH_LSB) /** Description of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_DESC "Clock enable bits" /** Address of the AGATES0 register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_AGATES0_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_AGATES0_OFFSET) /** Get the content of the AGATES0 register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_AGATES0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES0_ADDR(UNIT))) /** Set the content of the AGATES0 register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_AGATES0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of AGATES0 register. * * \return the description of AGATES0 register */ static inline const int8_t *ATON_CLKCTRL_AGATES0_GetDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES0_DESC; } /** * Get the offset of the AGATES0 register. * * \return the offset of AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_GetOffset(void) { return ATON_CLKCTRL_AGATES0_OFFSET; } /** * Get the address of the AGATES0 register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of AGATES0 register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_AGATES0_GetAddr(uint32_t instance) { return ATON_CLKCTRL_AGATES0_ADDR(instance); } /** * Read the content of the AGATES0 register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of AGATES0 register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_AGATES0_Get(uint32_t instance) { return ATON_CLKCTRL_AGATES0_GET(instance); } /** * Write the content of the AGATES0 register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CLKCTRL_AGATES0_Set(uint32_t instance, uint32_t data) { ATON_CLKCTRL_AGATES0_SET(instance, data); } /* --------------------------------------------------------- INTCTRL field of the AGATES0 register ---------------------------------------------------------- */ /** Description of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_DESC "Enable clock of Interrupt Controller" /** Offset of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_LSB 0UL /** Size in bits of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_W (1UL) /** Mask for retrieving the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_DT 0x0UL /** Access rights of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_AC "RW" /** Check whether access to the INTCTRL field of the AGATES0 register is secured or not. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_S 0 /** Check whether access to the INTCTRL field of the AGATES0 register is privileged or not. */ #define ATON_CLKCTRL_AGATES0_INTCTRL_P 0 /** Read the content of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_GET_INTCTRL(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_INTCTRL_LSB, ATON_CLKCTRL_AGATES0_INTCTRL_W) /** Modify the content of the INTCTRL field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_SET_INTCTRL(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_INTCTRL_LSB, ATON_CLKCTRL_AGATES0_INTCTRL_W, DATA) /** * Get the description of the INTCTRL field of AGATES0 register. * * \return the description of the INTCTRL field of AGATES0 register */ static inline const int8_t *ATON_CLKCTRL_AGATES0_INTCTRL_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES0_INTCTRL_DESC; } /** * Read the content of the INTCTRL field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * * \return the content of the INTCTRL field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Get_INTCTRL(uint32_t reg) { return ATON_CLKCTRL_AGATES0_GET_INTCTRL(reg); } /** * Write the content of the INTCTRL field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INTCTRL field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Set_INTCTRL(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES0_SET_INTCTRL(reg, data); } /* ---------------------------------------------------------- BUSIF0 field of the AGATES0 register ---------------------------------------------------------- */ /** Description of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_DESC "Enable clock of Bus Interface 0" /** Offset of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_LSB 1UL /** Size in bits of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_W (1UL) /** Mask for retrieving the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_DT 0x0UL /** Access rights of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_AC "RW" /** Check whether access to the BUSIF0 field of the AGATES0 register is secured or not. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_S 0 /** Check whether access to the BUSIF0 field of the AGATES0 register is privileged or not. */ #define ATON_CLKCTRL_AGATES0_BUSIF0_P 0 /** Read the content of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_GET_BUSIF0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF0_LSB, ATON_CLKCTRL_AGATES0_BUSIF0_W) /** Modify the content of the BUSIF0 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_SET_BUSIF0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF0_LSB, ATON_CLKCTRL_AGATES0_BUSIF0_W, DATA) /** * Get the description of the BUSIF0 field of AGATES0 register. * * \return the description of the BUSIF0 field of AGATES0 register */ static inline const int8_t *ATON_CLKCTRL_AGATES0_BUSIF0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES0_BUSIF0_DESC; } /** * Read the content of the BUSIF0 field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * * \return the content of the BUSIF0 field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Get_BUSIF0(uint32_t reg) { return ATON_CLKCTRL_AGATES0_GET_BUSIF0(reg); } /** * Write the content of the BUSIF0 field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSIF0 field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Set_BUSIF0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES0_SET_BUSIF0(reg, data); } /* ---------------------------------------------------------- BUSIF1 field of the AGATES0 register ---------------------------------------------------------- */ /** Description of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_DESC "Enable clock of Bus Interface 1" /** Offset of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_LSB 2UL /** Size in bits of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_W (1UL) /** Mask for retrieving the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_DT 0x0UL /** Access rights of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_AC "RW" /** Check whether access to the BUSIF1 field of the AGATES0 register is secured or not. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_S 0 /** Check whether access to the BUSIF1 field of the AGATES0 register is privileged or not. */ #define ATON_CLKCTRL_AGATES0_BUSIF1_P 0 /** Read the content of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_GET_BUSIF1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF1_LSB, ATON_CLKCTRL_AGATES0_BUSIF1_W) /** Modify the content of the BUSIF1 field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_SET_BUSIF1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_BUSIF1_LSB, ATON_CLKCTRL_AGATES0_BUSIF1_W, DATA) /** * Get the description of the BUSIF1 field of AGATES0 register. * * \return the description of the BUSIF1 field of AGATES0 register */ static inline const int8_t *ATON_CLKCTRL_AGATES0_BUSIF1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES0_BUSIF1_DESC; } /** * Read the content of the BUSIF1 field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * * \return the content of the BUSIF1 field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Get_BUSIF1(uint32_t reg) { return ATON_CLKCTRL_AGATES0_GET_BUSIF1(reg); } /** * Write the content of the BUSIF1 field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSIF1 field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Set_BUSIF1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES0_SET_BUSIF1(reg, data); } /* -------------------------------------------------------- STRSWITCH field of the AGATES0 register --------------------------------------------------------- */ /** Description of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_DESC "Enable clock of Stream Switch" /** Offset of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_LSB 3UL /** Size in bits of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_W (1UL) /** Mask for retrieving the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_DT 0x0UL /** Access rights of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_AC "RW" /** Check whether access to the STRSWITCH field of the AGATES0 register is secured or not. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_S 0 /** Check whether access to the STRSWITCH field of the AGATES0 register is privileged or not. */ #define ATON_CLKCTRL_AGATES0_STRSWITCH_P 0 /** Read the content of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_GET_STRSWITCH(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES0_STRSWITCH_LSB, ATON_CLKCTRL_AGATES0_STRSWITCH_W) /** Modify the content of the STRSWITCH field of the AGATES0 register. */ #define ATON_CLKCTRL_AGATES0_SET_STRSWITCH(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES0_STRSWITCH_LSB, ATON_CLKCTRL_AGATES0_STRSWITCH_W, DATA) /** * Get the description of the STRSWITCH field of AGATES0 register. * * \return the description of the STRSWITCH field of AGATES0 register */ static inline const int8_t *ATON_CLKCTRL_AGATES0_STRSWITCH_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES0_STRSWITCH_DESC; } /** * Read the content of the STRSWITCH field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * * \return the content of the STRSWITCH field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Get_STRSWITCH(uint32_t reg) { return ATON_CLKCTRL_AGATES0_GET_STRSWITCH(reg); } /** * Write the content of the STRSWITCH field of the AGATES0 register. * * \param[in] reg is the value of the AGATES0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRSWITCH field belonging to AGATES0 register */ static inline uint32_t ATON_CLKCTRL_AGATES0_Set_STRSWITCH(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES0_SET_STRSWITCH(reg, data); } /* ****************************************************** AGATES1 register of one of the CLKCTRL Units ****************************************************** */ /** Offset of the AGATES1 register from the base address of the CLKCTRL Unit. */ #define ATON_CLKCTRL_AGATES1_OFFSET 0xcUL /** Reset value of the AGATES1 register of the CLKCTRL Unit. */ #define ATON_CLKCTRL_AGATES1_DT \ (ATON_CLKCTRL_AGATES1_INTCTRL_DT << ATON_CLKCTRL_AGATES1_INTCTRL_LSB) | \ (ATON_CLKCTRL_AGATES1_BUSIF0_DT << ATON_CLKCTRL_AGATES1_BUSIF0_LSB) | \ (ATON_CLKCTRL_AGATES1_BUSIF1_DT << ATON_CLKCTRL_AGATES1_BUSIF1_LSB) | \ (ATON_CLKCTRL_AGATES1_STRSWITCH_DT << ATON_CLKCTRL_AGATES1_STRSWITCH_LSB) /** Description of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_DESC "Copy of AGATES0 register" /** Address of the AGATES1 register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_AGATES1_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_AGATES1_OFFSET) /** Get the content of the AGATES1 register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_AGATES1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES1_ADDR(UNIT))) /** Set the content of the AGATES1 register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_AGATES1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_AGATES1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of AGATES1 register. * * \return the description of AGATES1 register */ static inline const int8_t *ATON_CLKCTRL_AGATES1_GetDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES1_DESC; } /** * Get the offset of the AGATES1 register. * * \return the offset of AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_GetOffset(void) { return ATON_CLKCTRL_AGATES1_OFFSET; } /** * Get the address of the AGATES1 register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of AGATES1 register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_AGATES1_GetAddr(uint32_t instance) { return ATON_CLKCTRL_AGATES1_ADDR(instance); } /** * Read the content of the AGATES1 register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of AGATES1 register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_AGATES1_Get(uint32_t instance) { return ATON_CLKCTRL_AGATES1_GET(instance); } /** * Write the content of the AGATES1 register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the AGATES1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CLKCTRL_AGATES1_Set(uint32_t instance, uint32_t data) { ATON_CLKCTRL_AGATES1_SET(instance, data); } /* --------------------------------------------------------- INTCTRL field of the AGATES1 register ---------------------------------------------------------- */ /** Description of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_DESC "Enable clock of Interrupt Controller" /** Offset of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_LSB 0UL /** Size in bits of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_W (1UL) /** Mask for retrieving the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_DT 0x0UL /** Access rights of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_AC "RW" /** Check whether access to the INTCTRL field of the AGATES1 register is secured or not. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_S 0 /** Check whether access to the INTCTRL field of the AGATES1 register is privileged or not. */ #define ATON_CLKCTRL_AGATES1_INTCTRL_P 0 /** Read the content of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_GET_INTCTRL(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_INTCTRL_LSB, ATON_CLKCTRL_AGATES1_INTCTRL_W) /** Modify the content of the INTCTRL field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_SET_INTCTRL(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_INTCTRL_LSB, ATON_CLKCTRL_AGATES1_INTCTRL_W, DATA) /** * Get the description of the INTCTRL field of AGATES1 register. * * \return the description of the INTCTRL field of AGATES1 register */ static inline const int8_t *ATON_CLKCTRL_AGATES1_INTCTRL_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES1_INTCTRL_DESC; } /** * Read the content of the INTCTRL field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * * \return the content of the INTCTRL field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Get_INTCTRL(uint32_t reg) { return ATON_CLKCTRL_AGATES1_GET_INTCTRL(reg); } /** * Write the content of the INTCTRL field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INTCTRL field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Set_INTCTRL(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES1_SET_INTCTRL(reg, data); } /* ---------------------------------------------------------- BUSIF0 field of the AGATES1 register ---------------------------------------------------------- */ /** Description of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_DESC "Enable clock of Bus Interface 0" /** Offset of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_LSB 1UL /** Size in bits of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_W (1UL) /** Mask for retrieving the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_DT 0x0UL /** Access rights of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_AC "RW" /** Check whether access to the BUSIF0 field of the AGATES1 register is secured or not. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_S 0 /** Check whether access to the BUSIF0 field of the AGATES1 register is privileged or not. */ #define ATON_CLKCTRL_AGATES1_BUSIF0_P 0 /** Read the content of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_GET_BUSIF0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF0_LSB, ATON_CLKCTRL_AGATES1_BUSIF0_W) /** Modify the content of the BUSIF0 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_SET_BUSIF0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF0_LSB, ATON_CLKCTRL_AGATES1_BUSIF0_W, DATA) /** * Get the description of the BUSIF0 field of AGATES1 register. * * \return the description of the BUSIF0 field of AGATES1 register */ static inline const int8_t *ATON_CLKCTRL_AGATES1_BUSIF0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES1_BUSIF0_DESC; } /** * Read the content of the BUSIF0 field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * * \return the content of the BUSIF0 field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Get_BUSIF0(uint32_t reg) { return ATON_CLKCTRL_AGATES1_GET_BUSIF0(reg); } /** * Write the content of the BUSIF0 field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSIF0 field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Set_BUSIF0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES1_SET_BUSIF0(reg, data); } /* ---------------------------------------------------------- BUSIF1 field of the AGATES1 register ---------------------------------------------------------- */ /** Description of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_DESC "Enable clock of Bus Interface 1" /** Offset of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_LSB 2UL /** Size in bits of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_W (1UL) /** Mask for retrieving the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_DT 0x0UL /** Access rights of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_AC "RW" /** Check whether access to the BUSIF1 field of the AGATES1 register is secured or not. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_S 0 /** Check whether access to the BUSIF1 field of the AGATES1 register is privileged or not. */ #define ATON_CLKCTRL_AGATES1_BUSIF1_P 0 /** Read the content of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_GET_BUSIF1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF1_LSB, ATON_CLKCTRL_AGATES1_BUSIF1_W) /** Modify the content of the BUSIF1 field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_SET_BUSIF1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_BUSIF1_LSB, ATON_CLKCTRL_AGATES1_BUSIF1_W, DATA) /** * Get the description of the BUSIF1 field of AGATES1 register. * * \return the description of the BUSIF1 field of AGATES1 register */ static inline const int8_t *ATON_CLKCTRL_AGATES1_BUSIF1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES1_BUSIF1_DESC; } /** * Read the content of the BUSIF1 field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * * \return the content of the BUSIF1 field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Get_BUSIF1(uint32_t reg) { return ATON_CLKCTRL_AGATES1_GET_BUSIF1(reg); } /** * Write the content of the BUSIF1 field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSIF1 field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Set_BUSIF1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES1_SET_BUSIF1(reg, data); } /* -------------------------------------------------------- STRSWITCH field of the AGATES1 register --------------------------------------------------------- */ /** Description of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_DESC "Enable clock of Stream Switch" /** Offset of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_LSB 3UL /** Size in bits of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_W (1UL) /** Mask for retrieving the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_DT 0x0UL /** Access rights of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_AC "RW" /** Check whether access to the STRSWITCH field of the AGATES1 register is secured or not. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_S 0 /** Check whether access to the STRSWITCH field of the AGATES1 register is privileged or not. */ #define ATON_CLKCTRL_AGATES1_STRSWITCH_P 0 /** Read the content of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_GET_STRSWITCH(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_AGATES1_STRSWITCH_LSB, ATON_CLKCTRL_AGATES1_STRSWITCH_W) /** Modify the content of the STRSWITCH field of the AGATES1 register. */ #define ATON_CLKCTRL_AGATES1_SET_STRSWITCH(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_AGATES1_STRSWITCH_LSB, ATON_CLKCTRL_AGATES1_STRSWITCH_W, DATA) /** * Get the description of the STRSWITCH field of AGATES1 register. * * \return the description of the STRSWITCH field of AGATES1 register */ static inline const int8_t *ATON_CLKCTRL_AGATES1_STRSWITCH_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_AGATES1_STRSWITCH_DESC; } /** * Read the content of the STRSWITCH field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * * \return the content of the STRSWITCH field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Get_STRSWITCH(uint32_t reg) { return ATON_CLKCTRL_AGATES1_GET_STRSWITCH(reg); } /** * Write the content of the STRSWITCH field of the AGATES1 register. * * \param[in] reg is the value of the AGATES1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRSWITCH field belonging to AGATES1 register */ static inline uint32_t ATON_CLKCTRL_AGATES1_Set_STRSWITCH(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_AGATES1_SET_STRSWITCH(reg, data); } /* ****************************************************** BGATES register of one of the CLKCTRL Units ******************************************************* */ /** Offset of the BGATES register from the base address of the CLKCTRL Unit. */ #define ATON_CLKCTRL_BGATES_OFFSET 0x10UL /** Reset value of the BGATES register of the CLKCTRL Unit. */ #define ATON_CLKCTRL_BGATES_DT \ (ATON_CLKCTRL_BGATES_STRENG0_DT << ATON_CLKCTRL_BGATES_STRENG0_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG1_DT << ATON_CLKCTRL_BGATES_STRENG1_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG2_DT << ATON_CLKCTRL_BGATES_STRENG2_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG3_DT << ATON_CLKCTRL_BGATES_STRENG3_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG4_DT << ATON_CLKCTRL_BGATES_STRENG4_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG5_DT << ATON_CLKCTRL_BGATES_STRENG5_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG6_DT << ATON_CLKCTRL_BGATES_STRENG6_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG7_DT << ATON_CLKCTRL_BGATES_STRENG7_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG8_DT << ATON_CLKCTRL_BGATES_STRENG8_LSB) | \ (ATON_CLKCTRL_BGATES_STRENG9_DT << ATON_CLKCTRL_BGATES_STRENG9_LSB) | \ (ATON_CLKCTRL_BGATES_CONVACC0_DT << ATON_CLKCTRL_BGATES_CONVACC0_LSB) | \ (ATON_CLKCTRL_BGATES_CONVACC1_DT << ATON_CLKCTRL_BGATES_CONVACC1_LSB) | \ (ATON_CLKCTRL_BGATES_CONVACC2_DT << ATON_CLKCTRL_BGATES_CONVACC2_LSB) | \ (ATON_CLKCTRL_BGATES_CONVACC3_DT << ATON_CLKCTRL_BGATES_CONVACC3_LSB) | \ (ATON_CLKCTRL_BGATES_DECUN0_DT << ATON_CLKCTRL_BGATES_DECUN0_LSB) | \ (ATON_CLKCTRL_BGATES_DECUN1_DT << ATON_CLKCTRL_BGATES_DECUN1_LSB) | \ (ATON_CLKCTRL_BGATES_ACTIV0_DT << ATON_CLKCTRL_BGATES_ACTIV0_LSB) | \ (ATON_CLKCTRL_BGATES_ACTIV1_DT << ATON_CLKCTRL_BGATES_ACTIV1_LSB) | \ (ATON_CLKCTRL_BGATES_ARITH0_DT << ATON_CLKCTRL_BGATES_ARITH0_LSB) | \ (ATON_CLKCTRL_BGATES_ARITH1_DT << ATON_CLKCTRL_BGATES_ARITH1_LSB) | \ (ATON_CLKCTRL_BGATES_ARITH2_DT << ATON_CLKCTRL_BGATES_ARITH2_LSB) | \ (ATON_CLKCTRL_BGATES_ARITH3_DT << ATON_CLKCTRL_BGATES_ARITH3_LSB) | \ (ATON_CLKCTRL_BGATES_POOL0_DT << ATON_CLKCTRL_BGATES_POOL0_LSB) | \ (ATON_CLKCTRL_BGATES_POOL1_DT << ATON_CLKCTRL_BGATES_POOL1_LSB) | \ (ATON_CLKCTRL_BGATES_RECBUF0_DT << ATON_CLKCTRL_BGATES_RECBUF0_LSB) | \ (ATON_CLKCTRL_BGATES_EPOCHCTRL0_DT << ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB) | \ (ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DT << ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB) /** Description of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DESC "Clock enable bits register for B clocks" /** Address of the BGATES register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_BGATES_ADDR(UNIT) (ATON_CLKCTRL_BASE(UNIT) + ATON_CLKCTRL_BGATES_OFFSET) /** Get the content of the BGATES register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_BGATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_BGATES_ADDR(UNIT))) /** Set the content of the BGATES register of one of the CLKCTRL Units. */ #define ATON_CLKCTRL_BGATES_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CLKCTRL_BGATES_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of BGATES register. * * \return the description of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_GetDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_DESC; } /** * Get the offset of the BGATES register. * * \return the offset of BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_GetOffset(void) { return ATON_CLKCTRL_BGATES_OFFSET; } /** * Get the address of the BGATES register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the BGATES register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of BGATES register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_BGATES_GetAddr(uint32_t instance) { return ATON_CLKCTRL_BGATES_ADDR(instance); } /** * Read the content of the BGATES register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the BGATES register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of BGATES register belonging to Unit having index \e instance among the CLKCTRL Units */ static inline uint32_t ATON_CLKCTRL_BGATES_Get(uint32_t instance) { return ATON_CLKCTRL_BGATES_GET(instance); } /** * Write the content of the BGATES register. * * \param[in] instance is the index of the Unit (among the CLKCTRL Units) containing the BGATES register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CLKCTRL_BGATES_Set(uint32_t instance, uint32_t data) { ATON_CLKCTRL_BGATES_SET(instance, data); } /* ---------------------------------------------------------- STRENG0 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG0_DESC "Enable clock of Stream Engine 0" /** Offset of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG0_LSB 0UL /** Size in bits of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG0_W (1UL) /** Mask for retrieving the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG0_DT 0x0UL /** Access rights of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG0_AC "RW" /** Check whether access to the STRENG0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG0_S 0 /** Check whether access to the STRENG0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG0_P 0 /** Read the content of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG0_LSB, ATON_CLKCTRL_BGATES_STRENG0_W) /** Modify the content of the STRENG0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG0_LSB, ATON_CLKCTRL_BGATES_STRENG0_W, DATA) /** * Get the description of the STRENG0 field of BGATES register. * * \return the description of the STRENG0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG0_DESC; } /** * Read the content of the STRENG0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG0(reg); } /** * Write the content of the STRENG0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG0(reg, data); } /* ---------------------------------------------------------- STRENG1 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG1_DESC "Enable clock of Stream Engine 1" /** Offset of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG1_LSB 1UL /** Size in bits of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG1_W (1UL) /** Mask for retrieving the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG1_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG1_DT 0x0UL /** Access rights of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG1_AC "RW" /** Check whether access to the STRENG1 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG1_S 0 /** Check whether access to the STRENG1 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG1_P 0 /** Read the content of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG1_LSB, ATON_CLKCTRL_BGATES_STRENG1_W) /** Modify the content of the STRENG1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG1_LSB, ATON_CLKCTRL_BGATES_STRENG1_W, DATA) /** * Get the description of the STRENG1 field of BGATES register. * * \return the description of the STRENG1 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG1_DESC; } /** * Read the content of the STRENG1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG1(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG1(reg); } /** * Write the content of the STRENG1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG1(reg, data); } /* ---------------------------------------------------------- STRENG2 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG2_DESC "Enable clock of Stream Engine 2" /** Offset of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG2_LSB 2UL /** Size in bits of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG2_W (1UL) /** Mask for retrieving the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG2_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG2_DT 0x0UL /** Access rights of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG2_AC "RW" /** Check whether access to the STRENG2 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG2_S 0 /** Check whether access to the STRENG2 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG2_P 0 /** Read the content of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG2(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG2_LSB, ATON_CLKCTRL_BGATES_STRENG2_W) /** Modify the content of the STRENG2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG2(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG2_LSB, ATON_CLKCTRL_BGATES_STRENG2_W, DATA) /** * Get the description of the STRENG2 field of BGATES register. * * \return the description of the STRENG2 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG2_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG2_DESC; } /** * Read the content of the STRENG2 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG2 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG2(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG2(reg); } /** * Write the content of the STRENG2 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG2 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG2(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG2(reg, data); } /* ---------------------------------------------------------- STRENG3 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG3_DESC "Enable clock of Stream Engine 3" /** Offset of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG3_LSB 3UL /** Size in bits of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG3_W (1UL) /** Mask for retrieving the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG3_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG3_DT 0x0UL /** Access rights of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG3_AC "RW" /** Check whether access to the STRENG3 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG3_S 0 /** Check whether access to the STRENG3 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG3_P 0 /** Read the content of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG3(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG3_LSB, ATON_CLKCTRL_BGATES_STRENG3_W) /** Modify the content of the STRENG3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG3(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG3_LSB, ATON_CLKCTRL_BGATES_STRENG3_W, DATA) /** * Get the description of the STRENG3 field of BGATES register. * * \return the description of the STRENG3 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG3_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG3_DESC; } /** * Read the content of the STRENG3 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG3 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG3(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG3(reg); } /** * Write the content of the STRENG3 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG3 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG3(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG3(reg, data); } /* ---------------------------------------------------------- STRENG4 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG4_DESC "Enable clock of Stream Engine 4" /** Offset of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG4_LSB 4UL /** Size in bits of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG4_W (1UL) /** Mask for retrieving the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG4_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG4_DT 0x0UL /** Access rights of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG4_AC "RW" /** Check whether access to the STRENG4 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG4_S 0 /** Check whether access to the STRENG4 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG4_P 0 /** Read the content of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG4(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG4_LSB, ATON_CLKCTRL_BGATES_STRENG4_W) /** Modify the content of the STRENG4 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG4(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG4_LSB, ATON_CLKCTRL_BGATES_STRENG4_W, DATA) /** * Get the description of the STRENG4 field of BGATES register. * * \return the description of the STRENG4 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG4_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG4_DESC; } /** * Read the content of the STRENG4 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG4 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG4(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG4(reg); } /** * Write the content of the STRENG4 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG4 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG4(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG4(reg, data); } /* ---------------------------------------------------------- STRENG5 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG5_DESC "Enable clock of Stream Engine 5" /** Offset of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG5_LSB 5UL /** Size in bits of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG5_W (1UL) /** Mask for retrieving the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG5_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG5_DT 0x0UL /** Access rights of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG5_AC "RW" /** Check whether access to the STRENG5 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG5_S 0 /** Check whether access to the STRENG5 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG5_P 0 /** Read the content of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG5(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG5_LSB, ATON_CLKCTRL_BGATES_STRENG5_W) /** Modify the content of the STRENG5 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG5(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG5_LSB, ATON_CLKCTRL_BGATES_STRENG5_W, DATA) /** * Get the description of the STRENG5 field of BGATES register. * * \return the description of the STRENG5 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG5_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG5_DESC; } /** * Read the content of the STRENG5 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG5 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG5(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG5(reg); } /** * Write the content of the STRENG5 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG5 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG5(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG5(reg, data); } /* ---------------------------------------------------------- STRENG6 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG6_DESC "Enable clock of Stream Engine 6" /** Offset of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG6_LSB 6UL /** Size in bits of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG6_W (1UL) /** Mask for retrieving the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG6_MASK ATON_FIELD_MASK(6UL, 1UL) /** Reset value of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG6_DT 0x0UL /** Access rights of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG6_AC "RW" /** Check whether access to the STRENG6 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG6_S 0 /** Check whether access to the STRENG6 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG6_P 0 /** Read the content of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG6(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG6_LSB, ATON_CLKCTRL_BGATES_STRENG6_W) /** Modify the content of the STRENG6 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG6(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG6_LSB, ATON_CLKCTRL_BGATES_STRENG6_W, DATA) /** * Get the description of the STRENG6 field of BGATES register. * * \return the description of the STRENG6 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG6_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG6_DESC; } /** * Read the content of the STRENG6 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG6 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG6(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG6(reg); } /** * Write the content of the STRENG6 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG6 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG6(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG6(reg, data); } /* ---------------------------------------------------------- STRENG7 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG7_DESC "Enable clock of Stream Engine 7" /** Offset of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG7_LSB 7UL /** Size in bits of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG7_W (1UL) /** Mask for retrieving the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG7_MASK ATON_FIELD_MASK(7UL, 1UL) /** Reset value of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG7_DT 0x0UL /** Access rights of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG7_AC "RW" /** Check whether access to the STRENG7 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG7_S 0 /** Check whether access to the STRENG7 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG7_P 0 /** Read the content of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG7(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG7_LSB, ATON_CLKCTRL_BGATES_STRENG7_W) /** Modify the content of the STRENG7 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG7(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG7_LSB, ATON_CLKCTRL_BGATES_STRENG7_W, DATA) /** * Get the description of the STRENG7 field of BGATES register. * * \return the description of the STRENG7 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG7_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG7_DESC; } /** * Read the content of the STRENG7 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG7 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG7(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG7(reg); } /** * Write the content of the STRENG7 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG7 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG7(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG7(reg, data); } /* ---------------------------------------------------------- STRENG8 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG8_DESC "Enable clock of Stream Engine 8" /** Offset of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG8_LSB 8UL /** Size in bits of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG8_W (1UL) /** Mask for retrieving the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG8_MASK ATON_FIELD_MASK(8UL, 1UL) /** Reset value of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG8_DT 0x0UL /** Access rights of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG8_AC "RW" /** Check whether access to the STRENG8 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG8_S 0 /** Check whether access to the STRENG8 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG8_P 0 /** Read the content of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG8(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG8_LSB, ATON_CLKCTRL_BGATES_STRENG8_W) /** Modify the content of the STRENG8 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG8(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG8_LSB, ATON_CLKCTRL_BGATES_STRENG8_W, DATA) /** * Get the description of the STRENG8 field of BGATES register. * * \return the description of the STRENG8 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG8_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG8_DESC; } /** * Read the content of the STRENG8 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG8 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG8(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG8(reg); } /** * Write the content of the STRENG8 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG8 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG8(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG8(reg, data); } /* ---------------------------------------------------------- STRENG9 field of the BGATES register ---------------------------------------------------------- */ /** Description of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG9_DESC "Enable clock of Stream Engine 9" /** Offset of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG9_LSB 9UL /** Size in bits of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG9_W (1UL) /** Mask for retrieving the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG9_MASK ATON_FIELD_MASK(9UL, 1UL) /** Reset value of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG9_DT 0x0UL /** Access rights of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_STRENG9_AC "RW" /** Check whether access to the STRENG9 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_STRENG9_S 0 /** Check whether access to the STRENG9 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_STRENG9_P 0 /** Read the content of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_STRENG9(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG9_LSB, ATON_CLKCTRL_BGATES_STRENG9_W) /** Modify the content of the STRENG9 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_STRENG9(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_STRENG9_LSB, ATON_CLKCTRL_BGATES_STRENG9_W, DATA) /** * Get the description of the STRENG9 field of BGATES register. * * \return the description of the STRENG9 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_STRENG9_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_STRENG9_DESC; } /** * Read the content of the STRENG9 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the STRENG9 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_STRENG9(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_STRENG9(reg); } /** * Write the content of the STRENG9 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STRENG9 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_STRENG9(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_STRENG9(reg, data); } /* --------------------------------------------------------- CONVACC0 field of the BGATES register ---------------------------------------------------------- */ /** Description of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC0_DESC "Enable clock of Convolutional Accelerator 0" /** Offset of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC0_LSB 10UL /** Size in bits of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC0_W (1UL) /** Mask for retrieving the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC0_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC0_DT 0x0UL /** Access rights of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC0_AC "RW" /** Check whether access to the CONVACC0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_CONVACC0_S 0 /** Check whether access to the CONVACC0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_CONVACC0_P 0 /** Read the content of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_CONVACC0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC0_LSB, ATON_CLKCTRL_BGATES_CONVACC0_W) /** Modify the content of the CONVACC0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_CONVACC0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC0_LSB, ATON_CLKCTRL_BGATES_CONVACC0_W, DATA) /** * Get the description of the CONVACC0 field of BGATES register. * * \return the description of the CONVACC0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC0_DESC; } /** * Read the content of the CONVACC0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the CONVACC0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_CONVACC0(reg); } /** * Write the content of the CONVACC0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONVACC0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_CONVACC0(reg, data); } /* --------------------------------------------------------- CONVACC1 field of the BGATES register ---------------------------------------------------------- */ /** Description of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC1_DESC "Enable clock of Convolutional Accelerator 1" /** Offset of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC1_LSB 11UL /** Size in bits of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC1_W (1UL) /** Mask for retrieving the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC1_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC1_DT 0x0UL /** Access rights of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC1_AC "RW" /** Check whether access to the CONVACC1 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_CONVACC1_S 0 /** Check whether access to the CONVACC1 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_CONVACC1_P 0 /** Read the content of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_CONVACC1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC1_LSB, ATON_CLKCTRL_BGATES_CONVACC1_W) /** Modify the content of the CONVACC1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_CONVACC1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC1_LSB, ATON_CLKCTRL_BGATES_CONVACC1_W, DATA) /** * Get the description of the CONVACC1 field of BGATES register. * * \return the description of the CONVACC1 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC1_DESC; } /** * Read the content of the CONVACC1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the CONVACC1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC1(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_CONVACC1(reg); } /** * Write the content of the CONVACC1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONVACC1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_CONVACC1(reg, data); } /* --------------------------------------------------------- CONVACC2 field of the BGATES register ---------------------------------------------------------- */ /** Description of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC2_DESC "Enable clock of Convolutional Accelerator 2" /** Offset of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC2_LSB 12UL /** Size in bits of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC2_W (1UL) /** Mask for retrieving the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC2_MASK ATON_FIELD_MASK(12UL, 1UL) /** Reset value of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC2_DT 0x0UL /** Access rights of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC2_AC "RW" /** Check whether access to the CONVACC2 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_CONVACC2_S 0 /** Check whether access to the CONVACC2 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_CONVACC2_P 0 /** Read the content of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_CONVACC2(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC2_LSB, ATON_CLKCTRL_BGATES_CONVACC2_W) /** Modify the content of the CONVACC2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_CONVACC2(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC2_LSB, ATON_CLKCTRL_BGATES_CONVACC2_W, DATA) /** * Get the description of the CONVACC2 field of BGATES register. * * \return the description of the CONVACC2 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC2_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC2_DESC; } /** * Read the content of the CONVACC2 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the CONVACC2 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC2(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_CONVACC2(reg); } /** * Write the content of the CONVACC2 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONVACC2 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC2(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_CONVACC2(reg, data); } /* --------------------------------------------------------- CONVACC3 field of the BGATES register ---------------------------------------------------------- */ /** Description of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC3_DESC "Enable clock of Convolutional Accelerator 3" /** Offset of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC3_LSB 13UL /** Size in bits of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC3_W (1UL) /** Mask for retrieving the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC3_MASK ATON_FIELD_MASK(13UL, 1UL) /** Reset value of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC3_DT 0x0UL /** Access rights of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_CONVACC3_AC "RW" /** Check whether access to the CONVACC3 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_CONVACC3_S 0 /** Check whether access to the CONVACC3 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_CONVACC3_P 0 /** Read the content of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_CONVACC3(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC3_LSB, ATON_CLKCTRL_BGATES_CONVACC3_W) /** Modify the content of the CONVACC3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_CONVACC3(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_CONVACC3_LSB, ATON_CLKCTRL_BGATES_CONVACC3_W, DATA) /** * Get the description of the CONVACC3 field of BGATES register. * * \return the description of the CONVACC3 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_CONVACC3_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_CONVACC3_DESC; } /** * Read the content of the CONVACC3 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the CONVACC3 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_CONVACC3(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_CONVACC3(reg); } /** * Write the content of the CONVACC3 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONVACC3 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_CONVACC3(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_CONVACC3(reg, data); } /* ---------------------------------------------------------- DECUN0 field of the BGATES register ----------------------------------------------------------- */ /** Description of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN0_DESC "Enable clock of Decompression Unit 0" /** Offset of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN0_LSB 14UL /** Size in bits of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN0_W (1UL) /** Mask for retrieving the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN0_MASK ATON_FIELD_MASK(14UL, 1UL) /** Reset value of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN0_DT 0x0UL /** Access rights of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN0_AC "RW" /** Check whether access to the DECUN0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_DECUN0_S 0 /** Check whether access to the DECUN0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_DECUN0_P 0 /** Read the content of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_DECUN0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN0_LSB, ATON_CLKCTRL_BGATES_DECUN0_W) /** Modify the content of the DECUN0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_DECUN0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN0_LSB, ATON_CLKCTRL_BGATES_DECUN0_W, DATA) /** * Get the description of the DECUN0 field of BGATES register. * * \return the description of the DECUN0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_DECUN0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_DECUN0_DESC; } /** * Read the content of the DECUN0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the DECUN0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_DECUN0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_DECUN0(reg); } /** * Write the content of the DECUN0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DECUN0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_DECUN0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_DECUN0(reg, data); } /* ---------------------------------------------------------- DECUN1 field of the BGATES register ----------------------------------------------------------- */ /** Description of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN1_DESC "Enable clock of Decompression Unit 1" /** Offset of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN1_LSB 15UL /** Size in bits of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN1_W (1UL) /** Mask for retrieving the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN1_MASK ATON_FIELD_MASK(15UL, 1UL) /** Reset value of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN1_DT 0x0UL /** Access rights of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DECUN1_AC "RW" /** Check whether access to the DECUN1 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_DECUN1_S 0 /** Check whether access to the DECUN1 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_DECUN1_P 0 /** Read the content of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_DECUN1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN1_LSB, ATON_CLKCTRL_BGATES_DECUN1_W) /** Modify the content of the DECUN1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_DECUN1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_DECUN1_LSB, ATON_CLKCTRL_BGATES_DECUN1_W, DATA) /** * Get the description of the DECUN1 field of BGATES register. * * \return the description of the DECUN1 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_DECUN1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_DECUN1_DESC; } /** * Read the content of the DECUN1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the DECUN1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_DECUN1(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_DECUN1(reg); } /** * Write the content of the DECUN1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DECUN1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_DECUN1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_DECUN1(reg, data); } /* ---------------------------------------------------------- ACTIV0 field of the BGATES register ----------------------------------------------------------- */ /** Description of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV0_DESC "Enable clock of Activation Accelerator 0" /** Offset of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV0_LSB 16UL /** Size in bits of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV0_W (1UL) /** Mask for retrieving the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV0_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV0_DT 0x0UL /** Access rights of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV0_AC "RW" /** Check whether access to the ACTIV0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_ACTIV0_S 0 /** Check whether access to the ACTIV0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_ACTIV0_P 0 /** Read the content of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_ACTIV0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV0_LSB, ATON_CLKCTRL_BGATES_ACTIV0_W) /** Modify the content of the ACTIV0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_ACTIV0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV0_LSB, ATON_CLKCTRL_BGATES_ACTIV0_W, DATA) /** * Get the description of the ACTIV0 field of BGATES register. * * \return the description of the ACTIV0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_ACTIV0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_ACTIV0_DESC; } /** * Read the content of the ACTIV0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the ACTIV0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_ACTIV0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_ACTIV0(reg); } /** * Write the content of the ACTIV0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ACTIV0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_ACTIV0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_ACTIV0(reg, data); } /* ---------------------------------------------------------- ACTIV1 field of the BGATES register ----------------------------------------------------------- */ /** Description of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV1_DESC "Enable clock of Activation Accelerator 1" /** Offset of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV1_LSB 17UL /** Size in bits of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV1_W (1UL) /** Mask for retrieving the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV1_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV1_DT 0x0UL /** Access rights of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ACTIV1_AC "RW" /** Check whether access to the ACTIV1 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_ACTIV1_S 0 /** Check whether access to the ACTIV1 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_ACTIV1_P 0 /** Read the content of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_ACTIV1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV1_LSB, ATON_CLKCTRL_BGATES_ACTIV1_W) /** Modify the content of the ACTIV1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_ACTIV1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ACTIV1_LSB, ATON_CLKCTRL_BGATES_ACTIV1_W, DATA) /** * Get the description of the ACTIV1 field of BGATES register. * * \return the description of the ACTIV1 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_ACTIV1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_ACTIV1_DESC; } /** * Read the content of the ACTIV1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the ACTIV1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_ACTIV1(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_ACTIV1(reg); } /** * Write the content of the ACTIV1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ACTIV1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_ACTIV1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_ACTIV1(reg, data); } /* ---------------------------------------------------------- ARITH0 field of the BGATES register ----------------------------------------------------------- */ /** Description of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH0_DESC "Enable clock of Arithmetic Accelerator 0" /** Offset of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH0_LSB 18UL /** Size in bits of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH0_W (1UL) /** Mask for retrieving the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH0_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH0_DT 0x0UL /** Access rights of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH0_AC "RW" /** Check whether access to the ARITH0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_ARITH0_S 0 /** Check whether access to the ARITH0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_ARITH0_P 0 /** Read the content of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_ARITH0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH0_LSB, ATON_CLKCTRL_BGATES_ARITH0_W) /** Modify the content of the ARITH0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_ARITH0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH0_LSB, ATON_CLKCTRL_BGATES_ARITH0_W, DATA) /** * Get the description of the ARITH0 field of BGATES register. * * \return the description of the ARITH0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH0_DESC; } /** * Read the content of the ARITH0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the ARITH0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_ARITH0(reg); } /** * Write the content of the ARITH0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ARITH0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_ARITH0(reg, data); } /* ---------------------------------------------------------- ARITH1 field of the BGATES register ----------------------------------------------------------- */ /** Description of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH1_DESC "Enable clock of Arithmetic Accelerator 1" /** Offset of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH1_LSB 19UL /** Size in bits of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH1_W (1UL) /** Mask for retrieving the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH1_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH1_DT 0x0UL /** Access rights of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH1_AC "RW" /** Check whether access to the ARITH1 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_ARITH1_S 0 /** Check whether access to the ARITH1 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_ARITH1_P 0 /** Read the content of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_ARITH1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH1_LSB, ATON_CLKCTRL_BGATES_ARITH1_W) /** Modify the content of the ARITH1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_ARITH1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH1_LSB, ATON_CLKCTRL_BGATES_ARITH1_W, DATA) /** * Get the description of the ARITH1 field of BGATES register. * * \return the description of the ARITH1 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH1_DESC; } /** * Read the content of the ARITH1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the ARITH1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH1(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_ARITH1(reg); } /** * Write the content of the ARITH1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ARITH1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_ARITH1(reg, data); } /* ---------------------------------------------------------- ARITH2 field of the BGATES register ----------------------------------------------------------- */ /** Description of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH2_DESC "Enable clock of Arithmetic Accelerator 2" /** Offset of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH2_LSB 20UL /** Size in bits of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH2_W (1UL) /** Mask for retrieving the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH2_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH2_DT 0x0UL /** Access rights of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH2_AC "RW" /** Check whether access to the ARITH2 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_ARITH2_S 0 /** Check whether access to the ARITH2 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_ARITH2_P 0 /** Read the content of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_ARITH2(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH2_LSB, ATON_CLKCTRL_BGATES_ARITH2_W) /** Modify the content of the ARITH2 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_ARITH2(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH2_LSB, ATON_CLKCTRL_BGATES_ARITH2_W, DATA) /** * Get the description of the ARITH2 field of BGATES register. * * \return the description of the ARITH2 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH2_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH2_DESC; } /** * Read the content of the ARITH2 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the ARITH2 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH2(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_ARITH2(reg); } /** * Write the content of the ARITH2 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ARITH2 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH2(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_ARITH2(reg, data); } /* ---------------------------------------------------------- ARITH3 field of the BGATES register ----------------------------------------------------------- */ /** Description of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH3_DESC "Enable clock of Arithmetic Accelerator 3" /** Offset of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH3_LSB 21UL /** Size in bits of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH3_W (1UL) /** Mask for retrieving the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH3_MASK ATON_FIELD_MASK(21UL, 1UL) /** Reset value of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH3_DT 0x0UL /** Access rights of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_ARITH3_AC "RW" /** Check whether access to the ARITH3 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_ARITH3_S 0 /** Check whether access to the ARITH3 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_ARITH3_P 0 /** Read the content of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_ARITH3(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH3_LSB, ATON_CLKCTRL_BGATES_ARITH3_W) /** Modify the content of the ARITH3 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_ARITH3(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_ARITH3_LSB, ATON_CLKCTRL_BGATES_ARITH3_W, DATA) /** * Get the description of the ARITH3 field of BGATES register. * * \return the description of the ARITH3 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_ARITH3_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_ARITH3_DESC; } /** * Read the content of the ARITH3 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the ARITH3 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_ARITH3(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_ARITH3(reg); } /** * Write the content of the ARITH3 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ARITH3 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_ARITH3(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_ARITH3(reg, data); } /* ----------------------------------------------------------- POOL0 field of the BGATES register ----------------------------------------------------------- */ /** Description of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL0_DESC "Enable clock of Pooling Accelerator 0" /** Offset of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL0_LSB 22UL /** Size in bits of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL0_W (1UL) /** Mask for retrieving the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL0_MASK ATON_FIELD_MASK(22UL, 1UL) /** Reset value of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL0_DT 0x0UL /** Access rights of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL0_AC "RW" /** Check whether access to the POOL0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_POOL0_S 0 /** Check whether access to the POOL0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_POOL0_P 0 /** Read the content of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_POOL0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL0_LSB, ATON_CLKCTRL_BGATES_POOL0_W) /** Modify the content of the POOL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_POOL0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL0_LSB, ATON_CLKCTRL_BGATES_POOL0_W, DATA) /** * Get the description of the POOL0 field of BGATES register. * * \return the description of the POOL0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_POOL0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_POOL0_DESC; } /** * Read the content of the POOL0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the POOL0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_POOL0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_POOL0(reg); } /** * Write the content of the POOL0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the POOL0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_POOL0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_POOL0(reg, data); } /* ----------------------------------------------------------- POOL1 field of the BGATES register ----------------------------------------------------------- */ /** Description of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL1_DESC "Enable clock of Pooling Accelerator 1" /** Offset of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL1_LSB 23UL /** Size in bits of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL1_W (1UL) /** Mask for retrieving the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL1_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL1_DT 0x0UL /** Access rights of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_POOL1_AC "RW" /** Check whether access to the POOL1 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_POOL1_S 0 /** Check whether access to the POOL1 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_POOL1_P 0 /** Read the content of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_POOL1(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL1_LSB, ATON_CLKCTRL_BGATES_POOL1_W) /** Modify the content of the POOL1 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_POOL1(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_POOL1_LSB, ATON_CLKCTRL_BGATES_POOL1_W, DATA) /** * Get the description of the POOL1 field of BGATES register. * * \return the description of the POOL1 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_POOL1_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_POOL1_DESC; } /** * Read the content of the POOL1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the POOL1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_POOL1(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_POOL1(reg); } /** * Write the content of the POOL1 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the POOL1 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_POOL1(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_POOL1(reg, data); } /* ---------------------------------------------------------- RECBUF0 field of the BGATES register ---------------------------------------------------------- */ /** Description of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_RECBUF0_DESC "Enable clock of Reconfigurable Buffer 0" /** Offset of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_RECBUF0_LSB 24UL /** Size in bits of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_RECBUF0_W (1UL) /** Mask for retrieving the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_RECBUF0_MASK ATON_FIELD_MASK(24UL, 1UL) /** Reset value of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_RECBUF0_DT 0x0UL /** Access rights of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_RECBUF0_AC "RW" /** Check whether access to the RECBUF0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_RECBUF0_S 0 /** Check whether access to the RECBUF0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_RECBUF0_P 0 /** Read the content of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_RECBUF0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_RECBUF0_LSB, ATON_CLKCTRL_BGATES_RECBUF0_W) /** Modify the content of the RECBUF0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_RECBUF0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_RECBUF0_LSB, ATON_CLKCTRL_BGATES_RECBUF0_W, DATA) /** * Get the description of the RECBUF0 field of BGATES register. * * \return the description of the RECBUF0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_RECBUF0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_RECBUF0_DESC; } /** * Read the content of the RECBUF0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the RECBUF0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_RECBUF0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_RECBUF0(reg); } /** * Write the content of the RECBUF0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RECBUF0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_RECBUF0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_RECBUF0(reg, data); } /* -------------------------------------------------------- EPOCHCTRL0 field of the BGATES register --------------------------------------------------------- */ /** Description of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_DESC "Enable clock of Epoch Controller 0" /** Offset of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB 25UL /** Size in bits of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_W (1UL) /** Mask for retrieving the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_MASK ATON_FIELD_MASK(25UL, 1UL) /** Reset value of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_DT 0x0UL /** Access rights of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_AC "RW" /** Check whether access to the EPOCHCTRL0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_S 0 /** Check whether access to the EPOCHCTRL0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_EPOCHCTRL0_P 0 /** Read the content of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_EPOCHCTRL0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB, ATON_CLKCTRL_BGATES_EPOCHCTRL0_W) /** Modify the content of the EPOCHCTRL0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_EPOCHCTRL0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_EPOCHCTRL0_LSB, ATON_CLKCTRL_BGATES_EPOCHCTRL0_W, DATA) /** * Get the description of the EPOCHCTRL0 field of BGATES register. * * \return the description of the EPOCHCTRL0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_EPOCHCTRL0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_EPOCHCTRL0_DESC; } /** * Read the content of the EPOCHCTRL0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the EPOCHCTRL0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_EPOCHCTRL0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_EPOCHCTRL0(reg); } /** * Write the content of the EPOCHCTRL0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EPOCHCTRL0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_EPOCHCTRL0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_EPOCHCTRL0(reg, data); } /* ------------------------------------------------------- DEBUG_TRACE0 field of the BGATES register -------------------------------------------------------- */ /** Description of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DESC "Enable clock of Debug Trace 0" /** Offset of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB 26UL /** Size in bits of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_W (1UL) /** Mask for retrieving the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_MASK ATON_FIELD_MASK(26UL, 1UL) /** Reset value of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DT 0x0UL /** Access rights of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_AC "RW" /** Check whether access to the DEBUG_TRACE0 field of the BGATES register is secured or not. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_S 0 /** Check whether access to the DEBUG_TRACE0 field of the BGATES register is privileged or not. */ #define ATON_CLKCTRL_BGATES_DEBUG_TRACE0_P 0 /** Read the content of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_GET_DEBUG_TRACE0(REG) ATON_GET_FIELD(REG, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_W) /** Modify the content of the DEBUG_TRACE0 field of the BGATES register. */ #define ATON_CLKCTRL_BGATES_SET_DEBUG_TRACE0(REG, DATA) ATON_SET_FIELD(REG, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_LSB, ATON_CLKCTRL_BGATES_DEBUG_TRACE0_W, DATA) /** * Get the description of the DEBUG_TRACE0 field of BGATES register. * * \return the description of the DEBUG_TRACE0 field of BGATES register */ static inline const int8_t *ATON_CLKCTRL_BGATES_DEBUG_TRACE0_GetdDesc(void) { return (const int8_t *)ATON_CLKCTRL_BGATES_DEBUG_TRACE0_DESC; } /** * Read the content of the DEBUG_TRACE0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * * \return the content of the DEBUG_TRACE0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Get_DEBUG_TRACE0(uint32_t reg) { return ATON_CLKCTRL_BGATES_GET_DEBUG_TRACE0(reg); } /** * Write the content of the DEBUG_TRACE0 field of the BGATES register. * * \param[in] reg is the value of the BGATES register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DEBUG_TRACE0 field belonging to BGATES register */ static inline uint32_t ATON_CLKCTRL_BGATES_Set_DEBUG_TRACE0(uint32_t reg, uint32_t data) { return ATON_CLKCTRL_BGATES_SET_DEBUG_TRACE0(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* INTCTRL Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of INTCTRL Unit instances. */ #define ATON_INTCTRL_NUM 1 /** * \name Structures, macros and functions of the INTCTRL Units */ /*@{*/ /** * Registers of the INTCTRL Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e INTREG register (Interrupt register). */ uint32_t INTREG; /** \e INTSET register (Set interrupts). */ uint32_t INTSET; /** \e INTCLR register (Clear interrupts). */ uint32_t INTCLR; /** \e INTORMSK0 register (Interrupt OR mask 0). */ uint32_t INTORMSK0; /** \e INTORMSK1 register (Interrupt OR mask 1). */ uint32_t INTORMSK1; /** \e INTORMSK2 register (Interrupt OR mask 2). */ uint32_t INTORMSK2; /** \e INTORMSK3 register (Interrupt OR mask 3). */ uint32_t INTORMSK3; /** \e INTANDMSK0 register (Interrupt AND mask 0). */ uint32_t INTANDMSK0; /** \e INTANDMSK1 register (Interrupt AND mask 1). */ uint32_t INTANDMSK1; /** \e INTANDMSK2 register (Interrupt AND mask 2). */ uint32_t INTANDMSK2; /** \e INTANDMSK3 register (Interrupt AND mask 3). */ uint32_t INTANDMSK3; } ATON_INTCTRL_t; /** Return the pointer to one of the INTCTRL Units. */ #define ATON_INTCTRL(UNIT) ((ATON_INTCTRL_t *)(intptr_t)ATON_INTCTRL_BASE(UNIT)) /** Name of one of the INTCTRL Units. */ #define ATON_INTCTRL_NAME(UNIT) \ (((UNIT) == 0) ? "INTCTRL" : "") /** Version of the INTCTRL Units. */ #define ATON_INTCTRL_VERSION "1.1" /** Description of one of the INTCTRL Units. */ #define ATON_INTCTRL_DESC(UNIT) \ (((UNIT) == 0) ? "Interrupt Controller" : "") /** Base address of one of the INTCTRL Units. */ #define ATON_INTCTRL_BASE(UNIT) \ (ATON_BASE + 0x1000UL + ((UNIT) * 0x0UL)) /** Size in bytes of the INTCTRL Units. */ #define ATON_INTCTRL_SIZE 0x1000UL /** * Get the name of one of the INTCTRL Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) * * \return the name of Unit having index \e instance among the INTCTRL Units */ static inline const int8_t *ATON_INTCTRL_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"INTCTRL"; break; default: break; } return str; } /** * Get the description of one of the INTCTRL Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) * * \return the description of Unit having index \e instance among the INTCTRL Units */ static inline const int8_t *ATON_INTCTRL_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Interrupt Controller"; break; default: break; } return str; } /** * Get the version of the INTCTRL Units. * * \return the version of the INTCTRL Units */ static inline const int8_t *ATON_INTCTRL_GetVersion(void) { return (const int8_t *)ATON_INTCTRL_VERSION; } /** * Get the base address of one of the INTCTRL Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) * * \return the base address of Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_GetBase(uint32_t instance) { return ATON_INTCTRL_BASE(instance); } /** * Get the size in bytes of the INTCTRL Units. * * \return the size in bytes of the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_GetSize(void) { return ATON_INTCTRL_SIZE; } /* ******************************************************* CTRL register of one of the INTCTRL Units ******************************************************** */ /** Offset of the CTRL register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the INTCTRL Unit. */ #define ATON_INTCTRL_CTRL_DT \ (ATON_INTCTRL_CTRL_EN_DT << ATON_INTCTRL_CTRL_EN_LSB) | \ (ATON_INTCTRL_CTRL_CLR_DT << ATON_INTCTRL_CTRL_CLR_LSB) | \ (ATON_INTCTRL_CTRL_CONFCLR_DT << ATON_INTCTRL_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_INTCTRL_CTRL_DESC "Control register" /** Address of the CTRL register of one of the INTCTRL Units. */ #define ATON_INTCTRL_CTRL_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_CTRL_OFFSET) /** Get the content of the CTRL register of one of the INTCTRL Units. */ #define ATON_INTCTRL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the INTCTRL Units. */ #define ATON_INTCTRL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_INTCTRL_CTRL_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_GetOffset(void) { return ATON_INTCTRL_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the CTRL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_CTRL_GetAddr(uint32_t instance) { return ATON_INTCTRL_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_CTRL_Get(uint32_t instance) { return ATON_INTCTRL_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the CTRL register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_CTRL_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_EN_DESC "Enable the Interrupt Controller" /** Offset of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_INTCTRL_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_INTCTRL_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_CTRL_EN_LSB, ATON_INTCTRL_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_INTCTRL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_CTRL_EN_LSB, ATON_INTCTRL_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_INTCTRL_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_Get_EN(uint32_t reg) { return ATON_INTCTRL_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_INTCTRL_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CLR_DESC "Clear interrupts" /** Offset of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_INTCTRL_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_INTCTRL_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_CTRL_CLR_LSB, ATON_INTCTRL_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_CTRL_CLR_LSB, ATON_INTCTRL_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_INTCTRL_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_Get_CLR(uint32_t reg) { return ATON_INTCTRL_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_INTCTRL_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_INTCTRL_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_INTCTRL_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_CTRL_CONFCLR_LSB, ATON_INTCTRL_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_INTCTRL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_CTRL_CONFCLR_LSB, ATON_INTCTRL_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_INTCTRL_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_INTCTRL_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_INTCTRL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_INTCTRL_CTRL_SET_CONFCLR(reg, data); } /* ****************************************************** VERSION register of one of the INTCTRL Units ****************************************************** */ /** Offset of the VERSION register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the INTCTRL Unit. */ #define ATON_INTCTRL_VERSION_DT \ (ATON_INTCTRL_VERSION_TYPE_DT << ATON_INTCTRL_VERSION_TYPE_LSB) | \ (ATON_INTCTRL_VERSION_MINOR_DT << ATON_INTCTRL_VERSION_MINOR_LSB) | \ (ATON_INTCTRL_VERSION_MAJOR_DT << ATON_INTCTRL_VERSION_MAJOR_LSB) | \ (ATON_INTCTRL_VERSION_NRINTS_DT << ATON_INTCTRL_VERSION_NRINTS_LSB) | \ (ATON_INTCTRL_VERSION_HOSTINTS_DT << ATON_INTCTRL_VERSION_HOSTINTS_LSB) /** Description of the VERSION register. */ #define ATON_INTCTRL_VERSION_DESC "Version register" /** Address of the VERSION register of one of the INTCTRL Units. */ #define ATON_INTCTRL_VERSION_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_VERSION_OFFSET) /** Get the content of the VERSION register of one of the INTCTRL Units. */ #define ATON_INTCTRL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_INTCTRL_VERSION_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_INTCTRL_VERSION_GetOffset(void) { return ATON_INTCTRL_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the VERSION register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_VERSION_GetAddr(uint32_t instance) { return ATON_INTCTRL_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_VERSION_Get(uint32_t instance) { return ATON_INTCTRL_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_TYPE_DT 0x1eUL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_INTCTRL_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_INTCTRL_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_INTCTRL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_TYPE_LSB, ATON_INTCTRL_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_INTCTRL_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_INTCTRL_VERSION_Get_TYPE(uint32_t reg) { return ATON_INTCTRL_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MINOR_DT 0x1UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_INTCTRL_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_INTCTRL_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_MINOR_LSB, ATON_INTCTRL_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_INTCTRL_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_INTCTRL_VERSION_Get_MINOR(uint32_t reg) { return ATON_INTCTRL_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_INTCTRL_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_INTCTRL_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_INTCTRL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_MAJOR_LSB, ATON_INTCTRL_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_INTCTRL_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_INTCTRL_VERSION_Get_MAJOR(uint32_t reg) { return ATON_INTCTRL_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- NRINTS field of the VERSION register ---------------------------------------------------------- */ /** Description of the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_NRINTS_DESC "Number of internal interrupts" /** Offset of the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_NRINTS_LSB 16UL /** Size in bits of the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_NRINTS_W (8UL) /** Mask for retrieving the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_NRINTS_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_NRINTS_DT 0x20UL /** Access rights of the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_NRINTS_AC "R" /** Check whether access to the NRINTS field of the VERSION register is secured or not. */ #define ATON_INTCTRL_VERSION_NRINTS_S 0 /** Check whether access to the NRINTS field of the VERSION register is privileged or not. */ #define ATON_INTCTRL_VERSION_NRINTS_P 0 /** Read the content of the NRINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_GET_NRINTS(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_NRINTS_LSB, ATON_INTCTRL_VERSION_NRINTS_W) /** * Get the description of the NRINTS field of VERSION register. * * \return the description of the NRINTS field of VERSION register */ static inline const int8_t *ATON_INTCTRL_VERSION_NRINTS_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_VERSION_NRINTS_DESC; } /** * Read the content of the NRINTS field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the NRINTS field belonging to VERSION register */ static inline uint32_t ATON_INTCTRL_VERSION_Get_NRINTS(uint32_t reg) { return ATON_INTCTRL_VERSION_GET_NRINTS(reg); } /* --------------------------------------------------------- HOSTINTS field of the VERSION register --------------------------------------------------------- */ /** Description of the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_HOSTINTS_DESC "Number of host interrupt lines" /** Offset of the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_HOSTINTS_LSB 24UL /** Size in bits of the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_HOSTINTS_W (8UL) /** Mask for retrieving the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_HOSTINTS_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_HOSTINTS_DT 0x4UL /** Access rights of the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_HOSTINTS_AC "R" /** Check whether access to the HOSTINTS field of the VERSION register is secured or not. */ #define ATON_INTCTRL_VERSION_HOSTINTS_S 0 /** Check whether access to the HOSTINTS field of the VERSION register is privileged or not. */ #define ATON_INTCTRL_VERSION_HOSTINTS_P 0 /** Read the content of the HOSTINTS field of the VERSION register. */ #define ATON_INTCTRL_VERSION_GET_HOSTINTS(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_VERSION_HOSTINTS_LSB, ATON_INTCTRL_VERSION_HOSTINTS_W) /** * Get the description of the HOSTINTS field of VERSION register. * * \return the description of the HOSTINTS field of VERSION register */ static inline const int8_t *ATON_INTCTRL_VERSION_HOSTINTS_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_VERSION_HOSTINTS_DESC; } /** * Read the content of the HOSTINTS field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the HOSTINTS field belonging to VERSION register */ static inline uint32_t ATON_INTCTRL_VERSION_Get_HOSTINTS(uint32_t reg) { return ATON_INTCTRL_VERSION_GET_HOSTINTS(reg); } /* ****************************************************** INTREG register of one of the INTCTRL Units ******************************************************* */ /** Offset of the INTREG register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTREG_OFFSET 0x8UL /** Reset value of the INTREG register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTREG_DT \ (ATON_INTCTRL_INTREG_REG_DT << ATON_INTCTRL_INTREG_REG_LSB) /** Description of the INTREG register. */ #define ATON_INTCTRL_INTREG_DESC "Interrupt register" /** Address of the INTREG register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTREG_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTREG_OFFSET) /** Get the content of the INTREG register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTREG_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTREG_ADDR(UNIT))) /** * Get the description of INTREG register. * * \return the description of INTREG register */ static inline const int8_t *ATON_INTCTRL_INTREG_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTREG_DESC; } /** * Get the offset of the INTREG register. * * \return the offset of INTREG register */ static inline uint32_t ATON_INTCTRL_INTREG_GetOffset(void) { return ATON_INTCTRL_INTREG_OFFSET; } /** * Get the address of the INTREG register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTREG register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTREG register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTREG_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTREG_ADDR(instance); } /** * Read the content of the INTREG register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTREG register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTREG register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTREG_Get(uint32_t instance) { return ATON_INTCTRL_INTREG_GET(instance); } /* ------------------------------------------------------------ REG field of the INTREG register ------------------------------------------------------------ */ /** Description of the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_REG_DESC "If interrupt X is set, bit X is set" /** Offset of the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_REG_LSB 0UL /** Size in bits of the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_REG_W (32UL) /** Mask for retrieving the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_REG_DT 0x0UL /** Access rights of the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_REG_AC "R" /** Check whether access to the REG field of the INTREG register is secured or not. */ #define ATON_INTCTRL_INTREG_REG_S 0 /** Check whether access to the REG field of the INTREG register is privileged or not. */ #define ATON_INTCTRL_INTREG_REG_P 0 /** Read the content of the REG field of the INTREG register. */ #define ATON_INTCTRL_INTREG_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTREG_REG_LSB, ATON_INTCTRL_INTREG_REG_W) /** * Get the description of the REG field of INTREG register. * * \return the description of the REG field of INTREG register */ static inline const int8_t *ATON_INTCTRL_INTREG_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTREG_REG_DESC; } /** * Read the content of the REG field of the INTREG register. * * \param[in] reg is the value of the INTREG register * * \return the content of the REG field belonging to INTREG register */ static inline uint32_t ATON_INTCTRL_INTREG_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTREG_GET_REG(reg); } /* ****************************************************** INTSET register of one of the INTCTRL Units ******************************************************* */ /** Offset of the INTSET register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTSET_OFFSET 0xcUL /** Reset value of the INTSET register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTSET_DT \ (ATON_INTCTRL_INTSET_REG_DT << ATON_INTCTRL_INTSET_REG_LSB) /** Description of the INTSET register. */ #define ATON_INTCTRL_INTSET_DESC "Set interrupts" /** Address of the INTSET register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTSET_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTSET_OFFSET) /** Get the content of the INTSET register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTSET_ADDR(UNIT))) /** Set the content of the INTSET register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTSET_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTSET register. * * \return the description of INTSET register */ static inline const int8_t *ATON_INTCTRL_INTSET_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTSET_DESC; } /** * Get the offset of the INTSET register. * * \return the offset of INTSET register */ static inline uint32_t ATON_INTCTRL_INTSET_GetOffset(void) { return ATON_INTCTRL_INTSET_OFFSET; } /** * Get the address of the INTSET register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTSET register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTSET register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTSET_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTSET_ADDR(instance); } /** * Read the content of the INTSET register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTSET register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTSET register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTSET_Get(uint32_t instance) { return ATON_INTCTRL_INTSET_GET(instance); } /** * Write the content of the INTSET register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTSET register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTSET_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTSET_SET(instance, data); } /* ------------------------------------------------------------ REG field of the INTSET register ------------------------------------------------------------ */ /** Description of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_REG_DESC "If bit X is set, interrupt X is raised. Reading this register returns same content as INTREG" /** Offset of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_REG_LSB 0UL /** Size in bits of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_REG_W (32UL) /** Mask for retrieving the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_REG_DT 0x0UL /** Access rights of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_REG_AC "RW" /** Check whether access to the REG field of the INTSET register is secured or not. */ #define ATON_INTCTRL_INTSET_REG_S 0 /** Check whether access to the REG field of the INTSET register is privileged or not. */ #define ATON_INTCTRL_INTSET_REG_P 0 /** Read the content of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTSET_REG_LSB, ATON_INTCTRL_INTSET_REG_W) /** Modify the content of the REG field of the INTSET register. */ #define ATON_INTCTRL_INTSET_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTSET_REG_LSB, ATON_INTCTRL_INTSET_REG_W, DATA) /** * Get the description of the REG field of INTSET register. * * \return the description of the REG field of INTSET register */ static inline const int8_t *ATON_INTCTRL_INTSET_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTSET_REG_DESC; } /** * Read the content of the REG field of the INTSET register. * * \param[in] reg is the value of the INTSET register * * \return the content of the REG field belonging to INTSET register */ static inline uint32_t ATON_INTCTRL_INTSET_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTSET_GET_REG(reg); } /** * Write the content of the REG field of the INTSET register. * * \param[in] reg is the value of the INTSET register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTSET register */ static inline uint32_t ATON_INTCTRL_INTSET_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTSET_SET_REG(reg, data); } /* ****************************************************** INTCLR register of one of the INTCTRL Units ******************************************************* */ /** Offset of the INTCLR register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTCLR_OFFSET 0x10UL /** Reset value of the INTCLR register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTCLR_DT \ (ATON_INTCTRL_INTCLR_REG_DT << ATON_INTCTRL_INTCLR_REG_LSB) /** Description of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_DESC "Clear interrupts" /** Address of the INTCLR register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTCLR_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTCLR_OFFSET) /** Get the content of the INTCLR register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTCLR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTCLR_ADDR(UNIT))) /** Set the content of the INTCLR register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTCLR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTCLR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTCLR register. * * \return the description of INTCLR register */ static inline const int8_t *ATON_INTCTRL_INTCLR_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTCLR_DESC; } /** * Get the offset of the INTCLR register. * * \return the offset of INTCLR register */ static inline uint32_t ATON_INTCTRL_INTCLR_GetOffset(void) { return ATON_INTCTRL_INTCLR_OFFSET; } /** * Get the address of the INTCLR register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTCLR register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTCLR register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTCLR_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTCLR_ADDR(instance); } /** * Read the content of the INTCLR register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTCLR register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTCLR register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTCLR_Get(uint32_t instance) { return ATON_INTCTRL_INTCLR_GET(instance); } /** * Write the content of the INTCLR register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTCLR register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTCLR_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTCLR_SET(instance, data); } /* ------------------------------------------------------------ REG field of the INTCLR register ------------------------------------------------------------ */ /** Description of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_REG_DESC "If bit X is set, interrupt X is cleared. Reading this register returns same content as INTREG" /** Offset of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_REG_LSB 0UL /** Size in bits of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_REG_W (32UL) /** Mask for retrieving the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_REG_DT 0x0UL /** Access rights of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_REG_AC "RW" /** Check whether access to the REG field of the INTCLR register is secured or not. */ #define ATON_INTCTRL_INTCLR_REG_S 0 /** Check whether access to the REG field of the INTCLR register is privileged or not. */ #define ATON_INTCTRL_INTCLR_REG_P 0 /** Read the content of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTCLR_REG_LSB, ATON_INTCTRL_INTCLR_REG_W) /** Modify the content of the REG field of the INTCLR register. */ #define ATON_INTCTRL_INTCLR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTCLR_REG_LSB, ATON_INTCTRL_INTCLR_REG_W, DATA) /** * Get the description of the REG field of INTCLR register. * * \return the description of the REG field of INTCLR register */ static inline const int8_t *ATON_INTCTRL_INTCLR_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTCLR_REG_DESC; } /** * Read the content of the REG field of the INTCLR register. * * \param[in] reg is the value of the INTCLR register * * \return the content of the REG field belonging to INTCLR register */ static inline uint32_t ATON_INTCTRL_INTCLR_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTCLR_GET_REG(reg); } /** * Write the content of the REG field of the INTCLR register. * * \param[in] reg is the value of the INTCLR register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTCLR register */ static inline uint32_t ATON_INTCTRL_INTCLR_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTCLR_SET_REG(reg, data); } /* ***************************************************** INTORMSK0 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTORMSK0 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK0_OFFSET 0x14UL /** Reset value of the INTORMSK0 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK0_DT \ (ATON_INTCTRL_INTORMSK0_REG_DT << ATON_INTCTRL_INTORMSK0_REG_LSB) /** Description of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_DESC "Interrupt OR mask 0" /** Address of the INTORMSK0 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK0_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK0_OFFSET) /** Get the content of the INTORMSK0 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK0_ADDR(UNIT))) /** Set the content of the INTORMSK0 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTORMSK0 register. * * \return the description of INTORMSK0 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK0_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK0_DESC; } /** * Get the offset of the INTORMSK0 register. * * \return the offset of INTORMSK0 register */ static inline uint32_t ATON_INTCTRL_INTORMSK0_GetOffset(void) { return ATON_INTCTRL_INTORMSK0_OFFSET; } /** * Get the address of the INTORMSK0 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTORMSK0 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK0_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTORMSK0_ADDR(instance); } /** * Read the content of the INTORMSK0 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTORMSK0 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK0_Get(uint32_t instance) { return ATON_INTCTRL_INTORMSK0_GET(instance); } /** * Write the content of the INTORMSK0 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTORMSK0_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTORMSK0_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTORMSK0 register ----------------------------------------------------------- */ /** Description of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" /** Offset of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_REG_LSB 0UL /** Size in bits of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_REG_W (32UL) /** Mask for retrieving the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_REG_AC "RW" /** Check whether access to the REG field of the INTORMSK0 register is secured or not. */ #define ATON_INTCTRL_INTORMSK0_REG_S 0 /** Check whether access to the REG field of the INTORMSK0 register is privileged or not. */ #define ATON_INTCTRL_INTORMSK0_REG_P 0 /** Read the content of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK0_REG_LSB, ATON_INTCTRL_INTORMSK0_REG_W) /** Modify the content of the REG field of the INTORMSK0 register. */ #define ATON_INTCTRL_INTORMSK0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK0_REG_LSB, ATON_INTCTRL_INTORMSK0_REG_W, DATA) /** * Get the description of the REG field of INTORMSK0 register. * * \return the description of the REG field of INTORMSK0 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK0_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK0_REG_DESC; } /** * Read the content of the REG field of the INTORMSK0 register. * * \param[in] reg is the value of the INTORMSK0 register * * \return the content of the REG field belonging to INTORMSK0 register */ static inline uint32_t ATON_INTCTRL_INTORMSK0_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTORMSK0_GET_REG(reg); } /** * Write the content of the REG field of the INTORMSK0 register. * * \param[in] reg is the value of the INTORMSK0 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTORMSK0 register */ static inline uint32_t ATON_INTCTRL_INTORMSK0_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTORMSK0_SET_REG(reg, data); } /* ***************************************************** INTORMSK1 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTORMSK1 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK1_OFFSET 0x18UL /** Reset value of the INTORMSK1 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK1_DT \ (ATON_INTCTRL_INTORMSK1_REG_DT << ATON_INTCTRL_INTORMSK1_REG_LSB) /** Description of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_DESC "Interrupt OR mask 1" /** Address of the INTORMSK1 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK1_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK1_OFFSET) /** Get the content of the INTORMSK1 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK1_ADDR(UNIT))) /** Set the content of the INTORMSK1 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTORMSK1 register. * * \return the description of INTORMSK1 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK1_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK1_DESC; } /** * Get the offset of the INTORMSK1 register. * * \return the offset of INTORMSK1 register */ static inline uint32_t ATON_INTCTRL_INTORMSK1_GetOffset(void) { return ATON_INTCTRL_INTORMSK1_OFFSET; } /** * Get the address of the INTORMSK1 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTORMSK1 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK1_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTORMSK1_ADDR(instance); } /** * Read the content of the INTORMSK1 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTORMSK1 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK1_Get(uint32_t instance) { return ATON_INTCTRL_INTORMSK1_GET(instance); } /** * Write the content of the INTORMSK1 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTORMSK1_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTORMSK1_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTORMSK1 register ----------------------------------------------------------- */ /** Description of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" /** Offset of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_REG_LSB 0UL /** Size in bits of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_REG_W (32UL) /** Mask for retrieving the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_REG_AC "RW" /** Check whether access to the REG field of the INTORMSK1 register is secured or not. */ #define ATON_INTCTRL_INTORMSK1_REG_S 0 /** Check whether access to the REG field of the INTORMSK1 register is privileged or not. */ #define ATON_INTCTRL_INTORMSK1_REG_P 0 /** Read the content of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK1_REG_LSB, ATON_INTCTRL_INTORMSK1_REG_W) /** Modify the content of the REG field of the INTORMSK1 register. */ #define ATON_INTCTRL_INTORMSK1_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK1_REG_LSB, ATON_INTCTRL_INTORMSK1_REG_W, DATA) /** * Get the description of the REG field of INTORMSK1 register. * * \return the description of the REG field of INTORMSK1 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK1_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK1_REG_DESC; } /** * Read the content of the REG field of the INTORMSK1 register. * * \param[in] reg is the value of the INTORMSK1 register * * \return the content of the REG field belonging to INTORMSK1 register */ static inline uint32_t ATON_INTCTRL_INTORMSK1_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTORMSK1_GET_REG(reg); } /** * Write the content of the REG field of the INTORMSK1 register. * * \param[in] reg is the value of the INTORMSK1 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTORMSK1 register */ static inline uint32_t ATON_INTCTRL_INTORMSK1_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTORMSK1_SET_REG(reg, data); } /* ***************************************************** INTORMSK2 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTORMSK2 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK2_OFFSET 0x1cUL /** Reset value of the INTORMSK2 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK2_DT \ (ATON_INTCTRL_INTORMSK2_REG_DT << ATON_INTCTRL_INTORMSK2_REG_LSB) /** Description of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_DESC "Interrupt OR mask 2" /** Address of the INTORMSK2 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK2_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK2_OFFSET) /** Get the content of the INTORMSK2 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK2_ADDR(UNIT))) /** Set the content of the INTORMSK2 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTORMSK2 register. * * \return the description of INTORMSK2 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK2_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK2_DESC; } /** * Get the offset of the INTORMSK2 register. * * \return the offset of INTORMSK2 register */ static inline uint32_t ATON_INTCTRL_INTORMSK2_GetOffset(void) { return ATON_INTCTRL_INTORMSK2_OFFSET; } /** * Get the address of the INTORMSK2 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK2 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTORMSK2 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK2_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTORMSK2_ADDR(instance); } /** * Read the content of the INTORMSK2 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK2 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTORMSK2 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK2_Get(uint32_t instance) { return ATON_INTCTRL_INTORMSK2_GET(instance); } /** * Write the content of the INTORMSK2 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK2 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTORMSK2_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTORMSK2_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTORMSK2 register ----------------------------------------------------------- */ /** Description of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" /** Offset of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_REG_LSB 0UL /** Size in bits of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_REG_W (32UL) /** Mask for retrieving the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_REG_AC "RW" /** Check whether access to the REG field of the INTORMSK2 register is secured or not. */ #define ATON_INTCTRL_INTORMSK2_REG_S 0 /** Check whether access to the REG field of the INTORMSK2 register is privileged or not. */ #define ATON_INTCTRL_INTORMSK2_REG_P 0 /** Read the content of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK2_REG_LSB, ATON_INTCTRL_INTORMSK2_REG_W) /** Modify the content of the REG field of the INTORMSK2 register. */ #define ATON_INTCTRL_INTORMSK2_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK2_REG_LSB, ATON_INTCTRL_INTORMSK2_REG_W, DATA) /** * Get the description of the REG field of INTORMSK2 register. * * \return the description of the REG field of INTORMSK2 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK2_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK2_REG_DESC; } /** * Read the content of the REG field of the INTORMSK2 register. * * \param[in] reg is the value of the INTORMSK2 register * * \return the content of the REG field belonging to INTORMSK2 register */ static inline uint32_t ATON_INTCTRL_INTORMSK2_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTORMSK2_GET_REG(reg); } /** * Write the content of the REG field of the INTORMSK2 register. * * \param[in] reg is the value of the INTORMSK2 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTORMSK2 register */ static inline uint32_t ATON_INTCTRL_INTORMSK2_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTORMSK2_SET_REG(reg, data); } /* ***************************************************** INTORMSK3 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTORMSK3 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK3_OFFSET 0x20UL /** Reset value of the INTORMSK3 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTORMSK3_DT \ (ATON_INTCTRL_INTORMSK3_REG_DT << ATON_INTCTRL_INTORMSK3_REG_LSB) /** Description of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_DESC "Interrupt OR mask 3" /** Address of the INTORMSK3 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK3_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK3_OFFSET) /** Get the content of the INTORMSK3 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK3_ADDR(UNIT))) /** Set the content of the INTORMSK3 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTORMSK3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTORMSK3_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTORMSK3 register. * * \return the description of INTORMSK3 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK3_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK3_DESC; } /** * Get the offset of the INTORMSK3 register. * * \return the offset of INTORMSK3 register */ static inline uint32_t ATON_INTCTRL_INTORMSK3_GetOffset(void) { return ATON_INTCTRL_INTORMSK3_OFFSET; } /** * Get the address of the INTORMSK3 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK3 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTORMSK3 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK3_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTORMSK3_ADDR(instance); } /** * Read the content of the INTORMSK3 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK3 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTORMSK3 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTORMSK3_Get(uint32_t instance) { return ATON_INTCTRL_INTORMSK3_GET(instance); } /** * Write the content of the INTORMSK3 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTORMSK3 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTORMSK3_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTORMSK3_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTORMSK3 register ----------------------------------------------------------- */ /** Description of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_REG_DESC "If bit X is set, interrupt X on OR related interrupt line is masked for ARM host" /** Offset of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_REG_LSB 0UL /** Size in bits of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_REG_W (32UL) /** Mask for retrieving the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_REG_AC "RW" /** Check whether access to the REG field of the INTORMSK3 register is secured or not. */ #define ATON_INTCTRL_INTORMSK3_REG_S 0 /** Check whether access to the REG field of the INTORMSK3 register is privileged or not. */ #define ATON_INTCTRL_INTORMSK3_REG_P 0 /** Read the content of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTORMSK3_REG_LSB, ATON_INTCTRL_INTORMSK3_REG_W) /** Modify the content of the REG field of the INTORMSK3 register. */ #define ATON_INTCTRL_INTORMSK3_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTORMSK3_REG_LSB, ATON_INTCTRL_INTORMSK3_REG_W, DATA) /** * Get the description of the REG field of INTORMSK3 register. * * \return the description of the REG field of INTORMSK3 register */ static inline const int8_t *ATON_INTCTRL_INTORMSK3_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTORMSK3_REG_DESC; } /** * Read the content of the REG field of the INTORMSK3 register. * * \param[in] reg is the value of the INTORMSK3 register * * \return the content of the REG field belonging to INTORMSK3 register */ static inline uint32_t ATON_INTCTRL_INTORMSK3_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTORMSK3_GET_REG(reg); } /** * Write the content of the REG field of the INTORMSK3 register. * * \param[in] reg is the value of the INTORMSK3 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTORMSK3 register */ static inline uint32_t ATON_INTCTRL_INTORMSK3_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTORMSK3_SET_REG(reg, data); } /* **************************************************** INTANDMSK0 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTANDMSK0 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK0_OFFSET 0x24UL /** Reset value of the INTANDMSK0 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK0_DT \ (ATON_INTCTRL_INTANDMSK0_REG_DT << ATON_INTCTRL_INTANDMSK0_REG_LSB) /** Description of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_DESC "Interrupt AND mask 0" /** Address of the INTANDMSK0 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK0_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK0_OFFSET) /** Get the content of the INTANDMSK0 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK0_ADDR(UNIT))) /** Set the content of the INTANDMSK0 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTANDMSK0 register. * * \return the description of INTANDMSK0 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK0_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK0_DESC; } /** * Get the offset of the INTANDMSK0 register. * * \return the offset of INTANDMSK0 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK0_GetOffset(void) { return ATON_INTCTRL_INTANDMSK0_OFFSET; } /** * Get the address of the INTANDMSK0 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTANDMSK0 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK0_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTANDMSK0_ADDR(instance); } /** * Read the content of the INTANDMSK0 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTANDMSK0 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK0_Get(uint32_t instance) { return ATON_INTCTRL_INTANDMSK0_GET(instance); } /** * Write the content of the INTANDMSK0 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTANDMSK0_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTANDMSK0_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTANDMSK0 register ---------------------------------------------------------- */ /** Description of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" /** Offset of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_REG_LSB 0UL /** Size in bits of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_REG_W (32UL) /** Mask for retrieving the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_REG_AC "RW" /** Check whether access to the REG field of the INTANDMSK0 register is secured or not. */ #define ATON_INTCTRL_INTANDMSK0_REG_S 0 /** Check whether access to the REG field of the INTANDMSK0 register is privileged or not. */ #define ATON_INTCTRL_INTANDMSK0_REG_P 0 /** Read the content of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK0_REG_LSB, ATON_INTCTRL_INTANDMSK0_REG_W) /** Modify the content of the REG field of the INTANDMSK0 register. */ #define ATON_INTCTRL_INTANDMSK0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK0_REG_LSB, ATON_INTCTRL_INTANDMSK0_REG_W, DATA) /** * Get the description of the REG field of INTANDMSK0 register. * * \return the description of the REG field of INTANDMSK0 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK0_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK0_REG_DESC; } /** * Read the content of the REG field of the INTANDMSK0 register. * * \param[in] reg is the value of the INTANDMSK0 register * * \return the content of the REG field belonging to INTANDMSK0 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK0_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTANDMSK0_GET_REG(reg); } /** * Write the content of the REG field of the INTANDMSK0 register. * * \param[in] reg is the value of the INTANDMSK0 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTANDMSK0 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK0_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTANDMSK0_SET_REG(reg, data); } /* **************************************************** INTANDMSK1 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTANDMSK1 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK1_OFFSET 0x28UL /** Reset value of the INTANDMSK1 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK1_DT \ (ATON_INTCTRL_INTANDMSK1_REG_DT << ATON_INTCTRL_INTANDMSK1_REG_LSB) /** Description of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_DESC "Interrupt AND mask 1" /** Address of the INTANDMSK1 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK1_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK1_OFFSET) /** Get the content of the INTANDMSK1 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK1_ADDR(UNIT))) /** Set the content of the INTANDMSK1 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTANDMSK1 register. * * \return the description of INTANDMSK1 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK1_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK1_DESC; } /** * Get the offset of the INTANDMSK1 register. * * \return the offset of INTANDMSK1 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK1_GetOffset(void) { return ATON_INTCTRL_INTANDMSK1_OFFSET; } /** * Get the address of the INTANDMSK1 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTANDMSK1 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK1_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTANDMSK1_ADDR(instance); } /** * Read the content of the INTANDMSK1 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTANDMSK1 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK1_Get(uint32_t instance) { return ATON_INTCTRL_INTANDMSK1_GET(instance); } /** * Write the content of the INTANDMSK1 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTANDMSK1_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTANDMSK1_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTANDMSK1 register ---------------------------------------------------------- */ /** Description of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" /** Offset of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_REG_LSB 0UL /** Size in bits of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_REG_W (32UL) /** Mask for retrieving the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_REG_AC "RW" /** Check whether access to the REG field of the INTANDMSK1 register is secured or not. */ #define ATON_INTCTRL_INTANDMSK1_REG_S 0 /** Check whether access to the REG field of the INTANDMSK1 register is privileged or not. */ #define ATON_INTCTRL_INTANDMSK1_REG_P 0 /** Read the content of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK1_REG_LSB, ATON_INTCTRL_INTANDMSK1_REG_W) /** Modify the content of the REG field of the INTANDMSK1 register. */ #define ATON_INTCTRL_INTANDMSK1_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK1_REG_LSB, ATON_INTCTRL_INTANDMSK1_REG_W, DATA) /** * Get the description of the REG field of INTANDMSK1 register. * * \return the description of the REG field of INTANDMSK1 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK1_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK1_REG_DESC; } /** * Read the content of the REG field of the INTANDMSK1 register. * * \param[in] reg is the value of the INTANDMSK1 register * * \return the content of the REG field belonging to INTANDMSK1 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK1_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTANDMSK1_GET_REG(reg); } /** * Write the content of the REG field of the INTANDMSK1 register. * * \param[in] reg is the value of the INTANDMSK1 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTANDMSK1 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK1_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTANDMSK1_SET_REG(reg, data); } /* **************************************************** INTANDMSK2 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTANDMSK2 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK2_OFFSET 0x2cUL /** Reset value of the INTANDMSK2 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK2_DT \ (ATON_INTCTRL_INTANDMSK2_REG_DT << ATON_INTCTRL_INTANDMSK2_REG_LSB) /** Description of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_DESC "Interrupt AND mask 2" /** Address of the INTANDMSK2 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK2_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK2_OFFSET) /** Get the content of the INTANDMSK2 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK2_ADDR(UNIT))) /** Set the content of the INTANDMSK2 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTANDMSK2 register. * * \return the description of INTANDMSK2 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK2_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK2_DESC; } /** * Get the offset of the INTANDMSK2 register. * * \return the offset of INTANDMSK2 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK2_GetOffset(void) { return ATON_INTCTRL_INTANDMSK2_OFFSET; } /** * Get the address of the INTANDMSK2 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK2 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTANDMSK2 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK2_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTANDMSK2_ADDR(instance); } /** * Read the content of the INTANDMSK2 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK2 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTANDMSK2 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK2_Get(uint32_t instance) { return ATON_INTCTRL_INTANDMSK2_GET(instance); } /** * Write the content of the INTANDMSK2 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK2 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTANDMSK2_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTANDMSK2_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTANDMSK2 register ---------------------------------------------------------- */ /** Description of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" /** Offset of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_REG_LSB 0UL /** Size in bits of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_REG_W (32UL) /** Mask for retrieving the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_REG_AC "RW" /** Check whether access to the REG field of the INTANDMSK2 register is secured or not. */ #define ATON_INTCTRL_INTANDMSK2_REG_S 0 /** Check whether access to the REG field of the INTANDMSK2 register is privileged or not. */ #define ATON_INTCTRL_INTANDMSK2_REG_P 0 /** Read the content of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK2_REG_LSB, ATON_INTCTRL_INTANDMSK2_REG_W) /** Modify the content of the REG field of the INTANDMSK2 register. */ #define ATON_INTCTRL_INTANDMSK2_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK2_REG_LSB, ATON_INTCTRL_INTANDMSK2_REG_W, DATA) /** * Get the description of the REG field of INTANDMSK2 register. * * \return the description of the REG field of INTANDMSK2 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK2_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK2_REG_DESC; } /** * Read the content of the REG field of the INTANDMSK2 register. * * \param[in] reg is the value of the INTANDMSK2 register * * \return the content of the REG field belonging to INTANDMSK2 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK2_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTANDMSK2_GET_REG(reg); } /** * Write the content of the REG field of the INTANDMSK2 register. * * \param[in] reg is the value of the INTANDMSK2 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTANDMSK2 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK2_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTANDMSK2_SET_REG(reg, data); } /* **************************************************** INTANDMSK3 register of one of the INTCTRL Units ***************************************************** */ /** Offset of the INTANDMSK3 register from the base address of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK3_OFFSET 0x30UL /** Reset value of the INTANDMSK3 register of the INTCTRL Unit. */ #define ATON_INTCTRL_INTANDMSK3_DT \ (ATON_INTCTRL_INTANDMSK3_REG_DT << ATON_INTCTRL_INTANDMSK3_REG_LSB) /** Description of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_DESC "Interrupt AND mask 3" /** Address of the INTANDMSK3 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK3_ADDR(UNIT) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK3_OFFSET) /** Get the content of the INTANDMSK3 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK3_ADDR(UNIT))) /** Set the content of the INTANDMSK3 register of one of the INTCTRL Units. */ #define ATON_INTCTRL_INTANDMSK3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_INTCTRL_INTANDMSK3_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INTANDMSK3 register. * * \return the description of INTANDMSK3 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK3_GetDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK3_DESC; } /** * Get the offset of the INTANDMSK3 register. * * \return the offset of INTANDMSK3 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK3_GetOffset(void) { return ATON_INTCTRL_INTANDMSK3_OFFSET; } /** * Get the address of the INTANDMSK3 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK3 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of INTANDMSK3 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK3_GetAddr(uint32_t instance) { return ATON_INTCTRL_INTANDMSK3_ADDR(instance); } /** * Read the content of the INTANDMSK3 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK3 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of INTANDMSK3 register belonging to Unit having index \e instance among the INTCTRL Units */ static inline uint32_t ATON_INTCTRL_INTANDMSK3_Get(uint32_t instance) { return ATON_INTCTRL_INTANDMSK3_GET(instance); } /** * Write the content of the INTANDMSK3 register. * * \param[in] instance is the index of the Unit (among the INTCTRL Units) containing the INTANDMSK3 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_INTCTRL_INTANDMSK3_Set(uint32_t instance, uint32_t data) { ATON_INTCTRL_INTANDMSK3_SET(instance, data); } /* ---------------------------------------------------------- REG field of the INTANDMSK3 register ---------------------------------------------------------- */ /** Description of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_REG_DESC "If bit X is set, interrupt X on AND related interrupt line is masked for ARM host" /** Offset of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_REG_LSB 0UL /** Size in bits of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_REG_W (32UL) /** Mask for retrieving the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_REG_DT 0xffffffffUL /** Access rights of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_REG_AC "RW" /** Check whether access to the REG field of the INTANDMSK3 register is secured or not. */ #define ATON_INTCTRL_INTANDMSK3_REG_S 0 /** Check whether access to the REG field of the INTANDMSK3 register is privileged or not. */ #define ATON_INTCTRL_INTANDMSK3_REG_P 0 /** Read the content of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_GET_REG(REG) ATON_GET_FIELD(REG, ATON_INTCTRL_INTANDMSK3_REG_LSB, ATON_INTCTRL_INTANDMSK3_REG_W) /** Modify the content of the REG field of the INTANDMSK3 register. */ #define ATON_INTCTRL_INTANDMSK3_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_INTCTRL_INTANDMSK3_REG_LSB, ATON_INTCTRL_INTANDMSK3_REG_W, DATA) /** * Get the description of the REG field of INTANDMSK3 register. * * \return the description of the REG field of INTANDMSK3 register */ static inline const int8_t *ATON_INTCTRL_INTANDMSK3_REG_GetdDesc(void) { return (const int8_t *)ATON_INTCTRL_INTANDMSK3_REG_DESC; } /** * Read the content of the REG field of the INTANDMSK3 register. * * \param[in] reg is the value of the INTANDMSK3 register * * \return the content of the REG field belonging to INTANDMSK3 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK3_Get_REG(uint32_t reg) { return ATON_INTCTRL_INTANDMSK3_GET_REG(reg); } /** * Write the content of the REG field of the INTANDMSK3 register. * * \param[in] reg is the value of the INTANDMSK3 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to INTANDMSK3 register */ static inline uint32_t ATON_INTCTRL_INTANDMSK3_Set_REG(uint32_t reg, uint32_t data) { return ATON_INTCTRL_INTANDMSK3_SET_REG(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* ACTIV Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of ACTIV Unit instances. */ #define ATON_ACTIV_NUM 2 /** * \name Structures, macros and functions of the ACTIV Units */ /*@{*/ /** * Registers of the ACTIV Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e ACTIVPARAM register (ReLU parameter for parametric ReLU or thresholded ReLU). */ uint32_t ACTIVPARAM; /** \e FUNC register (Functional parameter). */ uint32_t FUNC; /** \e ACTIVPARAM2 register (additional activation parameters). */ uint32_t ACTIVPARAM2; /** \e FSUB register (Feature data subtract). */ uint32_t FSUB; } ATON_ACTIV_t; /** Return the pointer to one of the ACTIV Units. */ #define ATON_ACTIV(UNIT) ((ATON_ACTIV_t *)(intptr_t)ATON_ACTIV_BASE(UNIT)) /** Name of one of the ACTIV Units. */ #define ATON_ACTIV_NAME(UNIT) \ (((UNIT) == 0) ? "ACTIV0" : \ (((UNIT) == 1) ? "ACTIV1" : "")) /** Version of the ACTIV Units. */ #define ATON_ACTIV_VERSION "1.1" /** Description of one of the ACTIV Units. */ #define ATON_ACTIV_DESC(UNIT) \ (((UNIT) == 0) ? "Activation Accelerator 0" : \ (((UNIT) == 1) ? "Activation Accelerator 1" : "")) /** Base address of one of the ACTIV Units. */ #define ATON_ACTIV_BASE(UNIT) \ (ATON_BASE + 0x15000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the ACTIV Units. */ #define ATON_ACTIV_SIZE 0x1000UL /** * Get the name of one of the ACTIV Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) * * \return the name of Unit having index \e instance among the ACTIV Units */ static inline const int8_t *ATON_ACTIV_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"ACTIV0"; break; case 1: str = (const int8_t *)"ACTIV1"; break; default: break; } return str; } /** * Get the description of one of the ACTIV Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) * * \return the description of Unit having index \e instance among the ACTIV Units */ static inline const int8_t *ATON_ACTIV_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Activation Accelerator 0"; break; case 1: str = (const int8_t *)"Activation Accelerator 1"; break; default: break; } return str; } /** * Get the version of the ACTIV Units. * * \return the version of the ACTIV Units */ static inline const int8_t *ATON_ACTIV_GetVersion(void) { return (const int8_t *)ATON_ACTIV_VERSION; } /** * Get the base address of one of the ACTIV Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) * * \return the base address of Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_GetBase(uint32_t instance) { return ATON_ACTIV_BASE(instance); } /** * Get the size in bytes of the ACTIV Units. * * \return the size in bytes of the ACTIV Units */ static inline uint32_t ATON_ACTIV_GetSize(void) { return ATON_ACTIV_SIZE; } /* ******************************************************** CTRL register of one of the ACTIV Units ********************************************************* */ /** Offset of the CTRL register from the base address of the ACTIV Unit. */ #define ATON_ACTIV_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the ACTIV Unit. */ #define ATON_ACTIV_CTRL_DT \ (ATON_ACTIV_CTRL_EN_DT << ATON_ACTIV_CTRL_EN_LSB) | \ (ATON_ACTIV_CTRL_CLR_DT << ATON_ACTIV_CTRL_CLR_LSB) | \ (ATON_ACTIV_CTRL_TYPE_DT << ATON_ACTIV_CTRL_TYPE_LSB) | \ (ATON_ACTIV_CTRL_FBYTES_DT << ATON_ACTIV_CTRL_FBYTES_LSB) | \ (ATON_ACTIV_CTRL_FSHIFT_DT << ATON_ACTIV_CTRL_FSHIFT_LSB) | \ (ATON_ACTIV_CTRL_FROUND_DT << ATON_ACTIV_CTRL_FROUND_LSB) | \ (ATON_ACTIV_CTRL_FSAT_DT << ATON_ACTIV_CTRL_FSAT_LSB) | \ (ATON_ACTIV_CTRL_FRNDMODE_DT << ATON_ACTIV_CTRL_FRNDMODE_LSB) | \ (ATON_ACTIV_CTRL_FOBYTES_DT << ATON_ACTIV_CTRL_FOBYTES_LSB) | \ (ATON_ACTIV_CTRL_ROUND_DT << ATON_ACTIV_CTRL_ROUND_LSB) | \ (ATON_ACTIV_CTRL_SAT_DT << ATON_ACTIV_CTRL_SAT_LSB) | \ (ATON_ACTIV_CTRL_OBYTES_DT << ATON_ACTIV_CTRL_OBYTES_LSB) | \ (ATON_ACTIV_CTRL_ORNDMODE_DT << ATON_ACTIV_CTRL_ORNDMODE_LSB) | \ (ATON_ACTIV_CTRL_CONFCLR_DT << ATON_ACTIV_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_ACTIV_CTRL_DESC "Control register" /** Address of the CTRL register of one of the ACTIV Units. */ #define ATON_ACTIV_CTRL_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_CTRL_OFFSET) /** Get the content of the CTRL register of one of the ACTIV Units. */ #define ATON_ACTIV_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the ACTIV Units. */ #define ATON_ACTIV_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_GetDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_GetOffset(void) { return ATON_ACTIV_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the CTRL register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_CTRL_GetAddr(uint32_t instance) { return ATON_ACTIV_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_CTRL_Get(uint32_t instance) { return ATON_ACTIV_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the CTRL register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ACTIV_CTRL_Set(uint32_t instance, uint32_t data) { ATON_ACTIV_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_EN_DESC "Enable the Activation Unit" /** Offset of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_EN_LSB, ATON_ACTIV_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_EN_LSB, ATON_ACTIV_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_EN(uint32_t reg) { return ATON_ACTIV_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_CLR_LSB, ATON_ACTIV_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_CLR_LSB, ATON_ACTIV_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_CLR(uint32_t reg) { return ATON_ACTIV_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_CLR(reg, data); } /* ------------------------------------------------------------ TYPE field of the CTRL register ------------------------------------------------------------- */ /** Description of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_TYPE_DESC "Activation type" /** Offset of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_TYPE_LSB 2UL /** Size in bits of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_TYPE_W (2UL) /** Mask for retrieving the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_TYPE_MASK ATON_FIELD_MASK(2UL, 2UL) /** Reset value of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_TYPE_DT 0x0UL /** Access rights of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_TYPE_AC "RW" /** Check whether access to the TYPE field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_TYPE_S 0 /** Check whether access to the TYPE field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_TYPE_P 0 /** Read the content of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_TYPE_LSB, ATON_ACTIV_CTRL_TYPE_W) /** Modify the content of the TYPE field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_TYPE_LSB, ATON_ACTIV_CTRL_TYPE_W, DATA) /** * Get the description of the TYPE field of CTRL register. * * \return the description of the TYPE field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_TYPE_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_TYPE_DESC; } /** * Read the content of the TYPE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the TYPE field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_TYPE(uint32_t reg) { return ATON_ACTIV_CTRL_GET_TYPE(reg); } /** * Write the content of the TYPE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the TYPE field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_TYPE(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_TYPE(reg, data); } /* ----------------------------------------------------------- FBYTES field of the CTRL register ------------------------------------------------------------ */ /** Description of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FBYTES_DESC "Input data width in bytes. Valid values are 1,2 or 3 bytes" /** Offset of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FBYTES_LSB 6UL /** Size in bits of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FBYTES_W (2UL) /** Mask for retrieving the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FBYTES_MASK ATON_FIELD_MASK(6UL, 2UL) /** Reset value of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FBYTES_DT 0x2UL /** Access rights of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FBYTES_AC "RW" /** Check whether access to the FBYTES field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_FBYTES_S 0 /** Check whether access to the FBYTES field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_FBYTES_P 0 /** Read the content of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_FBYTES(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FBYTES_LSB, ATON_ACTIV_CTRL_FBYTES_W) /** Modify the content of the FBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_FBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FBYTES_LSB, ATON_ACTIV_CTRL_FBYTES_W, DATA) /** * Get the description of the FBYTES field of CTRL register. * * \return the description of the FBYTES field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_FBYTES_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_FBYTES_DESC; } /** * Read the content of the FBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FBYTES field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_FBYTES(uint32_t reg) { return ATON_ACTIV_CTRL_GET_FBYTES(reg); } /** * Write the content of the FBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FBYTES field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_FBYTES(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_FBYTES(reg, data); } /* ----------------------------------------------------------- FSHIFT field of the CTRL register ------------------------------------------------------------ */ /** Description of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSHIFT_DESC "Input feature data shift. Range [0-40]. For no shift, set to 16" /** Offset of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSHIFT_LSB 8UL /** Size in bits of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSHIFT_W (6UL) /** Mask for retrieving the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSHIFT_MASK ATON_FIELD_MASK(8UL, 6UL) /** Reset value of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSHIFT_DT 0x10UL /** Access rights of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSHIFT_AC "RW" /** Check whether access to the FSHIFT field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_FSHIFT_S 0 /** Check whether access to the FSHIFT field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_FSHIFT_P 0 /** Read the content of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_FSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FSHIFT_LSB, ATON_ACTIV_CTRL_FSHIFT_W) /** Modify the content of the FSHIFT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_FSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FSHIFT_LSB, ATON_ACTIV_CTRL_FSHIFT_W, DATA) /** * Get the description of the FSHIFT field of CTRL register. * * \return the description of the FSHIFT field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_FSHIFT_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_FSHIFT_DESC; } /** * Read the content of the FSHIFT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSHIFT field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_FSHIFT(uint32_t reg) { return ATON_ACTIV_CTRL_GET_FSHIFT(reg); } /** * Write the content of the FSHIFT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the FSHIFT field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_FSHIFT(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_FSHIFT(reg, data); } /* ----------------------------------------------------------- FROUND field of the CTRL register ------------------------------------------------------------ */ /** Description of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_FROUND_DESC "Input feature data rounding control,1=enable,0=disable" /** Offset of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_FROUND_LSB 14UL /** Size in bits of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_FROUND_W (1UL) /** Mask for retrieving the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_FROUND_MASK ATON_FIELD_MASK(14UL, 1UL) /** Reset value of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_FROUND_DT 0x0UL /** Access rights of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_FROUND_AC "RW" /** Check whether access to the FROUND field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_FROUND_S 0 /** Check whether access to the FROUND field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_FROUND_P 0 /** Read the content of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_FROUND(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FROUND_LSB, ATON_ACTIV_CTRL_FROUND_W) /** Modify the content of the FROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_FROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FROUND_LSB, ATON_ACTIV_CTRL_FROUND_W, DATA) /** * Get the description of the FROUND field of CTRL register. * * \return the description of the FROUND field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_FROUND_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_FROUND_DESC; } /** * Read the content of the FROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FROUND field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_FROUND(uint32_t reg) { return ATON_ACTIV_CTRL_GET_FROUND(reg); } /** * Write the content of the FROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FROUND field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_FROUND(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_FROUND(reg, data); } /* ------------------------------------------------------------ FSAT field of the CTRL register ------------------------------------------------------------- */ /** Description of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSAT_DESC "Input feature data saturation control,1=enable,0=disable" /** Offset of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSAT_LSB 15UL /** Size in bits of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSAT_W (1UL) /** Mask for retrieving the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSAT_MASK ATON_FIELD_MASK(15UL, 1UL) /** Reset value of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSAT_DT 0x0UL /** Access rights of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_FSAT_AC "RW" /** Check whether access to the FSAT field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_FSAT_S 0 /** Check whether access to the FSAT field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_FSAT_P 0 /** Read the content of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_FSAT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FSAT_LSB, ATON_ACTIV_CTRL_FSAT_W) /** Modify the content of the FSAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_FSAT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FSAT_LSB, ATON_ACTIV_CTRL_FSAT_W, DATA) /** * Get the description of the FSAT field of CTRL register. * * \return the description of the FSAT field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_FSAT_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_FSAT_DESC; } /** * Read the content of the FSAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSAT field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_FSAT(uint32_t reg) { return ATON_ACTIV_CTRL_GET_FSAT(reg); } /** * Write the content of the FSAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSAT field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_FSAT(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_FSAT(reg, data); } /* ---------------------------------------------------------- FRNDMODE field of the CTRL register ----------------------------------------------------------- */ /** Description of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_FRNDMODE_DESC "Input feature round mode. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_FRNDMODE_LSB 16UL /** Size in bits of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_FRNDMODE_W (2UL) /** Mask for retrieving the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_FRNDMODE_MASK ATON_FIELD_MASK(16UL, 2UL) /** Reset value of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_FRNDMODE_DT 0x0UL /** Access rights of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_FRNDMODE_AC "RW" /** Check whether access to the FRNDMODE field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_FRNDMODE_S 0 /** Check whether access to the FRNDMODE field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_FRNDMODE_P 0 /** Read the content of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_FRNDMODE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FRNDMODE_LSB, ATON_ACTIV_CTRL_FRNDMODE_W) /** Modify the content of the FRNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_FRNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FRNDMODE_LSB, ATON_ACTIV_CTRL_FRNDMODE_W, DATA) /** * Get the description of the FRNDMODE field of CTRL register. * * \return the description of the FRNDMODE field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_FRNDMODE_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_FRNDMODE_DESC; } /** * Read the content of the FRNDMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FRNDMODE field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_FRNDMODE(uint32_t reg) { return ATON_ACTIV_CTRL_GET_FRNDMODE(reg); } /** * Write the content of the FRNDMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FRNDMODE field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_FRNDMODE(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_FRNDMODE(reg, data); } /* ----------------------------------------------------------- FOBYTES field of the CTRL register ----------------------------------------------------------- */ /** Description of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FOBYTES_DESC "Input feature out bytes after shift. Valid values are 1 or 2 bytes" /** Offset of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FOBYTES_LSB 18UL /** Size in bits of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FOBYTES_W (2UL) /** Mask for retrieving the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FOBYTES_MASK ATON_FIELD_MASK(18UL, 2UL) /** Reset value of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FOBYTES_DT 0x2UL /** Access rights of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_FOBYTES_AC "RW" /** Check whether access to the FOBYTES field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_FOBYTES_S 0 /** Check whether access to the FOBYTES field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_FOBYTES_P 0 /** Read the content of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_FOBYTES(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_FOBYTES_LSB, ATON_ACTIV_CTRL_FOBYTES_W) /** Modify the content of the FOBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_FOBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_FOBYTES_LSB, ATON_ACTIV_CTRL_FOBYTES_W, DATA) /** * Get the description of the FOBYTES field of CTRL register. * * \return the description of the FOBYTES field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_FOBYTES_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_FOBYTES_DESC; } /** * Read the content of the FOBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FOBYTES field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_FOBYTES(uint32_t reg) { return ATON_ACTIV_CTRL_GET_FOBYTES(reg); } /** * Write the content of the FOBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FOBYTES field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_FOBYTES(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_FOBYTES(reg, data); } /* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ /** Description of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_ROUND_DESC "output rounding control, 1=enable,0=disable" /** Offset of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_ROUND_LSB 20UL /** Size in bits of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_ROUND_W (1UL) /** Mask for retrieving the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_ROUND_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_ROUND_DT 0x0UL /** Access rights of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_ROUND_AC "RW" /** Check whether access to the ROUND field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_ROUND_S 0 /** Check whether access to the ROUND field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_ROUND_P 0 /** Read the content of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_ROUND_LSB, ATON_ACTIV_CTRL_ROUND_W) /** Modify the content of the ROUND field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_ROUND_LSB, ATON_ACTIV_CTRL_ROUND_W, DATA) /** * Get the description of the ROUND field of CTRL register. * * \return the description of the ROUND field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_ROUND_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_ROUND_DESC; } /** * Read the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_ROUND(uint32_t reg) { return ATON_ACTIV_CTRL_GET_ROUND(reg); } /** * Write the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_ROUND(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_ROUND(reg, data); } /* ------------------------------------------------------------- SAT field of the CTRL register ------------------------------------------------------------- */ /** Description of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SAT_DESC "output saturation control,1=enable,0=disable" /** Offset of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SAT_LSB 21UL /** Size in bits of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SAT_W (1UL) /** Mask for retrieving the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SAT_MASK ATON_FIELD_MASK(21UL, 1UL) /** Reset value of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SAT_DT 0x0UL /** Access rights of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SAT_AC "RW" /** Check whether access to the SAT field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_SAT_S 0 /** Check whether access to the SAT field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_SAT_P 0 /** Read the content of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_SAT_LSB, ATON_ACTIV_CTRL_SAT_W) /** Modify the content of the SAT field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_SAT_LSB, ATON_ACTIV_CTRL_SAT_W, DATA) /** * Get the description of the SAT field of CTRL register. * * \return the description of the SAT field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_SAT_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_SAT_DESC; } /** * Read the content of the SAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SAT field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_SAT(uint32_t reg) { return ATON_ACTIV_CTRL_GET_SAT(reg); } /** * Write the content of the SAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SAT field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_SAT(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_SAT(reg, data); } /* ----------------------------------------------------------- OBYTES field of the CTRL register ------------------------------------------------------------ */ /** Description of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_OBYTES_DESC "number of output bytes:1, 2 or 3" /** Offset of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_OBYTES_LSB 22UL /** Size in bits of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_OBYTES_W (2UL) /** Mask for retrieving the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_OBYTES_MASK ATON_FIELD_MASK(22UL, 2UL) /** Reset value of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_OBYTES_DT 0x2UL /** Access rights of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_OBYTES_AC "RW" /** Check whether access to the OBYTES field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_OBYTES_S 0 /** Check whether access to the OBYTES field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_OBYTES_P 0 /** Read the content of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_OBYTES_LSB, ATON_ACTIV_CTRL_OBYTES_W) /** Modify the content of the OBYTES field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_OBYTES_LSB, ATON_ACTIV_CTRL_OBYTES_W, DATA) /** * Get the description of the OBYTES field of CTRL register. * * \return the description of the OBYTES field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_OBYTES_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_OBYTES_DESC; } /** * Read the content of the OBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the OBYTES field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_OBYTES(uint32_t reg) { return ATON_ACTIV_CTRL_GET_OBYTES(reg); } /** * Write the content of the OBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the OBYTES field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_OBYTES(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_OBYTES(reg, data); } /* ---------------------------------------------------------- ORNDMODE field of the CTRL register ----------------------------------------------------------- */ /** Description of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_ORNDMODE_DESC "output rounding mode. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_ORNDMODE_LSB 24UL /** Size in bits of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_ORNDMODE_W (2UL) /** Mask for retrieving the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_ORNDMODE_MASK ATON_FIELD_MASK(24UL, 2UL) /** Reset value of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_ORNDMODE_DT 0x0UL /** Access rights of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_ORNDMODE_AC "RW" /** Check whether access to the ORNDMODE field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_ORNDMODE_S 0 /** Check whether access to the ORNDMODE field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_ORNDMODE_P 0 /** Read the content of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_ORNDMODE_LSB, ATON_ACTIV_CTRL_ORNDMODE_W) /** Modify the content of the ORNDMODE field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_ORNDMODE_LSB, ATON_ACTIV_CTRL_ORNDMODE_W, DATA) /** * Get the description of the ORNDMODE field of CTRL register. * * \return the description of the ORNDMODE field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_ORNDMODE_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_ORNDMODE_DESC; } /** * Read the content of the ORNDMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ORNDMODE field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_ORNDMODE(uint32_t reg) { return ATON_ACTIV_CTRL_GET_ORNDMODE(reg); } /** * Write the content of the ORNDMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ORNDMODE field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_ORNDMODE(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_ORNDMODE(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CONFCLR_DESC "Clear configuration registers (auto-cleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_ACTIV_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_ACTIV_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_CTRL_CONFCLR_LSB, ATON_ACTIV_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_ACTIV_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_CTRL_CONFCLR_LSB, ATON_ACTIV_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_ACTIV_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_ACTIV_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_ACTIV_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_ACTIV_CTRL_SET_CONFCLR(reg, data); } /* ******************************************************* VERSION register of one of the ACTIV Units ******************************************************* */ /** Offset of the VERSION register from the base address of the ACTIV Unit. */ #define ATON_ACTIV_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the ACTIV Unit. */ #define ATON_ACTIV_VERSION_DT \ (ATON_ACTIV_VERSION_TYPE_DT << ATON_ACTIV_VERSION_TYPE_LSB) | \ (ATON_ACTIV_VERSION_MINOR_DT << ATON_ACTIV_VERSION_MINOR_LSB) | \ (ATON_ACTIV_VERSION_MAJOR_DT << ATON_ACTIV_VERSION_MAJOR_LSB) /** Description of the VERSION register. */ #define ATON_ACTIV_VERSION_DESC "Version register" /** Address of the VERSION register of one of the ACTIV Units. */ #define ATON_ACTIV_VERSION_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_VERSION_OFFSET) /** Get the content of the VERSION register of one of the ACTIV Units. */ #define ATON_ACTIV_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_ACTIV_VERSION_GetDesc(void) { return (const int8_t *)ATON_ACTIV_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_ACTIV_VERSION_GetOffset(void) { return ATON_ACTIV_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the VERSION register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_VERSION_GetAddr(uint32_t instance) { return ATON_ACTIV_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_VERSION_Get(uint32_t instance) { return ATON_ACTIV_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_TYPE_DT 0x1bUL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_ACTIV_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_ACTIV_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_ACTIV_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_ACTIV_VERSION_TYPE_LSB, ATON_ACTIV_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_ACTIV_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_ACTIV_VERSION_Get_TYPE(uint32_t reg) { return ATON_ACTIV_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MINOR_DT 0x1UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_ACTIV_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_ACTIV_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_VERSION_MINOR_LSB, ATON_ACTIV_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_ACTIV_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_ACTIV_VERSION_Get_MINOR(uint32_t reg) { return ATON_ACTIV_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_ACTIV_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_ACTIV_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_ACTIV_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_ACTIV_VERSION_MAJOR_LSB, ATON_ACTIV_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_ACTIV_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_ACTIV_VERSION_Get_MAJOR(uint32_t reg) { return ATON_ACTIV_VERSION_GET_MAJOR(reg); } /* ***************************************************** ACTIVPARAM register of one of the ACTIV Units ****************************************************** */ /** Offset of the ACTIVPARAM register from the base address of the ACTIV Unit. */ #define ATON_ACTIV_ACTIVPARAM_OFFSET 0x8UL /** Reset value of the ACTIVPARAM register of the ACTIV Unit. */ #define ATON_ACTIV_ACTIVPARAM_DT \ (ATON_ACTIV_ACTIVPARAM_PARAM_DT << ATON_ACTIV_ACTIVPARAM_PARAM_LSB) | \ (ATON_ACTIV_ACTIVPARAM_FUNC_DT << ATON_ACTIV_ACTIVPARAM_FUNC_LSB) /** Description of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_DESC "ReLU parameter for parametric ReLU or thresholded ReLU" /** Address of the ACTIVPARAM register of one of the ACTIV Units. */ #define ATON_ACTIV_ACTIVPARAM_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ACTIVPARAM_OFFSET) /** Get the content of the ACTIVPARAM register of one of the ACTIV Units. */ #define ATON_ACTIV_ACTIVPARAM_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM_ADDR(UNIT))) /** Set the content of the ACTIVPARAM register of one of the ACTIV Units. */ #define ATON_ACTIV_ACTIVPARAM_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ACTIVPARAM register. * * \return the description of ACTIVPARAM register */ static inline const int8_t *ATON_ACTIV_ACTIVPARAM_GetDesc(void) { return (const int8_t *)ATON_ACTIV_ACTIVPARAM_DESC; } /** * Get the offset of the ACTIVPARAM register. * * \return the offset of ACTIVPARAM register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_GetOffset(void) { return ATON_ACTIV_ACTIVPARAM_OFFSET; } /** * Get the address of the ACTIVPARAM register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of ACTIVPARAM register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_GetAddr(uint32_t instance) { return ATON_ACTIV_ACTIVPARAM_ADDR(instance); } /** * Read the content of the ACTIVPARAM register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of ACTIVPARAM register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_Get(uint32_t instance) { return ATON_ACTIV_ACTIVPARAM_GET(instance); } /** * Write the content of the ACTIVPARAM register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ACTIV_ACTIVPARAM_Set(uint32_t instance, uint32_t data) { ATON_ACTIV_ACTIVPARAM_SET(instance, data); } /* --------------------------------------------------------- PARAM field of the ACTIVPARAM register --------------------------------------------------------- */ /** Description of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_DESC "ReLU parameter" /** Offset of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_LSB 0UL /** Size in bits of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_W (16UL) /** Mask for retrieving the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_DT 0x0UL /** Access rights of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_AC "RW" /** Check whether access to the PARAM field of the ACTIVPARAM register is secured or not. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_S 0 /** Check whether access to the PARAM field of the ACTIVPARAM register is privileged or not. */ #define ATON_ACTIV_ACTIVPARAM_PARAM_P 0 /** Read the content of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_GET_PARAM(REG) ATON_GET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_PARAM_LSB, ATON_ACTIV_ACTIVPARAM_PARAM_W) /** Modify the content of the PARAM field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_SET_PARAM(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_PARAM_LSB, ATON_ACTIV_ACTIVPARAM_PARAM_W, DATA) /** * Get the description of the PARAM field of ACTIVPARAM register. * * \return the description of the PARAM field of ACTIVPARAM register */ static inline const int8_t *ATON_ACTIV_ACTIVPARAM_PARAM_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_ACTIVPARAM_PARAM_DESC; } /** * Read the content of the PARAM field of the ACTIVPARAM register. * * \param[in] reg is the value of the ACTIVPARAM register * * \return the content of the PARAM field belonging to ACTIVPARAM register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_Get_PARAM(uint32_t reg) { return ATON_ACTIV_ACTIVPARAM_GET_PARAM(reg); } /** * Write the content of the PARAM field of the ACTIVPARAM register. * * \param[in] reg is the value of the ACTIVPARAM register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the PARAM field belonging to ACTIVPARAM register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_Set_PARAM(uint32_t reg, uint32_t data) { return ATON_ACTIV_ACTIVPARAM_SET_PARAM(reg, data); } /* --------------------------------------------------------- FUNC field of the ACTIVPARAM register ---------------------------------------------------------- */ /** Description of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_DESC "function input range normalization left shift parameter" /** Offset of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_LSB 16UL /** Size in bits of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_W (4UL) /** Mask for retrieving the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_MASK ATON_FIELD_MASK(16UL, 4UL) /** Reset value of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_DT 0x0UL /** Access rights of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_AC "RW" /** Check whether access to the FUNC field of the ACTIVPARAM register is secured or not. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_S 0 /** Check whether access to the FUNC field of the ACTIVPARAM register is privileged or not. */ #define ATON_ACTIV_ACTIVPARAM_FUNC_P 0 /** Read the content of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_GET_FUNC(REG) ATON_GET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_FUNC_LSB, ATON_ACTIV_ACTIVPARAM_FUNC_W) /** Modify the content of the FUNC field of the ACTIVPARAM register. */ #define ATON_ACTIV_ACTIVPARAM_SET_FUNC(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_ACTIVPARAM_FUNC_LSB, ATON_ACTIV_ACTIVPARAM_FUNC_W, DATA) /** * Get the description of the FUNC field of ACTIVPARAM register. * * \return the description of the FUNC field of ACTIVPARAM register */ static inline const int8_t *ATON_ACTIV_ACTIVPARAM_FUNC_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_ACTIVPARAM_FUNC_DESC; } /** * Read the content of the FUNC field of the ACTIVPARAM register. * * \param[in] reg is the value of the ACTIVPARAM register * * \return the content of the FUNC field belonging to ACTIVPARAM register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_Get_FUNC(uint32_t reg) { return ATON_ACTIV_ACTIVPARAM_GET_FUNC(reg); } /** * Write the content of the FUNC field of the ACTIVPARAM register. * * \param[in] reg is the value of the ACTIVPARAM register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the FUNC field belonging to ACTIVPARAM register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM_Set_FUNC(uint32_t reg, uint32_t data) { return ATON_ACTIV_ACTIVPARAM_SET_FUNC(reg, data); } /* ******************************************************** FUNC register of one of the ACTIV Units ********************************************************* */ /** Offset of the FUNC register from the base address of the ACTIV Unit. */ #define ATON_ACTIV_FUNC_OFFSET 0xcUL /** Reset value of the FUNC register of the ACTIV Unit. */ #define ATON_ACTIV_FUNC_DT \ (ATON_ACTIV_FUNC_OUTSHIFT_DT << ATON_ACTIV_FUNC_OUTSHIFT_LSB) | \ (ATON_ACTIV_FUNC_CSHIFT_DT << ATON_ACTIV_FUNC_CSHIFT_LSB) | \ (ATON_ACTIV_FUNC_BSHIFT_DT << ATON_ACTIV_FUNC_BSHIFT_LSB) | \ (ATON_ACTIV_FUNC_SIGNEDOP_DT << ATON_ACTIV_FUNC_SIGNEDOP_LSB) | \ (ATON_ACTIV_FUNC_BWIDTH_DT << ATON_ACTIV_FUNC_BWIDTH_LSB) /** Description of the FUNC register. */ #define ATON_ACTIV_FUNC_DESC "Functional parameter" /** Address of the FUNC register of one of the ACTIV Units. */ #define ATON_ACTIV_FUNC_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_FUNC_OFFSET) /** Get the content of the FUNC register of one of the ACTIV Units. */ #define ATON_ACTIV_FUNC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FUNC_ADDR(UNIT))) /** Set the content of the FUNC register of one of the ACTIV Units. */ #define ATON_ACTIV_FUNC_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FUNC_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FUNC register. * * \return the description of FUNC register */ static inline const int8_t *ATON_ACTIV_FUNC_GetDesc(void) { return (const int8_t *)ATON_ACTIV_FUNC_DESC; } /** * Get the offset of the FUNC register. * * \return the offset of FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_GetOffset(void) { return ATON_ACTIV_FUNC_OFFSET; } /** * Get the address of the FUNC register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FUNC register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of FUNC register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_FUNC_GetAddr(uint32_t instance) { return ATON_ACTIV_FUNC_ADDR(instance); } /** * Read the content of the FUNC register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FUNC register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of FUNC register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_FUNC_Get(uint32_t instance) { return ATON_ACTIV_FUNC_GET(instance); } /** * Write the content of the FUNC register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FUNC register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ACTIV_FUNC_Set(uint32_t instance, uint32_t data) { ATON_ACTIV_FUNC_SET(instance, data); } /* ---------------------------------------------------------- OUTSHIFT field of the FUNC register ----------------------------------------------------------- */ /** Description of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_OUTSHIFT_DESC "Optional right shift to be applied to the function evaluator final result" /** Offset of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_OUTSHIFT_LSB 0UL /** Size in bits of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_OUTSHIFT_W (6UL) /** Mask for retrieving the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_OUTSHIFT_MASK ATON_FIELD_MASK(0UL, 6UL) /** Reset value of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_OUTSHIFT_DT 0x0UL /** Access rights of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_OUTSHIFT_AC "RW" /** Check whether access to the OUTSHIFT field of the FUNC register is secured or not. */ #define ATON_ACTIV_FUNC_OUTSHIFT_S 0 /** Check whether access to the OUTSHIFT field of the FUNC register is privileged or not. */ #define ATON_ACTIV_FUNC_OUTSHIFT_P 0 /** Read the content of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_GET_OUTSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_OUTSHIFT_LSB, ATON_ACTIV_FUNC_OUTSHIFT_W) /** Modify the content of the OUTSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_SET_OUTSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_OUTSHIFT_LSB, ATON_ACTIV_FUNC_OUTSHIFT_W, DATA) /** * Get the description of the OUTSHIFT field of FUNC register. * * \return the description of the OUTSHIFT field of FUNC register */ static inline const int8_t *ATON_ACTIV_FUNC_OUTSHIFT_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_FUNC_OUTSHIFT_DESC; } /** * Read the content of the OUTSHIFT field of the FUNC register. * * \param[in] reg is the value of the FUNC register * * \return the content of the OUTSHIFT field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Get_OUTSHIFT(uint32_t reg) { return ATON_ACTIV_FUNC_GET_OUTSHIFT(reg); } /** * Write the content of the OUTSHIFT field of the FUNC register. * * \param[in] reg is the value of the FUNC register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the OUTSHIFT field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Set_OUTSHIFT(uint32_t reg, uint32_t data) { return ATON_ACTIV_FUNC_SET_OUTSHIFT(reg, data); } /* ----------------------------------------------------------- CSHIFT field of the FUNC register ------------------------------------------------------------ */ /** Description of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_CSHIFT_DESC "Optional left shift to be applied to coefficient C" /** Offset of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_CSHIFT_LSB 6UL /** Size in bits of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_CSHIFT_W (6UL) /** Mask for retrieving the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_CSHIFT_MASK ATON_FIELD_MASK(6UL, 6UL) /** Reset value of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_CSHIFT_DT 0x0UL /** Access rights of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_CSHIFT_AC "RW" /** Check whether access to the CSHIFT field of the FUNC register is secured or not. */ #define ATON_ACTIV_FUNC_CSHIFT_S 0 /** Check whether access to the CSHIFT field of the FUNC register is privileged or not. */ #define ATON_ACTIV_FUNC_CSHIFT_P 0 /** Read the content of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_GET_CSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_CSHIFT_LSB, ATON_ACTIV_FUNC_CSHIFT_W) /** Modify the content of the CSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_SET_CSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_CSHIFT_LSB, ATON_ACTIV_FUNC_CSHIFT_W, DATA) /** * Get the description of the CSHIFT field of FUNC register. * * \return the description of the CSHIFT field of FUNC register */ static inline const int8_t *ATON_ACTIV_FUNC_CSHIFT_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_FUNC_CSHIFT_DESC; } /** * Read the content of the CSHIFT field of the FUNC register. * * \param[in] reg is the value of the FUNC register * * \return the content of the CSHIFT field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Get_CSHIFT(uint32_t reg) { return ATON_ACTIV_FUNC_GET_CSHIFT(reg); } /** * Write the content of the CSHIFT field of the FUNC register. * * \param[in] reg is the value of the FUNC register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the CSHIFT field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Set_CSHIFT(uint32_t reg, uint32_t data) { return ATON_ACTIV_FUNC_SET_CSHIFT(reg, data); } /* ----------------------------------------------------------- BSHIFT field of the FUNC register ------------------------------------------------------------ */ /** Description of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_BSHIFT_DESC "Optional left shift to be applied to coefficient B" /** Offset of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_BSHIFT_LSB 12UL /** Size in bits of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_BSHIFT_W (5UL) /** Mask for retrieving the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_BSHIFT_MASK ATON_FIELD_MASK(12UL, 5UL) /** Reset value of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_BSHIFT_DT 0x0UL /** Access rights of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_BSHIFT_AC "RW" /** Check whether access to the BSHIFT field of the FUNC register is secured or not. */ #define ATON_ACTIV_FUNC_BSHIFT_S 0 /** Check whether access to the BSHIFT field of the FUNC register is privileged or not. */ #define ATON_ACTIV_FUNC_BSHIFT_P 0 /** Read the content of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_GET_BSHIFT(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_BSHIFT_LSB, ATON_ACTIV_FUNC_BSHIFT_W) /** Modify the content of the BSHIFT field of the FUNC register. */ #define ATON_ACTIV_FUNC_SET_BSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_BSHIFT_LSB, ATON_ACTIV_FUNC_BSHIFT_W, DATA) /** * Get the description of the BSHIFT field of FUNC register. * * \return the description of the BSHIFT field of FUNC register */ static inline const int8_t *ATON_ACTIV_FUNC_BSHIFT_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_FUNC_BSHIFT_DESC; } /** * Read the content of the BSHIFT field of the FUNC register. * * \param[in] reg is the value of the FUNC register * * \return the content of the BSHIFT field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Get_BSHIFT(uint32_t reg) { return ATON_ACTIV_FUNC_GET_BSHIFT(reg); } /** * Write the content of the BSHIFT field of the FUNC register. * * \param[in] reg is the value of the FUNC register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the BSHIFT field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Set_BSHIFT(uint32_t reg, uint32_t data) { return ATON_ACTIV_FUNC_SET_BSHIFT(reg, data); } /* ---------------------------------------------------------- SIGNEDOP field of the FUNC register ----------------------------------------------------------- */ /** Description of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SIGNEDOP_DESC "Signed/unsigned activations" /** Offset of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SIGNEDOP_LSB 20UL /** Size in bits of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SIGNEDOP_W (1UL) /** Mask for retrieving the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SIGNEDOP_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SIGNEDOP_DT 0x0UL /** Access rights of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SIGNEDOP_AC "RW" /** Check whether access to the SIGNEDOP field of the FUNC register is secured or not. */ #define ATON_ACTIV_FUNC_SIGNEDOP_S 0 /** Check whether access to the SIGNEDOP field of the FUNC register is privileged or not. */ #define ATON_ACTIV_FUNC_SIGNEDOP_P 0 /** Read the content of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_GET_SIGNEDOP(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_SIGNEDOP_LSB, ATON_ACTIV_FUNC_SIGNEDOP_W) /** Modify the content of the SIGNEDOP field of the FUNC register. */ #define ATON_ACTIV_FUNC_SET_SIGNEDOP(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_SIGNEDOP_LSB, ATON_ACTIV_FUNC_SIGNEDOP_W, DATA) /** * Get the description of the SIGNEDOP field of FUNC register. * * \return the description of the SIGNEDOP field of FUNC register */ static inline const int8_t *ATON_ACTIV_FUNC_SIGNEDOP_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_FUNC_SIGNEDOP_DESC; } /** * Read the content of the SIGNEDOP field of the FUNC register. * * \param[in] reg is the value of the FUNC register * * \return the content of the SIGNEDOP field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Get_SIGNEDOP(uint32_t reg) { return ATON_ACTIV_FUNC_GET_SIGNEDOP(reg); } /** * Write the content of the SIGNEDOP field of the FUNC register. * * \param[in] reg is the value of the FUNC register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SIGNEDOP field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Set_SIGNEDOP(uint32_t reg, uint32_t data) { return ATON_ACTIV_FUNC_SET_SIGNEDOP(reg, data); } /* ----------------------------------------------------------- BWIDTH field of the FUNC register ------------------------------------------------------------ */ /** Description of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_BWIDTH_DESC "Number of MSB bits of the input activation to be used to address ROM0. This field configures the number of outer segments (max outer segments = 32). Valid values range = 0,1,2,3,4 and 5 corresponding to 1,2,4,8,16 and 32 outer segment(s) respectively" /** Offset of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_BWIDTH_LSB 23UL /** Size in bits of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_BWIDTH_W (3UL) /** Mask for retrieving the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_BWIDTH_MASK ATON_FIELD_MASK(23UL, 3UL) /** Reset value of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_BWIDTH_DT 0x0UL /** Access rights of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_BWIDTH_AC "RW" /** Check whether access to the BWIDTH field of the FUNC register is secured or not. */ #define ATON_ACTIV_FUNC_BWIDTH_S 0 /** Check whether access to the BWIDTH field of the FUNC register is privileged or not. */ #define ATON_ACTIV_FUNC_BWIDTH_P 0 /** Read the content of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_GET_BWIDTH(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FUNC_BWIDTH_LSB, ATON_ACTIV_FUNC_BWIDTH_W) /** Modify the content of the BWIDTH field of the FUNC register. */ #define ATON_ACTIV_FUNC_SET_BWIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FUNC_BWIDTH_LSB, ATON_ACTIV_FUNC_BWIDTH_W, DATA) /** * Get the description of the BWIDTH field of FUNC register. * * \return the description of the BWIDTH field of FUNC register */ static inline const int8_t *ATON_ACTIV_FUNC_BWIDTH_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_FUNC_BWIDTH_DESC; } /** * Read the content of the BWIDTH field of the FUNC register. * * \param[in] reg is the value of the FUNC register * * \return the content of the BWIDTH field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Get_BWIDTH(uint32_t reg) { return ATON_ACTIV_FUNC_GET_BWIDTH(reg); } /** * Write the content of the BWIDTH field of the FUNC register. * * \param[in] reg is the value of the FUNC register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the BWIDTH field belonging to FUNC register */ static inline uint32_t ATON_ACTIV_FUNC_Set_BWIDTH(uint32_t reg, uint32_t data) { return ATON_ACTIV_FUNC_SET_BWIDTH(reg, data); } /* ***************************************************** ACTIVPARAM2 register of one of the ACTIV Units ***************************************************** */ /** Offset of the ACTIVPARAM2 register from the base address of the ACTIV Unit. */ #define ATON_ACTIV_ACTIVPARAM2_OFFSET 0x10UL /** Reset value of the ACTIVPARAM2 register of the ACTIV Unit. */ #define ATON_ACTIV_ACTIVPARAM2_DT \ (ATON_ACTIV_ACTIVPARAM2_PARAM2_DT << ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB) /** Description of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_DESC "additional activation parameters" /** Address of the ACTIVPARAM2 register of one of the ACTIV Units. */ #define ATON_ACTIV_ACTIVPARAM2_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ACTIVPARAM2_OFFSET) /** Get the content of the ACTIVPARAM2 register of one of the ACTIV Units. */ #define ATON_ACTIV_ACTIVPARAM2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM2_ADDR(UNIT))) /** Set the content of the ACTIVPARAM2 register of one of the ACTIV Units. */ #define ATON_ACTIV_ACTIVPARAM2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_ACTIVPARAM2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ACTIVPARAM2 register. * * \return the description of ACTIVPARAM2 register */ static inline const int8_t *ATON_ACTIV_ACTIVPARAM2_GetDesc(void) { return (const int8_t *)ATON_ACTIV_ACTIVPARAM2_DESC; } /** * Get the offset of the ACTIVPARAM2 register. * * \return the offset of ACTIVPARAM2 register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM2_GetOffset(void) { return ATON_ACTIV_ACTIVPARAM2_OFFSET; } /** * Get the address of the ACTIVPARAM2 register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM2 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of ACTIVPARAM2 register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_ACTIVPARAM2_GetAddr(uint32_t instance) { return ATON_ACTIV_ACTIVPARAM2_ADDR(instance); } /** * Read the content of the ACTIVPARAM2 register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM2 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of ACTIVPARAM2 register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_ACTIVPARAM2_Get(uint32_t instance) { return ATON_ACTIV_ACTIVPARAM2_GET(instance); } /** * Write the content of the ACTIVPARAM2 register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the ACTIVPARAM2 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ACTIV_ACTIVPARAM2_Set(uint32_t instance, uint32_t data) { ATON_ACTIV_ACTIVPARAM2_SET(instance, data); } /* -------------------------------------------------------- PARAM2 field of the ACTIVPARAM2 register -------------------------------------------------------- */ /** Description of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_DESC "zero offset for TRELU operation for use in scale/offset integer arithmetic" /** Offset of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB 0UL /** Size in bits of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_W (16UL) /** Mask for retrieving the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_DT 0x0UL /** Access rights of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_AC "RW" /** Check whether access to the PARAM2 field of the ACTIVPARAM2 register is secured or not. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_S 0 /** Check whether access to the PARAM2 field of the ACTIVPARAM2 register is privileged or not. */ #define ATON_ACTIV_ACTIVPARAM2_PARAM2_P 0 /** Read the content of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_GET_PARAM2(REG) ATON_GET_FIELD(REG, ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB, ATON_ACTIV_ACTIVPARAM2_PARAM2_W) /** Modify the content of the PARAM2 field of the ACTIVPARAM2 register. */ #define ATON_ACTIV_ACTIVPARAM2_SET_PARAM2(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_ACTIVPARAM2_PARAM2_LSB, ATON_ACTIV_ACTIVPARAM2_PARAM2_W, DATA) /** * Get the description of the PARAM2 field of ACTIVPARAM2 register. * * \return the description of the PARAM2 field of ACTIVPARAM2 register */ static inline const int8_t *ATON_ACTIV_ACTIVPARAM2_PARAM2_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_ACTIVPARAM2_PARAM2_DESC; } /** * Read the content of the PARAM2 field of the ACTIVPARAM2 register. * * \param[in] reg is the value of the ACTIVPARAM2 register * * \return the content of the PARAM2 field belonging to ACTIVPARAM2 register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM2_Get_PARAM2(uint32_t reg) { return ATON_ACTIV_ACTIVPARAM2_GET_PARAM2(reg); } /** * Write the content of the PARAM2 field of the ACTIVPARAM2 register. * * \param[in] reg is the value of the ACTIVPARAM2 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the PARAM2 field belonging to ACTIVPARAM2 register */ static inline uint32_t ATON_ACTIV_ACTIVPARAM2_Set_PARAM2(uint32_t reg, uint32_t data) { return ATON_ACTIV_ACTIVPARAM2_SET_PARAM2(reg, data); } /* ******************************************************** FSUB register of one of the ACTIV Units ********************************************************* */ /** Offset of the FSUB register from the base address of the ACTIV Unit. */ #define ATON_ACTIV_FSUB_OFFSET 0x14UL /** Reset value of the FSUB register of the ACTIV Unit. */ #define ATON_ACTIV_FSUB_DT \ (ATON_ACTIV_FSUB_FSUB_DT << ATON_ACTIV_FSUB_FSUB_LSB) /** Description of the FSUB register. */ #define ATON_ACTIV_FSUB_DESC "Feature data subtract" /** Address of the FSUB register of one of the ACTIV Units. */ #define ATON_ACTIV_FSUB_ADDR(UNIT) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_FSUB_OFFSET) /** Get the content of the FSUB register of one of the ACTIV Units. */ #define ATON_ACTIV_FSUB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FSUB_ADDR(UNIT))) /** Set the content of the FSUB register of one of the ACTIV Units. */ #define ATON_ACTIV_FSUB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ACTIV_FSUB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FSUB register. * * \return the description of FSUB register */ static inline const int8_t *ATON_ACTIV_FSUB_GetDesc(void) { return (const int8_t *)ATON_ACTIV_FSUB_DESC; } /** * Get the offset of the FSUB register. * * \return the offset of FSUB register */ static inline uint32_t ATON_ACTIV_FSUB_GetOffset(void) { return ATON_ACTIV_FSUB_OFFSET; } /** * Get the address of the FSUB register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FSUB register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of FSUB register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_FSUB_GetAddr(uint32_t instance) { return ATON_ACTIV_FSUB_ADDR(instance); } /** * Read the content of the FSUB register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FSUB register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of FSUB register belonging to Unit having index \e instance among the ACTIV Units */ static inline uint32_t ATON_ACTIV_FSUB_Get(uint32_t instance) { return ATON_ACTIV_FSUB_GET(instance); } /** * Write the content of the FSUB register. * * \param[in] instance is the index of the Unit (among the ACTIV Units) containing the FSUB register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ACTIV_FSUB_Set(uint32_t instance, uint32_t data) { ATON_ACTIV_FSUB_SET(instance, data); } /* ------------------------------------------------------------ FSUB field of the FSUB register ------------------------------------------------------------- */ /** Description of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_FSUB_DESC "Feature data subtract value" /** Offset of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_FSUB_LSB 0UL /** Size in bits of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_FSUB_W (24UL) /** Mask for retrieving the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_FSUB_MASK ATON_FIELD_MASK(0UL, 24UL) /** Reset value of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_FSUB_DT 0x0UL /** Access rights of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_FSUB_AC "RW" /** Check whether access to the FSUB field of the FSUB register is secured or not. */ #define ATON_ACTIV_FSUB_FSUB_S 0 /** Check whether access to the FSUB field of the FSUB register is privileged or not. */ #define ATON_ACTIV_FSUB_FSUB_P 0 /** Read the content of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_GET_FSUB(REG) ATON_GET_FIELD(REG, ATON_ACTIV_FSUB_FSUB_LSB, ATON_ACTIV_FSUB_FSUB_W) /** Modify the content of the FSUB field of the FSUB register. */ #define ATON_ACTIV_FSUB_SET_FSUB(REG, DATA) ATON_SET_FIELD(REG, ATON_ACTIV_FSUB_FSUB_LSB, ATON_ACTIV_FSUB_FSUB_W, DATA) /** * Get the description of the FSUB field of FSUB register. * * \return the description of the FSUB field of FSUB register */ static inline const int8_t *ATON_ACTIV_FSUB_FSUB_GetdDesc(void) { return (const int8_t *)ATON_ACTIV_FSUB_FSUB_DESC; } /** * Read the content of the FSUB field of the FSUB register. * * \param[in] reg is the value of the FSUB register * * \return the content of the FSUB field belonging to FSUB register */ static inline uint32_t ATON_ACTIV_FSUB_Get_FSUB(uint32_t reg) { return ATON_ACTIV_FSUB_GET_FSUB(reg); } /** * Write the content of the FSUB field of the FSUB register. * * \param[in] reg is the value of the FSUB register * \param[in] data is 24-bit value that must be written to the field * * \return the new content of the FSUB field belonging to FSUB register */ static inline uint32_t ATON_ACTIV_FSUB_Set_FSUB(uint32_t reg, uint32_t data) { return ATON_ACTIV_FSUB_SET_FSUB(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* ARITH Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of ARITH Unit instances. */ #define ATON_ARITH_NUM 4 /** * \name Structures, macros and functions of the ARITH Units */ /*@{*/ /** * Registers of the ARITH Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e SHIFT register (Shift parameters). */ uint32_t SHIFT; /** \e INCCNT register (Increment counter). */ uint32_t INCCNT; /** \e RSTCNT1 register (Reset counter 1). */ uint32_t RSTCNT1; /** \e RSTCNT2 register (Reset counter 2). */ uint32_t RSTCNT2; /** \e RSTCNT3 register (Reset counter 3). */ uint32_t RSTCNT3; /** \e COEFFAC register (Scalar coefficients A and C). */ uint32_t COEFFAC; /** \e COEFFB register (Scalar coefficient B). */ uint32_t COEFFB; /** \e ADDROFFSET register (Address offsets). */ uint32_t ADDROFFSET; /** \e INCOFFSET register (Address increment offset). */ uint32_t INCOFFSET; /** \e TRANSLATEADDR register (Address translation control for memory). */ uint32_t TRANSLATEADDR; /** \e COEFFADDR register (Coeff Address). */ uint32_t COEFFADDR; /** \e INSHIFTER register (input shifter configuration). */ uint32_t INSHIFTER; /** \e CLIPRANGE register (Output clip range [min,max]). */ uint32_t CLIPRANGE; } ATON_ARITH_t; /** Return the pointer to one of the ARITH Units. */ #define ATON_ARITH(UNIT) ((ATON_ARITH_t *)(intptr_t)ATON_ARITH_BASE(UNIT)) /** Name of one of the ARITH Units. */ #define ATON_ARITH_NAME(UNIT) \ (((UNIT) == 0) ? "ARITH0" : \ (((UNIT) == 1) ? "ARITH1" : \ (((UNIT) == 2) ? "ARITH2" : \ (((UNIT) == 3) ? "ARITH3" : "")))) /** Version of the ARITH Units. */ #define ATON_ARITH_VERSION "1.0" /** Description of one of the ARITH Units. */ #define ATON_ARITH_DESC(UNIT) \ (((UNIT) == 0) ? "Arithmetic Accelerator 0" : \ (((UNIT) == 1) ? "Arithmetic Accelerator 1" : \ (((UNIT) == 2) ? "Arithmetic Accelerator 2" : \ (((UNIT) == 3) ? "Arithmetic Accelerator 3" : "")))) /** Base address of one of the ARITH Units. */ #define ATON_ARITH_BASE(UNIT) \ (ATON_BASE + 0x17000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the ARITH Units. */ #define ATON_ARITH_SIZE 0x1000UL /** * Get the name of one of the ARITH Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 4<\em>) * * \return the name of Unit having index \e instance among the ARITH Units */ static inline const int8_t *ATON_ARITH_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"ARITH0"; break; case 1: str = (const int8_t *)"ARITH1"; break; case 2: str = (const int8_t *)"ARITH2"; break; case 3: str = (const int8_t *)"ARITH3"; break; default: break; } return str; } /** * Get the description of one of the ARITH Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 4<\em>) * * \return the description of Unit having index \e instance among the ARITH Units */ static inline const int8_t *ATON_ARITH_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Arithmetic Accelerator 0"; break; case 1: str = (const int8_t *)"Arithmetic Accelerator 1"; break; case 2: str = (const int8_t *)"Arithmetic Accelerator 2"; break; case 3: str = (const int8_t *)"Arithmetic Accelerator 3"; break; default: break; } return str; } /** * Get the version of the ARITH Units. * * \return the version of the ARITH Units */ static inline const int8_t *ATON_ARITH_GetVersion(void) { return (const int8_t *)ATON_ARITH_VERSION; } /** * Get the base address of one of the ARITH Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 4<\em>) * * \return the base address of Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_GetBase(uint32_t instance) { return ATON_ARITH_BASE(instance); } /** * Get the size in bytes of the ARITH Units. * * \return the size in bytes of the ARITH Units */ static inline uint32_t ATON_ARITH_GetSize(void) { return ATON_ARITH_SIZE; } /* ******************************************************** CTRL register of one of the ARITH Units ********************************************************* */ /** Offset of the CTRL register from the base address of the ARITH Unit. */ #define ATON_ARITH_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the ARITH Unit. */ #define ATON_ARITH_CTRL_DT \ (ATON_ARITH_CTRL_EN_DT << ATON_ARITH_CTRL_EN_LSB) | \ (ATON_ARITH_CTRL_CLR_DT << ATON_ARITH_CTRL_CLR_LSB) | \ (ATON_ARITH_CTRL_CNT1_DT << ATON_ARITH_CTRL_CNT1_LSB) | \ (ATON_ARITH_CTRL_CNT2_DT << ATON_ARITH_CTRL_CNT2_LSB) | \ (ATON_ARITH_CTRL_CNT3_DT << ATON_ARITH_CTRL_CNT3_LSB) | \ (ATON_ARITH_CTRL_ROUND_DT << ATON_ARITH_CTRL_ROUND_LSB) | \ (ATON_ARITH_CTRL_SAT_DT << ATON_ARITH_CTRL_SAT_LSB) | \ (ATON_ARITH_CTRL_COEFFA_DT << ATON_ARITH_CTRL_COEFFA_LSB) | \ (ATON_ARITH_CTRL_DUALIN_DT << ATON_ARITH_CTRL_DUALIN_LSB) | \ (ATON_ARITH_CTRL_OP_DT << ATON_ARITH_CTRL_OP_LSB) | \ (ATON_ARITH_CTRL_COEFFB_DT << ATON_ARITH_CTRL_COEFFB_LSB) | \ (ATON_ARITH_CTRL_COEFFC_DT << ATON_ARITH_CTRL_COEFFC_LSB) | \ (ATON_ARITH_CTRL_LOGICALOP_DT << ATON_ARITH_CTRL_LOGICALOP_LSB) | \ (ATON_ARITH_CTRL_ORNDMODE_DT << ATON_ARITH_CTRL_ORNDMODE_LSB) | \ (ATON_ARITH_CTRL_OBYTES_DT << ATON_ARITH_CTRL_OBYTES_LSB) | \ (ATON_ARITH_CTRL_COMBINEBC_DT << ATON_ARITH_CTRL_COMBINEBC_LSB) | \ (ATON_ARITH_CTRL_CLIPOUT_DT << ATON_ARITH_CTRL_CLIPOUT_LSB) | \ (ATON_ARITH_CTRL_CONFCLR_DT << ATON_ARITH_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_ARITH_CTRL_DESC "Control register" /** Address of the CTRL register of one of the ARITH Units. */ #define ATON_ARITH_CTRL_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_CTRL_OFFSET) /** Get the content of the CTRL register of one of the ARITH Units. */ #define ATON_ARITH_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the ARITH Units. */ #define ATON_ARITH_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_GetDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_ARITH_CTRL_GetOffset(void) { return ATON_ARITH_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CTRL register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_CTRL_GetAddr(uint32_t instance) { return ATON_ARITH_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_CTRL_Get(uint32_t instance) { return ATON_ARITH_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CTRL register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_CTRL_Set(uint32_t instance, uint32_t data) { ATON_ARITH_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_EN_DESC "Enable the Arithmetic Unit" /** Offset of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_EN_LSB, ATON_ARITH_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_EN_LSB, ATON_ARITH_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_EN(uint32_t reg) { return ATON_ARITH_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CLR_LSB, ATON_ARITH_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CLR_LSB, ATON_ARITH_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_CLR(uint32_t reg) { return ATON_ARITH_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_CLR(reg, data); } /* ------------------------------------------------------------ CNT1 field of the CTRL register ------------------------------------------------------------- */ /** Description of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT1_DESC "Enable counter 1" /** Offset of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT1_LSB 2UL /** Size in bits of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT1_W (1UL) /** Mask for retrieving the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT1_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT1_DT 0x0UL /** Access rights of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT1_AC "RW" /** Check whether access to the CNT1 field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_CNT1_S 0 /** Check whether access to the CNT1 field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_CNT1_P 0 /** Read the content of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_CNT1(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CNT1_LSB, ATON_ARITH_CTRL_CNT1_W) /** Modify the content of the CNT1 field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_CNT1(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CNT1_LSB, ATON_ARITH_CTRL_CNT1_W, DATA) /** * Get the description of the CNT1 field of CTRL register. * * \return the description of the CNT1 field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_CNT1_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_CNT1_DESC; } /** * Read the content of the CNT1 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CNT1 field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_CNT1(uint32_t reg) { return ATON_ARITH_CTRL_GET_CNT1(reg); } /** * Write the content of the CNT1 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT1 field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_CNT1(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_CNT1(reg, data); } /* ------------------------------------------------------------ CNT2 field of the CTRL register ------------------------------------------------------------- */ /** Description of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT2_DESC "Enable counter 2" /** Offset of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT2_LSB 3UL /** Size in bits of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT2_W (1UL) /** Mask for retrieving the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT2_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT2_DT 0x0UL /** Access rights of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT2_AC "RW" /** Check whether access to the CNT2 field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_CNT2_S 0 /** Check whether access to the CNT2 field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_CNT2_P 0 /** Read the content of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_CNT2(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CNT2_LSB, ATON_ARITH_CTRL_CNT2_W) /** Modify the content of the CNT2 field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_CNT2(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CNT2_LSB, ATON_ARITH_CTRL_CNT2_W, DATA) /** * Get the description of the CNT2 field of CTRL register. * * \return the description of the CNT2 field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_CNT2_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_CNT2_DESC; } /** * Read the content of the CNT2 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CNT2 field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_CNT2(uint32_t reg) { return ATON_ARITH_CTRL_GET_CNT2(reg); } /** * Write the content of the CNT2 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT2 field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_CNT2(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_CNT2(reg, data); } /* ------------------------------------------------------------ CNT3 field of the CTRL register ------------------------------------------------------------- */ /** Description of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT3_DESC "Enable counter 3" /** Offset of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT3_LSB 4UL /** Size in bits of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT3_W (1UL) /** Mask for retrieving the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT3_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT3_DT 0x0UL /** Access rights of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_CNT3_AC "RW" /** Check whether access to the CNT3 field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_CNT3_S 0 /** Check whether access to the CNT3 field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_CNT3_P 0 /** Read the content of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_CNT3(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CNT3_LSB, ATON_ARITH_CTRL_CNT3_W) /** Modify the content of the CNT3 field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_CNT3(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CNT3_LSB, ATON_ARITH_CTRL_CNT3_W, DATA) /** * Get the description of the CNT3 field of CTRL register. * * \return the description of the CNT3 field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_CNT3_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_CNT3_DESC; } /** * Read the content of the CNT3 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CNT3 field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_CNT3(uint32_t reg) { return ATON_ARITH_CTRL_GET_CNT3(reg); } /** * Write the content of the CNT3 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT3 field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_CNT3(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_CNT3(reg, data); } /* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ /** Description of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_ROUND_DESC "Rounding control, 1=enable,0=disable" /** Offset of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_ROUND_LSB 5UL /** Size in bits of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_ROUND_W (1UL) /** Mask for retrieving the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_ROUND_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_ROUND_DT 0x0UL /** Access rights of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_ROUND_AC "RW" /** Check whether access to the ROUND field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_ROUND_S 0 /** Check whether access to the ROUND field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_ROUND_P 0 /** Read the content of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_ROUND_LSB, ATON_ARITH_CTRL_ROUND_W) /** Modify the content of the ROUND field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_ROUND_LSB, ATON_ARITH_CTRL_ROUND_W, DATA) /** * Get the description of the ROUND field of CTRL register. * * \return the description of the ROUND field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_ROUND_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_ROUND_DESC; } /** * Read the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_ROUND(uint32_t reg) { return ATON_ARITH_CTRL_GET_ROUND(reg); } /** * Write the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_ROUND(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_ROUND(reg, data); } /* ------------------------------------------------------------- SAT field of the CTRL register ------------------------------------------------------------- */ /** Description of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SAT_DESC "Saturation control, 1=enable,0=disable" /** Offset of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SAT_LSB 6UL /** Size in bits of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SAT_W (1UL) /** Mask for retrieving the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SAT_MASK ATON_FIELD_MASK(6UL, 1UL) /** Reset value of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SAT_DT 0x0UL /** Access rights of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SAT_AC "RW" /** Check whether access to the SAT field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_SAT_S 0 /** Check whether access to the SAT field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_SAT_P 0 /** Read the content of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_SAT_LSB, ATON_ARITH_CTRL_SAT_W) /** Modify the content of the SAT field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_SAT_LSB, ATON_ARITH_CTRL_SAT_W, DATA) /** * Get the description of the SAT field of CTRL register. * * \return the description of the SAT field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_SAT_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_SAT_DESC; } /** * Read the content of the SAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SAT field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_SAT(uint32_t reg) { return ATON_ARITH_CTRL_GET_SAT(reg); } /** * Write the content of the SAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SAT field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_SAT(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_SAT(reg, data); } /* ----------------------------------------------------------- COEFFA field of the CTRL register ------------------------------------------------------------ */ /** Description of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFA_DESC "Coefficient type for A" /** Offset of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFA_LSB 7UL /** Size in bits of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFA_W (1UL) /** Mask for retrieving the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFA_MASK ATON_FIELD_MASK(7UL, 1UL) /** Reset value of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFA_DT 0x0UL /** Access rights of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFA_AC "RW" /** Check whether access to the COEFFA field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_COEFFA_S 0 /** Check whether access to the COEFFA field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_COEFFA_P 0 /** Read the content of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_COEFFA(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COEFFA_LSB, ATON_ARITH_CTRL_COEFFA_W) /** Modify the content of the COEFFA field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_COEFFA(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COEFFA_LSB, ATON_ARITH_CTRL_COEFFA_W, DATA) /** * Get the description of the COEFFA field of CTRL register. * * \return the description of the COEFFA field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_COEFFA_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_COEFFA_DESC; } /** * Read the content of the COEFFA field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the COEFFA field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_COEFFA(uint32_t reg) { return ATON_ARITH_CTRL_GET_COEFFA(reg); } /** * Write the content of the COEFFA field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the COEFFA field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_COEFFA(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_COEFFA(reg, data); } /* ----------------------------------------------------------- DUALIN field of the CTRL register ------------------------------------------------------------ */ /** Description of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_DUALIN_DESC "dual input control, 1=both X,Y streams valid, 0=only X stream is valid" /** Offset of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_DUALIN_LSB 8UL /** Size in bits of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_DUALIN_W (1UL) /** Mask for retrieving the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_DUALIN_MASK ATON_FIELD_MASK(8UL, 1UL) /** Reset value of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_DUALIN_DT 0x0UL /** Access rights of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_DUALIN_AC "RW" /** Check whether access to the DUALIN field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_DUALIN_S 0 /** Check whether access to the DUALIN field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_DUALIN_P 0 /** Read the content of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_DUALIN(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_DUALIN_LSB, ATON_ARITH_CTRL_DUALIN_W) /** Modify the content of the DUALIN field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_DUALIN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_DUALIN_LSB, ATON_ARITH_CTRL_DUALIN_W, DATA) /** * Get the description of the DUALIN field of CTRL register. * * \return the description of the DUALIN field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_DUALIN_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_DUALIN_DESC; } /** * Read the content of the DUALIN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DUALIN field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_DUALIN(uint32_t reg) { return ATON_ARITH_CTRL_GET_DUALIN(reg); } /** * Write the content of the DUALIN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DUALIN field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_DUALIN(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_DUALIN(reg, data); } /* ------------------------------------------------------------- OP field of the CTRL register -------------------------------------------------------------- */ /** Description of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_OP_DESC "Arithmetic operation" /** Offset of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_OP_LSB 9UL /** Size in bits of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_OP_W (6UL) /** Mask for retrieving the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_OP_MASK ATON_FIELD_MASK(9UL, 6UL) /** Reset value of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_OP_DT 0x0UL /** Access rights of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_OP_AC "RW" /** Check whether access to the OP field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_OP_S 0 /** Check whether access to the OP field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_OP_P 0 /** Read the content of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_OP(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_OP_LSB, ATON_ARITH_CTRL_OP_W) /** Modify the content of the OP field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_OP(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_OP_LSB, ATON_ARITH_CTRL_OP_W, DATA) /** * Get the description of the OP field of CTRL register. * * \return the description of the OP field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_OP_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_OP_DESC; } /** * Read the content of the OP field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the OP field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_OP(uint32_t reg) { return ATON_ARITH_CTRL_GET_OP(reg); } /** * Write the content of the OP field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the OP field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_OP(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_OP(reg, data); } /* ----------------------------------------------------------- COEFFB field of the CTRL register ------------------------------------------------------------ */ /** Description of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFB_DESC "Coefficient type for B" /** Offset of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFB_LSB 21UL /** Size in bits of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFB_W (1UL) /** Mask for retrieving the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFB_MASK ATON_FIELD_MASK(21UL, 1UL) /** Reset value of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFB_DT 0x0UL /** Access rights of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFB_AC "RW" /** Check whether access to the COEFFB field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_COEFFB_S 0 /** Check whether access to the COEFFB field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_COEFFB_P 0 /** Read the content of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_COEFFB(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COEFFB_LSB, ATON_ARITH_CTRL_COEFFB_W) /** Modify the content of the COEFFB field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_COEFFB(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COEFFB_LSB, ATON_ARITH_CTRL_COEFFB_W, DATA) /** * Get the description of the COEFFB field of CTRL register. * * \return the description of the COEFFB field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_COEFFB_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_COEFFB_DESC; } /** * Read the content of the COEFFB field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the COEFFB field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_COEFFB(uint32_t reg) { return ATON_ARITH_CTRL_GET_COEFFB(reg); } /** * Write the content of the COEFFB field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the COEFFB field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_COEFFB(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_COEFFB(reg, data); } /* ----------------------------------------------------------- COEFFC field of the CTRL register ------------------------------------------------------------ */ /** Description of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFC_DESC "Coefficient type for C" /** Offset of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFC_LSB 22UL /** Size in bits of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFC_W (1UL) /** Mask for retrieving the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFC_MASK ATON_FIELD_MASK(22UL, 1UL) /** Reset value of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFC_DT 0x0UL /** Access rights of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_COEFFC_AC "RW" /** Check whether access to the COEFFC field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_COEFFC_S 0 /** Check whether access to the COEFFC field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_COEFFC_P 0 /** Read the content of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_COEFFC(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COEFFC_LSB, ATON_ARITH_CTRL_COEFFC_W) /** Modify the content of the COEFFC field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_COEFFC(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COEFFC_LSB, ATON_ARITH_CTRL_COEFFC_W, DATA) /** * Get the description of the COEFFC field of CTRL register. * * \return the description of the COEFFC field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_COEFFC_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_COEFFC_DESC; } /** * Read the content of the COEFFC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the COEFFC field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_COEFFC(uint32_t reg) { return ATON_ARITH_CTRL_GET_COEFFC(reg); } /** * Write the content of the COEFFC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the COEFFC field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_COEFFC(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_COEFFC(reg, data); } /* ---------------------------------------------------------- LOGICALOP field of the CTRL register ---------------------------------------------------------- */ /** Description of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_LOGICALOP_DESC "logical or bitwise operation for AND,OR,NOT,1=logical, 0=bitwise" /** Offset of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_LOGICALOP_LSB 23UL /** Size in bits of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_LOGICALOP_W (1UL) /** Mask for retrieving the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_LOGICALOP_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_LOGICALOP_DT 0x0UL /** Access rights of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_LOGICALOP_AC "RW" /** Check whether access to the LOGICALOP field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_LOGICALOP_S 0 /** Check whether access to the LOGICALOP field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_LOGICALOP_P 0 /** Read the content of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_LOGICALOP(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_LOGICALOP_LSB, ATON_ARITH_CTRL_LOGICALOP_W) /** Modify the content of the LOGICALOP field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_LOGICALOP(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_LOGICALOP_LSB, ATON_ARITH_CTRL_LOGICALOP_W, DATA) /** * Get the description of the LOGICALOP field of CTRL register. * * \return the description of the LOGICALOP field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_LOGICALOP_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_LOGICALOP_DESC; } /** * Read the content of the LOGICALOP field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the LOGICALOP field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_LOGICALOP(uint32_t reg) { return ATON_ARITH_CTRL_GET_LOGICALOP(reg); } /** * Write the content of the LOGICALOP field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the LOGICALOP field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_LOGICALOP(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_LOGICALOP(reg, data); } /* ---------------------------------------------------------- ORNDMODE field of the CTRL register ----------------------------------------------------------- */ /** Description of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_ORNDMODE_DESC "output rounding mode control. For more information see section: Rounding and Saturation. Valid values are 0 and 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_ORNDMODE_LSB 24UL /** Size in bits of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_ORNDMODE_W (2UL) /** Mask for retrieving the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_ORNDMODE_MASK ATON_FIELD_MASK(24UL, 2UL) /** Reset value of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_ORNDMODE_DT 0x0UL /** Access rights of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_ORNDMODE_AC "RW" /** Check whether access to the ORNDMODE field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_ORNDMODE_S 0 /** Check whether access to the ORNDMODE field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_ORNDMODE_P 0 /** Read the content of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_ORNDMODE_LSB, ATON_ARITH_CTRL_ORNDMODE_W) /** Modify the content of the ORNDMODE field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_ORNDMODE_LSB, ATON_ARITH_CTRL_ORNDMODE_W, DATA) /** * Get the description of the ORNDMODE field of CTRL register. * * \return the description of the ORNDMODE field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_ORNDMODE_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_ORNDMODE_DESC; } /** * Read the content of the ORNDMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ORNDMODE field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_ORNDMODE(uint32_t reg) { return ATON_ARITH_CTRL_GET_ORNDMODE(reg); } /** * Write the content of the ORNDMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ORNDMODE field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_ORNDMODE(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_ORNDMODE(reg, data); } /* ----------------------------------------------------------- OBYTES field of the CTRL register ------------------------------------------------------------ */ /** Description of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_OBYTES_DESC "number of output bytes: 1 or 2" /** Offset of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_OBYTES_LSB 26UL /** Size in bits of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_OBYTES_W (2UL) /** Mask for retrieving the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_OBYTES_MASK ATON_FIELD_MASK(26UL, 2UL) /** Reset value of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_OBYTES_DT 0x2UL /** Access rights of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_OBYTES_AC "RW" /** Check whether access to the OBYTES field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_OBYTES_S 0 /** Check whether access to the OBYTES field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_OBYTES_P 0 /** Read the content of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_OBYTES_LSB, ATON_ARITH_CTRL_OBYTES_W) /** Modify the content of the OBYTES field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_OBYTES_LSB, ATON_ARITH_CTRL_OBYTES_W, DATA) /** * Get the description of the OBYTES field of CTRL register. * * \return the description of the OBYTES field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_OBYTES_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_OBYTES_DESC; } /** * Read the content of the OBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the OBYTES field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_OBYTES(uint32_t reg) { return ATON_ARITH_CTRL_GET_OBYTES(reg); } /** * Write the content of the OBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the OBYTES field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_OBYTES(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_OBYTES(reg, data); } /* ---------------------------------------------------------- COMBINEBC field of the CTRL register ---------------------------------------------------------- */ /** Description of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_COMBINEBC_DESC "Combine coeff B and C to form a 32b coeff BC = {B[15:0],C[15:0]}" /** Offset of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_COMBINEBC_LSB 28UL /** Size in bits of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_COMBINEBC_W (1UL) /** Mask for retrieving the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_COMBINEBC_MASK ATON_FIELD_MASK(28UL, 1UL) /** Reset value of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_COMBINEBC_DT 0x0UL /** Access rights of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_COMBINEBC_AC "RW" /** Check whether access to the COMBINEBC field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_COMBINEBC_S 0 /** Check whether access to the COMBINEBC field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_COMBINEBC_P 0 /** Read the content of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_COMBINEBC(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_COMBINEBC_LSB, ATON_ARITH_CTRL_COMBINEBC_W) /** Modify the content of the COMBINEBC field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_COMBINEBC(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_COMBINEBC_LSB, ATON_ARITH_CTRL_COMBINEBC_W, DATA) /** * Get the description of the COMBINEBC field of CTRL register. * * \return the description of the COMBINEBC field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_COMBINEBC_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_COMBINEBC_DESC; } /** * Read the content of the COMBINEBC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the COMBINEBC field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_COMBINEBC(uint32_t reg) { return ATON_ARITH_CTRL_GET_COMBINEBC(reg); } /** * Write the content of the COMBINEBC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the COMBINEBC field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_COMBINEBC(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_COMBINEBC(reg, data); } /* ----------------------------------------------------------- CLIPOUT field of the CTRL register ----------------------------------------------------------- */ /** Description of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_CLIPOUT_DESC "Controls output clipping to range specified by clip range register. 1=enable,0=disable" /** Offset of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_CLIPOUT_LSB 29UL /** Size in bits of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_CLIPOUT_W (1UL) /** Mask for retrieving the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_CLIPOUT_MASK ATON_FIELD_MASK(29UL, 1UL) /** Reset value of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_CLIPOUT_DT 0x0UL /** Access rights of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_CLIPOUT_AC "RW" /** Check whether access to the CLIPOUT field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_CLIPOUT_S 0 /** Check whether access to the CLIPOUT field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_CLIPOUT_P 0 /** Read the content of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_CLIPOUT(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CLIPOUT_LSB, ATON_ARITH_CTRL_CLIPOUT_W) /** Modify the content of the CLIPOUT field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_CLIPOUT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CLIPOUT_LSB, ATON_ARITH_CTRL_CLIPOUT_W, DATA) /** * Get the description of the CLIPOUT field of CTRL register. * * \return the description of the CLIPOUT field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_CLIPOUT_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_CLIPOUT_DESC; } /** * Read the content of the CLIPOUT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLIPOUT field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_CLIPOUT(uint32_t reg) { return ATON_ARITH_CTRL_GET_CLIPOUT(reg); } /** * Write the content of the CLIPOUT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLIPOUT field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_CLIPOUT(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_CLIPOUT(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CONFCLR_DESC "Clear configuration registers (auto-cleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_ARITH_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_ARITH_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_ARITH_CTRL_CONFCLR_LSB, ATON_ARITH_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_ARITH_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CTRL_CONFCLR_LSB, ATON_ARITH_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_ARITH_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_ARITH_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_ARITH_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_ARITH_CTRL_SET_CONFCLR(reg, data); } /* ******************************************************* VERSION register of one of the ARITH Units ******************************************************* */ /** Offset of the VERSION register from the base address of the ARITH Unit. */ #define ATON_ARITH_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the ARITH Unit. */ #define ATON_ARITH_VERSION_DT \ (ATON_ARITH_VERSION_TYPE_DT << ATON_ARITH_VERSION_TYPE_LSB) | \ (ATON_ARITH_VERSION_MINOR_DT << ATON_ARITH_VERSION_MINOR_LSB) | \ (ATON_ARITH_VERSION_MAJOR_DT << ATON_ARITH_VERSION_MAJOR_LSB) /** Description of the VERSION register. */ #define ATON_ARITH_VERSION_DESC "Version register" /** Address of the VERSION register of one of the ARITH Units. */ #define ATON_ARITH_VERSION_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_VERSION_OFFSET) /** Get the content of the VERSION register of one of the ARITH Units. */ #define ATON_ARITH_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_ARITH_VERSION_GetDesc(void) { return (const int8_t *)ATON_ARITH_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_ARITH_VERSION_GetOffset(void) { return ATON_ARITH_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the VERSION register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_VERSION_GetAddr(uint32_t instance) { return ATON_ARITH_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_VERSION_Get(uint32_t instance) { return ATON_ARITH_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_TYPE_DT 0x1aUL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_ARITH_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_ARITH_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_ARITH_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_ARITH_VERSION_TYPE_LSB, ATON_ARITH_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_ARITH_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_ARITH_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_ARITH_VERSION_Get_TYPE(uint32_t reg) { return ATON_ARITH_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MINOR_DT 0x0UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_ARITH_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_ARITH_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_ARITH_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_ARITH_VERSION_MINOR_LSB, ATON_ARITH_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_ARITH_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_ARITH_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_ARITH_VERSION_Get_MINOR(uint32_t reg) { return ATON_ARITH_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_ARITH_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_ARITH_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_ARITH_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_ARITH_VERSION_MAJOR_LSB, ATON_ARITH_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_ARITH_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_ARITH_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_ARITH_VERSION_Get_MAJOR(uint32_t reg) { return ATON_ARITH_VERSION_GET_MAJOR(reg); } /* ******************************************************** SHIFT register of one of the ARITH Units ******************************************************** */ /** Offset of the SHIFT register from the base address of the ARITH Unit. */ #define ATON_ARITH_SHIFT_OFFSET 0x8UL /** Reset value of the SHIFT register of the ARITH Unit. */ #define ATON_ARITH_SHIFT_DT \ (ATON_ARITH_SHIFT_AX_DT << ATON_ARITH_SHIFT_AX_LSB) | \ (ATON_ARITH_SHIFT_BY_DT << ATON_ARITH_SHIFT_BY_LSB) | \ (ATON_ARITH_SHIFT_C_DT << ATON_ARITH_SHIFT_C_LSB) | \ (ATON_ARITH_SHIFT_RES_DT << ATON_ARITH_SHIFT_RES_LSB) /** Description of the SHIFT register. */ #define ATON_ARITH_SHIFT_DESC "Shift parameters" /** Address of the SHIFT register of one of the ARITH Units. */ #define ATON_ARITH_SHIFT_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_SHIFT_OFFSET) /** Get the content of the SHIFT register of one of the ARITH Units. */ #define ATON_ARITH_SHIFT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_SHIFT_ADDR(UNIT))) /** Set the content of the SHIFT register of one of the ARITH Units. */ #define ATON_ARITH_SHIFT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_SHIFT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of SHIFT register. * * \return the description of SHIFT register */ static inline const int8_t *ATON_ARITH_SHIFT_GetDesc(void) { return (const int8_t *)ATON_ARITH_SHIFT_DESC; } /** * Get the offset of the SHIFT register. * * \return the offset of SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_GetOffset(void) { return ATON_ARITH_SHIFT_OFFSET; } /** * Get the address of the SHIFT register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the SHIFT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of SHIFT register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_SHIFT_GetAddr(uint32_t instance) { return ATON_ARITH_SHIFT_ADDR(instance); } /** * Read the content of the SHIFT register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the SHIFT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of SHIFT register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_SHIFT_Get(uint32_t instance) { return ATON_ARITH_SHIFT_GET(instance); } /** * Write the content of the SHIFT register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the SHIFT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_SHIFT_Set(uint32_t instance, uint32_t data) { ATON_ARITH_SHIFT_SET(instance, data); } /* ------------------------------------------------------------- AX field of the SHIFT register ------------------------------------------------------------- */ /** Description of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_AX_DESC "Optional right shift to result of Ax" /** Offset of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_AX_LSB 0UL /** Size in bits of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_AX_W (5UL) /** Mask for retrieving the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_AX_MASK ATON_FIELD_MASK(0UL, 5UL) /** Reset value of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_AX_DT 0x0UL /** Access rights of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_AX_AC "RW" /** Check whether access to the AX field of the SHIFT register is secured or not. */ #define ATON_ARITH_SHIFT_AX_S 0 /** Check whether access to the AX field of the SHIFT register is privileged or not. */ #define ATON_ARITH_SHIFT_AX_P 0 /** Read the content of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_GET_AX(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_AX_LSB, ATON_ARITH_SHIFT_AX_W) /** Modify the content of the AX field of the SHIFT register. */ #define ATON_ARITH_SHIFT_SET_AX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_AX_LSB, ATON_ARITH_SHIFT_AX_W, DATA) /** * Get the description of the AX field of SHIFT register. * * \return the description of the AX field of SHIFT register */ static inline const int8_t *ATON_ARITH_SHIFT_AX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_SHIFT_AX_DESC; } /** * Read the content of the AX field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * * \return the content of the AX field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Get_AX(uint32_t reg) { return ATON_ARITH_SHIFT_GET_AX(reg); } /** * Write the content of the AX field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the AX field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Set_AX(uint32_t reg, uint32_t data) { return ATON_ARITH_SHIFT_SET_AX(reg, data); } /* ------------------------------------------------------------- BY field of the SHIFT register ------------------------------------------------------------- */ /** Description of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_BY_DESC "Optional right shift to result of By" /** Offset of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_BY_LSB 5UL /** Size in bits of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_BY_W (5UL) /** Mask for retrieving the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_BY_MASK ATON_FIELD_MASK(5UL, 5UL) /** Reset value of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_BY_DT 0x0UL /** Access rights of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_BY_AC "RW" /** Check whether access to the BY field of the SHIFT register is secured or not. */ #define ATON_ARITH_SHIFT_BY_S 0 /** Check whether access to the BY field of the SHIFT register is privileged or not. */ #define ATON_ARITH_SHIFT_BY_P 0 /** Read the content of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_GET_BY(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_BY_LSB, ATON_ARITH_SHIFT_BY_W) /** Modify the content of the BY field of the SHIFT register. */ #define ATON_ARITH_SHIFT_SET_BY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_BY_LSB, ATON_ARITH_SHIFT_BY_W, DATA) /** * Get the description of the BY field of SHIFT register. * * \return the description of the BY field of SHIFT register */ static inline const int8_t *ATON_ARITH_SHIFT_BY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_SHIFT_BY_DESC; } /** * Read the content of the BY field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * * \return the content of the BY field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Get_BY(uint32_t reg) { return ATON_ARITH_SHIFT_GET_BY(reg); } /** * Write the content of the BY field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the BY field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Set_BY(uint32_t reg, uint32_t data) { return ATON_ARITH_SHIFT_SET_BY(reg, data); } /* ------------------------------------------------------------- C field of the SHIFT register -------------------------------------------------------------- */ /** Description of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_C_DESC "Optional left shift to apply to C" /** Offset of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_C_LSB 10UL /** Size in bits of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_C_W (5UL) /** Mask for retrieving the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_C_MASK ATON_FIELD_MASK(10UL, 5UL) /** Reset value of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_C_DT 0x0UL /** Access rights of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_C_AC "RW" /** Check whether access to the C field of the SHIFT register is secured or not. */ #define ATON_ARITH_SHIFT_C_S 0 /** Check whether access to the C field of the SHIFT register is privileged or not. */ #define ATON_ARITH_SHIFT_C_P 0 /** Read the content of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_GET_C(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_C_LSB, ATON_ARITH_SHIFT_C_W) /** Modify the content of the C field of the SHIFT register. */ #define ATON_ARITH_SHIFT_SET_C(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_C_LSB, ATON_ARITH_SHIFT_C_W, DATA) /** * Get the description of the C field of SHIFT register. * * \return the description of the C field of SHIFT register */ static inline const int8_t *ATON_ARITH_SHIFT_C_GetdDesc(void) { return (const int8_t *)ATON_ARITH_SHIFT_C_DESC; } /** * Read the content of the C field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * * \return the content of the C field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Get_C(uint32_t reg) { return ATON_ARITH_SHIFT_GET_C(reg); } /** * Write the content of the C field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the C field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Set_C(uint32_t reg, uint32_t data) { return ATON_ARITH_SHIFT_SET_C(reg, data); } /* ------------------------------------------------------------ RES field of the SHIFT register ------------------------------------------------------------- */ /** Description of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_RES_DESC "Optional right shift to apply to final result of operation" /** Offset of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_RES_LSB 15UL /** Size in bits of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_RES_W (6UL) /** Mask for retrieving the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_RES_MASK ATON_FIELD_MASK(15UL, 6UL) /** Reset value of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_RES_DT 0x0UL /** Access rights of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_RES_AC "RW" /** Check whether access to the RES field of the SHIFT register is secured or not. */ #define ATON_ARITH_SHIFT_RES_S 0 /** Check whether access to the RES field of the SHIFT register is privileged or not. */ #define ATON_ARITH_SHIFT_RES_P 0 /** Read the content of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_GET_RES(REG) ATON_GET_FIELD(REG, ATON_ARITH_SHIFT_RES_LSB, ATON_ARITH_SHIFT_RES_W) /** Modify the content of the RES field of the SHIFT register. */ #define ATON_ARITH_SHIFT_SET_RES(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_SHIFT_RES_LSB, ATON_ARITH_SHIFT_RES_W, DATA) /** * Get the description of the RES field of SHIFT register. * * \return the description of the RES field of SHIFT register */ static inline const int8_t *ATON_ARITH_SHIFT_RES_GetdDesc(void) { return (const int8_t *)ATON_ARITH_SHIFT_RES_DESC; } /** * Read the content of the RES field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * * \return the content of the RES field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Get_RES(uint32_t reg) { return ATON_ARITH_SHIFT_GET_RES(reg); } /** * Write the content of the RES field of the SHIFT register. * * \param[in] reg is the value of the SHIFT register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the RES field belonging to SHIFT register */ static inline uint32_t ATON_ARITH_SHIFT_Set_RES(uint32_t reg, uint32_t data) { return ATON_ARITH_SHIFT_SET_RES(reg, data); } /* ******************************************************* INCCNT register of one of the ARITH Units ******************************************************** */ /** Offset of the INCCNT register from the base address of the ARITH Unit. */ #define ATON_ARITH_INCCNT_OFFSET 0xcUL /** Reset value of the INCCNT register of the ARITH Unit. */ #define ATON_ARITH_INCCNT_DT \ (ATON_ARITH_INCCNT_INCVAL_DT << ATON_ARITH_INCCNT_INCVAL_LSB) /** Description of the INCCNT register. */ #define ATON_ARITH_INCCNT_DESC "Increment counter" /** Address of the INCCNT register of one of the ARITH Units. */ #define ATON_ARITH_INCCNT_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_INCCNT_OFFSET) /** Get the content of the INCCNT register of one of the ARITH Units. */ #define ATON_ARITH_INCCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCCNT_ADDR(UNIT))) /** Set the content of the INCCNT register of one of the ARITH Units. */ #define ATON_ARITH_INCCNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCCNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INCCNT register. * * \return the description of INCCNT register */ static inline const int8_t *ATON_ARITH_INCCNT_GetDesc(void) { return (const int8_t *)ATON_ARITH_INCCNT_DESC; } /** * Get the offset of the INCCNT register. * * \return the offset of INCCNT register */ static inline uint32_t ATON_ARITH_INCCNT_GetOffset(void) { return ATON_ARITH_INCCNT_OFFSET; } /** * Get the address of the INCCNT register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCCNT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of INCCNT register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_INCCNT_GetAddr(uint32_t instance) { return ATON_ARITH_INCCNT_ADDR(instance); } /** * Read the content of the INCCNT register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCCNT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of INCCNT register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_INCCNT_Get(uint32_t instance) { return ATON_ARITH_INCCNT_GET(instance); } /** * Write the content of the INCCNT register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCCNT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_INCCNT_Set(uint32_t instance, uint32_t data) { ATON_ARITH_INCCNT_SET(instance, data); } /* ---------------------------------------------------------- INCVAL field of the INCCNT register ----------------------------------------------------------- */ /** Description of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_INCVAL_DESC "Counter value, this controls when the address will be updated (INCOFFSET will be added to the current address when this counter with its programmed value, INCVAL, expires)" /** Offset of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_INCVAL_LSB 0UL /** Size in bits of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_INCVAL_W (27UL) /** Mask for retrieving the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_INCVAL_MASK ATON_FIELD_MASK(0UL, 27UL) /** Reset value of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_INCVAL_DT 0x0UL /** Access rights of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_INCVAL_AC "RW" /** Check whether access to the INCVAL field of the INCCNT register is secured or not. */ #define ATON_ARITH_INCCNT_INCVAL_S 0 /** Check whether access to the INCVAL field of the INCCNT register is privileged or not. */ #define ATON_ARITH_INCCNT_INCVAL_P 0 /** Read the content of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_GET_INCVAL(REG) ATON_GET_FIELD(REG, ATON_ARITH_INCCNT_INCVAL_LSB, ATON_ARITH_INCCNT_INCVAL_W) /** Modify the content of the INCVAL field of the INCCNT register. */ #define ATON_ARITH_INCCNT_SET_INCVAL(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INCCNT_INCVAL_LSB, ATON_ARITH_INCCNT_INCVAL_W, DATA) /** * Get the description of the INCVAL field of INCCNT register. * * \return the description of the INCVAL field of INCCNT register */ static inline const int8_t *ATON_ARITH_INCCNT_INCVAL_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INCCNT_INCVAL_DESC; } /** * Read the content of the INCVAL field of the INCCNT register. * * \param[in] reg is the value of the INCCNT register * * \return the content of the INCVAL field belonging to INCCNT register */ static inline uint32_t ATON_ARITH_INCCNT_Get_INCVAL(uint32_t reg) { return ATON_ARITH_INCCNT_GET_INCVAL(reg); } /** * Write the content of the INCVAL field of the INCCNT register. * * \param[in] reg is the value of the INCCNT register * \param[in] data is 27-bit value that must be written to the field * * \return the new content of the INCVAL field belonging to INCCNT register */ static inline uint32_t ATON_ARITH_INCCNT_Set_INCVAL(uint32_t reg, uint32_t data) { return ATON_ARITH_INCCNT_SET_INCVAL(reg, data); } /* ******************************************************* RSTCNT1 register of one of the ARITH Units ******************************************************* */ /** Offset of the RSTCNT1 register from the base address of the ARITH Unit. */ #define ATON_ARITH_RSTCNT1_OFFSET 0x10UL /** Reset value of the RSTCNT1 register of the ARITH Unit. */ #define ATON_ARITH_RSTCNT1_DT \ (ATON_ARITH_RSTCNT1_RSTCNT_DT << ATON_ARITH_RSTCNT1_RSTCNT_LSB) /** Description of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_DESC "Reset counter 1" /** Address of the RSTCNT1 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT1_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_RSTCNT1_OFFSET) /** Get the content of the RSTCNT1 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT1_ADDR(UNIT))) /** Set the content of the RSTCNT1 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of RSTCNT1 register. * * \return the description of RSTCNT1 register */ static inline const int8_t *ATON_ARITH_RSTCNT1_GetDesc(void) { return (const int8_t *)ATON_ARITH_RSTCNT1_DESC; } /** * Get the offset of the RSTCNT1 register. * * \return the offset of RSTCNT1 register */ static inline uint32_t ATON_ARITH_RSTCNT1_GetOffset(void) { return ATON_ARITH_RSTCNT1_OFFSET; } /** * Get the address of the RSTCNT1 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT1 register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of RSTCNT1 register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_RSTCNT1_GetAddr(uint32_t instance) { return ATON_ARITH_RSTCNT1_ADDR(instance); } /** * Read the content of the RSTCNT1 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT1 register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of RSTCNT1 register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_RSTCNT1_Get(uint32_t instance) { return ATON_ARITH_RSTCNT1_GET(instance); } /** * Write the content of the RSTCNT1 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT1 register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_RSTCNT1_Set(uint32_t instance, uint32_t data) { ATON_ARITH_RSTCNT1_SET(instance, data); } /* ---------------------------------------------------------- RSTCNT field of the RSTCNT1 register ---------------------------------------------------------- */ /** Description of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_RSTCNT_DESC "Counter value, this controls when the address will be updated (the corresponding OFFSETx in ADDROFFSET will be added to the current address when this counter with its programmed value, RSTCNTx, expires)" /** Offset of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_RSTCNT_LSB 0UL /** Size in bits of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_RSTCNT_W (27UL) /** Mask for retrieving the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_RSTCNT_MASK ATON_FIELD_MASK(0UL, 27UL) /** Reset value of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_RSTCNT_DT 0x0UL /** Access rights of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_RSTCNT_AC "RW" /** Check whether access to the RSTCNT field of the RSTCNT1 register is secured or not. */ #define ATON_ARITH_RSTCNT1_RSTCNT_S 0 /** Check whether access to the RSTCNT field of the RSTCNT1 register is privileged or not. */ #define ATON_ARITH_RSTCNT1_RSTCNT_P 0 /** Read the content of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_GET_RSTCNT(REG) ATON_GET_FIELD(REG, ATON_ARITH_RSTCNT1_RSTCNT_LSB, ATON_ARITH_RSTCNT1_RSTCNT_W) /** Modify the content of the RSTCNT field of the RSTCNT1 register. */ #define ATON_ARITH_RSTCNT1_SET_RSTCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_RSTCNT1_RSTCNT_LSB, ATON_ARITH_RSTCNT1_RSTCNT_W, DATA) /** * Get the description of the RSTCNT field of RSTCNT1 register. * * \return the description of the RSTCNT field of RSTCNT1 register */ static inline const int8_t *ATON_ARITH_RSTCNT1_RSTCNT_GetdDesc(void) { return (const int8_t *)ATON_ARITH_RSTCNT1_RSTCNT_DESC; } /** * Read the content of the RSTCNT field of the RSTCNT1 register. * * \param[in] reg is the value of the RSTCNT1 register * * \return the content of the RSTCNT field belonging to RSTCNT1 register */ static inline uint32_t ATON_ARITH_RSTCNT1_Get_RSTCNT(uint32_t reg) { return ATON_ARITH_RSTCNT1_GET_RSTCNT(reg); } /** * Write the content of the RSTCNT field of the RSTCNT1 register. * * \param[in] reg is the value of the RSTCNT1 register * \param[in] data is 27-bit value that must be written to the field * * \return the new content of the RSTCNT field belonging to RSTCNT1 register */ static inline uint32_t ATON_ARITH_RSTCNT1_Set_RSTCNT(uint32_t reg, uint32_t data) { return ATON_ARITH_RSTCNT1_SET_RSTCNT(reg, data); } /* ******************************************************* RSTCNT2 register of one of the ARITH Units ******************************************************* */ /** Offset of the RSTCNT2 register from the base address of the ARITH Unit. */ #define ATON_ARITH_RSTCNT2_OFFSET 0x14UL /** Reset value of the RSTCNT2 register of the ARITH Unit. */ #define ATON_ARITH_RSTCNT2_DT \ (ATON_ARITH_RSTCNT2_RSTCNT_DT << ATON_ARITH_RSTCNT2_RSTCNT_LSB) /** Description of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_DESC "Reset counter 2" /** Address of the RSTCNT2 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT2_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_RSTCNT2_OFFSET) /** Get the content of the RSTCNT2 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT2_ADDR(UNIT))) /** Set the content of the RSTCNT2 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of RSTCNT2 register. * * \return the description of RSTCNT2 register */ static inline const int8_t *ATON_ARITH_RSTCNT2_GetDesc(void) { return (const int8_t *)ATON_ARITH_RSTCNT2_DESC; } /** * Get the offset of the RSTCNT2 register. * * \return the offset of RSTCNT2 register */ static inline uint32_t ATON_ARITH_RSTCNT2_GetOffset(void) { return ATON_ARITH_RSTCNT2_OFFSET; } /** * Get the address of the RSTCNT2 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT2 register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of RSTCNT2 register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_RSTCNT2_GetAddr(uint32_t instance) { return ATON_ARITH_RSTCNT2_ADDR(instance); } /** * Read the content of the RSTCNT2 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT2 register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of RSTCNT2 register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_RSTCNT2_Get(uint32_t instance) { return ATON_ARITH_RSTCNT2_GET(instance); } /** * Write the content of the RSTCNT2 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT2 register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_RSTCNT2_Set(uint32_t instance, uint32_t data) { ATON_ARITH_RSTCNT2_SET(instance, data); } /* ---------------------------------------------------------- RSTCNT field of the RSTCNT2 register ---------------------------------------------------------- */ /** Description of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_RSTCNT_DESC "Counter value, this controls when the address will be updated (the corresponding OFFSETx in ADDROFFSET will be added to the current address when this counter with its programmed value, RSTCNTx, expires)" /** Offset of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_RSTCNT_LSB 0UL /** Size in bits of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_RSTCNT_W (27UL) /** Mask for retrieving the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_RSTCNT_MASK ATON_FIELD_MASK(0UL, 27UL) /** Reset value of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_RSTCNT_DT 0x0UL /** Access rights of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_RSTCNT_AC "RW" /** Check whether access to the RSTCNT field of the RSTCNT2 register is secured or not. */ #define ATON_ARITH_RSTCNT2_RSTCNT_S 0 /** Check whether access to the RSTCNT field of the RSTCNT2 register is privileged or not. */ #define ATON_ARITH_RSTCNT2_RSTCNT_P 0 /** Read the content of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_GET_RSTCNT(REG) ATON_GET_FIELD(REG, ATON_ARITH_RSTCNT2_RSTCNT_LSB, ATON_ARITH_RSTCNT2_RSTCNT_W) /** Modify the content of the RSTCNT field of the RSTCNT2 register. */ #define ATON_ARITH_RSTCNT2_SET_RSTCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_RSTCNT2_RSTCNT_LSB, ATON_ARITH_RSTCNT2_RSTCNT_W, DATA) /** * Get the description of the RSTCNT field of RSTCNT2 register. * * \return the description of the RSTCNT field of RSTCNT2 register */ static inline const int8_t *ATON_ARITH_RSTCNT2_RSTCNT_GetdDesc(void) { return (const int8_t *)ATON_ARITH_RSTCNT2_RSTCNT_DESC; } /** * Read the content of the RSTCNT field of the RSTCNT2 register. * * \param[in] reg is the value of the RSTCNT2 register * * \return the content of the RSTCNT field belonging to RSTCNT2 register */ static inline uint32_t ATON_ARITH_RSTCNT2_Get_RSTCNT(uint32_t reg) { return ATON_ARITH_RSTCNT2_GET_RSTCNT(reg); } /** * Write the content of the RSTCNT field of the RSTCNT2 register. * * \param[in] reg is the value of the RSTCNT2 register * \param[in] data is 27-bit value that must be written to the field * * \return the new content of the RSTCNT field belonging to RSTCNT2 register */ static inline uint32_t ATON_ARITH_RSTCNT2_Set_RSTCNT(uint32_t reg, uint32_t data) { return ATON_ARITH_RSTCNT2_SET_RSTCNT(reg, data); } /* ******************************************************* RSTCNT3 register of one of the ARITH Units ******************************************************* */ /** Offset of the RSTCNT3 register from the base address of the ARITH Unit. */ #define ATON_ARITH_RSTCNT3_OFFSET 0x18UL /** Reset value of the RSTCNT3 register of the ARITH Unit. */ #define ATON_ARITH_RSTCNT3_DT \ (ATON_ARITH_RSTCNT3_RSTCNT_DT << ATON_ARITH_RSTCNT3_RSTCNT_LSB) /** Description of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_DESC "Reset counter 3" /** Address of the RSTCNT3 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT3_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_RSTCNT3_OFFSET) /** Get the content of the RSTCNT3 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT3_ADDR(UNIT))) /** Set the content of the RSTCNT3 register of one of the ARITH Units. */ #define ATON_ARITH_RSTCNT3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_RSTCNT3_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of RSTCNT3 register. * * \return the description of RSTCNT3 register */ static inline const int8_t *ATON_ARITH_RSTCNT3_GetDesc(void) { return (const int8_t *)ATON_ARITH_RSTCNT3_DESC; } /** * Get the offset of the RSTCNT3 register. * * \return the offset of RSTCNT3 register */ static inline uint32_t ATON_ARITH_RSTCNT3_GetOffset(void) { return ATON_ARITH_RSTCNT3_OFFSET; } /** * Get the address of the RSTCNT3 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT3 register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of RSTCNT3 register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_RSTCNT3_GetAddr(uint32_t instance) { return ATON_ARITH_RSTCNT3_ADDR(instance); } /** * Read the content of the RSTCNT3 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT3 register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of RSTCNT3 register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_RSTCNT3_Get(uint32_t instance) { return ATON_ARITH_RSTCNT3_GET(instance); } /** * Write the content of the RSTCNT3 register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the RSTCNT3 register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_RSTCNT3_Set(uint32_t instance, uint32_t data) { ATON_ARITH_RSTCNT3_SET(instance, data); } /* ---------------------------------------------------------- RSTCNT field of the RSTCNT3 register ---------------------------------------------------------- */ /** Description of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_RSTCNT_DESC "Counter value, this controls when the address will be updated (the corresponding OFFSETx in ADDROFFSET will be added to the current address when this counter with its programmed value, RSTCNTx, expires)" /** Offset of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_RSTCNT_LSB 0UL /** Size in bits of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_RSTCNT_W (27UL) /** Mask for retrieving the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_RSTCNT_MASK ATON_FIELD_MASK(0UL, 27UL) /** Reset value of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_RSTCNT_DT 0x0UL /** Access rights of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_RSTCNT_AC "RW" /** Check whether access to the RSTCNT field of the RSTCNT3 register is secured or not. */ #define ATON_ARITH_RSTCNT3_RSTCNT_S 0 /** Check whether access to the RSTCNT field of the RSTCNT3 register is privileged or not. */ #define ATON_ARITH_RSTCNT3_RSTCNT_P 0 /** Read the content of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_GET_RSTCNT(REG) ATON_GET_FIELD(REG, ATON_ARITH_RSTCNT3_RSTCNT_LSB, ATON_ARITH_RSTCNT3_RSTCNT_W) /** Modify the content of the RSTCNT field of the RSTCNT3 register. */ #define ATON_ARITH_RSTCNT3_SET_RSTCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_RSTCNT3_RSTCNT_LSB, ATON_ARITH_RSTCNT3_RSTCNT_W, DATA) /** * Get the description of the RSTCNT field of RSTCNT3 register. * * \return the description of the RSTCNT field of RSTCNT3 register */ static inline const int8_t *ATON_ARITH_RSTCNT3_RSTCNT_GetdDesc(void) { return (const int8_t *)ATON_ARITH_RSTCNT3_RSTCNT_DESC; } /** * Read the content of the RSTCNT field of the RSTCNT3 register. * * \param[in] reg is the value of the RSTCNT3 register * * \return the content of the RSTCNT field belonging to RSTCNT3 register */ static inline uint32_t ATON_ARITH_RSTCNT3_Get_RSTCNT(uint32_t reg) { return ATON_ARITH_RSTCNT3_GET_RSTCNT(reg); } /** * Write the content of the RSTCNT field of the RSTCNT3 register. * * \param[in] reg is the value of the RSTCNT3 register * \param[in] data is 27-bit value that must be written to the field * * \return the new content of the RSTCNT field belonging to RSTCNT3 register */ static inline uint32_t ATON_ARITH_RSTCNT3_Set_RSTCNT(uint32_t reg, uint32_t data) { return ATON_ARITH_RSTCNT3_SET_RSTCNT(reg, data); } /* ******************************************************* COEFFAC register of one of the ARITH Units ******************************************************* */ /** Offset of the COEFFAC register from the base address of the ARITH Unit. */ #define ATON_ARITH_COEFFAC_OFFSET 0x1cUL /** Reset value of the COEFFAC register of the ARITH Unit. */ #define ATON_ARITH_COEFFAC_DT \ (ATON_ARITH_COEFFAC_A_DT << ATON_ARITH_COEFFAC_A_LSB) | \ (ATON_ARITH_COEFFAC_C_DT << ATON_ARITH_COEFFAC_C_LSB) /** Description of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_DESC "Scalar coefficients A and C" /** Address of the COEFFAC register of one of the ARITH Units. */ #define ATON_ARITH_COEFFAC_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFFAC_OFFSET) /** Get the content of the COEFFAC register of one of the ARITH Units. */ #define ATON_ARITH_COEFFAC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFAC_ADDR(UNIT))) /** Set the content of the COEFFAC register of one of the ARITH Units. */ #define ATON_ARITH_COEFFAC_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFAC_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of COEFFAC register. * * \return the description of COEFFAC register */ static inline const int8_t *ATON_ARITH_COEFFAC_GetDesc(void) { return (const int8_t *)ATON_ARITH_COEFFAC_DESC; } /** * Get the offset of the COEFFAC register. * * \return the offset of COEFFAC register */ static inline uint32_t ATON_ARITH_COEFFAC_GetOffset(void) { return ATON_ARITH_COEFFAC_OFFSET; } /** * Get the address of the COEFFAC register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFAC register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of COEFFAC register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_COEFFAC_GetAddr(uint32_t instance) { return ATON_ARITH_COEFFAC_ADDR(instance); } /** * Read the content of the COEFFAC register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFAC register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of COEFFAC register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_COEFFAC_Get(uint32_t instance) { return ATON_ARITH_COEFFAC_GET(instance); } /** * Write the content of the COEFFAC register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFAC register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_COEFFAC_Set(uint32_t instance, uint32_t data) { ATON_ARITH_COEFFAC_SET(instance, data); } /* ------------------------------------------------------------ A field of the COEFFAC register ------------------------------------------------------------- */ /** Description of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_A_DESC "Scalar coefficient A" /** Offset of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_A_LSB 0UL /** Size in bits of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_A_W (16UL) /** Mask for retrieving the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_A_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_A_DT 0x0UL /** Access rights of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_A_AC "RW" /** Check whether access to the A field of the COEFFAC register is secured or not. */ #define ATON_ARITH_COEFFAC_A_S 0 /** Check whether access to the A field of the COEFFAC register is privileged or not. */ #define ATON_ARITH_COEFFAC_A_P 0 /** Read the content of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_GET_A(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFAC_A_LSB, ATON_ARITH_COEFFAC_A_W) /** Modify the content of the A field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_SET_A(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFAC_A_LSB, ATON_ARITH_COEFFAC_A_W, DATA) /** * Get the description of the A field of COEFFAC register. * * \return the description of the A field of COEFFAC register */ static inline const int8_t *ATON_ARITH_COEFFAC_A_GetdDesc(void) { return (const int8_t *)ATON_ARITH_COEFFAC_A_DESC; } /** * Read the content of the A field of the COEFFAC register. * * \param[in] reg is the value of the COEFFAC register * * \return the content of the A field belonging to COEFFAC register */ static inline uint32_t ATON_ARITH_COEFFAC_Get_A(uint32_t reg) { return ATON_ARITH_COEFFAC_GET_A(reg); } /** * Write the content of the A field of the COEFFAC register. * * \param[in] reg is the value of the COEFFAC register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the A field belonging to COEFFAC register */ static inline uint32_t ATON_ARITH_COEFFAC_Set_A(uint32_t reg, uint32_t data) { return ATON_ARITH_COEFFAC_SET_A(reg, data); } /* ------------------------------------------------------------ C field of the COEFFAC register ------------------------------------------------------------- */ /** Description of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_C_DESC "Scalar coefficient C" /** Offset of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_C_LSB 16UL /** Size in bits of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_C_W (16UL) /** Mask for retrieving the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_C_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_C_DT 0x0UL /** Access rights of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_C_AC "RW" /** Check whether access to the C field of the COEFFAC register is secured or not. */ #define ATON_ARITH_COEFFAC_C_S 0 /** Check whether access to the C field of the COEFFAC register is privileged or not. */ #define ATON_ARITH_COEFFAC_C_P 0 /** Read the content of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_GET_C(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFAC_C_LSB, ATON_ARITH_COEFFAC_C_W) /** Modify the content of the C field of the COEFFAC register. */ #define ATON_ARITH_COEFFAC_SET_C(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFAC_C_LSB, ATON_ARITH_COEFFAC_C_W, DATA) /** * Get the description of the C field of COEFFAC register. * * \return the description of the C field of COEFFAC register */ static inline const int8_t *ATON_ARITH_COEFFAC_C_GetdDesc(void) { return (const int8_t *)ATON_ARITH_COEFFAC_C_DESC; } /** * Read the content of the C field of the COEFFAC register. * * \param[in] reg is the value of the COEFFAC register * * \return the content of the C field belonging to COEFFAC register */ static inline uint32_t ATON_ARITH_COEFFAC_Get_C(uint32_t reg) { return ATON_ARITH_COEFFAC_GET_C(reg); } /** * Write the content of the C field of the COEFFAC register. * * \param[in] reg is the value of the COEFFAC register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the C field belonging to COEFFAC register */ static inline uint32_t ATON_ARITH_COEFFAC_Set_C(uint32_t reg, uint32_t data) { return ATON_ARITH_COEFFAC_SET_C(reg, data); } /* ******************************************************* COEFFB register of one of the ARITH Units ******************************************************** */ /** Offset of the COEFFB register from the base address of the ARITH Unit. */ #define ATON_ARITH_COEFFB_OFFSET 0x20UL /** Reset value of the COEFFB register of the ARITH Unit. */ #define ATON_ARITH_COEFFB_DT \ (ATON_ARITH_COEFFB_B_DT << ATON_ARITH_COEFFB_B_LSB) /** Description of the COEFFB register. */ #define ATON_ARITH_COEFFB_DESC "Scalar coefficient B" /** Address of the COEFFB register of one of the ARITH Units. */ #define ATON_ARITH_COEFFB_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFFB_OFFSET) /** Get the content of the COEFFB register of one of the ARITH Units. */ #define ATON_ARITH_COEFFB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFB_ADDR(UNIT))) /** Set the content of the COEFFB register of one of the ARITH Units. */ #define ATON_ARITH_COEFFB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of COEFFB register. * * \return the description of COEFFB register */ static inline const int8_t *ATON_ARITH_COEFFB_GetDesc(void) { return (const int8_t *)ATON_ARITH_COEFFB_DESC; } /** * Get the offset of the COEFFB register. * * \return the offset of COEFFB register */ static inline uint32_t ATON_ARITH_COEFFB_GetOffset(void) { return ATON_ARITH_COEFFB_OFFSET; } /** * Get the address of the COEFFB register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFB register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of COEFFB register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_COEFFB_GetAddr(uint32_t instance) { return ATON_ARITH_COEFFB_ADDR(instance); } /** * Read the content of the COEFFB register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFB register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of COEFFB register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_COEFFB_Get(uint32_t instance) { return ATON_ARITH_COEFFB_GET(instance); } /** * Write the content of the COEFFB register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFB register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_COEFFB_Set(uint32_t instance, uint32_t data) { ATON_ARITH_COEFFB_SET(instance, data); } /* ------------------------------------------------------------- B field of the COEFFB register ------------------------------------------------------------- */ /** Description of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_B_DESC "Scalar coefficient B" /** Offset of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_B_LSB 0UL /** Size in bits of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_B_W (16UL) /** Mask for retrieving the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_B_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_B_DT 0x0UL /** Access rights of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_B_AC "RW" /** Check whether access to the B field of the COEFFB register is secured or not. */ #define ATON_ARITH_COEFFB_B_S 0 /** Check whether access to the B field of the COEFFB register is privileged or not. */ #define ATON_ARITH_COEFFB_B_P 0 /** Read the content of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_GET_B(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFB_B_LSB, ATON_ARITH_COEFFB_B_W) /** Modify the content of the B field of the COEFFB register. */ #define ATON_ARITH_COEFFB_SET_B(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFB_B_LSB, ATON_ARITH_COEFFB_B_W, DATA) /** * Get the description of the B field of COEFFB register. * * \return the description of the B field of COEFFB register */ static inline const int8_t *ATON_ARITH_COEFFB_B_GetdDesc(void) { return (const int8_t *)ATON_ARITH_COEFFB_B_DESC; } /** * Read the content of the B field of the COEFFB register. * * \param[in] reg is the value of the COEFFB register * * \return the content of the B field belonging to COEFFB register */ static inline uint32_t ATON_ARITH_COEFFB_Get_B(uint32_t reg) { return ATON_ARITH_COEFFB_GET_B(reg); } /** * Write the content of the B field of the COEFFB register. * * \param[in] reg is the value of the COEFFB register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the B field belonging to COEFFB register */ static inline uint32_t ATON_ARITH_COEFFB_Set_B(uint32_t reg, uint32_t data) { return ATON_ARITH_COEFFB_SET_B(reg, data); } /* ***************************************************** ADDROFFSET register of one of the ARITH Units ****************************************************** */ /** Offset of the ADDROFFSET register from the base address of the ARITH Unit. */ #define ATON_ARITH_ADDROFFSET_OFFSET 0x24UL /** Reset value of the ADDROFFSET register of the ARITH Unit. */ #define ATON_ARITH_ADDROFFSET_DT \ (ATON_ARITH_ADDROFFSET_OFFSET1_DT << ATON_ARITH_ADDROFFSET_OFFSET1_LSB) | \ (ATON_ARITH_ADDROFFSET_OFFSET2_DT << ATON_ARITH_ADDROFFSET_OFFSET2_LSB) | \ (ATON_ARITH_ADDROFFSET_OFFSET3_DT << ATON_ARITH_ADDROFFSET_OFFSET3_LSB) /** Description of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_DESC "Address offsets" /** Address of the ADDROFFSET register of one of the ARITH Units. */ #define ATON_ARITH_ADDROFFSET_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_ADDROFFSET_OFFSET) /** Get the content of the ADDROFFSET register of one of the ARITH Units. */ #define ATON_ARITH_ADDROFFSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_ADDROFFSET_ADDR(UNIT))) /** Set the content of the ADDROFFSET register of one of the ARITH Units. */ #define ATON_ARITH_ADDROFFSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_ADDROFFSET_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ADDROFFSET register. * * \return the description of ADDROFFSET register */ static inline const int8_t *ATON_ARITH_ADDROFFSET_GetDesc(void) { return (const int8_t *)ATON_ARITH_ADDROFFSET_DESC; } /** * Get the offset of the ADDROFFSET register. * * \return the offset of ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_GetOffset(void) { return ATON_ARITH_ADDROFFSET_OFFSET; } /** * Get the address of the ADDROFFSET register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the ADDROFFSET register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of ADDROFFSET register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_ADDROFFSET_GetAddr(uint32_t instance) { return ATON_ARITH_ADDROFFSET_ADDR(instance); } /** * Read the content of the ADDROFFSET register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the ADDROFFSET register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of ADDROFFSET register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_ADDROFFSET_Get(uint32_t instance) { return ATON_ARITH_ADDROFFSET_GET(instance); } /** * Write the content of the ADDROFFSET register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the ADDROFFSET register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_ADDROFFSET_Set(uint32_t instance, uint32_t data) { ATON_ARITH_ADDROFFSET_SET(instance, data); } /* -------------------------------------------------------- OFFSET1 field of the ADDROFFSET register -------------------------------------------------------- */ /** Description of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_DESC "Offset to be added to address when reset counter RSTCNT1 expires" /** Offset of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_LSB 0UL /** Size in bits of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_W (9UL) /** Mask for retrieving the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_MASK ATON_FIELD_MASK(0UL, 9UL) /** Reset value of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_DT 0x0UL /** Access rights of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_AC "RW" /** Check whether access to the OFFSET1 field of the ADDROFFSET register is secured or not. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_S 0 /** Check whether access to the OFFSET1 field of the ADDROFFSET register is privileged or not. */ #define ATON_ARITH_ADDROFFSET_OFFSET1_P 0 /** Read the content of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_GET_OFFSET1(REG) ATON_GET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET1_LSB, ATON_ARITH_ADDROFFSET_OFFSET1_W) /** Modify the content of the OFFSET1 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_SET_OFFSET1(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET1_LSB, ATON_ARITH_ADDROFFSET_OFFSET1_W, DATA) /** * Get the description of the OFFSET1 field of ADDROFFSET register. * * \return the description of the OFFSET1 field of ADDROFFSET register */ static inline const int8_t *ATON_ARITH_ADDROFFSET_OFFSET1_GetdDesc(void) { return (const int8_t *)ATON_ARITH_ADDROFFSET_OFFSET1_DESC; } /** * Read the content of the OFFSET1 field of the ADDROFFSET register. * * \param[in] reg is the value of the ADDROFFSET register * * \return the content of the OFFSET1 field belonging to ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_Get_OFFSET1(uint32_t reg) { return ATON_ARITH_ADDROFFSET_GET_OFFSET1(reg); } /** * Write the content of the OFFSET1 field of the ADDROFFSET register. * * \param[in] reg is the value of the ADDROFFSET register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the OFFSET1 field belonging to ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_Set_OFFSET1(uint32_t reg, uint32_t data) { return ATON_ARITH_ADDROFFSET_SET_OFFSET1(reg, data); } /* -------------------------------------------------------- OFFSET2 field of the ADDROFFSET register -------------------------------------------------------- */ /** Description of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_DESC "Offset to be added to address when reset counter RSTCNT2 expires" /** Offset of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_LSB 9UL /** Size in bits of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_W (9UL) /** Mask for retrieving the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_MASK ATON_FIELD_MASK(9UL, 9UL) /** Reset value of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_DT 0x0UL /** Access rights of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_AC "RW" /** Check whether access to the OFFSET2 field of the ADDROFFSET register is secured or not. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_S 0 /** Check whether access to the OFFSET2 field of the ADDROFFSET register is privileged or not. */ #define ATON_ARITH_ADDROFFSET_OFFSET2_P 0 /** Read the content of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_GET_OFFSET2(REG) ATON_GET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET2_LSB, ATON_ARITH_ADDROFFSET_OFFSET2_W) /** Modify the content of the OFFSET2 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_SET_OFFSET2(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET2_LSB, ATON_ARITH_ADDROFFSET_OFFSET2_W, DATA) /** * Get the description of the OFFSET2 field of ADDROFFSET register. * * \return the description of the OFFSET2 field of ADDROFFSET register */ static inline const int8_t *ATON_ARITH_ADDROFFSET_OFFSET2_GetdDesc(void) { return (const int8_t *)ATON_ARITH_ADDROFFSET_OFFSET2_DESC; } /** * Read the content of the OFFSET2 field of the ADDROFFSET register. * * \param[in] reg is the value of the ADDROFFSET register * * \return the content of the OFFSET2 field belonging to ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_Get_OFFSET2(uint32_t reg) { return ATON_ARITH_ADDROFFSET_GET_OFFSET2(reg); } /** * Write the content of the OFFSET2 field of the ADDROFFSET register. * * \param[in] reg is the value of the ADDROFFSET register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the OFFSET2 field belonging to ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_Set_OFFSET2(uint32_t reg, uint32_t data) { return ATON_ARITH_ADDROFFSET_SET_OFFSET2(reg, data); } /* -------------------------------------------------------- OFFSET3 field of the ADDROFFSET register -------------------------------------------------------- */ /** Description of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_DESC "Offset to be added to address when reset counter RSTCNT3 expires" /** Offset of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_LSB 18UL /** Size in bits of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_W (9UL) /** Mask for retrieving the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_MASK ATON_FIELD_MASK(18UL, 9UL) /** Reset value of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_DT 0x0UL /** Access rights of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_AC "RW" /** Check whether access to the OFFSET3 field of the ADDROFFSET register is secured or not. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_S 0 /** Check whether access to the OFFSET3 field of the ADDROFFSET register is privileged or not. */ #define ATON_ARITH_ADDROFFSET_OFFSET3_P 0 /** Read the content of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_GET_OFFSET3(REG) ATON_GET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET3_LSB, ATON_ARITH_ADDROFFSET_OFFSET3_W) /** Modify the content of the OFFSET3 field of the ADDROFFSET register. */ #define ATON_ARITH_ADDROFFSET_SET_OFFSET3(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_ADDROFFSET_OFFSET3_LSB, ATON_ARITH_ADDROFFSET_OFFSET3_W, DATA) /** * Get the description of the OFFSET3 field of ADDROFFSET register. * * \return the description of the OFFSET3 field of ADDROFFSET register */ static inline const int8_t *ATON_ARITH_ADDROFFSET_OFFSET3_GetdDesc(void) { return (const int8_t *)ATON_ARITH_ADDROFFSET_OFFSET3_DESC; } /** * Read the content of the OFFSET3 field of the ADDROFFSET register. * * \param[in] reg is the value of the ADDROFFSET register * * \return the content of the OFFSET3 field belonging to ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_Get_OFFSET3(uint32_t reg) { return ATON_ARITH_ADDROFFSET_GET_OFFSET3(reg); } /** * Write the content of the OFFSET3 field of the ADDROFFSET register. * * \param[in] reg is the value of the ADDROFFSET register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the OFFSET3 field belonging to ADDROFFSET register */ static inline uint32_t ATON_ARITH_ADDROFFSET_Set_OFFSET3(uint32_t reg, uint32_t data) { return ATON_ARITH_ADDROFFSET_SET_OFFSET3(reg, data); } /* ****************************************************** INCOFFSET register of one of the ARITH Units ****************************************************** */ /** Offset of the INCOFFSET register from the base address of the ARITH Unit. */ #define ATON_ARITH_INCOFFSET_OFFSET 0x28UL /** Reset value of the INCOFFSET register of the ARITH Unit. */ #define ATON_ARITH_INCOFFSET_DT \ (ATON_ARITH_INCOFFSET_VAL_DT << ATON_ARITH_INCOFFSET_VAL_LSB) /** Description of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_DESC "Address increment offset" /** Address of the INCOFFSET register of one of the ARITH Units. */ #define ATON_ARITH_INCOFFSET_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_INCOFFSET_OFFSET) /** Get the content of the INCOFFSET register of one of the ARITH Units. */ #define ATON_ARITH_INCOFFSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCOFFSET_ADDR(UNIT))) /** Set the content of the INCOFFSET register of one of the ARITH Units. */ #define ATON_ARITH_INCOFFSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_INCOFFSET_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INCOFFSET register. * * \return the description of INCOFFSET register */ static inline const int8_t *ATON_ARITH_INCOFFSET_GetDesc(void) { return (const int8_t *)ATON_ARITH_INCOFFSET_DESC; } /** * Get the offset of the INCOFFSET register. * * \return the offset of INCOFFSET register */ static inline uint32_t ATON_ARITH_INCOFFSET_GetOffset(void) { return ATON_ARITH_INCOFFSET_OFFSET; } /** * Get the address of the INCOFFSET register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCOFFSET register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of INCOFFSET register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_INCOFFSET_GetAddr(uint32_t instance) { return ATON_ARITH_INCOFFSET_ADDR(instance); } /** * Read the content of the INCOFFSET register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCOFFSET register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of INCOFFSET register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_INCOFFSET_Get(uint32_t instance) { return ATON_ARITH_INCOFFSET_GET(instance); } /** * Write the content of the INCOFFSET register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INCOFFSET register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_INCOFFSET_Set(uint32_t instance, uint32_t data) { ATON_ARITH_INCOFFSET_SET(instance, data); } /* ---------------------------------------------------------- VAL field of the INCOFFSET register ----------------------------------------------------------- */ /** Description of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_VAL_DESC "Offset to be added to address when increment counter INCCNT expires" /** Offset of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_VAL_LSB 0UL /** Size in bits of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_VAL_W (9UL) /** Mask for retrieving the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_VAL_MASK ATON_FIELD_MASK(0UL, 9UL) /** Reset value of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_VAL_DT 0x0UL /** Access rights of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_VAL_AC "RW" /** Check whether access to the VAL field of the INCOFFSET register is secured or not. */ #define ATON_ARITH_INCOFFSET_VAL_S 0 /** Check whether access to the VAL field of the INCOFFSET register is privileged or not. */ #define ATON_ARITH_INCOFFSET_VAL_P 0 /** Read the content of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_GET_VAL(REG) ATON_GET_FIELD(REG, ATON_ARITH_INCOFFSET_VAL_LSB, ATON_ARITH_INCOFFSET_VAL_W) /** Modify the content of the VAL field of the INCOFFSET register. */ #define ATON_ARITH_INCOFFSET_SET_VAL(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INCOFFSET_VAL_LSB, ATON_ARITH_INCOFFSET_VAL_W, DATA) /** * Get the description of the VAL field of INCOFFSET register. * * \return the description of the VAL field of INCOFFSET register */ static inline const int8_t *ATON_ARITH_INCOFFSET_VAL_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INCOFFSET_VAL_DESC; } /** * Read the content of the VAL field of the INCOFFSET register. * * \param[in] reg is the value of the INCOFFSET register * * \return the content of the VAL field belonging to INCOFFSET register */ static inline uint32_t ATON_ARITH_INCOFFSET_Get_VAL(uint32_t reg) { return ATON_ARITH_INCOFFSET_GET_VAL(reg); } /** * Write the content of the VAL field of the INCOFFSET register. * * \param[in] reg is the value of the INCOFFSET register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the VAL field belonging to INCOFFSET register */ static inline uint32_t ATON_ARITH_INCOFFSET_Set_VAL(uint32_t reg, uint32_t data) { return ATON_ARITH_INCOFFSET_SET_VAL(reg, data); } /* **************************************************** TRANSLATEADDR register of one of the ARITH Units **************************************************** */ /** Offset of the TRANSLATEADDR register from the base address of the ARITH Unit. */ #define ATON_ARITH_TRANSLATEADDR_OFFSET 0x2cUL /** Reset value of the TRANSLATEADDR register of the ARITH Unit. */ #define ATON_ARITH_TRANSLATEADDR_DT \ (ATON_ARITH_TRANSLATEADDR_EN_DT << ATON_ARITH_TRANSLATEADDR_EN_LSB) /** Description of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_DESC "Address translation control for memory" /** Address of the TRANSLATEADDR register of one of the ARITH Units. */ #define ATON_ARITH_TRANSLATEADDR_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_TRANSLATEADDR_OFFSET) /** Get the content of the TRANSLATEADDR register of one of the ARITH Units. */ #define ATON_ARITH_TRANSLATEADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_TRANSLATEADDR_ADDR(UNIT))) /** Set the content of the TRANSLATEADDR register of one of the ARITH Units. */ #define ATON_ARITH_TRANSLATEADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_TRANSLATEADDR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRANSLATEADDR register. * * \return the description of TRANSLATEADDR register */ static inline const int8_t *ATON_ARITH_TRANSLATEADDR_GetDesc(void) { return (const int8_t *)ATON_ARITH_TRANSLATEADDR_DESC; } /** * Get the offset of the TRANSLATEADDR register. * * \return the offset of TRANSLATEADDR register */ static inline uint32_t ATON_ARITH_TRANSLATEADDR_GetOffset(void) { return ATON_ARITH_TRANSLATEADDR_OFFSET; } /** * Get the address of the TRANSLATEADDR register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the TRANSLATEADDR register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of TRANSLATEADDR register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_TRANSLATEADDR_GetAddr(uint32_t instance) { return ATON_ARITH_TRANSLATEADDR_ADDR(instance); } /** * Read the content of the TRANSLATEADDR register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the TRANSLATEADDR register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of TRANSLATEADDR register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_TRANSLATEADDR_Get(uint32_t instance) { return ATON_ARITH_TRANSLATEADDR_GET(instance); } /** * Write the content of the TRANSLATEADDR register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the TRANSLATEADDR register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_TRANSLATEADDR_Set(uint32_t instance, uint32_t data) { ATON_ARITH_TRANSLATEADDR_SET(instance, data); } /* --------------------------------------------------------- EN field of the TRANSLATEADDR register --------------------------------------------------------- */ /** Description of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_EN_DESC "address translation control" /** Offset of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_EN_LSB 0UL /** Size in bits of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_EN_W (1UL) /** Mask for retrieving the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_EN_DT 0x0UL /** Access rights of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_EN_AC "RW" /** Check whether access to the EN field of the TRANSLATEADDR register is secured or not. */ #define ATON_ARITH_TRANSLATEADDR_EN_S 0 /** Check whether access to the EN field of the TRANSLATEADDR register is privileged or not. */ #define ATON_ARITH_TRANSLATEADDR_EN_P 0 /** Read the content of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_GET_EN(REG) ATON_GET_FIELD(REG, ATON_ARITH_TRANSLATEADDR_EN_LSB, ATON_ARITH_TRANSLATEADDR_EN_W) /** Modify the content of the EN field of the TRANSLATEADDR register. */ #define ATON_ARITH_TRANSLATEADDR_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_TRANSLATEADDR_EN_LSB, ATON_ARITH_TRANSLATEADDR_EN_W, DATA) /** * Get the description of the EN field of TRANSLATEADDR register. * * \return the description of the EN field of TRANSLATEADDR register */ static inline const int8_t *ATON_ARITH_TRANSLATEADDR_EN_GetdDesc(void) { return (const int8_t *)ATON_ARITH_TRANSLATEADDR_EN_DESC; } /** * Read the content of the EN field of the TRANSLATEADDR register. * * \param[in] reg is the value of the TRANSLATEADDR register * * \return the content of the EN field belonging to TRANSLATEADDR register */ static inline uint32_t ATON_ARITH_TRANSLATEADDR_Get_EN(uint32_t reg) { return ATON_ARITH_TRANSLATEADDR_GET_EN(reg); } /** * Write the content of the EN field of the TRANSLATEADDR register. * * \param[in] reg is the value of the TRANSLATEADDR register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRANSLATEADDR register */ static inline uint32_t ATON_ARITH_TRANSLATEADDR_Set_EN(uint32_t reg, uint32_t data) { return ATON_ARITH_TRANSLATEADDR_SET_EN(reg, data); } /* ****************************************************** COEFFADDR register of one of the ARITH Units ****************************************************** */ /** Offset of the COEFFADDR register from the base address of the ARITH Unit. */ #define ATON_ARITH_COEFFADDR_OFFSET 0x30UL /** Reset value of the COEFFADDR register of the ARITH Unit. */ #define ATON_ARITH_COEFFADDR_DT \ (ATON_ARITH_COEFFADDR_ADDR_DT << ATON_ARITH_COEFFADDR_ADDR_LSB) /** Description of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_DESC "Coeff Address" /** Address of the COEFFADDR register of one of the ARITH Units. */ #define ATON_ARITH_COEFFADDR_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFFADDR_OFFSET) /** Get the content of the COEFFADDR register of one of the ARITH Units. */ #define ATON_ARITH_COEFFADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFADDR_ADDR(UNIT))) /** Set the content of the COEFFADDR register of one of the ARITH Units. */ #define ATON_ARITH_COEFFADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_COEFFADDR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of COEFFADDR register. * * \return the description of COEFFADDR register */ static inline const int8_t *ATON_ARITH_COEFFADDR_GetDesc(void) { return (const int8_t *)ATON_ARITH_COEFFADDR_DESC; } /** * Get the offset of the COEFFADDR register. * * \return the offset of COEFFADDR register */ static inline uint32_t ATON_ARITH_COEFFADDR_GetOffset(void) { return ATON_ARITH_COEFFADDR_OFFSET; } /** * Get the address of the COEFFADDR register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFADDR register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of COEFFADDR register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_COEFFADDR_GetAddr(uint32_t instance) { return ATON_ARITH_COEFFADDR_ADDR(instance); } /** * Read the content of the COEFFADDR register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFADDR register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of COEFFADDR register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_COEFFADDR_Get(uint32_t instance) { return ATON_ARITH_COEFFADDR_GET(instance); } /** * Write the content of the COEFFADDR register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the COEFFADDR register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_COEFFADDR_Set(uint32_t instance, uint32_t data) { ATON_ARITH_COEFFADDR_SET(instance, data); } /* ---------------------------------------------------------- ADDR field of the COEFFADDR register ---------------------------------------------------------- */ /** Description of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_ADDR_DESC "Writing will set the start address of coeff memory. Reading this register will return the current address in use in the datapath, ie. the address of the coeffs to be read next. The address will take effect only after the block has been enabled and a valid stream is input. Subsequent updates to this register will take effect only after the clear bit has been set in the control register" /** Offset of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_ADDR_LSB 0UL /** Size in bits of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_ADDR_W (9UL) /** Mask for retrieving the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_ADDR_MASK ATON_FIELD_MASK(0UL, 9UL) /** Reset value of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_ADDR_DT 0x0UL /** Access rights of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_ADDR_AC "RW" /** Check whether access to the ADDR field of the COEFFADDR register is secured or not. */ #define ATON_ARITH_COEFFADDR_ADDR_S 0 /** Check whether access to the ADDR field of the COEFFADDR register is privileged or not. */ #define ATON_ARITH_COEFFADDR_ADDR_P 0 /** Read the content of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_GET_ADDR(REG) ATON_GET_FIELD(REG, ATON_ARITH_COEFFADDR_ADDR_LSB, ATON_ARITH_COEFFADDR_ADDR_W) /** Modify the content of the ADDR field of the COEFFADDR register. */ #define ATON_ARITH_COEFFADDR_SET_ADDR(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_COEFFADDR_ADDR_LSB, ATON_ARITH_COEFFADDR_ADDR_W, DATA) /** * Get the description of the ADDR field of COEFFADDR register. * * \return the description of the ADDR field of COEFFADDR register */ static inline const int8_t *ATON_ARITH_COEFFADDR_ADDR_GetdDesc(void) { return (const int8_t *)ATON_ARITH_COEFFADDR_ADDR_DESC; } /** * Read the content of the ADDR field of the COEFFADDR register. * * \param[in] reg is the value of the COEFFADDR register * * \return the content of the ADDR field belonging to COEFFADDR register */ static inline uint32_t ATON_ARITH_COEFFADDR_Get_ADDR(uint32_t reg) { return ATON_ARITH_COEFFADDR_GET_ADDR(reg); } /** * Write the content of the ADDR field of the COEFFADDR register. * * \param[in] reg is the value of the COEFFADDR register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the ADDR field belonging to COEFFADDR register */ static inline uint32_t ATON_ARITH_COEFFADDR_Set_ADDR(uint32_t reg, uint32_t data) { return ATON_ARITH_COEFFADDR_SET_ADDR(reg, data); } /* ****************************************************** INSHIFTER register of one of the ARITH Units ****************************************************** */ /** Offset of the INSHIFTER register from the base address of the ARITH Unit. */ #define ATON_ARITH_INSHIFTER_OFFSET 0x34UL /** Reset value of the INSHIFTER register of the ARITH Unit. */ #define ATON_ARITH_INSHIFTER_DT \ (ATON_ARITH_INSHIFTER_FBYTESX_DT << ATON_ARITH_INSHIFTER_FBYTESX_LSB) | \ (ATON_ARITH_INSHIFTER_FSHIFTX_DT << ATON_ARITH_INSHIFTER_FSHIFTX_LSB) | \ (ATON_ARITH_INSHIFTER_FROUNDX_DT << ATON_ARITH_INSHIFTER_FROUNDX_LSB) | \ (ATON_ARITH_INSHIFTER_FSATX_DT << ATON_ARITH_INSHIFTER_FSATX_LSB) | \ (ATON_ARITH_INSHIFTER_FRNDMODEX_DT << ATON_ARITH_INSHIFTER_FRNDMODEX_LSB) | \ (ATON_ARITH_INSHIFTER_FOBYTESX_DT << ATON_ARITH_INSHIFTER_FOBYTESX_LSB) | \ (ATON_ARITH_INSHIFTER_FBYTESY_DT << ATON_ARITH_INSHIFTER_FBYTESY_LSB) | \ (ATON_ARITH_INSHIFTER_FSHIFTY_DT << ATON_ARITH_INSHIFTER_FSHIFTY_LSB) | \ (ATON_ARITH_INSHIFTER_FROUNDY_DT << ATON_ARITH_INSHIFTER_FROUNDY_LSB) | \ (ATON_ARITH_INSHIFTER_FSATY_DT << ATON_ARITH_INSHIFTER_FSATY_LSB) | \ (ATON_ARITH_INSHIFTER_FRNDMODEY_DT << ATON_ARITH_INSHIFTER_FRNDMODEY_LSB) | \ (ATON_ARITH_INSHIFTER_FOBYTESY_DT << ATON_ARITH_INSHIFTER_FOBYTESY_LSB) /** Description of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_DESC "input shifter configuration" /** Address of the INSHIFTER register of one of the ARITH Units. */ #define ATON_ARITH_INSHIFTER_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_INSHIFTER_OFFSET) /** Get the content of the INSHIFTER register of one of the ARITH Units. */ #define ATON_ARITH_INSHIFTER_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_INSHIFTER_ADDR(UNIT))) /** Set the content of the INSHIFTER register of one of the ARITH Units. */ #define ATON_ARITH_INSHIFTER_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_INSHIFTER_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of INSHIFTER register. * * \return the description of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_GetDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_DESC; } /** * Get the offset of the INSHIFTER register. * * \return the offset of INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_GetOffset(void) { return ATON_ARITH_INSHIFTER_OFFSET; } /** * Get the address of the INSHIFTER register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INSHIFTER register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of INSHIFTER register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_INSHIFTER_GetAddr(uint32_t instance) { return ATON_ARITH_INSHIFTER_ADDR(instance); } /** * Read the content of the INSHIFTER register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INSHIFTER register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of INSHIFTER register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_INSHIFTER_Get(uint32_t instance) { return ATON_ARITH_INSHIFTER_GET(instance); } /** * Write the content of the INSHIFTER register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the INSHIFTER register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_INSHIFTER_Set(uint32_t instance, uint32_t data) { ATON_ARITH_INSHIFTER_SET(instance, data); } /* -------------------------------------------------------- FBYTESX field of the INSHIFTER register --------------------------------------------------------- */ /** Description of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESX_DESC "Input data width in bytes for stream X. Valid values are 1,2 or 3 bytes" /** Offset of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESX_LSB 0UL /** Size in bits of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESX_W (2UL) /** Mask for retrieving the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESX_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESX_DT 0x2UL /** Access rights of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESX_AC "RW" /** Check whether access to the FBYTESX field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FBYTESX_S 0 /** Check whether access to the FBYTESX field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FBYTESX_P 0 /** Read the content of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FBYTESX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESX_LSB, ATON_ARITH_INSHIFTER_FBYTESX_W) /** Modify the content of the FBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FBYTESX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESX_LSB, ATON_ARITH_INSHIFTER_FBYTESX_W, DATA) /** * Get the description of the FBYTESX field of INSHIFTER register. * * \return the description of the FBYTESX field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FBYTESX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FBYTESX_DESC; } /** * Read the content of the FBYTESX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FBYTESX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FBYTESX(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FBYTESX(reg); } /** * Write the content of the FBYTESX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FBYTESX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FBYTESX(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FBYTESX(reg, data); } /* -------------------------------------------------------- FSHIFTX field of the INSHIFTER register --------------------------------------------------------- */ /** Description of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_DESC "Input feature data shift for stream X. Range [0-40]. For no shift, set to 16" /** Offset of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_LSB 2UL /** Size in bits of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_W (6UL) /** Mask for retrieving the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_MASK ATON_FIELD_MASK(2UL, 6UL) /** Reset value of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_DT 0x10UL /** Access rights of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_AC "RW" /** Check whether access to the FSHIFTX field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_S 0 /** Check whether access to the FSHIFTX field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FSHIFTX_P 0 /** Read the content of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FSHIFTX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTX_LSB, ATON_ARITH_INSHIFTER_FSHIFTX_W) /** Modify the content of the FSHIFTX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FSHIFTX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTX_LSB, ATON_ARITH_INSHIFTER_FSHIFTX_W, DATA) /** * Get the description of the FSHIFTX field of INSHIFTER register. * * \return the description of the FSHIFTX field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FSHIFTX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FSHIFTX_DESC; } /** * Read the content of the FSHIFTX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FSHIFTX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSHIFTX(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FSHIFTX(reg); } /** * Write the content of the FSHIFTX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the FSHIFTX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSHIFTX(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FSHIFTX(reg, data); } /* -------------------------------------------------------- FROUNDX field of the INSHIFTER register --------------------------------------------------------- */ /** Description of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDX_DESC "Input feature data rounding for stream X" /** Offset of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDX_LSB 8UL /** Size in bits of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDX_W (1UL) /** Mask for retrieving the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDX_MASK ATON_FIELD_MASK(8UL, 1UL) /** Reset value of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDX_DT 0x0UL /** Access rights of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDX_AC "RW" /** Check whether access to the FROUNDX field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FROUNDX_S 0 /** Check whether access to the FROUNDX field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FROUNDX_P 0 /** Read the content of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FROUNDX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDX_LSB, ATON_ARITH_INSHIFTER_FROUNDX_W) /** Modify the content of the FROUNDX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FROUNDX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDX_LSB, ATON_ARITH_INSHIFTER_FROUNDX_W, DATA) /** * Get the description of the FROUNDX field of INSHIFTER register. * * \return the description of the FROUNDX field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FROUNDX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FROUNDX_DESC; } /** * Read the content of the FROUNDX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FROUNDX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FROUNDX(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FROUNDX(reg); } /** * Write the content of the FROUNDX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FROUNDX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FROUNDX(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FROUNDX(reg, data); } /* --------------------------------------------------------- FSATX field of the INSHIFTER register ---------------------------------------------------------- */ /** Description of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATX_DESC "Input feature data saturation for stream X" /** Offset of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATX_LSB 9UL /** Size in bits of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATX_W (1UL) /** Mask for retrieving the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATX_MASK ATON_FIELD_MASK(9UL, 1UL) /** Reset value of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATX_DT 0x0UL /** Access rights of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATX_AC "RW" /** Check whether access to the FSATX field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FSATX_S 0 /** Check whether access to the FSATX field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FSATX_P 0 /** Read the content of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FSATX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATX_LSB, ATON_ARITH_INSHIFTER_FSATX_W) /** Modify the content of the FSATX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FSATX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATX_LSB, ATON_ARITH_INSHIFTER_FSATX_W, DATA) /** * Get the description of the FSATX field of INSHIFTER register. * * \return the description of the FSATX field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FSATX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FSATX_DESC; } /** * Read the content of the FSATX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FSATX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSATX(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FSATX(reg); } /** * Write the content of the FSATX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSATX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSATX(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FSATX(reg, data); } /* ------------------------------------------------------- FRNDMODEX field of the INSHIFTER register -------------------------------------------------------- */ /** Description of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_DESC "Input feature data rounding mode for stream X. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_LSB 10UL /** Size in bits of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_W (2UL) /** Mask for retrieving the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_MASK ATON_FIELD_MASK(10UL, 2UL) /** Reset value of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_DT 0x0UL /** Access rights of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_AC "RW" /** Check whether access to the FRNDMODEX field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_S 0 /** Check whether access to the FRNDMODEX field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FRNDMODEX_P 0 /** Read the content of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FRNDMODEX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEX_LSB, ATON_ARITH_INSHIFTER_FRNDMODEX_W) /** Modify the content of the FRNDMODEX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FRNDMODEX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEX_LSB, ATON_ARITH_INSHIFTER_FRNDMODEX_W, DATA) /** * Get the description of the FRNDMODEX field of INSHIFTER register. * * \return the description of the FRNDMODEX field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FRNDMODEX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FRNDMODEX_DESC; } /** * Read the content of the FRNDMODEX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FRNDMODEX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FRNDMODEX(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FRNDMODEX(reg); } /** * Write the content of the FRNDMODEX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FRNDMODEX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FRNDMODEX(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FRNDMODEX(reg, data); } /* -------------------------------------------------------- FOBYTESX field of the INSHIFTER register -------------------------------------------------------- */ /** Description of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_DESC "Number of output bytes to use for input feature data of stream X after rounding or saturation. Valid values are 1 or 2 bytes" /** Offset of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_LSB 12UL /** Size in bits of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_W (2UL) /** Mask for retrieving the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_MASK ATON_FIELD_MASK(12UL, 2UL) /** Reset value of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_DT 0x2UL /** Access rights of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_AC "RW" /** Check whether access to the FOBYTESX field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_S 0 /** Check whether access to the FOBYTESX field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FOBYTESX_P 0 /** Read the content of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FOBYTESX(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESX_LSB, ATON_ARITH_INSHIFTER_FOBYTESX_W) /** Modify the content of the FOBYTESX field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FOBYTESX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESX_LSB, ATON_ARITH_INSHIFTER_FOBYTESX_W, DATA) /** * Get the description of the FOBYTESX field of INSHIFTER register. * * \return the description of the FOBYTESX field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FOBYTESX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FOBYTESX_DESC; } /** * Read the content of the FOBYTESX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FOBYTESX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FOBYTESX(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FOBYTESX(reg); } /** * Write the content of the FOBYTESX field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FOBYTESX field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FOBYTESX(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FOBYTESX(reg, data); } /* -------------------------------------------------------- FBYTESY field of the INSHIFTER register --------------------------------------------------------- */ /** Description of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESY_DESC "Input data width in bytes for stream Y. Valid values are 1,2 or 3 bytes" /** Offset of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESY_LSB 16UL /** Size in bits of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESY_W (2UL) /** Mask for retrieving the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESY_MASK ATON_FIELD_MASK(16UL, 2UL) /** Reset value of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESY_DT 0x2UL /** Access rights of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FBYTESY_AC "RW" /** Check whether access to the FBYTESY field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FBYTESY_S 0 /** Check whether access to the FBYTESY field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FBYTESY_P 0 /** Read the content of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FBYTESY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESY_LSB, ATON_ARITH_INSHIFTER_FBYTESY_W) /** Modify the content of the FBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FBYTESY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FBYTESY_LSB, ATON_ARITH_INSHIFTER_FBYTESY_W, DATA) /** * Get the description of the FBYTESY field of INSHIFTER register. * * \return the description of the FBYTESY field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FBYTESY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FBYTESY_DESC; } /** * Read the content of the FBYTESY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FBYTESY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FBYTESY(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FBYTESY(reg); } /** * Write the content of the FBYTESY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FBYTESY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FBYTESY(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FBYTESY(reg, data); } /* -------------------------------------------------------- FSHIFTY field of the INSHIFTER register --------------------------------------------------------- */ /** Description of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_DESC "Input feature data shift for stream Y. Range [0-40]. For no shift, set to 16" /** Offset of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_LSB 18UL /** Size in bits of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_W (6UL) /** Mask for retrieving the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_MASK ATON_FIELD_MASK(18UL, 6UL) /** Reset value of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_DT 0x10UL /** Access rights of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_AC "RW" /** Check whether access to the FSHIFTY field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_S 0 /** Check whether access to the FSHIFTY field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FSHIFTY_P 0 /** Read the content of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FSHIFTY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTY_LSB, ATON_ARITH_INSHIFTER_FSHIFTY_W) /** Modify the content of the FSHIFTY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FSHIFTY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSHIFTY_LSB, ATON_ARITH_INSHIFTER_FSHIFTY_W, DATA) /** * Get the description of the FSHIFTY field of INSHIFTER register. * * \return the description of the FSHIFTY field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FSHIFTY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FSHIFTY_DESC; } /** * Read the content of the FSHIFTY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FSHIFTY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSHIFTY(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FSHIFTY(reg); } /** * Write the content of the FSHIFTY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the FSHIFTY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSHIFTY(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FSHIFTY(reg, data); } /* -------------------------------------------------------- FROUNDY field of the INSHIFTER register --------------------------------------------------------- */ /** Description of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDY_DESC "Input feature data rounding for stream Y" /** Offset of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDY_LSB 24UL /** Size in bits of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDY_W (1UL) /** Mask for retrieving the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDY_MASK ATON_FIELD_MASK(24UL, 1UL) /** Reset value of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDY_DT 0x0UL /** Access rights of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FROUNDY_AC "RW" /** Check whether access to the FROUNDY field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FROUNDY_S 0 /** Check whether access to the FROUNDY field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FROUNDY_P 0 /** Read the content of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FROUNDY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDY_LSB, ATON_ARITH_INSHIFTER_FROUNDY_W) /** Modify the content of the FROUNDY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FROUNDY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FROUNDY_LSB, ATON_ARITH_INSHIFTER_FROUNDY_W, DATA) /** * Get the description of the FROUNDY field of INSHIFTER register. * * \return the description of the FROUNDY field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FROUNDY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FROUNDY_DESC; } /** * Read the content of the FROUNDY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FROUNDY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FROUNDY(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FROUNDY(reg); } /** * Write the content of the FROUNDY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FROUNDY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FROUNDY(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FROUNDY(reg, data); } /* --------------------------------------------------------- FSATY field of the INSHIFTER register ---------------------------------------------------------- */ /** Description of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATY_DESC "Input feature data saturation for stream Y" /** Offset of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATY_LSB 25UL /** Size in bits of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATY_W (1UL) /** Mask for retrieving the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATY_MASK ATON_FIELD_MASK(25UL, 1UL) /** Reset value of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATY_DT 0x0UL /** Access rights of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FSATY_AC "RW" /** Check whether access to the FSATY field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FSATY_S 0 /** Check whether access to the FSATY field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FSATY_P 0 /** Read the content of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FSATY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATY_LSB, ATON_ARITH_INSHIFTER_FSATY_W) /** Modify the content of the FSATY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FSATY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FSATY_LSB, ATON_ARITH_INSHIFTER_FSATY_W, DATA) /** * Get the description of the FSATY field of INSHIFTER register. * * \return the description of the FSATY field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FSATY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FSATY_DESC; } /** * Read the content of the FSATY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FSATY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FSATY(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FSATY(reg); } /** * Write the content of the FSATY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSATY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FSATY(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FSATY(reg, data); } /* ------------------------------------------------------- FRNDMODEY field of the INSHIFTER register -------------------------------------------------------- */ /** Description of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_DESC "Input feature data rounding mode for stream Y. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_LSB 26UL /** Size in bits of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_W (2UL) /** Mask for retrieving the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_MASK ATON_FIELD_MASK(26UL, 2UL) /** Reset value of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_DT 0x0UL /** Access rights of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_AC "RW" /** Check whether access to the FRNDMODEY field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_S 0 /** Check whether access to the FRNDMODEY field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FRNDMODEY_P 0 /** Read the content of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FRNDMODEY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEY_LSB, ATON_ARITH_INSHIFTER_FRNDMODEY_W) /** Modify the content of the FRNDMODEY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FRNDMODEY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FRNDMODEY_LSB, ATON_ARITH_INSHIFTER_FRNDMODEY_W, DATA) /** * Get the description of the FRNDMODEY field of INSHIFTER register. * * \return the description of the FRNDMODEY field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FRNDMODEY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FRNDMODEY_DESC; } /** * Read the content of the FRNDMODEY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FRNDMODEY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FRNDMODEY(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FRNDMODEY(reg); } /** * Write the content of the FRNDMODEY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FRNDMODEY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FRNDMODEY(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FRNDMODEY(reg, data); } /* -------------------------------------------------------- FOBYTESY field of the INSHIFTER register -------------------------------------------------------- */ /** Description of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_DESC "Number of output bytes to use for input feature data of stream Y after rounding or saturation. Valid values are 1 or 2 bytes" /** Offset of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_LSB 28UL /** Size in bits of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_W (2UL) /** Mask for retrieving the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_MASK ATON_FIELD_MASK(28UL, 2UL) /** Reset value of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_DT 0x2UL /** Access rights of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_AC "RW" /** Check whether access to the FOBYTESY field of the INSHIFTER register is secured or not. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_S 0 /** Check whether access to the FOBYTESY field of the INSHIFTER register is privileged or not. */ #define ATON_ARITH_INSHIFTER_FOBYTESY_P 0 /** Read the content of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_GET_FOBYTESY(REG) ATON_GET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESY_LSB, ATON_ARITH_INSHIFTER_FOBYTESY_W) /** Modify the content of the FOBYTESY field of the INSHIFTER register. */ #define ATON_ARITH_INSHIFTER_SET_FOBYTESY(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_INSHIFTER_FOBYTESY_LSB, ATON_ARITH_INSHIFTER_FOBYTESY_W, DATA) /** * Get the description of the FOBYTESY field of INSHIFTER register. * * \return the description of the FOBYTESY field of INSHIFTER register */ static inline const int8_t *ATON_ARITH_INSHIFTER_FOBYTESY_GetdDesc(void) { return (const int8_t *)ATON_ARITH_INSHIFTER_FOBYTESY_DESC; } /** * Read the content of the FOBYTESY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * * \return the content of the FOBYTESY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Get_FOBYTESY(uint32_t reg) { return ATON_ARITH_INSHIFTER_GET_FOBYTESY(reg); } /** * Write the content of the FOBYTESY field of the INSHIFTER register. * * \param[in] reg is the value of the INSHIFTER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FOBYTESY field belonging to INSHIFTER register */ static inline uint32_t ATON_ARITH_INSHIFTER_Set_FOBYTESY(uint32_t reg, uint32_t data) { return ATON_ARITH_INSHIFTER_SET_FOBYTESY(reg, data); } /* ****************************************************** CLIPRANGE register of one of the ARITH Units ****************************************************** */ /** Offset of the CLIPRANGE register from the base address of the ARITH Unit. */ #define ATON_ARITH_CLIPRANGE_OFFSET 0x38UL /** Reset value of the CLIPRANGE register of the ARITH Unit. */ #define ATON_ARITH_CLIPRANGE_DT \ (ATON_ARITH_CLIPRANGE_CLIPMAX_DT << ATON_ARITH_CLIPRANGE_CLIPMAX_LSB) | \ (ATON_ARITH_CLIPRANGE_CLIPMIN_DT << ATON_ARITH_CLIPRANGE_CLIPMIN_LSB) /** Description of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_DESC "Output clip range [min,max]" /** Address of the CLIPRANGE register of one of the ARITH Units. */ #define ATON_ARITH_CLIPRANGE_ADDR(UNIT) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_CLIPRANGE_OFFSET) /** Get the content of the CLIPRANGE register of one of the ARITH Units. */ #define ATON_ARITH_CLIPRANGE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_ARITH_CLIPRANGE_ADDR(UNIT))) /** Set the content of the CLIPRANGE register of one of the ARITH Units. */ #define ATON_ARITH_CLIPRANGE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_ARITH_CLIPRANGE_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CLIPRANGE register. * * \return the description of CLIPRANGE register */ static inline const int8_t *ATON_ARITH_CLIPRANGE_GetDesc(void) { return (const int8_t *)ATON_ARITH_CLIPRANGE_DESC; } /** * Get the offset of the CLIPRANGE register. * * \return the offset of CLIPRANGE register */ static inline uint32_t ATON_ARITH_CLIPRANGE_GetOffset(void) { return ATON_ARITH_CLIPRANGE_OFFSET; } /** * Get the address of the CLIPRANGE register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CLIPRANGE register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of CLIPRANGE register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_CLIPRANGE_GetAddr(uint32_t instance) { return ATON_ARITH_CLIPRANGE_ADDR(instance); } /** * Read the content of the CLIPRANGE register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CLIPRANGE register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of CLIPRANGE register belonging to Unit having index \e instance among the ARITH Units */ static inline uint32_t ATON_ARITH_CLIPRANGE_Get(uint32_t instance) { return ATON_ARITH_CLIPRANGE_GET(instance); } /** * Write the content of the CLIPRANGE register. * * \param[in] instance is the index of the Unit (among the ARITH Units) containing the CLIPRANGE register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_ARITH_CLIPRANGE_Set(uint32_t instance, uint32_t data) { ATON_ARITH_CLIPRANGE_SET(instance, data); } /* -------------------------------------------------------- CLIPMAX field of the CLIPRANGE register --------------------------------------------------------- */ /** Description of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_DESC "signed 16b value specifying output clip max" /** Offset of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_LSB 0UL /** Size in bits of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_W (16UL) /** Mask for retrieving the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_DT 0x0UL /** Access rights of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_AC "RW" /** Check whether access to the CLIPMAX field of the CLIPRANGE register is secured or not. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_S 0 /** Check whether access to the CLIPMAX field of the CLIPRANGE register is privileged or not. */ #define ATON_ARITH_CLIPRANGE_CLIPMAX_P 0 /** Read the content of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_GET_CLIPMAX(REG) ATON_GET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMAX_LSB, ATON_ARITH_CLIPRANGE_CLIPMAX_W) /** Modify the content of the CLIPMAX field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_SET_CLIPMAX(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMAX_LSB, ATON_ARITH_CLIPRANGE_CLIPMAX_W, DATA) /** * Get the description of the CLIPMAX field of CLIPRANGE register. * * \return the description of the CLIPMAX field of CLIPRANGE register */ static inline const int8_t *ATON_ARITH_CLIPRANGE_CLIPMAX_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CLIPRANGE_CLIPMAX_DESC; } /** * Read the content of the CLIPMAX field of the CLIPRANGE register. * * \param[in] reg is the value of the CLIPRANGE register * * \return the content of the CLIPMAX field belonging to CLIPRANGE register */ static inline uint32_t ATON_ARITH_CLIPRANGE_Get_CLIPMAX(uint32_t reg) { return ATON_ARITH_CLIPRANGE_GET_CLIPMAX(reg); } /** * Write the content of the CLIPMAX field of the CLIPRANGE register. * * \param[in] reg is the value of the CLIPRANGE register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the CLIPMAX field belonging to CLIPRANGE register */ static inline uint32_t ATON_ARITH_CLIPRANGE_Set_CLIPMAX(uint32_t reg, uint32_t data) { return ATON_ARITH_CLIPRANGE_SET_CLIPMAX(reg, data); } /* -------------------------------------------------------- CLIPMIN field of the CLIPRANGE register --------------------------------------------------------- */ /** Description of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_DESC "signed 16b value specifying output clip min" /** Offset of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_LSB 16UL /** Size in bits of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_W (16UL) /** Mask for retrieving the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_DT 0x0UL /** Access rights of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_AC "RW" /** Check whether access to the CLIPMIN field of the CLIPRANGE register is secured or not. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_S 0 /** Check whether access to the CLIPMIN field of the CLIPRANGE register is privileged or not. */ #define ATON_ARITH_CLIPRANGE_CLIPMIN_P 0 /** Read the content of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_GET_CLIPMIN(REG) ATON_GET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMIN_LSB, ATON_ARITH_CLIPRANGE_CLIPMIN_W) /** Modify the content of the CLIPMIN field of the CLIPRANGE register. */ #define ATON_ARITH_CLIPRANGE_SET_CLIPMIN(REG, DATA) ATON_SET_FIELD(REG, ATON_ARITH_CLIPRANGE_CLIPMIN_LSB, ATON_ARITH_CLIPRANGE_CLIPMIN_W, DATA) /** * Get the description of the CLIPMIN field of CLIPRANGE register. * * \return the description of the CLIPMIN field of CLIPRANGE register */ static inline const int8_t *ATON_ARITH_CLIPRANGE_CLIPMIN_GetdDesc(void) { return (const int8_t *)ATON_ARITH_CLIPRANGE_CLIPMIN_DESC; } /** * Read the content of the CLIPMIN field of the CLIPRANGE register. * * \param[in] reg is the value of the CLIPRANGE register * * \return the content of the CLIPMIN field belonging to CLIPRANGE register */ static inline uint32_t ATON_ARITH_CLIPRANGE_Get_CLIPMIN(uint32_t reg) { return ATON_ARITH_CLIPRANGE_GET_CLIPMIN(reg); } /** * Write the content of the CLIPMIN field of the CLIPRANGE register. * * \param[in] reg is the value of the CLIPRANGE register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the CLIPMIN field belonging to CLIPRANGE register */ static inline uint32_t ATON_ARITH_CLIPRANGE_Set_CLIPMIN(uint32_t reg, uint32_t data) { return ATON_ARITH_CLIPRANGE_SET_CLIPMIN(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* POOL Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of POOL Unit instances. */ #define ATON_POOL_NUM 2 /** * \name Structures, macros and functions of the POOL Units */ /*@{*/ /** * Registers of the POOL Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e PDIMS register (Pool dimensions). */ uint32_t PDIMS; /** \e FDIMS register (Feature dimensions). */ uint32_t FDIMS; /** \e OUTDIMS register (Output feature dimensions). */ uint32_t OUTDIMS; /** \e MULVAL register (average pooling data). */ uint32_t MULVAL; /** \e XCROP register (left/right cropping dimensions). */ uint32_t XCROP; /** \e YCROP register (top/bottom cropping dimensions). */ uint32_t YCROP; /** \e RNDCTRL register (input and output rounding control). */ uint32_t RNDCTRL; } ATON_POOL_t; /** Return the pointer to one of the POOL Units. */ #define ATON_POOL(UNIT) ((ATON_POOL_t *)(intptr_t)ATON_POOL_BASE(UNIT)) /** Name of one of the POOL Units. */ #define ATON_POOL_NAME(UNIT) \ (((UNIT) == 0) ? "POOL0" : \ (((UNIT) == 1) ? "POOL1" : "")) /** Version of the POOL Units. */ #define ATON_POOL_VERSION "1.1" /** Description of one of the POOL Units. */ #define ATON_POOL_DESC(UNIT) \ (((UNIT) == 0) ? "Pooling Accelerator 0" : \ (((UNIT) == 1) ? "Pooling Accelerator 1" : "")) /** Base address of one of the POOL Units. */ #define ATON_POOL_BASE(UNIT) \ (ATON_BASE + 0x1b000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the POOL Units. */ #define ATON_POOL_SIZE 0x1000UL /** * Get the name of one of the POOL Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) * * \return the name of Unit having index \e instance among the POOL Units */ static inline const int8_t *ATON_POOL_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"POOL0"; break; case 1: str = (const int8_t *)"POOL1"; break; default: break; } return str; } /** * Get the description of one of the POOL Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) * * \return the description of Unit having index \e instance among the POOL Units */ static inline const int8_t *ATON_POOL_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Pooling Accelerator 0"; break; case 1: str = (const int8_t *)"Pooling Accelerator 1"; break; default: break; } return str; } /** * Get the version of the POOL Units. * * \return the version of the POOL Units */ static inline const int8_t *ATON_POOL_GetVersion(void) { return (const int8_t *)ATON_POOL_VERSION; } /** * Get the base address of one of the POOL Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) * * \return the base address of Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_GetBase(uint32_t instance) { return ATON_POOL_BASE(instance); } /** * Get the size in bytes of the POOL Units. * * \return the size in bytes of the POOL Units */ static inline uint32_t ATON_POOL_GetSize(void) { return ATON_POOL_SIZE; } /* ********************************************************* CTRL register of one of the POOL Units ********************************************************* */ /** Offset of the CTRL register from the base address of the POOL Unit. */ #define ATON_POOL_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the POOL Unit. */ #define ATON_POOL_CTRL_DT \ (ATON_POOL_CTRL_EN_DT << ATON_POOL_CTRL_EN_LSB) | \ (ATON_POOL_CTRL_CLR_DT << ATON_POOL_CTRL_CLR_LSB) | \ (ATON_POOL_CTRL_TYPE_DT << ATON_POOL_CTRL_TYPE_LSB) | \ (ATON_POOL_CTRL_ROUND_DT << ATON_POOL_CTRL_ROUND_LSB) | \ (ATON_POOL_CTRL_SAT_DT << ATON_POOL_CTRL_SAT_LSB) | \ (ATON_POOL_CTRL_OUTSHIFT_DT << ATON_POOL_CTRL_OUTSHIFT_LSB) | \ (ATON_POOL_CTRL_DUALLINE_DT << ATON_POOL_CTRL_DUALLINE_LSB) | \ (ATON_POOL_CTRL_CROPEN_DT << ATON_POOL_CTRL_CROPEN_LSB) | \ (ATON_POOL_CTRL_FBYTES_DT << ATON_POOL_CTRL_FBYTES_LSB) | \ (ATON_POOL_CTRL_FSHIFT_DT << ATON_POOL_CTRL_FSHIFT_LSB) | \ (ATON_POOL_CTRL_FROUND_DT << ATON_POOL_CTRL_FROUND_LSB) | \ (ATON_POOL_CTRL_FSAT_DT << ATON_POOL_CTRL_FSAT_LSB) | \ (ATON_POOL_CTRL_CONFCLR_DT << ATON_POOL_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_POOL_CTRL_DESC "Control register" /** Address of the CTRL register of one of the POOL Units. */ #define ATON_POOL_CTRL_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_CTRL_OFFSET) /** Get the content of the CTRL register of one of the POOL Units. */ #define ATON_POOL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the POOL Units. */ #define ATON_POOL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_GetDesc(void) { return (const int8_t *)ATON_POOL_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_POOL_CTRL_GetOffset(void) { return ATON_POOL_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the CTRL register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_CTRL_GetAddr(uint32_t instance) { return ATON_POOL_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_CTRL_Get(uint32_t instance) { return ATON_POOL_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the CTRL register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_CTRL_Set(uint32_t instance, uint32_t data) { ATON_POOL_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_EN_DESC "Enable the Pooling Accelerator" /** Offset of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_POOL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_EN_LSB, ATON_POOL_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_POOL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_EN_LSB, ATON_POOL_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_EN(uint32_t reg) { return ATON_POOL_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_CLR_LSB, ATON_POOL_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_POOL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_CLR_LSB, ATON_POOL_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_CLR(uint32_t reg) { return ATON_POOL_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_CLR(reg, data); } /* ------------------------------------------------------------ TYPE field of the CTRL register ------------------------------------------------------------- */ /** Description of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_TYPE_DESC "Pool operation type" /** Offset of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_TYPE_LSB 2UL /** Size in bits of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_TYPE_W (4UL) /** Mask for retrieving the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_TYPE_MASK ATON_FIELD_MASK(2UL, 4UL) /** Reset value of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_TYPE_DT 0x0UL /** Access rights of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_TYPE_AC "RW" /** Check whether access to the TYPE field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_TYPE_S 0 /** Check whether access to the TYPE field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_TYPE_P 0 /** Read the content of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_TYPE_LSB, ATON_POOL_CTRL_TYPE_W) /** Modify the content of the TYPE field of the CTRL register. */ #define ATON_POOL_CTRL_SET_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_TYPE_LSB, ATON_POOL_CTRL_TYPE_W, DATA) /** * Get the description of the TYPE field of CTRL register. * * \return the description of the TYPE field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_TYPE_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_TYPE_DESC; } /** * Read the content of the TYPE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the TYPE field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_TYPE(uint32_t reg) { return ATON_POOL_CTRL_GET_TYPE(reg); } /** * Write the content of the TYPE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the TYPE field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_TYPE(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_TYPE(reg, data); } /* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ /** Description of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_ROUND_DESC "Enable output rounding using round-to-nearest (round up) (applicable to average pooling operations)" /** Offset of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_ROUND_LSB 6UL /** Size in bits of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_ROUND_W (1UL) /** Mask for retrieving the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_ROUND_MASK ATON_FIELD_MASK(6UL, 1UL) /** Reset value of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_ROUND_DT 0x0UL /** Access rights of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_ROUND_AC "RW" /** Check whether access to the ROUND field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_ROUND_S 0 /** Check whether access to the ROUND field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_ROUND_P 0 /** Read the content of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_ROUND_LSB, ATON_POOL_CTRL_ROUND_W) /** Modify the content of the ROUND field of the CTRL register. */ #define ATON_POOL_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_ROUND_LSB, ATON_POOL_CTRL_ROUND_W, DATA) /** * Get the description of the ROUND field of CTRL register. * * \return the description of the ROUND field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_ROUND_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_ROUND_DESC; } /** * Read the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_ROUND(uint32_t reg) { return ATON_POOL_CTRL_GET_ROUND(reg); } /** * Write the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_ROUND(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_ROUND(reg, data); } /* ------------------------------------------------------------- SAT field of the CTRL register ------------------------------------------------------------- */ /** Description of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SAT_DESC "Enable output saturation (applicable to average pooling operations)" /** Offset of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SAT_LSB 7UL /** Size in bits of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SAT_W (1UL) /** Mask for retrieving the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SAT_MASK ATON_FIELD_MASK(7UL, 1UL) /** Reset value of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SAT_DT 0x0UL /** Access rights of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SAT_AC "RW" /** Check whether access to the SAT field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_SAT_S 0 /** Check whether access to the SAT field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_SAT_P 0 /** Read the content of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_SAT_LSB, ATON_POOL_CTRL_SAT_W) /** Modify the content of the SAT field of the CTRL register. */ #define ATON_POOL_CTRL_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_SAT_LSB, ATON_POOL_CTRL_SAT_W, DATA) /** * Get the description of the SAT field of CTRL register. * * \return the description of the SAT field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_SAT_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_SAT_DESC; } /** * Read the content of the SAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SAT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_SAT(uint32_t reg) { return ATON_POOL_CTRL_GET_SAT(reg); } /** * Write the content of the SAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SAT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_SAT(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_SAT(reg, data); } /* ---------------------------------------------------------- OUTSHIFT field of the CTRL register ----------------------------------------------------------- */ /** Description of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_OUTSHIFT_DESC "Optional right shift to apply the average pooling output" /** Offset of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_OUTSHIFT_LSB 8UL /** Size in bits of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_OUTSHIFT_W (6UL) /** Mask for retrieving the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_OUTSHIFT_MASK ATON_FIELD_MASK(8UL, 6UL) /** Reset value of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_OUTSHIFT_DT 0x0UL /** Access rights of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_OUTSHIFT_AC "RW" /** Check whether access to the OUTSHIFT field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_OUTSHIFT_S 0 /** Check whether access to the OUTSHIFT field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_OUTSHIFT_P 0 /** Read the content of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_GET_OUTSHIFT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_OUTSHIFT_LSB, ATON_POOL_CTRL_OUTSHIFT_W) /** Modify the content of the OUTSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_SET_OUTSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_OUTSHIFT_LSB, ATON_POOL_CTRL_OUTSHIFT_W, DATA) /** * Get the description of the OUTSHIFT field of CTRL register. * * \return the description of the OUTSHIFT field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_OUTSHIFT_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_OUTSHIFT_DESC; } /** * Read the content of the OUTSHIFT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the OUTSHIFT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_OUTSHIFT(uint32_t reg) { return ATON_POOL_CTRL_GET_OUTSHIFT(reg); } /** * Write the content of the OUTSHIFT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the OUTSHIFT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_OUTSHIFT(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_OUTSHIFT(reg, data); } /* ---------------------------------------------------------- DUALLINE field of the CTRL register ----------------------------------------------------------- */ /** Description of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_DUALLINE_DESC "Enable dual line, allows each linebuffer line to work as 2 lines, applicable for 8-bit data" /** Offset of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_DUALLINE_LSB 14UL /** Size in bits of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_DUALLINE_W (1UL) /** Mask for retrieving the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_DUALLINE_MASK ATON_FIELD_MASK(14UL, 1UL) /** Reset value of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_DUALLINE_DT 0x0UL /** Access rights of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_DUALLINE_AC "RW" /** Check whether access to the DUALLINE field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_DUALLINE_S 0 /** Check whether access to the DUALLINE field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_DUALLINE_P 0 /** Read the content of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_GET_DUALLINE(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_DUALLINE_LSB, ATON_POOL_CTRL_DUALLINE_W) /** Modify the content of the DUALLINE field of the CTRL register. */ #define ATON_POOL_CTRL_SET_DUALLINE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_DUALLINE_LSB, ATON_POOL_CTRL_DUALLINE_W, DATA) /** * Get the description of the DUALLINE field of CTRL register. * * \return the description of the DUALLINE field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_DUALLINE_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_DUALLINE_DESC; } /** * Read the content of the DUALLINE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DUALLINE field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_DUALLINE(uint32_t reg) { return ATON_POOL_CTRL_GET_DUALLINE(reg); } /** * Write the content of the DUALLINE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DUALLINE field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_DUALLINE(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_DUALLINE(reg, data); } /* ----------------------------------------------------------- CROPEN field of the CTRL register ------------------------------------------------------------ */ /** Description of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_CROPEN_DESC "Enable input feature cropping" /** Offset of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_CROPEN_LSB 15UL /** Size in bits of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_CROPEN_W (1UL) /** Mask for retrieving the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_CROPEN_MASK ATON_FIELD_MASK(15UL, 1UL) /** Reset value of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_CROPEN_DT 0x0UL /** Access rights of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_CROPEN_AC "RW" /** Check whether access to the CROPEN field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_CROPEN_S 0 /** Check whether access to the CROPEN field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_CROPEN_P 0 /** Read the content of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_GET_CROPEN(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_CROPEN_LSB, ATON_POOL_CTRL_CROPEN_W) /** Modify the content of the CROPEN field of the CTRL register. */ #define ATON_POOL_CTRL_SET_CROPEN(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_CROPEN_LSB, ATON_POOL_CTRL_CROPEN_W, DATA) /** * Get the description of the CROPEN field of CTRL register. * * \return the description of the CROPEN field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_CROPEN_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_CROPEN_DESC; } /** * Read the content of the CROPEN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CROPEN field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_CROPEN(uint32_t reg) { return ATON_POOL_CTRL_GET_CROPEN(reg); } /** * Write the content of the CROPEN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CROPEN field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_CROPEN(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_CROPEN(reg, data); } /* ----------------------------------------------------------- FBYTES field of the CTRL register ------------------------------------------------------------ */ /** Description of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_FBYTES_DESC "Input data width in bytes. Valid values are 1,2 or 3 bytes" /** Offset of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_FBYTES_LSB 16UL /** Size in bits of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_FBYTES_W (2UL) /** Mask for retrieving the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_FBYTES_MASK ATON_FIELD_MASK(16UL, 2UL) /** Reset value of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_FBYTES_DT 0x2UL /** Access rights of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_FBYTES_AC "RW" /** Check whether access to the FBYTES field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_FBYTES_S 0 /** Check whether access to the FBYTES field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_FBYTES_P 0 /** Read the content of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_GET_FBYTES(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FBYTES_LSB, ATON_POOL_CTRL_FBYTES_W) /** Modify the content of the FBYTES field of the CTRL register. */ #define ATON_POOL_CTRL_SET_FBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FBYTES_LSB, ATON_POOL_CTRL_FBYTES_W, DATA) /** * Get the description of the FBYTES field of CTRL register. * * \return the description of the FBYTES field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_FBYTES_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_FBYTES_DESC; } /** * Read the content of the FBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FBYTES field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_FBYTES(uint32_t reg) { return ATON_POOL_CTRL_GET_FBYTES(reg); } /** * Write the content of the FBYTES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FBYTES field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_FBYTES(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_FBYTES(reg, data); } /* ----------------------------------------------------------- FSHIFT field of the CTRL register ------------------------------------------------------------ */ /** Description of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_FSHIFT_DESC "Input feature data shift. Range [0,40]. For no shift, set to 16" /** Offset of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_FSHIFT_LSB 18UL /** Size in bits of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_FSHIFT_W (6UL) /** Mask for retrieving the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_FSHIFT_MASK ATON_FIELD_MASK(18UL, 6UL) /** Reset value of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_FSHIFT_DT 0x10UL /** Access rights of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_FSHIFT_AC "RW" /** Check whether access to the FSHIFT field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_FSHIFT_S 0 /** Check whether access to the FSHIFT field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_FSHIFT_P 0 /** Read the content of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_GET_FSHIFT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FSHIFT_LSB, ATON_POOL_CTRL_FSHIFT_W) /** Modify the content of the FSHIFT field of the CTRL register. */ #define ATON_POOL_CTRL_SET_FSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FSHIFT_LSB, ATON_POOL_CTRL_FSHIFT_W, DATA) /** * Get the description of the FSHIFT field of CTRL register. * * \return the description of the FSHIFT field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_FSHIFT_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_FSHIFT_DESC; } /** * Read the content of the FSHIFT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSHIFT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_FSHIFT(uint32_t reg) { return ATON_POOL_CTRL_GET_FSHIFT(reg); } /** * Write the content of the FSHIFT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the FSHIFT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_FSHIFT(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_FSHIFT(reg, data); } /* ----------------------------------------------------------- FROUND field of the CTRL register ------------------------------------------------------------ */ /** Description of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_FROUND_DESC "Input feature data rounding" /** Offset of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_FROUND_LSB 24UL /** Size in bits of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_FROUND_W (1UL) /** Mask for retrieving the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_FROUND_MASK ATON_FIELD_MASK(24UL, 1UL) /** Reset value of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_FROUND_DT 0x0UL /** Access rights of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_FROUND_AC "RW" /** Check whether access to the FROUND field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_FROUND_S 0 /** Check whether access to the FROUND field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_FROUND_P 0 /** Read the content of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_GET_FROUND(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FROUND_LSB, ATON_POOL_CTRL_FROUND_W) /** Modify the content of the FROUND field of the CTRL register. */ #define ATON_POOL_CTRL_SET_FROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FROUND_LSB, ATON_POOL_CTRL_FROUND_W, DATA) /** * Get the description of the FROUND field of CTRL register. * * \return the description of the FROUND field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_FROUND_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_FROUND_DESC; } /** * Read the content of the FROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FROUND field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_FROUND(uint32_t reg) { return ATON_POOL_CTRL_GET_FROUND(reg); } /** * Write the content of the FROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FROUND field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_FROUND(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_FROUND(reg, data); } /* ------------------------------------------------------------ FSAT field of the CTRL register ------------------------------------------------------------- */ /** Description of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_FSAT_DESC "Input feature data saturation" /** Offset of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_FSAT_LSB 25UL /** Size in bits of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_FSAT_W (1UL) /** Mask for retrieving the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_FSAT_MASK ATON_FIELD_MASK(25UL, 1UL) /** Reset value of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_FSAT_DT 0x0UL /** Access rights of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_FSAT_AC "RW" /** Check whether access to the FSAT field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_FSAT_S 0 /** Check whether access to the FSAT field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_FSAT_P 0 /** Read the content of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_GET_FSAT(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_FSAT_LSB, ATON_POOL_CTRL_FSAT_W) /** Modify the content of the FSAT field of the CTRL register. */ #define ATON_POOL_CTRL_SET_FSAT(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_FSAT_LSB, ATON_POOL_CTRL_FSAT_W, DATA) /** * Get the description of the FSAT field of CTRL register. * * \return the description of the FSAT field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_FSAT_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_FSAT_DESC; } /** * Read the content of the FSAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSAT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_FSAT(uint32_t reg) { return ATON_POOL_CTRL_GET_FSAT(reg); } /** * Write the content of the FSAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSAT field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_FSAT(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_FSAT(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_CONFCLR_DESC "Clear configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_POOL_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_POOL_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_POOL_CTRL_CONFCLR_LSB, ATON_POOL_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_POOL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_CTRL_CONFCLR_LSB, ATON_POOL_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_POOL_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_POOL_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_POOL_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_POOL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_POOL_CTRL_SET_CONFCLR(reg, data); } /* ******************************************************* VERSION register of one of the POOL Units ******************************************************** */ /** Offset of the VERSION register from the base address of the POOL Unit. */ #define ATON_POOL_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the POOL Unit. */ #define ATON_POOL_VERSION_DT \ (ATON_POOL_VERSION_TYPE_DT << ATON_POOL_VERSION_TYPE_LSB) | \ (ATON_POOL_VERSION_MINOR_DT << ATON_POOL_VERSION_MINOR_LSB) | \ (ATON_POOL_VERSION_MAJOR_DT << ATON_POOL_VERSION_MAJOR_LSB) /** Description of the VERSION register. */ #define ATON_POOL_VERSION_DESC "Version register" /** Address of the VERSION register of one of the POOL Units. */ #define ATON_POOL_VERSION_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_VERSION_OFFSET) /** Get the content of the VERSION register of one of the POOL Units. */ #define ATON_POOL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_POOL_VERSION_GetDesc(void) { return (const int8_t *)ATON_POOL_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_POOL_VERSION_GetOffset(void) { return ATON_POOL_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the VERSION register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_VERSION_GetAddr(uint32_t instance) { return ATON_POOL_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_VERSION_Get(uint32_t instance) { return ATON_POOL_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_TYPE_DT 0x1cUL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_POOL_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_POOL_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_POOL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_POOL_VERSION_TYPE_LSB, ATON_POOL_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_POOL_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_POOL_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_POOL_VERSION_Get_TYPE(uint32_t reg) { return ATON_POOL_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_MINOR_DT 0x1UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_POOL_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_POOL_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_POOL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_POOL_VERSION_MINOR_LSB, ATON_POOL_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_POOL_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_POOL_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_POOL_VERSION_Get_MINOR(uint32_t reg) { return ATON_POOL_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_POOL_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_POOL_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_POOL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_POOL_VERSION_MAJOR_LSB, ATON_POOL_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_POOL_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_POOL_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_POOL_VERSION_Get_MAJOR(uint32_t reg) { return ATON_POOL_VERSION_GET_MAJOR(reg); } /* ******************************************************** PDIMS register of one of the POOL Units ********************************************************* */ /** Offset of the PDIMS register from the base address of the POOL Unit. */ #define ATON_POOL_PDIMS_OFFSET 0x8UL /** Reset value of the PDIMS register of the POOL Unit. */ #define ATON_POOL_PDIMS_DT \ (ATON_POOL_PDIMS_WINX_DT << ATON_POOL_PDIMS_WINX_LSB) | \ (ATON_POOL_PDIMS_WINY_DT << ATON_POOL_PDIMS_WINY_LSB) | \ (ATON_POOL_PDIMS_STRDX_DT << ATON_POOL_PDIMS_STRDX_LSB) | \ (ATON_POOL_PDIMS_STRDY_DT << ATON_POOL_PDIMS_STRDY_LSB) | \ (ATON_POOL_PDIMS_TPAD_DT << ATON_POOL_PDIMS_TPAD_LSB) | \ (ATON_POOL_PDIMS_BPAD_DT << ATON_POOL_PDIMS_BPAD_LSB) | \ (ATON_POOL_PDIMS_LPAD_DT << ATON_POOL_PDIMS_LPAD_LSB) | \ (ATON_POOL_PDIMS_RPAD_DT << ATON_POOL_PDIMS_RPAD_LSB) | \ (ATON_POOL_PDIMS_BSIZE_DT << ATON_POOL_PDIMS_BSIZE_LSB) /** Description of the PDIMS register. */ #define ATON_POOL_PDIMS_DESC "Pool dimensions" /** Address of the PDIMS register of one of the POOL Units. */ #define ATON_POOL_PDIMS_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_PDIMS_OFFSET) /** Get the content of the PDIMS register of one of the POOL Units. */ #define ATON_POOL_PDIMS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_PDIMS_ADDR(UNIT))) /** Set the content of the PDIMS register of one of the POOL Units. */ #define ATON_POOL_PDIMS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_PDIMS_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of PDIMS register. * * \return the description of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_GetDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_DESC; } /** * Get the offset of the PDIMS register. * * \return the offset of PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_GetOffset(void) { return ATON_POOL_PDIMS_OFFSET; } /** * Get the address of the PDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the PDIMS register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of PDIMS register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_PDIMS_GetAddr(uint32_t instance) { return ATON_POOL_PDIMS_ADDR(instance); } /** * Read the content of the PDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the PDIMS register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of PDIMS register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_PDIMS_Get(uint32_t instance) { return ATON_POOL_PDIMS_GET(instance); } /** * Write the content of the PDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the PDIMS register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_PDIMS_Set(uint32_t instance, uint32_t data) { ATON_POOL_PDIMS_SET(instance, data); } /* ------------------------------------------------------------ WINX field of the PDIMS register ------------------------------------------------------------ */ /** Description of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINX_DESC "Pool window width" /** Offset of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINX_LSB 0UL /** Size in bits of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINX_W (3UL) /** Mask for retrieving the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINX_MASK ATON_FIELD_MASK(0UL, 3UL) /** Reset value of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINX_DT 0x0UL /** Access rights of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINX_AC "RW" /** Check whether access to the WINX field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_WINX_S 0 /** Check whether access to the WINX field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_WINX_P 0 /** Read the content of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_WINX(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_WINX_LSB, ATON_POOL_PDIMS_WINX_W) /** Modify the content of the WINX field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_WINX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_WINX_LSB, ATON_POOL_PDIMS_WINX_W, DATA) /** * Get the description of the WINX field of PDIMS register. * * \return the description of the WINX field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_WINX_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_WINX_DESC; } /** * Read the content of the WINX field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the WINX field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_WINX(uint32_t reg) { return ATON_POOL_PDIMS_GET_WINX(reg); } /** * Write the content of the WINX field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the WINX field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_WINX(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_WINX(reg, data); } /* ------------------------------------------------------------ WINY field of the PDIMS register ------------------------------------------------------------ */ /** Description of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINY_DESC "Pool window height" /** Offset of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINY_LSB 3UL /** Size in bits of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINY_W (3UL) /** Mask for retrieving the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINY_MASK ATON_FIELD_MASK(3UL, 3UL) /** Reset value of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINY_DT 0x0UL /** Access rights of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_WINY_AC "RW" /** Check whether access to the WINY field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_WINY_S 0 /** Check whether access to the WINY field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_WINY_P 0 /** Read the content of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_WINY(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_WINY_LSB, ATON_POOL_PDIMS_WINY_W) /** Modify the content of the WINY field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_WINY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_WINY_LSB, ATON_POOL_PDIMS_WINY_W, DATA) /** * Get the description of the WINY field of PDIMS register. * * \return the description of the WINY field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_WINY_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_WINY_DESC; } /** * Read the content of the WINY field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the WINY field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_WINY(uint32_t reg) { return ATON_POOL_PDIMS_GET_WINY(reg); } /** * Write the content of the WINY field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the WINY field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_WINY(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_WINY(reg, data); } /* ----------------------------------------------------------- STRDX field of the PDIMS register ------------------------------------------------------------ */ /** Description of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDX_DESC "Window stride in X direction along width" /** Offset of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDX_LSB 6UL /** Size in bits of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDX_W (4UL) /** Mask for retrieving the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDX_MASK ATON_FIELD_MASK(6UL, 4UL) /** Reset value of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDX_DT 0x0UL /** Access rights of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDX_AC "RW" /** Check whether access to the STRDX field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_STRDX_S 0 /** Check whether access to the STRDX field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_STRDX_P 0 /** Read the content of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_STRDX(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_STRDX_LSB, ATON_POOL_PDIMS_STRDX_W) /** Modify the content of the STRDX field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_STRDX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_STRDX_LSB, ATON_POOL_PDIMS_STRDX_W, DATA) /** * Get the description of the STRDX field of PDIMS register. * * \return the description of the STRDX field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_STRDX_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_STRDX_DESC; } /** * Read the content of the STRDX field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the STRDX field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_STRDX(uint32_t reg) { return ATON_POOL_PDIMS_GET_STRDX(reg); } /** * Write the content of the STRDX field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STRDX field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_STRDX(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_STRDX(reg, data); } /* ----------------------------------------------------------- STRDY field of the PDIMS register ------------------------------------------------------------ */ /** Description of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDY_DESC "Window stride in Y direction along height" /** Offset of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDY_LSB 10UL /** Size in bits of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDY_W (4UL) /** Mask for retrieving the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDY_MASK ATON_FIELD_MASK(10UL, 4UL) /** Reset value of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDY_DT 0x0UL /** Access rights of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_STRDY_AC "RW" /** Check whether access to the STRDY field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_STRDY_S 0 /** Check whether access to the STRDY field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_STRDY_P 0 /** Read the content of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_STRDY(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_STRDY_LSB, ATON_POOL_PDIMS_STRDY_W) /** Modify the content of the STRDY field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_STRDY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_STRDY_LSB, ATON_POOL_PDIMS_STRDY_W, DATA) /** * Get the description of the STRDY field of PDIMS register. * * \return the description of the STRDY field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_STRDY_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_STRDY_DESC; } /** * Read the content of the STRDY field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the STRDY field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_STRDY(uint32_t reg) { return ATON_POOL_PDIMS_GET_STRDY(reg); } /** * Write the content of the STRDY field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STRDY field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_STRDY(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_STRDY(reg, data); } /* ------------------------------------------------------------ TPAD field of the PDIMS register ------------------------------------------------------------ */ /** Description of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_TPAD_DESC "Padding applied to top" /** Offset of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_TPAD_LSB 14UL /** Size in bits of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_TPAD_W (3UL) /** Mask for retrieving the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_TPAD_MASK ATON_FIELD_MASK(14UL, 3UL) /** Reset value of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_TPAD_DT 0x0UL /** Access rights of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_TPAD_AC "RW" /** Check whether access to the TPAD field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_TPAD_S 0 /** Check whether access to the TPAD field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_TPAD_P 0 /** Read the content of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_TPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_TPAD_LSB, ATON_POOL_PDIMS_TPAD_W) /** Modify the content of the TPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_TPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_TPAD_LSB, ATON_POOL_PDIMS_TPAD_W, DATA) /** * Get the description of the TPAD field of PDIMS register. * * \return the description of the TPAD field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_TPAD_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_TPAD_DESC; } /** * Read the content of the TPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the TPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_TPAD(uint32_t reg) { return ATON_POOL_PDIMS_GET_TPAD(reg); } /** * Write the content of the TPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the TPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_TPAD(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_TPAD(reg, data); } /* ------------------------------------------------------------ BPAD field of the PDIMS register ------------------------------------------------------------ */ /** Description of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_BPAD_DESC "Padding applied to bottom" /** Offset of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_BPAD_LSB 17UL /** Size in bits of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_BPAD_W (3UL) /** Mask for retrieving the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_BPAD_MASK ATON_FIELD_MASK(17UL, 3UL) /** Reset value of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_BPAD_DT 0x0UL /** Access rights of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_BPAD_AC "RW" /** Check whether access to the BPAD field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_BPAD_S 0 /** Check whether access to the BPAD field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_BPAD_P 0 /** Read the content of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_BPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_BPAD_LSB, ATON_POOL_PDIMS_BPAD_W) /** Modify the content of the BPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_BPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_BPAD_LSB, ATON_POOL_PDIMS_BPAD_W, DATA) /** * Get the description of the BPAD field of PDIMS register. * * \return the description of the BPAD field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_BPAD_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_BPAD_DESC; } /** * Read the content of the BPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the BPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_BPAD(uint32_t reg) { return ATON_POOL_PDIMS_GET_BPAD(reg); } /** * Write the content of the BPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the BPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_BPAD(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_BPAD(reg, data); } /* ------------------------------------------------------------ LPAD field of the PDIMS register ------------------------------------------------------------ */ /** Description of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_LPAD_DESC "Padding applied to left" /** Offset of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_LPAD_LSB 20UL /** Size in bits of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_LPAD_W (3UL) /** Mask for retrieving the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_LPAD_MASK ATON_FIELD_MASK(20UL, 3UL) /** Reset value of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_LPAD_DT 0x0UL /** Access rights of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_LPAD_AC "RW" /** Check whether access to the LPAD field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_LPAD_S 0 /** Check whether access to the LPAD field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_LPAD_P 0 /** Read the content of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_LPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_LPAD_LSB, ATON_POOL_PDIMS_LPAD_W) /** Modify the content of the LPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_LPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_LPAD_LSB, ATON_POOL_PDIMS_LPAD_W, DATA) /** * Get the description of the LPAD field of PDIMS register. * * \return the description of the LPAD field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_LPAD_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_LPAD_DESC; } /** * Read the content of the LPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the LPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_LPAD(uint32_t reg) { return ATON_POOL_PDIMS_GET_LPAD(reg); } /** * Write the content of the LPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the LPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_LPAD(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_LPAD(reg, data); } /* ------------------------------------------------------------ RPAD field of the PDIMS register ------------------------------------------------------------ */ /** Description of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_RPAD_DESC "Padding applied to right" /** Offset of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_RPAD_LSB 23UL /** Size in bits of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_RPAD_W (3UL) /** Mask for retrieving the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_RPAD_MASK ATON_FIELD_MASK(23UL, 3UL) /** Reset value of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_RPAD_DT 0x0UL /** Access rights of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_RPAD_AC "RW" /** Check whether access to the RPAD field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_RPAD_S 0 /** Check whether access to the RPAD field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_RPAD_P 0 /** Read the content of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_RPAD(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_RPAD_LSB, ATON_POOL_PDIMS_RPAD_W) /** Modify the content of the RPAD field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_RPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_RPAD_LSB, ATON_POOL_PDIMS_RPAD_W, DATA) /** * Get the description of the RPAD field of PDIMS register. * * \return the description of the RPAD field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_RPAD_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_RPAD_DESC; } /** * Read the content of the RPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the RPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_RPAD(uint32_t reg) { return ATON_POOL_PDIMS_GET_RPAD(reg); } /** * Write the content of the RPAD field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the RPAD field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_RPAD(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_RPAD(reg, data); } /* ----------------------------------------------------------- BSIZE field of the PDIMS register ------------------------------------------------------------ */ /** Description of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_BSIZE_DESC "Batch size" /** Offset of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_BSIZE_LSB 26UL /** Size in bits of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_BSIZE_W (4UL) /** Mask for retrieving the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_BSIZE_MASK ATON_FIELD_MASK(26UL, 4UL) /** Reset value of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_BSIZE_DT 0x0UL /** Access rights of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_BSIZE_AC "RW" /** Check whether access to the BSIZE field of the PDIMS register is secured or not. */ #define ATON_POOL_PDIMS_BSIZE_S 0 /** Check whether access to the BSIZE field of the PDIMS register is privileged or not. */ #define ATON_POOL_PDIMS_BSIZE_P 0 /** Read the content of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_GET_BSIZE(REG) ATON_GET_FIELD(REG, ATON_POOL_PDIMS_BSIZE_LSB, ATON_POOL_PDIMS_BSIZE_W) /** Modify the content of the BSIZE field of the PDIMS register. */ #define ATON_POOL_PDIMS_SET_BSIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_PDIMS_BSIZE_LSB, ATON_POOL_PDIMS_BSIZE_W, DATA) /** * Get the description of the BSIZE field of PDIMS register. * * \return the description of the BSIZE field of PDIMS register */ static inline const int8_t *ATON_POOL_PDIMS_BSIZE_GetdDesc(void) { return (const int8_t *)ATON_POOL_PDIMS_BSIZE_DESC; } /** * Read the content of the BSIZE field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * * \return the content of the BSIZE field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Get_BSIZE(uint32_t reg) { return ATON_POOL_PDIMS_GET_BSIZE(reg); } /** * Write the content of the BSIZE field of the PDIMS register. * * \param[in] reg is the value of the PDIMS register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the BSIZE field belonging to PDIMS register */ static inline uint32_t ATON_POOL_PDIMS_Set_BSIZE(uint32_t reg, uint32_t data) { return ATON_POOL_PDIMS_SET_BSIZE(reg, data); } /* ******************************************************** FDIMS register of one of the POOL Units ********************************************************* */ /** Offset of the FDIMS register from the base address of the POOL Unit. */ #define ATON_POOL_FDIMS_OFFSET 0xcUL /** Reset value of the FDIMS register of the POOL Unit. */ #define ATON_POOL_FDIMS_DT \ (ATON_POOL_FDIMS_FEATX_DT << ATON_POOL_FDIMS_FEATX_LSB) | \ (ATON_POOL_FDIMS_FEATY_DT << ATON_POOL_FDIMS_FEATY_LSB) /** Description of the FDIMS register. */ #define ATON_POOL_FDIMS_DESC "Feature dimensions" /** Address of the FDIMS register of one of the POOL Units. */ #define ATON_POOL_FDIMS_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_FDIMS_OFFSET) /** Get the content of the FDIMS register of one of the POOL Units. */ #define ATON_POOL_FDIMS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_FDIMS_ADDR(UNIT))) /** Set the content of the FDIMS register of one of the POOL Units. */ #define ATON_POOL_FDIMS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_FDIMS_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FDIMS register. * * \return the description of FDIMS register */ static inline const int8_t *ATON_POOL_FDIMS_GetDesc(void) { return (const int8_t *)ATON_POOL_FDIMS_DESC; } /** * Get the offset of the FDIMS register. * * \return the offset of FDIMS register */ static inline uint32_t ATON_POOL_FDIMS_GetOffset(void) { return ATON_POOL_FDIMS_OFFSET; } /** * Get the address of the FDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the FDIMS register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of FDIMS register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_FDIMS_GetAddr(uint32_t instance) { return ATON_POOL_FDIMS_ADDR(instance); } /** * Read the content of the FDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the FDIMS register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of FDIMS register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_FDIMS_Get(uint32_t instance) { return ATON_POOL_FDIMS_GET(instance); } /** * Write the content of the FDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the FDIMS register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_FDIMS_Set(uint32_t instance, uint32_t data) { ATON_POOL_FDIMS_SET(instance, data); } /* ----------------------------------------------------------- FEATX field of the FDIMS register ------------------------------------------------------------ */ /** Description of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATX_DESC "Input feature width (actual feature width x batch size)" /** Offset of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATX_LSB 0UL /** Size in bits of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATX_W (12UL) /** Mask for retrieving the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATX_MASK ATON_FIELD_MASK(0UL, 12UL) /** Reset value of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATX_DT 0x0UL /** Access rights of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATX_AC "RW" /** Check whether access to the FEATX field of the FDIMS register is secured or not. */ #define ATON_POOL_FDIMS_FEATX_S 0 /** Check whether access to the FEATX field of the FDIMS register is privileged or not. */ #define ATON_POOL_FDIMS_FEATX_P 0 /** Read the content of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_GET_FEATX(REG) ATON_GET_FIELD(REG, ATON_POOL_FDIMS_FEATX_LSB, ATON_POOL_FDIMS_FEATX_W) /** Modify the content of the FEATX field of the FDIMS register. */ #define ATON_POOL_FDIMS_SET_FEATX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_FDIMS_FEATX_LSB, ATON_POOL_FDIMS_FEATX_W, DATA) /** * Get the description of the FEATX field of FDIMS register. * * \return the description of the FEATX field of FDIMS register */ static inline const int8_t *ATON_POOL_FDIMS_FEATX_GetdDesc(void) { return (const int8_t *)ATON_POOL_FDIMS_FEATX_DESC; } /** * Read the content of the FEATX field of the FDIMS register. * * \param[in] reg is the value of the FDIMS register * * \return the content of the FEATX field belonging to FDIMS register */ static inline uint32_t ATON_POOL_FDIMS_Get_FEATX(uint32_t reg) { return ATON_POOL_FDIMS_GET_FEATX(reg); } /** * Write the content of the FEATX field of the FDIMS register. * * \param[in] reg is the value of the FDIMS register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the FEATX field belonging to FDIMS register */ static inline uint32_t ATON_POOL_FDIMS_Set_FEATX(uint32_t reg, uint32_t data) { return ATON_POOL_FDIMS_SET_FEATX(reg, data); } /* ----------------------------------------------------------- FEATY field of the FDIMS register ------------------------------------------------------------ */ /** Description of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATY_DESC "Input feature height (actual feature height)" /** Offset of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATY_LSB 16UL /** Size in bits of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATY_W (12UL) /** Mask for retrieving the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATY_MASK ATON_FIELD_MASK(16UL, 12UL) /** Reset value of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATY_DT 0x0UL /** Access rights of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_FEATY_AC "RW" /** Check whether access to the FEATY field of the FDIMS register is secured or not. */ #define ATON_POOL_FDIMS_FEATY_S 0 /** Check whether access to the FEATY field of the FDIMS register is privileged or not. */ #define ATON_POOL_FDIMS_FEATY_P 0 /** Read the content of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_GET_FEATY(REG) ATON_GET_FIELD(REG, ATON_POOL_FDIMS_FEATY_LSB, ATON_POOL_FDIMS_FEATY_W) /** Modify the content of the FEATY field of the FDIMS register. */ #define ATON_POOL_FDIMS_SET_FEATY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_FDIMS_FEATY_LSB, ATON_POOL_FDIMS_FEATY_W, DATA) /** * Get the description of the FEATY field of FDIMS register. * * \return the description of the FEATY field of FDIMS register */ static inline const int8_t *ATON_POOL_FDIMS_FEATY_GetdDesc(void) { return (const int8_t *)ATON_POOL_FDIMS_FEATY_DESC; } /** * Read the content of the FEATY field of the FDIMS register. * * \param[in] reg is the value of the FDIMS register * * \return the content of the FEATY field belonging to FDIMS register */ static inline uint32_t ATON_POOL_FDIMS_Get_FEATY(uint32_t reg) { return ATON_POOL_FDIMS_GET_FEATY(reg); } /** * Write the content of the FEATY field of the FDIMS register. * * \param[in] reg is the value of the FDIMS register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the FEATY field belonging to FDIMS register */ static inline uint32_t ATON_POOL_FDIMS_Set_FEATY(uint32_t reg, uint32_t data) { return ATON_POOL_FDIMS_SET_FEATY(reg, data); } /* ******************************************************* OUTDIMS register of one of the POOL Units ******************************************************** */ /** Offset of the OUTDIMS register from the base address of the POOL Unit. */ #define ATON_POOL_OUTDIMS_OFFSET 0x10UL /** Reset value of the OUTDIMS register of the POOL Unit. */ #define ATON_POOL_OUTDIMS_DT \ (ATON_POOL_OUTDIMS_FEATX_DT << ATON_POOL_OUTDIMS_FEATX_LSB) | \ (ATON_POOL_OUTDIMS_FEATY_DT << ATON_POOL_OUTDIMS_FEATY_LSB) /** Description of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_DESC "Output feature dimensions" /** Address of the OUTDIMS register of one of the POOL Units. */ #define ATON_POOL_OUTDIMS_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_OUTDIMS_OFFSET) /** Get the content of the OUTDIMS register of one of the POOL Units. */ #define ATON_POOL_OUTDIMS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_OUTDIMS_ADDR(UNIT))) /** Set the content of the OUTDIMS register of one of the POOL Units. */ #define ATON_POOL_OUTDIMS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_OUTDIMS_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of OUTDIMS register. * * \return the description of OUTDIMS register */ static inline const int8_t *ATON_POOL_OUTDIMS_GetDesc(void) { return (const int8_t *)ATON_POOL_OUTDIMS_DESC; } /** * Get the offset of the OUTDIMS register. * * \return the offset of OUTDIMS register */ static inline uint32_t ATON_POOL_OUTDIMS_GetOffset(void) { return ATON_POOL_OUTDIMS_OFFSET; } /** * Get the address of the OUTDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the OUTDIMS register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of OUTDIMS register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_OUTDIMS_GetAddr(uint32_t instance) { return ATON_POOL_OUTDIMS_ADDR(instance); } /** * Read the content of the OUTDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the OUTDIMS register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of OUTDIMS register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_OUTDIMS_Get(uint32_t instance) { return ATON_POOL_OUTDIMS_GET(instance); } /** * Write the content of the OUTDIMS register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the OUTDIMS register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_OUTDIMS_Set(uint32_t instance, uint32_t data) { ATON_POOL_OUTDIMS_SET(instance, data); } /* ---------------------------------------------------------- FEATX field of the OUTDIMS register ----------------------------------------------------------- */ /** Description of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATX_DESC "Output feature width" /** Offset of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATX_LSB 0UL /** Size in bits of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATX_W (12UL) /** Mask for retrieving the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATX_MASK ATON_FIELD_MASK(0UL, 12UL) /** Reset value of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATX_DT 0x0UL /** Access rights of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATX_AC "RW" /** Check whether access to the FEATX field of the OUTDIMS register is secured or not. */ #define ATON_POOL_OUTDIMS_FEATX_S 0 /** Check whether access to the FEATX field of the OUTDIMS register is privileged or not. */ #define ATON_POOL_OUTDIMS_FEATX_P 0 /** Read the content of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_GET_FEATX(REG) ATON_GET_FIELD(REG, ATON_POOL_OUTDIMS_FEATX_LSB, ATON_POOL_OUTDIMS_FEATX_W) /** Modify the content of the FEATX field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_SET_FEATX(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_OUTDIMS_FEATX_LSB, ATON_POOL_OUTDIMS_FEATX_W, DATA) /** * Get the description of the FEATX field of OUTDIMS register. * * \return the description of the FEATX field of OUTDIMS register */ static inline const int8_t *ATON_POOL_OUTDIMS_FEATX_GetdDesc(void) { return (const int8_t *)ATON_POOL_OUTDIMS_FEATX_DESC; } /** * Read the content of the FEATX field of the OUTDIMS register. * * \param[in] reg is the value of the OUTDIMS register * * \return the content of the FEATX field belonging to OUTDIMS register */ static inline uint32_t ATON_POOL_OUTDIMS_Get_FEATX(uint32_t reg) { return ATON_POOL_OUTDIMS_GET_FEATX(reg); } /** * Write the content of the FEATX field of the OUTDIMS register. * * \param[in] reg is the value of the OUTDIMS register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the FEATX field belonging to OUTDIMS register */ static inline uint32_t ATON_POOL_OUTDIMS_Set_FEATX(uint32_t reg, uint32_t data) { return ATON_POOL_OUTDIMS_SET_FEATX(reg, data); } /* ---------------------------------------------------------- FEATY field of the OUTDIMS register ----------------------------------------------------------- */ /** Description of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATY_DESC "Output feature height" /** Offset of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATY_LSB 16UL /** Size in bits of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATY_W (12UL) /** Mask for retrieving the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATY_MASK ATON_FIELD_MASK(16UL, 12UL) /** Reset value of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATY_DT 0x0UL /** Access rights of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_FEATY_AC "RW" /** Check whether access to the FEATY field of the OUTDIMS register is secured or not. */ #define ATON_POOL_OUTDIMS_FEATY_S 0 /** Check whether access to the FEATY field of the OUTDIMS register is privileged or not. */ #define ATON_POOL_OUTDIMS_FEATY_P 0 /** Read the content of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_GET_FEATY(REG) ATON_GET_FIELD(REG, ATON_POOL_OUTDIMS_FEATY_LSB, ATON_POOL_OUTDIMS_FEATY_W) /** Modify the content of the FEATY field of the OUTDIMS register. */ #define ATON_POOL_OUTDIMS_SET_FEATY(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_OUTDIMS_FEATY_LSB, ATON_POOL_OUTDIMS_FEATY_W, DATA) /** * Get the description of the FEATY field of OUTDIMS register. * * \return the description of the FEATY field of OUTDIMS register */ static inline const int8_t *ATON_POOL_OUTDIMS_FEATY_GetdDesc(void) { return (const int8_t *)ATON_POOL_OUTDIMS_FEATY_DESC; } /** * Read the content of the FEATY field of the OUTDIMS register. * * \param[in] reg is the value of the OUTDIMS register * * \return the content of the FEATY field belonging to OUTDIMS register */ static inline uint32_t ATON_POOL_OUTDIMS_Get_FEATY(uint32_t reg) { return ATON_POOL_OUTDIMS_GET_FEATY(reg); } /** * Write the content of the FEATY field of the OUTDIMS register. * * \param[in] reg is the value of the OUTDIMS register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the FEATY field belonging to OUTDIMS register */ static inline uint32_t ATON_POOL_OUTDIMS_Set_FEATY(uint32_t reg, uint32_t data) { return ATON_POOL_OUTDIMS_SET_FEATY(reg, data); } /* ******************************************************** MULVAL register of one of the POOL Units ******************************************************** */ /** Offset of the MULVAL register from the base address of the POOL Unit. */ #define ATON_POOL_MULVAL_OFFSET 0x14UL /** Reset value of the MULVAL register of the POOL Unit. */ #define ATON_POOL_MULVAL_DT \ (ATON_POOL_MULVAL_MULVAL_DT << ATON_POOL_MULVAL_MULVAL_LSB) /** Description of the MULVAL register. */ #define ATON_POOL_MULVAL_DESC "average pooling data" /** Address of the MULVAL register of one of the POOL Units. */ #define ATON_POOL_MULVAL_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_MULVAL_OFFSET) /** Get the content of the MULVAL register of one of the POOL Units. */ #define ATON_POOL_MULVAL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_MULVAL_ADDR(UNIT))) /** Set the content of the MULVAL register of one of the POOL Units. */ #define ATON_POOL_MULVAL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_MULVAL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of MULVAL register. * * \return the description of MULVAL register */ static inline const int8_t *ATON_POOL_MULVAL_GetDesc(void) { return (const int8_t *)ATON_POOL_MULVAL_DESC; } /** * Get the offset of the MULVAL register. * * \return the offset of MULVAL register */ static inline uint32_t ATON_POOL_MULVAL_GetOffset(void) { return ATON_POOL_MULVAL_OFFSET; } /** * Get the address of the MULVAL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the MULVAL register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of MULVAL register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_MULVAL_GetAddr(uint32_t instance) { return ATON_POOL_MULVAL_ADDR(instance); } /** * Read the content of the MULVAL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the MULVAL register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of MULVAL register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_MULVAL_Get(uint32_t instance) { return ATON_POOL_MULVAL_GET(instance); } /** * Write the content of the MULVAL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the MULVAL register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_MULVAL_Set(uint32_t instance, uint32_t data) { ATON_POOL_MULVAL_SET(instance, data); } /* ---------------------------------------------------------- MULVAL field of the MULVAL register ----------------------------------------------------------- */ /** Description of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_MULVAL_DESC "constant to be multiplied to accumulated sum of pooling window. For average operation, it represents the reciprocal of the divisor in 16-bit fixed point. The average is computed by multiplying this constant with the accumulated sum and then applying the relevant right shift at the output. (Applicable to average pooling operations)" /** Offset of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_MULVAL_LSB 0UL /** Size in bits of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_MULVAL_W (16UL) /** Mask for retrieving the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_MULVAL_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_MULVAL_DT 0x0UL /** Access rights of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_MULVAL_AC "RW" /** Check whether access to the MULVAL field of the MULVAL register is secured or not. */ #define ATON_POOL_MULVAL_MULVAL_S 0 /** Check whether access to the MULVAL field of the MULVAL register is privileged or not. */ #define ATON_POOL_MULVAL_MULVAL_P 0 /** Read the content of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_GET_MULVAL(REG) ATON_GET_FIELD(REG, ATON_POOL_MULVAL_MULVAL_LSB, ATON_POOL_MULVAL_MULVAL_W) /** Modify the content of the MULVAL field of the MULVAL register. */ #define ATON_POOL_MULVAL_SET_MULVAL(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_MULVAL_MULVAL_LSB, ATON_POOL_MULVAL_MULVAL_W, DATA) /** * Get the description of the MULVAL field of MULVAL register. * * \return the description of the MULVAL field of MULVAL register */ static inline const int8_t *ATON_POOL_MULVAL_MULVAL_GetdDesc(void) { return (const int8_t *)ATON_POOL_MULVAL_MULVAL_DESC; } /** * Read the content of the MULVAL field of the MULVAL register. * * \param[in] reg is the value of the MULVAL register * * \return the content of the MULVAL field belonging to MULVAL register */ static inline uint32_t ATON_POOL_MULVAL_Get_MULVAL(uint32_t reg) { return ATON_POOL_MULVAL_GET_MULVAL(reg); } /** * Write the content of the MULVAL field of the MULVAL register. * * \param[in] reg is the value of the MULVAL register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the MULVAL field belonging to MULVAL register */ static inline uint32_t ATON_POOL_MULVAL_Set_MULVAL(uint32_t reg, uint32_t data) { return ATON_POOL_MULVAL_SET_MULVAL(reg, data); } /* ******************************************************** XCROP register of one of the POOL Units ********************************************************* */ /** Offset of the XCROP register from the base address of the POOL Unit. */ #define ATON_POOL_XCROP_OFFSET 0x18UL /** Reset value of the XCROP register of the POOL Unit. */ #define ATON_POOL_XCROP_DT \ (ATON_POOL_XCROP_LCROP_DT << ATON_POOL_XCROP_LCROP_LSB) | \ (ATON_POOL_XCROP_RCROP_DT << ATON_POOL_XCROP_RCROP_LSB) /** Description of the XCROP register. */ #define ATON_POOL_XCROP_DESC "left/right cropping dimensions" /** Address of the XCROP register of one of the POOL Units. */ #define ATON_POOL_XCROP_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_XCROP_OFFSET) /** Get the content of the XCROP register of one of the POOL Units. */ #define ATON_POOL_XCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_XCROP_ADDR(UNIT))) /** Set the content of the XCROP register of one of the POOL Units. */ #define ATON_POOL_XCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_XCROP_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of XCROP register. * * \return the description of XCROP register */ static inline const int8_t *ATON_POOL_XCROP_GetDesc(void) { return (const int8_t *)ATON_POOL_XCROP_DESC; } /** * Get the offset of the XCROP register. * * \return the offset of XCROP register */ static inline uint32_t ATON_POOL_XCROP_GetOffset(void) { return ATON_POOL_XCROP_OFFSET; } /** * Get the address of the XCROP register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the XCROP register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of XCROP register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_XCROP_GetAddr(uint32_t instance) { return ATON_POOL_XCROP_ADDR(instance); } /** * Read the content of the XCROP register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the XCROP register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of XCROP register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_XCROP_Get(uint32_t instance) { return ATON_POOL_XCROP_GET(instance); } /** * Write the content of the XCROP register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the XCROP register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_XCROP_Set(uint32_t instance, uint32_t data) { ATON_POOL_XCROP_SET(instance, data); } /* ----------------------------------------------------------- LCROP field of the XCROP register ------------------------------------------------------------ */ /** Description of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_LCROP_DESC "left crop index (zero-indexed) to be included in the crop" /** Offset of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_LCROP_LSB 0UL /** Size in bits of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_LCROP_W (12UL) /** Mask for retrieving the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_LCROP_MASK ATON_FIELD_MASK(0UL, 12UL) /** Reset value of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_LCROP_DT 0x0UL /** Access rights of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_LCROP_AC "RW" /** Check whether access to the LCROP field of the XCROP register is secured or not. */ #define ATON_POOL_XCROP_LCROP_S 0 /** Check whether access to the LCROP field of the XCROP register is privileged or not. */ #define ATON_POOL_XCROP_LCROP_P 0 /** Read the content of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_GET_LCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_XCROP_LCROP_LSB, ATON_POOL_XCROP_LCROP_W) /** Modify the content of the LCROP field of the XCROP register. */ #define ATON_POOL_XCROP_SET_LCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_XCROP_LCROP_LSB, ATON_POOL_XCROP_LCROP_W, DATA) /** * Get the description of the LCROP field of XCROP register. * * \return the description of the LCROP field of XCROP register */ static inline const int8_t *ATON_POOL_XCROP_LCROP_GetdDesc(void) { return (const int8_t *)ATON_POOL_XCROP_LCROP_DESC; } /** * Read the content of the LCROP field of the XCROP register. * * \param[in] reg is the value of the XCROP register * * \return the content of the LCROP field belonging to XCROP register */ static inline uint32_t ATON_POOL_XCROP_Get_LCROP(uint32_t reg) { return ATON_POOL_XCROP_GET_LCROP(reg); } /** * Write the content of the LCROP field of the XCROP register. * * \param[in] reg is the value of the XCROP register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the LCROP field belonging to XCROP register */ static inline uint32_t ATON_POOL_XCROP_Set_LCROP(uint32_t reg, uint32_t data) { return ATON_POOL_XCROP_SET_LCROP(reg, data); } /* ----------------------------------------------------------- RCROP field of the XCROP register ------------------------------------------------------------ */ /** Description of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_RCROP_DESC "right crop index (zero-indexed) to be included in the crop" /** Offset of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_RCROP_LSB 16UL /** Size in bits of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_RCROP_W (12UL) /** Mask for retrieving the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_RCROP_MASK ATON_FIELD_MASK(16UL, 12UL) /** Reset value of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_RCROP_DT 0x0UL /** Access rights of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_RCROP_AC "RW" /** Check whether access to the RCROP field of the XCROP register is secured or not. */ #define ATON_POOL_XCROP_RCROP_S 0 /** Check whether access to the RCROP field of the XCROP register is privileged or not. */ #define ATON_POOL_XCROP_RCROP_P 0 /** Read the content of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_GET_RCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_XCROP_RCROP_LSB, ATON_POOL_XCROP_RCROP_W) /** Modify the content of the RCROP field of the XCROP register. */ #define ATON_POOL_XCROP_SET_RCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_XCROP_RCROP_LSB, ATON_POOL_XCROP_RCROP_W, DATA) /** * Get the description of the RCROP field of XCROP register. * * \return the description of the RCROP field of XCROP register */ static inline const int8_t *ATON_POOL_XCROP_RCROP_GetdDesc(void) { return (const int8_t *)ATON_POOL_XCROP_RCROP_DESC; } /** * Read the content of the RCROP field of the XCROP register. * * \param[in] reg is the value of the XCROP register * * \return the content of the RCROP field belonging to XCROP register */ static inline uint32_t ATON_POOL_XCROP_Get_RCROP(uint32_t reg) { return ATON_POOL_XCROP_GET_RCROP(reg); } /** * Write the content of the RCROP field of the XCROP register. * * \param[in] reg is the value of the XCROP register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the RCROP field belonging to XCROP register */ static inline uint32_t ATON_POOL_XCROP_Set_RCROP(uint32_t reg, uint32_t data) { return ATON_POOL_XCROP_SET_RCROP(reg, data); } /* ******************************************************** YCROP register of one of the POOL Units ********************************************************* */ /** Offset of the YCROP register from the base address of the POOL Unit. */ #define ATON_POOL_YCROP_OFFSET 0x1cUL /** Reset value of the YCROP register of the POOL Unit. */ #define ATON_POOL_YCROP_DT \ (ATON_POOL_YCROP_TCROP_DT << ATON_POOL_YCROP_TCROP_LSB) | \ (ATON_POOL_YCROP_BCROP_DT << ATON_POOL_YCROP_BCROP_LSB) /** Description of the YCROP register. */ #define ATON_POOL_YCROP_DESC "top/bottom cropping dimensions" /** Address of the YCROP register of one of the POOL Units. */ #define ATON_POOL_YCROP_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_YCROP_OFFSET) /** Get the content of the YCROP register of one of the POOL Units. */ #define ATON_POOL_YCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_YCROP_ADDR(UNIT))) /** Set the content of the YCROP register of one of the POOL Units. */ #define ATON_POOL_YCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_YCROP_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of YCROP register. * * \return the description of YCROP register */ static inline const int8_t *ATON_POOL_YCROP_GetDesc(void) { return (const int8_t *)ATON_POOL_YCROP_DESC; } /** * Get the offset of the YCROP register. * * \return the offset of YCROP register */ static inline uint32_t ATON_POOL_YCROP_GetOffset(void) { return ATON_POOL_YCROP_OFFSET; } /** * Get the address of the YCROP register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the YCROP register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of YCROP register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_YCROP_GetAddr(uint32_t instance) { return ATON_POOL_YCROP_ADDR(instance); } /** * Read the content of the YCROP register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the YCROP register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of YCROP register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_YCROP_Get(uint32_t instance) { return ATON_POOL_YCROP_GET(instance); } /** * Write the content of the YCROP register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the YCROP register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_YCROP_Set(uint32_t instance, uint32_t data) { ATON_POOL_YCROP_SET(instance, data); } /* ----------------------------------------------------------- TCROP field of the YCROP register ------------------------------------------------------------ */ /** Description of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_TCROP_DESC "top crop index (zero-indexed) to be included in the crop" /** Offset of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_TCROP_LSB 0UL /** Size in bits of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_TCROP_W (12UL) /** Mask for retrieving the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_TCROP_MASK ATON_FIELD_MASK(0UL, 12UL) /** Reset value of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_TCROP_DT 0x0UL /** Access rights of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_TCROP_AC "RW" /** Check whether access to the TCROP field of the YCROP register is secured or not. */ #define ATON_POOL_YCROP_TCROP_S 0 /** Check whether access to the TCROP field of the YCROP register is privileged or not. */ #define ATON_POOL_YCROP_TCROP_P 0 /** Read the content of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_GET_TCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_YCROP_TCROP_LSB, ATON_POOL_YCROP_TCROP_W) /** Modify the content of the TCROP field of the YCROP register. */ #define ATON_POOL_YCROP_SET_TCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_YCROP_TCROP_LSB, ATON_POOL_YCROP_TCROP_W, DATA) /** * Get the description of the TCROP field of YCROP register. * * \return the description of the TCROP field of YCROP register */ static inline const int8_t *ATON_POOL_YCROP_TCROP_GetdDesc(void) { return (const int8_t *)ATON_POOL_YCROP_TCROP_DESC; } /** * Read the content of the TCROP field of the YCROP register. * * \param[in] reg is the value of the YCROP register * * \return the content of the TCROP field belonging to YCROP register */ static inline uint32_t ATON_POOL_YCROP_Get_TCROP(uint32_t reg) { return ATON_POOL_YCROP_GET_TCROP(reg); } /** * Write the content of the TCROP field of the YCROP register. * * \param[in] reg is the value of the YCROP register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the TCROP field belonging to YCROP register */ static inline uint32_t ATON_POOL_YCROP_Set_TCROP(uint32_t reg, uint32_t data) { return ATON_POOL_YCROP_SET_TCROP(reg, data); } /* ----------------------------------------------------------- BCROP field of the YCROP register ------------------------------------------------------------ */ /** Description of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_BCROP_DESC "bottom crop index (zero-indexed) to be included in the crop" /** Offset of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_BCROP_LSB 16UL /** Size in bits of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_BCROP_W (12UL) /** Mask for retrieving the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_BCROP_MASK ATON_FIELD_MASK(16UL, 12UL) /** Reset value of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_BCROP_DT 0x0UL /** Access rights of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_BCROP_AC "RW" /** Check whether access to the BCROP field of the YCROP register is secured or not. */ #define ATON_POOL_YCROP_BCROP_S 0 /** Check whether access to the BCROP field of the YCROP register is privileged or not. */ #define ATON_POOL_YCROP_BCROP_P 0 /** Read the content of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_GET_BCROP(REG) ATON_GET_FIELD(REG, ATON_POOL_YCROP_BCROP_LSB, ATON_POOL_YCROP_BCROP_W) /** Modify the content of the BCROP field of the YCROP register. */ #define ATON_POOL_YCROP_SET_BCROP(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_YCROP_BCROP_LSB, ATON_POOL_YCROP_BCROP_W, DATA) /** * Get the description of the BCROP field of YCROP register. * * \return the description of the BCROP field of YCROP register */ static inline const int8_t *ATON_POOL_YCROP_BCROP_GetdDesc(void) { return (const int8_t *)ATON_POOL_YCROP_BCROP_DESC; } /** * Read the content of the BCROP field of the YCROP register. * * \param[in] reg is the value of the YCROP register * * \return the content of the BCROP field belonging to YCROP register */ static inline uint32_t ATON_POOL_YCROP_Get_BCROP(uint32_t reg) { return ATON_POOL_YCROP_GET_BCROP(reg); } /** * Write the content of the BCROP field of the YCROP register. * * \param[in] reg is the value of the YCROP register * \param[in] data is 12-bit value that must be written to the field * * \return the new content of the BCROP field belonging to YCROP register */ static inline uint32_t ATON_POOL_YCROP_Set_BCROP(uint32_t reg, uint32_t data) { return ATON_POOL_YCROP_SET_BCROP(reg, data); } /* ******************************************************* RNDCTRL register of one of the POOL Units ******************************************************** */ /** Offset of the RNDCTRL register from the base address of the POOL Unit. */ #define ATON_POOL_RNDCTRL_OFFSET 0x20UL /** Reset value of the RNDCTRL register of the POOL Unit. */ #define ATON_POOL_RNDCTRL_DT \ (ATON_POOL_RNDCTRL_FOBYTES_DT << ATON_POOL_RNDCTRL_FOBYTES_LSB) | \ (ATON_POOL_RNDCTRL_FRNDMODE_DT << ATON_POOL_RNDCTRL_FRNDMODE_LSB) | \ (ATON_POOL_RNDCTRL_OBYTES_DT << ATON_POOL_RNDCTRL_OBYTES_LSB) | \ (ATON_POOL_RNDCTRL_ORNDMODE_DT << ATON_POOL_RNDCTRL_ORNDMODE_LSB) /** Description of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_DESC "input and output rounding control" /** Address of the RNDCTRL register of one of the POOL Units. */ #define ATON_POOL_RNDCTRL_ADDR(UNIT) (ATON_POOL_BASE(UNIT) + ATON_POOL_RNDCTRL_OFFSET) /** Get the content of the RNDCTRL register of one of the POOL Units. */ #define ATON_POOL_RNDCTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_POOL_RNDCTRL_ADDR(UNIT))) /** Set the content of the RNDCTRL register of one of the POOL Units. */ #define ATON_POOL_RNDCTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_POOL_RNDCTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of RNDCTRL register. * * \return the description of RNDCTRL register */ static inline const int8_t *ATON_POOL_RNDCTRL_GetDesc(void) { return (const int8_t *)ATON_POOL_RNDCTRL_DESC; } /** * Get the offset of the RNDCTRL register. * * \return the offset of RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_GetOffset(void) { return ATON_POOL_RNDCTRL_OFFSET; } /** * Get the address of the RNDCTRL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the RNDCTRL register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of RNDCTRL register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_RNDCTRL_GetAddr(uint32_t instance) { return ATON_POOL_RNDCTRL_ADDR(instance); } /** * Read the content of the RNDCTRL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the RNDCTRL register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of RNDCTRL register belonging to Unit having index \e instance among the POOL Units */ static inline uint32_t ATON_POOL_RNDCTRL_Get(uint32_t instance) { return ATON_POOL_RNDCTRL_GET(instance); } /** * Write the content of the RNDCTRL register. * * \param[in] instance is the index of the Unit (among the POOL Units) containing the RNDCTRL register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_POOL_RNDCTRL_Set(uint32_t instance, uint32_t data) { ATON_POOL_RNDCTRL_SET(instance, data); } /* --------------------------------------------------------- FOBYTES field of the RNDCTRL register ---------------------------------------------------------- */ /** Description of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FOBYTES_DESC "Number of output bytes to use for input feature data after rounding or saturation. Valid values are 1 or 2 bytes" /** Offset of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FOBYTES_LSB 0UL /** Size in bits of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FOBYTES_W (2UL) /** Mask for retrieving the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FOBYTES_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FOBYTES_DT 0x2UL /** Access rights of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FOBYTES_AC "RW" /** Check whether access to the FOBYTES field of the RNDCTRL register is secured or not. */ #define ATON_POOL_RNDCTRL_FOBYTES_S 0 /** Check whether access to the FOBYTES field of the RNDCTRL register is privileged or not. */ #define ATON_POOL_RNDCTRL_FOBYTES_P 0 /** Read the content of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_GET_FOBYTES(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_FOBYTES_LSB, ATON_POOL_RNDCTRL_FOBYTES_W) /** Modify the content of the FOBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_SET_FOBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_FOBYTES_LSB, ATON_POOL_RNDCTRL_FOBYTES_W, DATA) /** * Get the description of the FOBYTES field of RNDCTRL register. * * \return the description of the FOBYTES field of RNDCTRL register */ static inline const int8_t *ATON_POOL_RNDCTRL_FOBYTES_GetdDesc(void) { return (const int8_t *)ATON_POOL_RNDCTRL_FOBYTES_DESC; } /** * Read the content of the FOBYTES field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * * \return the content of the FOBYTES field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Get_FOBYTES(uint32_t reg) { return ATON_POOL_RNDCTRL_GET_FOBYTES(reg); } /** * Write the content of the FOBYTES field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FOBYTES field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Set_FOBYTES(uint32_t reg, uint32_t data) { return ATON_POOL_RNDCTRL_SET_FOBYTES(reg, data); } /* --------------------------------------------------------- FRNDMODE field of the RNDCTRL register --------------------------------------------------------- */ /** Description of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FRNDMODE_DESC "rounding mode to apply to input feature data. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FRNDMODE_LSB 2UL /** Size in bits of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FRNDMODE_W (2UL) /** Mask for retrieving the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FRNDMODE_MASK ATON_FIELD_MASK(2UL, 2UL) /** Reset value of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FRNDMODE_DT 0x0UL /** Access rights of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_FRNDMODE_AC "RW" /** Check whether access to the FRNDMODE field of the RNDCTRL register is secured or not. */ #define ATON_POOL_RNDCTRL_FRNDMODE_S 0 /** Check whether access to the FRNDMODE field of the RNDCTRL register is privileged or not. */ #define ATON_POOL_RNDCTRL_FRNDMODE_P 0 /** Read the content of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_GET_FRNDMODE(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_FRNDMODE_LSB, ATON_POOL_RNDCTRL_FRNDMODE_W) /** Modify the content of the FRNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_SET_FRNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_FRNDMODE_LSB, ATON_POOL_RNDCTRL_FRNDMODE_W, DATA) /** * Get the description of the FRNDMODE field of RNDCTRL register. * * \return the description of the FRNDMODE field of RNDCTRL register */ static inline const int8_t *ATON_POOL_RNDCTRL_FRNDMODE_GetdDesc(void) { return (const int8_t *)ATON_POOL_RNDCTRL_FRNDMODE_DESC; } /** * Read the content of the FRNDMODE field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * * \return the content of the FRNDMODE field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Get_FRNDMODE(uint32_t reg) { return ATON_POOL_RNDCTRL_GET_FRNDMODE(reg); } /** * Write the content of the FRNDMODE field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FRNDMODE field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Set_FRNDMODE(uint32_t reg, uint32_t data) { return ATON_POOL_RNDCTRL_SET_FRNDMODE(reg, data); } /* ---------------------------------------------------------- OBYTES field of the RNDCTRL register ---------------------------------------------------------- */ /** Description of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_OBYTES_DESC "Number of output bytes to use for final result after rounding or saturation. Valid values are 1 or 2 bytes" /** Offset of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_OBYTES_LSB 16UL /** Size in bits of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_OBYTES_W (2UL) /** Mask for retrieving the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_OBYTES_MASK ATON_FIELD_MASK(16UL, 2UL) /** Reset value of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_OBYTES_DT 0x2UL /** Access rights of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_OBYTES_AC "RW" /** Check whether access to the OBYTES field of the RNDCTRL register is secured or not. */ #define ATON_POOL_RNDCTRL_OBYTES_S 0 /** Check whether access to the OBYTES field of the RNDCTRL register is privileged or not. */ #define ATON_POOL_RNDCTRL_OBYTES_P 0 /** Read the content of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_OBYTES_LSB, ATON_POOL_RNDCTRL_OBYTES_W) /** Modify the content of the OBYTES field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_OBYTES_LSB, ATON_POOL_RNDCTRL_OBYTES_W, DATA) /** * Get the description of the OBYTES field of RNDCTRL register. * * \return the description of the OBYTES field of RNDCTRL register */ static inline const int8_t *ATON_POOL_RNDCTRL_OBYTES_GetdDesc(void) { return (const int8_t *)ATON_POOL_RNDCTRL_OBYTES_DESC; } /** * Read the content of the OBYTES field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * * \return the content of the OBYTES field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Get_OBYTES(uint32_t reg) { return ATON_POOL_RNDCTRL_GET_OBYTES(reg); } /** * Write the content of the OBYTES field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the OBYTES field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Set_OBYTES(uint32_t reg, uint32_t data) { return ATON_POOL_RNDCTRL_SET_OBYTES(reg, data); } /* --------------------------------------------------------- ORNDMODE field of the RNDCTRL register --------------------------------------------------------- */ /** Description of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_ORNDMODE_DESC "rounding mode to apply to output feature data. For more information see section: Rounding and Saturation. Valid values are 0 or 1. Bit 1 of this field is reserved for future use and ignored in this implementation" /** Offset of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_ORNDMODE_LSB 18UL /** Size in bits of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_ORNDMODE_W (2UL) /** Mask for retrieving the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_ORNDMODE_MASK ATON_FIELD_MASK(18UL, 2UL) /** Reset value of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_ORNDMODE_DT 0x0UL /** Access rights of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_ORNDMODE_AC "RW" /** Check whether access to the ORNDMODE field of the RNDCTRL register is secured or not. */ #define ATON_POOL_RNDCTRL_ORNDMODE_S 0 /** Check whether access to the ORNDMODE field of the RNDCTRL register is privileged or not. */ #define ATON_POOL_RNDCTRL_ORNDMODE_P 0 /** Read the content of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_POOL_RNDCTRL_ORNDMODE_LSB, ATON_POOL_RNDCTRL_ORNDMODE_W) /** Modify the content of the ORNDMODE field of the RNDCTRL register. */ #define ATON_POOL_RNDCTRL_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_POOL_RNDCTRL_ORNDMODE_LSB, ATON_POOL_RNDCTRL_ORNDMODE_W, DATA) /** * Get the description of the ORNDMODE field of RNDCTRL register. * * \return the description of the ORNDMODE field of RNDCTRL register */ static inline const int8_t *ATON_POOL_RNDCTRL_ORNDMODE_GetdDesc(void) { return (const int8_t *)ATON_POOL_RNDCTRL_ORNDMODE_DESC; } /** * Read the content of the ORNDMODE field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * * \return the content of the ORNDMODE field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Get_ORNDMODE(uint32_t reg) { return ATON_POOL_RNDCTRL_GET_ORNDMODE(reg); } /** * Write the content of the ORNDMODE field of the RNDCTRL register. * * \param[in] reg is the value of the RNDCTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ORNDMODE field belonging to RNDCTRL register */ static inline uint32_t ATON_POOL_RNDCTRL_Set_ORNDMODE(uint32_t reg, uint32_t data) { return ATON_POOL_RNDCTRL_SET_ORNDMODE(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* BUSIF Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of BUSIF Unit instances. */ #define ATON_BUSIF_NUM 2 /** * \name Structures, macros and functions of the BUSIF Units */ /*@{*/ /** * Registers of the BUSIF Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e PRIO1 register (Priority register 1). */ uint32_t PRIO1; /** \e PRIO2 register (Priority register 2). */ uint32_t PRIO2; /** \e ERR register (Error register). */ uint32_t ERR; /** \e KEY0_31_0 register (Encryption key 0 (bits 31:0)). */ uint32_t KEY0_31_0; /** \e KEY0_63_32 register (Encryption key 0 (bits 63:32)). */ uint32_t KEY0_63_32; /** \e KEY0_95_64 register (Encryption key 0 (bits 95:64)). */ uint32_t KEY0_95_64; /** \e KEY0_127_96 register (Encryption key 0 (bits 127:96)). */ uint32_t KEY0_127_96; /** \e KEY1_31_0 register (Encryption key 1 (bits 31:0)). */ uint32_t KEY1_31_0; /** \e KEY1_63_32 register (Encryption key 1 (bits 63:32)). */ uint32_t KEY1_63_32; /** \e KEY1_95_64 register (Encryption key 1 (bits 95:64)). */ uint32_t KEY1_95_64; /** \e KEY1_127_96 register (Encryption key 1 (bits 127:96)). */ uint32_t KEY1_127_96; } ATON_BUSIF_t; /** Return the pointer to one of the BUSIF Units. */ #define ATON_BUSIF(UNIT) ((ATON_BUSIF_t *)(intptr_t)ATON_BUSIF_BASE(UNIT)) /** Name of one of the BUSIF Units. */ #define ATON_BUSIF_NAME(UNIT) \ (((UNIT) == 0) ? "BUSIF0" : \ (((UNIT) == 1) ? "BUSIF1" : "")) /** Version of the BUSIF Units. */ #define ATON_BUSIF_VERSION "5.0" /** Description of one of the BUSIF Units. */ #define ATON_BUSIF_DESC(UNIT) \ (((UNIT) == 0) ? "Bus Interface 0" : \ (((UNIT) == 1) ? "Bus Interface 1" : "")) /** Base address of one of the BUSIF Units. */ #define ATON_BUSIF_BASE(UNIT) \ (ATON_BASE + 0x2000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the BUSIF Units. */ #define ATON_BUSIF_SIZE 0x1000UL /** * Get the name of one of the BUSIF Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) * * \return the name of Unit having index \e instance among the BUSIF Units */ static inline const int8_t *ATON_BUSIF_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"BUSIF0"; break; case 1: str = (const int8_t *)"BUSIF1"; break; default: break; } return str; } /** * Get the description of one of the BUSIF Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) * * \return the description of Unit having index \e instance among the BUSIF Units */ static inline const int8_t *ATON_BUSIF_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Bus Interface 0"; break; case 1: str = (const int8_t *)"Bus Interface 1"; break; default: break; } return str; } /** * Get the version of the BUSIF Units. * * \return the version of the BUSIF Units */ static inline const int8_t *ATON_BUSIF_GetVersion(void) { return (const int8_t *)ATON_BUSIF_VERSION; } /** * Get the base address of one of the BUSIF Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) * * \return the base address of Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_GetBase(uint32_t instance) { return ATON_BUSIF_BASE(instance); } /** * Get the size in bytes of the BUSIF Units. * * \return the size in bytes of the BUSIF Units */ static inline uint32_t ATON_BUSIF_GetSize(void) { return ATON_BUSIF_SIZE; } /* ******************************************************** CTRL register of one of the BUSIF Units ********************************************************* */ /** Offset of the CTRL register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the BUSIF Unit. */ #define ATON_BUSIF_CTRL_DT \ (ATON_BUSIF_CTRL_EN_DT << ATON_BUSIF_CTRL_EN_LSB) | \ (ATON_BUSIF_CTRL_CLR_DT << ATON_BUSIF_CTRL_CLR_LSB) | \ (ATON_BUSIF_CTRL_KEY0_VALID_DT << ATON_BUSIF_CTRL_KEY0_VALID_LSB) | \ (ATON_BUSIF_CTRL_KEY1_VALID_DT << ATON_BUSIF_CTRL_KEY1_VALID_LSB) | \ (ATON_BUSIF_CTRL_CONFCLR_DT << ATON_BUSIF_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_BUSIF_CTRL_DESC "Control register" /** Address of the CTRL register of one of the BUSIF Units. */ #define ATON_BUSIF_CTRL_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_CTRL_OFFSET) /** Get the content of the CTRL register of one of the BUSIF Units. */ #define ATON_BUSIF_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the BUSIF Units. */ #define ATON_BUSIF_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_BUSIF_CTRL_GetDesc(void) { return (const int8_t *)ATON_BUSIF_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_GetOffset(void) { return ATON_BUSIF_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the CTRL register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_CTRL_GetAddr(uint32_t instance) { return ATON_BUSIF_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_CTRL_Get(uint32_t instance) { return ATON_BUSIF_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the CTRL register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_CTRL_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_EN_DESC "Enable the Bus Interface" /** Offset of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_BUSIF_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_BUSIF_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_EN_LSB, ATON_BUSIF_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_BUSIF_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_CTRL_EN_LSB, ATON_BUSIF_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_BUSIF_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Get_EN(uint32_t reg) { return ATON_BUSIF_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_BUSIF_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_BUSIF_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_BUSIF_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_CLR_LSB, ATON_BUSIF_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_CTRL_CLR_LSB, ATON_BUSIF_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_BUSIF_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Get_CLR(uint32_t reg) { return ATON_BUSIF_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_BUSIF_CTRL_SET_CLR(reg, data); } /* --------------------------------------------------------- KEY0_VALID field of the CTRL register ---------------------------------------------------------- */ /** Description of the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY0_VALID_DESC "Reports key 0 validity" /** Offset of the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY0_VALID_LSB 16UL /** Size in bits of the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY0_VALID_W (1UL) /** Mask for retrieving the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY0_VALID_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY0_VALID_DT 0x0UL /** Access rights of the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY0_VALID_AC "R" /** Check whether access to the KEY0_VALID field of the CTRL register is secured or not. */ #define ATON_BUSIF_CTRL_KEY0_VALID_S 0 /** Check whether access to the KEY0_VALID field of the CTRL register is privileged or not. */ #define ATON_BUSIF_CTRL_KEY0_VALID_P 0 /** Read the content of the KEY0_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_GET_KEY0_VALID(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_KEY0_VALID_LSB, ATON_BUSIF_CTRL_KEY0_VALID_W) /** * Get the description of the KEY0_VALID field of CTRL register. * * \return the description of the KEY0_VALID field of CTRL register */ static inline const int8_t *ATON_BUSIF_CTRL_KEY0_VALID_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_CTRL_KEY0_VALID_DESC; } /** * Read the content of the KEY0_VALID field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the KEY0_VALID field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Get_KEY0_VALID(uint32_t reg) { return ATON_BUSIF_CTRL_GET_KEY0_VALID(reg); } /* --------------------------------------------------------- KEY1_VALID field of the CTRL register ---------------------------------------------------------- */ /** Description of the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY1_VALID_DESC "Reports key 1 validity" /** Offset of the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY1_VALID_LSB 17UL /** Size in bits of the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY1_VALID_W (1UL) /** Mask for retrieving the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY1_VALID_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY1_VALID_DT 0x0UL /** Access rights of the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_KEY1_VALID_AC "R" /** Check whether access to the KEY1_VALID field of the CTRL register is secured or not. */ #define ATON_BUSIF_CTRL_KEY1_VALID_S 0 /** Check whether access to the KEY1_VALID field of the CTRL register is privileged or not. */ #define ATON_BUSIF_CTRL_KEY1_VALID_P 0 /** Read the content of the KEY1_VALID field of the CTRL register. */ #define ATON_BUSIF_CTRL_GET_KEY1_VALID(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_KEY1_VALID_LSB, ATON_BUSIF_CTRL_KEY1_VALID_W) /** * Get the description of the KEY1_VALID field of CTRL register. * * \return the description of the KEY1_VALID field of CTRL register */ static inline const int8_t *ATON_BUSIF_CTRL_KEY1_VALID_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_CTRL_KEY1_VALID_DESC; } /** * Read the content of the KEY1_VALID field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the KEY1_VALID field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Get_KEY1_VALID(uint32_t reg) { return ATON_BUSIF_CTRL_GET_KEY1_VALID(reg); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_BUSIF_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_BUSIF_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_CTRL_CONFCLR_LSB, ATON_BUSIF_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_BUSIF_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_CTRL_CONFCLR_LSB, ATON_BUSIF_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_BUSIF_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_BUSIF_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_BUSIF_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_BUSIF_CTRL_SET_CONFCLR(reg, data); } /* ******************************************************* VERSION register of one of the BUSIF Units ******************************************************* */ /** Offset of the VERSION register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_VERSION_OFFSET 0x4UL /** * Get the reset value of the VERSION register of the BUSIF Unit. * * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') * * \return the reset value of the VERSION register of the BUSIF Unit */ #define ATON_BUSIF_VERSION_DT(UNIT) \ (((UNIT) == 0) ? ((ATON_BUSIF_VERSION_TYPE_DT << ATON_BUSIF_VERSION_TYPE_LSB) | \ (ATON_BUSIF_VERSION_MINOR_DT << ATON_BUSIF_VERSION_MINOR_LSB) | \ (ATON_BUSIF_VERSION_MAJOR_DT << ATON_BUSIF_VERSION_MAJOR_LSB) | \ (ATON_BUSIF_VERSION_PORTNR_DT(UNIT) << ATON_BUSIF_VERSION_PORTNR_LSB)) : \ (((UNIT) == 1) ? ((ATON_BUSIF_VERSION_TYPE_DT << ATON_BUSIF_VERSION_TYPE_LSB) | \ (ATON_BUSIF_VERSION_MINOR_DT << ATON_BUSIF_VERSION_MINOR_LSB) | \ (ATON_BUSIF_VERSION_MAJOR_DT << ATON_BUSIF_VERSION_MAJOR_LSB) | \ (ATON_BUSIF_VERSION_PORTNR_DT(UNIT) << ATON_BUSIF_VERSION_PORTNR_LSB)) : \ 0)) /** Description of the VERSION register. */ #define ATON_BUSIF_VERSION_DESC "Version register" /** Address of the VERSION register of one of the BUSIF Units. */ #define ATON_BUSIF_VERSION_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_VERSION_OFFSET) /** Get the content of the VERSION register of one of the BUSIF Units. */ #define ATON_BUSIF_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_BUSIF_VERSION_GetDesc(void) { return (const int8_t *)ATON_BUSIF_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_BUSIF_VERSION_GetOffset(void) { return ATON_BUSIF_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the VERSION register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_VERSION_GetAddr(uint32_t instance) { return ATON_BUSIF_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_VERSION_Get(uint32_t instance) { return ATON_BUSIF_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_TYPE_DT 0x1dUL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_BUSIF_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_BUSIF_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_BUSIF_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_TYPE_LSB, ATON_BUSIF_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_BUSIF_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_BUSIF_VERSION_Get_TYPE(uint32_t reg) { return ATON_BUSIF_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MINOR_DT 0x0UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_BUSIF_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_BUSIF_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_MINOR_LSB, ATON_BUSIF_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_BUSIF_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_BUSIF_VERSION_Get_MINOR(uint32_t reg) { return ATON_BUSIF_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MAJOR_DT 0x5UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_BUSIF_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_BUSIF_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_BUSIF_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_MAJOR_LSB, ATON_BUSIF_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_BUSIF_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_BUSIF_VERSION_Get_MAJOR(uint32_t reg) { return ATON_BUSIF_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- PORTNR field of the VERSION register ---------------------------------------------------------- */ /** Description of the PORTNR field of the VERSION register. */ #define ATON_BUSIF_VERSION_PORTNR_DESC "Number of stream engines bus muxed into AXI" /** Offset of the PORTNR field of the VERSION register. */ #define ATON_BUSIF_VERSION_PORTNR_LSB 16UL /** Size in bits of the PORTNR field of the VERSION register. */ #define ATON_BUSIF_VERSION_PORTNR_W (8UL) /** Mask for retrieving the PORTNR field of the VERSION register. */ #define ATON_BUSIF_VERSION_PORTNR_MASK ATON_FIELD_MASK(16UL, 8UL) /** * Get the reset value of the PORTNR field of the VERSION register. * * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') * * \return the reset value of the PORTNR field of the VERSION register */ #define ATON_BUSIF_VERSION_PORTNR_DT(UNIT) \ (((UNIT) == 0) ? 0x6 : \ (((UNIT) == 1) ? 0x6 : 0)) /** Access rights of the PORTNR field of the VERSION register. */ #define ATON_BUSIF_VERSION_PORTNR_AC "R" /** Check whether access to the PORTNR field of the VERSION register is secured or not. */ #define ATON_BUSIF_VERSION_PORTNR_S 0 /** Check whether access to the PORTNR field of the VERSION register is privileged or not. */ #define ATON_BUSIF_VERSION_PORTNR_P 0 /** Read the content of the PORTNR field of the VERSION register. */ #define ATON_BUSIF_VERSION_GET_PORTNR(REG) ATON_GET_FIELD(REG, ATON_BUSIF_VERSION_PORTNR_LSB, ATON_BUSIF_VERSION_PORTNR_W) /** * Get the description of the PORTNR field of VERSION register. * * \return the description of the PORTNR field of VERSION register */ static inline const int8_t *ATON_BUSIF_VERSION_PORTNR_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_VERSION_PORTNR_DESC; } /** * Read the content of the PORTNR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the PORTNR field belonging to VERSION register */ static inline uint32_t ATON_BUSIF_VERSION_Get_PORTNR(uint32_t reg) { return ATON_BUSIF_VERSION_GET_PORTNR(reg); } /* ******************************************************** PRIO1 register of one of the BUSIF Units ******************************************************** */ /** Offset of the PRIO1 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_PRIO1_OFFSET 0x8UL /** * Get the reset value of the PRIO1 register of the BUSIF Unit. * * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') * * \return the reset value of the PRIO1 register of the BUSIF Unit */ #define ATON_BUSIF_PRIO1_DT(UNIT) \ (((UNIT) == 0) ? ((ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(0)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(1)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(2)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(3)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(4)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(5))) : \ (((UNIT) == 1) ? ((ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(0)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(1)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(2)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(3)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(4)) | \ (ATON_BUSIF_PRIO1_BUSPORTN_DT << ATON_BUSIF_PRIO1_BUSPORTN_LSB(5))) : \ 0)) /** Description of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_DESC "Priority register 1" /** Address of the PRIO1 register of one of the BUSIF Units. */ #define ATON_BUSIF_PRIO1_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_PRIO1_OFFSET) /** Get the content of the PRIO1 register of one of the BUSIF Units. */ #define ATON_BUSIF_PRIO1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO1_ADDR(UNIT))) /** Set the content of the PRIO1 register of one of the BUSIF Units. */ #define ATON_BUSIF_PRIO1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of PRIO1 register. * * \return the description of PRIO1 register */ static inline const int8_t *ATON_BUSIF_PRIO1_GetDesc(void) { return (const int8_t *)ATON_BUSIF_PRIO1_DESC; } /** * Get the offset of the PRIO1 register. * * \return the offset of PRIO1 register */ static inline uint32_t ATON_BUSIF_PRIO1_GetOffset(void) { return ATON_BUSIF_PRIO1_OFFSET; } /** * Get the address of the PRIO1 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO1 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of PRIO1 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_PRIO1_GetAddr(uint32_t instance) { return ATON_BUSIF_PRIO1_ADDR(instance); } /** * Read the content of the PRIO1 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO1 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of PRIO1 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_PRIO1_Get(uint32_t instance) { return ATON_BUSIF_PRIO1_GET(instance); } /** * Write the content of the PRIO1 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO1 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_PRIO1_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_PRIO1_SET(instance, data); } /* ---------------------------------------------------------- BUSPORTN field of the PRIO1 register ---------------------------------------------------------- */ /** Description of one of the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_BUSPORTN_DESC "Priority mask 1 for busport N of the current instance (see the table for busports connections) [where N = ]" /** Number of BUSPORTN fields in the different instances of the PRIO1 register of the BUSIF Unit template. */ #define ATON_BUSIF_PRIO1_BUSPORTN_NUM(UNIT) \ (((UNIT) == 0) ? 6 : \ (((UNIT) == 1) ? 6 : 0)) /** Displacement in bits among the various BUSPORTN fields (due to template specialization). */ #define ATON_BUSIF_PRIO1_BUSPORTN_DISPL 1 /** Offset of one of the BUSPORTN fields of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_BUSPORTN_LSB(IDX) (0UL + (IDX) * ATON_BUSIF_PRIO1_BUSPORTN_DISPL) /** Size in bits of the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_BUSPORTN_W (1UL) /** Mask for retrieving the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_BUSPORTN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_BUSPORTN_DT 0x0UL /** Access rights of the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_BUSPORTN_AC "RW" /** Check whether access to the BUSPORTN field of the PRIO1 register is secured or not. */ #define ATON_BUSIF_PRIO1_BUSPORTN_S 0 /** Check whether access to the BUSPORTN field of the PRIO1 register is privileged or not. */ #define ATON_BUSIF_PRIO1_BUSPORTN_P 0 /** Read the content of one of the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_GET_BUSPORTN(REG, IDX) ATON_GET_FIELD(REG, ATON_BUSIF_PRIO1_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO1_BUSPORTN_W) /** Modify the content of one of the BUSPORTN field of the PRIO1 register. */ #define ATON_BUSIF_PRIO1_SET_BUSPORTN(REG, IDX, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_PRIO1_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO1_BUSPORTN_W, DATA) /** * Get the description of the BUSPORTN field of PRIO1 register. * * \return the description of the BUSPORTN field of PRIO1 register */ static inline const int8_t *ATON_BUSIF_PRIO1_BUSPORTN_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_PRIO1_BUSPORTN_DESC; } /** * Read the content of one of the BUSPORTN field of the PRIO1 register. * * \param[in] reg is the value of the PRIO1 register * * \return the content of the BUSPORTN field having index \e idx and belonging to PRIO1 register */ static inline uint32_t ATON_BUSIF_PRIO1_Get_BUSPORTN(uint32_t reg, uint32_t idx) { return ATON_BUSIF_PRIO1_GET_BUSPORTN(reg, idx); } /** * Write the content of one of the BUSPORTN field of the PRIO1 register. * * \param[in] reg is the value of the PRIO1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSPORTN field having index \e idx and belonging to PRIO1 register */ static inline uint32_t ATON_BUSIF_PRIO1_Set_BUSPORTN(uint32_t reg, uint32_t idx, uint32_t data) { return ATON_BUSIF_PRIO1_SET_BUSPORTN(reg, idx, data); } /* ******************************************************** PRIO2 register of one of the BUSIF Units ******************************************************** */ /** Offset of the PRIO2 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_PRIO2_OFFSET 0xcUL /** * Get the reset value of the PRIO2 register of the BUSIF Unit. * * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') * * \return the reset value of the PRIO2 register of the BUSIF Unit */ #define ATON_BUSIF_PRIO2_DT(UNIT) \ (((UNIT) == 0) ? ((ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(0)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(1)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(2)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(3)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(4)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(5))) : \ (((UNIT) == 1) ? ((ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(0)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(1)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(2)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(3)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(4)) | \ (ATON_BUSIF_PRIO2_BUSPORTN_DT << ATON_BUSIF_PRIO2_BUSPORTN_LSB(5))) : \ 0)) /** Description of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_DESC "Priority register 2" /** Address of the PRIO2 register of one of the BUSIF Units. */ #define ATON_BUSIF_PRIO2_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_PRIO2_OFFSET) /** Get the content of the PRIO2 register of one of the BUSIF Units. */ #define ATON_BUSIF_PRIO2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO2_ADDR(UNIT))) /** Set the content of the PRIO2 register of one of the BUSIF Units. */ #define ATON_BUSIF_PRIO2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_PRIO2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of PRIO2 register. * * \return the description of PRIO2 register */ static inline const int8_t *ATON_BUSIF_PRIO2_GetDesc(void) { return (const int8_t *)ATON_BUSIF_PRIO2_DESC; } /** * Get the offset of the PRIO2 register. * * \return the offset of PRIO2 register */ static inline uint32_t ATON_BUSIF_PRIO2_GetOffset(void) { return ATON_BUSIF_PRIO2_OFFSET; } /** * Get the address of the PRIO2 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO2 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of PRIO2 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_PRIO2_GetAddr(uint32_t instance) { return ATON_BUSIF_PRIO2_ADDR(instance); } /** * Read the content of the PRIO2 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO2 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of PRIO2 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_PRIO2_Get(uint32_t instance) { return ATON_BUSIF_PRIO2_GET(instance); } /** * Write the content of the PRIO2 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the PRIO2 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_PRIO2_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_PRIO2_SET(instance, data); } /* ---------------------------------------------------------- BUSPORTN field of the PRIO2 register ---------------------------------------------------------- */ /** Description of one of the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_BUSPORTN_DESC "Priority mask 2 for busport N of the current instance (see the table for busports connections) [where N = ]" /** Number of BUSPORTN fields in the different instances of the PRIO2 register of the BUSIF Unit template. */ #define ATON_BUSIF_PRIO2_BUSPORTN_NUM(UNIT) \ (((UNIT) == 0) ? 6 : \ (((UNIT) == 1) ? 6 : 0)) /** Displacement in bits among the various BUSPORTN fields (due to template specialization). */ #define ATON_BUSIF_PRIO2_BUSPORTN_DISPL 1 /** Offset of one of the BUSPORTN fields of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_BUSPORTN_LSB(IDX) (0UL + (IDX) * ATON_BUSIF_PRIO2_BUSPORTN_DISPL) /** Size in bits of the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_BUSPORTN_W (1UL) /** Mask for retrieving the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_BUSPORTN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_BUSPORTN_DT 0x0UL /** Access rights of the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_BUSPORTN_AC "RW" /** Check whether access to the BUSPORTN field of the PRIO2 register is secured or not. */ #define ATON_BUSIF_PRIO2_BUSPORTN_S 0 /** Check whether access to the BUSPORTN field of the PRIO2 register is privileged or not. */ #define ATON_BUSIF_PRIO2_BUSPORTN_P 0 /** Read the content of one of the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_GET_BUSPORTN(REG, IDX) ATON_GET_FIELD(REG, ATON_BUSIF_PRIO2_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO2_BUSPORTN_W) /** Modify the content of one of the BUSPORTN field of the PRIO2 register. */ #define ATON_BUSIF_PRIO2_SET_BUSPORTN(REG, IDX, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_PRIO2_BUSPORTN_LSB(IDX), ATON_BUSIF_PRIO2_BUSPORTN_W, DATA) /** * Get the description of the BUSPORTN field of PRIO2 register. * * \return the description of the BUSPORTN field of PRIO2 register */ static inline const int8_t *ATON_BUSIF_PRIO2_BUSPORTN_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_PRIO2_BUSPORTN_DESC; } /** * Read the content of one of the BUSPORTN field of the PRIO2 register. * * \param[in] reg is the value of the PRIO2 register * * \return the content of the BUSPORTN field having index \e idx and belonging to PRIO2 register */ static inline uint32_t ATON_BUSIF_PRIO2_Get_BUSPORTN(uint32_t reg, uint32_t idx) { return ATON_BUSIF_PRIO2_GET_BUSPORTN(reg, idx); } /** * Write the content of one of the BUSPORTN field of the PRIO2 register. * * \param[in] reg is the value of the PRIO2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSPORTN field having index \e idx and belonging to PRIO2 register */ static inline uint32_t ATON_BUSIF_PRIO2_Set_BUSPORTN(uint32_t reg, uint32_t idx, uint32_t data) { return ATON_BUSIF_PRIO2_SET_BUSPORTN(reg, idx, data); } /* ********************************************************* ERR register of one of the BUSIF Units ********************************************************* */ /** Offset of the ERR register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_ERR_OFFSET 0x10UL /** * Get the reset value of the ERR register of the BUSIF Unit. * * \param[in] UNIT is the instance index (0: 'BUSIF0', 1: 'BUSIF1') * * \return the reset value of the ERR register of the BUSIF Unit */ #define ATON_BUSIF_ERR_DT(UNIT) \ (((UNIT) == 0) ? ((ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(0)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(1)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(2)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(3)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(4)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(5))) : \ (((UNIT) == 1) ? ((ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(0)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(1)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(2)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(3)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(4)) | \ (ATON_BUSIF_ERR_BUSPORTN_DT << ATON_BUSIF_ERR_BUSPORTN_LSB(5))) : \ 0)) /** Description of the ERR register. */ #define ATON_BUSIF_ERR_DESC "Error register" /** Address of the ERR register of one of the BUSIF Units. */ #define ATON_BUSIF_ERR_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_ERR_OFFSET) /** Get the content of the ERR register of one of the BUSIF Units. */ #define ATON_BUSIF_ERR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_ERR_ADDR(UNIT))) /** Set the content of the ERR register of one of the BUSIF Units. */ #define ATON_BUSIF_ERR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_ERR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ERR register. * * \return the description of ERR register */ static inline const int8_t *ATON_BUSIF_ERR_GetDesc(void) { return (const int8_t *)ATON_BUSIF_ERR_DESC; } /** * Get the offset of the ERR register. * * \return the offset of ERR register */ static inline uint32_t ATON_BUSIF_ERR_GetOffset(void) { return ATON_BUSIF_ERR_OFFSET; } /** * Get the address of the ERR register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the ERR register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of ERR register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_ERR_GetAddr(uint32_t instance) { return ATON_BUSIF_ERR_ADDR(instance); } /** * Read the content of the ERR register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the ERR register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of ERR register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_ERR_Get(uint32_t instance) { return ATON_BUSIF_ERR_GET(instance); } /** * Write the content of the ERR register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the ERR register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_ERR_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_ERR_SET(instance, data); } /* ----------------------------------------------------------- BUSPORTN field of the ERR register ----------------------------------------------------------- */ /** Description of one of the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_BUSPORTN_DESC "Errors from AXI bus related to busport N of the current instance (see the table for busports connections). Writing 1 will clear the error (and the interrupt source), writing 0 has no effect. [where N = ]" /** Number of BUSPORTN fields in the different instances of the ERR register of the BUSIF Unit template. */ #define ATON_BUSIF_ERR_BUSPORTN_NUM(UNIT) \ (((UNIT) == 0) ? 6 : \ (((UNIT) == 1) ? 6 : 0)) /** Displacement in bits among the various BUSPORTN fields (due to template specialization). */ #define ATON_BUSIF_ERR_BUSPORTN_DISPL 1 /** Offset of one of the BUSPORTN fields of the ERR register. */ #define ATON_BUSIF_ERR_BUSPORTN_LSB(IDX) (0UL + (IDX) * ATON_BUSIF_ERR_BUSPORTN_DISPL) /** Size in bits of the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_BUSPORTN_W (1UL) /** Mask for retrieving the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_BUSPORTN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_BUSPORTN_DT 0x0UL /** Access rights of the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_BUSPORTN_AC "RW" /** Check whether access to the BUSPORTN field of the ERR register is secured or not. */ #define ATON_BUSIF_ERR_BUSPORTN_S 0 /** Check whether access to the BUSPORTN field of the ERR register is privileged or not. */ #define ATON_BUSIF_ERR_BUSPORTN_P 0 /** Read the content of one of the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_GET_BUSPORTN(REG, IDX) ATON_GET_FIELD(REG, ATON_BUSIF_ERR_BUSPORTN_LSB(IDX), ATON_BUSIF_ERR_BUSPORTN_W) /** Modify the content of one of the BUSPORTN field of the ERR register. */ #define ATON_BUSIF_ERR_SET_BUSPORTN(REG, IDX, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_ERR_BUSPORTN_LSB(IDX), ATON_BUSIF_ERR_BUSPORTN_W, DATA) /** * Get the description of the BUSPORTN field of ERR register. * * \return the description of the BUSPORTN field of ERR register */ static inline const int8_t *ATON_BUSIF_ERR_BUSPORTN_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_ERR_BUSPORTN_DESC; } /** * Read the content of one of the BUSPORTN field of the ERR register. * * \param[in] reg is the value of the ERR register * * \return the content of the BUSPORTN field having index \e idx and belonging to ERR register */ static inline uint32_t ATON_BUSIF_ERR_Get_BUSPORTN(uint32_t reg, uint32_t idx) { return ATON_BUSIF_ERR_GET_BUSPORTN(reg, idx); } /** * Write the content of one of the BUSPORTN field of the ERR register. * * \param[in] reg is the value of the ERR register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BUSPORTN field having index \e idx and belonging to ERR register */ static inline uint32_t ATON_BUSIF_ERR_Set_BUSPORTN(uint32_t reg, uint32_t idx, uint32_t data) { return ATON_BUSIF_ERR_SET_BUSPORTN(reg, idx, data); } /* ****************************************************** KEY0_31_0 register of one of the BUSIF Units ****************************************************** */ /** Offset of the KEY0_31_0 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_31_0_OFFSET 0x14UL /** Reset value of the KEY0_31_0 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_31_0_DT \ (ATON_BUSIF_KEY0_31_0_REG_DT << ATON_BUSIF_KEY0_31_0_REG_LSB) /** Description of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_DESC "Encryption key 0 (bits 31:0)" /** Address of the KEY0_31_0 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_31_0_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_31_0_OFFSET) /** Get the content of the KEY0_31_0 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_31_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_31_0_ADDR(UNIT))) /** Set the content of the KEY0_31_0 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_31_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_31_0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY0_31_0 register. * * \return the description of KEY0_31_0 register */ static inline const int8_t *ATON_BUSIF_KEY0_31_0_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_31_0_DESC; } /** * Get the offset of the KEY0_31_0 register. * * \return the offset of KEY0_31_0 register */ static inline uint32_t ATON_BUSIF_KEY0_31_0_GetOffset(void) { return ATON_BUSIF_KEY0_31_0_OFFSET; } /** * Get the address of the KEY0_31_0 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_31_0 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY0_31_0 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_31_0_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY0_31_0_ADDR(instance); } /** * Read the content of the KEY0_31_0 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_31_0 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY0_31_0 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_31_0_Get(uint32_t instance) { return ATON_BUSIF_KEY0_31_0_GET(instance); } /** * Write the content of the KEY0_31_0 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_31_0 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY0_31_0_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY0_31_0_SET(instance, data); } /* ---------------------------------------------------------- REG field of the KEY0_31_0 register ----------------------------------------------------------- */ /** Description of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_REG_DESC "Encryption key 0 (bits 31:0)" /** Offset of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_REG_LSB 0UL /** Size in bits of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_REG_W (32UL) /** Mask for retrieving the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_REG_DT 0x0UL /** Access rights of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_REG_AC "W" /** Check whether access to the REG field of the KEY0_31_0 register is secured or not. */ #define ATON_BUSIF_KEY0_31_0_REG_S 0 /** Check whether access to the REG field of the KEY0_31_0 register is privileged or not. */ #define ATON_BUSIF_KEY0_31_0_REG_P 0 /** Read the content of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_31_0_REG_LSB, ATON_BUSIF_KEY0_31_0_REG_W) /** Modify the content of the REG field of the KEY0_31_0 register. */ #define ATON_BUSIF_KEY0_31_0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_31_0_REG_LSB, ATON_BUSIF_KEY0_31_0_REG_W, DATA) /** * Get the description of the REG field of KEY0_31_0 register. * * \return the description of the REG field of KEY0_31_0 register */ static inline const int8_t *ATON_BUSIF_KEY0_31_0_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_31_0_REG_DESC; } /** * Read the content of the REG field of the KEY0_31_0 register. * * \param[in] reg is the value of the KEY0_31_0 register * * \return the content of the REG field belonging to KEY0_31_0 register */ static inline uint32_t ATON_BUSIF_KEY0_31_0_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY0_31_0_GET_REG(reg); } /** * Write the content of the REG field of the KEY0_31_0 register. * * \param[in] reg is the value of the KEY0_31_0 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY0_31_0 register */ static inline uint32_t ATON_BUSIF_KEY0_31_0_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY0_31_0_SET_REG(reg, data); } /* ***************************************************** KEY0_63_32 register of one of the BUSIF Units ****************************************************** */ /** Offset of the KEY0_63_32 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_63_32_OFFSET 0x18UL /** Reset value of the KEY0_63_32 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_63_32_DT \ (ATON_BUSIF_KEY0_63_32_REG_DT << ATON_BUSIF_KEY0_63_32_REG_LSB) /** Description of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_DESC "Encryption key 0 (bits 63:32)" /** Address of the KEY0_63_32 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_63_32_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_63_32_OFFSET) /** Get the content of the KEY0_63_32 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_63_32_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_63_32_ADDR(UNIT))) /** Set the content of the KEY0_63_32 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_63_32_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_63_32_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY0_63_32 register. * * \return the description of KEY0_63_32 register */ static inline const int8_t *ATON_BUSIF_KEY0_63_32_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_63_32_DESC; } /** * Get the offset of the KEY0_63_32 register. * * \return the offset of KEY0_63_32 register */ static inline uint32_t ATON_BUSIF_KEY0_63_32_GetOffset(void) { return ATON_BUSIF_KEY0_63_32_OFFSET; } /** * Get the address of the KEY0_63_32 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_63_32 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY0_63_32 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_63_32_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY0_63_32_ADDR(instance); } /** * Read the content of the KEY0_63_32 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_63_32 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY0_63_32 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_63_32_Get(uint32_t instance) { return ATON_BUSIF_KEY0_63_32_GET(instance); } /** * Write the content of the KEY0_63_32 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_63_32 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY0_63_32_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY0_63_32_SET(instance, data); } /* ---------------------------------------------------------- REG field of the KEY0_63_32 register ---------------------------------------------------------- */ /** Description of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_REG_DESC "Encryption key 0 (bits 63:32)" /** Offset of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_REG_LSB 0UL /** Size in bits of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_REG_W (32UL) /** Mask for retrieving the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_REG_DT 0x0UL /** Access rights of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_REG_AC "W" /** Check whether access to the REG field of the KEY0_63_32 register is secured or not. */ #define ATON_BUSIF_KEY0_63_32_REG_S 0 /** Check whether access to the REG field of the KEY0_63_32 register is privileged or not. */ #define ATON_BUSIF_KEY0_63_32_REG_P 0 /** Read the content of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_63_32_REG_LSB, ATON_BUSIF_KEY0_63_32_REG_W) /** Modify the content of the REG field of the KEY0_63_32 register. */ #define ATON_BUSIF_KEY0_63_32_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_63_32_REG_LSB, ATON_BUSIF_KEY0_63_32_REG_W, DATA) /** * Get the description of the REG field of KEY0_63_32 register. * * \return the description of the REG field of KEY0_63_32 register */ static inline const int8_t *ATON_BUSIF_KEY0_63_32_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_63_32_REG_DESC; } /** * Read the content of the REG field of the KEY0_63_32 register. * * \param[in] reg is the value of the KEY0_63_32 register * * \return the content of the REG field belonging to KEY0_63_32 register */ static inline uint32_t ATON_BUSIF_KEY0_63_32_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY0_63_32_GET_REG(reg); } /** * Write the content of the REG field of the KEY0_63_32 register. * * \param[in] reg is the value of the KEY0_63_32 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY0_63_32 register */ static inline uint32_t ATON_BUSIF_KEY0_63_32_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY0_63_32_SET_REG(reg, data); } /* ***************************************************** KEY0_95_64 register of one of the BUSIF Units ****************************************************** */ /** Offset of the KEY0_95_64 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_95_64_OFFSET 0x1cUL /** Reset value of the KEY0_95_64 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_95_64_DT \ (ATON_BUSIF_KEY0_95_64_REG_DT << ATON_BUSIF_KEY0_95_64_REG_LSB) /** Description of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_DESC "Encryption key 0 (bits 95:64)" /** Address of the KEY0_95_64 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_95_64_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_95_64_OFFSET) /** Get the content of the KEY0_95_64 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_95_64_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_95_64_ADDR(UNIT))) /** Set the content of the KEY0_95_64 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_95_64_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_95_64_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY0_95_64 register. * * \return the description of KEY0_95_64 register */ static inline const int8_t *ATON_BUSIF_KEY0_95_64_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_95_64_DESC; } /** * Get the offset of the KEY0_95_64 register. * * \return the offset of KEY0_95_64 register */ static inline uint32_t ATON_BUSIF_KEY0_95_64_GetOffset(void) { return ATON_BUSIF_KEY0_95_64_OFFSET; } /** * Get the address of the KEY0_95_64 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_95_64 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY0_95_64 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_95_64_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY0_95_64_ADDR(instance); } /** * Read the content of the KEY0_95_64 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_95_64 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY0_95_64 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_95_64_Get(uint32_t instance) { return ATON_BUSIF_KEY0_95_64_GET(instance); } /** * Write the content of the KEY0_95_64 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_95_64 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY0_95_64_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY0_95_64_SET(instance, data); } /* ---------------------------------------------------------- REG field of the KEY0_95_64 register ---------------------------------------------------------- */ /** Description of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_REG_DESC "Encryption key 0 (bits 95:64)" /** Offset of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_REG_LSB 0UL /** Size in bits of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_REG_W (32UL) /** Mask for retrieving the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_REG_DT 0x0UL /** Access rights of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_REG_AC "W" /** Check whether access to the REG field of the KEY0_95_64 register is secured or not. */ #define ATON_BUSIF_KEY0_95_64_REG_S 0 /** Check whether access to the REG field of the KEY0_95_64 register is privileged or not. */ #define ATON_BUSIF_KEY0_95_64_REG_P 0 /** Read the content of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_95_64_REG_LSB, ATON_BUSIF_KEY0_95_64_REG_W) /** Modify the content of the REG field of the KEY0_95_64 register. */ #define ATON_BUSIF_KEY0_95_64_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_95_64_REG_LSB, ATON_BUSIF_KEY0_95_64_REG_W, DATA) /** * Get the description of the REG field of KEY0_95_64 register. * * \return the description of the REG field of KEY0_95_64 register */ static inline const int8_t *ATON_BUSIF_KEY0_95_64_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_95_64_REG_DESC; } /** * Read the content of the REG field of the KEY0_95_64 register. * * \param[in] reg is the value of the KEY0_95_64 register * * \return the content of the REG field belonging to KEY0_95_64 register */ static inline uint32_t ATON_BUSIF_KEY0_95_64_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY0_95_64_GET_REG(reg); } /** * Write the content of the REG field of the KEY0_95_64 register. * * \param[in] reg is the value of the KEY0_95_64 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY0_95_64 register */ static inline uint32_t ATON_BUSIF_KEY0_95_64_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY0_95_64_SET_REG(reg, data); } /* ***************************************************** KEY0_127_96 register of one of the BUSIF Units ***************************************************** */ /** Offset of the KEY0_127_96 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_127_96_OFFSET 0x20UL /** Reset value of the KEY0_127_96 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY0_127_96_DT \ (ATON_BUSIF_KEY0_127_96_REG_DT << ATON_BUSIF_KEY0_127_96_REG_LSB) /** Description of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_DESC "Encryption key 0 (bits 127:96)" /** Address of the KEY0_127_96 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_127_96_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY0_127_96_OFFSET) /** Get the content of the KEY0_127_96 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_127_96_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_127_96_ADDR(UNIT))) /** Set the content of the KEY0_127_96 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY0_127_96_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY0_127_96_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY0_127_96 register. * * \return the description of KEY0_127_96 register */ static inline const int8_t *ATON_BUSIF_KEY0_127_96_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_127_96_DESC; } /** * Get the offset of the KEY0_127_96 register. * * \return the offset of KEY0_127_96 register */ static inline uint32_t ATON_BUSIF_KEY0_127_96_GetOffset(void) { return ATON_BUSIF_KEY0_127_96_OFFSET; } /** * Get the address of the KEY0_127_96 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_127_96 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY0_127_96 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_127_96_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY0_127_96_ADDR(instance); } /** * Read the content of the KEY0_127_96 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_127_96 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY0_127_96 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY0_127_96_Get(uint32_t instance) { return ATON_BUSIF_KEY0_127_96_GET(instance); } /** * Write the content of the KEY0_127_96 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY0_127_96 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY0_127_96_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY0_127_96_SET(instance, data); } /* --------------------------------------------------------- REG field of the KEY0_127_96 register ---------------------------------------------------------- */ /** Description of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_REG_DESC "Encryption key 0 (bits 127:96)" /** Offset of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_REG_LSB 0UL /** Size in bits of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_REG_W (32UL) /** Mask for retrieving the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_REG_DT 0x0UL /** Access rights of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_REG_AC "W" /** Check whether access to the REG field of the KEY0_127_96 register is secured or not. */ #define ATON_BUSIF_KEY0_127_96_REG_S 0 /** Check whether access to the REG field of the KEY0_127_96 register is privileged or not. */ #define ATON_BUSIF_KEY0_127_96_REG_P 0 /** Read the content of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY0_127_96_REG_LSB, ATON_BUSIF_KEY0_127_96_REG_W) /** Modify the content of the REG field of the KEY0_127_96 register. */ #define ATON_BUSIF_KEY0_127_96_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY0_127_96_REG_LSB, ATON_BUSIF_KEY0_127_96_REG_W, DATA) /** * Get the description of the REG field of KEY0_127_96 register. * * \return the description of the REG field of KEY0_127_96 register */ static inline const int8_t *ATON_BUSIF_KEY0_127_96_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY0_127_96_REG_DESC; } /** * Read the content of the REG field of the KEY0_127_96 register. * * \param[in] reg is the value of the KEY0_127_96 register * * \return the content of the REG field belonging to KEY0_127_96 register */ static inline uint32_t ATON_BUSIF_KEY0_127_96_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY0_127_96_GET_REG(reg); } /** * Write the content of the REG field of the KEY0_127_96 register. * * \param[in] reg is the value of the KEY0_127_96 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY0_127_96 register */ static inline uint32_t ATON_BUSIF_KEY0_127_96_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY0_127_96_SET_REG(reg, data); } /* ****************************************************** KEY1_31_0 register of one of the BUSIF Units ****************************************************** */ /** Offset of the KEY1_31_0 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_31_0_OFFSET 0x24UL /** Reset value of the KEY1_31_0 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_31_0_DT \ (ATON_BUSIF_KEY1_31_0_REG_DT << ATON_BUSIF_KEY1_31_0_REG_LSB) /** Description of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_DESC "Encryption key 1 (bits 31:0)" /** Address of the KEY1_31_0 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_31_0_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_31_0_OFFSET) /** Get the content of the KEY1_31_0 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_31_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_31_0_ADDR(UNIT))) /** Set the content of the KEY1_31_0 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_31_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_31_0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY1_31_0 register. * * \return the description of KEY1_31_0 register */ static inline const int8_t *ATON_BUSIF_KEY1_31_0_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_31_0_DESC; } /** * Get the offset of the KEY1_31_0 register. * * \return the offset of KEY1_31_0 register */ static inline uint32_t ATON_BUSIF_KEY1_31_0_GetOffset(void) { return ATON_BUSIF_KEY1_31_0_OFFSET; } /** * Get the address of the KEY1_31_0 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_31_0 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY1_31_0 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_31_0_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY1_31_0_ADDR(instance); } /** * Read the content of the KEY1_31_0 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_31_0 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY1_31_0 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_31_0_Get(uint32_t instance) { return ATON_BUSIF_KEY1_31_0_GET(instance); } /** * Write the content of the KEY1_31_0 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_31_0 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY1_31_0_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY1_31_0_SET(instance, data); } /* ---------------------------------------------------------- REG field of the KEY1_31_0 register ----------------------------------------------------------- */ /** Description of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_REG_DESC "Encryption key 1 (bits 31:0)" /** Offset of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_REG_LSB 0UL /** Size in bits of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_REG_W (32UL) /** Mask for retrieving the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_REG_DT 0x0UL /** Access rights of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_REG_AC "W" /** Check whether access to the REG field of the KEY1_31_0 register is secured or not. */ #define ATON_BUSIF_KEY1_31_0_REG_S 0 /** Check whether access to the REG field of the KEY1_31_0 register is privileged or not. */ #define ATON_BUSIF_KEY1_31_0_REG_P 0 /** Read the content of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_31_0_REG_LSB, ATON_BUSIF_KEY1_31_0_REG_W) /** Modify the content of the REG field of the KEY1_31_0 register. */ #define ATON_BUSIF_KEY1_31_0_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_31_0_REG_LSB, ATON_BUSIF_KEY1_31_0_REG_W, DATA) /** * Get the description of the REG field of KEY1_31_0 register. * * \return the description of the REG field of KEY1_31_0 register */ static inline const int8_t *ATON_BUSIF_KEY1_31_0_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_31_0_REG_DESC; } /** * Read the content of the REG field of the KEY1_31_0 register. * * \param[in] reg is the value of the KEY1_31_0 register * * \return the content of the REG field belonging to KEY1_31_0 register */ static inline uint32_t ATON_BUSIF_KEY1_31_0_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY1_31_0_GET_REG(reg); } /** * Write the content of the REG field of the KEY1_31_0 register. * * \param[in] reg is the value of the KEY1_31_0 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY1_31_0 register */ static inline uint32_t ATON_BUSIF_KEY1_31_0_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY1_31_0_SET_REG(reg, data); } /* ***************************************************** KEY1_63_32 register of one of the BUSIF Units ****************************************************** */ /** Offset of the KEY1_63_32 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_63_32_OFFSET 0x28UL /** Reset value of the KEY1_63_32 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_63_32_DT \ (ATON_BUSIF_KEY1_63_32_REG_DT << ATON_BUSIF_KEY1_63_32_REG_LSB) /** Description of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_DESC "Encryption key 1 (bits 63:32)" /** Address of the KEY1_63_32 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_63_32_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_63_32_OFFSET) /** Get the content of the KEY1_63_32 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_63_32_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_63_32_ADDR(UNIT))) /** Set the content of the KEY1_63_32 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_63_32_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_63_32_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY1_63_32 register. * * \return the description of KEY1_63_32 register */ static inline const int8_t *ATON_BUSIF_KEY1_63_32_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_63_32_DESC; } /** * Get the offset of the KEY1_63_32 register. * * \return the offset of KEY1_63_32 register */ static inline uint32_t ATON_BUSIF_KEY1_63_32_GetOffset(void) { return ATON_BUSIF_KEY1_63_32_OFFSET; } /** * Get the address of the KEY1_63_32 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_63_32 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY1_63_32 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_63_32_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY1_63_32_ADDR(instance); } /** * Read the content of the KEY1_63_32 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_63_32 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY1_63_32 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_63_32_Get(uint32_t instance) { return ATON_BUSIF_KEY1_63_32_GET(instance); } /** * Write the content of the KEY1_63_32 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_63_32 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY1_63_32_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY1_63_32_SET(instance, data); } /* ---------------------------------------------------------- REG field of the KEY1_63_32 register ---------------------------------------------------------- */ /** Description of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_REG_DESC "Encryption key 1 (bits 63:32)" /** Offset of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_REG_LSB 0UL /** Size in bits of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_REG_W (32UL) /** Mask for retrieving the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_REG_DT 0x0UL /** Access rights of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_REG_AC "W" /** Check whether access to the REG field of the KEY1_63_32 register is secured or not. */ #define ATON_BUSIF_KEY1_63_32_REG_S 0 /** Check whether access to the REG field of the KEY1_63_32 register is privileged or not. */ #define ATON_BUSIF_KEY1_63_32_REG_P 0 /** Read the content of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_63_32_REG_LSB, ATON_BUSIF_KEY1_63_32_REG_W) /** Modify the content of the REG field of the KEY1_63_32 register. */ #define ATON_BUSIF_KEY1_63_32_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_63_32_REG_LSB, ATON_BUSIF_KEY1_63_32_REG_W, DATA) /** * Get the description of the REG field of KEY1_63_32 register. * * \return the description of the REG field of KEY1_63_32 register */ static inline const int8_t *ATON_BUSIF_KEY1_63_32_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_63_32_REG_DESC; } /** * Read the content of the REG field of the KEY1_63_32 register. * * \param[in] reg is the value of the KEY1_63_32 register * * \return the content of the REG field belonging to KEY1_63_32 register */ static inline uint32_t ATON_BUSIF_KEY1_63_32_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY1_63_32_GET_REG(reg); } /** * Write the content of the REG field of the KEY1_63_32 register. * * \param[in] reg is the value of the KEY1_63_32 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY1_63_32 register */ static inline uint32_t ATON_BUSIF_KEY1_63_32_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY1_63_32_SET_REG(reg, data); } /* ***************************************************** KEY1_95_64 register of one of the BUSIF Units ****************************************************** */ /** Offset of the KEY1_95_64 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_95_64_OFFSET 0x2cUL /** Reset value of the KEY1_95_64 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_95_64_DT \ (ATON_BUSIF_KEY1_95_64_REG_DT << ATON_BUSIF_KEY1_95_64_REG_LSB) /** Description of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_DESC "Encryption key 1 (bits 95:64)" /** Address of the KEY1_95_64 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_95_64_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_95_64_OFFSET) /** Get the content of the KEY1_95_64 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_95_64_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_95_64_ADDR(UNIT))) /** Set the content of the KEY1_95_64 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_95_64_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_95_64_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY1_95_64 register. * * \return the description of KEY1_95_64 register */ static inline const int8_t *ATON_BUSIF_KEY1_95_64_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_95_64_DESC; } /** * Get the offset of the KEY1_95_64 register. * * \return the offset of KEY1_95_64 register */ static inline uint32_t ATON_BUSIF_KEY1_95_64_GetOffset(void) { return ATON_BUSIF_KEY1_95_64_OFFSET; } /** * Get the address of the KEY1_95_64 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_95_64 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY1_95_64 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_95_64_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY1_95_64_ADDR(instance); } /** * Read the content of the KEY1_95_64 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_95_64 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY1_95_64 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_95_64_Get(uint32_t instance) { return ATON_BUSIF_KEY1_95_64_GET(instance); } /** * Write the content of the KEY1_95_64 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_95_64 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY1_95_64_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY1_95_64_SET(instance, data); } /* ---------------------------------------------------------- REG field of the KEY1_95_64 register ---------------------------------------------------------- */ /** Description of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_REG_DESC "Encryption key 1 (bits 95:64)" /** Offset of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_REG_LSB 0UL /** Size in bits of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_REG_W (32UL) /** Mask for retrieving the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_REG_DT 0x0UL /** Access rights of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_REG_AC "W" /** Check whether access to the REG field of the KEY1_95_64 register is secured or not. */ #define ATON_BUSIF_KEY1_95_64_REG_S 0 /** Check whether access to the REG field of the KEY1_95_64 register is privileged or not. */ #define ATON_BUSIF_KEY1_95_64_REG_P 0 /** Read the content of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_95_64_REG_LSB, ATON_BUSIF_KEY1_95_64_REG_W) /** Modify the content of the REG field of the KEY1_95_64 register. */ #define ATON_BUSIF_KEY1_95_64_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_95_64_REG_LSB, ATON_BUSIF_KEY1_95_64_REG_W, DATA) /** * Get the description of the REG field of KEY1_95_64 register. * * \return the description of the REG field of KEY1_95_64 register */ static inline const int8_t *ATON_BUSIF_KEY1_95_64_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_95_64_REG_DESC; } /** * Read the content of the REG field of the KEY1_95_64 register. * * \param[in] reg is the value of the KEY1_95_64 register * * \return the content of the REG field belonging to KEY1_95_64 register */ static inline uint32_t ATON_BUSIF_KEY1_95_64_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY1_95_64_GET_REG(reg); } /** * Write the content of the REG field of the KEY1_95_64 register. * * \param[in] reg is the value of the KEY1_95_64 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY1_95_64 register */ static inline uint32_t ATON_BUSIF_KEY1_95_64_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY1_95_64_SET_REG(reg, data); } /* ***************************************************** KEY1_127_96 register of one of the BUSIF Units ***************************************************** */ /** Offset of the KEY1_127_96 register from the base address of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_127_96_OFFSET 0x30UL /** Reset value of the KEY1_127_96 register of the BUSIF Unit. */ #define ATON_BUSIF_KEY1_127_96_DT \ (ATON_BUSIF_KEY1_127_96_REG_DT << ATON_BUSIF_KEY1_127_96_REG_LSB) /** Description of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_DESC "Encryption key 1 (bits 127:96)" /** Address of the KEY1_127_96 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_127_96_ADDR(UNIT) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY1_127_96_OFFSET) /** Get the content of the KEY1_127_96 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_127_96_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_127_96_ADDR(UNIT))) /** Set the content of the KEY1_127_96 register of one of the BUSIF Units. */ #define ATON_BUSIF_KEY1_127_96_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_BUSIF_KEY1_127_96_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KEY1_127_96 register. * * \return the description of KEY1_127_96 register */ static inline const int8_t *ATON_BUSIF_KEY1_127_96_GetDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_127_96_DESC; } /** * Get the offset of the KEY1_127_96 register. * * \return the offset of KEY1_127_96 register */ static inline uint32_t ATON_BUSIF_KEY1_127_96_GetOffset(void) { return ATON_BUSIF_KEY1_127_96_OFFSET; } /** * Get the address of the KEY1_127_96 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_127_96 register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of KEY1_127_96 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_127_96_GetAddr(uint32_t instance) { return ATON_BUSIF_KEY1_127_96_ADDR(instance); } /** * Read the content of the KEY1_127_96 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_127_96 register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of KEY1_127_96 register belonging to Unit having index \e instance among the BUSIF Units */ static inline uint32_t ATON_BUSIF_KEY1_127_96_Get(uint32_t instance) { return ATON_BUSIF_KEY1_127_96_GET(instance); } /** * Write the content of the KEY1_127_96 register. * * \param[in] instance is the index of the Unit (among the BUSIF Units) containing the KEY1_127_96 register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_BUSIF_KEY1_127_96_Set(uint32_t instance, uint32_t data) { ATON_BUSIF_KEY1_127_96_SET(instance, data); } /* --------------------------------------------------------- REG field of the KEY1_127_96 register ---------------------------------------------------------- */ /** Description of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_REG_DESC "Encryption key 1 (bits 127:96)" /** Offset of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_REG_LSB 0UL /** Size in bits of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_REG_W (32UL) /** Mask for retrieving the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_REG_DT 0x0UL /** Access rights of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_REG_AC "W" /** Check whether access to the REG field of the KEY1_127_96 register is secured or not. */ #define ATON_BUSIF_KEY1_127_96_REG_S 0 /** Check whether access to the REG field of the KEY1_127_96 register is privileged or not. */ #define ATON_BUSIF_KEY1_127_96_REG_P 0 /** Read the content of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_GET_REG(REG) ATON_GET_FIELD(REG, ATON_BUSIF_KEY1_127_96_REG_LSB, ATON_BUSIF_KEY1_127_96_REG_W) /** Modify the content of the REG field of the KEY1_127_96 register. */ #define ATON_BUSIF_KEY1_127_96_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_BUSIF_KEY1_127_96_REG_LSB, ATON_BUSIF_KEY1_127_96_REG_W, DATA) /** * Get the description of the REG field of KEY1_127_96 register. * * \return the description of the REG field of KEY1_127_96 register */ static inline const int8_t *ATON_BUSIF_KEY1_127_96_REG_GetdDesc(void) { return (const int8_t *)ATON_BUSIF_KEY1_127_96_REG_DESC; } /** * Read the content of the REG field of the KEY1_127_96 register. * * \param[in] reg is the value of the KEY1_127_96 register * * \return the content of the REG field belonging to KEY1_127_96 register */ static inline uint32_t ATON_BUSIF_KEY1_127_96_Get_REG(uint32_t reg) { return ATON_BUSIF_KEY1_127_96_GET_REG(reg); } /** * Write the content of the REG field of the KEY1_127_96 register. * * \param[in] reg is the value of the KEY1_127_96 register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to KEY1_127_96 register */ static inline uint32_t ATON_BUSIF_KEY1_127_96_Set_REG(uint32_t reg, uint32_t data) { return ATON_BUSIF_KEY1_127_96_SET_REG(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* STRENG Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of STRENG Unit instances. */ #define ATON_STRENG_NUM 10 /** * \name Structures, macros and functions of the STRENG Units */ /*@{*/ /** * Registers of the STRENG Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e ADDR register (Source/destination address). */ uint32_t ADDR; /** \e FSIZE register (Frame size). */ uint32_t FSIZE; /** \e DEPTH register (Depth for batch mode). */ uint32_t DEPTH; /** \e STRD register (Stride). */ uint32_t STRD; /** \e FOFFSET register (Frame offset within frame repetition loop). */ uint32_t FOFFSET; /** \e FRAME_RPT register (Number of frames to loop on). */ uint32_t FRAME_RPT; /** \e FRPTOFF register (Frame offset between frame repetition loops). */ uint32_t FRPTOFF; /** \e POS register (Position). */ uint32_t POS; /** \e EVENT register (Event). */ uint32_t EVENT; /** \e STOPTAG register (RAW file stop tag). */ uint32_t STOPTAG; /** \e LIMITEN register (Limiter enables). */ uint32_t LIMITEN; /** \e LIMIT register (Limiter). */ uint32_t LIMIT; /** \e LIMITADDR register (Limiter address). */ uint32_t LIMITADDR; /** \e IRQ register (Events and interrupt enable). */ uint32_t IRQ; /** \e ENCR_LSB register (Encryption ID LSB (RO when CTRL.RUNNING)). */ uint32_t ENCR_LSB; /** \e ENCR_MSB register (Encryption ID MSB (RO when CTRL.RUNNING)). */ uint32_t ENCR_MSB; /** \e CID_CACHE register (Compartment ID / Cache register (RO when CTRL.RUNNING)). */ uint32_t CID_CACHE; /** \e EXTSYNC register (External triggers 1st control register (RO when CTRL.RUNNING)). */ uint32_t EXTSYNC; /** \e EXTSYNC2 register (External triggers 2st control register (RO when CTRL.RUNNING)). */ uint32_t EXTSYNC2; /** \e DESCRADDR register (Descriptor fetch address). */ uint32_t DESCRADDR; /** \e LASTADDR register (Address of the last transaction on master bus IF). */ uint32_t LASTADDR; /** \e DEPTHCNT register (Current processed sub-pixel (1 to depth size)). */ uint32_t DEPTHCNT; /** \e PIXCNT register (Current processed pixel (1 to line width)). */ uint32_t PIXCNT; /** \e LINECNT register (Current processed line (1 to frame height)). */ uint32_t LINECNT; /** \e FCNT register (Frame counter). */ uint32_t FCNT; } ATON_STRENG_t; /** Return the pointer to one of the STRENG Units. */ #define ATON_STRENG(UNIT) ((ATON_STRENG_t *)(intptr_t)ATON_STRENG_BASE(UNIT)) /** Name of one of the STRENG Units. */ #define ATON_STRENG_NAME(UNIT) \ (((UNIT) == 0) ? "STRENG0" : \ (((UNIT) == 1) ? "STRENG1" : \ (((UNIT) == 2) ? "STRENG2" : \ (((UNIT) == 3) ? "STRENG3" : \ (((UNIT) == 4) ? "STRENG4" : \ (((UNIT) == 5) ? "STRENG5" : \ (((UNIT) == 6) ? "STRENG6" : \ (((UNIT) == 7) ? "STRENG7" : \ (((UNIT) == 8) ? "STRENG8" : \ (((UNIT) == 9) ? "STRENG9" : "")))))))))) /** Version of the STRENG Units. */ #define ATON_STRENG_VERSION "5.0" /** Description of one of the STRENG Units. */ #define ATON_STRENG_DESC(UNIT) \ (((UNIT) == 0) ? "Stream Engine 0" : \ (((UNIT) == 1) ? "Stream Engine 1" : \ (((UNIT) == 2) ? "Stream Engine 2" : \ (((UNIT) == 3) ? "Stream Engine 3" : \ (((UNIT) == 4) ? "Stream Engine 4" : \ (((UNIT) == 5) ? "Stream Engine 5" : \ (((UNIT) == 6) ? "Stream Engine 6" : \ (((UNIT) == 7) ? "Stream Engine 7" : \ (((UNIT) == 8) ? "Stream Engine 8" : \ (((UNIT) == 9) ? "Stream Engine 9" : "")))))))))) /** Base address of one of the STRENG Units. */ #define ATON_STRENG_BASE(UNIT) \ (ATON_BASE + 0x5000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the STRENG Units. */ #define ATON_STRENG_SIZE 0x1000UL /** * Get the name of one of the STRENG Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 10<\em>) * * \return the name of Unit having index \e instance among the STRENG Units */ static inline const int8_t *ATON_STRENG_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"STRENG0"; break; case 1: str = (const int8_t *)"STRENG1"; break; case 2: str = (const int8_t *)"STRENG2"; break; case 3: str = (const int8_t *)"STRENG3"; break; case 4: str = (const int8_t *)"STRENG4"; break; case 5: str = (const int8_t *)"STRENG5"; break; case 6: str = (const int8_t *)"STRENG6"; break; case 7: str = (const int8_t *)"STRENG7"; break; case 8: str = (const int8_t *)"STRENG8"; break; case 9: str = (const int8_t *)"STRENG9"; break; default: break; } return str; } /** * Get the description of one of the STRENG Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 10<\em>) * * \return the description of Unit having index \e instance among the STRENG Units */ static inline const int8_t *ATON_STRENG_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Stream Engine 0"; break; case 1: str = (const int8_t *)"Stream Engine 1"; break; case 2: str = (const int8_t *)"Stream Engine 2"; break; case 3: str = (const int8_t *)"Stream Engine 3"; break; case 4: str = (const int8_t *)"Stream Engine 4"; break; case 5: str = (const int8_t *)"Stream Engine 5"; break; case 6: str = (const int8_t *)"Stream Engine 6"; break; case 7: str = (const int8_t *)"Stream Engine 7"; break; case 8: str = (const int8_t *)"Stream Engine 8"; break; case 9: str = (const int8_t *)"Stream Engine 9"; break; default: break; } return str; } /** * Get the version of the STRENG Units. * * \return the version of the STRENG Units */ static inline const int8_t *ATON_STRENG_GetVersion(void) { return (const int8_t *)ATON_STRENG_VERSION; } /** * Get the base address of one of the STRENG Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 10<\em>) * * \return the base address of Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_GetBase(uint32_t instance) { return ATON_STRENG_BASE(instance); } /** * Get the size in bytes of the STRENG Units. * * \return the size in bytes of the STRENG Units */ static inline uint32_t ATON_STRENG_GetSize(void) { return ATON_STRENG_SIZE; } /* ******************************************************** CTRL register of one of the STRENG Units ******************************************************** */ /** Offset of the CTRL register from the base address of the STRENG Unit. */ #define ATON_STRENG_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the STRENG Unit. */ #define ATON_STRENG_CTRL_DT \ (ATON_STRENG_CTRL_EN_DT << ATON_STRENG_CTRL_EN_LSB) | \ (ATON_STRENG_CTRL_CLR_DT << ATON_STRENG_CTRL_CLR_LSB) | \ (ATON_STRENG_CTRL_SINGLE_DT << ATON_STRENG_CTRL_SINGLE_LSB) | \ (ATON_STRENG_CTRL_DIR_DT << ATON_STRENG_CTRL_DIR_LSB) | \ (ATON_STRENG_CTRL_NOINC_DT << ATON_STRENG_CTRL_NOINC_LSB) | \ (ATON_STRENG_CTRL_ISTART_DT << ATON_STRENG_CTRL_ISTART_LSB) | \ (ATON_STRENG_CTRL_SUBSAMPLE_DT << ATON_STRENG_CTRL_SUBSAMPLE_LSB) | \ (ATON_STRENG_CTRL_CONT_DT << ATON_STRENG_CTRL_CONT_LSB) | \ (ATON_STRENG_CTRL_RAW_DT << ATON_STRENG_CTRL_RAW_LSB) | \ (ATON_STRENG_CTRL_RAW_OUT_DT << ATON_STRENG_CTRL_RAW_OUT_LSB) | \ (ATON_STRENG_CTRL_DESCR_DT << ATON_STRENG_CTRL_DESCR_LSB) | \ (ATON_STRENG_CTRL_NOBLK_DT << ATON_STRENG_CTRL_NOBLK_LSB) | \ (ATON_STRENG_CTRL_ROUND_DT << ATON_STRENG_CTRL_ROUND_LSB) | \ (ATON_STRENG_CTRL_BEFORCE_DT << ATON_STRENG_CTRL_BEFORCE_LSB) | \ (ATON_STRENG_CTRL_LSBMODE_DT << ATON_STRENG_CTRL_LSBMODE_LSB) | \ (ATON_STRENG_CTRL_SIGNEXT_DT << ATON_STRENG_CTRL_SIGNEXT_LSB) | \ (ATON_STRENG_CTRL_SIZE0_DT << ATON_STRENG_CTRL_SIZE0_LSB) | \ (ATON_STRENG_CTRL_SIZE1_DT << ATON_STRENG_CTRL_SIZE1_LSB) | \ (ATON_STRENG_CTRL_SIZE2_DT << ATON_STRENG_CTRL_SIZE2_LSB) | \ (ATON_STRENG_CTRL_SERDES_DT << ATON_STRENG_CTRL_SERDES_LSB) | \ (ATON_STRENG_CTRL_CONFCLR_DT << ATON_STRENG_CTRL_CONFCLR_LSB) | \ (ATON_STRENG_CTRL_RUNNING_DT << ATON_STRENG_CTRL_RUNNING_LSB) /** Description of the CTRL register. */ #define ATON_STRENG_CTRL_DESC "Control register" /** Address of the CTRL register of one of the STRENG Units. */ #define ATON_STRENG_CTRL_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_CTRL_OFFSET) /** Get the content of the CTRL register of one of the STRENG Units. */ #define ATON_STRENG_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the STRENG Units. */ #define ATON_STRENG_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_GetDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_STRENG_CTRL_GetOffset(void) { return ATON_STRENG_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CTRL register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_CTRL_GetAddr(uint32_t instance) { return ATON_STRENG_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_CTRL_Get(uint32_t instance) { return ATON_STRENG_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CTRL register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_CTRL_Set(uint32_t instance, uint32_t data) { ATON_STRENG_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_EN_DESC "Enable the Stream Engine" /** Offset of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_EN_LSB, ATON_STRENG_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_EN_LSB, ATON_STRENG_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_EN(uint32_t reg) { return ATON_STRENG_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_CLR_LSB, ATON_STRENG_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_CLR_LSB, ATON_STRENG_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_CLR(uint32_t reg) { return ATON_STRENG_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- SINGLE field of the CTRL register ------------------------------------------------------------ */ /** Description of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SINGLE_DESC "Stop after one frame (RO when CTRL.RUNNING)" /** Offset of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SINGLE_LSB 2UL /** Size in bits of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SINGLE_W (1UL) /** Mask for retrieving the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SINGLE_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SINGLE_DT 0x0UL /** Access rights of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SINGLE_AC "RW" /** Check whether access to the SINGLE field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SINGLE_S 0 /** Check whether access to the SINGLE field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SINGLE_P 0 /** Read the content of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SINGLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SINGLE_LSB, ATON_STRENG_CTRL_SINGLE_W) /** Modify the content of the SINGLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SINGLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SINGLE_LSB, ATON_STRENG_CTRL_SINGLE_W, DATA) /** * Get the description of the SINGLE field of CTRL register. * * \return the description of the SINGLE field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SINGLE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SINGLE_DESC; } /** * Read the content of the SINGLE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SINGLE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SINGLE(uint32_t reg) { return ATON_STRENG_CTRL_GET_SINGLE(reg); } /** * Write the content of the SINGLE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SINGLE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SINGLE(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SINGLE(reg, data); } /* ------------------------------------------------------------- DIR field of the CTRL register ------------------------------------------------------------- */ /** Description of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_DIR_DESC "Direction (RO when CTRL.RUNNING)" /** Offset of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_DIR_LSB 3UL /** Size in bits of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_DIR_W (1UL) /** Mask for retrieving the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_DIR_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_DIR_DT 0x0UL /** Access rights of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_DIR_AC "RW" /** Check whether access to the DIR field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_DIR_S 0 /** Check whether access to the DIR field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_DIR_P 0 /** Read the content of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_DIR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_DIR_LSB, ATON_STRENG_CTRL_DIR_W) /** Modify the content of the DIR field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_DIR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_DIR_LSB, ATON_STRENG_CTRL_DIR_W, DATA) /** * Get the description of the DIR field of CTRL register. * * \return the description of the DIR field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_DIR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_DIR_DESC; } /** * Read the content of the DIR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DIR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_DIR(uint32_t reg) { return ATON_STRENG_CTRL_GET_DIR(reg); } /** * Write the content of the DIR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DIR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_DIR(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_DIR(reg, data); } /* ------------------------------------------------------------ NOINC field of the CTRL register ------------------------------------------------------------ */ /** Description of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_NOINC_DESC "Do not increment address (RO when CTRL.RUNNING)" /** Offset of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_NOINC_LSB 4UL /** Size in bits of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_NOINC_W (1UL) /** Mask for retrieving the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_NOINC_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_NOINC_DT 0x0UL /** Access rights of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_NOINC_AC "RW" /** Check whether access to the NOINC field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_NOINC_S 0 /** Check whether access to the NOINC field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_NOINC_P 0 /** Read the content of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_NOINC(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_NOINC_LSB, ATON_STRENG_CTRL_NOINC_W) /** Modify the content of the NOINC field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_NOINC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_NOINC_LSB, ATON_STRENG_CTRL_NOINC_W, DATA) /** * Get the description of the NOINC field of CTRL register. * * \return the description of the NOINC field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_NOINC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_NOINC_DESC; } /** * Read the content of the NOINC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the NOINC field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_NOINC(uint32_t reg) { return ATON_STRENG_CTRL_GET_NOINC(reg); } /** * Write the content of the NOINC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the NOINC field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_NOINC(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_NOINC(reg, data); } /* ----------------------------------------------------------- ISTART field of the CTRL register ------------------------------------------------------------ */ /** Description of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_ISTART_DESC "Do not wait for frame start (RO when CTRL.RUNNING)" /** Offset of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_ISTART_LSB 5UL /** Size in bits of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_ISTART_W (1UL) /** Mask for retrieving the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_ISTART_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_ISTART_DT 0x0UL /** Access rights of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_ISTART_AC "RW" /** Check whether access to the ISTART field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_ISTART_S 0 /** Check whether access to the ISTART field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_ISTART_P 0 /** Read the content of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_ISTART(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_ISTART_LSB, ATON_STRENG_CTRL_ISTART_W) /** Modify the content of the ISTART field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_ISTART(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_ISTART_LSB, ATON_STRENG_CTRL_ISTART_W, DATA) /** * Get the description of the ISTART field of CTRL register. * * \return the description of the ISTART field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_ISTART_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_ISTART_DESC; } /** * Read the content of the ISTART field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ISTART field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_ISTART(uint32_t reg) { return ATON_STRENG_CTRL_GET_ISTART(reg); } /** * Write the content of the ISTART field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ISTART field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_ISTART(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_ISTART(reg, data); } /* ---------------------------------------------------------- SUBSAMPLE field of the CTRL register ---------------------------------------------------------- */ /** Description of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SUBSAMPLE_DESC "Handle data as 4:2:2 (RO when CTRL.RUNNING)" /** Offset of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SUBSAMPLE_LSB 6UL /** Size in bits of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SUBSAMPLE_W (1UL) /** Mask for retrieving the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SUBSAMPLE_MASK ATON_FIELD_MASK(6UL, 1UL) /** Reset value of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SUBSAMPLE_DT 0x0UL /** Access rights of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SUBSAMPLE_AC "RW" /** Check whether access to the SUBSAMPLE field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SUBSAMPLE_S 0 /** Check whether access to the SUBSAMPLE field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SUBSAMPLE_P 0 /** Read the content of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SUBSAMPLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SUBSAMPLE_LSB, ATON_STRENG_CTRL_SUBSAMPLE_W) /** Modify the content of the SUBSAMPLE field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SUBSAMPLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SUBSAMPLE_LSB, ATON_STRENG_CTRL_SUBSAMPLE_W, DATA) /** * Get the description of the SUBSAMPLE field of CTRL register. * * \return the description of the SUBSAMPLE field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SUBSAMPLE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SUBSAMPLE_DESC; } /** * Read the content of the SUBSAMPLE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SUBSAMPLE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SUBSAMPLE(uint32_t reg) { return ATON_STRENG_CTRL_GET_SUBSAMPLE(reg); } /** * Write the content of the SUBSAMPLE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SUBSAMPLE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SUBSAMPLE(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SUBSAMPLE(reg, data); } /* ------------------------------------------------------------ CONT field of the CTRL register ------------------------------------------------------------- */ /** Description of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_CONT_DESC "Do not restart address pointer at end of frame (RO when CTRL.RUNNING)" /** Offset of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_CONT_LSB 7UL /** Size in bits of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_CONT_W (1UL) /** Mask for retrieving the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_CONT_MASK ATON_FIELD_MASK(7UL, 1UL) /** Reset value of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_CONT_DT 0x0UL /** Access rights of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_CONT_AC "RW" /** Check whether access to the CONT field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_CONT_S 0 /** Check whether access to the CONT field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_CONT_P 0 /** Read the content of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_CONT(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_CONT_LSB, ATON_STRENG_CTRL_CONT_W) /** Modify the content of the CONT field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_CONT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_CONT_LSB, ATON_STRENG_CTRL_CONT_W, DATA) /** * Get the description of the CONT field of CTRL register. * * \return the description of the CONT field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_CONT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_CONT_DESC; } /** * Read the content of the CONT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONT field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_CONT(uint32_t reg) { return ATON_STRENG_CTRL_GET_CONT(reg); } /** * Write the content of the CONT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONT field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_CONT(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_CONT(reg, data); } /* ------------------------------------------------------------- RAW field of the CTRL register ------------------------------------------------------------- */ /** Description of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_DESC "Send RAW files (RO when CTRL.RUNNING)" /** Offset of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_LSB 8UL /** Size in bits of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_W (1UL) /** Mask for retrieving the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_MASK ATON_FIELD_MASK(8UL, 1UL) /** Reset value of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_DT 0x0UL /** Access rights of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_AC "RW" /** Check whether access to the RAW field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_RAW_S 0 /** Check whether access to the RAW field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_RAW_P 0 /** Read the content of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_RAW(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_RAW_LSB, ATON_STRENG_CTRL_RAW_W) /** Modify the content of the RAW field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_RAW(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_RAW_LSB, ATON_STRENG_CTRL_RAW_W, DATA) /** * Get the description of the RAW field of CTRL register. * * \return the description of the RAW field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_RAW_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_RAW_DESC; } /** * Read the content of the RAW field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the RAW field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_RAW(uint32_t reg) { return ATON_STRENG_CTRL_GET_RAW(reg); } /** * Write the content of the RAW field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_RAW(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_RAW(reg, data); } /* ----------------------------------------------------------- RAW_OUT field of the CTRL register ----------------------------------------------------------- */ /** Description of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_OUT_DESC "Force RAW output (bus to stream only) even if the engine is programmed in raster mode (RO when CTRL.RUNNING)" /** Offset of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_OUT_LSB 9UL /** Size in bits of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_OUT_W (1UL) /** Mask for retrieving the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_OUT_MASK ATON_FIELD_MASK(9UL, 1UL) /** Reset value of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_OUT_DT 0x0UL /** Access rights of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_RAW_OUT_AC "RW" /** Check whether access to the RAW_OUT field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_RAW_OUT_S 0 /** Check whether access to the RAW_OUT field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_RAW_OUT_P 0 /** Read the content of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_RAW_OUT(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_RAW_OUT_LSB, ATON_STRENG_CTRL_RAW_OUT_W) /** Modify the content of the RAW_OUT field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_RAW_OUT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_RAW_OUT_LSB, ATON_STRENG_CTRL_RAW_OUT_W, DATA) /** * Get the description of the RAW_OUT field of CTRL register. * * \return the description of the RAW_OUT field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_RAW_OUT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_RAW_OUT_DESC; } /** * Read the content of the RAW_OUT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the RAW_OUT field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_RAW_OUT(uint32_t reg) { return ATON_STRENG_CTRL_GET_RAW_OUT(reg); } /** * Write the content of the RAW_OUT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_OUT field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_RAW_OUT(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_RAW_OUT(reg, data); } /* ------------------------------------------------------------ DESCR field of the CTRL register ------------------------------------------------------------ */ /** Description of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_DESCR_DESC "Fetch descriptor from memory (RO when CTRL.RUNNING)" /** Offset of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_DESCR_LSB 10UL /** Size in bits of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_DESCR_W (1UL) /** Mask for retrieving the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_DESCR_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_DESCR_DT 0x0UL /** Access rights of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_DESCR_AC "RW" /** Check whether access to the DESCR field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_DESCR_S 0 /** Check whether access to the DESCR field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_DESCR_P 0 /** Read the content of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_DESCR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_DESCR_LSB, ATON_STRENG_CTRL_DESCR_W) /** Modify the content of the DESCR field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_DESCR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_DESCR_LSB, ATON_STRENG_CTRL_DESCR_W, DATA) /** * Get the description of the DESCR field of CTRL register. * * \return the description of the DESCR field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_DESCR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_DESCR_DESC; } /** * Read the content of the DESCR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DESCR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_DESCR(uint32_t reg) { return ATON_STRENG_CTRL_GET_DESCR(reg); } /** * Write the content of the DESCR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DESCR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_DESCR(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_DESCR(reg, data); } /* ------------------------------------------------------------ NOBLK field of the CTRL register ------------------------------------------------------------ */ /** Description of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_NOBLK_DESC "Do not use blocks wider that the native bus size (RO when CTRL.RUNNING)" /** Offset of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_NOBLK_LSB 11UL /** Size in bits of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_NOBLK_W (1UL) /** Mask for retrieving the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_NOBLK_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_NOBLK_DT 0x0UL /** Access rights of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_NOBLK_AC "RW" /** Check whether access to the NOBLK field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_NOBLK_S 0 /** Check whether access to the NOBLK field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_NOBLK_P 0 /** Read the content of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_NOBLK(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_NOBLK_LSB, ATON_STRENG_CTRL_NOBLK_W) /** Modify the content of the NOBLK field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_NOBLK(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_NOBLK_LSB, ATON_STRENG_CTRL_NOBLK_W, DATA) /** * Get the description of the NOBLK field of CTRL register. * * \return the description of the NOBLK field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_NOBLK_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_NOBLK_DESC; } /** * Read the content of the NOBLK field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the NOBLK field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_NOBLK(uint32_t reg) { return ATON_STRENG_CTRL_GET_NOBLK(reg); } /** * Write the content of the NOBLK field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the NOBLK field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_NOBLK(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_NOBLK(reg, data); } /* ------------------------------------------------------------ ROUND field of the CTRL register ------------------------------------------------------------ */ /** Description of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_ROUND_DESC "Channels data rounding enable (RO when CTRL.RUNNING)" /** Offset of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_ROUND_LSB 12UL /** Size in bits of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_ROUND_W (1UL) /** Mask for retrieving the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_ROUND_MASK ATON_FIELD_MASK(12UL, 1UL) /** Reset value of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_ROUND_DT 0x0UL /** Access rights of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_ROUND_AC "RW" /** Check whether access to the ROUND field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_ROUND_S 0 /** Check whether access to the ROUND field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_ROUND_P 0 /** Read the content of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_ROUND_LSB, ATON_STRENG_CTRL_ROUND_W) /** Modify the content of the ROUND field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_ROUND_LSB, ATON_STRENG_CTRL_ROUND_W, DATA) /** * Get the description of the ROUND field of CTRL register. * * \return the description of the ROUND field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_ROUND_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_ROUND_DESC; } /** * Read the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_ROUND(uint32_t reg) { return ATON_STRENG_CTRL_GET_ROUND(reg); } /** * Write the content of the ROUND field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUND field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_ROUND(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_ROUND(reg, data); } /* ----------------------------------------------------------- BEFORCE field of the CTRL register ----------------------------------------------------------- */ /** Description of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_BEFORCE_DESC "Force bus-wide write (RO when CTRL.RUNNING)" /** Offset of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_BEFORCE_LSB 13UL /** Size in bits of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_BEFORCE_W (1UL) /** Mask for retrieving the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_BEFORCE_MASK ATON_FIELD_MASK(13UL, 1UL) /** Reset value of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_BEFORCE_DT 0x0UL /** Access rights of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_BEFORCE_AC "RW" /** Check whether access to the BEFORCE field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_BEFORCE_S 0 /** Check whether access to the BEFORCE field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_BEFORCE_P 0 /** Read the content of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_BEFORCE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_BEFORCE_LSB, ATON_STRENG_CTRL_BEFORCE_W) /** Modify the content of the BEFORCE field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_BEFORCE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_BEFORCE_LSB, ATON_STRENG_CTRL_BEFORCE_W, DATA) /** * Get the description of the BEFORCE field of CTRL register. * * \return the description of the BEFORCE field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_BEFORCE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_BEFORCE_DESC; } /** * Read the content of the BEFORCE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the BEFORCE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_BEFORCE(uint32_t reg) { return ATON_STRENG_CTRL_GET_BEFORCE(reg); } /** * Write the content of the BEFORCE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BEFORCE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_BEFORCE(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_BEFORCE(reg, data); } /* ----------------------------------------------------------- LSBMODE field of the CTRL register ----------------------------------------------------------- */ /** Description of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_LSBMODE_DESC "Use the three 8 bits channels as a unique 24 bit channel LSB aligned (RO when CTRL.RUNNING)" /** Offset of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_LSBMODE_LSB 14UL /** Size in bits of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_LSBMODE_W (1UL) /** Mask for retrieving the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_LSBMODE_MASK ATON_FIELD_MASK(14UL, 1UL) /** Reset value of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_LSBMODE_DT 0x0UL /** Access rights of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_LSBMODE_AC "RW" /** Check whether access to the LSBMODE field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_LSBMODE_S 0 /** Check whether access to the LSBMODE field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_LSBMODE_P 0 /** Read the content of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_LSBMODE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_LSBMODE_LSB, ATON_STRENG_CTRL_LSBMODE_W) /** Modify the content of the LSBMODE field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_LSBMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_LSBMODE_LSB, ATON_STRENG_CTRL_LSBMODE_W, DATA) /** * Get the description of the LSBMODE field of CTRL register. * * \return the description of the LSBMODE field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_LSBMODE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_LSBMODE_DESC; } /** * Read the content of the LSBMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the LSBMODE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_LSBMODE(uint32_t reg) { return ATON_STRENG_CTRL_GET_LSBMODE(reg); } /** * Write the content of the LSBMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the LSBMODE field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_LSBMODE(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_LSBMODE(reg, data); } /* ----------------------------------------------------------- SIGNEXT field of the CTRL register ----------------------------------------------------------- */ /** Description of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SIGNEXT_DESC "24 bit sign extension (valid only if LSBMODE is set to 1 and direction is bus to stream) (RO when CTRL.RUNNING)" /** Offset of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SIGNEXT_LSB 15UL /** Size in bits of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SIGNEXT_W (1UL) /** Mask for retrieving the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SIGNEXT_MASK ATON_FIELD_MASK(15UL, 1UL) /** Reset value of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SIGNEXT_DT 0x0UL /** Access rights of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SIGNEXT_AC "RW" /** Check whether access to the SIGNEXT field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SIGNEXT_S 0 /** Check whether access to the SIGNEXT field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SIGNEXT_P 0 /** Read the content of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SIGNEXT(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIGNEXT_LSB, ATON_STRENG_CTRL_SIGNEXT_W) /** Modify the content of the SIGNEXT field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SIGNEXT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIGNEXT_LSB, ATON_STRENG_CTRL_SIGNEXT_W, DATA) /** * Get the description of the SIGNEXT field of CTRL register. * * \return the description of the SIGNEXT field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SIGNEXT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SIGNEXT_DESC; } /** * Read the content of the SIGNEXT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SIGNEXT field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SIGNEXT(uint32_t reg) { return ATON_STRENG_CTRL_GET_SIGNEXT(reg); } /** * Write the content of the SIGNEXT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SIGNEXT field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SIGNEXT(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SIGNEXT(reg, data); } /* ------------------------------------------------------------ SIZE0 field of the CTRL register ------------------------------------------------------------ */ /** Description of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE0_DESC "Size in bits of channel 0 (values greater than 8 will be refused) (RO when CTRL.RUNNING)" /** Offset of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE0_LSB 16UL /** Size in bits of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE0_W (4UL) /** Mask for retrieving the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE0_MASK ATON_FIELD_MASK(16UL, 4UL) /** Reset value of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE0_DT 0x0UL /** Access rights of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE0_AC "RW" /** Check whether access to the SIZE0 field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SIZE0_S 0 /** Check whether access to the SIZE0 field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SIZE0_P 0 /** Read the content of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SIZE0(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIZE0_LSB, ATON_STRENG_CTRL_SIZE0_W) /** Modify the content of the SIZE0 field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SIZE0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIZE0_LSB, ATON_STRENG_CTRL_SIZE0_W, DATA) /** * Get the description of the SIZE0 field of CTRL register. * * \return the description of the SIZE0 field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SIZE0_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SIZE0_DESC; } /** * Read the content of the SIZE0 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SIZE0 field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SIZE0(uint32_t reg) { return ATON_STRENG_CTRL_GET_SIZE0(reg); } /** * Write the content of the SIZE0 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the SIZE0 field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SIZE0(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SIZE0(reg, data); } /* ------------------------------------------------------------ SIZE1 field of the CTRL register ------------------------------------------------------------ */ /** Description of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE1_DESC "Size in bits of channel 1 (values greater than 8 will be refused) (RO when CTRL.RUNNING)" /** Offset of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE1_LSB 20UL /** Size in bits of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE1_W (4UL) /** Mask for retrieving the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE1_MASK ATON_FIELD_MASK(20UL, 4UL) /** Reset value of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE1_DT 0x0UL /** Access rights of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE1_AC "RW" /** Check whether access to the SIZE1 field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SIZE1_S 0 /** Check whether access to the SIZE1 field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SIZE1_P 0 /** Read the content of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SIZE1(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIZE1_LSB, ATON_STRENG_CTRL_SIZE1_W) /** Modify the content of the SIZE1 field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SIZE1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIZE1_LSB, ATON_STRENG_CTRL_SIZE1_W, DATA) /** * Get the description of the SIZE1 field of CTRL register. * * \return the description of the SIZE1 field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SIZE1_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SIZE1_DESC; } /** * Read the content of the SIZE1 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SIZE1 field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SIZE1(uint32_t reg) { return ATON_STRENG_CTRL_GET_SIZE1(reg); } /** * Write the content of the SIZE1 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the SIZE1 field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SIZE1(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SIZE1(reg, data); } /* ------------------------------------------------------------ SIZE2 field of the CTRL register ------------------------------------------------------------ */ /** Description of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE2_DESC "Size in bits of channel 2 (values greater than 8 will be refused) (RO when CTRL.RUNNING - ignored, 0 used instead, if CTRL.SUBSAMPLE is set)" /** Offset of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE2_LSB 24UL /** Size in bits of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE2_W (4UL) /** Mask for retrieving the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE2_MASK ATON_FIELD_MASK(24UL, 4UL) /** Reset value of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE2_DT 0x0UL /** Access rights of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SIZE2_AC "RW" /** Check whether access to the SIZE2 field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SIZE2_S 0 /** Check whether access to the SIZE2 field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SIZE2_P 0 /** Read the content of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SIZE2(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SIZE2_LSB, ATON_STRENG_CTRL_SIZE2_W) /** Modify the content of the SIZE2 field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SIZE2(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SIZE2_LSB, ATON_STRENG_CTRL_SIZE2_W, DATA) /** * Get the description of the SIZE2 field of CTRL register. * * \return the description of the SIZE2 field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SIZE2_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SIZE2_DESC; } /** * Read the content of the SIZE2 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SIZE2 field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SIZE2(uint32_t reg) { return ATON_STRENG_CTRL_GET_SIZE2(reg); } /** * Write the content of the SIZE2 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the SIZE2 field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SIZE2(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SIZE2(reg, data); } /* ----------------------------------------------------------- SERDES field of the CTRL register ------------------------------------------------------------ */ /** Description of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SERDES_DESC "Enable serdes feature (00/01 -> disable, 10 -> CH0/1, 11 -> CH0/1/2) (RO when CTRL.RUNNING)" /** Offset of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SERDES_LSB 28UL /** Size in bits of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SERDES_W (2UL) /** Mask for retrieving the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SERDES_MASK ATON_FIELD_MASK(28UL, 2UL) /** Reset value of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SERDES_DT 0x0UL /** Access rights of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SERDES_AC "RW" /** Check whether access to the SERDES field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_SERDES_S 0 /** Check whether access to the SERDES field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_SERDES_P 0 /** Read the content of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_SERDES(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_SERDES_LSB, ATON_STRENG_CTRL_SERDES_W) /** Modify the content of the SERDES field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_SERDES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_SERDES_LSB, ATON_STRENG_CTRL_SERDES_W, DATA) /** * Get the description of the SERDES field of CTRL register. * * \return the description of the SERDES field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_SERDES_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_SERDES_DESC; } /** * Read the content of the SERDES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SERDES field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_SERDES(uint32_t reg) { return ATON_STRENG_CTRL_GET_SERDES(reg); } /** * Write the content of the SERDES field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the SERDES field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_SERDES(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_SERDES(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared) (RO when CTRL.RUNNING)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_CONFCLR_LSB, ATON_STRENG_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_STRENG_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CTRL_CONFCLR_LSB, ATON_STRENG_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_STRENG_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_STRENG_CTRL_SET_CONFCLR(reg, data); } /* ----------------------------------------------------------- RUNNING field of the CTRL register ----------------------------------------------------------- */ /** Description of the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_RUNNING_DESC "Running condition" /** Offset of the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_RUNNING_LSB 31UL /** Size in bits of the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_RUNNING_W (1UL) /** Mask for retrieving the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_RUNNING_MASK ATON_FIELD_MASK(31UL, 1UL) /** Reset value of the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_RUNNING_DT 0x0UL /** Access rights of the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_RUNNING_AC "R" /** Check whether access to the RUNNING field of the CTRL register is secured or not. */ #define ATON_STRENG_CTRL_RUNNING_S 0 /** Check whether access to the RUNNING field of the CTRL register is privileged or not. */ #define ATON_STRENG_CTRL_RUNNING_P 0 /** Read the content of the RUNNING field of the CTRL register. */ #define ATON_STRENG_CTRL_GET_RUNNING(REG) ATON_GET_FIELD(REG, ATON_STRENG_CTRL_RUNNING_LSB, ATON_STRENG_CTRL_RUNNING_W) /** * Get the description of the RUNNING field of CTRL register. * * \return the description of the RUNNING field of CTRL register */ static inline const int8_t *ATON_STRENG_CTRL_RUNNING_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CTRL_RUNNING_DESC; } /** * Read the content of the RUNNING field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the RUNNING field belonging to CTRL register */ static inline uint32_t ATON_STRENG_CTRL_Get_RUNNING(uint32_t reg) { return ATON_STRENG_CTRL_GET_RUNNING(reg); } /* ****************************************************** VERSION register of one of the STRENG Units ******************************************************* */ /** Offset of the VERSION register from the base address of the STRENG Unit. */ #define ATON_STRENG_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the STRENG Unit. */ #define ATON_STRENG_VERSION_DT \ (ATON_STRENG_VERSION_TYPE_DT << ATON_STRENG_VERSION_TYPE_LSB) | \ (ATON_STRENG_VERSION_MINOR_DT << ATON_STRENG_VERSION_MINOR_LSB) | \ (ATON_STRENG_VERSION_MAJOR_DT << ATON_STRENG_VERSION_MAJOR_LSB) | \ (ATON_STRENG_VERSION_STRCMD_DT << ATON_STRENG_VERSION_STRCMD_LSB) | \ (ATON_STRENG_VERSION_SERDES_DT << ATON_STRENG_VERSION_SERDES_LSB) | \ (ATON_STRENG_VERSION_ENCR_DT << ATON_STRENG_VERSION_ENCR_LSB) | \ (ATON_STRENG_VERSION_CACHE_DT << ATON_STRENG_VERSION_CACHE_LSB) | \ (ATON_STRENG_VERSION_CID_DT << ATON_STRENG_VERSION_CID_LSB) | \ (ATON_STRENG_VERSION_EXTSYNC_DT << ATON_STRENG_VERSION_EXTSYNC_LSB) /** Description of the VERSION register. */ #define ATON_STRENG_VERSION_DESC "Version register" /** Address of the VERSION register of one of the STRENG Units. */ #define ATON_STRENG_VERSION_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_VERSION_OFFSET) /** Get the content of the VERSION register of one of the STRENG Units. */ #define ATON_STRENG_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_GetDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_STRENG_VERSION_GetOffset(void) { return ATON_STRENG_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the VERSION register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_VERSION_GetAddr(uint32_t instance) { return ATON_STRENG_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_VERSION_Get(uint32_t instance) { return ATON_STRENG_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_TYPE_DT 0x1UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_TYPE_LSB, ATON_STRENG_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_TYPE(uint32_t reg) { return ATON_STRENG_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MINOR_DT 0x0UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_MINOR_LSB, ATON_STRENG_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_MINOR(uint32_t reg) { return ATON_STRENG_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MAJOR_DT 0x5UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_MAJOR_LSB, ATON_STRENG_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_MAJOR(uint32_t reg) { return ATON_STRENG_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- STRCMD field of the VERSION register ---------------------------------------------------------- */ /** Description of the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_STRCMD_DESC "Stream commands support" /** Offset of the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_STRCMD_LSB 16UL /** Size in bits of the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_STRCMD_W (1UL) /** Mask for retrieving the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_STRCMD_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_STRCMD_DT 0x0UL /** Access rights of the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_STRCMD_AC "R" /** Check whether access to the STRCMD field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_STRCMD_S 0 /** Check whether access to the STRCMD field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_STRCMD_P 0 /** Read the content of the STRCMD field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_STRCMD(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_STRCMD_LSB, ATON_STRENG_VERSION_STRCMD_W) /** * Get the description of the STRCMD field of VERSION register. * * \return the description of the STRCMD field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_STRCMD_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_STRCMD_DESC; } /** * Read the content of the STRCMD field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the STRCMD field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_STRCMD(uint32_t reg) { return ATON_STRENG_VERSION_GET_STRCMD(reg); } /* ---------------------------------------------------------- SERDES field of the VERSION register ---------------------------------------------------------- */ /** Description of the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_SERDES_DESC "Serdes support" /** Offset of the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_SERDES_LSB 17UL /** Size in bits of the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_SERDES_W (1UL) /** Mask for retrieving the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_SERDES_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_SERDES_DT 0x1UL /** Access rights of the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_SERDES_AC "R" /** Check whether access to the SERDES field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_SERDES_S 0 /** Check whether access to the SERDES field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_SERDES_P 0 /** Read the content of the SERDES field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_SERDES(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_SERDES_LSB, ATON_STRENG_VERSION_SERDES_W) /** * Get the description of the SERDES field of VERSION register. * * \return the description of the SERDES field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_SERDES_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_SERDES_DESC; } /** * Read the content of the SERDES field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the SERDES field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_SERDES(uint32_t reg) { return ATON_STRENG_VERSION_GET_SERDES(reg); } /* ----------------------------------------------------------- ENCR field of the VERSION register ----------------------------------------------------------- */ /** Description of the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_ENCR_DESC "Encription support" /** Offset of the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_ENCR_LSB 18UL /** Size in bits of the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_ENCR_W (1UL) /** Mask for retrieving the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_ENCR_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_ENCR_DT 0x1UL /** Access rights of the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_ENCR_AC "R" /** Check whether access to the ENCR field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_ENCR_S 0 /** Check whether access to the ENCR field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_ENCR_P 0 /** Read the content of the ENCR field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_ENCR(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_ENCR_LSB, ATON_STRENG_VERSION_ENCR_W) /** * Get the description of the ENCR field of VERSION register. * * \return the description of the ENCR field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_ENCR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_ENCR_DESC; } /** * Read the content of the ENCR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the ENCR field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_ENCR(uint32_t reg) { return ATON_STRENG_VERSION_GET_ENCR(reg); } /* ---------------------------------------------------------- CACHE field of the VERSION register ----------------------------------------------------------- */ /** Description of the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_CACHE_DESC "Cache support" /** Offset of the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_CACHE_LSB 19UL /** Size in bits of the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_CACHE_W (1UL) /** Mask for retrieving the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_CACHE_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_CACHE_DT 0x1UL /** Access rights of the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_CACHE_AC "R" /** Check whether access to the CACHE field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_CACHE_S 0 /** Check whether access to the CACHE field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_CACHE_P 0 /** Read the content of the CACHE field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_CACHE(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_CACHE_LSB, ATON_STRENG_VERSION_CACHE_W) /** * Get the description of the CACHE field of VERSION register. * * \return the description of the CACHE field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_CACHE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_CACHE_DESC; } /** * Read the content of the CACHE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the CACHE field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_CACHE(uint32_t reg) { return ATON_STRENG_VERSION_GET_CACHE(reg); } /* ----------------------------------------------------------- CID field of the VERSION register ------------------------------------------------------------ */ /** Description of the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_CID_DESC "Compartment ID support" /** Offset of the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_CID_LSB 20UL /** Size in bits of the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_CID_W (1UL) /** Mask for retrieving the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_CID_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_CID_DT 0x1UL /** Access rights of the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_CID_AC "R" /** Check whether access to the CID field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_CID_S 0 /** Check whether access to the CID field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_CID_P 0 /** Read the content of the CID field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_CID(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_CID_LSB, ATON_STRENG_VERSION_CID_W) /** * Get the description of the CID field of VERSION register. * * \return the description of the CID field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_CID_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_CID_DESC; } /** * Read the content of the CID field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the CID field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_CID(uint32_t reg) { return ATON_STRENG_VERSION_GET_CID(reg); } /* --------------------------------------------------------- EXTSYNC field of the VERSION register ---------------------------------------------------------- */ /** Description of the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_EXTSYNC_DESC "External triggers support" /** Offset of the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_EXTSYNC_LSB 21UL /** Size in bits of the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_EXTSYNC_W (1UL) /** Mask for retrieving the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_EXTSYNC_MASK ATON_FIELD_MASK(21UL, 1UL) /** Reset value of the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_EXTSYNC_DT 0x1UL /** Access rights of the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_EXTSYNC_AC "R" /** Check whether access to the EXTSYNC field of the VERSION register is secured or not. */ #define ATON_STRENG_VERSION_EXTSYNC_S 0 /** Check whether access to the EXTSYNC field of the VERSION register is privileged or not. */ #define ATON_STRENG_VERSION_EXTSYNC_P 0 /** Read the content of the EXTSYNC field of the VERSION register. */ #define ATON_STRENG_VERSION_GET_EXTSYNC(REG) ATON_GET_FIELD(REG, ATON_STRENG_VERSION_EXTSYNC_LSB, ATON_STRENG_VERSION_EXTSYNC_W) /** * Get the description of the EXTSYNC field of VERSION register. * * \return the description of the EXTSYNC field of VERSION register */ static inline const int8_t *ATON_STRENG_VERSION_EXTSYNC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_VERSION_EXTSYNC_DESC; } /** * Read the content of the EXTSYNC field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the EXTSYNC field belonging to VERSION register */ static inline uint32_t ATON_STRENG_VERSION_Get_EXTSYNC(uint32_t reg) { return ATON_STRENG_VERSION_GET_EXTSYNC(reg); } /* ******************************************************** ADDR register of one of the STRENG Units ******************************************************** */ /** Offset of the ADDR register from the base address of the STRENG Unit. */ #define ATON_STRENG_ADDR_OFFSET 0x8UL /** Reset value of the ADDR register of the STRENG Unit. */ #define ATON_STRENG_ADDR_DT \ (ATON_STRENG_ADDR_REG_DT << ATON_STRENG_ADDR_REG_LSB) /** Description of the ADDR register. */ #define ATON_STRENG_ADDR_DESC "Source/destination address" /** Address of the ADDR register of one of the STRENG Units. */ #define ATON_STRENG_ADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_ADDR_OFFSET) /** Get the content of the ADDR register of one of the STRENG Units. */ #define ATON_STRENG_ADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_ADDR_ADDR(UNIT))) /** Set the content of the ADDR register of one of the STRENG Units. */ #define ATON_STRENG_ADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_ADDR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ADDR register. * * \return the description of ADDR register */ static inline const int8_t *ATON_STRENG_ADDR_GetDesc(void) { return (const int8_t *)ATON_STRENG_ADDR_DESC; } /** * Get the offset of the ADDR register. * * \return the offset of ADDR register */ static inline uint32_t ATON_STRENG_ADDR_GetOffset(void) { return ATON_STRENG_ADDR_OFFSET; } /** * Get the address of the ADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ADDR register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of ADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_ADDR_GetAddr(uint32_t instance) { return ATON_STRENG_ADDR_ADDR(instance); } /** * Read the content of the ADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ADDR register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of ADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_ADDR_Get(uint32_t instance) { return ATON_STRENG_ADDR_GET(instance); } /** * Write the content of the ADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ADDR register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_ADDR_Set(uint32_t instance, uint32_t data) { ATON_STRENG_ADDR_SET(instance, data); } /* ------------------------------------------------------------- REG field of the ADDR register ------------------------------------------------------------- */ /** Description of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_REG_DESC "Address (RO when CTRL.RUNNING)" /** Offset of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_REG_LSB 0UL /** Size in bits of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_REG_W (32UL) /** Mask for retrieving the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_REG_DT 0x0UL /** Access rights of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_REG_AC "RW" /** Check whether access to the REG field of the ADDR register is secured or not. */ #define ATON_STRENG_ADDR_REG_S 0 /** Check whether access to the REG field of the ADDR register is privileged or not. */ #define ATON_STRENG_ADDR_REG_P 0 /** Read the content of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_ADDR_REG_LSB, ATON_STRENG_ADDR_REG_W) /** Modify the content of the REG field of the ADDR register. */ #define ATON_STRENG_ADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ADDR_REG_LSB, ATON_STRENG_ADDR_REG_W, DATA) /** * Get the description of the REG field of ADDR register. * * \return the description of the REG field of ADDR register */ static inline const int8_t *ATON_STRENG_ADDR_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ADDR_REG_DESC; } /** * Read the content of the REG field of the ADDR register. * * \param[in] reg is the value of the ADDR register * * \return the content of the REG field belonging to ADDR register */ static inline uint32_t ATON_STRENG_ADDR_Get_REG(uint32_t reg) { return ATON_STRENG_ADDR_GET_REG(reg); } /** * Write the content of the REG field of the ADDR register. * * \param[in] reg is the value of the ADDR register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to ADDR register */ static inline uint32_t ATON_STRENG_ADDR_Set_REG(uint32_t reg, uint32_t data) { return ATON_STRENG_ADDR_SET_REG(reg, data); } /* ******************************************************* FSIZE register of one of the STRENG Units ******************************************************** */ /** Offset of the FSIZE register from the base address of the STRENG Unit. */ #define ATON_STRENG_FSIZE_OFFSET 0xcUL /** Reset value of the FSIZE register of the STRENG Unit. */ #define ATON_STRENG_FSIZE_DT \ (ATON_STRENG_FSIZE_WIDTH_DT << ATON_STRENG_FSIZE_WIDTH_LSB) | \ (ATON_STRENG_FSIZE_HEIGHT_DT << ATON_STRENG_FSIZE_HEIGHT_LSB) /** Description of the FSIZE register. */ #define ATON_STRENG_FSIZE_DESC "Frame size" /** Address of the FSIZE register of one of the STRENG Units. */ #define ATON_STRENG_FSIZE_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FSIZE_OFFSET) /** Get the content of the FSIZE register of one of the STRENG Units. */ #define ATON_STRENG_FSIZE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FSIZE_ADDR(UNIT))) /** Set the content of the FSIZE register of one of the STRENG Units. */ #define ATON_STRENG_FSIZE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FSIZE_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FSIZE register. * * \return the description of FSIZE register */ static inline const int8_t *ATON_STRENG_FSIZE_GetDesc(void) { return (const int8_t *)ATON_STRENG_FSIZE_DESC; } /** * Get the offset of the FSIZE register. * * \return the offset of FSIZE register */ static inline uint32_t ATON_STRENG_FSIZE_GetOffset(void) { return ATON_STRENG_FSIZE_OFFSET; } /** * Get the address of the FSIZE register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FSIZE register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of FSIZE register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FSIZE_GetAddr(uint32_t instance) { return ATON_STRENG_FSIZE_ADDR(instance); } /** * Read the content of the FSIZE register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FSIZE register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of FSIZE register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FSIZE_Get(uint32_t instance) { return ATON_STRENG_FSIZE_GET(instance); } /** * Write the content of the FSIZE register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FSIZE register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_FSIZE_Set(uint32_t instance, uint32_t data) { ATON_STRENG_FSIZE_SET(instance, data); } /* ----------------------------------------------------------- WIDTH field of the FSIZE register ------------------------------------------------------------ */ /** Description of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_WIDTH_DESC "Frame width (pixl per line). In RAW mode this register contains the lower part of the frame length (RO when CTRL.RUNNING)" /** Offset of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_WIDTH_LSB 0UL /** Size in bits of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_WIDTH_W (16UL) /** Mask for retrieving the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_WIDTH_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_WIDTH_DT 0x0UL /** Access rights of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_WIDTH_AC "RW" /** Check whether access to the WIDTH field of the FSIZE register is secured or not. */ #define ATON_STRENG_FSIZE_WIDTH_S 0 /** Check whether access to the WIDTH field of the FSIZE register is privileged or not. */ #define ATON_STRENG_FSIZE_WIDTH_P 0 /** Read the content of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_GET_WIDTH(REG) ATON_GET_FIELD(REG, ATON_STRENG_FSIZE_WIDTH_LSB, ATON_STRENG_FSIZE_WIDTH_W) /** Modify the content of the WIDTH field of the FSIZE register. */ #define ATON_STRENG_FSIZE_SET_WIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FSIZE_WIDTH_LSB, ATON_STRENG_FSIZE_WIDTH_W, DATA) /** * Get the description of the WIDTH field of FSIZE register. * * \return the description of the WIDTH field of FSIZE register */ static inline const int8_t *ATON_STRENG_FSIZE_WIDTH_GetdDesc(void) { return (const int8_t *)ATON_STRENG_FSIZE_WIDTH_DESC; } /** * Read the content of the WIDTH field of the FSIZE register. * * \param[in] reg is the value of the FSIZE register * * \return the content of the WIDTH field belonging to FSIZE register */ static inline uint32_t ATON_STRENG_FSIZE_Get_WIDTH(uint32_t reg) { return ATON_STRENG_FSIZE_GET_WIDTH(reg); } /** * Write the content of the WIDTH field of the FSIZE register. * * \param[in] reg is the value of the FSIZE register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the WIDTH field belonging to FSIZE register */ static inline uint32_t ATON_STRENG_FSIZE_Set_WIDTH(uint32_t reg, uint32_t data) { return ATON_STRENG_FSIZE_SET_WIDTH(reg, data); } /* ----------------------------------------------------------- HEIGHT field of the FSIZE register ----------------------------------------------------------- */ /** Description of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_HEIGHT_DESC "Frame height (number of lines). In RAW mode this register contains the higher part of the frame length (RO when CTRL.RUNNING)" /** Offset of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_HEIGHT_LSB 16UL /** Size in bits of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_HEIGHT_W (16UL) /** Mask for retrieving the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_HEIGHT_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_HEIGHT_DT 0x0UL /** Access rights of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_HEIGHT_AC "RW" /** Check whether access to the HEIGHT field of the FSIZE register is secured or not. */ #define ATON_STRENG_FSIZE_HEIGHT_S 0 /** Check whether access to the HEIGHT field of the FSIZE register is privileged or not. */ #define ATON_STRENG_FSIZE_HEIGHT_P 0 /** Read the content of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_GET_HEIGHT(REG) ATON_GET_FIELD(REG, ATON_STRENG_FSIZE_HEIGHT_LSB, ATON_STRENG_FSIZE_HEIGHT_W) /** Modify the content of the HEIGHT field of the FSIZE register. */ #define ATON_STRENG_FSIZE_SET_HEIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FSIZE_HEIGHT_LSB, ATON_STRENG_FSIZE_HEIGHT_W, DATA) /** * Get the description of the HEIGHT field of FSIZE register. * * \return the description of the HEIGHT field of FSIZE register */ static inline const int8_t *ATON_STRENG_FSIZE_HEIGHT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_FSIZE_HEIGHT_DESC; } /** * Read the content of the HEIGHT field of the FSIZE register. * * \param[in] reg is the value of the FSIZE register * * \return the content of the HEIGHT field belonging to FSIZE register */ static inline uint32_t ATON_STRENG_FSIZE_Get_HEIGHT(uint32_t reg) { return ATON_STRENG_FSIZE_GET_HEIGHT(reg); } /** * Write the content of the HEIGHT field of the FSIZE register. * * \param[in] reg is the value of the FSIZE register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the HEIGHT field belonging to FSIZE register */ static inline uint32_t ATON_STRENG_FSIZE_Set_HEIGHT(uint32_t reg, uint32_t data) { return ATON_STRENG_FSIZE_SET_HEIGHT(reg, data); } /* ******************************************************* DEPTH register of one of the STRENG Units ******************************************************** */ /** Offset of the DEPTH register from the base address of the STRENG Unit. */ #define ATON_STRENG_DEPTH_OFFSET 0x10UL /** Reset value of the DEPTH register of the STRENG Unit. */ #define ATON_STRENG_DEPTH_DT \ (ATON_STRENG_DEPTH_SIZE_DT << ATON_STRENG_DEPTH_SIZE_LSB) | \ (ATON_STRENG_DEPTH_OFFSET_DT << ATON_STRENG_DEPTH_OFFSET_LSB) /** Description of the DEPTH register. */ #define ATON_STRENG_DEPTH_DESC "Depth for batch mode" /** Address of the DEPTH register of one of the STRENG Units. */ #define ATON_STRENG_DEPTH_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_DEPTH_OFFSET) /** Get the content of the DEPTH register of one of the STRENG Units. */ #define ATON_STRENG_DEPTH_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_DEPTH_ADDR(UNIT))) /** Set the content of the DEPTH register of one of the STRENG Units. */ #define ATON_STRENG_DEPTH_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_DEPTH_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DEPTH register. * * \return the description of DEPTH register */ static inline const int8_t *ATON_STRENG_DEPTH_GetDesc(void) { return (const int8_t *)ATON_STRENG_DEPTH_DESC; } /** * Get the offset of the DEPTH register. * * \return the offset of DEPTH register */ static inline uint32_t ATON_STRENG_DEPTH_GetOffset(void) { return ATON_STRENG_DEPTH_OFFSET; } /** * Get the address of the DEPTH register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTH register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of DEPTH register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_DEPTH_GetAddr(uint32_t instance) { return ATON_STRENG_DEPTH_ADDR(instance); } /** * Read the content of the DEPTH register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTH register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of DEPTH register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_DEPTH_Get(uint32_t instance) { return ATON_STRENG_DEPTH_GET(instance); } /** * Write the content of the DEPTH register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTH register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_DEPTH_Set(uint32_t instance, uint32_t data) { ATON_STRENG_DEPTH_SET(instance, data); } /* ------------------------------------------------------------ SIZE field of the DEPTH register ------------------------------------------------------------ */ /** Description of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SIZE_DESC "Batch depth (subpix per pixel) (RO when CTRL.RUNNING)" /** Offset of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SIZE_LSB 0UL /** Size in bits of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SIZE_W (16UL) /** Mask for retrieving the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SIZE_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SIZE_DT 0x0UL /** Access rights of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SIZE_AC "RW" /** Check whether access to the SIZE field of the DEPTH register is secured or not. */ #define ATON_STRENG_DEPTH_SIZE_S 0 /** Check whether access to the SIZE field of the DEPTH register is privileged or not. */ #define ATON_STRENG_DEPTH_SIZE_P 0 /** Read the content of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_GET_SIZE(REG) ATON_GET_FIELD(REG, ATON_STRENG_DEPTH_SIZE_LSB, ATON_STRENG_DEPTH_SIZE_W) /** Modify the content of the SIZE field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SET_SIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_DEPTH_SIZE_LSB, ATON_STRENG_DEPTH_SIZE_W, DATA) /** * Get the description of the SIZE field of DEPTH register. * * \return the description of the SIZE field of DEPTH register */ static inline const int8_t *ATON_STRENG_DEPTH_SIZE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_DEPTH_SIZE_DESC; } /** * Read the content of the SIZE field of the DEPTH register. * * \param[in] reg is the value of the DEPTH register * * \return the content of the SIZE field belonging to DEPTH register */ static inline uint32_t ATON_STRENG_DEPTH_Get_SIZE(uint32_t reg) { return ATON_STRENG_DEPTH_GET_SIZE(reg); } /** * Write the content of the SIZE field of the DEPTH register. * * \param[in] reg is the value of the DEPTH register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the SIZE field belonging to DEPTH register */ static inline uint32_t ATON_STRENG_DEPTH_Set_SIZE(uint32_t reg, uint32_t data) { return ATON_STRENG_DEPTH_SET_SIZE(reg, data); } /* ----------------------------------------------------------- OFFSET field of the DEPTH register ----------------------------------------------------------- */ /** Description of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_OFFSET_DESC "Offset (bytes) between batches (RO when CTRL.RUNNING)" /** Offset of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_OFFSET_LSB 16UL /** Size in bits of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_OFFSET_W (16UL) /** Mask for retrieving the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_OFFSET_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_OFFSET_DT 0x0UL /** Access rights of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_OFFSET_AC "RW" /** Check whether access to the OFFSET field of the DEPTH register is secured or not. */ #define ATON_STRENG_DEPTH_OFFSET_S 0 /** Check whether access to the OFFSET field of the DEPTH register is privileged or not. */ #define ATON_STRENG_DEPTH_OFFSET_P 0 /** Read the content of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_GET_OFFSET(REG) ATON_GET_FIELD(REG, ATON_STRENG_DEPTH_OFFSET_LSB, ATON_STRENG_DEPTH_OFFSET_W) /** Modify the content of the OFFSET field of the DEPTH register. */ #define ATON_STRENG_DEPTH_SET_OFFSET(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_DEPTH_OFFSET_LSB, ATON_STRENG_DEPTH_OFFSET_W, DATA) /** * Get the description of the OFFSET field of DEPTH register. * * \return the description of the OFFSET field of DEPTH register */ static inline const int8_t *ATON_STRENG_DEPTH_OFFSET_GetdDesc(void) { return (const int8_t *)ATON_STRENG_DEPTH_OFFSET_DESC; } /** * Read the content of the OFFSET field of the DEPTH register. * * \param[in] reg is the value of the DEPTH register * * \return the content of the OFFSET field belonging to DEPTH register */ static inline uint32_t ATON_STRENG_DEPTH_Get_OFFSET(uint32_t reg) { return ATON_STRENG_DEPTH_GET_OFFSET(reg); } /** * Write the content of the OFFSET field of the DEPTH register. * * \param[in] reg is the value of the DEPTH register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the OFFSET field belonging to DEPTH register */ static inline uint32_t ATON_STRENG_DEPTH_Set_OFFSET(uint32_t reg, uint32_t data) { return ATON_STRENG_DEPTH_SET_OFFSET(reg, data); } /* ******************************************************** STRD register of one of the STRENG Units ******************************************************** */ /** Offset of the STRD register from the base address of the STRENG Unit. */ #define ATON_STRENG_STRD_OFFSET 0x14UL /** Reset value of the STRD register of the STRENG Unit. */ #define ATON_STRENG_STRD_DT \ (ATON_STRENG_STRD_LOFF_DT << ATON_STRENG_STRD_LOFF_LSB) | \ (ATON_STRENG_STRD_FGAP_DT << ATON_STRENG_STRD_FGAP_LSB) | \ (ATON_STRENG_STRD_BGAP_DT << ATON_STRENG_STRD_BGAP_LSB) /** Description of the STRD register. */ #define ATON_STRENG_STRD_DESC "Stride" /** Address of the STRD register of one of the STRENG Units. */ #define ATON_STRENG_STRD_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_STRD_OFFSET) /** Get the content of the STRD register of one of the STRENG Units. */ #define ATON_STRENG_STRD_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_STRD_ADDR(UNIT))) /** Set the content of the STRD register of one of the STRENG Units. */ #define ATON_STRENG_STRD_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_STRD_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of STRD register. * * \return the description of STRD register */ static inline const int8_t *ATON_STRENG_STRD_GetDesc(void) { return (const int8_t *)ATON_STRENG_STRD_DESC; } /** * Get the offset of the STRD register. * * \return the offset of STRD register */ static inline uint32_t ATON_STRENG_STRD_GetOffset(void) { return ATON_STRENG_STRD_OFFSET; } /** * Get the address of the STRD register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STRD register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of STRD register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_STRD_GetAddr(uint32_t instance) { return ATON_STRENG_STRD_ADDR(instance); } /** * Read the content of the STRD register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STRD register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of STRD register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_STRD_Get(uint32_t instance) { return ATON_STRENG_STRD_GET(instance); } /** * Write the content of the STRD register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STRD register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_STRD_Set(uint32_t instance, uint32_t data) { ATON_STRENG_STRD_SET(instance, data); } /* ------------------------------------------------------------ LOFF field of the STRD register ------------------------------------------------------------- */ /** Description of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_LOFF_DESC "Memory offset (bytes) between line starts (RO when CTRL.RUNNING)" /** Offset of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_LOFF_LSB 0UL /** Size in bits of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_LOFF_W (16UL) /** Mask for retrieving the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_LOFF_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_LOFF_DT 0x0UL /** Access rights of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_LOFF_AC "RW" /** Check whether access to the LOFF field of the STRD register is secured or not. */ #define ATON_STRENG_STRD_LOFF_S 0 /** Check whether access to the LOFF field of the STRD register is privileged or not. */ #define ATON_STRENG_STRD_LOFF_P 0 /** Read the content of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_GET_LOFF(REG) ATON_GET_FIELD(REG, ATON_STRENG_STRD_LOFF_LSB, ATON_STRENG_STRD_LOFF_W) /** Modify the content of the LOFF field of the STRD register. */ #define ATON_STRENG_STRD_SET_LOFF(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STRD_LOFF_LSB, ATON_STRENG_STRD_LOFF_W, DATA) /** * Get the description of the LOFF field of STRD register. * * \return the description of the LOFF field of STRD register */ static inline const int8_t *ATON_STRENG_STRD_LOFF_GetdDesc(void) { return (const int8_t *)ATON_STRENG_STRD_LOFF_DESC; } /** * Read the content of the LOFF field of the STRD register. * * \param[in] reg is the value of the STRD register * * \return the content of the LOFF field belonging to STRD register */ static inline uint32_t ATON_STRENG_STRD_Get_LOFF(uint32_t reg) { return ATON_STRENG_STRD_GET_LOFF(reg); } /** * Write the content of the LOFF field of the STRD register. * * \param[in] reg is the value of the STRD register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the LOFF field belonging to STRD register */ static inline uint32_t ATON_STRENG_STRD_Set_LOFF(uint32_t reg, uint32_t data) { return ATON_STRENG_STRD_SET_LOFF(reg, data); } /* ------------------------------------------------------------ FGAP field of the STRD register ------------------------------------------------------------- */ /** Description of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_FGAP_DESC "Memory gap in bits in front of each pixel (RO when CTRL.RUNNING)" /** Offset of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_FGAP_LSB 16UL /** Size in bits of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_FGAP_W (6UL) /** Mask for retrieving the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_FGAP_MASK ATON_FIELD_MASK(16UL, 6UL) /** Reset value of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_FGAP_DT 0x0UL /** Access rights of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_FGAP_AC "RW" /** Check whether access to the FGAP field of the STRD register is secured or not. */ #define ATON_STRENG_STRD_FGAP_S 0 /** Check whether access to the FGAP field of the STRD register is privileged or not. */ #define ATON_STRENG_STRD_FGAP_P 0 /** Read the content of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_GET_FGAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_STRD_FGAP_LSB, ATON_STRENG_STRD_FGAP_W) /** Modify the content of the FGAP field of the STRD register. */ #define ATON_STRENG_STRD_SET_FGAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STRD_FGAP_LSB, ATON_STRENG_STRD_FGAP_W, DATA) /** * Get the description of the FGAP field of STRD register. * * \return the description of the FGAP field of STRD register */ static inline const int8_t *ATON_STRENG_STRD_FGAP_GetdDesc(void) { return (const int8_t *)ATON_STRENG_STRD_FGAP_DESC; } /** * Read the content of the FGAP field of the STRD register. * * \param[in] reg is the value of the STRD register * * \return the content of the FGAP field belonging to STRD register */ static inline uint32_t ATON_STRENG_STRD_Get_FGAP(uint32_t reg) { return ATON_STRENG_STRD_GET_FGAP(reg); } /** * Write the content of the FGAP field of the STRD register. * * \param[in] reg is the value of the STRD register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the FGAP field belonging to STRD register */ static inline uint32_t ATON_STRENG_STRD_Set_FGAP(uint32_t reg, uint32_t data) { return ATON_STRENG_STRD_SET_FGAP(reg, data); } /* ------------------------------------------------------------ BGAP field of the STRD register ------------------------------------------------------------- */ /** Description of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_BGAP_DESC "Memory gap in bits after each pixel (RO when CTRL.RUNNING)" /** Offset of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_BGAP_LSB 24UL /** Size in bits of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_BGAP_W (6UL) /** Mask for retrieving the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_BGAP_MASK ATON_FIELD_MASK(24UL, 6UL) /** Reset value of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_BGAP_DT 0x0UL /** Access rights of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_BGAP_AC "RW" /** Check whether access to the BGAP field of the STRD register is secured or not. */ #define ATON_STRENG_STRD_BGAP_S 0 /** Check whether access to the BGAP field of the STRD register is privileged or not. */ #define ATON_STRENG_STRD_BGAP_P 0 /** Read the content of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_GET_BGAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_STRD_BGAP_LSB, ATON_STRENG_STRD_BGAP_W) /** Modify the content of the BGAP field of the STRD register. */ #define ATON_STRENG_STRD_SET_BGAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STRD_BGAP_LSB, ATON_STRENG_STRD_BGAP_W, DATA) /** * Get the description of the BGAP field of STRD register. * * \return the description of the BGAP field of STRD register */ static inline const int8_t *ATON_STRENG_STRD_BGAP_GetdDesc(void) { return (const int8_t *)ATON_STRENG_STRD_BGAP_DESC; } /** * Read the content of the BGAP field of the STRD register. * * \param[in] reg is the value of the STRD register * * \return the content of the BGAP field belonging to STRD register */ static inline uint32_t ATON_STRENG_STRD_Get_BGAP(uint32_t reg) { return ATON_STRENG_STRD_GET_BGAP(reg); } /** * Write the content of the BGAP field of the STRD register. * * \param[in] reg is the value of the STRD register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the BGAP field belonging to STRD register */ static inline uint32_t ATON_STRENG_STRD_Set_BGAP(uint32_t reg, uint32_t data) { return ATON_STRENG_STRD_SET_BGAP(reg, data); } /* ****************************************************** FOFFSET register of one of the STRENG Units ******************************************************* */ /** Offset of the FOFFSET register from the base address of the STRENG Unit. */ #define ATON_STRENG_FOFFSET_OFFSET 0x18UL /** Reset value of the FOFFSET register of the STRENG Unit. */ #define ATON_STRENG_FOFFSET_DT \ (ATON_STRENG_FOFFSET_REG_DT << ATON_STRENG_FOFFSET_REG_LSB) /** Description of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_DESC "Frame offset within frame repetition loop" /** Address of the FOFFSET register of one of the STRENG Units. */ #define ATON_STRENG_FOFFSET_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FOFFSET_OFFSET) /** Get the content of the FOFFSET register of one of the STRENG Units. */ #define ATON_STRENG_FOFFSET_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FOFFSET_ADDR(UNIT))) /** Set the content of the FOFFSET register of one of the STRENG Units. */ #define ATON_STRENG_FOFFSET_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FOFFSET_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FOFFSET register. * * \return the description of FOFFSET register */ static inline const int8_t *ATON_STRENG_FOFFSET_GetDesc(void) { return (const int8_t *)ATON_STRENG_FOFFSET_DESC; } /** * Get the offset of the FOFFSET register. * * \return the offset of FOFFSET register */ static inline uint32_t ATON_STRENG_FOFFSET_GetOffset(void) { return ATON_STRENG_FOFFSET_OFFSET; } /** * Get the address of the FOFFSET register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FOFFSET register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of FOFFSET register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FOFFSET_GetAddr(uint32_t instance) { return ATON_STRENG_FOFFSET_ADDR(instance); } /** * Read the content of the FOFFSET register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FOFFSET register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of FOFFSET register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FOFFSET_Get(uint32_t instance) { return ATON_STRENG_FOFFSET_GET(instance); } /** * Write the content of the FOFFSET register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FOFFSET register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_FOFFSET_Set(uint32_t instance, uint32_t data) { ATON_STRENG_FOFFSET_SET(instance, data); } /* ----------------------------------------------------------- REG field of the FOFFSET register ------------------------------------------------------------ */ /** Description of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_REG_DESC "Offset between multiple frames within frame repetition loop (RO when CTRL.RUNNING)" /** Offset of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_REG_LSB 0UL /** Size in bits of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_REG_W (32UL) /** Mask for retrieving the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_REG_DT 0x0UL /** Access rights of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_REG_AC "RW" /** Check whether access to the REG field of the FOFFSET register is secured or not. */ #define ATON_STRENG_FOFFSET_REG_S 0 /** Check whether access to the REG field of the FOFFSET register is privileged or not. */ #define ATON_STRENG_FOFFSET_REG_P 0 /** Read the content of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FOFFSET_REG_LSB, ATON_STRENG_FOFFSET_REG_W) /** Modify the content of the REG field of the FOFFSET register. */ #define ATON_STRENG_FOFFSET_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FOFFSET_REG_LSB, ATON_STRENG_FOFFSET_REG_W, DATA) /** * Get the description of the REG field of FOFFSET register. * * \return the description of the REG field of FOFFSET register */ static inline const int8_t *ATON_STRENG_FOFFSET_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_FOFFSET_REG_DESC; } /** * Read the content of the REG field of the FOFFSET register. * * \param[in] reg is the value of the FOFFSET register * * \return the content of the REG field belonging to FOFFSET register */ static inline uint32_t ATON_STRENG_FOFFSET_Get_REG(uint32_t reg) { return ATON_STRENG_FOFFSET_GET_REG(reg); } /** * Write the content of the REG field of the FOFFSET register. * * \param[in] reg is the value of the FOFFSET register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to FOFFSET register */ static inline uint32_t ATON_STRENG_FOFFSET_Set_REG(uint32_t reg, uint32_t data) { return ATON_STRENG_FOFFSET_SET_REG(reg, data); } /* ***************************************************** FRAME_RPT register of one of the STRENG Units ****************************************************** */ /** Offset of the FRAME_RPT register from the base address of the STRENG Unit. */ #define ATON_STRENG_FRAME_RPT_OFFSET 0x1cUL /** Reset value of the FRAME_RPT register of the STRENG Unit. */ #define ATON_STRENG_FRAME_RPT_DT \ (ATON_STRENG_FRAME_RPT_REG_DT << ATON_STRENG_FRAME_RPT_REG_LSB) /** Description of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_DESC "Number of frames to loop on" /** Address of the FRAME_RPT register of one of the STRENG Units. */ #define ATON_STRENG_FRAME_RPT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FRAME_RPT_OFFSET) /** Get the content of the FRAME_RPT register of one of the STRENG Units. */ #define ATON_STRENG_FRAME_RPT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRAME_RPT_ADDR(UNIT))) /** Set the content of the FRAME_RPT register of one of the STRENG Units. */ #define ATON_STRENG_FRAME_RPT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRAME_RPT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FRAME_RPT register. * * \return the description of FRAME_RPT register */ static inline const int8_t *ATON_STRENG_FRAME_RPT_GetDesc(void) { return (const int8_t *)ATON_STRENG_FRAME_RPT_DESC; } /** * Get the offset of the FRAME_RPT register. * * \return the offset of FRAME_RPT register */ static inline uint32_t ATON_STRENG_FRAME_RPT_GetOffset(void) { return ATON_STRENG_FRAME_RPT_OFFSET; } /** * Get the address of the FRAME_RPT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRAME_RPT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of FRAME_RPT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FRAME_RPT_GetAddr(uint32_t instance) { return ATON_STRENG_FRAME_RPT_ADDR(instance); } /** * Read the content of the FRAME_RPT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRAME_RPT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of FRAME_RPT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FRAME_RPT_Get(uint32_t instance) { return ATON_STRENG_FRAME_RPT_GET(instance); } /** * Write the content of the FRAME_RPT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRAME_RPT register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_FRAME_RPT_Set(uint32_t instance, uint32_t data) { ATON_STRENG_FRAME_RPT_SET(instance, data); } /* ---------------------------------------------------------- REG field of the FRAME_RPT register ----------------------------------------------------------- */ /** Description of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_REG_DESC "Number of frames to loop on (RO when CTRL.RUNNING)" /** Offset of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_REG_LSB 0UL /** Size in bits of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_REG_W (32UL) /** Mask for retrieving the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_REG_DT 0x0UL /** Access rights of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_REG_AC "RW" /** Check whether access to the REG field of the FRAME_RPT register is secured or not. */ #define ATON_STRENG_FRAME_RPT_REG_S 0 /** Check whether access to the REG field of the FRAME_RPT register is privileged or not. */ #define ATON_STRENG_FRAME_RPT_REG_P 0 /** Read the content of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FRAME_RPT_REG_LSB, ATON_STRENG_FRAME_RPT_REG_W) /** Modify the content of the REG field of the FRAME_RPT register. */ #define ATON_STRENG_FRAME_RPT_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FRAME_RPT_REG_LSB, ATON_STRENG_FRAME_RPT_REG_W, DATA) /** * Get the description of the REG field of FRAME_RPT register. * * \return the description of the REG field of FRAME_RPT register */ static inline const int8_t *ATON_STRENG_FRAME_RPT_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_FRAME_RPT_REG_DESC; } /** * Read the content of the REG field of the FRAME_RPT register. * * \param[in] reg is the value of the FRAME_RPT register * * \return the content of the REG field belonging to FRAME_RPT register */ static inline uint32_t ATON_STRENG_FRAME_RPT_Get_REG(uint32_t reg) { return ATON_STRENG_FRAME_RPT_GET_REG(reg); } /** * Write the content of the REG field of the FRAME_RPT register. * * \param[in] reg is the value of the FRAME_RPT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to FRAME_RPT register */ static inline uint32_t ATON_STRENG_FRAME_RPT_Set_REG(uint32_t reg, uint32_t data) { return ATON_STRENG_FRAME_RPT_SET_REG(reg, data); } /* ****************************************************** FRPTOFF register of one of the STRENG Units ******************************************************* */ /** Offset of the FRPTOFF register from the base address of the STRENG Unit. */ #define ATON_STRENG_FRPTOFF_OFFSET 0x20UL /** Reset value of the FRPTOFF register of the STRENG Unit. */ #define ATON_STRENG_FRPTOFF_DT \ (ATON_STRENG_FRPTOFF_REG_DT << ATON_STRENG_FRPTOFF_REG_LSB) /** Description of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_DESC "Frame offset between frame repetition loops" /** Address of the FRPTOFF register of one of the STRENG Units. */ #define ATON_STRENG_FRPTOFF_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FRPTOFF_OFFSET) /** Get the content of the FRPTOFF register of one of the STRENG Units. */ #define ATON_STRENG_FRPTOFF_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRPTOFF_ADDR(UNIT))) /** Set the content of the FRPTOFF register of one of the STRENG Units. */ #define ATON_STRENG_FRPTOFF_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_FRPTOFF_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FRPTOFF register. * * \return the description of FRPTOFF register */ static inline const int8_t *ATON_STRENG_FRPTOFF_GetDesc(void) { return (const int8_t *)ATON_STRENG_FRPTOFF_DESC; } /** * Get the offset of the FRPTOFF register. * * \return the offset of FRPTOFF register */ static inline uint32_t ATON_STRENG_FRPTOFF_GetOffset(void) { return ATON_STRENG_FRPTOFF_OFFSET; } /** * Get the address of the FRPTOFF register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRPTOFF register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of FRPTOFF register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FRPTOFF_GetAddr(uint32_t instance) { return ATON_STRENG_FRPTOFF_ADDR(instance); } /** * Read the content of the FRPTOFF register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRPTOFF register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of FRPTOFF register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FRPTOFF_Get(uint32_t instance) { return ATON_STRENG_FRPTOFF_GET(instance); } /** * Write the content of the FRPTOFF register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FRPTOFF register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_FRPTOFF_Set(uint32_t instance, uint32_t data) { ATON_STRENG_FRPTOFF_SET(instance, data); } /* ----------------------------------------------------------- REG field of the FRPTOFF register ------------------------------------------------------------ */ /** Description of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_REG_DESC "Offset between frame repetition loops (RO when CTRL.RUNNING)" /** Offset of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_REG_LSB 0UL /** Size in bits of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_REG_W (32UL) /** Mask for retrieving the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_REG_DT 0x0UL /** Access rights of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_REG_AC "RW" /** Check whether access to the REG field of the FRPTOFF register is secured or not. */ #define ATON_STRENG_FRPTOFF_REG_S 0 /** Check whether access to the REG field of the FRPTOFF register is privileged or not. */ #define ATON_STRENG_FRPTOFF_REG_P 0 /** Read the content of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FRPTOFF_REG_LSB, ATON_STRENG_FRPTOFF_REG_W) /** Modify the content of the REG field of the FRPTOFF register. */ #define ATON_STRENG_FRPTOFF_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_FRPTOFF_REG_LSB, ATON_STRENG_FRPTOFF_REG_W, DATA) /** * Get the description of the REG field of FRPTOFF register. * * \return the description of the REG field of FRPTOFF register */ static inline const int8_t *ATON_STRENG_FRPTOFF_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_FRPTOFF_REG_DESC; } /** * Read the content of the REG field of the FRPTOFF register. * * \param[in] reg is the value of the FRPTOFF register * * \return the content of the REG field belonging to FRPTOFF register */ static inline uint32_t ATON_STRENG_FRPTOFF_Get_REG(uint32_t reg) { return ATON_STRENG_FRPTOFF_GET_REG(reg); } /** * Write the content of the REG field of the FRPTOFF register. * * \param[in] reg is the value of the FRPTOFF register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to FRPTOFF register */ static inline uint32_t ATON_STRENG_FRPTOFF_Set_REG(uint32_t reg, uint32_t data) { return ATON_STRENG_FRPTOFF_SET_REG(reg, data); } /* ******************************************************** POS register of one of the STRENG Units ********************************************************* */ /** Offset of the POS register from the base address of the STRENG Unit. */ #define ATON_STRENG_POS_OFFSET 0x24UL /** Reset value of the POS register of the STRENG Unit. */ #define ATON_STRENG_POS_DT \ (ATON_STRENG_POS_POS0_DT << ATON_STRENG_POS_POS0_LSB) | \ (ATON_STRENG_POS_POS1_DT << ATON_STRENG_POS_POS1_LSB) | \ (ATON_STRENG_POS_POS2_DT << ATON_STRENG_POS_POS2_LSB) | \ (ATON_STRENG_POS_WSWAP_DT << ATON_STRENG_POS_WSWAP_LSB) | \ (ATON_STRENG_POS_HSWAP_DT << ATON_STRENG_POS_HSWAP_LSB) | \ (ATON_STRENG_POS_BSWAP_DT << ATON_STRENG_POS_BSWAP_LSB) | \ (ATON_STRENG_POS_THROTTLE_DT << ATON_STRENG_POS_THROTTLE_LSB) | \ (ATON_STRENG_POS_GAPCYCLES_DT << ATON_STRENG_POS_GAPCYCLES_LSB) /** Description of the POS register. */ #define ATON_STRENG_POS_DESC "Position" /** Address of the POS register of one of the STRENG Units. */ #define ATON_STRENG_POS_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_POS_OFFSET) /** Get the content of the POS register of one of the STRENG Units. */ #define ATON_STRENG_POS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_POS_ADDR(UNIT))) /** Set the content of the POS register of one of the STRENG Units. */ #define ATON_STRENG_POS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_POS_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of POS register. * * \return the description of POS register */ static inline const int8_t *ATON_STRENG_POS_GetDesc(void) { return (const int8_t *)ATON_STRENG_POS_DESC; } /** * Get the offset of the POS register. * * \return the offset of POS register */ static inline uint32_t ATON_STRENG_POS_GetOffset(void) { return ATON_STRENG_POS_OFFSET; } /** * Get the address of the POS register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the POS register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of POS register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_POS_GetAddr(uint32_t instance) { return ATON_STRENG_POS_ADDR(instance); } /** * Read the content of the POS register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the POS register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of POS register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_POS_Get(uint32_t instance) { return ATON_STRENG_POS_GET(instance); } /** * Write the content of the POS register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the POS register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_POS_Set(uint32_t instance, uint32_t data) { ATON_STRENG_POS_SET(instance, data); } /* ------------------------------------------------------------- POS0 field of the POS register ------------------------------------------------------------- */ /** Description of the POS0 field of the POS register. */ #define ATON_STRENG_POS_POS0_DESC "Data at position 0 (RO when CTRL.RUNNING)" /** Offset of the POS0 field of the POS register. */ #define ATON_STRENG_POS_POS0_LSB 0UL /** Size in bits of the POS0 field of the POS register. */ #define ATON_STRENG_POS_POS0_W (2UL) /** Mask for retrieving the POS0 field of the POS register. */ #define ATON_STRENG_POS_POS0_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the POS0 field of the POS register. */ #define ATON_STRENG_POS_POS0_DT 0x0UL /** Access rights of the POS0 field of the POS register. */ #define ATON_STRENG_POS_POS0_AC "RW" /** Check whether access to the POS0 field of the POS register is secured or not. */ #define ATON_STRENG_POS_POS0_S 0 /** Check whether access to the POS0 field of the POS register is privileged or not. */ #define ATON_STRENG_POS_POS0_P 0 /** Read the content of the POS0 field of the POS register. */ #define ATON_STRENG_POS_GET_POS0(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_POS0_LSB, ATON_STRENG_POS_POS0_W) /** Modify the content of the POS0 field of the POS register. */ #define ATON_STRENG_POS_SET_POS0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_POS0_LSB, ATON_STRENG_POS_POS0_W, DATA) /** * Get the description of the POS0 field of POS register. * * \return the description of the POS0 field of POS register */ static inline const int8_t *ATON_STRENG_POS_POS0_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_POS0_DESC; } /** * Read the content of the POS0 field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the POS0 field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_POS0(uint32_t reg) { return ATON_STRENG_POS_GET_POS0(reg); } /** * Write the content of the POS0 field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the POS0 field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_POS0(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_POS0(reg, data); } /* ------------------------------------------------------------- POS1 field of the POS register ------------------------------------------------------------- */ /** Description of the POS1 field of the POS register. */ #define ATON_STRENG_POS_POS1_DESC "Data at position 1 (RO when CTRL.RUNNING)" /** Offset of the POS1 field of the POS register. */ #define ATON_STRENG_POS_POS1_LSB 2UL /** Size in bits of the POS1 field of the POS register. */ #define ATON_STRENG_POS_POS1_W (2UL) /** Mask for retrieving the POS1 field of the POS register. */ #define ATON_STRENG_POS_POS1_MASK ATON_FIELD_MASK(2UL, 2UL) /** Reset value of the POS1 field of the POS register. */ #define ATON_STRENG_POS_POS1_DT 0x1UL /** Access rights of the POS1 field of the POS register. */ #define ATON_STRENG_POS_POS1_AC "RW" /** Check whether access to the POS1 field of the POS register is secured or not. */ #define ATON_STRENG_POS_POS1_S 0 /** Check whether access to the POS1 field of the POS register is privileged or not. */ #define ATON_STRENG_POS_POS1_P 0 /** Read the content of the POS1 field of the POS register. */ #define ATON_STRENG_POS_GET_POS1(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_POS1_LSB, ATON_STRENG_POS_POS1_W) /** Modify the content of the POS1 field of the POS register. */ #define ATON_STRENG_POS_SET_POS1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_POS1_LSB, ATON_STRENG_POS_POS1_W, DATA) /** * Get the description of the POS1 field of POS register. * * \return the description of the POS1 field of POS register */ static inline const int8_t *ATON_STRENG_POS_POS1_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_POS1_DESC; } /** * Read the content of the POS1 field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the POS1 field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_POS1(uint32_t reg) { return ATON_STRENG_POS_GET_POS1(reg); } /** * Write the content of the POS1 field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the POS1 field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_POS1(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_POS1(reg, data); } /* ------------------------------------------------------------- POS2 field of the POS register ------------------------------------------------------------- */ /** Description of the POS2 field of the POS register. */ #define ATON_STRENG_POS_POS2_DESC "Data at position 2 (RO when CTRL.RUNNING)" /** Offset of the POS2 field of the POS register. */ #define ATON_STRENG_POS_POS2_LSB 4UL /** Size in bits of the POS2 field of the POS register. */ #define ATON_STRENG_POS_POS2_W (2UL) /** Mask for retrieving the POS2 field of the POS register. */ #define ATON_STRENG_POS_POS2_MASK ATON_FIELD_MASK(4UL, 2UL) /** Reset value of the POS2 field of the POS register. */ #define ATON_STRENG_POS_POS2_DT 0x2UL /** Access rights of the POS2 field of the POS register. */ #define ATON_STRENG_POS_POS2_AC "RW" /** Check whether access to the POS2 field of the POS register is secured or not. */ #define ATON_STRENG_POS_POS2_S 0 /** Check whether access to the POS2 field of the POS register is privileged or not. */ #define ATON_STRENG_POS_POS2_P 0 /** Read the content of the POS2 field of the POS register. */ #define ATON_STRENG_POS_GET_POS2(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_POS2_LSB, ATON_STRENG_POS_POS2_W) /** Modify the content of the POS2 field of the POS register. */ #define ATON_STRENG_POS_SET_POS2(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_POS2_LSB, ATON_STRENG_POS_POS2_W, DATA) /** * Get the description of the POS2 field of POS register. * * \return the description of the POS2 field of POS register */ static inline const int8_t *ATON_STRENG_POS_POS2_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_POS2_DESC; } /** * Read the content of the POS2 field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the POS2 field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_POS2(uint32_t reg) { return ATON_STRENG_POS_GET_POS2(reg); } /** * Write the content of the POS2 field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the POS2 field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_POS2(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_POS2(reg, data); } /* ------------------------------------------------------------ WSWAP field of the POS register ------------------------------------------------------------- */ /** Description of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_WSWAP_DESC "Swap 32 bits in 64 bits (RO when CTRL.RUNNING)" /** Offset of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_WSWAP_LSB 8UL /** Size in bits of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_WSWAP_W (1UL) /** Mask for retrieving the WSWAP field of the POS register. */ #define ATON_STRENG_POS_WSWAP_MASK ATON_FIELD_MASK(8UL, 1UL) /** Reset value of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_WSWAP_DT 0x0UL /** Access rights of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_WSWAP_AC "RW" /** Check whether access to the WSWAP field of the POS register is secured or not. */ #define ATON_STRENG_POS_WSWAP_S 0 /** Check whether access to the WSWAP field of the POS register is privileged or not. */ #define ATON_STRENG_POS_WSWAP_P 0 /** Read the content of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_GET_WSWAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_WSWAP_LSB, ATON_STRENG_POS_WSWAP_W) /** Modify the content of the WSWAP field of the POS register. */ #define ATON_STRENG_POS_SET_WSWAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_WSWAP_LSB, ATON_STRENG_POS_WSWAP_W, DATA) /** * Get the description of the WSWAP field of POS register. * * \return the description of the WSWAP field of POS register */ static inline const int8_t *ATON_STRENG_POS_WSWAP_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_WSWAP_DESC; } /** * Read the content of the WSWAP field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the WSWAP field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_WSWAP(uint32_t reg) { return ATON_STRENG_POS_GET_WSWAP(reg); } /** * Write the content of the WSWAP field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WSWAP field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_WSWAP(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_WSWAP(reg, data); } /* ------------------------------------------------------------ HSWAP field of the POS register ------------------------------------------------------------- */ /** Description of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_HSWAP_DESC "Swap 16 bits in 32 bits (RO when CTRL.RUNNING)" /** Offset of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_HSWAP_LSB 9UL /** Size in bits of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_HSWAP_W (1UL) /** Mask for retrieving the HSWAP field of the POS register. */ #define ATON_STRENG_POS_HSWAP_MASK ATON_FIELD_MASK(9UL, 1UL) /** Reset value of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_HSWAP_DT 0x0UL /** Access rights of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_HSWAP_AC "RW" /** Check whether access to the HSWAP field of the POS register is secured or not. */ #define ATON_STRENG_POS_HSWAP_S 0 /** Check whether access to the HSWAP field of the POS register is privileged or not. */ #define ATON_STRENG_POS_HSWAP_P 0 /** Read the content of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_GET_HSWAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_HSWAP_LSB, ATON_STRENG_POS_HSWAP_W) /** Modify the content of the HSWAP field of the POS register. */ #define ATON_STRENG_POS_SET_HSWAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_HSWAP_LSB, ATON_STRENG_POS_HSWAP_W, DATA) /** * Get the description of the HSWAP field of POS register. * * \return the description of the HSWAP field of POS register */ static inline const int8_t *ATON_STRENG_POS_HSWAP_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_HSWAP_DESC; } /** * Read the content of the HSWAP field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the HSWAP field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_HSWAP(uint32_t reg) { return ATON_STRENG_POS_GET_HSWAP(reg); } /** * Write the content of the HSWAP field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the HSWAP field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_HSWAP(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_HSWAP(reg, data); } /* ------------------------------------------------------------ BSWAP field of the POS register ------------------------------------------------------------- */ /** Description of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_BSWAP_DESC "Swap 8 bits in 16 bits (RO when CTRL.RUNNING)" /** Offset of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_BSWAP_LSB 10UL /** Size in bits of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_BSWAP_W (1UL) /** Mask for retrieving the BSWAP field of the POS register. */ #define ATON_STRENG_POS_BSWAP_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_BSWAP_DT 0x0UL /** Access rights of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_BSWAP_AC "RW" /** Check whether access to the BSWAP field of the POS register is secured or not. */ #define ATON_STRENG_POS_BSWAP_S 0 /** Check whether access to the BSWAP field of the POS register is privileged or not. */ #define ATON_STRENG_POS_BSWAP_P 0 /** Read the content of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_GET_BSWAP(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_BSWAP_LSB, ATON_STRENG_POS_BSWAP_W) /** Modify the content of the BSWAP field of the POS register. */ #define ATON_STRENG_POS_SET_BSWAP(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_BSWAP_LSB, ATON_STRENG_POS_BSWAP_W, DATA) /** * Get the description of the BSWAP field of POS register. * * \return the description of the BSWAP field of POS register */ static inline const int8_t *ATON_STRENG_POS_BSWAP_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_BSWAP_DESC; } /** * Read the content of the BSWAP field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the BSWAP field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_BSWAP(uint32_t reg) { return ATON_STRENG_POS_GET_BSWAP(reg); } /** * Write the content of the BSWAP field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the BSWAP field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_BSWAP(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_BSWAP(reg, data); } /* ----------------------------------------------------------- THROTTLE field of the POS register ----------------------------------------------------------- */ /** Description of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_THROTTLE_DESC "Transmit only ever N cycles (RO when CTRL.RUNNING)" /** Offset of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_THROTTLE_LSB 12UL /** Size in bits of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_THROTTLE_W (4UL) /** Mask for retrieving the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_THROTTLE_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_THROTTLE_DT 0x0UL /** Access rights of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_THROTTLE_AC "RW" /** Check whether access to the THROTTLE field of the POS register is secured or not. */ #define ATON_STRENG_POS_THROTTLE_S 0 /** Check whether access to the THROTTLE field of the POS register is privileged or not. */ #define ATON_STRENG_POS_THROTTLE_P 0 /** Read the content of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_GET_THROTTLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_THROTTLE_LSB, ATON_STRENG_POS_THROTTLE_W) /** Modify the content of the THROTTLE field of the POS register. */ #define ATON_STRENG_POS_SET_THROTTLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_THROTTLE_LSB, ATON_STRENG_POS_THROTTLE_W, DATA) /** * Get the description of the THROTTLE field of POS register. * * \return the description of the THROTTLE field of POS register */ static inline const int8_t *ATON_STRENG_POS_THROTTLE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_THROTTLE_DESC; } /** * Read the content of the THROTTLE field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the THROTTLE field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_THROTTLE(uint32_t reg) { return ATON_STRENG_POS_GET_THROTTLE(reg); } /** * Write the content of the THROTTLE field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the THROTTLE field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_THROTTLE(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_THROTTLE(reg, data); } /* ---------------------------------------------------------- GAPCYCLES field of the POS register ----------------------------------------------------------- */ /** Description of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GAPCYCLES_DESC "Dead cycles among lines (RO when CTRL.RUNNING)" /** Offset of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GAPCYCLES_LSB 16UL /** Size in bits of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GAPCYCLES_W (16UL) /** Mask for retrieving the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GAPCYCLES_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GAPCYCLES_DT 0x8UL /** Access rights of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GAPCYCLES_AC "RW" /** Check whether access to the GAPCYCLES field of the POS register is secured or not. */ #define ATON_STRENG_POS_GAPCYCLES_S 0 /** Check whether access to the GAPCYCLES field of the POS register is privileged or not. */ #define ATON_STRENG_POS_GAPCYCLES_P 0 /** Read the content of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_GET_GAPCYCLES(REG) ATON_GET_FIELD(REG, ATON_STRENG_POS_GAPCYCLES_LSB, ATON_STRENG_POS_GAPCYCLES_W) /** Modify the content of the GAPCYCLES field of the POS register. */ #define ATON_STRENG_POS_SET_GAPCYCLES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_POS_GAPCYCLES_LSB, ATON_STRENG_POS_GAPCYCLES_W, DATA) /** * Get the description of the GAPCYCLES field of POS register. * * \return the description of the GAPCYCLES field of POS register */ static inline const int8_t *ATON_STRENG_POS_GAPCYCLES_GetdDesc(void) { return (const int8_t *)ATON_STRENG_POS_GAPCYCLES_DESC; } /** * Read the content of the GAPCYCLES field of the POS register. * * \param[in] reg is the value of the POS register * * \return the content of the GAPCYCLES field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Get_GAPCYCLES(uint32_t reg) { return ATON_STRENG_POS_GET_GAPCYCLES(reg); } /** * Write the content of the GAPCYCLES field of the POS register. * * \param[in] reg is the value of the POS register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the GAPCYCLES field belonging to POS register */ static inline uint32_t ATON_STRENG_POS_Set_GAPCYCLES(uint32_t reg, uint32_t data) { return ATON_STRENG_POS_SET_GAPCYCLES(reg, data); } /* ******************************************************* EVENT register of one of the STRENG Units ******************************************************** */ /** Offset of the EVENT register from the base address of the STRENG Unit. */ #define ATON_STRENG_EVENT_OFFSET 0x28UL /** Reset value of the EVENT register of the STRENG Unit. */ #define ATON_STRENG_EVENT_DT \ (ATON_STRENG_EVENT_LEVEL_DT << ATON_STRENG_EVENT_LEVEL_LSB) | \ (ATON_STRENG_EVENT_TYPE_DT << ATON_STRENG_EVENT_TYPE_LSB) | \ (ATON_STRENG_EVENT_SET_DT << ATON_STRENG_EVENT_SET_LSB) | \ (ATON_STRENG_EVENT_EN_BUFBL_DT << ATON_STRENG_EVENT_EN_BUFBL_LSB) | \ (ATON_STRENG_EVENT_EN_MRK_DT << ATON_STRENG_EVENT_EN_MRK_LSB) | \ (ATON_STRENG_EVENT_EN_OFLOW_ADD_DT << ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB) | \ (ATON_STRENG_EVENT_EN_OFLOW_FRM_DT << ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB) | \ (ATON_STRENG_EVENT_EN_ILLCFG_DT << ATON_STRENG_EVENT_EN_ILLCFG_LSB) | \ (ATON_STRENG_EVENT_EN_FMTMM_DT << ATON_STRENG_EVENT_EN_FMTMM_LSB) | \ (ATON_STRENG_EVENT_EN_CLRMSGRCV_DT << ATON_STRENG_EVENT_EN_CLRMSGRCV_LSB) | \ (ATON_STRENG_EVENT_FRMTRG_EN_DT << ATON_STRENG_EVENT_FRMTRG_EN_LSB) | \ (ATON_STRENG_EVENT_FRMTRG_SRC_DT << ATON_STRENG_EVENT_FRMTRG_SRC_LSB) /** Description of the EVENT register. */ #define ATON_STRENG_EVENT_DESC "Event" /** Address of the EVENT register of one of the STRENG Units. */ #define ATON_STRENG_EVENT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_EVENT_OFFSET) /** Get the content of the EVENT register of one of the STRENG Units. */ #define ATON_STRENG_EVENT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_EVENT_ADDR(UNIT))) /** Set the content of the EVENT register of one of the STRENG Units. */ #define ATON_STRENG_EVENT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_EVENT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT register. * * \return the description of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_GetDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_DESC; } /** * Get the offset of the EVENT register. * * \return the offset of EVENT register */ static inline uint32_t ATON_STRENG_EVENT_GetOffset(void) { return ATON_STRENG_EVENT_OFFSET; } /** * Get the address of the EVENT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EVENT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of EVENT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_EVENT_GetAddr(uint32_t instance) { return ATON_STRENG_EVENT_ADDR(instance); } /** * Read the content of the EVENT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EVENT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of EVENT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_EVENT_Get(uint32_t instance) { return ATON_STRENG_EVENT_GET(instance); } /** * Write the content of the EVENT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EVENT register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_EVENT_Set(uint32_t instance, uint32_t data) { ATON_STRENG_EVENT_SET(instance, data); } /* ----------------------------------------------------------- LEVEL field of the EVENT register ------------------------------------------------------------ */ /** Description of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_LEVEL_DESC "Event level" /** Offset of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_LEVEL_LSB 0UL /** Size in bits of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_LEVEL_W (13UL) /** Mask for retrieving the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_LEVEL_MASK ATON_FIELD_MASK(0UL, 13UL) /** Reset value of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_LEVEL_DT 0x0UL /** Access rights of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_LEVEL_AC "RW" /** Check whether access to the LEVEL field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_LEVEL_S 0 /** Check whether access to the LEVEL field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_LEVEL_P 0 /** Read the content of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_LEVEL(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_LEVEL_LSB, ATON_STRENG_EVENT_LEVEL_W) /** Modify the content of the LEVEL field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_LEVEL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_LEVEL_LSB, ATON_STRENG_EVENT_LEVEL_W, DATA) /** * Get the description of the LEVEL field of EVENT register. * * \return the description of the LEVEL field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_LEVEL_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_LEVEL_DESC; } /** * Read the content of the LEVEL field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the LEVEL field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_LEVEL(uint32_t reg) { return ATON_STRENG_EVENT_GET_LEVEL(reg); } /** * Write the content of the LEVEL field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the LEVEL field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_LEVEL(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_LEVEL(reg, data); } /* ------------------------------------------------------------ TYPE field of the EVENT register ------------------------------------------------------------ */ /** Description of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_TYPE_DESC "Event type" /** Offset of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_TYPE_LSB 13UL /** Size in bits of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_TYPE_W (2UL) /** Mask for retrieving the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_TYPE_MASK ATON_FIELD_MASK(13UL, 2UL) /** Reset value of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_TYPE_DT 0x0UL /** Access rights of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_TYPE_AC "RW" /** Check whether access to the TYPE field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_TYPE_S 0 /** Check whether access to the TYPE field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_TYPE_P 0 /** Read the content of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_TYPE_LSB, ATON_STRENG_EVENT_TYPE_W) /** Modify the content of the TYPE field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_TYPE_LSB, ATON_STRENG_EVENT_TYPE_W, DATA) /** * Get the description of the TYPE field of EVENT register. * * \return the description of the TYPE field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_TYPE_DESC; } /** * Read the content of the TYPE field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the TYPE field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_TYPE(uint32_t reg) { return ATON_STRENG_EVENT_GET_TYPE(reg); } /** * Write the content of the TYPE field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the TYPE field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_TYPE(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_TYPE(reg, data); } /* ------------------------------------------------------------ SET field of the EVENT register ------------------------------------------------------------- */ /** Description of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_DESC "Activate event trigger" /** Offset of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_LSB 15UL /** Size in bits of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_W (1UL) /** Mask for retrieving the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_MASK ATON_FIELD_MASK(15UL, 1UL) /** Reset value of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_DT 0x0UL /** Access rights of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_AC "RW" /** Check whether access to the SET field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_SET_S 0 /** Check whether access to the SET field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_SET_P 0 /** Read the content of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_SET(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_SET_LSB, ATON_STRENG_EVENT_SET_W) /** Modify the content of the SET field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_SET(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_SET_LSB, ATON_STRENG_EVENT_SET_W, DATA) /** * Get the description of the SET field of EVENT register. * * \return the description of the SET field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_SET_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_SET_DESC; } /** * Read the content of the SET field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the SET field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_SET(uint32_t reg) { return ATON_STRENG_EVENT_GET_SET(reg); } /** * Write the content of the SET field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SET field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_SET(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_SET(reg, data); } /* ---------------------------------------------------------- EN_BUFBL field of the EVENT register ---------------------------------------------------------- */ /** Description of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_BUFBL_DESC "Enable buffer bandwith limit hit irq" /** Offset of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_BUFBL_LSB 16UL /** Size in bits of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_BUFBL_W (1UL) /** Mask for retrieving the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_BUFBL_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_BUFBL_DT 0x0UL /** Access rights of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_BUFBL_AC "RW" /** Check whether access to the EN_BUFBL field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_BUFBL_S 0 /** Check whether access to the EN_BUFBL field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_BUFBL_P 0 /** Read the content of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_BUFBL(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_BUFBL_LSB, ATON_STRENG_EVENT_EN_BUFBL_W) /** Modify the content of the EN_BUFBL field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_EN_BUFBL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_BUFBL_LSB, ATON_STRENG_EVENT_EN_BUFBL_W, DATA) /** * Get the description of the EN_BUFBL field of EVENT register. * * \return the description of the EN_BUFBL field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_BUFBL_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_BUFBL_DESC; } /** * Read the content of the EN_BUFBL field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_BUFBL field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_BUFBL(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_BUFBL(reg); } /** * Write the content of the EN_BUFBL field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN_BUFBL field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_EN_BUFBL(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_EN_BUFBL(reg, data); } /* ----------------------------------------------------------- EN_MRK field of the EVENT register ----------------------------------------------------------- */ /** Description of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_MRK_DESC "Enable marker hit irq" /** Offset of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_MRK_LSB 17UL /** Size in bits of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_MRK_W (1UL) /** Mask for retrieving the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_MRK_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_MRK_DT 0x0UL /** Access rights of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_MRK_AC "RW" /** Check whether access to the EN_MRK field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_MRK_S 0 /** Check whether access to the EN_MRK field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_MRK_P 0 /** Read the content of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_MRK(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_MRK_LSB, ATON_STRENG_EVENT_EN_MRK_W) /** Modify the content of the EN_MRK field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_EN_MRK(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_MRK_LSB, ATON_STRENG_EVENT_EN_MRK_W, DATA) /** * Get the description of the EN_MRK field of EVENT register. * * \return the description of the EN_MRK field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_MRK_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_MRK_DESC; } /** * Read the content of the EN_MRK field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_MRK field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_MRK(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_MRK(reg); } /** * Write the content of the EN_MRK field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN_MRK field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_EN_MRK(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_EN_MRK(reg, data); } /* -------------------------------------------------------- EN_OFLOW_ADD field of the EVENT register -------------------------------------------------------- */ /** Description of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_DESC "Enable address limiter hit irq" /** Offset of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB 18UL /** Size in bits of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_W (1UL) /** Mask for retrieving the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_DT 0x0UL /** Access rights of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_AC "RW" /** Check whether access to the EN_OFLOW_ADD field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_S 0 /** Check whether access to the EN_OFLOW_ADD field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_OFLOW_ADD_P 0 /** Read the content of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_OFLOW_ADD(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB, ATON_STRENG_EVENT_EN_OFLOW_ADD_W) /** Modify the content of the EN_OFLOW_ADD field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_EN_OFLOW_ADD(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_ADD_LSB, ATON_STRENG_EVENT_EN_OFLOW_ADD_W, DATA) /** * Get the description of the EN_OFLOW_ADD field of EVENT register. * * \return the description of the EN_OFLOW_ADD field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_OFLOW_ADD_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_OFLOW_ADD_DESC; } /** * Read the content of the EN_OFLOW_ADD field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_OFLOW_ADD field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_OFLOW_ADD(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_OFLOW_ADD(reg); } /** * Write the content of the EN_OFLOW_ADD field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN_OFLOW_ADD field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_EN_OFLOW_ADD(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_EN_OFLOW_ADD(reg, data); } /* -------------------------------------------------------- EN_OFLOW_FRM field of the EVENT register -------------------------------------------------------- */ /** Description of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_DESC "Enable frame limiter hit irq" /** Offset of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB 19UL /** Size in bits of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_W (1UL) /** Mask for retrieving the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_DT 0x0UL /** Access rights of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_AC "RW" /** Check whether access to the EN_OFLOW_FRM field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_S 0 /** Check whether access to the EN_OFLOW_FRM field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_OFLOW_FRM_P 0 /** Read the content of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_OFLOW_FRM(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB, ATON_STRENG_EVENT_EN_OFLOW_FRM_W) /** Modify the content of the EN_OFLOW_FRM field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_EN_OFLOW_FRM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_OFLOW_FRM_LSB, ATON_STRENG_EVENT_EN_OFLOW_FRM_W, DATA) /** * Get the description of the EN_OFLOW_FRM field of EVENT register. * * \return the description of the EN_OFLOW_FRM field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_OFLOW_FRM_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_OFLOW_FRM_DESC; } /** * Read the content of the EN_OFLOW_FRM field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_OFLOW_FRM field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_OFLOW_FRM(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_OFLOW_FRM(reg); } /** * Write the content of the EN_OFLOW_FRM field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN_OFLOW_FRM field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_EN_OFLOW_FRM(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_EN_OFLOW_FRM(reg, data); } /* --------------------------------------------------------- EN_ILLCFG field of the EVENT register ---------------------------------------------------------- */ /** Description of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_ILLCFG_DESC "Enable illegal configuration irq" /** Offset of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_ILLCFG_LSB 20UL /** Size in bits of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_ILLCFG_W (1UL) /** Mask for retrieving the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_ILLCFG_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_ILLCFG_DT 0x0UL /** Access rights of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_ILLCFG_AC "RW" /** Check whether access to the EN_ILLCFG field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_ILLCFG_S 0 /** Check whether access to the EN_ILLCFG field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_ILLCFG_P 0 /** Read the content of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_ILLCFG(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_ILLCFG_LSB, ATON_STRENG_EVENT_EN_ILLCFG_W) /** Modify the content of the EN_ILLCFG field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_EN_ILLCFG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_ILLCFG_LSB, ATON_STRENG_EVENT_EN_ILLCFG_W, DATA) /** * Get the description of the EN_ILLCFG field of EVENT register. * * \return the description of the EN_ILLCFG field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_ILLCFG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_ILLCFG_DESC; } /** * Read the content of the EN_ILLCFG field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_ILLCFG field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_ILLCFG(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_ILLCFG(reg); } /** * Write the content of the EN_ILLCFG field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN_ILLCFG field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_EN_ILLCFG(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_EN_ILLCFG(reg, data); } /* ---------------------------------------------------------- EN_FMTMM field of the EVENT register ---------------------------------------------------------- */ /** Description of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_FMTMM_DESC "Enable format mismatch irq" /** Offset of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_FMTMM_LSB 21UL /** Size in bits of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_FMTMM_W (1UL) /** Mask for retrieving the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_FMTMM_MASK ATON_FIELD_MASK(21UL, 1UL) /** Reset value of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_FMTMM_DT 0x0UL /** Access rights of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_FMTMM_AC "RW" /** Check whether access to the EN_FMTMM field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_FMTMM_S 0 /** Check whether access to the EN_FMTMM field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_FMTMM_P 0 /** Read the content of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_FMTMM(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_FMTMM_LSB, ATON_STRENG_EVENT_EN_FMTMM_W) /** Modify the content of the EN_FMTMM field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_EN_FMTMM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_EN_FMTMM_LSB, ATON_STRENG_EVENT_EN_FMTMM_W, DATA) /** * Get the description of the EN_FMTMM field of EVENT register. * * \return the description of the EN_FMTMM field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_FMTMM_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_FMTMM_DESC; } /** * Read the content of the EN_FMTMM field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_FMTMM field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_FMTMM(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_FMTMM(reg); } /** * Write the content of the EN_FMTMM field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN_FMTMM field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_EN_FMTMM(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_EN_FMTMM(reg, data); } /* -------------------------------------------------------- EN_CLRMSGRCV field of the EVENT register -------------------------------------------------------- */ /** Description of the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_DESC "Reserved" /** Offset of the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_LSB 22UL /** Size in bits of the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_W (1UL) /** Mask for retrieving the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_MASK ATON_FIELD_MASK(22UL, 1UL) /** Reset value of the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_DT 0x0UL /** Access rights of the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_AC "R" /** Check whether access to the EN_CLRMSGRCV field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_S 0 /** Check whether access to the EN_CLRMSGRCV field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_EN_CLRMSGRCV_P 0 /** Read the content of the EN_CLRMSGRCV field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_EN_CLRMSGRCV(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_EN_CLRMSGRCV_LSB, ATON_STRENG_EVENT_EN_CLRMSGRCV_W) /** * Get the description of the EN_CLRMSGRCV field of EVENT register. * * \return the description of the EN_CLRMSGRCV field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_EN_CLRMSGRCV_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_EN_CLRMSGRCV_DESC; } /** * Read the content of the EN_CLRMSGRCV field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the EN_CLRMSGRCV field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_EN_CLRMSGRCV(uint32_t reg) { return ATON_STRENG_EVENT_GET_EN_CLRMSGRCV(reg); } /* --------------------------------------------------------- FRMTRG_EN field of the EVENT register ---------------------------------------------------------- */ /** Description of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_EN_DESC "Enable synchronizations signals between engines (RO when CTRL.RUNNING)" /** Offset of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_EN_LSB 23UL /** Size in bits of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_EN_W (1UL) /** Mask for retrieving the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_EN_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_EN_DT 0x0UL /** Access rights of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_EN_AC "RW" /** Check whether access to the FRMTRG_EN field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_FRMTRG_EN_S 0 /** Check whether access to the FRMTRG_EN field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_FRMTRG_EN_P 0 /** Read the content of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_FRMTRG_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_EN_LSB, ATON_STRENG_EVENT_FRMTRG_EN_W) /** Modify the content of the FRMTRG_EN field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_FRMTRG_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_EN_LSB, ATON_STRENG_EVENT_FRMTRG_EN_W, DATA) /** * Get the description of the FRMTRG_EN field of EVENT register. * * \return the description of the FRMTRG_EN field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_FRMTRG_EN_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_FRMTRG_EN_DESC; } /** * Read the content of the FRMTRG_EN field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the FRMTRG_EN field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_FRMTRG_EN(uint32_t reg) { return ATON_STRENG_EVENT_GET_FRMTRG_EN(reg); } /** * Write the content of the FRMTRG_EN field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FRMTRG_EN field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_FRMTRG_EN(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_FRMTRG_EN(reg, data); } /* --------------------------------------------------------- FRMTRG_SRC field of the EVENT register --------------------------------------------------------- */ /** Description of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_DESC "Synchronization signals source engine (RO when CTRL.RUNNING)" /** Offset of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_LSB 24UL /** Size in bits of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_W (5UL) /** Mask for retrieving the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_MASK ATON_FIELD_MASK(24UL, 5UL) /** Reset value of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_DT 0x0UL /** Access rights of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_AC "RW" /** Check whether access to the FRMTRG_SRC field of the EVENT register is secured or not. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_S 0 /** Check whether access to the FRMTRG_SRC field of the EVENT register is privileged or not. */ #define ATON_STRENG_EVENT_FRMTRG_SRC_P 0 /** Read the content of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_GET_FRMTRG_SRC(REG) ATON_GET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_SRC_LSB, ATON_STRENG_EVENT_FRMTRG_SRC_W) /** Modify the content of the FRMTRG_SRC field of the EVENT register. */ #define ATON_STRENG_EVENT_SET_FRMTRG_SRC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EVENT_FRMTRG_SRC_LSB, ATON_STRENG_EVENT_FRMTRG_SRC_W, DATA) /** * Get the description of the FRMTRG_SRC field of EVENT register. * * \return the description of the FRMTRG_SRC field of EVENT register */ static inline const int8_t *ATON_STRENG_EVENT_FRMTRG_SRC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EVENT_FRMTRG_SRC_DESC; } /** * Read the content of the FRMTRG_SRC field of the EVENT register. * * \param[in] reg is the value of the EVENT register * * \return the content of the FRMTRG_SRC field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Get_FRMTRG_SRC(uint32_t reg) { return ATON_STRENG_EVENT_GET_FRMTRG_SRC(reg); } /** * Write the content of the FRMTRG_SRC field of the EVENT register. * * \param[in] reg is the value of the EVENT register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the FRMTRG_SRC field belonging to EVENT register */ static inline uint32_t ATON_STRENG_EVENT_Set_FRMTRG_SRC(uint32_t reg, uint32_t data) { return ATON_STRENG_EVENT_SET_FRMTRG_SRC(reg, data); } /* ****************************************************** STOPTAG register of one of the STRENG Units ******************************************************* */ /** Offset of the STOPTAG register from the base address of the STRENG Unit. */ #define ATON_STRENG_STOPTAG_OFFSET 0x2cUL /** Reset value of the STOPTAG register of the STRENG Unit. */ #define ATON_STRENG_STOPTAG_DT \ (ATON_STRENG_STOPTAG_EN_DT << ATON_STRENG_STOPTAG_EN_LSB) | \ (ATON_STRENG_STOPTAG_TAG_DT << ATON_STRENG_STOPTAG_TAG_LSB) /** Description of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_DESC "RAW file stop tag" /** Address of the STOPTAG register of one of the STRENG Units. */ #define ATON_STRENG_STOPTAG_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_STOPTAG_OFFSET) /** Get the content of the STOPTAG register of one of the STRENG Units. */ #define ATON_STRENG_STOPTAG_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_STOPTAG_ADDR(UNIT))) /** Set the content of the STOPTAG register of one of the STRENG Units. */ #define ATON_STRENG_STOPTAG_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_STOPTAG_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of STOPTAG register. * * \return the description of STOPTAG register */ static inline const int8_t *ATON_STRENG_STOPTAG_GetDesc(void) { return (const int8_t *)ATON_STRENG_STOPTAG_DESC; } /** * Get the offset of the STOPTAG register. * * \return the offset of STOPTAG register */ static inline uint32_t ATON_STRENG_STOPTAG_GetOffset(void) { return ATON_STRENG_STOPTAG_OFFSET; } /** * Get the address of the STOPTAG register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STOPTAG register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of STOPTAG register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_STOPTAG_GetAddr(uint32_t instance) { return ATON_STRENG_STOPTAG_ADDR(instance); } /** * Read the content of the STOPTAG register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STOPTAG register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of STOPTAG register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_STOPTAG_Get(uint32_t instance) { return ATON_STRENG_STOPTAG_GET(instance); } /** * Write the content of the STOPTAG register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the STOPTAG register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_STOPTAG_Set(uint32_t instance, uint32_t data) { ATON_STRENG_STOPTAG_SET(instance, data); } /* ------------------------------------------------------------ EN field of the STOPTAG register ------------------------------------------------------------ */ /** Description of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_EN_DESC "Enable RAW file stop tag (RO when CTRL.RUNNING)" /** Offset of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_EN_LSB 0UL /** Size in bits of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_EN_W (1UL) /** Mask for retrieving the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_EN_DT 0x0UL /** Access rights of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_EN_AC "RW" /** Check whether access to the EN field of the STOPTAG register is secured or not. */ #define ATON_STRENG_STOPTAG_EN_S 0 /** Check whether access to the EN field of the STOPTAG register is privileged or not. */ #define ATON_STRENG_STOPTAG_EN_P 0 /** Read the content of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_STOPTAG_EN_LSB, ATON_STRENG_STOPTAG_EN_W) /** Modify the content of the EN field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STOPTAG_EN_LSB, ATON_STRENG_STOPTAG_EN_W, DATA) /** * Get the description of the EN field of STOPTAG register. * * \return the description of the EN field of STOPTAG register */ static inline const int8_t *ATON_STRENG_STOPTAG_EN_GetdDesc(void) { return (const int8_t *)ATON_STRENG_STOPTAG_EN_DESC; } /** * Read the content of the EN field of the STOPTAG register. * * \param[in] reg is the value of the STOPTAG register * * \return the content of the EN field belonging to STOPTAG register */ static inline uint32_t ATON_STRENG_STOPTAG_Get_EN(uint32_t reg) { return ATON_STRENG_STOPTAG_GET_EN(reg); } /** * Write the content of the EN field of the STOPTAG register. * * \param[in] reg is the value of the STOPTAG register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to STOPTAG register */ static inline uint32_t ATON_STRENG_STOPTAG_Set_EN(uint32_t reg, uint32_t data) { return ATON_STRENG_STOPTAG_SET_EN(reg, data); } /* ----------------------------------------------------------- TAG field of the STOPTAG register ------------------------------------------------------------ */ /** Description of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_TAG_DESC "Stop tag (RO when CTRL.RUNNING)" /** Offset of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_TAG_LSB 16UL /** Size in bits of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_TAG_W (16UL) /** Mask for retrieving the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_TAG_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_TAG_DT 0xffd9UL /** Access rights of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_TAG_AC "RW" /** Check whether access to the TAG field of the STOPTAG register is secured or not. */ #define ATON_STRENG_STOPTAG_TAG_S 0 /** Check whether access to the TAG field of the STOPTAG register is privileged or not. */ #define ATON_STRENG_STOPTAG_TAG_P 0 /** Read the content of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_GET_TAG(REG) ATON_GET_FIELD(REG, ATON_STRENG_STOPTAG_TAG_LSB, ATON_STRENG_STOPTAG_TAG_W) /** Modify the content of the TAG field of the STOPTAG register. */ #define ATON_STRENG_STOPTAG_SET_TAG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_STOPTAG_TAG_LSB, ATON_STRENG_STOPTAG_TAG_W, DATA) /** * Get the description of the TAG field of STOPTAG register. * * \return the description of the TAG field of STOPTAG register */ static inline const int8_t *ATON_STRENG_STOPTAG_TAG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_STOPTAG_TAG_DESC; } /** * Read the content of the TAG field of the STOPTAG register. * * \param[in] reg is the value of the STOPTAG register * * \return the content of the TAG field belonging to STOPTAG register */ static inline uint32_t ATON_STRENG_STOPTAG_Get_TAG(uint32_t reg) { return ATON_STRENG_STOPTAG_GET_TAG(reg); } /** * Write the content of the TAG field of the STOPTAG register. * * \param[in] reg is the value of the STOPTAG register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the TAG field belonging to STOPTAG register */ static inline uint32_t ATON_STRENG_STOPTAG_Set_TAG(uint32_t reg, uint32_t data) { return ATON_STRENG_STOPTAG_SET_TAG(reg, data); } /* ****************************************************** LIMITEN register of one of the STRENG Units ******************************************************* */ /** Offset of the LIMITEN register from the base address of the STRENG Unit. */ #define ATON_STRENG_LIMITEN_OFFSET 0x30UL /** Reset value of the LIMITEN register of the STRENG Unit. */ #define ATON_STRENG_LIMITEN_DT \ (ATON_STRENG_LIMITEN_ADDRLIMIT_DT << ATON_STRENG_LIMITEN_ADDRLIMIT_LSB) | \ (ATON_STRENG_LIMITEN_STOPPREFTC_DT << ATON_STRENG_LIMITEN_STOPPREFTC_LSB) | \ (ATON_STRENG_LIMITEN_FRAMELIMIT_DT << ATON_STRENG_LIMITEN_FRAMELIMIT_LSB) | \ (ATON_STRENG_LIMITEN_AUTOCLR_DT << ATON_STRENG_LIMITEN_AUTOCLR_LSB) | \ (ATON_STRENG_LIMITEN_CLRMSGSENT_DT << ATON_STRENG_LIMITEN_CLRMSGSENT_LSB) | \ (ATON_STRENG_LIMITEN_DOFF_MSB_DT << ATON_STRENG_LIMITEN_DOFF_MSB_LSB) /** Description of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DESC "Limiter enables" /** Address of the LIMITEN register of one of the STRENG Units. */ #define ATON_STRENG_LIMITEN_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LIMITEN_OFFSET) /** Get the content of the LIMITEN register of one of the STRENG Units. */ #define ATON_STRENG_LIMITEN_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITEN_ADDR(UNIT))) /** Set the content of the LIMITEN register of one of the STRENG Units. */ #define ATON_STRENG_LIMITEN_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITEN_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of LIMITEN register. * * \return the description of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_GetDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_DESC; } /** * Get the offset of the LIMITEN register. * * \return the offset of LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_GetOffset(void) { return ATON_STRENG_LIMITEN_OFFSET; } /** * Get the address of the LIMITEN register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITEN register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of LIMITEN register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LIMITEN_GetAddr(uint32_t instance) { return ATON_STRENG_LIMITEN_ADDR(instance); } /** * Read the content of the LIMITEN register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITEN register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of LIMITEN register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LIMITEN_Get(uint32_t instance) { return ATON_STRENG_LIMITEN_GET(instance); } /** * Write the content of the LIMITEN register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITEN register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_LIMITEN_Set(uint32_t instance, uint32_t data) { ATON_STRENG_LIMITEN_SET(instance, data); } /* -------------------------------------------------------- ADDRLIMIT field of the LIMITEN register --------------------------------------------------------- */ /** Description of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_DESC "Address limiter enable (RO when CTRL.RUNNING)" /** Offset of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_LSB 0UL /** Size in bits of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_W (1UL) /** Mask for retrieving the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_DT 0x0UL /** Access rights of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_AC "RW" /** Check whether access to the ADDRLIMIT field of the LIMITEN register is secured or not. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_S 0 /** Check whether access to the ADDRLIMIT field of the LIMITEN register is privileged or not. */ #define ATON_STRENG_LIMITEN_ADDRLIMIT_P 0 /** Read the content of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_GET_ADDRLIMIT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_ADDRLIMIT_LSB, ATON_STRENG_LIMITEN_ADDRLIMIT_W) /** Modify the content of the ADDRLIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_SET_ADDRLIMIT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_ADDRLIMIT_LSB, ATON_STRENG_LIMITEN_ADDRLIMIT_W, DATA) /** * Get the description of the ADDRLIMIT field of LIMITEN register. * * \return the description of the ADDRLIMIT field of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_ADDRLIMIT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_ADDRLIMIT_DESC; } /** * Read the content of the ADDRLIMIT field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * * \return the content of the ADDRLIMIT field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Get_ADDRLIMIT(uint32_t reg) { return ATON_STRENG_LIMITEN_GET_ADDRLIMIT(reg); } /** * Write the content of the ADDRLIMIT field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ADDRLIMIT field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Set_ADDRLIMIT(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMITEN_SET_ADDRLIMIT(reg, data); } /* -------------------------------------------------------- STOPPREFTC field of the LIMITEN register -------------------------------------------------------- */ /** Description of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_DESC "Address limiter stop prefetch (instead of error while in bus to stream direction) (RO when CTRL.RUNNING)" /** Offset of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_LSB 1UL /** Size in bits of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_W (1UL) /** Mask for retrieving the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_DT 0x1UL /** Access rights of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_AC "RW" /** Check whether access to the STOPPREFTC field of the LIMITEN register is secured or not. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_S 0 /** Check whether access to the STOPPREFTC field of the LIMITEN register is privileged or not. */ #define ATON_STRENG_LIMITEN_STOPPREFTC_P 0 /** Read the content of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_GET_STOPPREFTC(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_STOPPREFTC_LSB, ATON_STRENG_LIMITEN_STOPPREFTC_W) /** Modify the content of the STOPPREFTC field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_SET_STOPPREFTC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_STOPPREFTC_LSB, ATON_STRENG_LIMITEN_STOPPREFTC_W, DATA) /** * Get the description of the STOPPREFTC field of LIMITEN register. * * \return the description of the STOPPREFTC field of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_STOPPREFTC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_STOPPREFTC_DESC; } /** * Read the content of the STOPPREFTC field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * * \return the content of the STOPPREFTC field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Get_STOPPREFTC(uint32_t reg) { return ATON_STRENG_LIMITEN_GET_STOPPREFTC(reg); } /** * Write the content of the STOPPREFTC field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOPPREFTC field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Set_STOPPREFTC(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMITEN_SET_STOPPREFTC(reg, data); } /* -------------------------------------------------------- FRAMELIMIT field of the LIMITEN register -------------------------------------------------------- */ /** Description of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_DESC "Frame limiter enable (RO when CTRL.RUNNING)" /** Offset of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_LSB 2UL /** Size in bits of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_W (1UL) /** Mask for retrieving the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_DT 0x0UL /** Access rights of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_AC "RW" /** Check whether access to the FRAMELIMIT field of the LIMITEN register is secured or not. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_S 0 /** Check whether access to the FRAMELIMIT field of the LIMITEN register is privileged or not. */ #define ATON_STRENG_LIMITEN_FRAMELIMIT_P 0 /** Read the content of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_GET_FRAMELIMIT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_FRAMELIMIT_LSB, ATON_STRENG_LIMITEN_FRAMELIMIT_W) /** Modify the content of the FRAMELIMIT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_SET_FRAMELIMIT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_FRAMELIMIT_LSB, ATON_STRENG_LIMITEN_FRAMELIMIT_W, DATA) /** * Get the description of the FRAMELIMIT field of LIMITEN register. * * \return the description of the FRAMELIMIT field of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_FRAMELIMIT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_FRAMELIMIT_DESC; } /** * Read the content of the FRAMELIMIT field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * * \return the content of the FRAMELIMIT field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Get_FRAMELIMIT(uint32_t reg) { return ATON_STRENG_LIMITEN_GET_FRAMELIMIT(reg); } /** * Write the content of the FRAMELIMIT field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FRAMELIMIT field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Set_FRAMELIMIT(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMITEN_SET_FRAMELIMIT(reg, data); } /* --------------------------------------------------------- AUTOCLR field of the LIMITEN register ---------------------------------------------------------- */ /** Description of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_AUTOCLR_DESC "If 1, trigger clear if limiter is hit (RO when CTRL.RUNNING)" /** Offset of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_AUTOCLR_LSB 3UL /** Size in bits of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_AUTOCLR_W (1UL) /** Mask for retrieving the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_AUTOCLR_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_AUTOCLR_DT 0x0UL /** Access rights of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_AUTOCLR_AC "RW" /** Check whether access to the AUTOCLR field of the LIMITEN register is secured or not. */ #define ATON_STRENG_LIMITEN_AUTOCLR_S 0 /** Check whether access to the AUTOCLR field of the LIMITEN register is privileged or not. */ #define ATON_STRENG_LIMITEN_AUTOCLR_P 0 /** Read the content of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_GET_AUTOCLR(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_AUTOCLR_LSB, ATON_STRENG_LIMITEN_AUTOCLR_W) /** Modify the content of the AUTOCLR field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_SET_AUTOCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_AUTOCLR_LSB, ATON_STRENG_LIMITEN_AUTOCLR_W, DATA) /** * Get the description of the AUTOCLR field of LIMITEN register. * * \return the description of the AUTOCLR field of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_AUTOCLR_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_AUTOCLR_DESC; } /** * Read the content of the AUTOCLR field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * * \return the content of the AUTOCLR field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Get_AUTOCLR(uint32_t reg) { return ATON_STRENG_LIMITEN_GET_AUTOCLR(reg); } /** * Write the content of the AUTOCLR field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the AUTOCLR field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Set_AUTOCLR(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMITEN_SET_AUTOCLR(reg, data); } /* -------------------------------------------------------- CLRMSGSENT field of the LIMITEN register -------------------------------------------------------- */ /** Description of the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_DESC "Reserved" /** Offset of the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_LSB 8UL /** Size in bits of the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_W (1UL) /** Mask for retrieving the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_MASK ATON_FIELD_MASK(8UL, 1UL) /** Reset value of the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_DT 0x0UL /** Access rights of the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_AC "R" /** Check whether access to the CLRMSGSENT field of the LIMITEN register is secured or not. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_S 0 /** Check whether access to the CLRMSGSENT field of the LIMITEN register is privileged or not. */ #define ATON_STRENG_LIMITEN_CLRMSGSENT_P 0 /** Read the content of the CLRMSGSENT field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_GET_CLRMSGSENT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_CLRMSGSENT_LSB, ATON_STRENG_LIMITEN_CLRMSGSENT_W) /** * Get the description of the CLRMSGSENT field of LIMITEN register. * * \return the description of the CLRMSGSENT field of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_CLRMSGSENT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_CLRMSGSENT_DESC; } /** * Read the content of the CLRMSGSENT field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * * \return the content of the CLRMSGSENT field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Get_CLRMSGSENT(uint32_t reg) { return ATON_STRENG_LIMITEN_GET_CLRMSGSENT(reg); } /* --------------------------------------------------------- DOFF_MSB field of the LIMITEN register --------------------------------------------------------- */ /** Description of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_DESC "MSB depth offset extension (RO when CTRL.RUNNING)" /** Offset of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_LSB 16UL /** Size in bits of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_W (16UL) /** Mask for retrieving the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_DT 0x0UL /** Access rights of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_AC "RW" /** Check whether access to the DOFF_MSB field of the LIMITEN register is secured or not. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_S 0 /** Check whether access to the DOFF_MSB field of the LIMITEN register is privileged or not. */ #define ATON_STRENG_LIMITEN_DOFF_MSB_P 0 /** Read the content of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_GET_DOFF_MSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITEN_DOFF_MSB_LSB, ATON_STRENG_LIMITEN_DOFF_MSB_W) /** Modify the content of the DOFF_MSB field of the LIMITEN register. */ #define ATON_STRENG_LIMITEN_SET_DOFF_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITEN_DOFF_MSB_LSB, ATON_STRENG_LIMITEN_DOFF_MSB_W, DATA) /** * Get the description of the DOFF_MSB field of LIMITEN register. * * \return the description of the DOFF_MSB field of LIMITEN register */ static inline const int8_t *ATON_STRENG_LIMITEN_DOFF_MSB_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITEN_DOFF_MSB_DESC; } /** * Read the content of the DOFF_MSB field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * * \return the content of the DOFF_MSB field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Get_DOFF_MSB(uint32_t reg) { return ATON_STRENG_LIMITEN_GET_DOFF_MSB(reg); } /** * Write the content of the DOFF_MSB field of the LIMITEN register. * * \param[in] reg is the value of the LIMITEN register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the DOFF_MSB field belonging to LIMITEN register */ static inline uint32_t ATON_STRENG_LIMITEN_Set_DOFF_MSB(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMITEN_SET_DOFF_MSB(reg, data); } /* ******************************************************* LIMIT register of one of the STRENG Units ******************************************************** */ /** Offset of the LIMIT register from the base address of the STRENG Unit. */ #define ATON_STRENG_LIMIT_OFFSET 0x34UL /** Reset value of the LIMIT register of the STRENG Unit. */ #define ATON_STRENG_LIMIT_DT \ (ATON_STRENG_LIMIT_CNT_DT << ATON_STRENG_LIMIT_CNT_LSB) /** Description of the LIMIT register. */ #define ATON_STRENG_LIMIT_DESC "Limiter" /** Address of the LIMIT register of one of the STRENG Units. */ #define ATON_STRENG_LIMIT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LIMIT_OFFSET) /** Get the content of the LIMIT register of one of the STRENG Units. */ #define ATON_STRENG_LIMIT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMIT_ADDR(UNIT))) /** Set the content of the LIMIT register of one of the STRENG Units. */ #define ATON_STRENG_LIMIT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMIT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of LIMIT register. * * \return the description of LIMIT register */ static inline const int8_t *ATON_STRENG_LIMIT_GetDesc(void) { return (const int8_t *)ATON_STRENG_LIMIT_DESC; } /** * Get the offset of the LIMIT register. * * \return the offset of LIMIT register */ static inline uint32_t ATON_STRENG_LIMIT_GetOffset(void) { return ATON_STRENG_LIMIT_OFFSET; } /** * Get the address of the LIMIT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMIT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of LIMIT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LIMIT_GetAddr(uint32_t instance) { return ATON_STRENG_LIMIT_ADDR(instance); } /** * Read the content of the LIMIT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMIT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of LIMIT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LIMIT_Get(uint32_t instance) { return ATON_STRENG_LIMIT_GET(instance); } /** * Write the content of the LIMIT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMIT register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_LIMIT_Set(uint32_t instance, uint32_t data) { ATON_STRENG_LIMIT_SET(instance, data); } /* ------------------------------------------------------------ CNT field of the LIMIT register ------------------------------------------------------------- */ /** Description of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_CNT_DESC "Frame limit (RO when CTRL.RUNNING)" /** Offset of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_CNT_LSB 0UL /** Size in bits of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_CNT_W (32UL) /** Mask for retrieving the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_CNT_DT 0x0UL /** Access rights of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_CNT_AC "RW" /** Check whether access to the CNT field of the LIMIT register is secured or not. */ #define ATON_STRENG_LIMIT_CNT_S 0 /** Check whether access to the CNT field of the LIMIT register is privileged or not. */ #define ATON_STRENG_LIMIT_CNT_P 0 /** Read the content of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMIT_CNT_LSB, ATON_STRENG_LIMIT_CNT_W) /** Modify the content of the CNT field of the LIMIT register. */ #define ATON_STRENG_LIMIT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMIT_CNT_LSB, ATON_STRENG_LIMIT_CNT_W, DATA) /** * Get the description of the CNT field of LIMIT register. * * \return the description of the CNT field of LIMIT register */ static inline const int8_t *ATON_STRENG_LIMIT_CNT_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMIT_CNT_DESC; } /** * Read the content of the CNT field of the LIMIT register. * * \param[in] reg is the value of the LIMIT register * * \return the content of the CNT field belonging to LIMIT register */ static inline uint32_t ATON_STRENG_LIMIT_Get_CNT(uint32_t reg) { return ATON_STRENG_LIMIT_GET_CNT(reg); } /** * Write the content of the CNT field of the LIMIT register. * * \param[in] reg is the value of the LIMIT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to LIMIT register */ static inline uint32_t ATON_STRENG_LIMIT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMIT_SET_CNT(reg, data); } /* ***************************************************** LIMITADDR register of one of the STRENG Units ****************************************************** */ /** Offset of the LIMITADDR register from the base address of the STRENG Unit. */ #define ATON_STRENG_LIMITADDR_OFFSET 0x38UL /** Reset value of the LIMITADDR register of the STRENG Unit. */ #define ATON_STRENG_LIMITADDR_DT \ (ATON_STRENG_LIMITADDR_REG_DT << ATON_STRENG_LIMITADDR_REG_LSB) /** Description of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_DESC "Limiter address" /** Address of the LIMITADDR register of one of the STRENG Units. */ #define ATON_STRENG_LIMITADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LIMITADDR_OFFSET) /** Get the content of the LIMITADDR register of one of the STRENG Units. */ #define ATON_STRENG_LIMITADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITADDR_ADDR(UNIT))) /** Set the content of the LIMITADDR register of one of the STRENG Units. */ #define ATON_STRENG_LIMITADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_LIMITADDR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of LIMITADDR register. * * \return the description of LIMITADDR register */ static inline const int8_t *ATON_STRENG_LIMITADDR_GetDesc(void) { return (const int8_t *)ATON_STRENG_LIMITADDR_DESC; } /** * Get the offset of the LIMITADDR register. * * \return the offset of LIMITADDR register */ static inline uint32_t ATON_STRENG_LIMITADDR_GetOffset(void) { return ATON_STRENG_LIMITADDR_OFFSET; } /** * Get the address of the LIMITADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITADDR register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of LIMITADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LIMITADDR_GetAddr(uint32_t instance) { return ATON_STRENG_LIMITADDR_ADDR(instance); } /** * Read the content of the LIMITADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITADDR register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of LIMITADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LIMITADDR_Get(uint32_t instance) { return ATON_STRENG_LIMITADDR_GET(instance); } /** * Write the content of the LIMITADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LIMITADDR register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_LIMITADDR_Set(uint32_t instance, uint32_t data) { ATON_STRENG_LIMITADDR_SET(instance, data); } /* ---------------------------------------------------------- REG field of the LIMITADDR register ----------------------------------------------------------- */ /** Description of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_REG_DESC "Limiter address, bits 2:0 are RO (RO when CTRL.RUNNING)" /** Offset of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_REG_LSB 0UL /** Size in bits of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_REG_W (32UL) /** Mask for retrieving the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_REG_DT 0x0UL /** Access rights of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_REG_AC "RW" /** Check whether access to the REG field of the LIMITADDR register is secured or not. */ #define ATON_STRENG_LIMITADDR_REG_S 0 /** Check whether access to the REG field of the LIMITADDR register is privileged or not. */ #define ATON_STRENG_LIMITADDR_REG_P 0 /** Read the content of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_LIMITADDR_REG_LSB, ATON_STRENG_LIMITADDR_REG_W) /** Modify the content of the REG field of the LIMITADDR register. */ #define ATON_STRENG_LIMITADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_LIMITADDR_REG_LSB, ATON_STRENG_LIMITADDR_REG_W, DATA) /** * Get the description of the REG field of LIMITADDR register. * * \return the description of the REG field of LIMITADDR register */ static inline const int8_t *ATON_STRENG_LIMITADDR_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LIMITADDR_REG_DESC; } /** * Read the content of the REG field of the LIMITADDR register. * * \param[in] reg is the value of the LIMITADDR register * * \return the content of the REG field belonging to LIMITADDR register */ static inline uint32_t ATON_STRENG_LIMITADDR_Get_REG(uint32_t reg) { return ATON_STRENG_LIMITADDR_GET_REG(reg); } /** * Write the content of the REG field of the LIMITADDR register. * * \param[in] reg is the value of the LIMITADDR register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to LIMITADDR register */ static inline uint32_t ATON_STRENG_LIMITADDR_Set_REG(uint32_t reg, uint32_t data) { return ATON_STRENG_LIMITADDR_SET_REG(reg, data); } /* ******************************************************** IRQ register of one of the STRENG Units ********************************************************* */ /** Offset of the IRQ register from the base address of the STRENG Unit. */ #define ATON_STRENG_IRQ_OFFSET 0x3cUL /** Reset value of the IRQ register of the STRENG Unit. */ #define ATON_STRENG_IRQ_DT \ (ATON_STRENG_IRQ_RAW_BUFBL_DT << ATON_STRENG_IRQ_RAW_BUFBL_LSB) | \ (ATON_STRENG_IRQ_RAW_MRK_DT << ATON_STRENG_IRQ_RAW_MRK_LSB) | \ (ATON_STRENG_IRQ_RAW_OFLOW_ADD_DT << ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB) | \ (ATON_STRENG_IRQ_RAW_OFLOW_FRM_DT << ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB) | \ (ATON_STRENG_IRQ_RAW_ILLCFG_DT << ATON_STRENG_IRQ_RAW_ILLCFG_LSB) | \ (ATON_STRENG_IRQ_RAW_FMTMM_DT << ATON_STRENG_IRQ_RAW_FMTMM_LSB) | \ (ATON_STRENG_IRQ_RAW_CLRMSGRCV_DT << ATON_STRENG_IRQ_RAW_CLRMSGRCV_LSB) /** Description of the IRQ register. */ #define ATON_STRENG_IRQ_DESC "Events and interrupt enable" /** Address of the IRQ register of one of the STRENG Units. */ #define ATON_STRENG_IRQ_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_IRQ_OFFSET) /** Get the content of the IRQ register of one of the STRENG Units. */ #define ATON_STRENG_IRQ_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_IRQ_ADDR(UNIT))) /** Set the content of the IRQ register of one of the STRENG Units. */ #define ATON_STRENG_IRQ_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_IRQ_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of IRQ register. * * \return the description of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_GetDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_DESC; } /** * Get the offset of the IRQ register. * * \return the offset of IRQ register */ static inline uint32_t ATON_STRENG_IRQ_GetOffset(void) { return ATON_STRENG_IRQ_OFFSET; } /** * Get the address of the IRQ register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the IRQ register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of IRQ register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_IRQ_GetAddr(uint32_t instance) { return ATON_STRENG_IRQ_ADDR(instance); } /** * Read the content of the IRQ register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the IRQ register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of IRQ register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_IRQ_Get(uint32_t instance) { return ATON_STRENG_IRQ_GET(instance); } /** * Write the content of the IRQ register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the IRQ register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_IRQ_Set(uint32_t instance, uint32_t data) { ATON_STRENG_IRQ_SET(instance, data); } /* ---------------------------------------------------------- RAW_BUFBL field of the IRQ register ----------------------------------------------------------- */ /** Description of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_BUFBL_DESC "Buffer bandwith limit hit (write 1 to clear irq, write 0 has no effects)" /** Offset of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_BUFBL_LSB 0UL /** Size in bits of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_BUFBL_W (1UL) /** Mask for retrieving the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_BUFBL_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_BUFBL_DT 0x0UL /** Access rights of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_BUFBL_AC "RW" /** Check whether access to the RAW_BUFBL field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_BUFBL_S 0 /** Check whether access to the RAW_BUFBL field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_BUFBL_P 0 /** Read the content of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_BUFBL(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_BUFBL_LSB, ATON_STRENG_IRQ_RAW_BUFBL_W) /** Modify the content of the RAW_BUFBL field of the IRQ register. */ #define ATON_STRENG_IRQ_SET_RAW_BUFBL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_BUFBL_LSB, ATON_STRENG_IRQ_RAW_BUFBL_W, DATA) /** * Get the description of the RAW_BUFBL field of IRQ register. * * \return the description of the RAW_BUFBL field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_BUFBL_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_BUFBL_DESC; } /** * Read the content of the RAW_BUFBL field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_BUFBL field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_BUFBL(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_BUFBL(reg); } /** * Write the content of the RAW_BUFBL field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_BUFBL field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Set_RAW_BUFBL(uint32_t reg, uint32_t data) { return ATON_STRENG_IRQ_SET_RAW_BUFBL(reg, data); } /* ----------------------------------------------------------- RAW_MRK field of the IRQ register ------------------------------------------------------------ */ /** Description of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_MRK_DESC "Marker hit (write 1 to clear irq, write 0 has no effects)" /** Offset of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_MRK_LSB 1UL /** Size in bits of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_MRK_W (1UL) /** Mask for retrieving the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_MRK_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_MRK_DT 0x0UL /** Access rights of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_MRK_AC "RW" /** Check whether access to the RAW_MRK field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_MRK_S 0 /** Check whether access to the RAW_MRK field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_MRK_P 0 /** Read the content of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_MRK(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_MRK_LSB, ATON_STRENG_IRQ_RAW_MRK_W) /** Modify the content of the RAW_MRK field of the IRQ register. */ #define ATON_STRENG_IRQ_SET_RAW_MRK(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_MRK_LSB, ATON_STRENG_IRQ_RAW_MRK_W, DATA) /** * Get the description of the RAW_MRK field of IRQ register. * * \return the description of the RAW_MRK field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_MRK_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_MRK_DESC; } /** * Read the content of the RAW_MRK field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_MRK field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_MRK(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_MRK(reg); } /** * Write the content of the RAW_MRK field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_MRK field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Set_RAW_MRK(uint32_t reg, uint32_t data) { return ATON_STRENG_IRQ_SET_RAW_MRK(reg, data); } /* -------------------------------------------------------- RAW_OFLOW_ADD field of the IRQ register --------------------------------------------------------- */ /** Description of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_DESC "Address limiter hit (write 1 to clear irq, write 0 has no effects)" /** Offset of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB 2UL /** Size in bits of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_W (1UL) /** Mask for retrieving the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_DT 0x0UL /** Access rights of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_AC "RW" /** Check whether access to the RAW_OFLOW_ADD field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_S 0 /** Check whether access to the RAW_OFLOW_ADD field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_OFLOW_ADD_P 0 /** Read the content of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_OFLOW_ADD(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB, ATON_STRENG_IRQ_RAW_OFLOW_ADD_W) /** Modify the content of the RAW_OFLOW_ADD field of the IRQ register. */ #define ATON_STRENG_IRQ_SET_RAW_OFLOW_ADD(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_ADD_LSB, ATON_STRENG_IRQ_RAW_OFLOW_ADD_W, DATA) /** * Get the description of the RAW_OFLOW_ADD field of IRQ register. * * \return the description of the RAW_OFLOW_ADD field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_OFLOW_ADD_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_OFLOW_ADD_DESC; } /** * Read the content of the RAW_OFLOW_ADD field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_OFLOW_ADD field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_OFLOW_ADD(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_OFLOW_ADD(reg); } /** * Write the content of the RAW_OFLOW_ADD field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_OFLOW_ADD field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Set_RAW_OFLOW_ADD(uint32_t reg, uint32_t data) { return ATON_STRENG_IRQ_SET_RAW_OFLOW_ADD(reg, data); } /* -------------------------------------------------------- RAW_OFLOW_FRM field of the IRQ register --------------------------------------------------------- */ /** Description of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_DESC "Frame limiter hit (write 1 to clear irq, write 0 has no effects)" /** Offset of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB 3UL /** Size in bits of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_W (1UL) /** Mask for retrieving the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_DT 0x0UL /** Access rights of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_AC "RW" /** Check whether access to the RAW_OFLOW_FRM field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_S 0 /** Check whether access to the RAW_OFLOW_FRM field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_OFLOW_FRM_P 0 /** Read the content of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_OFLOW_FRM(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB, ATON_STRENG_IRQ_RAW_OFLOW_FRM_W) /** Modify the content of the RAW_OFLOW_FRM field of the IRQ register. */ #define ATON_STRENG_IRQ_SET_RAW_OFLOW_FRM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_OFLOW_FRM_LSB, ATON_STRENG_IRQ_RAW_OFLOW_FRM_W, DATA) /** * Get the description of the RAW_OFLOW_FRM field of IRQ register. * * \return the description of the RAW_OFLOW_FRM field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_OFLOW_FRM_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_OFLOW_FRM_DESC; } /** * Read the content of the RAW_OFLOW_FRM field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_OFLOW_FRM field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_OFLOW_FRM(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_OFLOW_FRM(reg); } /** * Write the content of the RAW_OFLOW_FRM field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_OFLOW_FRM field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Set_RAW_OFLOW_FRM(uint32_t reg, uint32_t data) { return ATON_STRENG_IRQ_SET_RAW_OFLOW_FRM(reg, data); } /* ---------------------------------------------------------- RAW_ILLCFG field of the IRQ register ---------------------------------------------------------- */ /** Description of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_DESC "Illegal configuration (write 1 to clear irq, write 0 has no effects)" /** Offset of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_LSB 4UL /** Size in bits of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_W (1UL) /** Mask for retrieving the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_DT 0x0UL /** Access rights of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_AC "RW" /** Check whether access to the RAW_ILLCFG field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_S 0 /** Check whether access to the RAW_ILLCFG field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_ILLCFG_P 0 /** Read the content of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_ILLCFG(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_ILLCFG_LSB, ATON_STRENG_IRQ_RAW_ILLCFG_W) /** Modify the content of the RAW_ILLCFG field of the IRQ register. */ #define ATON_STRENG_IRQ_SET_RAW_ILLCFG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_ILLCFG_LSB, ATON_STRENG_IRQ_RAW_ILLCFG_W, DATA) /** * Get the description of the RAW_ILLCFG field of IRQ register. * * \return the description of the RAW_ILLCFG field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_ILLCFG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_ILLCFG_DESC; } /** * Read the content of the RAW_ILLCFG field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_ILLCFG field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_ILLCFG(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_ILLCFG(reg); } /** * Write the content of the RAW_ILLCFG field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_ILLCFG field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Set_RAW_ILLCFG(uint32_t reg, uint32_t data) { return ATON_STRENG_IRQ_SET_RAW_ILLCFG(reg, data); } /* ---------------------------------------------------------- RAW_FMTMM field of the IRQ register ----------------------------------------------------------- */ /** Description of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_FMTMM_DESC "Format mismatch (write 1 to clear irq, write 0 has no effects)" /** Offset of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_FMTMM_LSB 5UL /** Size in bits of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_FMTMM_W (1UL) /** Mask for retrieving the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_FMTMM_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_FMTMM_DT 0x0UL /** Access rights of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_FMTMM_AC "RW" /** Check whether access to the RAW_FMTMM field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_FMTMM_S 0 /** Check whether access to the RAW_FMTMM field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_FMTMM_P 0 /** Read the content of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_FMTMM(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_FMTMM_LSB, ATON_STRENG_IRQ_RAW_FMTMM_W) /** Modify the content of the RAW_FMTMM field of the IRQ register. */ #define ATON_STRENG_IRQ_SET_RAW_FMTMM(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_IRQ_RAW_FMTMM_LSB, ATON_STRENG_IRQ_RAW_FMTMM_W, DATA) /** * Get the description of the RAW_FMTMM field of IRQ register. * * \return the description of the RAW_FMTMM field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_FMTMM_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_FMTMM_DESC; } /** * Read the content of the RAW_FMTMM field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_FMTMM field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_FMTMM(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_FMTMM(reg); } /** * Write the content of the RAW_FMTMM field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW_FMTMM field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Set_RAW_FMTMM(uint32_t reg, uint32_t data) { return ATON_STRENG_IRQ_SET_RAW_FMTMM(reg, data); } /* -------------------------------------------------------- RAW_CLRMSGRCV field of the IRQ register --------------------------------------------------------- */ /** Description of the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_DESC "Reserved" /** Offset of the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_LSB 6UL /** Size in bits of the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_W (1UL) /** Mask for retrieving the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_MASK ATON_FIELD_MASK(6UL, 1UL) /** Reset value of the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_DT 0x0UL /** Access rights of the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_AC "R" /** Check whether access to the RAW_CLRMSGRCV field of the IRQ register is secured or not. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_S 0 /** Check whether access to the RAW_CLRMSGRCV field of the IRQ register is privileged or not. */ #define ATON_STRENG_IRQ_RAW_CLRMSGRCV_P 0 /** Read the content of the RAW_CLRMSGRCV field of the IRQ register. */ #define ATON_STRENG_IRQ_GET_RAW_CLRMSGRCV(REG) ATON_GET_FIELD(REG, ATON_STRENG_IRQ_RAW_CLRMSGRCV_LSB, ATON_STRENG_IRQ_RAW_CLRMSGRCV_W) /** * Get the description of the RAW_CLRMSGRCV field of IRQ register. * * \return the description of the RAW_CLRMSGRCV field of IRQ register */ static inline const int8_t *ATON_STRENG_IRQ_RAW_CLRMSGRCV_GetdDesc(void) { return (const int8_t *)ATON_STRENG_IRQ_RAW_CLRMSGRCV_DESC; } /** * Read the content of the RAW_CLRMSGRCV field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the RAW_CLRMSGRCV field belonging to IRQ register */ static inline uint32_t ATON_STRENG_IRQ_Get_RAW_CLRMSGRCV(uint32_t reg) { return ATON_STRENG_IRQ_GET_RAW_CLRMSGRCV(reg); } /* ****************************************************** ENCR_LSB register of one of the STRENG Units ****************************************************** */ /** Offset of the ENCR_LSB register from the base address of the STRENG Unit. */ #define ATON_STRENG_ENCR_LSB_OFFSET 0x40UL /** Reset value of the ENCR_LSB register of the STRENG Unit. */ #define ATON_STRENG_ENCR_LSB_DT \ (ATON_STRENG_ENCR_LSB_ID_LSB_DT << ATON_STRENG_ENCR_LSB_ID_LSB_LSB) /** Description of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" /** Address of the ENCR_LSB register of one of the STRENG Units. */ #define ATON_STRENG_ENCR_LSB_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_ENCR_LSB_OFFSET) /** Get the content of the ENCR_LSB register of one of the STRENG Units. */ #define ATON_STRENG_ENCR_LSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_LSB_ADDR(UNIT))) /** Set the content of the ENCR_LSB register of one of the STRENG Units. */ #define ATON_STRENG_ENCR_LSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_LSB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ENCR_LSB register. * * \return the description of ENCR_LSB register */ static inline const int8_t *ATON_STRENG_ENCR_LSB_GetDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_LSB_DESC; } /** * Get the offset of the ENCR_LSB register. * * \return the offset of ENCR_LSB register */ static inline uint32_t ATON_STRENG_ENCR_LSB_GetOffset(void) { return ATON_STRENG_ENCR_LSB_OFFSET; } /** * Get the address of the ENCR_LSB register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_LSB register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of ENCR_LSB register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_ENCR_LSB_GetAddr(uint32_t instance) { return ATON_STRENG_ENCR_LSB_ADDR(instance); } /** * Read the content of the ENCR_LSB register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_LSB register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of ENCR_LSB register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_ENCR_LSB_Get(uint32_t instance) { return ATON_STRENG_ENCR_LSB_GET(instance); } /** * Write the content of the ENCR_LSB register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_LSB register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_ENCR_LSB_Set(uint32_t instance, uint32_t data) { ATON_STRENG_ENCR_LSB_SET(instance, data); } /* --------------------------------------------------------- ID_LSB field of the ENCR_LSB register ---------------------------------------------------------- */ /** Description of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" /** Offset of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_LSB 0UL /** Size in bits of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_W (32UL) /** Mask for retrieving the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_DT 0x0UL /** Access rights of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_AC "RW" /** Check whether access to the ID_LSB field of the ENCR_LSB register is secured or not. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_S 0 /** Check whether access to the ID_LSB field of the ENCR_LSB register is privileged or not. */ #define ATON_STRENG_ENCR_LSB_ID_LSB_P 0 /** Read the content of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_GET_ID_LSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_LSB_ID_LSB_LSB, ATON_STRENG_ENCR_LSB_ID_LSB_W) /** Modify the content of the ID_LSB field of the ENCR_LSB register. */ #define ATON_STRENG_ENCR_LSB_SET_ID_LSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_LSB_ID_LSB_LSB, ATON_STRENG_ENCR_LSB_ID_LSB_W, DATA) /** * Get the description of the ID_LSB field of ENCR_LSB register. * * \return the description of the ID_LSB field of ENCR_LSB register */ static inline const int8_t *ATON_STRENG_ENCR_LSB_ID_LSB_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_LSB_ID_LSB_DESC; } /** * Read the content of the ID_LSB field of the ENCR_LSB register. * * \param[in] reg is the value of the ENCR_LSB register * * \return the content of the ID_LSB field belonging to ENCR_LSB register */ static inline uint32_t ATON_STRENG_ENCR_LSB_Get_ID_LSB(uint32_t reg) { return ATON_STRENG_ENCR_LSB_GET_ID_LSB(reg); } /** * Write the content of the ID_LSB field of the ENCR_LSB register. * * \param[in] reg is the value of the ENCR_LSB register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the ID_LSB field belonging to ENCR_LSB register */ static inline uint32_t ATON_STRENG_ENCR_LSB_Set_ID_LSB(uint32_t reg, uint32_t data) { return ATON_STRENG_ENCR_LSB_SET_ID_LSB(reg, data); } /* ****************************************************** ENCR_MSB register of one of the STRENG Units ****************************************************** */ /** Offset of the ENCR_MSB register from the base address of the STRENG Unit. */ #define ATON_STRENG_ENCR_MSB_OFFSET 0x44UL /** Reset value of the ENCR_MSB register of the STRENG Unit. */ #define ATON_STRENG_ENCR_MSB_DT \ (ATON_STRENG_ENCR_MSB_ID_MSB_DT << ATON_STRENG_ENCR_MSB_ID_MSB_LSB) | \ (ATON_STRENG_ENCR_MSB_EN_DT << ATON_STRENG_ENCR_MSB_EN_LSB) | \ (ATON_STRENG_ENCR_MSB_ROUNDS_DT << ATON_STRENG_ENCR_MSB_ROUNDS_LSB) | \ (ATON_STRENG_ENCR_MSB_KEY_SEL_DT << ATON_STRENG_ENCR_MSB_KEY_SEL_LSB) | \ (ATON_STRENG_ENCR_MSB_INC_DT << ATON_STRENG_ENCR_MSB_INC_LSB) /** Description of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" /** Address of the ENCR_MSB register of one of the STRENG Units. */ #define ATON_STRENG_ENCR_MSB_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_ENCR_MSB_OFFSET) /** Get the content of the ENCR_MSB register of one of the STRENG Units. */ #define ATON_STRENG_ENCR_MSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_MSB_ADDR(UNIT))) /** Set the content of the ENCR_MSB register of one of the STRENG Units. */ #define ATON_STRENG_ENCR_MSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_ENCR_MSB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ENCR_MSB register. * * \return the description of ENCR_MSB register */ static inline const int8_t *ATON_STRENG_ENCR_MSB_GetDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_MSB_DESC; } /** * Get the offset of the ENCR_MSB register. * * \return the offset of ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_GetOffset(void) { return ATON_STRENG_ENCR_MSB_OFFSET; } /** * Get the address of the ENCR_MSB register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_MSB register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of ENCR_MSB register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_ENCR_MSB_GetAddr(uint32_t instance) { return ATON_STRENG_ENCR_MSB_ADDR(instance); } /** * Read the content of the ENCR_MSB register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_MSB register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of ENCR_MSB register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_ENCR_MSB_Get(uint32_t instance) { return ATON_STRENG_ENCR_MSB_GET(instance); } /** * Write the content of the ENCR_MSB register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the ENCR_MSB register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_ENCR_MSB_Set(uint32_t instance, uint32_t data) { ATON_STRENG_ENCR_MSB_SET(instance, data); } /* --------------------------------------------------------- ID_MSB field of the ENCR_MSB register ---------------------------------------------------------- */ /** Description of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" /** Offset of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_LSB 0UL /** Size in bits of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_W (11UL) /** Mask for retrieving the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_MASK ATON_FIELD_MASK(0UL, 11UL) /** Reset value of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_DT 0x0UL /** Access rights of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_AC "RW" /** Check whether access to the ID_MSB field of the ENCR_MSB register is secured or not. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_S 0 /** Check whether access to the ID_MSB field of the ENCR_MSB register is privileged or not. */ #define ATON_STRENG_ENCR_MSB_ID_MSB_P 0 /** Read the content of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_GET_ID_MSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_ID_MSB_LSB, ATON_STRENG_ENCR_MSB_ID_MSB_W) /** Modify the content of the ID_MSB field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_SET_ID_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ID_MSB_LSB, ATON_STRENG_ENCR_MSB_ID_MSB_W, DATA) /** * Get the description of the ID_MSB field of ENCR_MSB register. * * \return the description of the ID_MSB field of ENCR_MSB register */ static inline const int8_t *ATON_STRENG_ENCR_MSB_ID_MSB_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_MSB_ID_MSB_DESC; } /** * Read the content of the ID_MSB field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the ID_MSB field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Get_ID_MSB(uint32_t reg) { return ATON_STRENG_ENCR_MSB_GET_ID_MSB(reg); } /** * Write the content of the ID_MSB field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 11-bit value that must be written to the field * * \return the new content of the ID_MSB field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Set_ID_MSB(uint32_t reg, uint32_t data) { return ATON_STRENG_ENCR_MSB_SET_ID_MSB(reg, data); } /* ----------------------------------------------------------- EN field of the ENCR_MSB register ------------------------------------------------------------ */ /** Description of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_EN_DESC "Encryption enable (RO when CTRL.RUNNING)" /** Offset of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_EN_LSB 12UL /** Size in bits of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_EN_W (1UL) /** Mask for retrieving the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_EN_MASK ATON_FIELD_MASK(12UL, 1UL) /** Reset value of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_EN_DT 0x0UL /** Access rights of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_EN_AC "RW" /** Check whether access to the EN field of the ENCR_MSB register is secured or not. */ #define ATON_STRENG_ENCR_MSB_EN_S 0 /** Check whether access to the EN field of the ENCR_MSB register is privileged or not. */ #define ATON_STRENG_ENCR_MSB_EN_P 0 /** Read the content of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_EN_LSB, ATON_STRENG_ENCR_MSB_EN_W) /** Modify the content of the EN field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_EN_LSB, ATON_STRENG_ENCR_MSB_EN_W, DATA) /** * Get the description of the EN field of ENCR_MSB register. * * \return the description of the EN field of ENCR_MSB register */ static inline const int8_t *ATON_STRENG_ENCR_MSB_EN_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_MSB_EN_DESC; } /** * Read the content of the EN field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the EN field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Get_EN(uint32_t reg) { return ATON_STRENG_ENCR_MSB_GET_EN(reg); } /** * Write the content of the EN field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Set_EN(uint32_t reg, uint32_t data) { return ATON_STRENG_ENCR_MSB_SET_EN(reg, data); } /* --------------------------------------------------------- ROUNDS field of the ENCR_MSB register ---------------------------------------------------------- */ /** Description of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_DESC "Encryption number of rounds: 0->12, 1->9 (RO when CTRL.RUNNING)" /** Offset of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_LSB 13UL /** Size in bits of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_W (1UL) /** Mask for retrieving the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_MASK ATON_FIELD_MASK(13UL, 1UL) /** Reset value of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_DT 0x0UL /** Access rights of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_AC "RW" /** Check whether access to the ROUNDS field of the ENCR_MSB register is secured or not. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_S 0 /** Check whether access to the ROUNDS field of the ENCR_MSB register is privileged or not. */ #define ATON_STRENG_ENCR_MSB_ROUNDS_P 0 /** Read the content of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_GET_ROUNDS(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_ROUNDS_LSB, ATON_STRENG_ENCR_MSB_ROUNDS_W) /** Modify the content of the ROUNDS field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_SET_ROUNDS(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ROUNDS_LSB, ATON_STRENG_ENCR_MSB_ROUNDS_W, DATA) /** * Get the description of the ROUNDS field of ENCR_MSB register. * * \return the description of the ROUNDS field of ENCR_MSB register */ static inline const int8_t *ATON_STRENG_ENCR_MSB_ROUNDS_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_MSB_ROUNDS_DESC; } /** * Read the content of the ROUNDS field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the ROUNDS field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Get_ROUNDS(uint32_t reg) { return ATON_STRENG_ENCR_MSB_GET_ROUNDS(reg); } /** * Write the content of the ROUNDS field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUNDS field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Set_ROUNDS(uint32_t reg, uint32_t data) { return ATON_STRENG_ENCR_MSB_SET_ROUNDS(reg, data); } /* --------------------------------------------------------- KEY_SEL field of the ENCR_MSB register --------------------------------------------------------- */ /** Description of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_DESC "Encryption key selection (RO when CTRL.RUNNING)" /** Offset of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_LSB 14UL /** Size in bits of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_W (2UL) /** Mask for retrieving the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_DT 0x0UL /** Access rights of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_AC "RW" /** Check whether access to the KEY_SEL field of the ENCR_MSB register is secured or not. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_S 0 /** Check whether access to the KEY_SEL field of the ENCR_MSB register is privileged or not. */ #define ATON_STRENG_ENCR_MSB_KEY_SEL_P 0 /** Read the content of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_GET_KEY_SEL(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_KEY_SEL_LSB, ATON_STRENG_ENCR_MSB_KEY_SEL_W) /** Modify the content of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_SET_KEY_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_KEY_SEL_LSB, ATON_STRENG_ENCR_MSB_KEY_SEL_W, DATA) /** * Get the description of the KEY_SEL field of ENCR_MSB register. * * \return the description of the KEY_SEL field of ENCR_MSB register */ static inline const int8_t *ATON_STRENG_ENCR_MSB_KEY_SEL_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_MSB_KEY_SEL_DESC; } /** * Read the content of the KEY_SEL field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the KEY_SEL field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Get_KEY_SEL(uint32_t reg) { return ATON_STRENG_ENCR_MSB_GET_KEY_SEL(reg); } /** * Write the content of the KEY_SEL field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the KEY_SEL field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Set_KEY_SEL(uint32_t reg, uint32_t data) { return ATON_STRENG_ENCR_MSB_SET_KEY_SEL(reg, data); } /* ----------------------------------------------------------- INC field of the ENCR_MSB register ----------------------------------------------------------- */ /** Description of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_INC_DESC "Encryption ID increment rate: 0 -> no increment, -> +1 every n frames (RO when CTRL.RUNNING)" /** Offset of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_INC_LSB 16UL /** Size in bits of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_INC_W (16UL) /** Mask for retrieving the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_INC_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_INC_DT 0x0UL /** Access rights of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_INC_AC "RW" /** Check whether access to the INC field of the ENCR_MSB register is secured or not. */ #define ATON_STRENG_ENCR_MSB_INC_S 0 /** Check whether access to the INC field of the ENCR_MSB register is privileged or not. */ #define ATON_STRENG_ENCR_MSB_INC_P 0 /** Read the content of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_GET_INC(REG) ATON_GET_FIELD(REG, ATON_STRENG_ENCR_MSB_INC_LSB, ATON_STRENG_ENCR_MSB_INC_W) /** Modify the content of the INC field of the ENCR_MSB register. */ #define ATON_STRENG_ENCR_MSB_SET_INC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_INC_LSB, ATON_STRENG_ENCR_MSB_INC_W, DATA) /** * Get the description of the INC field of ENCR_MSB register. * * \return the description of the INC field of ENCR_MSB register */ static inline const int8_t *ATON_STRENG_ENCR_MSB_INC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_ENCR_MSB_INC_DESC; } /** * Read the content of the INC field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the INC field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Get_INC(uint32_t reg) { return ATON_STRENG_ENCR_MSB_GET_INC(reg); } /** * Write the content of the INC field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the INC field belonging to ENCR_MSB register */ static inline uint32_t ATON_STRENG_ENCR_MSB_Set_INC(uint32_t reg, uint32_t data) { return ATON_STRENG_ENCR_MSB_SET_INC(reg, data); } /* ***************************************************** CID_CACHE register of one of the STRENG Units ****************************************************** */ /** Offset of the CID_CACHE register from the base address of the STRENG Unit. */ #define ATON_STRENG_CID_CACHE_OFFSET 0x48UL /** Reset value of the CID_CACHE register of the STRENG Unit. */ #define ATON_STRENG_CID_CACHE_DT \ (ATON_STRENG_CID_CACHE_CID_DT << ATON_STRENG_CID_CACHE_CID_LSB) | \ (ATON_STRENG_CID_CACHE_CACHEABLE_DT << ATON_STRENG_CID_CACHE_CACHEABLE_LSB) | \ (ATON_STRENG_CID_CACHE_ALLOC_DT << ATON_STRENG_CID_CACHE_ALLOC_LSB) | \ (ATON_STRENG_CID_CACHE_PFETCH_DT << ATON_STRENG_CID_CACHE_PFETCH_LSB) | \ (ATON_STRENG_CID_CACHE_LINESIZE_DT << ATON_STRENG_CID_CACHE_LINESIZE_LSB) | \ (ATON_STRENG_CID_CACHE_LOFF_MSB_DT << ATON_STRENG_CID_CACHE_LOFF_MSB_LSB) /** Description of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_DESC "Compartment ID / Cache register (RO when CTRL.RUNNING)" /** Address of the CID_CACHE register of one of the STRENG Units. */ #define ATON_STRENG_CID_CACHE_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_CID_CACHE_OFFSET) /** Get the content of the CID_CACHE register of one of the STRENG Units. */ #define ATON_STRENG_CID_CACHE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_CID_CACHE_ADDR(UNIT))) /** Set the content of the CID_CACHE register of one of the STRENG Units. */ #define ATON_STRENG_CID_CACHE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_CID_CACHE_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CID_CACHE register. * * \return the description of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_GetDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_DESC; } /** * Get the offset of the CID_CACHE register. * * \return the offset of CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_GetOffset(void) { return ATON_STRENG_CID_CACHE_OFFSET; } /** * Get the address of the CID_CACHE register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CID_CACHE register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of CID_CACHE register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_CID_CACHE_GetAddr(uint32_t instance) { return ATON_STRENG_CID_CACHE_ADDR(instance); } /** * Read the content of the CID_CACHE register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CID_CACHE register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of CID_CACHE register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_CID_CACHE_Get(uint32_t instance) { return ATON_STRENG_CID_CACHE_GET(instance); } /** * Write the content of the CID_CACHE register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the CID_CACHE register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_CID_CACHE_Set(uint32_t instance, uint32_t data) { ATON_STRENG_CID_CACHE_SET(instance, data); } /* ---------------------------------------------------------- CID field of the CID_CACHE register ----------------------------------------------------------- */ /** Description of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CID_DESC "Compartment ID (RO when CTRL.RUNNING)" /** Offset of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CID_LSB 0UL /** Size in bits of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CID_W (3UL) /** Mask for retrieving the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CID_MASK ATON_FIELD_MASK(0UL, 3UL) /** Reset value of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CID_DT 0x0UL /** Access rights of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CID_AC "RW" /** Check whether access to the CID field of the CID_CACHE register is secured or not. */ #define ATON_STRENG_CID_CACHE_CID_S 0 /** Check whether access to the CID field of the CID_CACHE register is privileged or not. */ #define ATON_STRENG_CID_CACHE_CID_P 0 /** Read the content of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_GET_CID(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_CID_LSB, ATON_STRENG_CID_CACHE_CID_W) /** Modify the content of the CID field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_SET_CID(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_CID_LSB, ATON_STRENG_CID_CACHE_CID_W, DATA) /** * Get the description of the CID field of CID_CACHE register. * * \return the description of the CID field of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_CID_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_CID_DESC; } /** * Read the content of the CID field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the CID field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Get_CID(uint32_t reg) { return ATON_STRENG_CID_CACHE_GET_CID(reg); } /** * Write the content of the CID field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the CID field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Set_CID(uint32_t reg, uint32_t data) { return ATON_STRENG_CID_CACHE_SET_CID(reg, data); } /* ------------------------------------------------------- CACHEABLE field of the CID_CACHE register -------------------------------------------------------- */ /** Description of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_DESC "Cacheable (RO when CTRL.RUNNING)" /** Offset of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_LSB 3UL /** Size in bits of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_W (1UL) /** Mask for retrieving the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_DT 0x0UL /** Access rights of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_AC "RW" /** Check whether access to the CACHEABLE field of the CID_CACHE register is secured or not. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_S 0 /** Check whether access to the CACHEABLE field of the CID_CACHE register is privileged or not. */ #define ATON_STRENG_CID_CACHE_CACHEABLE_P 0 /** Read the content of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_GET_CACHEABLE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_CACHEABLE_LSB, ATON_STRENG_CID_CACHE_CACHEABLE_W) /** Modify the content of the CACHEABLE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_SET_CACHEABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_CACHEABLE_LSB, ATON_STRENG_CID_CACHE_CACHEABLE_W, DATA) /** * Get the description of the CACHEABLE field of CID_CACHE register. * * \return the description of the CACHEABLE field of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_CACHEABLE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_CACHEABLE_DESC; } /** * Read the content of the CACHEABLE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the CACHEABLE field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Get_CACHEABLE(uint32_t reg) { return ATON_STRENG_CID_CACHE_GET_CACHEABLE(reg); } /** * Write the content of the CACHEABLE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CACHEABLE field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Set_CACHEABLE(uint32_t reg, uint32_t data) { return ATON_STRENG_CID_CACHE_SET_CACHEABLE(reg, data); } /* --------------------------------------------------------- ALLOC field of the CID_CACHE register ---------------------------------------------------------- */ /** Description of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_ALLOC_DESC "Allocate (RO when CTRL.RUNNING)" /** Offset of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_ALLOC_LSB 4UL /** Size in bits of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_ALLOC_W (1UL) /** Mask for retrieving the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_ALLOC_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_ALLOC_DT 0x0UL /** Access rights of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_ALLOC_AC "RW" /** Check whether access to the ALLOC field of the CID_CACHE register is secured or not. */ #define ATON_STRENG_CID_CACHE_ALLOC_S 0 /** Check whether access to the ALLOC field of the CID_CACHE register is privileged or not. */ #define ATON_STRENG_CID_CACHE_ALLOC_P 0 /** Read the content of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_GET_ALLOC(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_ALLOC_LSB, ATON_STRENG_CID_CACHE_ALLOC_W) /** Modify the content of the ALLOC field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_SET_ALLOC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_ALLOC_LSB, ATON_STRENG_CID_CACHE_ALLOC_W, DATA) /** * Get the description of the ALLOC field of CID_CACHE register. * * \return the description of the ALLOC field of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_ALLOC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_ALLOC_DESC; } /** * Read the content of the ALLOC field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the ALLOC field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Get_ALLOC(uint32_t reg) { return ATON_STRENG_CID_CACHE_GET_ALLOC(reg); } /** * Write the content of the ALLOC field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ALLOC field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Set_ALLOC(uint32_t reg, uint32_t data) { return ATON_STRENG_CID_CACHE_SET_ALLOC(reg, data); } /* --------------------------------------------------------- PFETCH field of the CID_CACHE register --------------------------------------------------------- */ /** Description of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_PFETCH_DESC "Prefetch (RO when CTRL.RUNNING)" /** Offset of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_PFETCH_LSB 5UL /** Size in bits of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_PFETCH_W (1UL) /** Mask for retrieving the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_PFETCH_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_PFETCH_DT 0x0UL /** Access rights of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_PFETCH_AC "RW" /** Check whether access to the PFETCH field of the CID_CACHE register is secured or not. */ #define ATON_STRENG_CID_CACHE_PFETCH_S 0 /** Check whether access to the PFETCH field of the CID_CACHE register is privileged or not. */ #define ATON_STRENG_CID_CACHE_PFETCH_P 0 /** Read the content of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_GET_PFETCH(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_PFETCH_LSB, ATON_STRENG_CID_CACHE_PFETCH_W) /** Modify the content of the PFETCH field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_SET_PFETCH(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_PFETCH_LSB, ATON_STRENG_CID_CACHE_PFETCH_W, DATA) /** * Get the description of the PFETCH field of CID_CACHE register. * * \return the description of the PFETCH field of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_PFETCH_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_PFETCH_DESC; } /** * Read the content of the PFETCH field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the PFETCH field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Get_PFETCH(uint32_t reg) { return ATON_STRENG_CID_CACHE_GET_PFETCH(reg); } /** * Write the content of the PFETCH field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the PFETCH field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Set_PFETCH(uint32_t reg, uint32_t data) { return ATON_STRENG_CID_CACHE_SET_PFETCH(reg, data); } /* -------------------------------------------------------- LINESIZE field of the CID_CACHE register -------------------------------------------------------- */ /** Description of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LINESIZE_DESC "Line size: 0 -> 64B, 1 -> 128B, 2 -> 256B, 3 -> 512B (RO when CTRL.RUNNING)" /** Offset of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LINESIZE_LSB 6UL /** Size in bits of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LINESIZE_W (2UL) /** Mask for retrieving the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LINESIZE_MASK ATON_FIELD_MASK(6UL, 2UL) /** Reset value of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LINESIZE_DT 0x0UL /** Access rights of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LINESIZE_AC "RW" /** Check whether access to the LINESIZE field of the CID_CACHE register is secured or not. */ #define ATON_STRENG_CID_CACHE_LINESIZE_S 0 /** Check whether access to the LINESIZE field of the CID_CACHE register is privileged or not. */ #define ATON_STRENG_CID_CACHE_LINESIZE_P 0 /** Read the content of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_GET_LINESIZE(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_LINESIZE_LSB, ATON_STRENG_CID_CACHE_LINESIZE_W) /** Modify the content of the LINESIZE field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_SET_LINESIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_LINESIZE_LSB, ATON_STRENG_CID_CACHE_LINESIZE_W, DATA) /** * Get the description of the LINESIZE field of CID_CACHE register. * * \return the description of the LINESIZE field of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_LINESIZE_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_LINESIZE_DESC; } /** * Read the content of the LINESIZE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the LINESIZE field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Get_LINESIZE(uint32_t reg) { return ATON_STRENG_CID_CACHE_GET_LINESIZE(reg); } /** * Write the content of the LINESIZE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the LINESIZE field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Set_LINESIZE(uint32_t reg, uint32_t data) { return ATON_STRENG_CID_CACHE_SET_LINESIZE(reg, data); } /* -------------------------------------------------------- LOFF_MSB field of the CID_CACHE register -------------------------------------------------------- */ /** Description of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_DESC "MSB line offset extension (RO when CTRL.RUNNING)" /** Offset of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_LSB 16UL /** Size in bits of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_W (16UL) /** Mask for retrieving the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_DT 0x0UL /** Access rights of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_AC "RW" /** Check whether access to the LOFF_MSB field of the CID_CACHE register is secured or not. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_S 0 /** Check whether access to the LOFF_MSB field of the CID_CACHE register is privileged or not. */ #define ATON_STRENG_CID_CACHE_LOFF_MSB_P 0 /** Read the content of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_GET_LOFF_MSB(REG) ATON_GET_FIELD(REG, ATON_STRENG_CID_CACHE_LOFF_MSB_LSB, ATON_STRENG_CID_CACHE_LOFF_MSB_W) /** Modify the content of the LOFF_MSB field of the CID_CACHE register. */ #define ATON_STRENG_CID_CACHE_SET_LOFF_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_CID_CACHE_LOFF_MSB_LSB, ATON_STRENG_CID_CACHE_LOFF_MSB_W, DATA) /** * Get the description of the LOFF_MSB field of CID_CACHE register. * * \return the description of the LOFF_MSB field of CID_CACHE register */ static inline const int8_t *ATON_STRENG_CID_CACHE_LOFF_MSB_GetdDesc(void) { return (const int8_t *)ATON_STRENG_CID_CACHE_LOFF_MSB_DESC; } /** * Read the content of the LOFF_MSB field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the LOFF_MSB field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Get_LOFF_MSB(uint32_t reg) { return ATON_STRENG_CID_CACHE_GET_LOFF_MSB(reg); } /** * Write the content of the LOFF_MSB field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the LOFF_MSB field belonging to CID_CACHE register */ static inline uint32_t ATON_STRENG_CID_CACHE_Set_LOFF_MSB(uint32_t reg, uint32_t data) { return ATON_STRENG_CID_CACHE_SET_LOFF_MSB(reg, data); } /* ****************************************************** EXTSYNC register of one of the STRENG Units ******************************************************* */ /** Offset of the EXTSYNC register from the base address of the STRENG Unit. */ #define ATON_STRENG_EXTSYNC_OFFSET 0x4cUL /** Reset value of the EXTSYNC register of the STRENG Unit. */ #define ATON_STRENG_EXTSYNC_DT \ (ATON_STRENG_EXTSYNC_EN_DT << ATON_STRENG_EXTSYNC_EN_LSB) | \ (ATON_STRENG_EXTSYNC_SRC_DT << ATON_STRENG_EXTSYNC_SRC_LSB) | \ (ATON_STRENG_EXTSYNC_LINES_DT << ATON_STRENG_EXTSYNC_LINES_LSB) /** Description of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_DESC "External triggers 1st control register (RO when CTRL.RUNNING)" /** Address of the EXTSYNC register of one of the STRENG Units. */ #define ATON_STRENG_EXTSYNC_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_EXTSYNC_OFFSET) /** Get the content of the EXTSYNC register of one of the STRENG Units. */ #define ATON_STRENG_EXTSYNC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC_ADDR(UNIT))) /** Set the content of the EXTSYNC register of one of the STRENG Units. */ #define ATON_STRENG_EXTSYNC_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EXTSYNC register. * * \return the description of EXTSYNC register */ static inline const int8_t *ATON_STRENG_EXTSYNC_GetDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC_DESC; } /** * Get the offset of the EXTSYNC register. * * \return the offset of EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_GetOffset(void) { return ATON_STRENG_EXTSYNC_OFFSET; } /** * Get the address of the EXTSYNC register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of EXTSYNC register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_EXTSYNC_GetAddr(uint32_t instance) { return ATON_STRENG_EXTSYNC_ADDR(instance); } /** * Read the content of the EXTSYNC register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of EXTSYNC register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_EXTSYNC_Get(uint32_t instance) { return ATON_STRENG_EXTSYNC_GET(instance); } /** * Write the content of the EXTSYNC register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_EXTSYNC_Set(uint32_t instance, uint32_t data) { ATON_STRENG_EXTSYNC_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EXTSYNC register ------------------------------------------------------------ */ /** Description of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_EN_DESC "Enable external sync trigger mode (RO when CTRL.RUNNING)" /** Offset of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_EN_LSB 0UL /** Size in bits of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_EN_W (1UL) /** Mask for retrieving the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_EN_DT 0x0UL /** Access rights of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_EN_AC "RW" /** Check whether access to the EN field of the EXTSYNC register is secured or not. */ #define ATON_STRENG_EXTSYNC_EN_S 0 /** Check whether access to the EN field of the EXTSYNC register is privileged or not. */ #define ATON_STRENG_EXTSYNC_EN_P 0 /** Read the content of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC_EN_LSB, ATON_STRENG_EXTSYNC_EN_W) /** Modify the content of the EN field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC_EN_LSB, ATON_STRENG_EXTSYNC_EN_W, DATA) /** * Get the description of the EN field of EXTSYNC register. * * \return the description of the EN field of EXTSYNC register */ static inline const int8_t *ATON_STRENG_EXTSYNC_EN_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC_EN_DESC; } /** * Read the content of the EN field of the EXTSYNC register. * * \param[in] reg is the value of the EXTSYNC register * * \return the content of the EN field belonging to EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_Get_EN(uint32_t reg) { return ATON_STRENG_EXTSYNC_GET_EN(reg); } /** * Write the content of the EN field of the EXTSYNC register. * * \param[in] reg is the value of the EXTSYNC register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_Set_EN(uint32_t reg, uint32_t data) { return ATON_STRENG_EXTSYNC_SET_EN(reg, data); } /* ----------------------------------------------------------- SRC field of the EXTSYNC register ------------------------------------------------------------ */ /** Description of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SRC_DESC "External sync trigger source: range is 0 - 3, values not in range will be refused (RO when CTRL.RUNNING)" /** Offset of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SRC_LSB 4UL /** Size in bits of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SRC_W (4UL) /** Mask for retrieving the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SRC_MASK ATON_FIELD_MASK(4UL, 4UL) /** Reset value of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SRC_DT 0x0UL /** Access rights of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SRC_AC "RW" /** Check whether access to the SRC field of the EXTSYNC register is secured or not. */ #define ATON_STRENG_EXTSYNC_SRC_S 0 /** Check whether access to the SRC field of the EXTSYNC register is privileged or not. */ #define ATON_STRENG_EXTSYNC_SRC_P 0 /** Read the content of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_GET_SRC(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC_SRC_LSB, ATON_STRENG_EXTSYNC_SRC_W) /** Modify the content of the SRC field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SET_SRC(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC_SRC_LSB, ATON_STRENG_EXTSYNC_SRC_W, DATA) /** * Get the description of the SRC field of EXTSYNC register. * * \return the description of the SRC field of EXTSYNC register */ static inline const int8_t *ATON_STRENG_EXTSYNC_SRC_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC_SRC_DESC; } /** * Read the content of the SRC field of the EXTSYNC register. * * \param[in] reg is the value of the EXTSYNC register * * \return the content of the SRC field belonging to EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_Get_SRC(uint32_t reg) { return ATON_STRENG_EXTSYNC_GET_SRC(reg); } /** * Write the content of the SRC field of the EXTSYNC register. * * \param[in] reg is the value of the EXTSYNC register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the SRC field belonging to EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_Set_SRC(uint32_t reg, uint32_t data) { return ATON_STRENG_EXTSYNC_SET_SRC(reg, data); } /* ---------------------------------------------------------- LINES field of the EXTSYNC register ----------------------------------------------------------- */ /** Description of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_LINES_DESC "Number of lines associated to each trigger rising edge (RO when CTRL.RUNNING)" /** Offset of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_LINES_LSB 16UL /** Size in bits of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_LINES_W (16UL) /** Mask for retrieving the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_LINES_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_LINES_DT 0x0UL /** Access rights of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_LINES_AC "RW" /** Check whether access to the LINES field of the EXTSYNC register is secured or not. */ #define ATON_STRENG_EXTSYNC_LINES_S 0 /** Check whether access to the LINES field of the EXTSYNC register is privileged or not. */ #define ATON_STRENG_EXTSYNC_LINES_P 0 /** Read the content of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_GET_LINES(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC_LINES_LSB, ATON_STRENG_EXTSYNC_LINES_W) /** Modify the content of the LINES field of the EXTSYNC register. */ #define ATON_STRENG_EXTSYNC_SET_LINES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC_LINES_LSB, ATON_STRENG_EXTSYNC_LINES_W, DATA) /** * Get the description of the LINES field of EXTSYNC register. * * \return the description of the LINES field of EXTSYNC register */ static inline const int8_t *ATON_STRENG_EXTSYNC_LINES_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC_LINES_DESC; } /** * Read the content of the LINES field of the EXTSYNC register. * * \param[in] reg is the value of the EXTSYNC register * * \return the content of the LINES field belonging to EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_Get_LINES(uint32_t reg) { return ATON_STRENG_EXTSYNC_GET_LINES(reg); } /** * Write the content of the LINES field of the EXTSYNC register. * * \param[in] reg is the value of the EXTSYNC register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the LINES field belonging to EXTSYNC register */ static inline uint32_t ATON_STRENG_EXTSYNC_Set_LINES(uint32_t reg, uint32_t data) { return ATON_STRENG_EXTSYNC_SET_LINES(reg, data); } /* ****************************************************** EXTSYNC2 register of one of the STRENG Units ****************************************************** */ /** Offset of the EXTSYNC2 register from the base address of the STRENG Unit. */ #define ATON_STRENG_EXTSYNC2_OFFSET 0x50UL /** Reset value of the EXTSYNC2 register of the STRENG Unit. */ #define ATON_STRENG_EXTSYNC2_DT \ (ATON_STRENG_EXTSYNC2_LINES_DT << ATON_STRENG_EXTSYNC2_LINES_LSB) | \ (ATON_STRENG_EXTSYNC2_OFF_DT << ATON_STRENG_EXTSYNC2_OFF_LSB) /** Description of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_DESC "External triggers 2st control register (RO when CTRL.RUNNING)" /** Address of the EXTSYNC2 register of one of the STRENG Units. */ #define ATON_STRENG_EXTSYNC2_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_EXTSYNC2_OFFSET) /** Get the content of the EXTSYNC2 register of one of the STRENG Units. */ #define ATON_STRENG_EXTSYNC2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC2_ADDR(UNIT))) /** Set the content of the EXTSYNC2 register of one of the STRENG Units. */ #define ATON_STRENG_EXTSYNC2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_EXTSYNC2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EXTSYNC2 register. * * \return the description of EXTSYNC2 register */ static inline const int8_t *ATON_STRENG_EXTSYNC2_GetDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC2_DESC; } /** * Get the offset of the EXTSYNC2 register. * * \return the offset of EXTSYNC2 register */ static inline uint32_t ATON_STRENG_EXTSYNC2_GetOffset(void) { return ATON_STRENG_EXTSYNC2_OFFSET; } /** * Get the address of the EXTSYNC2 register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC2 register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of EXTSYNC2 register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_EXTSYNC2_GetAddr(uint32_t instance) { return ATON_STRENG_EXTSYNC2_ADDR(instance); } /** * Read the content of the EXTSYNC2 register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC2 register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of EXTSYNC2 register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_EXTSYNC2_Get(uint32_t instance) { return ATON_STRENG_EXTSYNC2_GET(instance); } /** * Write the content of the EXTSYNC2 register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the EXTSYNC2 register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_EXTSYNC2_Set(uint32_t instance, uint32_t data) { ATON_STRENG_EXTSYNC2_SET(instance, data); } /* ---------------------------------------------------------- LINES field of the EXTSYNC2 register ---------------------------------------------------------- */ /** Description of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_LINES_DESC "Number of lines after which the special offset will be applied (RO when CTRL.RUNNING)" /** Offset of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_LINES_LSB 0UL /** Size in bits of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_LINES_W (16UL) /** Mask for retrieving the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_LINES_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_LINES_DT 0x0UL /** Access rights of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_LINES_AC "RW" /** Check whether access to the LINES field of the EXTSYNC2 register is secured or not. */ #define ATON_STRENG_EXTSYNC2_LINES_S 0 /** Check whether access to the LINES field of the EXTSYNC2 register is privileged or not. */ #define ATON_STRENG_EXTSYNC2_LINES_P 0 /** Read the content of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_GET_LINES(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC2_LINES_LSB, ATON_STRENG_EXTSYNC2_LINES_W) /** Modify the content of the LINES field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_SET_LINES(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC2_LINES_LSB, ATON_STRENG_EXTSYNC2_LINES_W, DATA) /** * Get the description of the LINES field of EXTSYNC2 register. * * \return the description of the LINES field of EXTSYNC2 register */ static inline const int8_t *ATON_STRENG_EXTSYNC2_LINES_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC2_LINES_DESC; } /** * Read the content of the LINES field of the EXTSYNC2 register. * * \param[in] reg is the value of the EXTSYNC2 register * * \return the content of the LINES field belonging to EXTSYNC2 register */ static inline uint32_t ATON_STRENG_EXTSYNC2_Get_LINES(uint32_t reg) { return ATON_STRENG_EXTSYNC2_GET_LINES(reg); } /** * Write the content of the LINES field of the EXTSYNC2 register. * * \param[in] reg is the value of the EXTSYNC2 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the LINES field belonging to EXTSYNC2 register */ static inline uint32_t ATON_STRENG_EXTSYNC2_Set_LINES(uint32_t reg, uint32_t data) { return ATON_STRENG_EXTSYNC2_SET_LINES(reg, data); } /* ----------------------------------------------------------- OFF field of the EXTSYNC2 register ----------------------------------------------------------- */ /** Description of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_OFF_DESC "Special line offset (RO when CTRL.RUNNING)" /** Offset of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_OFF_LSB 16UL /** Size in bits of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_OFF_W (16UL) /** Mask for retrieving the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_OFF_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_OFF_DT 0x0UL /** Access rights of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_OFF_AC "RW" /** Check whether access to the OFF field of the EXTSYNC2 register is secured or not. */ #define ATON_STRENG_EXTSYNC2_OFF_S 0 /** Check whether access to the OFF field of the EXTSYNC2 register is privileged or not. */ #define ATON_STRENG_EXTSYNC2_OFF_P 0 /** Read the content of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_GET_OFF(REG) ATON_GET_FIELD(REG, ATON_STRENG_EXTSYNC2_OFF_LSB, ATON_STRENG_EXTSYNC2_OFF_W) /** Modify the content of the OFF field of the EXTSYNC2 register. */ #define ATON_STRENG_EXTSYNC2_SET_OFF(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_EXTSYNC2_OFF_LSB, ATON_STRENG_EXTSYNC2_OFF_W, DATA) /** * Get the description of the OFF field of EXTSYNC2 register. * * \return the description of the OFF field of EXTSYNC2 register */ static inline const int8_t *ATON_STRENG_EXTSYNC2_OFF_GetdDesc(void) { return (const int8_t *)ATON_STRENG_EXTSYNC2_OFF_DESC; } /** * Read the content of the OFF field of the EXTSYNC2 register. * * \param[in] reg is the value of the EXTSYNC2 register * * \return the content of the OFF field belonging to EXTSYNC2 register */ static inline uint32_t ATON_STRENG_EXTSYNC2_Get_OFF(uint32_t reg) { return ATON_STRENG_EXTSYNC2_GET_OFF(reg); } /** * Write the content of the OFF field of the EXTSYNC2 register. * * \param[in] reg is the value of the EXTSYNC2 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the OFF field belonging to EXTSYNC2 register */ static inline uint32_t ATON_STRENG_EXTSYNC2_Set_OFF(uint32_t reg, uint32_t data) { return ATON_STRENG_EXTSYNC2_SET_OFF(reg, data); } /* ***************************************************** DESCRADDR register of one of the STRENG Units ****************************************************** */ /** Offset of the DESCRADDR register from the base address of the STRENG Unit. */ #define ATON_STRENG_DESCRADDR_OFFSET 0x54UL /** Reset value of the DESCRADDR register of the STRENG Unit. */ #define ATON_STRENG_DESCRADDR_DT \ (ATON_STRENG_DESCRADDR_REG_DT << ATON_STRENG_DESCRADDR_REG_LSB) /** Description of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_DESC "Descriptor fetch address" /** Address of the DESCRADDR register of one of the STRENG Units. */ #define ATON_STRENG_DESCRADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_DESCRADDR_OFFSET) /** Get the content of the DESCRADDR register of one of the STRENG Units. */ #define ATON_STRENG_DESCRADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_DESCRADDR_ADDR(UNIT))) /** Set the content of the DESCRADDR register of one of the STRENG Units. */ #define ATON_STRENG_DESCRADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRENG_DESCRADDR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DESCRADDR register. * * \return the description of DESCRADDR register */ static inline const int8_t *ATON_STRENG_DESCRADDR_GetDesc(void) { return (const int8_t *)ATON_STRENG_DESCRADDR_DESC; } /** * Get the offset of the DESCRADDR register. * * \return the offset of DESCRADDR register */ static inline uint32_t ATON_STRENG_DESCRADDR_GetOffset(void) { return ATON_STRENG_DESCRADDR_OFFSET; } /** * Get the address of the DESCRADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DESCRADDR register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of DESCRADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_DESCRADDR_GetAddr(uint32_t instance) { return ATON_STRENG_DESCRADDR_ADDR(instance); } /** * Read the content of the DESCRADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DESCRADDR register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of DESCRADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_DESCRADDR_Get(uint32_t instance) { return ATON_STRENG_DESCRADDR_GET(instance); } /** * Write the content of the DESCRADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DESCRADDR register whose content must be modified * (it must be instance \< 10<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRENG_DESCRADDR_Set(uint32_t instance, uint32_t data) { ATON_STRENG_DESCRADDR_SET(instance, data); } /* ---------------------------------------------------------- REG field of the DESCRADDR register ----------------------------------------------------------- */ /** Description of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_REG_DESC "Descriptor fetch address. Must be 64 bit aligned (values not 64 bits aligned will be refused) (RO when CTRL.RUNNING)" /** Offset of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_REG_LSB 0UL /** Size in bits of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_REG_W (32UL) /** Mask for retrieving the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_REG_DT 0x0UL /** Access rights of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_REG_AC "RW" /** Check whether access to the REG field of the DESCRADDR register is secured or not. */ #define ATON_STRENG_DESCRADDR_REG_S 0 /** Check whether access to the REG field of the DESCRADDR register is privileged or not. */ #define ATON_STRENG_DESCRADDR_REG_P 0 /** Read the content of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_DESCRADDR_REG_LSB, ATON_STRENG_DESCRADDR_REG_W) /** Modify the content of the REG field of the DESCRADDR register. */ #define ATON_STRENG_DESCRADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_STRENG_DESCRADDR_REG_LSB, ATON_STRENG_DESCRADDR_REG_W, DATA) /** * Get the description of the REG field of DESCRADDR register. * * \return the description of the REG field of DESCRADDR register */ static inline const int8_t *ATON_STRENG_DESCRADDR_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_DESCRADDR_REG_DESC; } /** * Read the content of the REG field of the DESCRADDR register. * * \param[in] reg is the value of the DESCRADDR register * * \return the content of the REG field belonging to DESCRADDR register */ static inline uint32_t ATON_STRENG_DESCRADDR_Get_REG(uint32_t reg) { return ATON_STRENG_DESCRADDR_GET_REG(reg); } /** * Write the content of the REG field of the DESCRADDR register. * * \param[in] reg is the value of the DESCRADDR register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to DESCRADDR register */ static inline uint32_t ATON_STRENG_DESCRADDR_Set_REG(uint32_t reg, uint32_t data) { return ATON_STRENG_DESCRADDR_SET_REG(reg, data); } /* ****************************************************** LASTADDR register of one of the STRENG Units ****************************************************** */ /** Offset of the LASTADDR register from the base address of the STRENG Unit. */ #define ATON_STRENG_LASTADDR_OFFSET 0x58UL /** Reset value of the LASTADDR register of the STRENG Unit. */ #define ATON_STRENG_LASTADDR_DT \ (ATON_STRENG_LASTADDR_REG_DT << ATON_STRENG_LASTADDR_REG_LSB) /** Description of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_DESC "Address of the last transaction on master bus IF" /** Address of the LASTADDR register of one of the STRENG Units. */ #define ATON_STRENG_LASTADDR_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LASTADDR_OFFSET) /** Get the content of the LASTADDR register of one of the STRENG Units. */ #define ATON_STRENG_LASTADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LASTADDR_ADDR(UNIT))) /** * Get the description of LASTADDR register. * * \return the description of LASTADDR register */ static inline const int8_t *ATON_STRENG_LASTADDR_GetDesc(void) { return (const int8_t *)ATON_STRENG_LASTADDR_DESC; } /** * Get the offset of the LASTADDR register. * * \return the offset of LASTADDR register */ static inline uint32_t ATON_STRENG_LASTADDR_GetOffset(void) { return ATON_STRENG_LASTADDR_OFFSET; } /** * Get the address of the LASTADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LASTADDR register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of LASTADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LASTADDR_GetAddr(uint32_t instance) { return ATON_STRENG_LASTADDR_ADDR(instance); } /** * Read the content of the LASTADDR register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LASTADDR register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of LASTADDR register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LASTADDR_Get(uint32_t instance) { return ATON_STRENG_LASTADDR_GET(instance); } /* ----------------------------------------------------------- REG field of the LASTADDR register ----------------------------------------------------------- */ /** Description of the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_REG_DESC "Address of the last transaction on master bus IF" /** Offset of the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_REG_LSB 0UL /** Size in bits of the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_REG_W (32UL) /** Mask for retrieving the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_REG_DT 0x0UL /** Access rights of the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_REG_AC "R" /** Check whether access to the REG field of the LASTADDR register is secured or not. */ #define ATON_STRENG_LASTADDR_REG_S 0 /** Check whether access to the REG field of the LASTADDR register is privileged or not. */ #define ATON_STRENG_LASTADDR_REG_P 0 /** Read the content of the REG field of the LASTADDR register. */ #define ATON_STRENG_LASTADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_LASTADDR_REG_LSB, ATON_STRENG_LASTADDR_REG_W) /** * Get the description of the REG field of LASTADDR register. * * \return the description of the REG field of LASTADDR register */ static inline const int8_t *ATON_STRENG_LASTADDR_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LASTADDR_REG_DESC; } /** * Read the content of the REG field of the LASTADDR register. * * \param[in] reg is the value of the LASTADDR register * * \return the content of the REG field belonging to LASTADDR register */ static inline uint32_t ATON_STRENG_LASTADDR_Get_REG(uint32_t reg) { return ATON_STRENG_LASTADDR_GET_REG(reg); } /* ****************************************************** DEPTHCNT register of one of the STRENG Units ****************************************************** */ /** Offset of the DEPTHCNT register from the base address of the STRENG Unit. */ #define ATON_STRENG_DEPTHCNT_OFFSET 0x5cUL /** Reset value of the DEPTHCNT register of the STRENG Unit. */ #define ATON_STRENG_DEPTHCNT_DT \ (ATON_STRENG_DEPTHCNT_REG_DT << ATON_STRENG_DEPTHCNT_REG_LSB) /** Description of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_DESC "Current processed sub-pixel (1 to depth size)" /** Address of the DEPTHCNT register of one of the STRENG Units. */ #define ATON_STRENG_DEPTHCNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_DEPTHCNT_OFFSET) /** Get the content of the DEPTHCNT register of one of the STRENG Units. */ #define ATON_STRENG_DEPTHCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_DEPTHCNT_ADDR(UNIT))) /** * Get the description of DEPTHCNT register. * * \return the description of DEPTHCNT register */ static inline const int8_t *ATON_STRENG_DEPTHCNT_GetDesc(void) { return (const int8_t *)ATON_STRENG_DEPTHCNT_DESC; } /** * Get the offset of the DEPTHCNT register. * * \return the offset of DEPTHCNT register */ static inline uint32_t ATON_STRENG_DEPTHCNT_GetOffset(void) { return ATON_STRENG_DEPTHCNT_OFFSET; } /** * Get the address of the DEPTHCNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTHCNT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of DEPTHCNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_DEPTHCNT_GetAddr(uint32_t instance) { return ATON_STRENG_DEPTHCNT_ADDR(instance); } /** * Read the content of the DEPTHCNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the DEPTHCNT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of DEPTHCNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_DEPTHCNT_Get(uint32_t instance) { return ATON_STRENG_DEPTHCNT_GET(instance); } /* ----------------------------------------------------------- REG field of the DEPTHCNT register ----------------------------------------------------------- */ /** Description of the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_REG_DESC "Current processed sub-pixel (1 to depth size)" /** Offset of the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_REG_LSB 0UL /** Size in bits of the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_REG_W (32UL) /** Mask for retrieving the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_REG_DT 0x1UL /** Access rights of the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_REG_AC "R" /** Check whether access to the REG field of the DEPTHCNT register is secured or not. */ #define ATON_STRENG_DEPTHCNT_REG_S 0 /** Check whether access to the REG field of the DEPTHCNT register is privileged or not. */ #define ATON_STRENG_DEPTHCNT_REG_P 0 /** Read the content of the REG field of the DEPTHCNT register. */ #define ATON_STRENG_DEPTHCNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_DEPTHCNT_REG_LSB, ATON_STRENG_DEPTHCNT_REG_W) /** * Get the description of the REG field of DEPTHCNT register. * * \return the description of the REG field of DEPTHCNT register */ static inline const int8_t *ATON_STRENG_DEPTHCNT_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_DEPTHCNT_REG_DESC; } /** * Read the content of the REG field of the DEPTHCNT register. * * \param[in] reg is the value of the DEPTHCNT register * * \return the content of the REG field belonging to DEPTHCNT register */ static inline uint32_t ATON_STRENG_DEPTHCNT_Get_REG(uint32_t reg) { return ATON_STRENG_DEPTHCNT_GET_REG(reg); } /* ******************************************************* PIXCNT register of one of the STRENG Units ******************************************************* */ /** Offset of the PIXCNT register from the base address of the STRENG Unit. */ #define ATON_STRENG_PIXCNT_OFFSET 0x60UL /** Reset value of the PIXCNT register of the STRENG Unit. */ #define ATON_STRENG_PIXCNT_DT \ (ATON_STRENG_PIXCNT_REG_DT << ATON_STRENG_PIXCNT_REG_LSB) /** Description of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_DESC "Current processed pixel (1 to line width)" /** Address of the PIXCNT register of one of the STRENG Units. */ #define ATON_STRENG_PIXCNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_PIXCNT_OFFSET) /** Get the content of the PIXCNT register of one of the STRENG Units. */ #define ATON_STRENG_PIXCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_PIXCNT_ADDR(UNIT))) /** * Get the description of PIXCNT register. * * \return the description of PIXCNT register */ static inline const int8_t *ATON_STRENG_PIXCNT_GetDesc(void) { return (const int8_t *)ATON_STRENG_PIXCNT_DESC; } /** * Get the offset of the PIXCNT register. * * \return the offset of PIXCNT register */ static inline uint32_t ATON_STRENG_PIXCNT_GetOffset(void) { return ATON_STRENG_PIXCNT_OFFSET; } /** * Get the address of the PIXCNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the PIXCNT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of PIXCNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_PIXCNT_GetAddr(uint32_t instance) { return ATON_STRENG_PIXCNT_ADDR(instance); } /** * Read the content of the PIXCNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the PIXCNT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of PIXCNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_PIXCNT_Get(uint32_t instance) { return ATON_STRENG_PIXCNT_GET(instance); } /* ------------------------------------------------------------ REG field of the PIXCNT register ------------------------------------------------------------ */ /** Description of the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_REG_DESC "Current processed pixel (1 to frame width)" /** Offset of the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_REG_LSB 0UL /** Size in bits of the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_REG_W (32UL) /** Mask for retrieving the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_REG_DT 0x1UL /** Access rights of the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_REG_AC "R" /** Check whether access to the REG field of the PIXCNT register is secured or not. */ #define ATON_STRENG_PIXCNT_REG_S 0 /** Check whether access to the REG field of the PIXCNT register is privileged or not. */ #define ATON_STRENG_PIXCNT_REG_P 0 /** Read the content of the REG field of the PIXCNT register. */ #define ATON_STRENG_PIXCNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_PIXCNT_REG_LSB, ATON_STRENG_PIXCNT_REG_W) /** * Get the description of the REG field of PIXCNT register. * * \return the description of the REG field of PIXCNT register */ static inline const int8_t *ATON_STRENG_PIXCNT_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_PIXCNT_REG_DESC; } /** * Read the content of the REG field of the PIXCNT register. * * \param[in] reg is the value of the PIXCNT register * * \return the content of the REG field belonging to PIXCNT register */ static inline uint32_t ATON_STRENG_PIXCNT_Get_REG(uint32_t reg) { return ATON_STRENG_PIXCNT_GET_REG(reg); } /* ****************************************************** LINECNT register of one of the STRENG Units ******************************************************* */ /** Offset of the LINECNT register from the base address of the STRENG Unit. */ #define ATON_STRENG_LINECNT_OFFSET 0x64UL /** Reset value of the LINECNT register of the STRENG Unit. */ #define ATON_STRENG_LINECNT_DT \ (ATON_STRENG_LINECNT_REG_DT << ATON_STRENG_LINECNT_REG_LSB) /** Description of the LINECNT register. */ #define ATON_STRENG_LINECNT_DESC "Current processed line (1 to frame height)" /** Address of the LINECNT register of one of the STRENG Units. */ #define ATON_STRENG_LINECNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_LINECNT_OFFSET) /** Get the content of the LINECNT register of one of the STRENG Units. */ #define ATON_STRENG_LINECNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_LINECNT_ADDR(UNIT))) /** * Get the description of LINECNT register. * * \return the description of LINECNT register */ static inline const int8_t *ATON_STRENG_LINECNT_GetDesc(void) { return (const int8_t *)ATON_STRENG_LINECNT_DESC; } /** * Get the offset of the LINECNT register. * * \return the offset of LINECNT register */ static inline uint32_t ATON_STRENG_LINECNT_GetOffset(void) { return ATON_STRENG_LINECNT_OFFSET; } /** * Get the address of the LINECNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LINECNT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of LINECNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LINECNT_GetAddr(uint32_t instance) { return ATON_STRENG_LINECNT_ADDR(instance); } /** * Read the content of the LINECNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the LINECNT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of LINECNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_LINECNT_Get(uint32_t instance) { return ATON_STRENG_LINECNT_GET(instance); } /* ----------------------------------------------------------- REG field of the LINECNT register ------------------------------------------------------------ */ /** Description of the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_REG_DESC "Current processed line (1 to frame height)" /** Offset of the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_REG_LSB 0UL /** Size in bits of the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_REG_W (32UL) /** Mask for retrieving the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_REG_DT 0x1UL /** Access rights of the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_REG_AC "R" /** Check whether access to the REG field of the LINECNT register is secured or not. */ #define ATON_STRENG_LINECNT_REG_S 0 /** Check whether access to the REG field of the LINECNT register is privileged or not. */ #define ATON_STRENG_LINECNT_REG_P 0 /** Read the content of the REG field of the LINECNT register. */ #define ATON_STRENG_LINECNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_LINECNT_REG_LSB, ATON_STRENG_LINECNT_REG_W) /** * Get the description of the REG field of LINECNT register. * * \return the description of the REG field of LINECNT register */ static inline const int8_t *ATON_STRENG_LINECNT_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_LINECNT_REG_DESC; } /** * Read the content of the REG field of the LINECNT register. * * \param[in] reg is the value of the LINECNT register * * \return the content of the REG field belonging to LINECNT register */ static inline uint32_t ATON_STRENG_LINECNT_Get_REG(uint32_t reg) { return ATON_STRENG_LINECNT_GET_REG(reg); } /* ******************************************************** FCNT register of one of the STRENG Units ******************************************************** */ /** Offset of the FCNT register from the base address of the STRENG Unit. */ #define ATON_STRENG_FCNT_OFFSET 0x68UL /** Reset value of the FCNT register of the STRENG Unit. */ #define ATON_STRENG_FCNT_DT \ (ATON_STRENG_FCNT_REG_DT << ATON_STRENG_FCNT_REG_LSB) /** Description of the FCNT register. */ #define ATON_STRENG_FCNT_DESC "Frame counter" /** Address of the FCNT register of one of the STRENG Units. */ #define ATON_STRENG_FCNT_ADDR(UNIT) (ATON_STRENG_BASE(UNIT) + ATON_STRENG_FCNT_OFFSET) /** Get the content of the FCNT register of one of the STRENG Units. */ #define ATON_STRENG_FCNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRENG_FCNT_ADDR(UNIT))) /** * Get the description of FCNT register. * * \return the description of FCNT register */ static inline const int8_t *ATON_STRENG_FCNT_GetDesc(void) { return (const int8_t *)ATON_STRENG_FCNT_DESC; } /** * Get the offset of the FCNT register. * * \return the offset of FCNT register */ static inline uint32_t ATON_STRENG_FCNT_GetOffset(void) { return ATON_STRENG_FCNT_OFFSET; } /** * Get the address of the FCNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FCNT register whose address must be returned * (it must be instance \< 10<\em>) * * \return the address of FCNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FCNT_GetAddr(uint32_t instance) { return ATON_STRENG_FCNT_ADDR(instance); } /** * Read the content of the FCNT register. * * \param[in] instance is the index of the Unit (among the STRENG Units) containing the FCNT register whose content must be retrieved * (it must be instance \< 10<\em>) * * \return the content of FCNT register belonging to Unit having index \e instance among the STRENG Units */ static inline uint32_t ATON_STRENG_FCNT_Get(uint32_t instance) { return ATON_STRENG_FCNT_GET(instance); } /* ------------------------------------------------------------- REG field of the FCNT register ------------------------------------------------------------- */ /** Description of the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_REG_DESC "Frame counter" /** Offset of the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_REG_LSB 0UL /** Size in bits of the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_REG_W (32UL) /** Mask for retrieving the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_REG_DT 0x1UL /** Access rights of the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_REG_AC "R" /** Check whether access to the REG field of the FCNT register is secured or not. */ #define ATON_STRENG_FCNT_REG_S 0 /** Check whether access to the REG field of the FCNT register is privileged or not. */ #define ATON_STRENG_FCNT_REG_P 0 /** Read the content of the REG field of the FCNT register. */ #define ATON_STRENG_FCNT_GET_REG(REG) ATON_GET_FIELD(REG, ATON_STRENG_FCNT_REG_LSB, ATON_STRENG_FCNT_REG_W) /** * Get the description of the REG field of FCNT register. * * \return the description of the REG field of FCNT register */ static inline const int8_t *ATON_STRENG_FCNT_REG_GetdDesc(void) { return (const int8_t *)ATON_STRENG_FCNT_REG_DESC; } /** * Read the content of the REG field of the FCNT register. * * \param[in] reg is the value of the FCNT register * * \return the content of the REG field belonging to FCNT register */ static inline uint32_t ATON_STRENG_FCNT_Get_REG(uint32_t reg) { return ATON_STRENG_FCNT_GET_REG(reg); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* STRSWITCH Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of STRSWITCH Unit instances. */ #define ATON_STRSWITCH_NUM 1 /** * \name Structures, macros and functions of the STRSWITCH Units */ /*@{*/ /** * Registers of the STRSWITCH Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e DSTSTRENG0 register (Connection to input port of Stream Engine 0). */ uint32_t DSTSTRENG0; /** \e DSTSTRENG1 register (Connection to input port of Stream Engine 1). */ uint32_t DSTSTRENG1; /** \e DSTSTRENG2 register (Connection to input port of Stream Engine 2). */ uint32_t DSTSTRENG2; /** \e DSTSTRENG3 register (Connection to input port of Stream Engine 3). */ uint32_t DSTSTRENG3; /** \e DSTSTRENG4 register (Connection to input port of Stream Engine 4). */ uint32_t DSTSTRENG4; /** \e DSTSTRENG5 register (Connection to input port of Stream Engine 5). */ uint32_t DSTSTRENG5; /** \e DSTSTRENG6 register (Connection to input port of Stream Engine 6). */ uint32_t DSTSTRENG6; /** \e DSTSTRENG7 register (Connection to input port of Stream Engine 7). */ uint32_t DSTSTRENG7; /** \e DSTSTRENG8 register (Connection to input port of Stream Engine 8). */ uint32_t DSTSTRENG8; /** \e DSTSTRENG9 register (Connection to input port of Stream Engine 9). */ uint32_t DSTSTRENG9; /** \e DSTCONVACC00 register (Connection to input port 0 of Convolutional Accelerator 0). */ uint32_t DSTCONVACC00; /** \e DSTCONVACC01 register (Connection to input port 1 of Convolutional Accelerator 0). */ uint32_t DSTCONVACC01; /** \e DSTCONVACC02 register (Connection to input port 2 of Convolutional Accelerator 0). */ uint32_t DSTCONVACC02; /** \e DSTCONVACC10 register (Connection to input port 0 of Convolutional Accelerator 1). */ uint32_t DSTCONVACC10; /** \e DSTCONVACC11 register (Connection to input port 1 of Convolutional Accelerator 1). */ uint32_t DSTCONVACC11; /** \e DSTCONVACC12 register (Connection to input port 2 of Convolutional Accelerator 1). */ uint32_t DSTCONVACC12; /** \e DSTCONVACC20 register (Connection to input port 0 of Convolutional Accelerator 2). */ uint32_t DSTCONVACC20; /** \e DSTCONVACC21 register (Connection to input port 1 of Convolutional Accelerator 2). */ uint32_t DSTCONVACC21; /** \e DSTCONVACC22 register (Connection to input port 2 of Convolutional Accelerator 2). */ uint32_t DSTCONVACC22; /** \e DSTCONVACC30 register (Connection to input port 0 of Convolutional Accelerator 3). */ uint32_t DSTCONVACC30; /** \e DSTCONVACC31 register (Connection to input port 1 of Convolutional Accelerator 3). */ uint32_t DSTCONVACC31; /** \e DSTCONVACC32 register (Connection to input port 2 of Convolutional Accelerator 3). */ uint32_t DSTCONVACC32; /** \e DSTDECUN00 register (Connection to input port 0 of Decompression Unit 0). */ uint32_t DSTDECUN00; /** \e DSTDECUN01 register (Connection to input port 1 of Decompression Unit 0). */ uint32_t DSTDECUN01; /** \e DSTDECUN10 register (Connection to input port 0 of Decompression Unit 1). */ uint32_t DSTDECUN10; /** \e DSTDECUN11 register (Connection to input port 1 of Decompression Unit 1). */ uint32_t DSTDECUN11; /** \e DSTACTIV0 register (Connection to input port of Activation Accelerator 0). */ uint32_t DSTACTIV0; /** \e DSTACTIV1 register (Connection to input port of Activation Accelerator 1). */ uint32_t DSTACTIV1; /** \e DSTARITH00 register (Connection to input port 0 of Arithmetic Accelerator 0). */ uint32_t DSTARITH00; /** \e DSTARITH01 register (Connection to input port 1 of Arithmetic Accelerator 0). */ uint32_t DSTARITH01; /** \e DSTARITH10 register (Connection to input port 0 of Arithmetic Accelerator 1). */ uint32_t DSTARITH10; /** \e DSTARITH11 register (Connection to input port 1 of Arithmetic Accelerator 1). */ uint32_t DSTARITH11; /** \e DSTARITH20 register (Connection to input port 0 of Arithmetic Accelerator 2). */ uint32_t DSTARITH20; /** \e DSTARITH21 register (Connection to input port 1 of Arithmetic Accelerator 2). */ uint32_t DSTARITH21; /** \e DSTARITH30 register (Connection to input port 0 of Arithmetic Accelerator 3). */ uint32_t DSTARITH30; /** \e DSTARITH31 register (Connection to input port 1 of Arithmetic Accelerator 3). */ uint32_t DSTARITH31; /** \e DSTPOOL0 register (Connection to input port of Pooling Accelerator 0). */ uint32_t DSTPOOL0; /** \e DSTPOOL1 register (Connection to input port of Pooling Accelerator 1). */ uint32_t DSTPOOL1; /** \e DSTRECBUF00 register (Connection to input port 0 of Reconfigurable Buffer 0). */ uint32_t DSTRECBUF00; /** \e DSTRECBUF01 register (Connection to input port 1 of Reconfigurable Buffer 0). */ uint32_t DSTRECBUF01; /** \e DSTRECBUF02 register (Connection to input port 2 of Reconfigurable Buffer 0). */ uint32_t DSTRECBUF02; } ATON_STRSWITCH_t; /** Return the pointer to one of the STRSWITCH Units. */ #define ATON_STRSWITCH(UNIT) ((ATON_STRSWITCH_t *)(intptr_t)ATON_STRSWITCH_BASE(UNIT)) /** Name of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_NAME(UNIT) \ (((UNIT) == 0) ? "STRSWITCH" : "") /** Version of the STRSWITCH Units. */ #define ATON_STRSWITCH_VERSION "1.6" /** Description of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DESC(UNIT) \ (((UNIT) == 0) ? "Stream Switch" : "") /** Base address of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_BASE(UNIT) \ (ATON_BASE + 0x4000UL + ((UNIT) * 0x0UL)) /** Size in bytes of the STRSWITCH Units. */ #define ATON_STRSWITCH_SIZE 0x1000UL /** * Get the name of one of the STRSWITCH Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) * * \return the name of Unit having index \e instance among the STRSWITCH Units */ static inline const int8_t *ATON_STRSWITCH_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"STRSWITCH"; break; default: break; } return str; } /** * Get the description of one of the STRSWITCH Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) * * \return the description of Unit having index \e instance among the STRSWITCH Units */ static inline const int8_t *ATON_STRSWITCH_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Stream Switch"; break; default: break; } return str; } /** * Get the version of the STRSWITCH Units. * * \return the version of the STRSWITCH Units */ static inline const int8_t *ATON_STRSWITCH_GetVersion(void) { return (const int8_t *)ATON_STRSWITCH_VERSION; } /** * Get the base address of one of the STRSWITCH Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) * * \return the base address of Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_GetBase(uint32_t instance) { return ATON_STRSWITCH_BASE(instance); } /** * Get the size in bytes of the STRSWITCH Units. * * \return the size in bytes of the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_GetSize(void) { return ATON_STRSWITCH_SIZE; } /* ****************************************************** CTRL register of one of the STRSWITCH Units ******************************************************* */ /** Offset of the CTRL register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_CTRL_DT \ (ATON_STRSWITCH_CTRL_EN_DT << ATON_STRSWITCH_CTRL_EN_LSB) | \ (ATON_STRSWITCH_CTRL_CLR_DT << ATON_STRSWITCH_CTRL_CLR_LSB) | \ (ATON_STRSWITCH_CTRL_CONFCLR_DT << ATON_STRSWITCH_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_STRSWITCH_CTRL_DESC "Control register" /** Address of the CTRL register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_CTRL_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_CTRL_OFFSET) /** Get the content of the CTRL register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_STRSWITCH_CTRL_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_GetOffset(void) { return ATON_STRSWITCH_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the CTRL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_CTRL_GetAddr(uint32_t instance) { return ATON_STRSWITCH_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_CTRL_Get(uint32_t instance) { return ATON_STRSWITCH_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the CTRL register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_CTRL_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_EN_DESC "Enable the Stream Switch" /** Offset of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_STRSWITCH_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_STRSWITCH_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_CTRL_EN_LSB, ATON_STRSWITCH_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_CTRL_EN_LSB, ATON_STRSWITCH_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_STRSWITCH_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_Get_EN(uint32_t reg) { return ATON_STRSWITCH_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_STRSWITCH_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_STRSWITCH_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_CTRL_CLR_LSB, ATON_STRSWITCH_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_CTRL_CLR_LSB, ATON_STRSWITCH_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_STRSWITCH_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_Get_CLR(uint32_t reg) { return ATON_STRSWITCH_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_STRSWITCH_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_STRSWITCH_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_CTRL_CONFCLR_LSB, ATON_STRSWITCH_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_STRSWITCH_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_CTRL_CONFCLR_LSB, ATON_STRSWITCH_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_STRSWITCH_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_STRSWITCH_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_STRSWITCH_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_CTRL_SET_CONFCLR(reg, data); } /* ***************************************************** VERSION register of one of the STRSWITCH Units ***************************************************** */ /** Offset of the VERSION register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_VERSION_DT \ (ATON_STRSWITCH_VERSION_TYPE_DT << ATON_STRSWITCH_VERSION_TYPE_LSB) | \ (ATON_STRSWITCH_VERSION_MINOR_DT << ATON_STRSWITCH_VERSION_MINOR_LSB) | \ (ATON_STRSWITCH_VERSION_MAJOR_DT << ATON_STRSWITCH_VERSION_MAJOR_LSB) | \ (ATON_STRSWITCH_VERSION_IPORTS_DT << ATON_STRSWITCH_VERSION_IPORTS_LSB) | \ (ATON_STRSWITCH_VERSION_OPORTS_DT << ATON_STRSWITCH_VERSION_OPORTS_LSB) /** Description of the VERSION register. */ #define ATON_STRSWITCH_VERSION_DESC "Version register" /** Address of the VERSION register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_VERSION_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_VERSION_OFFSET) /** Get the content of the VERSION register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_STRSWITCH_VERSION_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_STRSWITCH_VERSION_GetOffset(void) { return ATON_STRSWITCH_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the VERSION register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_VERSION_GetAddr(uint32_t instance) { return ATON_STRSWITCH_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_VERSION_Get(uint32_t instance) { return ATON_STRSWITCH_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_TYPE_DT 0x0UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_STRSWITCH_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_STRSWITCH_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_TYPE_LSB, ATON_STRSWITCH_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_STRSWITCH_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_STRSWITCH_VERSION_Get_TYPE(uint32_t reg) { return ATON_STRSWITCH_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MINOR_DT 0x6UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_STRSWITCH_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_STRSWITCH_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_MINOR_LSB, ATON_STRSWITCH_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_STRSWITCH_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_STRSWITCH_VERSION_Get_MINOR(uint32_t reg) { return ATON_STRSWITCH_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_STRSWITCH_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_STRSWITCH_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_MAJOR_LSB, ATON_STRSWITCH_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_STRSWITCH_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_STRSWITCH_VERSION_Get_MAJOR(uint32_t reg) { return ATON_STRSWITCH_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- IPORTS field of the VERSION register ---------------------------------------------------------- */ /** Description of the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_IPORTS_DESC "Input Stream Links" /** Offset of the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_IPORTS_LSB 16UL /** Size in bits of the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_IPORTS_W (8UL) /** Mask for retrieving the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_IPORTS_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_IPORTS_DT 0x1bUL /** Access rights of the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_IPORTS_AC "R" /** Check whether access to the IPORTS field of the VERSION register is secured or not. */ #define ATON_STRSWITCH_VERSION_IPORTS_S 0 /** Check whether access to the IPORTS field of the VERSION register is privileged or not. */ #define ATON_STRSWITCH_VERSION_IPORTS_P 0 /** Read the content of the IPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_GET_IPORTS(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_IPORTS_LSB, ATON_STRSWITCH_VERSION_IPORTS_W) /** * Get the description of the IPORTS field of VERSION register. * * \return the description of the IPORTS field of VERSION register */ static inline const int8_t *ATON_STRSWITCH_VERSION_IPORTS_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_VERSION_IPORTS_DESC; } /** * Read the content of the IPORTS field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the IPORTS field belonging to VERSION register */ static inline uint32_t ATON_STRSWITCH_VERSION_Get_IPORTS(uint32_t reg) { return ATON_STRSWITCH_VERSION_GET_IPORTS(reg); } /* ---------------------------------------------------------- OPORTS field of the VERSION register ---------------------------------------------------------- */ /** Description of the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_OPORTS_DESC "Output Stream Links" /** Offset of the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_OPORTS_LSB 24UL /** Size in bits of the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_OPORTS_W (8UL) /** Mask for retrieving the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_OPORTS_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_OPORTS_DT 0x29UL /** Access rights of the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_OPORTS_AC "R" /** Check whether access to the OPORTS field of the VERSION register is secured or not. */ #define ATON_STRSWITCH_VERSION_OPORTS_S 0 /** Check whether access to the OPORTS field of the VERSION register is privileged or not. */ #define ATON_STRSWITCH_VERSION_OPORTS_P 0 /** Read the content of the OPORTS field of the VERSION register. */ #define ATON_STRSWITCH_VERSION_GET_OPORTS(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_VERSION_OPORTS_LSB, ATON_STRSWITCH_VERSION_OPORTS_W) /** * Get the description of the OPORTS field of VERSION register. * * \return the description of the OPORTS field of VERSION register */ static inline const int8_t *ATON_STRSWITCH_VERSION_OPORTS_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_VERSION_OPORTS_DESC; } /** * Read the content of the OPORTS field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the OPORTS field belonging to VERSION register */ static inline uint32_t ATON_STRSWITCH_VERSION_Get_OPORTS(uint32_t reg) { return ATON_STRSWITCH_VERSION_GET_OPORTS(reg); } /* *************************************************** DSTSTRENG0 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG0 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG0_OFFSET 0x8UL /** Reset value of the DSTSTRENG0 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG0_DT \ (ATON_STRSWITCH_DSTSTRENG0_EN0_DT << ATON_STRSWITCH_DSTSTRENG0_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG0_LINK0_DT << ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG0_FNR0_DT << ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG0_EN1_DT << ATON_STRSWITCH_DSTSTRENG0_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG0_LINK1_DT << ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG0_FNR1_DT << ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB) /** Description of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_DESC "Connection to input port of Stream Engine 0" /** Address of the DSTSTRENG0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG0_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG0_OFFSET) /** Get the content of the DSTSTRENG0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG0_ADDR(UNIT))) /** Set the content of the DSTSTRENG0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG0 register. * * \return the description of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_DESC; } /** * Get the offset of the DSTSTRENG0 register. * * \return the offset of DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG0_OFFSET; } /** * Get the address of the DSTSTRENG0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG0 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG0_ADDR(instance); } /** * Read the content of the DSTSTRENG0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG0 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG0_GET(instance); } /** * Write the content of the DSTSTRENG0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG0_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG0_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG0 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN0_LSB, ATON_STRSWITCH_DSTSTRENG0_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN0_LSB, ATON_STRSWITCH_DSTSTRENG0_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG0 register. * * \return the description of the EN0 field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the EN0 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG0 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG0 register. * * \return the description of the LINK0 field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the LINK0 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG0 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG0 register. * * \return the description of the FNR0 field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the FNR0 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG0 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN1_LSB, ATON_STRSWITCH_DSTSTRENG0_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_EN1_LSB, ATON_STRSWITCH_DSTSTRENG0_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG0 register. * * \return the description of the EN1 field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the EN1 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG0 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG0_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG0 register. * * \return the description of the LINK1 field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the LINK1 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG0 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG0 register. * * \return the description of the TICKTYPE field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG0 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG0 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG0 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG0_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG0 register. */ #define ATON_STRSWITCH_DSTSTRENG0_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG0_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG0 register. * * \return the description of the FNR1 field of DSTSTRENG0 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG0_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG0_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * * \return the content of the FNR1 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG0_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG0 register. * * \param[in] reg is the value of the DSTSTRENG0 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG0 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG0_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG0_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG1 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG1 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG1_OFFSET 0xcUL /** Reset value of the DSTSTRENG1 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG1_DT \ (ATON_STRSWITCH_DSTSTRENG1_EN0_DT << ATON_STRSWITCH_DSTSTRENG1_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG1_LINK0_DT << ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG1_FNR0_DT << ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG1_EN1_DT << ATON_STRSWITCH_DSTSTRENG1_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG1_LINK1_DT << ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG1_FNR1_DT << ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB) /** Description of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_DESC "Connection to input port of Stream Engine 1" /** Address of the DSTSTRENG1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG1_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG1_OFFSET) /** Get the content of the DSTSTRENG1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG1_ADDR(UNIT))) /** Set the content of the DSTSTRENG1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG1 register. * * \return the description of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_DESC; } /** * Get the offset of the DSTSTRENG1 register. * * \return the offset of DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG1_OFFSET; } /** * Get the address of the DSTSTRENG1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG1 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG1_ADDR(instance); } /** * Read the content of the DSTSTRENG1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG1 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG1_GET(instance); } /** * Write the content of the DSTSTRENG1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG1_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG1_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG1 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN0_LSB, ATON_STRSWITCH_DSTSTRENG1_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN0_LSB, ATON_STRSWITCH_DSTSTRENG1_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG1 register. * * \return the description of the EN0 field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the EN0 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG1 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG1 register. * * \return the description of the LINK0 field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the LINK0 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG1 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG1 register. * * \return the description of the FNR0 field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the FNR0 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG1 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN1_LSB, ATON_STRSWITCH_DSTSTRENG1_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_EN1_LSB, ATON_STRSWITCH_DSTSTRENG1_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG1 register. * * \return the description of the EN1 field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the EN1 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG1 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG1_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG1 register. * * \return the description of the LINK1 field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the LINK1 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG1 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG1 register. * * \return the description of the TICKTYPE field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG1 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG1 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG1 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG1_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG1 register. */ #define ATON_STRSWITCH_DSTSTRENG1_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG1_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG1_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG1 register. * * \return the description of the FNR1 field of DSTSTRENG1 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG1_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG1_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * * \return the content of the FNR1 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG1_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG1 register. * * \param[in] reg is the value of the DSTSTRENG1 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG1 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG1_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG1_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG2 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG2 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG2_OFFSET 0x10UL /** Reset value of the DSTSTRENG2 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG2_DT \ (ATON_STRSWITCH_DSTSTRENG2_EN0_DT << ATON_STRSWITCH_DSTSTRENG2_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG2_LINK0_DT << ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG2_FNR0_DT << ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG2_EN1_DT << ATON_STRSWITCH_DSTSTRENG2_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG2_LINK1_DT << ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG2_FNR1_DT << ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB) /** Description of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_DESC "Connection to input port of Stream Engine 2" /** Address of the DSTSTRENG2 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG2_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG2_OFFSET) /** Get the content of the DSTSTRENG2 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG2_ADDR(UNIT))) /** Set the content of the DSTSTRENG2 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG2 register. * * \return the description of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_DESC; } /** * Get the offset of the DSTSTRENG2 register. * * \return the offset of DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG2_OFFSET; } /** * Get the address of the DSTSTRENG2 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG2 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG2 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG2_ADDR(instance); } /** * Read the content of the DSTSTRENG2 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG2 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG2 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG2_GET(instance); } /** * Write the content of the DSTSTRENG2 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG2 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG2_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG2_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG2 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN0_LSB, ATON_STRSWITCH_DSTSTRENG2_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN0_LSB, ATON_STRSWITCH_DSTSTRENG2_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG2 register. * * \return the description of the EN0 field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the EN0 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG2 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG2 register. * * \return the description of the LINK0 field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the LINK0 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG2 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG2 register. * * \return the description of the FNR0 field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the FNR0 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG2 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN1_LSB, ATON_STRSWITCH_DSTSTRENG2_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_EN1_LSB, ATON_STRSWITCH_DSTSTRENG2_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG2 register. * * \return the description of the EN1 field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the EN1 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG2 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG2_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG2 register. * * \return the description of the LINK1 field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the LINK1 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG2 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG2 register. * * \return the description of the TICKTYPE field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG2 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG2 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG2 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG2_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG2 register. */ #define ATON_STRSWITCH_DSTSTRENG2_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG2_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG2_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG2 register. * * \return the description of the FNR1 field of DSTSTRENG2 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG2_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG2_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * * \return the content of the FNR1 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG2_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG2 register. * * \param[in] reg is the value of the DSTSTRENG2 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG2 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG2_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG2_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG3 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG3 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG3_OFFSET 0x14UL /** Reset value of the DSTSTRENG3 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG3_DT \ (ATON_STRSWITCH_DSTSTRENG3_EN0_DT << ATON_STRSWITCH_DSTSTRENG3_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG3_LINK0_DT << ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG3_FNR0_DT << ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG3_EN1_DT << ATON_STRSWITCH_DSTSTRENG3_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG3_LINK1_DT << ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG3_FNR1_DT << ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB) /** Description of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_DESC "Connection to input port of Stream Engine 3" /** Address of the DSTSTRENG3 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG3_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG3_OFFSET) /** Get the content of the DSTSTRENG3 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG3_ADDR(UNIT))) /** Set the content of the DSTSTRENG3 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG3_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG3 register. * * \return the description of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_DESC; } /** * Get the offset of the DSTSTRENG3 register. * * \return the offset of DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG3_OFFSET; } /** * Get the address of the DSTSTRENG3 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG3 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG3 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG3_ADDR(instance); } /** * Read the content of the DSTSTRENG3 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG3 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG3 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG3_GET(instance); } /** * Write the content of the DSTSTRENG3 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG3 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG3_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG3_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG3 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN0_LSB, ATON_STRSWITCH_DSTSTRENG3_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN0_LSB, ATON_STRSWITCH_DSTSTRENG3_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG3 register. * * \return the description of the EN0 field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the EN0 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG3 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG3 register. * * \return the description of the LINK0 field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the LINK0 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG3 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG3 register. * * \return the description of the FNR0 field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the FNR0 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG3 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN1_LSB, ATON_STRSWITCH_DSTSTRENG3_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_EN1_LSB, ATON_STRSWITCH_DSTSTRENG3_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG3 register. * * \return the description of the EN1 field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the EN1 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG3 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG3_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG3 register. * * \return the description of the LINK1 field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the LINK1 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG3 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG3 register. * * \return the description of the TICKTYPE field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG3 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG3 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG3 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG3_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG3 register. */ #define ATON_STRSWITCH_DSTSTRENG3_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG3_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG3_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG3 register. * * \return the description of the FNR1 field of DSTSTRENG3 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG3_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG3_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * * \return the content of the FNR1 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG3_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG3 register. * * \param[in] reg is the value of the DSTSTRENG3 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG3 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG3_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG3_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG4 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG4 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG4_OFFSET 0x18UL /** Reset value of the DSTSTRENG4 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG4_DT \ (ATON_STRSWITCH_DSTSTRENG4_EN0_DT << ATON_STRSWITCH_DSTSTRENG4_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG4_LINK0_DT << ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG4_FNR0_DT << ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG4_EN1_DT << ATON_STRSWITCH_DSTSTRENG4_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG4_LINK1_DT << ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG4_FNR1_DT << ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB) /** Description of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_DESC "Connection to input port of Stream Engine 4" /** Address of the DSTSTRENG4 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG4_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG4_OFFSET) /** Get the content of the DSTSTRENG4 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG4_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG4_ADDR(UNIT))) /** Set the content of the DSTSTRENG4 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG4_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG4_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG4 register. * * \return the description of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_DESC; } /** * Get the offset of the DSTSTRENG4 register. * * \return the offset of DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG4_OFFSET; } /** * Get the address of the DSTSTRENG4 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG4 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG4 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG4_ADDR(instance); } /** * Read the content of the DSTSTRENG4 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG4 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG4 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG4_GET(instance); } /** * Write the content of the DSTSTRENG4 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG4 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG4_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG4_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG4 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN0_LSB, ATON_STRSWITCH_DSTSTRENG4_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN0_LSB, ATON_STRSWITCH_DSTSTRENG4_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG4 register. * * \return the description of the EN0 field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the EN0 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG4 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG4 register. * * \return the description of the LINK0 field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the LINK0 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG4 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG4 register. * * \return the description of the FNR0 field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the FNR0 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG4 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN1_LSB, ATON_STRSWITCH_DSTSTRENG4_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_EN1_LSB, ATON_STRSWITCH_DSTSTRENG4_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG4 register. * * \return the description of the EN1 field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the EN1 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG4 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG4_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG4 register. * * \return the description of the LINK1 field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the LINK1 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG4 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG4 register. * * \return the description of the TICKTYPE field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG4 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG4 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG4 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG4_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG4 register. */ #define ATON_STRSWITCH_DSTSTRENG4_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG4_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG4_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG4 register. * * \return the description of the FNR1 field of DSTSTRENG4 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG4_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG4_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * * \return the content of the FNR1 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG4_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG4 register. * * \param[in] reg is the value of the DSTSTRENG4 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG4 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG4_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG4_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG5 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG5 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG5_OFFSET 0x1cUL /** Reset value of the DSTSTRENG5 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG5_DT \ (ATON_STRSWITCH_DSTSTRENG5_EN0_DT << ATON_STRSWITCH_DSTSTRENG5_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG5_LINK0_DT << ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG5_FNR0_DT << ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG5_EN1_DT << ATON_STRSWITCH_DSTSTRENG5_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG5_LINK1_DT << ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG5_FNR1_DT << ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB) /** Description of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_DESC "Connection to input port of Stream Engine 5" /** Address of the DSTSTRENG5 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG5_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG5_OFFSET) /** Get the content of the DSTSTRENG5 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG5_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG5_ADDR(UNIT))) /** Set the content of the DSTSTRENG5 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG5_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG5_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG5 register. * * \return the description of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_DESC; } /** * Get the offset of the DSTSTRENG5 register. * * \return the offset of DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG5_OFFSET; } /** * Get the address of the DSTSTRENG5 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG5 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG5 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG5_ADDR(instance); } /** * Read the content of the DSTSTRENG5 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG5 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG5 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG5_GET(instance); } /** * Write the content of the DSTSTRENG5 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG5 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG5_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG5_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG5 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN0_LSB, ATON_STRSWITCH_DSTSTRENG5_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN0_LSB, ATON_STRSWITCH_DSTSTRENG5_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG5 register. * * \return the description of the EN0 field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the EN0 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG5 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG5 register. * * \return the description of the LINK0 field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the LINK0 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG5 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG5 register. * * \return the description of the FNR0 field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the FNR0 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG5 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN1_LSB, ATON_STRSWITCH_DSTSTRENG5_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_EN1_LSB, ATON_STRSWITCH_DSTSTRENG5_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG5 register. * * \return the description of the EN1 field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the EN1 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG5 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG5_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG5 register. * * \return the description of the LINK1 field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the LINK1 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG5 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG5 register. * * \return the description of the TICKTYPE field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG5 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG5 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG5 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG5_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG5 register. */ #define ATON_STRSWITCH_DSTSTRENG5_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG5_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG5_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG5 register. * * \return the description of the FNR1 field of DSTSTRENG5 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG5_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG5_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * * \return the content of the FNR1 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG5_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG5 register. * * \param[in] reg is the value of the DSTSTRENG5 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG5 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG5_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG5_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG6 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG6 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG6_OFFSET 0x20UL /** Reset value of the DSTSTRENG6 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG6_DT \ (ATON_STRSWITCH_DSTSTRENG6_EN0_DT << ATON_STRSWITCH_DSTSTRENG6_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG6_LINK0_DT << ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG6_FNR0_DT << ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG6_EN1_DT << ATON_STRSWITCH_DSTSTRENG6_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG6_LINK1_DT << ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG6_FNR1_DT << ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB) /** Description of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_DESC "Connection to input port of Stream Engine 6" /** Address of the DSTSTRENG6 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG6_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG6_OFFSET) /** Get the content of the DSTSTRENG6 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG6_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG6_ADDR(UNIT))) /** Set the content of the DSTSTRENG6 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG6_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG6_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG6 register. * * \return the description of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_DESC; } /** * Get the offset of the DSTSTRENG6 register. * * \return the offset of DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG6_OFFSET; } /** * Get the address of the DSTSTRENG6 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG6 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG6 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG6_ADDR(instance); } /** * Read the content of the DSTSTRENG6 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG6 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG6 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG6_GET(instance); } /** * Write the content of the DSTSTRENG6 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG6 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG6_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG6_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG6 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN0_LSB, ATON_STRSWITCH_DSTSTRENG6_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN0_LSB, ATON_STRSWITCH_DSTSTRENG6_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG6 register. * * \return the description of the EN0 field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the EN0 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG6 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG6 register. * * \return the description of the LINK0 field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the LINK0 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG6 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG6 register. * * \return the description of the FNR0 field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the FNR0 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG6 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN1_LSB, ATON_STRSWITCH_DSTSTRENG6_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_EN1_LSB, ATON_STRSWITCH_DSTSTRENG6_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG6 register. * * \return the description of the EN1 field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the EN1 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG6 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG6_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG6 register. * * \return the description of the LINK1 field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the LINK1 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG6 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG6 register. * * \return the description of the TICKTYPE field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG6 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG6 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG6 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG6_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG6 register. */ #define ATON_STRSWITCH_DSTSTRENG6_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG6_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG6_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG6 register. * * \return the description of the FNR1 field of DSTSTRENG6 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG6_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG6_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * * \return the content of the FNR1 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG6_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG6 register. * * \param[in] reg is the value of the DSTSTRENG6 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG6 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG6_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG6_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG7 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG7 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG7_OFFSET 0x24UL /** Reset value of the DSTSTRENG7 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG7_DT \ (ATON_STRSWITCH_DSTSTRENG7_EN0_DT << ATON_STRSWITCH_DSTSTRENG7_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG7_LINK0_DT << ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG7_FNR0_DT << ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG7_EN1_DT << ATON_STRSWITCH_DSTSTRENG7_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG7_LINK1_DT << ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG7_FNR1_DT << ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB) /** Description of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_DESC "Connection to input port of Stream Engine 7" /** Address of the DSTSTRENG7 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG7_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG7_OFFSET) /** Get the content of the DSTSTRENG7 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG7_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG7_ADDR(UNIT))) /** Set the content of the DSTSTRENG7 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG7_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG7_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG7 register. * * \return the description of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_DESC; } /** * Get the offset of the DSTSTRENG7 register. * * \return the offset of DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG7_OFFSET; } /** * Get the address of the DSTSTRENG7 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG7 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG7 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG7_ADDR(instance); } /** * Read the content of the DSTSTRENG7 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG7 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG7 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG7_GET(instance); } /** * Write the content of the DSTSTRENG7 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG7 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG7_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG7_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG7 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN0_LSB, ATON_STRSWITCH_DSTSTRENG7_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN0_LSB, ATON_STRSWITCH_DSTSTRENG7_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG7 register. * * \return the description of the EN0 field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the EN0 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG7 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG7 register. * * \return the description of the LINK0 field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the LINK0 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG7 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG7 register. * * \return the description of the FNR0 field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the FNR0 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG7 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN1_LSB, ATON_STRSWITCH_DSTSTRENG7_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_EN1_LSB, ATON_STRSWITCH_DSTSTRENG7_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG7 register. * * \return the description of the EN1 field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the EN1 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG7 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG7_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG7 register. * * \return the description of the LINK1 field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the LINK1 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG7 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG7 register. * * \return the description of the TICKTYPE field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG7 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG7 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG7 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG7_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG7 register. */ #define ATON_STRSWITCH_DSTSTRENG7_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG7_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG7_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG7 register. * * \return the description of the FNR1 field of DSTSTRENG7 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG7_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG7_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * * \return the content of the FNR1 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG7_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG7 register. * * \param[in] reg is the value of the DSTSTRENG7 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG7 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG7_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG7_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG8 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG8 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG8_OFFSET 0x28UL /** Reset value of the DSTSTRENG8 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG8_DT \ (ATON_STRSWITCH_DSTSTRENG8_EN0_DT << ATON_STRSWITCH_DSTSTRENG8_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG8_LINK0_DT << ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG8_FNR0_DT << ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG8_EN1_DT << ATON_STRSWITCH_DSTSTRENG8_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG8_LINK1_DT << ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG8_FNR1_DT << ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB) /** Description of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_DESC "Connection to input port of Stream Engine 8" /** Address of the DSTSTRENG8 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG8_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG8_OFFSET) /** Get the content of the DSTSTRENG8 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG8_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG8_ADDR(UNIT))) /** Set the content of the DSTSTRENG8 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG8_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG8_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG8 register. * * \return the description of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_DESC; } /** * Get the offset of the DSTSTRENG8 register. * * \return the offset of DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG8_OFFSET; } /** * Get the address of the DSTSTRENG8 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG8 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG8 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG8_ADDR(instance); } /** * Read the content of the DSTSTRENG8 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG8 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG8 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG8_GET(instance); } /** * Write the content of the DSTSTRENG8 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG8 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG8_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG8_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG8 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN0_LSB, ATON_STRSWITCH_DSTSTRENG8_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN0_LSB, ATON_STRSWITCH_DSTSTRENG8_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG8 register. * * \return the description of the EN0 field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the EN0 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG8 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG8 register. * * \return the description of the LINK0 field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the LINK0 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG8 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG8 register. * * \return the description of the FNR0 field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the FNR0 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG8 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN1_LSB, ATON_STRSWITCH_DSTSTRENG8_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_EN1_LSB, ATON_STRSWITCH_DSTSTRENG8_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG8 register. * * \return the description of the EN1 field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the EN1 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG8 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG8_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG8 register. * * \return the description of the LINK1 field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the LINK1 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG8 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG8 register. * * \return the description of the TICKTYPE field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG8 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG8 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG8 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG8_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG8 register. */ #define ATON_STRSWITCH_DSTSTRENG8_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG8_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG8_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG8 register. * * \return the description of the FNR1 field of DSTSTRENG8 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG8_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG8_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * * \return the content of the FNR1 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG8_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG8 register. * * \param[in] reg is the value of the DSTSTRENG8 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG8 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG8_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG8_SET_FNR1(reg, data); } /* *************************************************** DSTSTRENG9 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTSTRENG9 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG9_OFFSET 0x2cUL /** Reset value of the DSTSTRENG9 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTSTRENG9_DT \ (ATON_STRSWITCH_DSTSTRENG9_EN0_DT << ATON_STRSWITCH_DSTSTRENG9_EN0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG9_LINK0_DT << ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG9_FNR0_DT << ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB) | \ (ATON_STRSWITCH_DSTSTRENG9_EN1_DT << ATON_STRSWITCH_DSTSTRENG9_EN1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG9_LINK1_DT << ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB) | \ (ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DT << ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTSTRENG9_FNR1_DT << ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB) /** Description of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_DESC "Connection to input port of Stream Engine 9" /** Address of the DSTSTRENG9 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG9_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTSTRENG9_OFFSET) /** Get the content of the DSTSTRENG9 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG9_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG9_ADDR(UNIT))) /** Set the content of the DSTSTRENG9 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTSTRENG9_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTSTRENG9_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTSTRENG9 register. * * \return the description of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_DESC; } /** * Get the offset of the DSTSTRENG9 register. * * \return the offset of DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_GetOffset(void) { return ATON_STRSWITCH_DSTSTRENG9_OFFSET; } /** * Get the address of the DSTSTRENG9 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG9 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTSTRENG9 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG9_ADDR(instance); } /** * Read the content of the DSTSTRENG9 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG9 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTSTRENG9 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get(uint32_t instance) { return ATON_STRSWITCH_DSTSTRENG9_GET(instance); } /** * Write the content of the DSTSTRENG9 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTSTRENG9 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTSTRENG9_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTSTRENG9_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTSTRENG9 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_S 0 /** Check whether access to the EN0 field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_EN0_P 0 /** Read the content of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN0_LSB, ATON_STRSWITCH_DSTSTRENG9_EN0_W) /** Modify the content of the EN0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN0_LSB, ATON_STRSWITCH_DSTSTRENG9_EN0_W, DATA) /** * Get the description of the EN0 field of DSTSTRENG9 register. * * \return the description of the EN0 field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_EN0_DESC; } /** * Read the content of the EN0 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the EN0 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTSTRENG9 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK0_P 0 /** Read the content of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK0_W) /** Modify the content of the LINK0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK0_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTSTRENG9 register. * * \return the description of the LINK0 field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the LINK0 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTSTRENG9 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR0_P 0 /** Read the content of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR0_W) /** Modify the content of the FNR0 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR0_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTSTRENG9 register. * * \return the description of the FNR0 field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the FNR0 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTSTRENG9 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_S 0 /** Check whether access to the EN1 field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_EN1_P 0 /** Read the content of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN1_LSB, ATON_STRSWITCH_DSTSTRENG9_EN1_W) /** Modify the content of the EN1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_EN1_LSB, ATON_STRSWITCH_DSTSTRENG9_EN1_W, DATA) /** * Get the description of the EN1 field of DSTSTRENG9 register. * * \return the description of the EN1 field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_EN1_DESC; } /** * Read the content of the EN1 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the EN1 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTSTRENG9 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_LINK1_P 0 /** Read the content of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK1_W) /** Modify the content of the LINK1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_LINK1_LSB, ATON_STRSWITCH_DSTSTRENG9_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTSTRENG9 register. * * \return the description of the LINK1 field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the LINK1 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTSTRENG9 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_LSB, ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTSTRENG9 register. * * \return the description of the TICKTYPE field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the TICKTYPE field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTSTRENG9 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTSTRENG9 register is secured or not. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTSTRENG9 register is privileged or not. */ #define ATON_STRSWITCH_DSTSTRENG9_FNR1_P 0 /** Read the content of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR1_W) /** Modify the content of the FNR1 field of the DSTSTRENG9 register. */ #define ATON_STRSWITCH_DSTSTRENG9_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTSTRENG9_FNR1_LSB, ATON_STRSWITCH_DSTSTRENG9_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTSTRENG9 register. * * \return the description of the FNR1 field of DSTSTRENG9 register */ static inline const int8_t *ATON_STRSWITCH_DSTSTRENG9_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTSTRENG9_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * * \return the content of the FNR1 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTSTRENG9_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTSTRENG9 register. * * \param[in] reg is the value of the DSTSTRENG9 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTSTRENG9 register */ static inline uint32_t ATON_STRSWITCH_DSTSTRENG9_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTSTRENG9_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC00 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC00 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC00_OFFSET 0x30UL /** Reset value of the DSTCONVACC00 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC00_DT \ (ATON_STRSWITCH_DSTCONVACC00_EN0_DT << ATON_STRSWITCH_DSTCONVACC00_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC00_LINK0_DT << ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC00_FNR0_DT << ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC00_EN1_DT << ATON_STRSWITCH_DSTCONVACC00_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC00_LINK1_DT << ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC00_FNR1_DT << ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB) /** Description of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_DESC "Connection to input port 0 of Convolutional Accelerator 0" /** Address of the DSTCONVACC00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC00_OFFSET) /** Get the content of the DSTCONVACC00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC00_ADDR(UNIT))) /** Set the content of the DSTCONVACC00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC00_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC00 register. * * \return the description of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_DESC; } /** * Get the offset of the DSTCONVACC00 register. * * \return the offset of DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC00_OFFSET; } /** * Get the address of the DSTCONVACC00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC00 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC00_ADDR(instance); } /** * Read the content of the DSTCONVACC00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC00 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC00_GET(instance); } /** * Write the content of the DSTCONVACC00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC00 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC00_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC00_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC00 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN0_LSB, ATON_STRSWITCH_DSTCONVACC00_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN0_LSB, ATON_STRSWITCH_DSTCONVACC00_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC00 register. * * \return the description of the EN0 field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the EN0 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC00 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC00 register. * * \return the description of the LINK0 field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the LINK0 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC00 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC00 register. * * \return the description of the FNR0 field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the FNR0 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC00 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN1_LSB, ATON_STRSWITCH_DSTCONVACC00_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_EN1_LSB, ATON_STRSWITCH_DSTCONVACC00_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC00 register. * * \return the description of the EN1 field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the EN1 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC00 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC00_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC00 register. * * \return the description of the LINK1 field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the LINK1 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC00 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC00 register. * * \return the description of the TICKTYPE field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC00 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC00 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC00 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC00_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC00 register. */ #define ATON_STRSWITCH_DSTCONVACC00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC00_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC00_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC00 register. * * \return the description of the FNR1 field of DSTCONVACC00 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC00_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC00_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * * \return the content of the FNR1 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC00_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC00 register. * * \param[in] reg is the value of the DSTCONVACC00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC00 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC00_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC00_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC01 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC01 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC01_OFFSET 0x34UL /** Reset value of the DSTCONVACC01 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC01_DT \ (ATON_STRSWITCH_DSTCONVACC01_EN0_DT << ATON_STRSWITCH_DSTCONVACC01_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC01_LINK0_DT << ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC01_FNR0_DT << ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC01_EN1_DT << ATON_STRSWITCH_DSTCONVACC01_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC01_LINK1_DT << ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC01_FNR1_DT << ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB) /** Description of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_DESC "Connection to input port 1 of Convolutional Accelerator 0" /** Address of the DSTCONVACC01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC01_OFFSET) /** Get the content of the DSTCONVACC01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC01_ADDR(UNIT))) /** Set the content of the DSTCONVACC01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC01_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC01 register. * * \return the description of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_DESC; } /** * Get the offset of the DSTCONVACC01 register. * * \return the offset of DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC01_OFFSET; } /** * Get the address of the DSTCONVACC01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC01 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC01_ADDR(instance); } /** * Read the content of the DSTCONVACC01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC01 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC01_GET(instance); } /** * Write the content of the DSTCONVACC01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC01 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC01_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC01_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC01 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN0_LSB, ATON_STRSWITCH_DSTCONVACC01_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN0_LSB, ATON_STRSWITCH_DSTCONVACC01_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC01 register. * * \return the description of the EN0 field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the EN0 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC01 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC01 register. * * \return the description of the LINK0 field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the LINK0 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC01 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC01 register. * * \return the description of the FNR0 field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the FNR0 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC01 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN1_LSB, ATON_STRSWITCH_DSTCONVACC01_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_EN1_LSB, ATON_STRSWITCH_DSTCONVACC01_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC01 register. * * \return the description of the EN1 field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the EN1 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC01 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC01_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC01 register. * * \return the description of the LINK1 field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the LINK1 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC01 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC01 register. * * \return the description of the TICKTYPE field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC01 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC01 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC01 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC01_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC01 register. */ #define ATON_STRSWITCH_DSTCONVACC01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC01_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC01_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC01 register. * * \return the description of the FNR1 field of DSTCONVACC01 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC01_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC01_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * * \return the content of the FNR1 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC01_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC01 register. * * \param[in] reg is the value of the DSTCONVACC01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC01 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC01_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC01_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC02 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC02 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC02_OFFSET 0x38UL /** Reset value of the DSTCONVACC02 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC02_DT \ (ATON_STRSWITCH_DSTCONVACC02_EN0_DT << ATON_STRSWITCH_DSTCONVACC02_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC02_LINK0_DT << ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC02_FNR0_DT << ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC02_EN1_DT << ATON_STRSWITCH_DSTCONVACC02_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC02_LINK1_DT << ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC02_FNR1_DT << ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB) /** Description of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_DESC "Connection to input port 2 of Convolutional Accelerator 0" /** Address of the DSTCONVACC02 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC02_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC02_OFFSET) /** Get the content of the DSTCONVACC02 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC02_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC02_ADDR(UNIT))) /** Set the content of the DSTCONVACC02 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC02_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC02_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC02 register. * * \return the description of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_DESC; } /** * Get the offset of the DSTCONVACC02 register. * * \return the offset of DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC02_OFFSET; } /** * Get the address of the DSTCONVACC02 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC02 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC02 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC02_ADDR(instance); } /** * Read the content of the DSTCONVACC02 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC02 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC02 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC02_GET(instance); } /** * Write the content of the DSTCONVACC02 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC02 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC02_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC02_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC02 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN0_LSB, ATON_STRSWITCH_DSTCONVACC02_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN0_LSB, ATON_STRSWITCH_DSTCONVACC02_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC02 register. * * \return the description of the EN0 field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the EN0 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC02 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC02 register. * * \return the description of the LINK0 field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the LINK0 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC02 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC02 register. * * \return the description of the FNR0 field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the FNR0 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC02 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN1_LSB, ATON_STRSWITCH_DSTCONVACC02_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_EN1_LSB, ATON_STRSWITCH_DSTCONVACC02_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC02 register. * * \return the description of the EN1 field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the EN1 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC02 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC02_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC02 register. * * \return the description of the LINK1 field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the LINK1 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC02 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC02 register. * * \return the description of the TICKTYPE field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC02 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC02 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC02 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC02_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC02 register. */ #define ATON_STRSWITCH_DSTCONVACC02_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC02_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC02_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC02 register. * * \return the description of the FNR1 field of DSTCONVACC02 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC02_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC02_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * * \return the content of the FNR1 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC02_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC02 register. * * \param[in] reg is the value of the DSTCONVACC02 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC02 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC02_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC02_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC10 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC10 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC10_OFFSET 0x3cUL /** Reset value of the DSTCONVACC10 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC10_DT \ (ATON_STRSWITCH_DSTCONVACC10_EN0_DT << ATON_STRSWITCH_DSTCONVACC10_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC10_LINK0_DT << ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC10_FNR0_DT << ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC10_EN1_DT << ATON_STRSWITCH_DSTCONVACC10_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC10_LINK1_DT << ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC10_FNR1_DT << ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB) /** Description of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_DESC "Connection to input port 0 of Convolutional Accelerator 1" /** Address of the DSTCONVACC10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC10_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC10_OFFSET) /** Get the content of the DSTCONVACC10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC10_ADDR(UNIT))) /** Set the content of the DSTCONVACC10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC10_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC10 register. * * \return the description of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_DESC; } /** * Get the offset of the DSTCONVACC10 register. * * \return the offset of DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC10_OFFSET; } /** * Get the address of the DSTCONVACC10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC10 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC10 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC10_ADDR(instance); } /** * Read the content of the DSTCONVACC10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC10 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC10 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC10_GET(instance); } /** * Write the content of the DSTCONVACC10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC10 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC10_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC10_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC10 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN0_LSB, ATON_STRSWITCH_DSTCONVACC10_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN0_LSB, ATON_STRSWITCH_DSTCONVACC10_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC10 register. * * \return the description of the EN0 field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the EN0 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC10 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC10 register. * * \return the description of the LINK0 field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the LINK0 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC10 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC10 register. * * \return the description of the FNR0 field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the FNR0 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC10 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN1_LSB, ATON_STRSWITCH_DSTCONVACC10_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_EN1_LSB, ATON_STRSWITCH_DSTCONVACC10_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC10 register. * * \return the description of the EN1 field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the EN1 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC10 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC10_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC10 register. * * \return the description of the LINK1 field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the LINK1 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC10 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC10 register. * * \return the description of the TICKTYPE field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC10 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC10 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC10 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC10_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC10 register. */ #define ATON_STRSWITCH_DSTCONVACC10_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC10_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC10_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC10 register. * * \return the description of the FNR1 field of DSTCONVACC10 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC10_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC10_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * * \return the content of the FNR1 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC10_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC10 register. * * \param[in] reg is the value of the DSTCONVACC10 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC10 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC10_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC10_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC11 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC11 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC11_OFFSET 0x40UL /** Reset value of the DSTCONVACC11 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC11_DT \ (ATON_STRSWITCH_DSTCONVACC11_EN0_DT << ATON_STRSWITCH_DSTCONVACC11_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC11_LINK0_DT << ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC11_FNR0_DT << ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC11_EN1_DT << ATON_STRSWITCH_DSTCONVACC11_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC11_LINK1_DT << ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC11_FNR1_DT << ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB) /** Description of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_DESC "Connection to input port 1 of Convolutional Accelerator 1" /** Address of the DSTCONVACC11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC11_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC11_OFFSET) /** Get the content of the DSTCONVACC11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC11_ADDR(UNIT))) /** Set the content of the DSTCONVACC11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC11_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC11 register. * * \return the description of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_DESC; } /** * Get the offset of the DSTCONVACC11 register. * * \return the offset of DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC11_OFFSET; } /** * Get the address of the DSTCONVACC11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC11 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC11 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC11_ADDR(instance); } /** * Read the content of the DSTCONVACC11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC11 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC11 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC11_GET(instance); } /** * Write the content of the DSTCONVACC11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC11 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC11_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC11_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC11 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN0_LSB, ATON_STRSWITCH_DSTCONVACC11_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN0_LSB, ATON_STRSWITCH_DSTCONVACC11_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC11 register. * * \return the description of the EN0 field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the EN0 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC11 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC11 register. * * \return the description of the LINK0 field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the LINK0 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC11 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC11 register. * * \return the description of the FNR0 field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the FNR0 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC11 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN1_LSB, ATON_STRSWITCH_DSTCONVACC11_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_EN1_LSB, ATON_STRSWITCH_DSTCONVACC11_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC11 register. * * \return the description of the EN1 field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the EN1 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC11 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC11_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC11 register. * * \return the description of the LINK1 field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the LINK1 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC11 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC11 register. * * \return the description of the TICKTYPE field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC11 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC11 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC11 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC11_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC11 register. */ #define ATON_STRSWITCH_DSTCONVACC11_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC11_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC11_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC11 register. * * \return the description of the FNR1 field of DSTCONVACC11 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC11_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC11_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * * \return the content of the FNR1 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC11_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC11 register. * * \param[in] reg is the value of the DSTCONVACC11 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC11 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC11_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC11_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC12 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC12 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC12_OFFSET 0x44UL /** Reset value of the DSTCONVACC12 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC12_DT \ (ATON_STRSWITCH_DSTCONVACC12_EN0_DT << ATON_STRSWITCH_DSTCONVACC12_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC12_LINK0_DT << ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC12_FNR0_DT << ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC12_EN1_DT << ATON_STRSWITCH_DSTCONVACC12_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC12_LINK1_DT << ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC12_FNR1_DT << ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB) /** Description of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_DESC "Connection to input port 2 of Convolutional Accelerator 1" /** Address of the DSTCONVACC12 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC12_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC12_OFFSET) /** Get the content of the DSTCONVACC12 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC12_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC12_ADDR(UNIT))) /** Set the content of the DSTCONVACC12 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC12_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC12_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC12 register. * * \return the description of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_DESC; } /** * Get the offset of the DSTCONVACC12 register. * * \return the offset of DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC12_OFFSET; } /** * Get the address of the DSTCONVACC12 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC12 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC12 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC12_ADDR(instance); } /** * Read the content of the DSTCONVACC12 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC12 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC12 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC12_GET(instance); } /** * Write the content of the DSTCONVACC12 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC12 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC12_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC12_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC12 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN0_LSB, ATON_STRSWITCH_DSTCONVACC12_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN0_LSB, ATON_STRSWITCH_DSTCONVACC12_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC12 register. * * \return the description of the EN0 field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the EN0 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC12 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC12 register. * * \return the description of the LINK0 field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the LINK0 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC12 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC12 register. * * \return the description of the FNR0 field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the FNR0 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC12 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN1_LSB, ATON_STRSWITCH_DSTCONVACC12_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_EN1_LSB, ATON_STRSWITCH_DSTCONVACC12_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC12 register. * * \return the description of the EN1 field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the EN1 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC12 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC12_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC12 register. * * \return the description of the LINK1 field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the LINK1 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC12 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC12 register. * * \return the description of the TICKTYPE field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC12 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC12 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC12 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC12_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC12 register. */ #define ATON_STRSWITCH_DSTCONVACC12_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC12_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC12_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC12 register. * * \return the description of the FNR1 field of DSTCONVACC12 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC12_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC12_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * * \return the content of the FNR1 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC12_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC12 register. * * \param[in] reg is the value of the DSTCONVACC12 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC12 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC12_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC12_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC20 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC20 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC20_OFFSET 0x48UL /** Reset value of the DSTCONVACC20 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC20_DT \ (ATON_STRSWITCH_DSTCONVACC20_EN0_DT << ATON_STRSWITCH_DSTCONVACC20_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC20_LINK0_DT << ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC20_FNR0_DT << ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC20_EN1_DT << ATON_STRSWITCH_DSTCONVACC20_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC20_LINK1_DT << ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC20_FNR1_DT << ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB) /** Description of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_DESC "Connection to input port 0 of Convolutional Accelerator 2" /** Address of the DSTCONVACC20 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC20_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC20_OFFSET) /** Get the content of the DSTCONVACC20 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC20_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC20_ADDR(UNIT))) /** Set the content of the DSTCONVACC20 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC20_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC20_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC20 register. * * \return the description of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_DESC; } /** * Get the offset of the DSTCONVACC20 register. * * \return the offset of DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC20_OFFSET; } /** * Get the address of the DSTCONVACC20 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC20 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC20 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC20_ADDR(instance); } /** * Read the content of the DSTCONVACC20 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC20 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC20 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC20_GET(instance); } /** * Write the content of the DSTCONVACC20 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC20 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC20_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC20_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC20 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN0_LSB, ATON_STRSWITCH_DSTCONVACC20_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN0_LSB, ATON_STRSWITCH_DSTCONVACC20_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC20 register. * * \return the description of the EN0 field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the EN0 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC20 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC20 register. * * \return the description of the LINK0 field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the LINK0 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC20 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC20 register. * * \return the description of the FNR0 field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the FNR0 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC20 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN1_LSB, ATON_STRSWITCH_DSTCONVACC20_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_EN1_LSB, ATON_STRSWITCH_DSTCONVACC20_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC20 register. * * \return the description of the EN1 field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the EN1 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC20 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC20_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC20 register. * * \return the description of the LINK1 field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the LINK1 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC20 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC20 register. * * \return the description of the TICKTYPE field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC20 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC20 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC20 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC20_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC20 register. */ #define ATON_STRSWITCH_DSTCONVACC20_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC20_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC20_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC20 register. * * \return the description of the FNR1 field of DSTCONVACC20 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC20_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC20_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * * \return the content of the FNR1 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC20_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC20 register. * * \param[in] reg is the value of the DSTCONVACC20 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC20 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC20_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC20_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC21 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC21 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC21_OFFSET 0x4cUL /** Reset value of the DSTCONVACC21 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC21_DT \ (ATON_STRSWITCH_DSTCONVACC21_EN0_DT << ATON_STRSWITCH_DSTCONVACC21_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC21_LINK0_DT << ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC21_FNR0_DT << ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC21_EN1_DT << ATON_STRSWITCH_DSTCONVACC21_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC21_LINK1_DT << ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC21_FNR1_DT << ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB) /** Description of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_DESC "Connection to input port 1 of Convolutional Accelerator 2" /** Address of the DSTCONVACC21 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC21_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC21_OFFSET) /** Get the content of the DSTCONVACC21 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC21_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC21_ADDR(UNIT))) /** Set the content of the DSTCONVACC21 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC21_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC21_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC21 register. * * \return the description of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_DESC; } /** * Get the offset of the DSTCONVACC21 register. * * \return the offset of DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC21_OFFSET; } /** * Get the address of the DSTCONVACC21 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC21 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC21 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC21_ADDR(instance); } /** * Read the content of the DSTCONVACC21 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC21 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC21 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC21_GET(instance); } /** * Write the content of the DSTCONVACC21 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC21 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC21_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC21_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC21 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN0_LSB, ATON_STRSWITCH_DSTCONVACC21_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN0_LSB, ATON_STRSWITCH_DSTCONVACC21_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC21 register. * * \return the description of the EN0 field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the EN0 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC21 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC21 register. * * \return the description of the LINK0 field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the LINK0 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC21 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC21 register. * * \return the description of the FNR0 field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the FNR0 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC21 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN1_LSB, ATON_STRSWITCH_DSTCONVACC21_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_EN1_LSB, ATON_STRSWITCH_DSTCONVACC21_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC21 register. * * \return the description of the EN1 field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the EN1 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC21 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC21_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC21 register. * * \return the description of the LINK1 field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the LINK1 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC21 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC21 register. * * \return the description of the TICKTYPE field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC21 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC21 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC21 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC21_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC21 register. */ #define ATON_STRSWITCH_DSTCONVACC21_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC21_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC21_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC21 register. * * \return the description of the FNR1 field of DSTCONVACC21 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC21_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC21_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * * \return the content of the FNR1 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC21_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC21 register. * * \param[in] reg is the value of the DSTCONVACC21 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC21 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC21_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC21_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC22 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC22 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC22_OFFSET 0x50UL /** Reset value of the DSTCONVACC22 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC22_DT \ (ATON_STRSWITCH_DSTCONVACC22_EN0_DT << ATON_STRSWITCH_DSTCONVACC22_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC22_LINK0_DT << ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC22_FNR0_DT << ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC22_EN1_DT << ATON_STRSWITCH_DSTCONVACC22_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC22_LINK1_DT << ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC22_FNR1_DT << ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB) /** Description of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_DESC "Connection to input port 2 of Convolutional Accelerator 2" /** Address of the DSTCONVACC22 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC22_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC22_OFFSET) /** Get the content of the DSTCONVACC22 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC22_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC22_ADDR(UNIT))) /** Set the content of the DSTCONVACC22 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC22_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC22_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC22 register. * * \return the description of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_DESC; } /** * Get the offset of the DSTCONVACC22 register. * * \return the offset of DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC22_OFFSET; } /** * Get the address of the DSTCONVACC22 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC22 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC22 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC22_ADDR(instance); } /** * Read the content of the DSTCONVACC22 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC22 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC22 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC22_GET(instance); } /** * Write the content of the DSTCONVACC22 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC22 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC22_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC22_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC22 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN0_LSB, ATON_STRSWITCH_DSTCONVACC22_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN0_LSB, ATON_STRSWITCH_DSTCONVACC22_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC22 register. * * \return the description of the EN0 field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the EN0 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC22 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC22 register. * * \return the description of the LINK0 field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the LINK0 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC22 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC22 register. * * \return the description of the FNR0 field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the FNR0 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC22 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN1_LSB, ATON_STRSWITCH_DSTCONVACC22_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_EN1_LSB, ATON_STRSWITCH_DSTCONVACC22_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC22 register. * * \return the description of the EN1 field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the EN1 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC22 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC22_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC22 register. * * \return the description of the LINK1 field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the LINK1 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC22 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC22 register. * * \return the description of the TICKTYPE field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC22 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC22 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC22 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC22_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC22 register. */ #define ATON_STRSWITCH_DSTCONVACC22_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC22_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC22_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC22 register. * * \return the description of the FNR1 field of DSTCONVACC22 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC22_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC22_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * * \return the content of the FNR1 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC22_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC22 register. * * \param[in] reg is the value of the DSTCONVACC22 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC22 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC22_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC22_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC30 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC30 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC30_OFFSET 0x54UL /** Reset value of the DSTCONVACC30 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC30_DT \ (ATON_STRSWITCH_DSTCONVACC30_EN0_DT << ATON_STRSWITCH_DSTCONVACC30_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC30_LINK0_DT << ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC30_FNR0_DT << ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC30_EN1_DT << ATON_STRSWITCH_DSTCONVACC30_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC30_LINK1_DT << ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC30_FNR1_DT << ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB) /** Description of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_DESC "Connection to input port 0 of Convolutional Accelerator 3" /** Address of the DSTCONVACC30 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC30_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC30_OFFSET) /** Get the content of the DSTCONVACC30 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC30_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC30_ADDR(UNIT))) /** Set the content of the DSTCONVACC30 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC30_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC30_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC30 register. * * \return the description of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_DESC; } /** * Get the offset of the DSTCONVACC30 register. * * \return the offset of DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC30_OFFSET; } /** * Get the address of the DSTCONVACC30 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC30 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC30 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC30_ADDR(instance); } /** * Read the content of the DSTCONVACC30 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC30 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC30 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC30_GET(instance); } /** * Write the content of the DSTCONVACC30 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC30 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC30_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC30_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC30 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN0_LSB, ATON_STRSWITCH_DSTCONVACC30_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN0_LSB, ATON_STRSWITCH_DSTCONVACC30_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC30 register. * * \return the description of the EN0 field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the EN0 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC30 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC30 register. * * \return the description of the LINK0 field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the LINK0 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC30 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC30 register. * * \return the description of the FNR0 field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the FNR0 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC30 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN1_LSB, ATON_STRSWITCH_DSTCONVACC30_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_EN1_LSB, ATON_STRSWITCH_DSTCONVACC30_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC30 register. * * \return the description of the EN1 field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the EN1 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC30 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC30_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC30 register. * * \return the description of the LINK1 field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the LINK1 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC30 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC30 register. * * \return the description of the TICKTYPE field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC30 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC30 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC30 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC30_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC30 register. */ #define ATON_STRSWITCH_DSTCONVACC30_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC30_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC30_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC30 register. * * \return the description of the FNR1 field of DSTCONVACC30 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC30_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC30_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * * \return the content of the FNR1 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC30_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC30 register. * * \param[in] reg is the value of the DSTCONVACC30 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC30 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC30_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC30_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC31 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC31 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC31_OFFSET 0x58UL /** Reset value of the DSTCONVACC31 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC31_DT \ (ATON_STRSWITCH_DSTCONVACC31_EN0_DT << ATON_STRSWITCH_DSTCONVACC31_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC31_LINK0_DT << ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC31_FNR0_DT << ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC31_EN1_DT << ATON_STRSWITCH_DSTCONVACC31_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC31_LINK1_DT << ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC31_FNR1_DT << ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB) /** Description of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_DESC "Connection to input port 1 of Convolutional Accelerator 3" /** Address of the DSTCONVACC31 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC31_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC31_OFFSET) /** Get the content of the DSTCONVACC31 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC31_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC31_ADDR(UNIT))) /** Set the content of the DSTCONVACC31 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC31_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC31_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC31 register. * * \return the description of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_DESC; } /** * Get the offset of the DSTCONVACC31 register. * * \return the offset of DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC31_OFFSET; } /** * Get the address of the DSTCONVACC31 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC31 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC31 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC31_ADDR(instance); } /** * Read the content of the DSTCONVACC31 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC31 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC31 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC31_GET(instance); } /** * Write the content of the DSTCONVACC31 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC31 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC31_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC31_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC31 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN0_LSB, ATON_STRSWITCH_DSTCONVACC31_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN0_LSB, ATON_STRSWITCH_DSTCONVACC31_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC31 register. * * \return the description of the EN0 field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the EN0 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC31 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC31 register. * * \return the description of the LINK0 field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the LINK0 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC31 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC31 register. * * \return the description of the FNR0 field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the FNR0 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC31 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN1_LSB, ATON_STRSWITCH_DSTCONVACC31_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_EN1_LSB, ATON_STRSWITCH_DSTCONVACC31_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC31 register. * * \return the description of the EN1 field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the EN1 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC31 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC31_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC31 register. * * \return the description of the LINK1 field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the LINK1 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC31 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC31 register. * * \return the description of the TICKTYPE field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC31 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC31 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC31 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC31_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC31 register. */ #define ATON_STRSWITCH_DSTCONVACC31_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC31_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC31_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC31 register. * * \return the description of the FNR1 field of DSTCONVACC31 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC31_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC31_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * * \return the content of the FNR1 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC31_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC31 register. * * \param[in] reg is the value of the DSTCONVACC31 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC31 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC31_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC31_SET_FNR1(reg, data); } /* ************************************************** DSTCONVACC32 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTCONVACC32 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC32_OFFSET 0x5cUL /** Reset value of the DSTCONVACC32 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTCONVACC32_DT \ (ATON_STRSWITCH_DSTCONVACC32_EN0_DT << ATON_STRSWITCH_DSTCONVACC32_EN0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC32_LINK0_DT << ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC32_FNR0_DT << ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB) | \ (ATON_STRSWITCH_DSTCONVACC32_EN1_DT << ATON_STRSWITCH_DSTCONVACC32_EN1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC32_LINK1_DT << ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB) | \ (ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DT << ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTCONVACC32_FNR1_DT << ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB) /** Description of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_DESC "Connection to input port 2 of Convolutional Accelerator 3" /** Address of the DSTCONVACC32 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC32_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTCONVACC32_OFFSET) /** Get the content of the DSTCONVACC32 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC32_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC32_ADDR(UNIT))) /** Set the content of the DSTCONVACC32 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTCONVACC32_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTCONVACC32_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTCONVACC32 register. * * \return the description of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_DESC; } /** * Get the offset of the DSTCONVACC32 register. * * \return the offset of DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_GetOffset(void) { return ATON_STRSWITCH_DSTCONVACC32_OFFSET; } /** * Get the address of the DSTCONVACC32 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC32 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTCONVACC32 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC32_ADDR(instance); } /** * Read the content of the DSTCONVACC32 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC32 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTCONVACC32 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get(uint32_t instance) { return ATON_STRSWITCH_DSTCONVACC32_GET(instance); } /** * Write the content of the DSTCONVACC32 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTCONVACC32 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTCONVACC32_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTCONVACC32_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTCONVACC32 register --------------------------------------------------------- */ /** Description of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_S 0 /** Check whether access to the EN0 field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_EN0_P 0 /** Read the content of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN0_LSB, ATON_STRSWITCH_DSTCONVACC32_EN0_W) /** Modify the content of the EN0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN0_LSB, ATON_STRSWITCH_DSTCONVACC32_EN0_W, DATA) /** * Get the description of the EN0 field of DSTCONVACC32 register. * * \return the description of the EN0 field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_EN0_DESC; } /** * Read the content of the EN0 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the EN0 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTCONVACC32 register -------------------------------------------------------- */ /** Description of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK0_P 0 /** Read the content of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK0_W) /** Modify the content of the LINK0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK0_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTCONVACC32 register. * * \return the description of the LINK0 field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the LINK0 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_LINK0(reg, data); } /* -------------------------------------------------------- FNR0 field of the DSTCONVACC32 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR0_P 0 /** Read the content of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR0_W) /** Modify the content of the FNR0 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR0_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTCONVACC32 register. * * \return the description of the FNR0 field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the FNR0 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTCONVACC32 register --------------------------------------------------------- */ /** Description of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_S 0 /** Check whether access to the EN1 field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_EN1_P 0 /** Read the content of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN1_LSB, ATON_STRSWITCH_DSTCONVACC32_EN1_W) /** Modify the content of the EN1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_EN1_LSB, ATON_STRSWITCH_DSTCONVACC32_EN1_W, DATA) /** * Get the description of the EN1 field of DSTCONVACC32 register. * * \return the description of the EN1 field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_EN1_DESC; } /** * Read the content of the EN1 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the EN1 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTCONVACC32 register -------------------------------------------------------- */ /** Description of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_LINK1_P 0 /** Read the content of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK1_W) /** Modify the content of the LINK1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_LINK1_LSB, ATON_STRSWITCH_DSTCONVACC32_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTCONVACC32 register. * * \return the description of the LINK1 field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the LINK1 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_LINK1(reg, data); } /* ------------------------------------------------------ TICKTYPE field of the DSTCONVACC32 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_LSB, ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTCONVACC32 register. * * \return the description of the TICKTYPE field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the TICKTYPE field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_TICKTYPE(reg, data); } /* -------------------------------------------------------- FNR1 field of the DSTCONVACC32 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTCONVACC32 register is secured or not. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTCONVACC32 register is privileged or not. */ #define ATON_STRSWITCH_DSTCONVACC32_FNR1_P 0 /** Read the content of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR1_W) /** Modify the content of the FNR1 field of the DSTCONVACC32 register. */ #define ATON_STRSWITCH_DSTCONVACC32_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTCONVACC32_FNR1_LSB, ATON_STRSWITCH_DSTCONVACC32_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTCONVACC32 register. * * \return the description of the FNR1 field of DSTCONVACC32 register */ static inline const int8_t *ATON_STRSWITCH_DSTCONVACC32_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTCONVACC32_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * * \return the content of the FNR1 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTCONVACC32_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTCONVACC32 register. * * \param[in] reg is the value of the DSTCONVACC32 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTCONVACC32 register */ static inline uint32_t ATON_STRSWITCH_DSTCONVACC32_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTCONVACC32_SET_FNR1(reg, data); } /* *************************************************** DSTDECUN00 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTDECUN00 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN00_OFFSET 0x60UL /** Reset value of the DSTDECUN00 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN00_DT \ (ATON_STRSWITCH_DSTDECUN00_EN0_DT << ATON_STRSWITCH_DSTDECUN00_EN0_LSB) | \ (ATON_STRSWITCH_DSTDECUN00_LINK0_DT << ATON_STRSWITCH_DSTDECUN00_LINK0_LSB) | \ (ATON_STRSWITCH_DSTDECUN00_FNR0_DT << ATON_STRSWITCH_DSTDECUN00_FNR0_LSB) | \ (ATON_STRSWITCH_DSTDECUN00_EN1_DT << ATON_STRSWITCH_DSTDECUN00_EN1_LSB) | \ (ATON_STRSWITCH_DSTDECUN00_LINK1_DT << ATON_STRSWITCH_DSTDECUN00_LINK1_LSB) | \ (ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTDECUN00_FNR1_DT << ATON_STRSWITCH_DSTDECUN00_FNR1_LSB) /** Description of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_DESC "Connection to input port 0 of Decompression Unit 0" /** Address of the DSTDECUN00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN00_OFFSET) /** Get the content of the DSTDECUN00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN00_ADDR(UNIT))) /** Set the content of the DSTDECUN00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN00_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTDECUN00 register. * * \return the description of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_DESC; } /** * Get the offset of the DSTDECUN00 register. * * \return the offset of DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_GetOffset(void) { return ATON_STRSWITCH_DSTDECUN00_OFFSET; } /** * Get the address of the DSTDECUN00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN00 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTDECUN00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN00_ADDR(instance); } /** * Read the content of the DSTDECUN00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN00 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTDECUN00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN00_GET(instance); } /** * Write the content of the DSTDECUN00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN00 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTDECUN00_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTDECUN00_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTDECUN00 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_S 0 /** Check whether access to the EN0 field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_EN0_P 0 /** Read the content of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN0_LSB, ATON_STRSWITCH_DSTDECUN00_EN0_W) /** Modify the content of the EN0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN0_LSB, ATON_STRSWITCH_DSTDECUN00_EN0_W, DATA) /** * Get the description of the EN0 field of DSTDECUN00 register. * * \return the description of the EN0 field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_EN0_DESC; } /** * Read the content of the EN0 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the EN0 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTDECUN00 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_LINK0_P 0 /** Read the content of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK0_LSB, ATON_STRSWITCH_DSTDECUN00_LINK0_W) /** Modify the content of the LINK0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK0_LSB, ATON_STRSWITCH_DSTDECUN00_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTDECUN00 register. * * \return the description of the LINK0 field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the LINK0 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTDECUN00 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_FNR0_P 0 /** Read the content of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR0_LSB, ATON_STRSWITCH_DSTDECUN00_FNR0_W) /** Modify the content of the FNR0 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR0_LSB, ATON_STRSWITCH_DSTDECUN00_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTDECUN00 register. * * \return the description of the FNR0 field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the FNR0 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTDECUN00 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_S 0 /** Check whether access to the EN1 field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_EN1_P 0 /** Read the content of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN1_LSB, ATON_STRSWITCH_DSTDECUN00_EN1_W) /** Modify the content of the EN1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_EN1_LSB, ATON_STRSWITCH_DSTDECUN00_EN1_W, DATA) /** * Get the description of the EN1 field of DSTDECUN00 register. * * \return the description of the EN1 field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_EN1_DESC; } /** * Read the content of the EN1 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the EN1 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTDECUN00 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_LINK1_P 0 /** Read the content of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK1_LSB, ATON_STRSWITCH_DSTDECUN00_LINK1_W) /** Modify the content of the LINK1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_LINK1_LSB, ATON_STRSWITCH_DSTDECUN00_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTDECUN00 register. * * \return the description of the LINK1 field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the LINK1 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTDECUN00 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN00_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTDECUN00 register. * * \return the description of the TICKTYPE field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the TICKTYPE field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTDECUN00 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTDECUN00 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTDECUN00 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN00_FNR1_P 0 /** Read the content of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR1_LSB, ATON_STRSWITCH_DSTDECUN00_FNR1_W) /** Modify the content of the FNR1 field of the DSTDECUN00 register. */ #define ATON_STRSWITCH_DSTDECUN00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN00_FNR1_LSB, ATON_STRSWITCH_DSTDECUN00_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTDECUN00 register. * * \return the description of the FNR1 field of DSTDECUN00 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN00_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN00_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * * \return the content of the FNR1 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN00_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTDECUN00 register. * * \param[in] reg is the value of the DSTDECUN00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTDECUN00 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN00_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN00_SET_FNR1(reg, data); } /* *************************************************** DSTDECUN01 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTDECUN01 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN01_OFFSET 0x64UL /** Reset value of the DSTDECUN01 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN01_DT \ (ATON_STRSWITCH_DSTDECUN01_EN0_DT << ATON_STRSWITCH_DSTDECUN01_EN0_LSB) | \ (ATON_STRSWITCH_DSTDECUN01_LINK0_DT << ATON_STRSWITCH_DSTDECUN01_LINK0_LSB) | \ (ATON_STRSWITCH_DSTDECUN01_FNR0_DT << ATON_STRSWITCH_DSTDECUN01_FNR0_LSB) | \ (ATON_STRSWITCH_DSTDECUN01_EN1_DT << ATON_STRSWITCH_DSTDECUN01_EN1_LSB) | \ (ATON_STRSWITCH_DSTDECUN01_LINK1_DT << ATON_STRSWITCH_DSTDECUN01_LINK1_LSB) | \ (ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTDECUN01_FNR1_DT << ATON_STRSWITCH_DSTDECUN01_FNR1_LSB) /** Description of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_DESC "Connection to input port 1 of Decompression Unit 0" /** Address of the DSTDECUN01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN01_OFFSET) /** Get the content of the DSTDECUN01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN01_ADDR(UNIT))) /** Set the content of the DSTDECUN01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN01_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTDECUN01 register. * * \return the description of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_DESC; } /** * Get the offset of the DSTDECUN01 register. * * \return the offset of DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_GetOffset(void) { return ATON_STRSWITCH_DSTDECUN01_OFFSET; } /** * Get the address of the DSTDECUN01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN01 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTDECUN01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN01_ADDR(instance); } /** * Read the content of the DSTDECUN01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN01 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTDECUN01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN01_GET(instance); } /** * Write the content of the DSTDECUN01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN01 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTDECUN01_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTDECUN01_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTDECUN01 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_S 0 /** Check whether access to the EN0 field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_EN0_P 0 /** Read the content of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN0_LSB, ATON_STRSWITCH_DSTDECUN01_EN0_W) /** Modify the content of the EN0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN0_LSB, ATON_STRSWITCH_DSTDECUN01_EN0_W, DATA) /** * Get the description of the EN0 field of DSTDECUN01 register. * * \return the description of the EN0 field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_EN0_DESC; } /** * Read the content of the EN0 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the EN0 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTDECUN01 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_LINK0_P 0 /** Read the content of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK0_LSB, ATON_STRSWITCH_DSTDECUN01_LINK0_W) /** Modify the content of the LINK0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK0_LSB, ATON_STRSWITCH_DSTDECUN01_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTDECUN01 register. * * \return the description of the LINK0 field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the LINK0 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTDECUN01 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_FNR0_P 0 /** Read the content of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR0_LSB, ATON_STRSWITCH_DSTDECUN01_FNR0_W) /** Modify the content of the FNR0 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR0_LSB, ATON_STRSWITCH_DSTDECUN01_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTDECUN01 register. * * \return the description of the FNR0 field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the FNR0 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTDECUN01 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_S 0 /** Check whether access to the EN1 field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_EN1_P 0 /** Read the content of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN1_LSB, ATON_STRSWITCH_DSTDECUN01_EN1_W) /** Modify the content of the EN1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_EN1_LSB, ATON_STRSWITCH_DSTDECUN01_EN1_W, DATA) /** * Get the description of the EN1 field of DSTDECUN01 register. * * \return the description of the EN1 field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_EN1_DESC; } /** * Read the content of the EN1 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the EN1 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTDECUN01 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_LINK1_P 0 /** Read the content of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK1_LSB, ATON_STRSWITCH_DSTDECUN01_LINK1_W) /** Modify the content of the LINK1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_LINK1_LSB, ATON_STRSWITCH_DSTDECUN01_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTDECUN01 register. * * \return the description of the LINK1 field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the LINK1 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTDECUN01 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN01_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTDECUN01 register. * * \return the description of the TICKTYPE field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the TICKTYPE field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTDECUN01 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTDECUN01 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTDECUN01 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN01_FNR1_P 0 /** Read the content of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR1_LSB, ATON_STRSWITCH_DSTDECUN01_FNR1_W) /** Modify the content of the FNR1 field of the DSTDECUN01 register. */ #define ATON_STRSWITCH_DSTDECUN01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN01_FNR1_LSB, ATON_STRSWITCH_DSTDECUN01_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTDECUN01 register. * * \return the description of the FNR1 field of DSTDECUN01 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN01_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN01_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * * \return the content of the FNR1 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN01_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTDECUN01 register. * * \param[in] reg is the value of the DSTDECUN01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTDECUN01 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN01_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN01_SET_FNR1(reg, data); } /* *************************************************** DSTDECUN10 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTDECUN10 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN10_OFFSET 0x68UL /** Reset value of the DSTDECUN10 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN10_DT \ (ATON_STRSWITCH_DSTDECUN10_EN0_DT << ATON_STRSWITCH_DSTDECUN10_EN0_LSB) | \ (ATON_STRSWITCH_DSTDECUN10_LINK0_DT << ATON_STRSWITCH_DSTDECUN10_LINK0_LSB) | \ (ATON_STRSWITCH_DSTDECUN10_FNR0_DT << ATON_STRSWITCH_DSTDECUN10_FNR0_LSB) | \ (ATON_STRSWITCH_DSTDECUN10_EN1_DT << ATON_STRSWITCH_DSTDECUN10_EN1_LSB) | \ (ATON_STRSWITCH_DSTDECUN10_LINK1_DT << ATON_STRSWITCH_DSTDECUN10_LINK1_LSB) | \ (ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTDECUN10_FNR1_DT << ATON_STRSWITCH_DSTDECUN10_FNR1_LSB) /** Description of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_DESC "Connection to input port 0 of Decompression Unit 1" /** Address of the DSTDECUN10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN10_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN10_OFFSET) /** Get the content of the DSTDECUN10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN10_ADDR(UNIT))) /** Set the content of the DSTDECUN10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN10_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTDECUN10 register. * * \return the description of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_DESC; } /** * Get the offset of the DSTDECUN10 register. * * \return the offset of DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_GetOffset(void) { return ATON_STRSWITCH_DSTDECUN10_OFFSET; } /** * Get the address of the DSTDECUN10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN10 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTDECUN10 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN10_ADDR(instance); } /** * Read the content of the DSTDECUN10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN10 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTDECUN10 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN10_GET(instance); } /** * Write the content of the DSTDECUN10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN10 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTDECUN10_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTDECUN10_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTDECUN10 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_S 0 /** Check whether access to the EN0 field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_EN0_P 0 /** Read the content of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN0_LSB, ATON_STRSWITCH_DSTDECUN10_EN0_W) /** Modify the content of the EN0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN0_LSB, ATON_STRSWITCH_DSTDECUN10_EN0_W, DATA) /** * Get the description of the EN0 field of DSTDECUN10 register. * * \return the description of the EN0 field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_EN0_DESC; } /** * Read the content of the EN0 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the EN0 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTDECUN10 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_LINK0_P 0 /** Read the content of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK0_LSB, ATON_STRSWITCH_DSTDECUN10_LINK0_W) /** Modify the content of the LINK0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK0_LSB, ATON_STRSWITCH_DSTDECUN10_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTDECUN10 register. * * \return the description of the LINK0 field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the LINK0 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTDECUN10 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_FNR0_P 0 /** Read the content of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR0_LSB, ATON_STRSWITCH_DSTDECUN10_FNR0_W) /** Modify the content of the FNR0 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR0_LSB, ATON_STRSWITCH_DSTDECUN10_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTDECUN10 register. * * \return the description of the FNR0 field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the FNR0 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTDECUN10 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_S 0 /** Check whether access to the EN1 field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_EN1_P 0 /** Read the content of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN1_LSB, ATON_STRSWITCH_DSTDECUN10_EN1_W) /** Modify the content of the EN1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_EN1_LSB, ATON_STRSWITCH_DSTDECUN10_EN1_W, DATA) /** * Get the description of the EN1 field of DSTDECUN10 register. * * \return the description of the EN1 field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_EN1_DESC; } /** * Read the content of the EN1 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the EN1 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTDECUN10 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_LINK1_P 0 /** Read the content of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK1_LSB, ATON_STRSWITCH_DSTDECUN10_LINK1_W) /** Modify the content of the LINK1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_LINK1_LSB, ATON_STRSWITCH_DSTDECUN10_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTDECUN10 register. * * \return the description of the LINK1 field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the LINK1 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTDECUN10 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN10_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTDECUN10 register. * * \return the description of the TICKTYPE field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the TICKTYPE field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTDECUN10 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTDECUN10 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTDECUN10 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN10_FNR1_P 0 /** Read the content of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR1_LSB, ATON_STRSWITCH_DSTDECUN10_FNR1_W) /** Modify the content of the FNR1 field of the DSTDECUN10 register. */ #define ATON_STRSWITCH_DSTDECUN10_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN10_FNR1_LSB, ATON_STRSWITCH_DSTDECUN10_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTDECUN10 register. * * \return the description of the FNR1 field of DSTDECUN10 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN10_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN10_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * * \return the content of the FNR1 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN10_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTDECUN10 register. * * \param[in] reg is the value of the DSTDECUN10 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTDECUN10 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN10_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN10_SET_FNR1(reg, data); } /* *************************************************** DSTDECUN11 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTDECUN11 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN11_OFFSET 0x6cUL /** Reset value of the DSTDECUN11 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTDECUN11_DT \ (ATON_STRSWITCH_DSTDECUN11_EN0_DT << ATON_STRSWITCH_DSTDECUN11_EN0_LSB) | \ (ATON_STRSWITCH_DSTDECUN11_LINK0_DT << ATON_STRSWITCH_DSTDECUN11_LINK0_LSB) | \ (ATON_STRSWITCH_DSTDECUN11_FNR0_DT << ATON_STRSWITCH_DSTDECUN11_FNR0_LSB) | \ (ATON_STRSWITCH_DSTDECUN11_EN1_DT << ATON_STRSWITCH_DSTDECUN11_EN1_LSB) | \ (ATON_STRSWITCH_DSTDECUN11_LINK1_DT << ATON_STRSWITCH_DSTDECUN11_LINK1_LSB) | \ (ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DT << ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTDECUN11_FNR1_DT << ATON_STRSWITCH_DSTDECUN11_FNR1_LSB) /** Description of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_DESC "Connection to input port 1 of Decompression Unit 1" /** Address of the DSTDECUN11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN11_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTDECUN11_OFFSET) /** Get the content of the DSTDECUN11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN11_ADDR(UNIT))) /** Set the content of the DSTDECUN11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTDECUN11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTDECUN11_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTDECUN11 register. * * \return the description of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_DESC; } /** * Get the offset of the DSTDECUN11 register. * * \return the offset of DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_GetOffset(void) { return ATON_STRSWITCH_DSTDECUN11_OFFSET; } /** * Get the address of the DSTDECUN11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN11 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTDECUN11 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN11_ADDR(instance); } /** * Read the content of the DSTDECUN11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN11 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTDECUN11 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get(uint32_t instance) { return ATON_STRSWITCH_DSTDECUN11_GET(instance); } /** * Write the content of the DSTDECUN11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTDECUN11 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTDECUN11_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTDECUN11_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTDECUN11 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_S 0 /** Check whether access to the EN0 field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_EN0_P 0 /** Read the content of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN0_LSB, ATON_STRSWITCH_DSTDECUN11_EN0_W) /** Modify the content of the EN0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN0_LSB, ATON_STRSWITCH_DSTDECUN11_EN0_W, DATA) /** * Get the description of the EN0 field of DSTDECUN11 register. * * \return the description of the EN0 field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_EN0_DESC; } /** * Read the content of the EN0 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the EN0 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTDECUN11 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_LINK0_P 0 /** Read the content of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK0_LSB, ATON_STRSWITCH_DSTDECUN11_LINK0_W) /** Modify the content of the LINK0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK0_LSB, ATON_STRSWITCH_DSTDECUN11_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTDECUN11 register. * * \return the description of the LINK0 field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the LINK0 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTDECUN11 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_FNR0_P 0 /** Read the content of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR0_LSB, ATON_STRSWITCH_DSTDECUN11_FNR0_W) /** Modify the content of the FNR0 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR0_LSB, ATON_STRSWITCH_DSTDECUN11_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTDECUN11 register. * * \return the description of the FNR0 field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the FNR0 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTDECUN11 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_S 0 /** Check whether access to the EN1 field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_EN1_P 0 /** Read the content of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN1_LSB, ATON_STRSWITCH_DSTDECUN11_EN1_W) /** Modify the content of the EN1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_EN1_LSB, ATON_STRSWITCH_DSTDECUN11_EN1_W, DATA) /** * Get the description of the EN1 field of DSTDECUN11 register. * * \return the description of the EN1 field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_EN1_DESC; } /** * Read the content of the EN1 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the EN1 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTDECUN11 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_LINK1_P 0 /** Read the content of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK1_LSB, ATON_STRSWITCH_DSTDECUN11_LINK1_W) /** Modify the content of the LINK1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_LINK1_LSB, ATON_STRSWITCH_DSTDECUN11_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTDECUN11 register. * * \return the description of the LINK1 field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the LINK1 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTDECUN11 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_LSB, ATON_STRSWITCH_DSTDECUN11_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTDECUN11 register. * * \return the description of the TICKTYPE field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the TICKTYPE field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTDECUN11 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTDECUN11 register is secured or not. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTDECUN11 register is privileged or not. */ #define ATON_STRSWITCH_DSTDECUN11_FNR1_P 0 /** Read the content of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR1_LSB, ATON_STRSWITCH_DSTDECUN11_FNR1_W) /** Modify the content of the FNR1 field of the DSTDECUN11 register. */ #define ATON_STRSWITCH_DSTDECUN11_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTDECUN11_FNR1_LSB, ATON_STRSWITCH_DSTDECUN11_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTDECUN11 register. * * \return the description of the FNR1 field of DSTDECUN11 register */ static inline const int8_t *ATON_STRSWITCH_DSTDECUN11_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTDECUN11_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * * \return the content of the FNR1 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTDECUN11_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTDECUN11 register. * * \param[in] reg is the value of the DSTDECUN11 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTDECUN11 register */ static inline uint32_t ATON_STRSWITCH_DSTDECUN11_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTDECUN11_SET_FNR1(reg, data); } /* **************************************************** DSTACTIV0 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTACTIV0 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTACTIV0_OFFSET 0x70UL /** Reset value of the DSTACTIV0 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTACTIV0_DT \ (ATON_STRSWITCH_DSTACTIV0_EN0_DT << ATON_STRSWITCH_DSTACTIV0_EN0_LSB) | \ (ATON_STRSWITCH_DSTACTIV0_LINK0_DT << ATON_STRSWITCH_DSTACTIV0_LINK0_LSB) | \ (ATON_STRSWITCH_DSTACTIV0_FNR0_DT << ATON_STRSWITCH_DSTACTIV0_FNR0_LSB) | \ (ATON_STRSWITCH_DSTACTIV0_EN1_DT << ATON_STRSWITCH_DSTACTIV0_EN1_LSB) | \ (ATON_STRSWITCH_DSTACTIV0_LINK1_DT << ATON_STRSWITCH_DSTACTIV0_LINK1_LSB) | \ (ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DT << ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTACTIV0_FNR1_DT << ATON_STRSWITCH_DSTACTIV0_FNR1_LSB) /** Description of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_DESC "Connection to input port of Activation Accelerator 0" /** Address of the DSTACTIV0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTACTIV0_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTACTIV0_OFFSET) /** Get the content of the DSTACTIV0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTACTIV0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV0_ADDR(UNIT))) /** Set the content of the DSTACTIV0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTACTIV0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTACTIV0 register. * * \return the description of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_DESC; } /** * Get the offset of the DSTACTIV0 register. * * \return the offset of DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_GetOffset(void) { return ATON_STRSWITCH_DSTACTIV0_OFFSET; } /** * Get the address of the DSTACTIV0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTACTIV0 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTACTIV0_ADDR(instance); } /** * Read the content of the DSTACTIV0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTACTIV0 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get(uint32_t instance) { return ATON_STRSWITCH_DSTACTIV0_GET(instance); } /** * Write the content of the DSTACTIV0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTACTIV0_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTACTIV0_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTACTIV0 register ----------------------------------------------------------- */ /** Description of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_S 0 /** Check whether access to the EN0 field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_EN0_P 0 /** Read the content of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN0_LSB, ATON_STRSWITCH_DSTACTIV0_EN0_W) /** Modify the content of the EN0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN0_LSB, ATON_STRSWITCH_DSTACTIV0_EN0_W, DATA) /** * Get the description of the EN0 field of DSTACTIV0 register. * * \return the description of the EN0 field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_EN0_DESC; } /** * Read the content of the EN0 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the EN0 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTACTIV0 register ---------------------------------------------------------- */ /** Description of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_LINK0_P 0 /** Read the content of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK0_LSB, ATON_STRSWITCH_DSTACTIV0_LINK0_W) /** Modify the content of the LINK0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK0_LSB, ATON_STRSWITCH_DSTACTIV0_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTACTIV0 register. * * \return the description of the LINK0 field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the LINK0 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_LINK0(reg, data); } /* ---------------------------------------------------------- FNR0 field of the DSTACTIV0 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_FNR0_P 0 /** Read the content of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR0_LSB, ATON_STRSWITCH_DSTACTIV0_FNR0_W) /** Modify the content of the FNR0 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR0_LSB, ATON_STRSWITCH_DSTACTIV0_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTACTIV0 register. * * \return the description of the FNR0 field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the FNR0 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTACTIV0 register ----------------------------------------------------------- */ /** Description of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_S 0 /** Check whether access to the EN1 field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_EN1_P 0 /** Read the content of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN1_LSB, ATON_STRSWITCH_DSTACTIV0_EN1_W) /** Modify the content of the EN1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_EN1_LSB, ATON_STRSWITCH_DSTACTIV0_EN1_W, DATA) /** * Get the description of the EN1 field of DSTACTIV0 register. * * \return the description of the EN1 field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_EN1_DESC; } /** * Read the content of the EN1 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the EN1 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTACTIV0 register ---------------------------------------------------------- */ /** Description of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_LINK1_P 0 /** Read the content of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK1_LSB, ATON_STRSWITCH_DSTACTIV0_LINK1_W) /** Modify the content of the LINK1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_LINK1_LSB, ATON_STRSWITCH_DSTACTIV0_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTACTIV0 register. * * \return the description of the LINK1 field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the LINK1 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_LINK1(reg, data); } /* -------------------------------------------------------- TICKTYPE field of the DSTACTIV0 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV0_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTACTIV0 register. * * \return the description of the TICKTYPE field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the TICKTYPE field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_TICKTYPE(reg, data); } /* ---------------------------------------------------------- FNR1 field of the DSTACTIV0 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTACTIV0 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTACTIV0 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV0_FNR1_P 0 /** Read the content of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR1_LSB, ATON_STRSWITCH_DSTACTIV0_FNR1_W) /** Modify the content of the FNR1 field of the DSTACTIV0 register. */ #define ATON_STRSWITCH_DSTACTIV0_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV0_FNR1_LSB, ATON_STRSWITCH_DSTACTIV0_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTACTIV0 register. * * \return the description of the FNR1 field of DSTACTIV0 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV0_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV0_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * * \return the content of the FNR1 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV0_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTACTIV0 register. * * \param[in] reg is the value of the DSTACTIV0 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTACTIV0 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV0_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV0_SET_FNR1(reg, data); } /* **************************************************** DSTACTIV1 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTACTIV1 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTACTIV1_OFFSET 0x74UL /** Reset value of the DSTACTIV1 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTACTIV1_DT \ (ATON_STRSWITCH_DSTACTIV1_EN0_DT << ATON_STRSWITCH_DSTACTIV1_EN0_LSB) | \ (ATON_STRSWITCH_DSTACTIV1_LINK0_DT << ATON_STRSWITCH_DSTACTIV1_LINK0_LSB) | \ (ATON_STRSWITCH_DSTACTIV1_FNR0_DT << ATON_STRSWITCH_DSTACTIV1_FNR0_LSB) | \ (ATON_STRSWITCH_DSTACTIV1_EN1_DT << ATON_STRSWITCH_DSTACTIV1_EN1_LSB) | \ (ATON_STRSWITCH_DSTACTIV1_LINK1_DT << ATON_STRSWITCH_DSTACTIV1_LINK1_LSB) | \ (ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DT << ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTACTIV1_FNR1_DT << ATON_STRSWITCH_DSTACTIV1_FNR1_LSB) /** Description of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_DESC "Connection to input port of Activation Accelerator 1" /** Address of the DSTACTIV1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTACTIV1_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTACTIV1_OFFSET) /** Get the content of the DSTACTIV1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTACTIV1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV1_ADDR(UNIT))) /** Set the content of the DSTACTIV1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTACTIV1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTACTIV1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTACTIV1 register. * * \return the description of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_DESC; } /** * Get the offset of the DSTACTIV1 register. * * \return the offset of DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_GetOffset(void) { return ATON_STRSWITCH_DSTACTIV1_OFFSET; } /** * Get the address of the DSTACTIV1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTACTIV1 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTACTIV1_ADDR(instance); } /** * Read the content of the DSTACTIV1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTACTIV1 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get(uint32_t instance) { return ATON_STRSWITCH_DSTACTIV1_GET(instance); } /** * Write the content of the DSTACTIV1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTACTIV1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTACTIV1_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTACTIV1_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTACTIV1 register ----------------------------------------------------------- */ /** Description of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_S 0 /** Check whether access to the EN0 field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_EN0_P 0 /** Read the content of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN0_LSB, ATON_STRSWITCH_DSTACTIV1_EN0_W) /** Modify the content of the EN0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN0_LSB, ATON_STRSWITCH_DSTACTIV1_EN0_W, DATA) /** * Get the description of the EN0 field of DSTACTIV1 register. * * \return the description of the EN0 field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_EN0_DESC; } /** * Read the content of the EN0 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the EN0 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTACTIV1 register ---------------------------------------------------------- */ /** Description of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_LINK0_P 0 /** Read the content of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK0_LSB, ATON_STRSWITCH_DSTACTIV1_LINK0_W) /** Modify the content of the LINK0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK0_LSB, ATON_STRSWITCH_DSTACTIV1_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTACTIV1 register. * * \return the description of the LINK0 field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the LINK0 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_LINK0(reg, data); } /* ---------------------------------------------------------- FNR0 field of the DSTACTIV1 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_FNR0_P 0 /** Read the content of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR0_LSB, ATON_STRSWITCH_DSTACTIV1_FNR0_W) /** Modify the content of the FNR0 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR0_LSB, ATON_STRSWITCH_DSTACTIV1_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTACTIV1 register. * * \return the description of the FNR0 field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the FNR0 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTACTIV1 register ----------------------------------------------------------- */ /** Description of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_S 0 /** Check whether access to the EN1 field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_EN1_P 0 /** Read the content of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN1_LSB, ATON_STRSWITCH_DSTACTIV1_EN1_W) /** Modify the content of the EN1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_EN1_LSB, ATON_STRSWITCH_DSTACTIV1_EN1_W, DATA) /** * Get the description of the EN1 field of DSTACTIV1 register. * * \return the description of the EN1 field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_EN1_DESC; } /** * Read the content of the EN1 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the EN1 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTACTIV1 register ---------------------------------------------------------- */ /** Description of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_LINK1_P 0 /** Read the content of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK1_LSB, ATON_STRSWITCH_DSTACTIV1_LINK1_W) /** Modify the content of the LINK1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_LINK1_LSB, ATON_STRSWITCH_DSTACTIV1_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTACTIV1 register. * * \return the description of the LINK1 field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the LINK1 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_LINK1(reg, data); } /* -------------------------------------------------------- TICKTYPE field of the DSTACTIV1 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_LSB, ATON_STRSWITCH_DSTACTIV1_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTACTIV1 register. * * \return the description of the TICKTYPE field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the TICKTYPE field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_TICKTYPE(reg, data); } /* ---------------------------------------------------------- FNR1 field of the DSTACTIV1 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTACTIV1 register is secured or not. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTACTIV1 register is privileged or not. */ #define ATON_STRSWITCH_DSTACTIV1_FNR1_P 0 /** Read the content of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR1_LSB, ATON_STRSWITCH_DSTACTIV1_FNR1_W) /** Modify the content of the FNR1 field of the DSTACTIV1 register. */ #define ATON_STRSWITCH_DSTACTIV1_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTACTIV1_FNR1_LSB, ATON_STRSWITCH_DSTACTIV1_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTACTIV1 register. * * \return the description of the FNR1 field of DSTACTIV1 register */ static inline const int8_t *ATON_STRSWITCH_DSTACTIV1_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTACTIV1_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * * \return the content of the FNR1 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTACTIV1_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTACTIV1 register. * * \param[in] reg is the value of the DSTACTIV1 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTACTIV1 register */ static inline uint32_t ATON_STRSWITCH_DSTACTIV1_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTACTIV1_SET_FNR1(reg, data); } /* *************************************************** DSTARITH00 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH00 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH00_OFFSET 0x78UL /** Reset value of the DSTARITH00 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH00_DT \ (ATON_STRSWITCH_DSTARITH00_EN0_DT << ATON_STRSWITCH_DSTARITH00_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH00_LINK0_DT << ATON_STRSWITCH_DSTARITH00_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH00_FNR0_DT << ATON_STRSWITCH_DSTARITH00_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH00_EN1_DT << ATON_STRSWITCH_DSTARITH00_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH00_LINK1_DT << ATON_STRSWITCH_DSTARITH00_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH00_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH00_FNR1_DT << ATON_STRSWITCH_DSTARITH00_FNR1_LSB) /** Description of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_DESC "Connection to input port 0 of Arithmetic Accelerator 0" /** Address of the DSTARITH00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH00_OFFSET) /** Get the content of the DSTARITH00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH00_ADDR(UNIT))) /** Set the content of the DSTARITH00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH00_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH00 register. * * \return the description of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_DESC; } /** * Get the offset of the DSTARITH00 register. * * \return the offset of DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_GetOffset(void) { return ATON_STRSWITCH_DSTARITH00_OFFSET; } /** * Get the address of the DSTARITH00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH00 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH00_ADDR(instance); } /** * Read the content of the DSTARITH00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH00 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH00_GET(instance); } /** * Write the content of the DSTARITH00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH00 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH00_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH00_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH00 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN0_LSB, ATON_STRSWITCH_DSTARITH00_EN0_W) /** Modify the content of the EN0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN0_LSB, ATON_STRSWITCH_DSTARITH00_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH00 register. * * \return the description of the EN0 field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the EN0 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH00 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK0_LSB, ATON_STRSWITCH_DSTARITH00_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK0_LSB, ATON_STRSWITCH_DSTARITH00_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH00 register. * * \return the description of the LINK0 field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the LINK0 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH00 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR0_LSB, ATON_STRSWITCH_DSTARITH00_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR0_LSB, ATON_STRSWITCH_DSTARITH00_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH00 register. * * \return the description of the FNR0 field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the FNR0 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH00 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN1_LSB, ATON_STRSWITCH_DSTARITH00_EN1_W) /** Modify the content of the EN1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_EN1_LSB, ATON_STRSWITCH_DSTARITH00_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH00 register. * * \return the description of the EN1 field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the EN1 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH00 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK1_LSB, ATON_STRSWITCH_DSTARITH00_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_LINK1_LSB, ATON_STRSWITCH_DSTARITH00_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH00 register. * * \return the description of the LINK1 field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the LINK1 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH00 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH00_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH00_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH00 register. * * \return the description of the TICKTYPE field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the TICKTYPE field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH00 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH00 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH00 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH00_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR1_LSB, ATON_STRSWITCH_DSTARITH00_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH00 register. */ #define ATON_STRSWITCH_DSTARITH00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH00_FNR1_LSB, ATON_STRSWITCH_DSTARITH00_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH00 register. * * \return the description of the FNR1 field of DSTARITH00 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH00_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH00_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * * \return the content of the FNR1 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH00_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH00 register. * * \param[in] reg is the value of the DSTARITH00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH00 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH00_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH00_SET_FNR1(reg, data); } /* *************************************************** DSTARITH01 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH01 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH01_OFFSET 0x7cUL /** Reset value of the DSTARITH01 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH01_DT \ (ATON_STRSWITCH_DSTARITH01_EN0_DT << ATON_STRSWITCH_DSTARITH01_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH01_LINK0_DT << ATON_STRSWITCH_DSTARITH01_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH01_FNR0_DT << ATON_STRSWITCH_DSTARITH01_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH01_EN1_DT << ATON_STRSWITCH_DSTARITH01_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH01_LINK1_DT << ATON_STRSWITCH_DSTARITH01_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH01_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH01_FNR1_DT << ATON_STRSWITCH_DSTARITH01_FNR1_LSB) /** Description of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_DESC "Connection to input port 1 of Arithmetic Accelerator 0" /** Address of the DSTARITH01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH01_OFFSET) /** Get the content of the DSTARITH01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH01_ADDR(UNIT))) /** Set the content of the DSTARITH01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH01_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH01 register. * * \return the description of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_DESC; } /** * Get the offset of the DSTARITH01 register. * * \return the offset of DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_GetOffset(void) { return ATON_STRSWITCH_DSTARITH01_OFFSET; } /** * Get the address of the DSTARITH01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH01 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH01_ADDR(instance); } /** * Read the content of the DSTARITH01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH01 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH01_GET(instance); } /** * Write the content of the DSTARITH01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH01 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH01_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH01_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH01 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN0_LSB, ATON_STRSWITCH_DSTARITH01_EN0_W) /** Modify the content of the EN0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN0_LSB, ATON_STRSWITCH_DSTARITH01_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH01 register. * * \return the description of the EN0 field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the EN0 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH01 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK0_LSB, ATON_STRSWITCH_DSTARITH01_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK0_LSB, ATON_STRSWITCH_DSTARITH01_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH01 register. * * \return the description of the LINK0 field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the LINK0 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH01 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR0_LSB, ATON_STRSWITCH_DSTARITH01_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR0_LSB, ATON_STRSWITCH_DSTARITH01_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH01 register. * * \return the description of the FNR0 field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the FNR0 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH01 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN1_LSB, ATON_STRSWITCH_DSTARITH01_EN1_W) /** Modify the content of the EN1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_EN1_LSB, ATON_STRSWITCH_DSTARITH01_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH01 register. * * \return the description of the EN1 field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the EN1 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH01 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK1_LSB, ATON_STRSWITCH_DSTARITH01_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_LINK1_LSB, ATON_STRSWITCH_DSTARITH01_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH01 register. * * \return the description of the LINK1 field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the LINK1 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH01 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH01_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH01_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH01 register. * * \return the description of the TICKTYPE field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the TICKTYPE field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH01 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH01 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH01 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH01_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR1_LSB, ATON_STRSWITCH_DSTARITH01_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH01 register. */ #define ATON_STRSWITCH_DSTARITH01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH01_FNR1_LSB, ATON_STRSWITCH_DSTARITH01_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH01 register. * * \return the description of the FNR1 field of DSTARITH01 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH01_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH01_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * * \return the content of the FNR1 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH01_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH01 register. * * \param[in] reg is the value of the DSTARITH01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH01 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH01_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH01_SET_FNR1(reg, data); } /* *************************************************** DSTARITH10 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH10 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH10_OFFSET 0x80UL /** Reset value of the DSTARITH10 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH10_DT \ (ATON_STRSWITCH_DSTARITH10_EN0_DT << ATON_STRSWITCH_DSTARITH10_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH10_LINK0_DT << ATON_STRSWITCH_DSTARITH10_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH10_FNR0_DT << ATON_STRSWITCH_DSTARITH10_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH10_EN1_DT << ATON_STRSWITCH_DSTARITH10_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH10_LINK1_DT << ATON_STRSWITCH_DSTARITH10_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH10_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH10_FNR1_DT << ATON_STRSWITCH_DSTARITH10_FNR1_LSB) /** Description of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_DESC "Connection to input port 0 of Arithmetic Accelerator 1" /** Address of the DSTARITH10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH10_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH10_OFFSET) /** Get the content of the DSTARITH10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH10_ADDR(UNIT))) /** Set the content of the DSTARITH10 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH10_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH10 register. * * \return the description of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_DESC; } /** * Get the offset of the DSTARITH10 register. * * \return the offset of DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_GetOffset(void) { return ATON_STRSWITCH_DSTARITH10_OFFSET; } /** * Get the address of the DSTARITH10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH10 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH10 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH10_ADDR(instance); } /** * Read the content of the DSTARITH10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH10 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH10 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH10_GET(instance); } /** * Write the content of the DSTARITH10 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH10 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH10_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH10_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH10 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN0_LSB, ATON_STRSWITCH_DSTARITH10_EN0_W) /** Modify the content of the EN0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN0_LSB, ATON_STRSWITCH_DSTARITH10_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH10 register. * * \return the description of the EN0 field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the EN0 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH10 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK0_LSB, ATON_STRSWITCH_DSTARITH10_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK0_LSB, ATON_STRSWITCH_DSTARITH10_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH10 register. * * \return the description of the LINK0 field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the LINK0 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH10 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR0_LSB, ATON_STRSWITCH_DSTARITH10_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR0_LSB, ATON_STRSWITCH_DSTARITH10_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH10 register. * * \return the description of the FNR0 field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the FNR0 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH10 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN1_LSB, ATON_STRSWITCH_DSTARITH10_EN1_W) /** Modify the content of the EN1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_EN1_LSB, ATON_STRSWITCH_DSTARITH10_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH10 register. * * \return the description of the EN1 field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the EN1 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH10 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK1_LSB, ATON_STRSWITCH_DSTARITH10_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_LINK1_LSB, ATON_STRSWITCH_DSTARITH10_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH10 register. * * \return the description of the LINK1 field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the LINK1 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH10 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH10_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH10_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH10 register. * * \return the description of the TICKTYPE field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the TICKTYPE field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH10 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH10 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH10 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH10_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR1_LSB, ATON_STRSWITCH_DSTARITH10_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH10 register. */ #define ATON_STRSWITCH_DSTARITH10_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH10_FNR1_LSB, ATON_STRSWITCH_DSTARITH10_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH10 register. * * \return the description of the FNR1 field of DSTARITH10 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH10_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH10_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * * \return the content of the FNR1 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH10_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH10 register. * * \param[in] reg is the value of the DSTARITH10 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH10 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH10_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH10_SET_FNR1(reg, data); } /* *************************************************** DSTARITH11 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH11 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH11_OFFSET 0x84UL /** Reset value of the DSTARITH11 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH11_DT \ (ATON_STRSWITCH_DSTARITH11_EN0_DT << ATON_STRSWITCH_DSTARITH11_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH11_LINK0_DT << ATON_STRSWITCH_DSTARITH11_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH11_FNR0_DT << ATON_STRSWITCH_DSTARITH11_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH11_EN1_DT << ATON_STRSWITCH_DSTARITH11_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH11_LINK1_DT << ATON_STRSWITCH_DSTARITH11_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH11_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH11_FNR1_DT << ATON_STRSWITCH_DSTARITH11_FNR1_LSB) /** Description of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_DESC "Connection to input port 1 of Arithmetic Accelerator 1" /** Address of the DSTARITH11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH11_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH11_OFFSET) /** Get the content of the DSTARITH11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH11_ADDR(UNIT))) /** Set the content of the DSTARITH11 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH11_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH11 register. * * \return the description of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_DESC; } /** * Get the offset of the DSTARITH11 register. * * \return the offset of DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_GetOffset(void) { return ATON_STRSWITCH_DSTARITH11_OFFSET; } /** * Get the address of the DSTARITH11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH11 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH11 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH11_ADDR(instance); } /** * Read the content of the DSTARITH11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH11 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH11 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH11_GET(instance); } /** * Write the content of the DSTARITH11 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH11 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH11_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH11_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH11 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN0_LSB, ATON_STRSWITCH_DSTARITH11_EN0_W) /** Modify the content of the EN0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN0_LSB, ATON_STRSWITCH_DSTARITH11_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH11 register. * * \return the description of the EN0 field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the EN0 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH11 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK0_LSB, ATON_STRSWITCH_DSTARITH11_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK0_LSB, ATON_STRSWITCH_DSTARITH11_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH11 register. * * \return the description of the LINK0 field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the LINK0 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH11 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR0_LSB, ATON_STRSWITCH_DSTARITH11_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR0_LSB, ATON_STRSWITCH_DSTARITH11_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH11 register. * * \return the description of the FNR0 field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the FNR0 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH11 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN1_LSB, ATON_STRSWITCH_DSTARITH11_EN1_W) /** Modify the content of the EN1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_EN1_LSB, ATON_STRSWITCH_DSTARITH11_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH11 register. * * \return the description of the EN1 field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the EN1 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH11 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK1_LSB, ATON_STRSWITCH_DSTARITH11_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_LINK1_LSB, ATON_STRSWITCH_DSTARITH11_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH11 register. * * \return the description of the LINK1 field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the LINK1 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH11 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH11_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH11_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH11 register. * * \return the description of the TICKTYPE field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the TICKTYPE field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH11 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH11 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH11 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH11_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR1_LSB, ATON_STRSWITCH_DSTARITH11_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH11 register. */ #define ATON_STRSWITCH_DSTARITH11_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH11_FNR1_LSB, ATON_STRSWITCH_DSTARITH11_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH11 register. * * \return the description of the FNR1 field of DSTARITH11 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH11_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH11_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * * \return the content of the FNR1 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH11_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH11 register. * * \param[in] reg is the value of the DSTARITH11 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH11 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH11_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH11_SET_FNR1(reg, data); } /* *************************************************** DSTARITH20 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH20 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH20_OFFSET 0x88UL /** Reset value of the DSTARITH20 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH20_DT \ (ATON_STRSWITCH_DSTARITH20_EN0_DT << ATON_STRSWITCH_DSTARITH20_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH20_LINK0_DT << ATON_STRSWITCH_DSTARITH20_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH20_FNR0_DT << ATON_STRSWITCH_DSTARITH20_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH20_EN1_DT << ATON_STRSWITCH_DSTARITH20_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH20_LINK1_DT << ATON_STRSWITCH_DSTARITH20_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH20_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH20_FNR1_DT << ATON_STRSWITCH_DSTARITH20_FNR1_LSB) /** Description of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_DESC "Connection to input port 0 of Arithmetic Accelerator 2" /** Address of the DSTARITH20 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH20_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH20_OFFSET) /** Get the content of the DSTARITH20 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH20_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH20_ADDR(UNIT))) /** Set the content of the DSTARITH20 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH20_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH20_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH20 register. * * \return the description of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_DESC; } /** * Get the offset of the DSTARITH20 register. * * \return the offset of DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_GetOffset(void) { return ATON_STRSWITCH_DSTARITH20_OFFSET; } /** * Get the address of the DSTARITH20 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH20 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH20 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH20_ADDR(instance); } /** * Read the content of the DSTARITH20 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH20 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH20 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH20_GET(instance); } /** * Write the content of the DSTARITH20 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH20 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH20_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH20_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH20 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN0_LSB, ATON_STRSWITCH_DSTARITH20_EN0_W) /** Modify the content of the EN0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN0_LSB, ATON_STRSWITCH_DSTARITH20_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH20 register. * * \return the description of the EN0 field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the EN0 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH20 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK0_LSB, ATON_STRSWITCH_DSTARITH20_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK0_LSB, ATON_STRSWITCH_DSTARITH20_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH20 register. * * \return the description of the LINK0 field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the LINK0 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH20 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR0_LSB, ATON_STRSWITCH_DSTARITH20_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR0_LSB, ATON_STRSWITCH_DSTARITH20_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH20 register. * * \return the description of the FNR0 field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the FNR0 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH20 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN1_LSB, ATON_STRSWITCH_DSTARITH20_EN1_W) /** Modify the content of the EN1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_EN1_LSB, ATON_STRSWITCH_DSTARITH20_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH20 register. * * \return the description of the EN1 field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the EN1 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH20 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK1_LSB, ATON_STRSWITCH_DSTARITH20_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_LINK1_LSB, ATON_STRSWITCH_DSTARITH20_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH20 register. * * \return the description of the LINK1 field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the LINK1 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH20 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH20_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH20_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH20 register. * * \return the description of the TICKTYPE field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the TICKTYPE field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH20 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH20 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH20 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH20_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR1_LSB, ATON_STRSWITCH_DSTARITH20_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH20 register. */ #define ATON_STRSWITCH_DSTARITH20_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH20_FNR1_LSB, ATON_STRSWITCH_DSTARITH20_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH20 register. * * \return the description of the FNR1 field of DSTARITH20 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH20_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH20_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * * \return the content of the FNR1 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH20_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH20 register. * * \param[in] reg is the value of the DSTARITH20 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH20 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH20_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH20_SET_FNR1(reg, data); } /* *************************************************** DSTARITH21 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH21 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH21_OFFSET 0x8cUL /** Reset value of the DSTARITH21 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH21_DT \ (ATON_STRSWITCH_DSTARITH21_EN0_DT << ATON_STRSWITCH_DSTARITH21_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH21_LINK0_DT << ATON_STRSWITCH_DSTARITH21_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH21_FNR0_DT << ATON_STRSWITCH_DSTARITH21_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH21_EN1_DT << ATON_STRSWITCH_DSTARITH21_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH21_LINK1_DT << ATON_STRSWITCH_DSTARITH21_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH21_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH21_FNR1_DT << ATON_STRSWITCH_DSTARITH21_FNR1_LSB) /** Description of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_DESC "Connection to input port 1 of Arithmetic Accelerator 2" /** Address of the DSTARITH21 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH21_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH21_OFFSET) /** Get the content of the DSTARITH21 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH21_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH21_ADDR(UNIT))) /** Set the content of the DSTARITH21 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH21_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH21_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH21 register. * * \return the description of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_DESC; } /** * Get the offset of the DSTARITH21 register. * * \return the offset of DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_GetOffset(void) { return ATON_STRSWITCH_DSTARITH21_OFFSET; } /** * Get the address of the DSTARITH21 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH21 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH21 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH21_ADDR(instance); } /** * Read the content of the DSTARITH21 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH21 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH21 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH21_GET(instance); } /** * Write the content of the DSTARITH21 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH21 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH21_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH21_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH21 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN0_LSB, ATON_STRSWITCH_DSTARITH21_EN0_W) /** Modify the content of the EN0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN0_LSB, ATON_STRSWITCH_DSTARITH21_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH21 register. * * \return the description of the EN0 field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the EN0 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH21 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK0_LSB, ATON_STRSWITCH_DSTARITH21_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK0_LSB, ATON_STRSWITCH_DSTARITH21_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH21 register. * * \return the description of the LINK0 field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the LINK0 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH21 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR0_LSB, ATON_STRSWITCH_DSTARITH21_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR0_LSB, ATON_STRSWITCH_DSTARITH21_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH21 register. * * \return the description of the FNR0 field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the FNR0 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH21 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN1_LSB, ATON_STRSWITCH_DSTARITH21_EN1_W) /** Modify the content of the EN1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_EN1_LSB, ATON_STRSWITCH_DSTARITH21_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH21 register. * * \return the description of the EN1 field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the EN1 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH21 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK1_LSB, ATON_STRSWITCH_DSTARITH21_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_LINK1_LSB, ATON_STRSWITCH_DSTARITH21_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH21 register. * * \return the description of the LINK1 field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the LINK1 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH21 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH21_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH21_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH21 register. * * \return the description of the TICKTYPE field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the TICKTYPE field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH21 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH21 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH21 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH21_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR1_LSB, ATON_STRSWITCH_DSTARITH21_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH21 register. */ #define ATON_STRSWITCH_DSTARITH21_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH21_FNR1_LSB, ATON_STRSWITCH_DSTARITH21_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH21 register. * * \return the description of the FNR1 field of DSTARITH21 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH21_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH21_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * * \return the content of the FNR1 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH21_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH21 register. * * \param[in] reg is the value of the DSTARITH21 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH21 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH21_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH21_SET_FNR1(reg, data); } /* *************************************************** DSTARITH30 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH30 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH30_OFFSET 0x90UL /** Reset value of the DSTARITH30 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH30_DT \ (ATON_STRSWITCH_DSTARITH30_EN0_DT << ATON_STRSWITCH_DSTARITH30_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH30_LINK0_DT << ATON_STRSWITCH_DSTARITH30_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH30_FNR0_DT << ATON_STRSWITCH_DSTARITH30_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH30_EN1_DT << ATON_STRSWITCH_DSTARITH30_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH30_LINK1_DT << ATON_STRSWITCH_DSTARITH30_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH30_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH30_FNR1_DT << ATON_STRSWITCH_DSTARITH30_FNR1_LSB) /** Description of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_DESC "Connection to input port 0 of Arithmetic Accelerator 3" /** Address of the DSTARITH30 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH30_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH30_OFFSET) /** Get the content of the DSTARITH30 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH30_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH30_ADDR(UNIT))) /** Set the content of the DSTARITH30 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH30_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH30_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH30 register. * * \return the description of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_DESC; } /** * Get the offset of the DSTARITH30 register. * * \return the offset of DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_GetOffset(void) { return ATON_STRSWITCH_DSTARITH30_OFFSET; } /** * Get the address of the DSTARITH30 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH30 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH30 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH30_ADDR(instance); } /** * Read the content of the DSTARITH30 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH30 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH30 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH30_GET(instance); } /** * Write the content of the DSTARITH30 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH30 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH30_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH30_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH30 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN0_LSB, ATON_STRSWITCH_DSTARITH30_EN0_W) /** Modify the content of the EN0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN0_LSB, ATON_STRSWITCH_DSTARITH30_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH30 register. * * \return the description of the EN0 field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the EN0 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH30 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK0_LSB, ATON_STRSWITCH_DSTARITH30_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK0_LSB, ATON_STRSWITCH_DSTARITH30_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH30 register. * * \return the description of the LINK0 field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the LINK0 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH30 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR0_LSB, ATON_STRSWITCH_DSTARITH30_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR0_LSB, ATON_STRSWITCH_DSTARITH30_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH30 register. * * \return the description of the FNR0 field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the FNR0 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH30 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN1_LSB, ATON_STRSWITCH_DSTARITH30_EN1_W) /** Modify the content of the EN1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_EN1_LSB, ATON_STRSWITCH_DSTARITH30_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH30 register. * * \return the description of the EN1 field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the EN1 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH30 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK1_LSB, ATON_STRSWITCH_DSTARITH30_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_LINK1_LSB, ATON_STRSWITCH_DSTARITH30_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH30 register. * * \return the description of the LINK1 field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the LINK1 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH30 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH30_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH30_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH30 register. * * \return the description of the TICKTYPE field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the TICKTYPE field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH30 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH30 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH30 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH30_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR1_LSB, ATON_STRSWITCH_DSTARITH30_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH30 register. */ #define ATON_STRSWITCH_DSTARITH30_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH30_FNR1_LSB, ATON_STRSWITCH_DSTARITH30_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH30 register. * * \return the description of the FNR1 field of DSTARITH30 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH30_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH30_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * * \return the content of the FNR1 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH30_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH30 register. * * \param[in] reg is the value of the DSTARITH30 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH30 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH30_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH30_SET_FNR1(reg, data); } /* *************************************************** DSTARITH31 register of one of the STRSWITCH Units **************************************************** */ /** Offset of the DSTARITH31 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH31_OFFSET 0x94UL /** Reset value of the DSTARITH31 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTARITH31_DT \ (ATON_STRSWITCH_DSTARITH31_EN0_DT << ATON_STRSWITCH_DSTARITH31_EN0_LSB) | \ (ATON_STRSWITCH_DSTARITH31_LINK0_DT << ATON_STRSWITCH_DSTARITH31_LINK0_LSB) | \ (ATON_STRSWITCH_DSTARITH31_FNR0_DT << ATON_STRSWITCH_DSTARITH31_FNR0_LSB) | \ (ATON_STRSWITCH_DSTARITH31_EN1_DT << ATON_STRSWITCH_DSTARITH31_EN1_LSB) | \ (ATON_STRSWITCH_DSTARITH31_LINK1_DT << ATON_STRSWITCH_DSTARITH31_LINK1_LSB) | \ (ATON_STRSWITCH_DSTARITH31_TICKTYPE_DT << ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTARITH31_FNR1_DT << ATON_STRSWITCH_DSTARITH31_FNR1_LSB) /** Description of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_DESC "Connection to input port 1 of Arithmetic Accelerator 3" /** Address of the DSTARITH31 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH31_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTARITH31_OFFSET) /** Get the content of the DSTARITH31 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH31_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH31_ADDR(UNIT))) /** Set the content of the DSTARITH31 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTARITH31_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTARITH31_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTARITH31 register. * * \return the description of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_DESC; } /** * Get the offset of the DSTARITH31 register. * * \return the offset of DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_GetOffset(void) { return ATON_STRSWITCH_DSTARITH31_OFFSET; } /** * Get the address of the DSTARITH31 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH31 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTARITH31 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTARITH31_ADDR(instance); } /** * Read the content of the DSTARITH31 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH31 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTARITH31 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get(uint32_t instance) { return ATON_STRSWITCH_DSTARITH31_GET(instance); } /** * Write the content of the DSTARITH31 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTARITH31 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTARITH31_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTARITH31_SET(instance, data); } /* ---------------------------------------------------------- EN0 field of the DSTARITH31 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_EN0_S 0 /** Check whether access to the EN0 field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_EN0_P 0 /** Read the content of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN0_LSB, ATON_STRSWITCH_DSTARITH31_EN0_W) /** Modify the content of the EN0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN0_LSB, ATON_STRSWITCH_DSTARITH31_EN0_W, DATA) /** * Get the description of the EN0 field of DSTARITH31 register. * * \return the description of the EN0 field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_EN0_DESC; } /** * Read the content of the EN0 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the EN0 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_EN0(reg, data); } /* --------------------------------------------------------- LINK0 field of the DSTARITH31 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_LINK0_P 0 /** Read the content of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK0_LSB, ATON_STRSWITCH_DSTARITH31_LINK0_W) /** Modify the content of the LINK0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK0_LSB, ATON_STRSWITCH_DSTARITH31_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTARITH31 register. * * \return the description of the LINK0 field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the LINK0 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTARITH31 register ---------------------------------------------------------- */ /** Description of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_FNR0_P 0 /** Read the content of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR0_LSB, ATON_STRSWITCH_DSTARITH31_FNR0_W) /** Modify the content of the FNR0 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR0_LSB, ATON_STRSWITCH_DSTARITH31_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTARITH31 register. * * \return the description of the FNR0 field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the FNR0 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_FNR0(reg, data); } /* ---------------------------------------------------------- EN1 field of the DSTARITH31 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_EN1_S 0 /** Check whether access to the EN1 field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_EN1_P 0 /** Read the content of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN1_LSB, ATON_STRSWITCH_DSTARITH31_EN1_W) /** Modify the content of the EN1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_EN1_LSB, ATON_STRSWITCH_DSTARITH31_EN1_W, DATA) /** * Get the description of the EN1 field of DSTARITH31 register. * * \return the description of the EN1 field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_EN1_DESC; } /** * Read the content of the EN1 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the EN1 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_EN1(reg, data); } /* --------------------------------------------------------- LINK1 field of the DSTARITH31 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_LINK1_P 0 /** Read the content of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK1_LSB, ATON_STRSWITCH_DSTARITH31_LINK1_W) /** Modify the content of the LINK1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_LINK1_LSB, ATON_STRSWITCH_DSTARITH31_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTARITH31 register. * * \return the description of the LINK1 field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the LINK1 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTARITH31 register -------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH31_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_TICKTYPE_LSB, ATON_STRSWITCH_DSTARITH31_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTARITH31 register. * * \return the description of the TICKTYPE field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the TICKTYPE field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTARITH31 register ---------------------------------------------------------- */ /** Description of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTARITH31 register is secured or not. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTARITH31 register is privileged or not. */ #define ATON_STRSWITCH_DSTARITH31_FNR1_P 0 /** Read the content of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR1_LSB, ATON_STRSWITCH_DSTARITH31_FNR1_W) /** Modify the content of the FNR1 field of the DSTARITH31 register. */ #define ATON_STRSWITCH_DSTARITH31_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTARITH31_FNR1_LSB, ATON_STRSWITCH_DSTARITH31_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTARITH31 register. * * \return the description of the FNR1 field of DSTARITH31 register */ static inline const int8_t *ATON_STRSWITCH_DSTARITH31_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTARITH31_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * * \return the content of the FNR1 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTARITH31_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTARITH31 register. * * \param[in] reg is the value of the DSTARITH31 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTARITH31 register */ static inline uint32_t ATON_STRSWITCH_DSTARITH31_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTARITH31_SET_FNR1(reg, data); } /* **************************************************** DSTPOOL0 register of one of the STRSWITCH Units ***************************************************** */ /** Offset of the DSTPOOL0 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTPOOL0_OFFSET 0x98UL /** Reset value of the DSTPOOL0 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTPOOL0_DT \ (ATON_STRSWITCH_DSTPOOL0_EN0_DT << ATON_STRSWITCH_DSTPOOL0_EN0_LSB) | \ (ATON_STRSWITCH_DSTPOOL0_LINK0_DT << ATON_STRSWITCH_DSTPOOL0_LINK0_LSB) | \ (ATON_STRSWITCH_DSTPOOL0_FNR0_DT << ATON_STRSWITCH_DSTPOOL0_FNR0_LSB) | \ (ATON_STRSWITCH_DSTPOOL0_EN1_DT << ATON_STRSWITCH_DSTPOOL0_EN1_LSB) | \ (ATON_STRSWITCH_DSTPOOL0_LINK1_DT << ATON_STRSWITCH_DSTPOOL0_LINK1_LSB) | \ (ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DT << ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTPOOL0_FNR1_DT << ATON_STRSWITCH_DSTPOOL0_FNR1_LSB) /** Description of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_DESC "Connection to input port of Pooling Accelerator 0" /** Address of the DSTPOOL0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTPOOL0_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTPOOL0_OFFSET) /** Get the content of the DSTPOOL0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTPOOL0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL0_ADDR(UNIT))) /** Set the content of the DSTPOOL0 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTPOOL0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTPOOL0 register. * * \return the description of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_DESC; } /** * Get the offset of the DSTPOOL0 register. * * \return the offset of DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_GetOffset(void) { return ATON_STRSWITCH_DSTPOOL0_OFFSET; } /** * Get the address of the DSTPOOL0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTPOOL0 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTPOOL0_ADDR(instance); } /** * Read the content of the DSTPOOL0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTPOOL0 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get(uint32_t instance) { return ATON_STRSWITCH_DSTPOOL0_GET(instance); } /** * Write the content of the DSTPOOL0 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTPOOL0_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTPOOL0_SET(instance, data); } /* ----------------------------------------------------------- EN0 field of the DSTPOOL0 register ----------------------------------------------------------- */ /** Description of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_S 0 /** Check whether access to the EN0 field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_EN0_P 0 /** Read the content of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN0_LSB, ATON_STRSWITCH_DSTPOOL0_EN0_W) /** Modify the content of the EN0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN0_LSB, ATON_STRSWITCH_DSTPOOL0_EN0_W, DATA) /** * Get the description of the EN0 field of DSTPOOL0 register. * * \return the description of the EN0 field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_EN0_DESC; } /** * Read the content of the EN0 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the EN0 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_EN0(reg, data); } /* ---------------------------------------------------------- LINK0 field of the DSTPOOL0 register ---------------------------------------------------------- */ /** Description of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_LINK0_P 0 /** Read the content of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK0_LSB, ATON_STRSWITCH_DSTPOOL0_LINK0_W) /** Modify the content of the LINK0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK0_LSB, ATON_STRSWITCH_DSTPOOL0_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTPOOL0 register. * * \return the description of the LINK0 field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the LINK0 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_LINK0(reg, data); } /* ---------------------------------------------------------- FNR0 field of the DSTPOOL0 register ----------------------------------------------------------- */ /** Description of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_FNR0_P 0 /** Read the content of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR0_LSB, ATON_STRSWITCH_DSTPOOL0_FNR0_W) /** Modify the content of the FNR0 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR0_LSB, ATON_STRSWITCH_DSTPOOL0_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTPOOL0 register. * * \return the description of the FNR0 field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the FNR0 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_FNR0(reg, data); } /* ----------------------------------------------------------- EN1 field of the DSTPOOL0 register ----------------------------------------------------------- */ /** Description of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_S 0 /** Check whether access to the EN1 field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_EN1_P 0 /** Read the content of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN1_LSB, ATON_STRSWITCH_DSTPOOL0_EN1_W) /** Modify the content of the EN1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_EN1_LSB, ATON_STRSWITCH_DSTPOOL0_EN1_W, DATA) /** * Get the description of the EN1 field of DSTPOOL0 register. * * \return the description of the EN1 field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_EN1_DESC; } /** * Read the content of the EN1 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the EN1 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_EN1(reg, data); } /* ---------------------------------------------------------- LINK1 field of the DSTPOOL0 register ---------------------------------------------------------- */ /** Description of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_LINK1_P 0 /** Read the content of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK1_LSB, ATON_STRSWITCH_DSTPOOL0_LINK1_W) /** Modify the content of the LINK1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_LINK1_LSB, ATON_STRSWITCH_DSTPOOL0_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTPOOL0 register. * * \return the description of the LINK1 field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the LINK1 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_LINK1(reg, data); } /* -------------------------------------------------------- TICKTYPE field of the DSTPOOL0 register --------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL0_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTPOOL0 register. * * \return the description of the TICKTYPE field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the TICKTYPE field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_TICKTYPE(reg, data); } /* ---------------------------------------------------------- FNR1 field of the DSTPOOL0 register ----------------------------------------------------------- */ /** Description of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTPOOL0 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTPOOL0 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL0_FNR1_P 0 /** Read the content of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR1_LSB, ATON_STRSWITCH_DSTPOOL0_FNR1_W) /** Modify the content of the FNR1 field of the DSTPOOL0 register. */ #define ATON_STRSWITCH_DSTPOOL0_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL0_FNR1_LSB, ATON_STRSWITCH_DSTPOOL0_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTPOOL0 register. * * \return the description of the FNR1 field of DSTPOOL0 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL0_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL0_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * * \return the content of the FNR1 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL0_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTPOOL0 register. * * \param[in] reg is the value of the DSTPOOL0 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTPOOL0 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL0_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL0_SET_FNR1(reg, data); } /* **************************************************** DSTPOOL1 register of one of the STRSWITCH Units ***************************************************** */ /** Offset of the DSTPOOL1 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTPOOL1_OFFSET 0x9cUL /** Reset value of the DSTPOOL1 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTPOOL1_DT \ (ATON_STRSWITCH_DSTPOOL1_EN0_DT << ATON_STRSWITCH_DSTPOOL1_EN0_LSB) | \ (ATON_STRSWITCH_DSTPOOL1_LINK0_DT << ATON_STRSWITCH_DSTPOOL1_LINK0_LSB) | \ (ATON_STRSWITCH_DSTPOOL1_FNR0_DT << ATON_STRSWITCH_DSTPOOL1_FNR0_LSB) | \ (ATON_STRSWITCH_DSTPOOL1_EN1_DT << ATON_STRSWITCH_DSTPOOL1_EN1_LSB) | \ (ATON_STRSWITCH_DSTPOOL1_LINK1_DT << ATON_STRSWITCH_DSTPOOL1_LINK1_LSB) | \ (ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DT << ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTPOOL1_FNR1_DT << ATON_STRSWITCH_DSTPOOL1_FNR1_LSB) /** Description of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_DESC "Connection to input port of Pooling Accelerator 1" /** Address of the DSTPOOL1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTPOOL1_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTPOOL1_OFFSET) /** Get the content of the DSTPOOL1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTPOOL1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL1_ADDR(UNIT))) /** Set the content of the DSTPOOL1 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTPOOL1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTPOOL1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTPOOL1 register. * * \return the description of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_DESC; } /** * Get the offset of the DSTPOOL1 register. * * \return the offset of DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_GetOffset(void) { return ATON_STRSWITCH_DSTPOOL1_OFFSET; } /** * Get the address of the DSTPOOL1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTPOOL1 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTPOOL1_ADDR(instance); } /** * Read the content of the DSTPOOL1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTPOOL1 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get(uint32_t instance) { return ATON_STRSWITCH_DSTPOOL1_GET(instance); } /** * Write the content of the DSTPOOL1 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTPOOL1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTPOOL1_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTPOOL1_SET(instance, data); } /* ----------------------------------------------------------- EN0 field of the DSTPOOL1 register ----------------------------------------------------------- */ /** Description of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_S 0 /** Check whether access to the EN0 field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_EN0_P 0 /** Read the content of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN0_LSB, ATON_STRSWITCH_DSTPOOL1_EN0_W) /** Modify the content of the EN0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN0_LSB, ATON_STRSWITCH_DSTPOOL1_EN0_W, DATA) /** * Get the description of the EN0 field of DSTPOOL1 register. * * \return the description of the EN0 field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_EN0_DESC; } /** * Read the content of the EN0 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the EN0 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_EN0(reg, data); } /* ---------------------------------------------------------- LINK0 field of the DSTPOOL1 register ---------------------------------------------------------- */ /** Description of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_LINK0_P 0 /** Read the content of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK0_LSB, ATON_STRSWITCH_DSTPOOL1_LINK0_W) /** Modify the content of the LINK0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK0_LSB, ATON_STRSWITCH_DSTPOOL1_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTPOOL1 register. * * \return the description of the LINK0 field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the LINK0 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_LINK0(reg, data); } /* ---------------------------------------------------------- FNR0 field of the DSTPOOL1 register ----------------------------------------------------------- */ /** Description of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_FNR0_P 0 /** Read the content of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR0_LSB, ATON_STRSWITCH_DSTPOOL1_FNR0_W) /** Modify the content of the FNR0 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR0_LSB, ATON_STRSWITCH_DSTPOOL1_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTPOOL1 register. * * \return the description of the FNR0 field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the FNR0 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_FNR0(reg, data); } /* ----------------------------------------------------------- EN1 field of the DSTPOOL1 register ----------------------------------------------------------- */ /** Description of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_S 0 /** Check whether access to the EN1 field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_EN1_P 0 /** Read the content of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN1_LSB, ATON_STRSWITCH_DSTPOOL1_EN1_W) /** Modify the content of the EN1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_EN1_LSB, ATON_STRSWITCH_DSTPOOL1_EN1_W, DATA) /** * Get the description of the EN1 field of DSTPOOL1 register. * * \return the description of the EN1 field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_EN1_DESC; } /** * Read the content of the EN1 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the EN1 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_EN1(reg, data); } /* ---------------------------------------------------------- LINK1 field of the DSTPOOL1 register ---------------------------------------------------------- */ /** Description of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_LINK1_P 0 /** Read the content of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK1_LSB, ATON_STRSWITCH_DSTPOOL1_LINK1_W) /** Modify the content of the LINK1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_LINK1_LSB, ATON_STRSWITCH_DSTPOOL1_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTPOOL1 register. * * \return the description of the LINK1 field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the LINK1 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_LINK1(reg, data); } /* -------------------------------------------------------- TICKTYPE field of the DSTPOOL1 register --------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_LSB, ATON_STRSWITCH_DSTPOOL1_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTPOOL1 register. * * \return the description of the TICKTYPE field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the TICKTYPE field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_TICKTYPE(reg, data); } /* ---------------------------------------------------------- FNR1 field of the DSTPOOL1 register ----------------------------------------------------------- */ /** Description of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTPOOL1 register is secured or not. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTPOOL1 register is privileged or not. */ #define ATON_STRSWITCH_DSTPOOL1_FNR1_P 0 /** Read the content of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR1_LSB, ATON_STRSWITCH_DSTPOOL1_FNR1_W) /** Modify the content of the FNR1 field of the DSTPOOL1 register. */ #define ATON_STRSWITCH_DSTPOOL1_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTPOOL1_FNR1_LSB, ATON_STRSWITCH_DSTPOOL1_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTPOOL1 register. * * \return the description of the FNR1 field of DSTPOOL1 register */ static inline const int8_t *ATON_STRSWITCH_DSTPOOL1_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTPOOL1_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * * \return the content of the FNR1 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTPOOL1_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTPOOL1 register. * * \param[in] reg is the value of the DSTPOOL1 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTPOOL1 register */ static inline uint32_t ATON_STRSWITCH_DSTPOOL1_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTPOOL1_SET_FNR1(reg, data); } /* *************************************************** DSTRECBUF00 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTRECBUF00 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTRECBUF00_OFFSET 0xa0UL /** Reset value of the DSTRECBUF00 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTRECBUF00_DT \ (ATON_STRSWITCH_DSTRECBUF00_EN0_DT << ATON_STRSWITCH_DSTRECBUF00_EN0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF00_LINK0_DT << ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF00_FNR0_DT << ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF00_EN1_DT << ATON_STRSWITCH_DSTRECBUF00_EN1_LSB) | \ (ATON_STRSWITCH_DSTRECBUF00_LINK1_DT << ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB) | \ (ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DT << ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTRECBUF00_FNR1_DT << ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB) /** Description of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_DESC "Connection to input port 0 of Reconfigurable Buffer 0" /** Address of the DSTRECBUF00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF00_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTRECBUF00_OFFSET) /** Get the content of the DSTRECBUF00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF00_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF00_ADDR(UNIT))) /** Set the content of the DSTRECBUF00 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF00_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF00_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTRECBUF00 register. * * \return the description of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_DESC; } /** * Get the offset of the DSTRECBUF00 register. * * \return the offset of DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_GetOffset(void) { return ATON_STRSWITCH_DSTRECBUF00_OFFSET; } /** * Get the address of the DSTRECBUF00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF00 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTRECBUF00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTRECBUF00_ADDR(instance); } /** * Read the content of the DSTRECBUF00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF00 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTRECBUF00 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get(uint32_t instance) { return ATON_STRSWITCH_DSTRECBUF00_GET(instance); } /** * Write the content of the DSTRECBUF00 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF00 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTRECBUF00_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTRECBUF00_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTRECBUF00 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_S 0 /** Check whether access to the EN0 field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_EN0_P 0 /** Read the content of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN0_LSB, ATON_STRSWITCH_DSTRECBUF00_EN0_W) /** Modify the content of the EN0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN0_LSB, ATON_STRSWITCH_DSTRECBUF00_EN0_W, DATA) /** * Get the description of the EN0 field of DSTRECBUF00 register. * * \return the description of the EN0 field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_EN0_DESC; } /** * Read the content of the EN0 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the EN0 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTRECBUF00 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK0_P 0 /** Read the content of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK0_W) /** Modify the content of the LINK0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTRECBUF00 register. * * \return the description of the LINK0 field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the LINK0 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTRECBUF00 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR0_P 0 /** Read the content of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR0_W) /** Modify the content of the FNR0 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTRECBUF00 register. * * \return the description of the FNR0 field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the FNR0 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTRECBUF00 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_S 0 /** Check whether access to the EN1 field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_EN1_P 0 /** Read the content of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN1_LSB, ATON_STRSWITCH_DSTRECBUF00_EN1_W) /** Modify the content of the EN1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_EN1_LSB, ATON_STRSWITCH_DSTRECBUF00_EN1_W, DATA) /** * Get the description of the EN1 field of DSTRECBUF00 register. * * \return the description of the EN1 field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_EN1_DESC; } /** * Read the content of the EN1 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the EN1 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTRECBUF00 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_LINK1_P 0 /** Read the content of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK1_W) /** Modify the content of the LINK1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF00_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTRECBUF00 register. * * \return the description of the LINK1 field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the LINK1 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTRECBUF00 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTRECBUF00 register. * * \return the description of the TICKTYPE field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the TICKTYPE field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTRECBUF00 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTRECBUF00 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTRECBUF00 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF00_FNR1_P 0 /** Read the content of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR1_W) /** Modify the content of the FNR1 field of the DSTRECBUF00 register. */ #define ATON_STRSWITCH_DSTRECBUF00_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF00_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF00_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTRECBUF00 register. * * \return the description of the FNR1 field of DSTRECBUF00 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF00_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF00_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * * \return the content of the FNR1 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF00_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTRECBUF00 register. * * \param[in] reg is the value of the DSTRECBUF00 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTRECBUF00 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF00_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF00_SET_FNR1(reg, data); } /* *************************************************** DSTRECBUF01 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTRECBUF01 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTRECBUF01_OFFSET 0xa4UL /** Reset value of the DSTRECBUF01 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTRECBUF01_DT \ (ATON_STRSWITCH_DSTRECBUF01_EN0_DT << ATON_STRSWITCH_DSTRECBUF01_EN0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF01_LINK0_DT << ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF01_FNR0_DT << ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF01_EN1_DT << ATON_STRSWITCH_DSTRECBUF01_EN1_LSB) | \ (ATON_STRSWITCH_DSTRECBUF01_LINK1_DT << ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB) | \ (ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DT << ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTRECBUF01_FNR1_DT << ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB) /** Description of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_DESC "Connection to input port 1 of Reconfigurable Buffer 0" /** Address of the DSTRECBUF01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF01_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTRECBUF01_OFFSET) /** Get the content of the DSTRECBUF01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF01_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF01_ADDR(UNIT))) /** Set the content of the DSTRECBUF01 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF01_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF01_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTRECBUF01 register. * * \return the description of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_DESC; } /** * Get the offset of the DSTRECBUF01 register. * * \return the offset of DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_GetOffset(void) { return ATON_STRSWITCH_DSTRECBUF01_OFFSET; } /** * Get the address of the DSTRECBUF01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF01 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTRECBUF01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTRECBUF01_ADDR(instance); } /** * Read the content of the DSTRECBUF01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF01 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTRECBUF01 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get(uint32_t instance) { return ATON_STRSWITCH_DSTRECBUF01_GET(instance); } /** * Write the content of the DSTRECBUF01 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF01 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTRECBUF01_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTRECBUF01_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTRECBUF01 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_S 0 /** Check whether access to the EN0 field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_EN0_P 0 /** Read the content of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN0_LSB, ATON_STRSWITCH_DSTRECBUF01_EN0_W) /** Modify the content of the EN0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN0_LSB, ATON_STRSWITCH_DSTRECBUF01_EN0_W, DATA) /** * Get the description of the EN0 field of DSTRECBUF01 register. * * \return the description of the EN0 field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_EN0_DESC; } /** * Read the content of the EN0 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the EN0 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTRECBUF01 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK0_P 0 /** Read the content of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK0_W) /** Modify the content of the LINK0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTRECBUF01 register. * * \return the description of the LINK0 field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the LINK0 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTRECBUF01 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR0_P 0 /** Read the content of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR0_W) /** Modify the content of the FNR0 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTRECBUF01 register. * * \return the description of the FNR0 field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the FNR0 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTRECBUF01 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_S 0 /** Check whether access to the EN1 field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_EN1_P 0 /** Read the content of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN1_LSB, ATON_STRSWITCH_DSTRECBUF01_EN1_W) /** Modify the content of the EN1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_EN1_LSB, ATON_STRSWITCH_DSTRECBUF01_EN1_W, DATA) /** * Get the description of the EN1 field of DSTRECBUF01 register. * * \return the description of the EN1 field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_EN1_DESC; } /** * Read the content of the EN1 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the EN1 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTRECBUF01 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_LINK1_P 0 /** Read the content of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK1_W) /** Modify the content of the LINK1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF01_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTRECBUF01 register. * * \return the description of the LINK1 field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the LINK1 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTRECBUF01 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTRECBUF01 register. * * \return the description of the TICKTYPE field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the TICKTYPE field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTRECBUF01 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTRECBUF01 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTRECBUF01 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF01_FNR1_P 0 /** Read the content of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR1_W) /** Modify the content of the FNR1 field of the DSTRECBUF01 register. */ #define ATON_STRSWITCH_DSTRECBUF01_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF01_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF01_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTRECBUF01 register. * * \return the description of the FNR1 field of DSTRECBUF01 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF01_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF01_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * * \return the content of the FNR1 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF01_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTRECBUF01 register. * * \param[in] reg is the value of the DSTRECBUF01 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTRECBUF01 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF01_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF01_SET_FNR1(reg, data); } /* *************************************************** DSTRECBUF02 register of one of the STRSWITCH Units *************************************************** */ /** Offset of the DSTRECBUF02 register from the base address of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTRECBUF02_OFFSET 0xa8UL /** Reset value of the DSTRECBUF02 register of the STRSWITCH Unit. */ #define ATON_STRSWITCH_DSTRECBUF02_DT \ (ATON_STRSWITCH_DSTRECBUF02_EN0_DT << ATON_STRSWITCH_DSTRECBUF02_EN0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF02_LINK0_DT << ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF02_FNR0_DT << ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB) | \ (ATON_STRSWITCH_DSTRECBUF02_EN1_DT << ATON_STRSWITCH_DSTRECBUF02_EN1_LSB) | \ (ATON_STRSWITCH_DSTRECBUF02_LINK1_DT << ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB) | \ (ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DT << ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB) | \ (ATON_STRSWITCH_DSTRECBUF02_FNR1_DT << ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB) /** Description of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_DESC "Connection to input port 2 of Reconfigurable Buffer 0" /** Address of the DSTRECBUF02 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF02_ADDR(UNIT) (ATON_STRSWITCH_BASE(UNIT) + ATON_STRSWITCH_DSTRECBUF02_OFFSET) /** Get the content of the DSTRECBUF02 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF02_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF02_ADDR(UNIT))) /** Set the content of the DSTRECBUF02 register of one of the STRSWITCH Units. */ #define ATON_STRSWITCH_DSTRECBUF02_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_STRSWITCH_DSTRECBUF02_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DSTRECBUF02 register. * * \return the description of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_GetDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_DESC; } /** * Get the offset of the DSTRECBUF02 register. * * \return the offset of DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_GetOffset(void) { return ATON_STRSWITCH_DSTRECBUF02_OFFSET; } /** * Get the address of the DSTRECBUF02 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF02 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of DSTRECBUF02 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_GetAddr(uint32_t instance) { return ATON_STRSWITCH_DSTRECBUF02_ADDR(instance); } /** * Read the content of the DSTRECBUF02 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF02 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of DSTRECBUF02 register belonging to Unit having index \e instance among the STRSWITCH Units */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get(uint32_t instance) { return ATON_STRSWITCH_DSTRECBUF02_GET(instance); } /** * Write the content of the DSTRECBUF02 register. * * \param[in] instance is the index of the Unit (among the STRSWITCH Units) containing the DSTRECBUF02 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_STRSWITCH_DSTRECBUF02_Set(uint32_t instance, uint32_t data) { ATON_STRSWITCH_DSTRECBUF02_SET(instance, data); } /* --------------------------------------------------------- EN0 field of the DSTRECBUF02 register ---------------------------------------------------------- */ /** Description of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_DESC "Enable context 0" /** Offset of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_LSB 0UL /** Size in bits of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_W (1UL) /** Mask for retrieving the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_DT 0x0UL /** Access rights of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_AC "RW" /** Check whether access to the EN0 field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_S 0 /** Check whether access to the EN0 field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_EN0_P 0 /** Read the content of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_EN0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN0_LSB, ATON_STRSWITCH_DSTRECBUF02_EN0_W) /** Modify the content of the EN0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_EN0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN0_LSB, ATON_STRSWITCH_DSTRECBUF02_EN0_W, DATA) /** * Get the description of the EN0 field of DSTRECBUF02 register. * * \return the description of the EN0 field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_EN0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_EN0_DESC; } /** * Read the content of the EN0 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the EN0 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_EN0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_EN0(reg); } /** * Write the content of the EN0 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN0 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_EN0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_EN0(reg, data); } /* -------------------------------------------------------- LINK0 field of the DSTRECBUF02 register --------------------------------------------------------- */ /** Description of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_DESC "Source port of context 0" /** Offset of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB 1UL /** Size in bits of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_W (5UL) /** Mask for retrieving the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_MASK ATON_FIELD_MASK(1UL, 5UL) /** Reset value of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_DT 0x0UL /** Access rights of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_AC "RW" /** Check whether access to the LINK0 field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_S 0 /** Check whether access to the LINK0 field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK0_P 0 /** Read the content of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_LINK0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK0_W) /** Modify the content of the LINK0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_LINK0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK0_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK0_W, DATA) /** * Get the description of the LINK0 field of DSTRECBUF02 register. * * \return the description of the LINK0 field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_LINK0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_LINK0_DESC; } /** * Read the content of the LINK0 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the LINK0 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_LINK0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_LINK0(reg); } /** * Write the content of the LINK0 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK0 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_LINK0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_LINK0(reg, data); } /* --------------------------------------------------------- FNR0 field of the DSTRECBUF02 register --------------------------------------------------------- */ /** Description of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_DESC "Number of ticks for context 0" /** Offset of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB 8UL /** Size in bits of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_W (8UL) /** Mask for retrieving the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_DT 0x0UL /** Access rights of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_AC "RW" /** Check whether access to the FNR0 field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_S 0 /** Check whether access to the FNR0 field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR0_P 0 /** Read the content of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_FNR0(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR0_W) /** Modify the content of the FNR0 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_FNR0(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR0_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR0_W, DATA) /** * Get the description of the FNR0 field of DSTRECBUF02 register. * * \return the description of the FNR0 field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_FNR0_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_FNR0_DESC; } /** * Read the content of the FNR0 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the FNR0 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_FNR0(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_FNR0(reg); } /** * Write the content of the FNR0 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR0 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_FNR0(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_FNR0(reg, data); } /* --------------------------------------------------------- EN1 field of the DSTRECBUF02 register ---------------------------------------------------------- */ /** Description of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_DESC "Enable context 1" /** Offset of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_LSB 16UL /** Size in bits of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_W (1UL) /** Mask for retrieving the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_DT 0x0UL /** Access rights of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_AC "RW" /** Check whether access to the EN1 field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_S 0 /** Check whether access to the EN1 field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_EN1_P 0 /** Read the content of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_EN1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN1_LSB, ATON_STRSWITCH_DSTRECBUF02_EN1_W) /** Modify the content of the EN1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_EN1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_EN1_LSB, ATON_STRSWITCH_DSTRECBUF02_EN1_W, DATA) /** * Get the description of the EN1 field of DSTRECBUF02 register. * * \return the description of the EN1 field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_EN1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_EN1_DESC; } /** * Read the content of the EN1 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the EN1 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_EN1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_EN1(reg); } /** * Write the content of the EN1 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN1 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_EN1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_EN1(reg, data); } /* -------------------------------------------------------- LINK1 field of the DSTRECBUF02 register --------------------------------------------------------- */ /** Description of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_DESC "Source port of context 1" /** Offset of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB 17UL /** Size in bits of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_W (5UL) /** Mask for retrieving the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_MASK ATON_FIELD_MASK(17UL, 5UL) /** Reset value of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_DT 0x0UL /** Access rights of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_AC "RW" /** Check whether access to the LINK1 field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_S 0 /** Check whether access to the LINK1 field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_LINK1_P 0 /** Read the content of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_LINK1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK1_W) /** Modify the content of the LINK1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_LINK1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_LINK1_LSB, ATON_STRSWITCH_DSTRECBUF02_LINK1_W, DATA) /** * Get the description of the LINK1 field of DSTRECBUF02 register. * * \return the description of the LINK1 field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_LINK1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_LINK1_DESC; } /** * Read the content of the LINK1 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the LINK1 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_LINK1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_LINK1(reg); } /** * Write the content of the LINK1 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 5-bit value that must be written to the field * * \return the new content of the LINK1 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_LINK1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_LINK1(reg, data); } /* ------------------------------------------------------- TICKTYPE field of the DSTRECBUF02 register ------------------------------------------------------- */ /** Description of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DESC "Select context tick type 0:frames, 1:pixels" /** Offset of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB 23UL /** Size in bits of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_W (1UL) /** Mask for retrieving the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_MASK ATON_FIELD_MASK(23UL, 1UL) /** Reset value of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DT 0x0UL /** Access rights of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_AC "RW" /** Check whether access to the TICKTYPE field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_S 0 /** Check whether access to the TICKTYPE field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_P 0 /** Read the content of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_TICKTYPE(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_W) /** Modify the content of the TICKTYPE field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_TICKTYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_LSB, ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_W, DATA) /** * Get the description of the TICKTYPE field of DSTRECBUF02 register. * * \return the description of the TICKTYPE field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_TICKTYPE_DESC; } /** * Read the content of the TICKTYPE field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the TICKTYPE field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_TICKTYPE(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_TICKTYPE(reg); } /** * Write the content of the TICKTYPE field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the TICKTYPE field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_TICKTYPE(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_TICKTYPE(reg, data); } /* --------------------------------------------------------- FNR1 field of the DSTRECBUF02 register --------------------------------------------------------- */ /** Description of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_DESC "Number of ticks for context 1" /** Offset of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB 24UL /** Size in bits of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_W (8UL) /** Mask for retrieving the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_DT 0x0UL /** Access rights of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_AC "RW" /** Check whether access to the FNR1 field of the DSTRECBUF02 register is secured or not. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_S 0 /** Check whether access to the FNR1 field of the DSTRECBUF02 register is privileged or not. */ #define ATON_STRSWITCH_DSTRECBUF02_FNR1_P 0 /** Read the content of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_GET_FNR1(REG) ATON_GET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR1_W) /** Modify the content of the FNR1 field of the DSTRECBUF02 register. */ #define ATON_STRSWITCH_DSTRECBUF02_SET_FNR1(REG, DATA) ATON_SET_FIELD(REG, ATON_STRSWITCH_DSTRECBUF02_FNR1_LSB, ATON_STRSWITCH_DSTRECBUF02_FNR1_W, DATA) /** * Get the description of the FNR1 field of DSTRECBUF02 register. * * \return the description of the FNR1 field of DSTRECBUF02 register */ static inline const int8_t *ATON_STRSWITCH_DSTRECBUF02_FNR1_GetdDesc(void) { return (const int8_t *)ATON_STRSWITCH_DSTRECBUF02_FNR1_DESC; } /** * Read the content of the FNR1 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * * \return the content of the FNR1 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Get_FNR1(uint32_t reg) { return ATON_STRSWITCH_DSTRECBUF02_GET_FNR1(reg); } /** * Write the content of the FNR1 field of the DSTRECBUF02 register. * * \param[in] reg is the value of the DSTRECBUF02 register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FNR1 field belonging to DSTRECBUF02 register */ static inline uint32_t ATON_STRSWITCH_DSTRECBUF02_Set_FNR1(uint32_t reg, uint32_t data) { return ATON_STRSWITCH_DSTRECBUF02_SET_FNR1(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* CONVACC Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of CONVACC Unit instances. */ #define ATON_CONVACC_NUM 4 /** * \name Structures, macros and functions of the CONVACC Units */ /*@{*/ /** * Registers of the CONVACC Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e KFORMAT register (Kernel format). */ uint32_t KFORMAT; /** \e SAMPLE register (Data sampling). */ uint32_t SAMPLE; /** \e DFORMAT register (Data format). */ uint32_t DFORMAT; /** \e FFORMAT register (Feature Data input dimensions). */ uint32_t FFORMAT; /** \e FHCROP register (Horizontal feature data cropping). */ uint32_t FHCROP; /** \e FVCROP register (Vertical feature data cropping). */ uint32_t FVCROP; /** \e KFILT register (Kernel filter). */ uint32_t KFILT; /** \e AFILT register (Accumulator filter). */ uint32_t AFILT; /** \e ZFRAME register (Zero Frame). */ uint32_t ZFRAME; /** \e ITER register (Iteration Control). */ uint32_t ITER; /** \e FSUB register (Feature data subtract). */ uint32_t FSUB; /** \e ZFBIAS register (Zero Frame Bias). */ uint32_t ZFBIAS; } ATON_CONVACC_t; /** Return the pointer to one of the CONVACC Units. */ #define ATON_CONVACC(UNIT) ((ATON_CONVACC_t *)(intptr_t)ATON_CONVACC_BASE(UNIT)) /** Name of one of the CONVACC Units. */ #define ATON_CONVACC_NAME(UNIT) \ (((UNIT) == 0) ? "CONVACC0" : \ (((UNIT) == 1) ? "CONVACC1" : \ (((UNIT) == 2) ? "CONVACC2" : \ (((UNIT) == 3) ? "CONVACC3" : "")))) /** Version of the CONVACC Units. */ #define ATON_CONVACC_VERSION "5.1" /** Description of one of the CONVACC Units. */ #define ATON_CONVACC_DESC(UNIT) \ (((UNIT) == 0) ? "Convolutional Accelerator 0" : \ (((UNIT) == 1) ? "Convolutional Accelerator 1" : \ (((UNIT) == 2) ? "Convolutional Accelerator 2" : \ (((UNIT) == 3) ? "Convolutional Accelerator 3" : "")))) /** Base address of one of the CONVACC Units. */ #define ATON_CONVACC_BASE(UNIT) \ (ATON_BASE + 0xf000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the CONVACC Units. */ #define ATON_CONVACC_SIZE 0x1000UL /** * Get the name of one of the CONVACC Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 4<\em>) * * \return the name of Unit having index \e instance among the CONVACC Units */ static inline const int8_t *ATON_CONVACC_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"CONVACC0"; break; case 1: str = (const int8_t *)"CONVACC1"; break; case 2: str = (const int8_t *)"CONVACC2"; break; case 3: str = (const int8_t *)"CONVACC3"; break; default: break; } return str; } /** * Get the description of one of the CONVACC Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 4<\em>) * * \return the description of Unit having index \e instance among the CONVACC Units */ static inline const int8_t *ATON_CONVACC_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Convolutional Accelerator 0"; break; case 1: str = (const int8_t *)"Convolutional Accelerator 1"; break; case 2: str = (const int8_t *)"Convolutional Accelerator 2"; break; case 3: str = (const int8_t *)"Convolutional Accelerator 3"; break; default: break; } return str; } /** * Get the version of the CONVACC Units. * * \return the version of the CONVACC Units */ static inline const int8_t *ATON_CONVACC_GetVersion(void) { return (const int8_t *)ATON_CONVACC_VERSION; } /** * Get the base address of one of the CONVACC Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 4<\em>) * * \return the base address of Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_GetBase(uint32_t instance) { return ATON_CONVACC_BASE(instance); } /** * Get the size in bytes of the CONVACC Units. * * \return the size in bytes of the CONVACC Units */ static inline uint32_t ATON_CONVACC_GetSize(void) { return ATON_CONVACC_SIZE; } /* ******************************************************* CTRL register of one of the CONVACC Units ******************************************************** */ /** Offset of the CTRL register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the CONVACC Unit. */ #define ATON_CONVACC_CTRL_DT \ (ATON_CONVACC_CTRL_EN_DT << ATON_CONVACC_CTRL_EN_LSB) | \ (ATON_CONVACC_CTRL_CLR_DT << ATON_CONVACC_CTRL_CLR_LSB) | \ (ATON_CONVACC_CTRL_NOSUM_DT << ATON_CONVACC_CTRL_NOSUM_LSB) | \ (ATON_CONVACC_CTRL_KT1_DT << ATON_CONVACC_CTRL_KT1_LSB) | \ (ATON_CONVACC_CTRL_NO1SUM_DT << ATON_CONVACC_CTRL_NO1SUM_LSB) | \ (ATON_CONVACC_CTRL_SIMD_DT << ATON_CONVACC_CTRL_SIMD_LSB) | \ (ATON_CONVACC_CTRL_AFILTMODE_DT << ATON_CONVACC_CTRL_AFILTMODE_LSB) | \ (ATON_CONVACC_CTRL_GEN1SUM_DT << ATON_CONVACC_CTRL_GEN1SUM_LSB) | \ (ATON_CONVACC_CTRL_FC_DT << ATON_CONVACC_CTRL_FC_LSB) | \ (ATON_CONVACC_CTRL_FC_TSIZE_DT << ATON_CONVACC_CTRL_FC_TSIZE_LSB) | \ (ATON_CONVACC_CTRL_FC_VSIZE_DT << ATON_CONVACC_CTRL_FC_VSIZE_LSB) | \ (ATON_CONVACC_CTRL_FUNSIGNED_DT << ATON_CONVACC_CTRL_FUNSIGNED_LSB) | \ (ATON_CONVACC_CTRL_KUNSIGNED_DT << ATON_CONVACC_CTRL_KUNSIGNED_LSB) | \ (ATON_CONVACC_CTRL_KSETEN_DT << ATON_CONVACC_CTRL_KSETEN_LSB) | \ (ATON_CONVACC_CTRL_FSTAT_DT << ATON_CONVACC_CTRL_FSTAT_LSB) | \ (ATON_CONVACC_CTRL_FSTATLOADED_DT << ATON_CONVACC_CTRL_FSTATLOADED_LSB) | \ (ATON_CONVACC_CTRL_FSTATCLEAR_DT << ATON_CONVACC_CTRL_FSTATCLEAR_LSB) | \ (ATON_CONVACC_CTRL_FSTATOVERF_DT << ATON_CONVACC_CTRL_FSTATOVERF_LSB) | \ (ATON_CONVACC_CTRL_DEEPMODE_DT << ATON_CONVACC_CTRL_DEEPMODE_LSB) | \ (ATON_CONVACC_CTRL_DSS2MODE_DT << ATON_CONVACC_CTRL_DSS2MODE_LSB) | \ (ATON_CONVACC_CTRL_CONFCLR_DT << ATON_CONVACC_CTRL_CONFCLR_LSB) | \ (ATON_CONVACC_CTRL_ILL_DT << ATON_CONVACC_CTRL_ILL_LSB) /** Description of the CTRL register. */ #define ATON_CONVACC_CTRL_DESC "Control register" /** Address of the CTRL register of one of the CONVACC Units. */ #define ATON_CONVACC_CTRL_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_CTRL_OFFSET) /** Get the content of the CTRL register of one of the CONVACC Units. */ #define ATON_CONVACC_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the CONVACC Units. */ #define ATON_CONVACC_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_GetDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_GetOffset(void) { return ATON_CONVACC_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the CTRL register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_CTRL_GetAddr(uint32_t instance) { return ATON_CONVACC_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_CTRL_Get(uint32_t instance) { return ATON_CONVACC_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the CTRL register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_CTRL_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_EN_DESC "Enable the Convolution Accelerator" /** Offset of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_EN_LSB, ATON_CONVACC_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_EN_LSB, ATON_CONVACC_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_EN(uint32_t reg) { return ATON_CONVACC_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_CLR_LSB, ATON_CONVACC_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_CLR_LSB, ATON_CONVACC_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_CLR(uint32_t reg) { return ATON_CONVACC_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_CLR(reg, data); } /* ------------------------------------------------------------ NOSUM field of the CTRL register ------------------------------------------------------------ */ /** Description of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NOSUM_DESC "Do not sum and synchronize with stream link input 2" /** Offset of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NOSUM_LSB 2UL /** Size in bits of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NOSUM_W (1UL) /** Mask for retrieving the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NOSUM_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NOSUM_DT 0x0UL /** Access rights of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NOSUM_AC "RW" /** Check whether access to the NOSUM field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_NOSUM_S 0 /** Check whether access to the NOSUM field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_NOSUM_P 0 /** Read the content of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_NOSUM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_NOSUM_LSB, ATON_CONVACC_CTRL_NOSUM_W) /** Modify the content of the NOSUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_NOSUM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_NOSUM_LSB, ATON_CONVACC_CTRL_NOSUM_W, DATA) /** * Get the description of the NOSUM field of CTRL register. * * \return the description of the NOSUM field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_NOSUM_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_NOSUM_DESC; } /** * Read the content of the NOSUM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the NOSUM field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_NOSUM(uint32_t reg) { return ATON_CONVACC_CTRL_GET_NOSUM(reg); } /** * Write the content of the NOSUM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the NOSUM field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_NOSUM(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_NOSUM(reg, data); } /* ------------------------------------------------------------- KT1 field of the CTRL register ------------------------------------------------------------- */ /** Description of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_KT1_DESC "Load kernel from T1 buffer" /** Offset of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_KT1_LSB 3UL /** Size in bits of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_KT1_W (1UL) /** Mask for retrieving the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_KT1_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_KT1_DT 0x0UL /** Access rights of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_KT1_AC "RW" /** Check whether access to the KT1 field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_KT1_S 0 /** Check whether access to the KT1 field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_KT1_P 0 /** Read the content of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_KT1(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_KT1_LSB, ATON_CONVACC_CTRL_KT1_W) /** Modify the content of the KT1 field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_KT1(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_KT1_LSB, ATON_CONVACC_CTRL_KT1_W, DATA) /** * Get the description of the KT1 field of CTRL register. * * \return the description of the KT1 field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_KT1_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_KT1_DESC; } /** * Read the content of the KT1 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the KT1 field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_KT1(uint32_t reg) { return ATON_CONVACC_CTRL_GET_KT1(reg); } /** * Write the content of the KT1 field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the KT1 field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_KT1(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_KT1(reg, data); } /* ----------------------------------------------------------- NO1SUM field of the CTRL register ------------------------------------------------------------ */ /** Description of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NO1SUM_DESC "No sum and synchronization with stream link input 2 for the first frame" /** Offset of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NO1SUM_LSB 4UL /** Size in bits of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NO1SUM_W (1UL) /** Mask for retrieving the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NO1SUM_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NO1SUM_DT 0x0UL /** Access rights of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_NO1SUM_AC "RW" /** Check whether access to the NO1SUM field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_NO1SUM_S 0 /** Check whether access to the NO1SUM field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_NO1SUM_P 0 /** Read the content of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_NO1SUM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_NO1SUM_LSB, ATON_CONVACC_CTRL_NO1SUM_W) /** Modify the content of the NO1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_NO1SUM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_NO1SUM_LSB, ATON_CONVACC_CTRL_NO1SUM_W, DATA) /** * Get the description of the NO1SUM field of CTRL register. * * \return the description of the NO1SUM field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_NO1SUM_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_NO1SUM_DESC; } /** * Read the content of the NO1SUM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the NO1SUM field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_NO1SUM(uint32_t reg) { return ATON_CONVACC_CTRL_GET_NO1SUM(reg); } /** * Write the content of the NO1SUM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the NO1SUM field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_NO1SUM(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_NO1SUM(reg, data); } /* ------------------------------------------------------------ SIMD field of the CTRL register ------------------------------------------------------------- */ /** Description of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SIMD_DESC "Enable 8x8bit (1) or 16x8bit (2) SIMD mode" /** Offset of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SIMD_LSB 5UL /** Size in bits of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SIMD_W (2UL) /** Mask for retrieving the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SIMD_MASK ATON_FIELD_MASK(5UL, 2UL) /** Reset value of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SIMD_DT 0x0UL /** Access rights of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SIMD_AC "RW" /** Check whether access to the SIMD field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_SIMD_S 0 /** Check whether access to the SIMD field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_SIMD_P 0 /** Read the content of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_SIMD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_SIMD_LSB, ATON_CONVACC_CTRL_SIMD_W) /** Modify the content of the SIMD field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_SIMD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_SIMD_LSB, ATON_CONVACC_CTRL_SIMD_W, DATA) /** * Get the description of the SIMD field of CTRL register. * * \return the description of the SIMD field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_SIMD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_SIMD_DESC; } /** * Read the content of the SIMD field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SIMD field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_SIMD(uint32_t reg) { return ATON_CONVACC_CTRL_GET_SIMD(reg); } /** * Write the content of the SIMD field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the SIMD field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_SIMD(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_SIMD(reg, data); } /* ---------------------------------------------------------- AFILTMODE field of the CTRL register ---------------------------------------------------------- */ /** Description of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_AFILTMODE_DESC "Accumulator port filter mode" /** Offset of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_AFILTMODE_LSB 8UL /** Size in bits of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_AFILTMODE_W (2UL) /** Mask for retrieving the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_AFILTMODE_MASK ATON_FIELD_MASK(8UL, 2UL) /** Reset value of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_AFILTMODE_DT 0x0UL /** Access rights of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_AFILTMODE_AC "RW" /** Check whether access to the AFILTMODE field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_AFILTMODE_S 0 /** Check whether access to the AFILTMODE field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_AFILTMODE_P 0 /** Read the content of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_AFILTMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_AFILTMODE_LSB, ATON_CONVACC_CTRL_AFILTMODE_W) /** Modify the content of the AFILTMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_AFILTMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_AFILTMODE_LSB, ATON_CONVACC_CTRL_AFILTMODE_W, DATA) /** * Get the description of the AFILTMODE field of CTRL register. * * \return the description of the AFILTMODE field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_AFILTMODE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_AFILTMODE_DESC; } /** * Read the content of the AFILTMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the AFILTMODE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_AFILTMODE(uint32_t reg) { return ATON_CONVACC_CTRL_GET_AFILTMODE(reg); } /** * Write the content of the AFILTMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the AFILTMODE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_AFILTMODE(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_AFILTMODE(reg, data); } /* ----------------------------------------------------------- GEN1SUM field of the CTRL register ----------------------------------------------------------- */ /** Description of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GEN1SUM_DESC "Generate first accumulator input frame internally" /** Offset of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GEN1SUM_LSB 10UL /** Size in bits of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GEN1SUM_W (1UL) /** Mask for retrieving the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GEN1SUM_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GEN1SUM_DT 0x0UL /** Access rights of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GEN1SUM_AC "RW" /** Check whether access to the GEN1SUM field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_GEN1SUM_S 0 /** Check whether access to the GEN1SUM field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_GEN1SUM_P 0 /** Read the content of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_GEN1SUM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_GEN1SUM_LSB, ATON_CONVACC_CTRL_GEN1SUM_W) /** Modify the content of the GEN1SUM field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_GEN1SUM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_GEN1SUM_LSB, ATON_CONVACC_CTRL_GEN1SUM_W, DATA) /** * Get the description of the GEN1SUM field of CTRL register. * * \return the description of the GEN1SUM field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_GEN1SUM_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_GEN1SUM_DESC; } /** * Read the content of the GEN1SUM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the GEN1SUM field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_GEN1SUM(uint32_t reg) { return ATON_CONVACC_CTRL_GET_GEN1SUM(reg); } /** * Write the content of the GEN1SUM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the GEN1SUM field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_GEN1SUM(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_GEN1SUM(reg, data); } /* ------------------------------------------------------------- FC field of the CTRL register -------------------------------------------------------------- */ /** Description of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_DESC "Run accelerator in fully connected mode" /** Offset of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_LSB 11UL /** Size in bits of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_W (1UL) /** Mask for retrieving the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_DT 0x0UL /** Access rights of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_AC "RW" /** Check whether access to the FC field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FC_S 0 /** Check whether access to the FC field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FC_P 0 /** Read the content of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FC(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FC_LSB, ATON_CONVACC_CTRL_FC_W) /** Modify the content of the FC field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FC(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FC_LSB, ATON_CONVACC_CTRL_FC_W, DATA) /** * Get the description of the FC field of CTRL register. * * \return the description of the FC field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FC_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FC_DESC; } /** * Read the content of the FC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FC field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FC(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FC(reg); } /** * Write the content of the FC field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FC field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FC(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FC(reg, data); } /* ---------------------------------------------------------- FC_TSIZE field of the CTRL register ----------------------------------------------------------- */ /** Description of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_TSIZE_DESC "FC decode table size" /** Offset of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_TSIZE_LSB 12UL /** Size in bits of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_TSIZE_W (4UL) /** Mask for retrieving the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_TSIZE_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_TSIZE_DT 0x0UL /** Access rights of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_TSIZE_AC "RW" /** Check whether access to the FC_TSIZE field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FC_TSIZE_S 0 /** Check whether access to the FC_TSIZE field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FC_TSIZE_P 0 /** Read the content of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FC_TSIZE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FC_TSIZE_LSB, ATON_CONVACC_CTRL_FC_TSIZE_W) /** Modify the content of the FC_TSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FC_TSIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FC_TSIZE_LSB, ATON_CONVACC_CTRL_FC_TSIZE_W, DATA) /** * Get the description of the FC_TSIZE field of CTRL register. * * \return the description of the FC_TSIZE field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FC_TSIZE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FC_TSIZE_DESC; } /** * Read the content of the FC_TSIZE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FC_TSIZE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FC_TSIZE(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FC_TSIZE(reg); } /** * Write the content of the FC_TSIZE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the FC_TSIZE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FC_TSIZE(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FC_TSIZE(reg, data); } /* ---------------------------------------------------------- FC_VSIZE field of the CTRL register ----------------------------------------------------------- */ /** Description of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_VSIZE_DESC "FC vector size" /** Offset of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_VSIZE_LSB 16UL /** Size in bits of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_VSIZE_W (4UL) /** Mask for retrieving the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_VSIZE_MASK ATON_FIELD_MASK(16UL, 4UL) /** Reset value of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_VSIZE_DT 0x0UL /** Access rights of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_FC_VSIZE_AC "RW" /** Check whether access to the FC_VSIZE field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FC_VSIZE_S 0 /** Check whether access to the FC_VSIZE field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FC_VSIZE_P 0 /** Read the content of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FC_VSIZE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FC_VSIZE_LSB, ATON_CONVACC_CTRL_FC_VSIZE_W) /** Modify the content of the FC_VSIZE field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FC_VSIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FC_VSIZE_LSB, ATON_CONVACC_CTRL_FC_VSIZE_W, DATA) /** * Get the description of the FC_VSIZE field of CTRL register. * * \return the description of the FC_VSIZE field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FC_VSIZE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FC_VSIZE_DESC; } /** * Read the content of the FC_VSIZE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FC_VSIZE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FC_VSIZE(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FC_VSIZE(reg); } /** * Write the content of the FC_VSIZE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the FC_VSIZE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FC_VSIZE(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FC_VSIZE(reg, data); } /* ---------------------------------------------------------- FUNSIGNED field of the CTRL register ---------------------------------------------------------- */ /** Description of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FUNSIGNED_DESC "Feature data unsigned" /** Offset of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FUNSIGNED_LSB 20UL /** Size in bits of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FUNSIGNED_W (1UL) /** Mask for retrieving the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FUNSIGNED_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FUNSIGNED_DT 0x0UL /** Access rights of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FUNSIGNED_AC "RW" /** Check whether access to the FUNSIGNED field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FUNSIGNED_S 0 /** Check whether access to the FUNSIGNED field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FUNSIGNED_P 0 /** Read the content of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FUNSIGNED(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FUNSIGNED_LSB, ATON_CONVACC_CTRL_FUNSIGNED_W) /** Modify the content of the FUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FUNSIGNED(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FUNSIGNED_LSB, ATON_CONVACC_CTRL_FUNSIGNED_W, DATA) /** * Get the description of the FUNSIGNED field of CTRL register. * * \return the description of the FUNSIGNED field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FUNSIGNED_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FUNSIGNED_DESC; } /** * Read the content of the FUNSIGNED field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FUNSIGNED field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FUNSIGNED(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FUNSIGNED(reg); } /** * Write the content of the FUNSIGNED field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FUNSIGNED field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FUNSIGNED(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FUNSIGNED(reg, data); } /* ---------------------------------------------------------- KUNSIGNED field of the CTRL register ---------------------------------------------------------- */ /** Description of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_KUNSIGNED_DESC "Kernel data unsigned" /** Offset of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_KUNSIGNED_LSB 21UL /** Size in bits of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_KUNSIGNED_W (1UL) /** Mask for retrieving the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_KUNSIGNED_MASK ATON_FIELD_MASK(21UL, 1UL) /** Reset value of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_KUNSIGNED_DT 0x0UL /** Access rights of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_KUNSIGNED_AC "RW" /** Check whether access to the KUNSIGNED field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_KUNSIGNED_S 0 /** Check whether access to the KUNSIGNED field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_KUNSIGNED_P 0 /** Read the content of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_KUNSIGNED(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_KUNSIGNED_LSB, ATON_CONVACC_CTRL_KUNSIGNED_W) /** Modify the content of the KUNSIGNED field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_KUNSIGNED(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_KUNSIGNED_LSB, ATON_CONVACC_CTRL_KUNSIGNED_W, DATA) /** * Get the description of the KUNSIGNED field of CTRL register. * * \return the description of the KUNSIGNED field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_KUNSIGNED_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_KUNSIGNED_DESC; } /** * Read the content of the KUNSIGNED field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the KUNSIGNED field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_KUNSIGNED(uint32_t reg) { return ATON_CONVACC_CTRL_GET_KUNSIGNED(reg); } /** * Write the content of the KUNSIGNED field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the KUNSIGNED field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_KUNSIGNED(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_KUNSIGNED(reg, data); } /* ----------------------------------------------------------- KSETEN field of the CTRL register ------------------------------------------------------------ */ /** Description of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_KSETEN_DESC "Enable kernel set 0 (bit 0) or 1 (bit 1) if KT1 is 1, otherwise select byte 1 (0), byte 2 (1), byte 3 (2) or all bytes (Deep1x1 mode only) (3) of kernel stream in SIMD mode " /** Offset of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_KSETEN_LSB 22UL /** Size in bits of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_KSETEN_W (2UL) /** Mask for retrieving the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_KSETEN_MASK ATON_FIELD_MASK(22UL, 2UL) /** Reset value of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_KSETEN_DT 0x0UL /** Access rights of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_KSETEN_AC "RW" /** Check whether access to the KSETEN field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_KSETEN_S 0 /** Check whether access to the KSETEN field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_KSETEN_P 0 /** Read the content of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_KSETEN(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_KSETEN_LSB, ATON_CONVACC_CTRL_KSETEN_W) /** Modify the content of the KSETEN field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_KSETEN(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_KSETEN_LSB, ATON_CONVACC_CTRL_KSETEN_W, DATA) /** * Get the description of the KSETEN field of CTRL register. * * \return the description of the KSETEN field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_KSETEN_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_KSETEN_DESC; } /** * Read the content of the KSETEN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the KSETEN field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_KSETEN(uint32_t reg) { return ATON_CONVACC_CTRL_GET_KSETEN(reg); } /** * Write the content of the KSETEN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the KSETEN field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_KSETEN(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_KSETEN(reg, data); } /* ------------------------------------------------------------ FSTAT field of the CTRL register ------------------------------------------------------------ */ /** Description of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTAT_DESC "Feature data stationary" /** Offset of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTAT_LSB 24UL /** Size in bits of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTAT_W (1UL) /** Mask for retrieving the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTAT_MASK ATON_FIELD_MASK(24UL, 1UL) /** Reset value of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTAT_DT 0x0UL /** Access rights of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTAT_AC "RW" /** Check whether access to the FSTAT field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FSTAT_S 0 /** Check whether access to the FSTAT field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FSTAT_P 0 /** Read the content of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FSTAT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTAT_LSB, ATON_CONVACC_CTRL_FSTAT_W) /** Modify the content of the FSTAT field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FSTAT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FSTAT_LSB, ATON_CONVACC_CTRL_FSTAT_W, DATA) /** * Get the description of the FSTAT field of CTRL register. * * \return the description of the FSTAT field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FSTAT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FSTAT_DESC; } /** * Read the content of the FSTAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSTAT field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FSTAT(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FSTAT(reg); } /** * Write the content of the FSTAT field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSTAT field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FSTAT(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FSTAT(reg, data); } /* --------------------------------------------------------- FSTATLOADED field of the CTRL register --------------------------------------------------------- */ /** Description of the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATLOADED_DESC "Feature data stationary loaded" /** Offset of the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATLOADED_LSB 25UL /** Size in bits of the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATLOADED_W (1UL) /** Mask for retrieving the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATLOADED_MASK ATON_FIELD_MASK(25UL, 1UL) /** Reset value of the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATLOADED_DT 0x0UL /** Access rights of the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATLOADED_AC "R" /** Check whether access to the FSTATLOADED field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FSTATLOADED_S 0 /** Check whether access to the FSTATLOADED field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FSTATLOADED_P 0 /** Read the content of the FSTATLOADED field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FSTATLOADED(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTATLOADED_LSB, ATON_CONVACC_CTRL_FSTATLOADED_W) /** * Get the description of the FSTATLOADED field of CTRL register. * * \return the description of the FSTATLOADED field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FSTATLOADED_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FSTATLOADED_DESC; } /** * Read the content of the FSTATLOADED field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSTATLOADED field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FSTATLOADED(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FSTATLOADED(reg); } /* --------------------------------------------------------- FSTATCLEAR field of the CTRL register ---------------------------------------------------------- */ /** Description of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_DESC "Feature data stationary clear" /** Offset of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_LSB 26UL /** Size in bits of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_W (1UL) /** Mask for retrieving the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_MASK ATON_FIELD_MASK(26UL, 1UL) /** Reset value of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_DT 0x0UL /** Access rights of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_AC "RW" /** Check whether access to the FSTATCLEAR field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_S 0 /** Check whether access to the FSTATCLEAR field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FSTATCLEAR_P 0 /** Read the content of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FSTATCLEAR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTATCLEAR_LSB, ATON_CONVACC_CTRL_FSTATCLEAR_W) /** Modify the content of the FSTATCLEAR field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FSTATCLEAR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FSTATCLEAR_LSB, ATON_CONVACC_CTRL_FSTATCLEAR_W, DATA) /** * Get the description of the FSTATCLEAR field of CTRL register. * * \return the description of the FSTATCLEAR field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FSTATCLEAR_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FSTATCLEAR_DESC; } /** * Read the content of the FSTATCLEAR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSTATCLEAR field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FSTATCLEAR(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FSTATCLEAR(reg); } /** * Write the content of the FSTATCLEAR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSTATCLEAR field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FSTATCLEAR(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FSTATCLEAR(reg, data); } /* --------------------------------------------------------- FSTATOVERF field of the CTRL register ---------------------------------------------------------- */ /** Description of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATOVERF_DESC "Feature data stationary overflow" /** Offset of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATOVERF_LSB 27UL /** Size in bits of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATOVERF_W (1UL) /** Mask for retrieving the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATOVERF_MASK ATON_FIELD_MASK(27UL, 1UL) /** Reset value of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATOVERF_DT 0x0UL /** Access rights of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_FSTATOVERF_AC "RW" /** Check whether access to the FSTATOVERF field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_FSTATOVERF_S 0 /** Check whether access to the FSTATOVERF field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_FSTATOVERF_P 0 /** Read the content of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_FSTATOVERF(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_FSTATOVERF_LSB, ATON_CONVACC_CTRL_FSTATOVERF_W) /** Modify the content of the FSTATOVERF field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_FSTATOVERF(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_FSTATOVERF_LSB, ATON_CONVACC_CTRL_FSTATOVERF_W, DATA) /** * Get the description of the FSTATOVERF field of CTRL register. * * \return the description of the FSTATOVERF field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_FSTATOVERF_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_FSTATOVERF_DESC; } /** * Read the content of the FSTATOVERF field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the FSTATOVERF field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_FSTATOVERF(uint32_t reg) { return ATON_CONVACC_CTRL_GET_FSTATOVERF(reg); } /** * Write the content of the FSTATOVERF field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSTATOVERF field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_FSTATOVERF(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_FSTATOVERF(reg, data); } /* ---------------------------------------------------------- DEEPMODE field of the CTRL register ----------------------------------------------------------- */ /** Description of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DEEPMODE_DESC "Deep1x1 optimized mode" /** Offset of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DEEPMODE_LSB 28UL /** Size in bits of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DEEPMODE_W (1UL) /** Mask for retrieving the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DEEPMODE_MASK ATON_FIELD_MASK(28UL, 1UL) /** Reset value of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DEEPMODE_DT 0x0UL /** Access rights of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DEEPMODE_AC "RW" /** Check whether access to the DEEPMODE field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_DEEPMODE_S 0 /** Check whether access to the DEEPMODE field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_DEEPMODE_P 0 /** Read the content of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_DEEPMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_DEEPMODE_LSB, ATON_CONVACC_CTRL_DEEPMODE_W) /** Modify the content of the DEEPMODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_DEEPMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_DEEPMODE_LSB, ATON_CONVACC_CTRL_DEEPMODE_W, DATA) /** * Get the description of the DEEPMODE field of CTRL register. * * \return the description of the DEEPMODE field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_DEEPMODE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_DEEPMODE_DESC; } /** * Read the content of the DEEPMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DEEPMODE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_DEEPMODE(uint32_t reg) { return ATON_CONVACC_CTRL_GET_DEEPMODE(reg); } /** * Write the content of the DEEPMODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DEEPMODE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_DEEPMODE(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_DEEPMODE(reg, data); } /* ---------------------------------------------------------- DSS2MODE field of the CTRL register ----------------------------------------------------------- */ /** Description of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DSS2MODE_DESC "DSS2 (depth separable stride 2) optimized mode" /** Offset of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DSS2MODE_LSB 29UL /** Size in bits of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DSS2MODE_W (1UL) /** Mask for retrieving the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DSS2MODE_MASK ATON_FIELD_MASK(29UL, 1UL) /** Reset value of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DSS2MODE_DT 0x0UL /** Access rights of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_DSS2MODE_AC "RW" /** Check whether access to the DSS2MODE field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_DSS2MODE_S 0 /** Check whether access to the DSS2MODE field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_DSS2MODE_P 0 /** Read the content of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_DSS2MODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_DSS2MODE_LSB, ATON_CONVACC_CTRL_DSS2MODE_W) /** Modify the content of the DSS2MODE field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_DSS2MODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_DSS2MODE_LSB, ATON_CONVACC_CTRL_DSS2MODE_W, DATA) /** * Get the description of the DSS2MODE field of CTRL register. * * \return the description of the DSS2MODE field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_DSS2MODE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_DSS2MODE_DESC; } /** * Read the content of the DSS2MODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DSS2MODE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_DSS2MODE(uint32_t reg) { return ATON_CONVACC_CTRL_GET_DSS2MODE(reg); } /** * Write the content of the DSS2MODE field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DSS2MODE field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_DSS2MODE(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_DSS2MODE(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CONFCLR_DESC "Clear Configuration registers (auto cleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_CONFCLR_LSB, ATON_CONVACC_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_CONVACC_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_CTRL_CONFCLR_LSB, ATON_CONVACC_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_CONVACC_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_CONVACC_CTRL_SET_CONFCLR(reg, data); } /* ------------------------------------------------------------- ILL field of the CTRL register ------------------------------------------------------------- */ /** Description of the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_ILL_DESC "Illegal configuration" /** Offset of the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_ILL_LSB 31UL /** Size in bits of the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_ILL_W (1UL) /** Mask for retrieving the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_ILL_MASK ATON_FIELD_MASK(31UL, 1UL) /** Reset value of the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_ILL_DT 0x0UL /** Access rights of the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_ILL_AC "R" /** Check whether access to the ILL field of the CTRL register is secured or not. */ #define ATON_CONVACC_CTRL_ILL_S 0 /** Check whether access to the ILL field of the CTRL register is privileged or not. */ #define ATON_CONVACC_CTRL_ILL_P 0 /** Read the content of the ILL field of the CTRL register. */ #define ATON_CONVACC_CTRL_GET_ILL(REG) ATON_GET_FIELD(REG, ATON_CONVACC_CTRL_ILL_LSB, ATON_CONVACC_CTRL_ILL_W) /** * Get the description of the ILL field of CTRL register. * * \return the description of the ILL field of CTRL register */ static inline const int8_t *ATON_CONVACC_CTRL_ILL_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_CTRL_ILL_DESC; } /** * Read the content of the ILL field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ILL field belonging to CTRL register */ static inline uint32_t ATON_CONVACC_CTRL_Get_ILL(uint32_t reg) { return ATON_CONVACC_CTRL_GET_ILL(reg); } /* ****************************************************** VERSION register of one of the CONVACC Units ****************************************************** */ /** Offset of the VERSION register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the CONVACC Unit. */ #define ATON_CONVACC_VERSION_DT \ (ATON_CONVACC_VERSION_TYPE_DT << ATON_CONVACC_VERSION_TYPE_LSB) | \ (ATON_CONVACC_VERSION_MINOR_DT << ATON_CONVACC_VERSION_MINOR_LSB) | \ (ATON_CONVACC_VERSION_MAJOR_DT << ATON_CONVACC_VERSION_MAJOR_LSB) | \ (ATON_CONVACC_VERSION_NRCLUSTER_DT << ATON_CONVACC_VERSION_NRCLUSTER_LSB) /** Description of the VERSION register. */ #define ATON_CONVACC_VERSION_DESC "Version register" /** Address of the VERSION register of one of the CONVACC Units. */ #define ATON_CONVACC_VERSION_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_VERSION_OFFSET) /** Get the content of the VERSION register of one of the CONVACC Units. */ #define ATON_CONVACC_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_CONVACC_VERSION_GetDesc(void) { return (const int8_t *)ATON_CONVACC_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_CONVACC_VERSION_GetOffset(void) { return ATON_CONVACC_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the VERSION register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_VERSION_GetAddr(uint32_t instance) { return ATON_CONVACC_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_VERSION_Get(uint32_t instance) { return ATON_CONVACC_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_TYPE_DT 0x17UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_CONVACC_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_CONVACC_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_CONVACC_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_TYPE_LSB, ATON_CONVACC_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_CONVACC_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_CONVACC_VERSION_Get_TYPE(uint32_t reg) { return ATON_CONVACC_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MINOR_DT 0x1UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_CONVACC_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_CONVACC_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_MINOR_LSB, ATON_CONVACC_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_CONVACC_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_CONVACC_VERSION_Get_MINOR(uint32_t reg) { return ATON_CONVACC_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MAJOR_DT 0x5UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_CONVACC_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_CONVACC_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_CONVACC_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_MAJOR_LSB, ATON_CONVACC_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_CONVACC_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_CONVACC_VERSION_Get_MAJOR(uint32_t reg) { return ATON_CONVACC_VERSION_GET_MAJOR(reg); } /* -------------------------------------------------------- NRCLUSTER field of the VERSION register --------------------------------------------------------- */ /** Description of the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_NRCLUSTER_DESC "Number of MAC clusters" /** Offset of the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_NRCLUSTER_LSB 16UL /** Size in bits of the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_NRCLUSTER_W (4UL) /** Mask for retrieving the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_NRCLUSTER_MASK ATON_FIELD_MASK(16UL, 4UL) /** Reset value of the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_NRCLUSTER_DT 0x6UL /** Access rights of the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_NRCLUSTER_AC "R" /** Check whether access to the NRCLUSTER field of the VERSION register is secured or not. */ #define ATON_CONVACC_VERSION_NRCLUSTER_S 0 /** Check whether access to the NRCLUSTER field of the VERSION register is privileged or not. */ #define ATON_CONVACC_VERSION_NRCLUSTER_P 0 /** Read the content of the NRCLUSTER field of the VERSION register. */ #define ATON_CONVACC_VERSION_GET_NRCLUSTER(REG) ATON_GET_FIELD(REG, ATON_CONVACC_VERSION_NRCLUSTER_LSB, ATON_CONVACC_VERSION_NRCLUSTER_W) /** * Get the description of the NRCLUSTER field of VERSION register. * * \return the description of the NRCLUSTER field of VERSION register */ static inline const int8_t *ATON_CONVACC_VERSION_NRCLUSTER_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_VERSION_NRCLUSTER_DESC; } /** * Read the content of the NRCLUSTER field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the NRCLUSTER field belonging to VERSION register */ static inline uint32_t ATON_CONVACC_VERSION_Get_NRCLUSTER(uint32_t reg) { return ATON_CONVACC_VERSION_GET_NRCLUSTER(reg); } /* ****************************************************** KFORMAT register of one of the CONVACC Units ****************************************************** */ /** Offset of the KFORMAT register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_KFORMAT_OFFSET 0x8UL /** Reset value of the KFORMAT register of the CONVACC Unit. */ #define ATON_CONVACC_KFORMAT_DT \ (ATON_CONVACC_KFORMAT_WIDTH_DT << ATON_CONVACC_KFORMAT_WIDTH_LSB) | \ (ATON_CONVACC_KFORMAT_HEIGHT_DT << ATON_CONVACC_KFORMAT_HEIGHT_LSB) | \ (ATON_CONVACC_KFORMAT_BTCDEPTH_DT << ATON_CONVACC_KFORMAT_BTCDEPTH_LSB) | \ (ATON_CONVACC_KFORMAT_NR_DT << ATON_CONVACC_KFORMAT_NR_LSB) /** Description of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_DESC "Kernel format" /** Address of the KFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_KFORMAT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_KFORMAT_OFFSET) /** Get the content of the KFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_KFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFORMAT_ADDR(UNIT))) /** Set the content of the KFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_KFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFORMAT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KFORMAT register. * * \return the description of KFORMAT register */ static inline const int8_t *ATON_CONVACC_KFORMAT_GetDesc(void) { return (const int8_t *)ATON_CONVACC_KFORMAT_DESC; } /** * Get the offset of the KFORMAT register. * * \return the offset of KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_GetOffset(void) { return ATON_CONVACC_KFORMAT_OFFSET; } /** * Get the address of the KFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFORMAT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of KFORMAT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_KFORMAT_GetAddr(uint32_t instance) { return ATON_CONVACC_KFORMAT_ADDR(instance); } /** * Read the content of the KFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFORMAT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of KFORMAT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_KFORMAT_Get(uint32_t instance) { return ATON_CONVACC_KFORMAT_GET(instance); } /** * Write the content of the KFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFORMAT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_KFORMAT_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_KFORMAT_SET(instance, data); } /* ---------------------------------------------------------- WIDTH field of the KFORMAT register ----------------------------------------------------------- */ /** Description of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_WIDTH_DESC "Kernel width" /** Offset of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_WIDTH_LSB 0UL /** Size in bits of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_WIDTH_W (8UL) /** Mask for retrieving the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_WIDTH_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_WIDTH_DT 0x3UL /** Access rights of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_WIDTH_AC "RW" /** Check whether access to the WIDTH field of the KFORMAT register is secured or not. */ #define ATON_CONVACC_KFORMAT_WIDTH_S 0 /** Check whether access to the WIDTH field of the KFORMAT register is privileged or not. */ #define ATON_CONVACC_KFORMAT_WIDTH_P 0 /** Read the content of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_GET_WIDTH(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_WIDTH_LSB, ATON_CONVACC_KFORMAT_WIDTH_W) /** Modify the content of the WIDTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_SET_WIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_WIDTH_LSB, ATON_CONVACC_KFORMAT_WIDTH_W, DATA) /** * Get the description of the WIDTH field of KFORMAT register. * * \return the description of the WIDTH field of KFORMAT register */ static inline const int8_t *ATON_CONVACC_KFORMAT_WIDTH_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFORMAT_WIDTH_DESC; } /** * Read the content of the WIDTH field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * * \return the content of the WIDTH field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Get_WIDTH(uint32_t reg) { return ATON_CONVACC_KFORMAT_GET_WIDTH(reg); } /** * Write the content of the WIDTH field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the WIDTH field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Set_WIDTH(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFORMAT_SET_WIDTH(reg, data); } /* ---------------------------------------------------------- HEIGHT field of the KFORMAT register ---------------------------------------------------------- */ /** Description of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_HEIGHT_DESC "Kernel height" /** Offset of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_HEIGHT_LSB 8UL /** Size in bits of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_HEIGHT_W (8UL) /** Mask for retrieving the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_HEIGHT_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_HEIGHT_DT 0x3UL /** Access rights of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_HEIGHT_AC "RW" /** Check whether access to the HEIGHT field of the KFORMAT register is secured or not. */ #define ATON_CONVACC_KFORMAT_HEIGHT_S 0 /** Check whether access to the HEIGHT field of the KFORMAT register is privileged or not. */ #define ATON_CONVACC_KFORMAT_HEIGHT_P 0 /** Read the content of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_GET_HEIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_HEIGHT_LSB, ATON_CONVACC_KFORMAT_HEIGHT_W) /** Modify the content of the HEIGHT field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_SET_HEIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_HEIGHT_LSB, ATON_CONVACC_KFORMAT_HEIGHT_W, DATA) /** * Get the description of the HEIGHT field of KFORMAT register. * * \return the description of the HEIGHT field of KFORMAT register */ static inline const int8_t *ATON_CONVACC_KFORMAT_HEIGHT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFORMAT_HEIGHT_DESC; } /** * Read the content of the HEIGHT field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * * \return the content of the HEIGHT field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Get_HEIGHT(uint32_t reg) { return ATON_CONVACC_KFORMAT_GET_HEIGHT(reg); } /** * Write the content of the HEIGHT field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the HEIGHT field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Set_HEIGHT(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFORMAT_SET_HEIGHT(reg, data); } /* --------------------------------------------------------- BTCDEPTH field of the KFORMAT register --------------------------------------------------------- */ /** Description of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_DESC "Batch Depth" /** Offset of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_LSB 16UL /** Size in bits of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_W (8UL) /** Mask for retrieving the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_DT 0x1UL /** Access rights of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_AC "RW" /** Check whether access to the BTCDEPTH field of the KFORMAT register is secured or not. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_S 0 /** Check whether access to the BTCDEPTH field of the KFORMAT register is privileged or not. */ #define ATON_CONVACC_KFORMAT_BTCDEPTH_P 0 /** Read the content of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_GET_BTCDEPTH(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_BTCDEPTH_LSB, ATON_CONVACC_KFORMAT_BTCDEPTH_W) /** Modify the content of the BTCDEPTH field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_SET_BTCDEPTH(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_BTCDEPTH_LSB, ATON_CONVACC_KFORMAT_BTCDEPTH_W, DATA) /** * Get the description of the BTCDEPTH field of KFORMAT register. * * \return the description of the BTCDEPTH field of KFORMAT register */ static inline const int8_t *ATON_CONVACC_KFORMAT_BTCDEPTH_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFORMAT_BTCDEPTH_DESC; } /** * Read the content of the BTCDEPTH field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * * \return the content of the BTCDEPTH field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Get_BTCDEPTH(uint32_t reg) { return ATON_CONVACC_KFORMAT_GET_BTCDEPTH(reg); } /** * Write the content of the BTCDEPTH field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the BTCDEPTH field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Set_BTCDEPTH(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFORMAT_SET_BTCDEPTH(reg, data); } /* ------------------------------------------------------------ NR field of the KFORMAT register ------------------------------------------------------------ */ /** Description of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_NR_DESC "Total number of parallel kernels" /** Offset of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_NR_LSB 24UL /** Size in bits of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_NR_W (8UL) /** Mask for retrieving the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_NR_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_NR_DT 0x1UL /** Access rights of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_NR_AC "RW" /** Check whether access to the NR field of the KFORMAT register is secured or not. */ #define ATON_CONVACC_KFORMAT_NR_S 0 /** Check whether access to the NR field of the KFORMAT register is privileged or not. */ #define ATON_CONVACC_KFORMAT_NR_P 0 /** Read the content of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_GET_NR(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFORMAT_NR_LSB, ATON_CONVACC_KFORMAT_NR_W) /** Modify the content of the NR field of the KFORMAT register. */ #define ATON_CONVACC_KFORMAT_SET_NR(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFORMAT_NR_LSB, ATON_CONVACC_KFORMAT_NR_W, DATA) /** * Get the description of the NR field of KFORMAT register. * * \return the description of the NR field of KFORMAT register */ static inline const int8_t *ATON_CONVACC_KFORMAT_NR_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFORMAT_NR_DESC; } /** * Read the content of the NR field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * * \return the content of the NR field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Get_NR(uint32_t reg) { return ATON_CONVACC_KFORMAT_GET_NR(reg); } /** * Write the content of the NR field of the KFORMAT register. * * \param[in] reg is the value of the KFORMAT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the NR field belonging to KFORMAT register */ static inline uint32_t ATON_CONVACC_KFORMAT_Set_NR(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFORMAT_SET_NR(reg, data); } /* ****************************************************** SAMPLE register of one of the CONVACC Units ******************************************************* */ /** Offset of the SAMPLE register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_SAMPLE_OFFSET 0xcUL /** Reset value of the SAMPLE register of the CONVACC Unit. */ #define ATON_CONVACC_SAMPLE_DT \ (ATON_CONVACC_SAMPLE_LPAD_DT << ATON_CONVACC_SAMPLE_LPAD_LSB) | \ (ATON_CONVACC_SAMPLE_RPAD_DT << ATON_CONVACC_SAMPLE_RPAD_LSB) | \ (ATON_CONVACC_SAMPLE_TPAD_DT << ATON_CONVACC_SAMPLE_TPAD_LSB) | \ (ATON_CONVACC_SAMPLE_BPAD_DT << ATON_CONVACC_SAMPLE_BPAD_LSB) | \ (ATON_CONVACC_SAMPLE_HSTRD_DT << ATON_CONVACC_SAMPLE_HSTRD_LSB) | \ (ATON_CONVACC_SAMPLE_VSTRD_DT << ATON_CONVACC_SAMPLE_VSTRD_LSB) | \ (ATON_CONVACC_SAMPLE_FSTATCNT_DT << ATON_CONVACC_SAMPLE_FSTATCNT_LSB) /** Description of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_DESC "Data sampling" /** Address of the SAMPLE register of one of the CONVACC Units. */ #define ATON_CONVACC_SAMPLE_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_SAMPLE_OFFSET) /** Get the content of the SAMPLE register of one of the CONVACC Units. */ #define ATON_CONVACC_SAMPLE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_SAMPLE_ADDR(UNIT))) /** Set the content of the SAMPLE register of one of the CONVACC Units. */ #define ATON_CONVACC_SAMPLE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_SAMPLE_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of SAMPLE register. * * \return the description of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_GetDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_DESC; } /** * Get the offset of the SAMPLE register. * * \return the offset of SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_GetOffset(void) { return ATON_CONVACC_SAMPLE_OFFSET; } /** * Get the address of the SAMPLE register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the SAMPLE register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of SAMPLE register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_SAMPLE_GetAddr(uint32_t instance) { return ATON_CONVACC_SAMPLE_ADDR(instance); } /** * Read the content of the SAMPLE register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the SAMPLE register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of SAMPLE register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_SAMPLE_Get(uint32_t instance) { return ATON_CONVACC_SAMPLE_GET(instance); } /** * Write the content of the SAMPLE register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the SAMPLE register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_SAMPLE_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_SAMPLE_SET(instance, data); } /* ----------------------------------------------------------- LPAD field of the SAMPLE register ------------------------------------------------------------ */ /** Description of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_LPAD_DESC "Number of vertical left dummy columns" /** Offset of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_LPAD_LSB 0UL /** Size in bits of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_LPAD_W (2UL) /** Mask for retrieving the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_LPAD_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_LPAD_DT 0x0UL /** Access rights of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_LPAD_AC "RW" /** Check whether access to the LPAD field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_LPAD_S 0 /** Check whether access to the LPAD field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_LPAD_P 0 /** Read the content of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_LPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_LPAD_LSB, ATON_CONVACC_SAMPLE_LPAD_W) /** Modify the content of the LPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_LPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_LPAD_LSB, ATON_CONVACC_SAMPLE_LPAD_W, DATA) /** * Get the description of the LPAD field of SAMPLE register. * * \return the description of the LPAD field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_LPAD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_LPAD_DESC; } /** * Read the content of the LPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the LPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_LPAD(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_LPAD(reg); } /** * Write the content of the LPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the LPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_LPAD(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_LPAD(reg, data); } /* ----------------------------------------------------------- RPAD field of the SAMPLE register ------------------------------------------------------------ */ /** Description of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_RPAD_DESC "Number of vertical right dummy columns" /** Offset of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_RPAD_LSB 2UL /** Size in bits of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_RPAD_W (2UL) /** Mask for retrieving the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_RPAD_MASK ATON_FIELD_MASK(2UL, 2UL) /** Reset value of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_RPAD_DT 0x0UL /** Access rights of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_RPAD_AC "RW" /** Check whether access to the RPAD field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_RPAD_S 0 /** Check whether access to the RPAD field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_RPAD_P 0 /** Read the content of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_RPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_RPAD_LSB, ATON_CONVACC_SAMPLE_RPAD_W) /** Modify the content of the RPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_RPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_RPAD_LSB, ATON_CONVACC_SAMPLE_RPAD_W, DATA) /** * Get the description of the RPAD field of SAMPLE register. * * \return the description of the RPAD field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_RPAD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_RPAD_DESC; } /** * Read the content of the RPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the RPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_RPAD(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_RPAD(reg); } /** * Write the content of the RPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the RPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_RPAD(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_RPAD(reg, data); } /* ----------------------------------------------------------- TPAD field of the SAMPLE register ------------------------------------------------------------ */ /** Description of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_TPAD_DESC "Number of horizontal top dummy lines" /** Offset of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_TPAD_LSB 4UL /** Size in bits of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_TPAD_W (2UL) /** Mask for retrieving the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_TPAD_MASK ATON_FIELD_MASK(4UL, 2UL) /** Reset value of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_TPAD_DT 0x0UL /** Access rights of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_TPAD_AC "RW" /** Check whether access to the TPAD field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_TPAD_S 0 /** Check whether access to the TPAD field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_TPAD_P 0 /** Read the content of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_TPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_TPAD_LSB, ATON_CONVACC_SAMPLE_TPAD_W) /** Modify the content of the TPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_TPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_TPAD_LSB, ATON_CONVACC_SAMPLE_TPAD_W, DATA) /** * Get the description of the TPAD field of SAMPLE register. * * \return the description of the TPAD field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_TPAD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_TPAD_DESC; } /** * Read the content of the TPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the TPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_TPAD(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_TPAD(reg); } /** * Write the content of the TPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the TPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_TPAD(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_TPAD(reg, data); } /* ----------------------------------------------------------- BPAD field of the SAMPLE register ------------------------------------------------------------ */ /** Description of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_BPAD_DESC "Number of horizontal bottom dummy lines" /** Offset of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_BPAD_LSB 6UL /** Size in bits of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_BPAD_W (2UL) /** Mask for retrieving the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_BPAD_MASK ATON_FIELD_MASK(6UL, 2UL) /** Reset value of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_BPAD_DT 0x0UL /** Access rights of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_BPAD_AC "RW" /** Check whether access to the BPAD field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_BPAD_S 0 /** Check whether access to the BPAD field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_BPAD_P 0 /** Read the content of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_BPAD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_BPAD_LSB, ATON_CONVACC_SAMPLE_BPAD_W) /** Modify the content of the BPAD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_BPAD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_BPAD_LSB, ATON_CONVACC_SAMPLE_BPAD_W, DATA) /** * Get the description of the BPAD field of SAMPLE register. * * \return the description of the BPAD field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_BPAD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_BPAD_DESC; } /** * Read the content of the BPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the BPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_BPAD(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_BPAD(reg); } /** * Write the content of the BPAD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the BPAD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_BPAD(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_BPAD(reg, data); } /* ----------------------------------------------------------- HSTRD field of the SAMPLE register ----------------------------------------------------------- */ /** Description of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_HSTRD_DESC "Horizontal stride" /** Offset of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_HSTRD_LSB 8UL /** Size in bits of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_HSTRD_W (3UL) /** Mask for retrieving the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_HSTRD_MASK ATON_FIELD_MASK(8UL, 3UL) /** Reset value of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_HSTRD_DT 0x1UL /** Access rights of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_HSTRD_AC "RW" /** Check whether access to the HSTRD field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_HSTRD_S 0 /** Check whether access to the HSTRD field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_HSTRD_P 0 /** Read the content of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_HSTRD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_HSTRD_LSB, ATON_CONVACC_SAMPLE_HSTRD_W) /** Modify the content of the HSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_HSTRD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_HSTRD_LSB, ATON_CONVACC_SAMPLE_HSTRD_W, DATA) /** * Get the description of the HSTRD field of SAMPLE register. * * \return the description of the HSTRD field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_HSTRD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_HSTRD_DESC; } /** * Read the content of the HSTRD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the HSTRD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_HSTRD(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_HSTRD(reg); } /** * Write the content of the HSTRD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the HSTRD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_HSTRD(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_HSTRD(reg, data); } /* ----------------------------------------------------------- VSTRD field of the SAMPLE register ----------------------------------------------------------- */ /** Description of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_VSTRD_DESC "Vertical stride" /** Offset of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_VSTRD_LSB 12UL /** Size in bits of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_VSTRD_W (3UL) /** Mask for retrieving the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_VSTRD_MASK ATON_FIELD_MASK(12UL, 3UL) /** Reset value of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_VSTRD_DT 0x1UL /** Access rights of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_VSTRD_AC "RW" /** Check whether access to the VSTRD field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_VSTRD_S 0 /** Check whether access to the VSTRD field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_VSTRD_P 0 /** Read the content of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_VSTRD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_VSTRD_LSB, ATON_CONVACC_SAMPLE_VSTRD_W) /** Modify the content of the VSTRD field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_VSTRD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_VSTRD_LSB, ATON_CONVACC_SAMPLE_VSTRD_W, DATA) /** * Get the description of the VSTRD field of SAMPLE register. * * \return the description of the VSTRD field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_VSTRD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_VSTRD_DESC; } /** * Read the content of the VSTRD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the VSTRD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_VSTRD(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_VSTRD(reg); } /** * Write the content of the VSTRD field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the VSTRD field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_VSTRD(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_VSTRD(reg, data); } /* --------------------------------------------------------- FSTATCNT field of the SAMPLE register ---------------------------------------------------------- */ /** Description of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_DESC "Number of frames before next reload of feature stationary frame" /** Offset of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_LSB 16UL /** Size in bits of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_W (16UL) /** Mask for retrieving the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_DT 0x0UL /** Access rights of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_AC "RW" /** Check whether access to the FSTATCNT field of the SAMPLE register is secured or not. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_S 0 /** Check whether access to the FSTATCNT field of the SAMPLE register is privileged or not. */ #define ATON_CONVACC_SAMPLE_FSTATCNT_P 0 /** Read the content of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_GET_FSTATCNT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_SAMPLE_FSTATCNT_LSB, ATON_CONVACC_SAMPLE_FSTATCNT_W) /** Modify the content of the FSTATCNT field of the SAMPLE register. */ #define ATON_CONVACC_SAMPLE_SET_FSTATCNT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_SAMPLE_FSTATCNT_LSB, ATON_CONVACC_SAMPLE_FSTATCNT_W, DATA) /** * Get the description of the FSTATCNT field of SAMPLE register. * * \return the description of the FSTATCNT field of SAMPLE register */ static inline const int8_t *ATON_CONVACC_SAMPLE_FSTATCNT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_SAMPLE_FSTATCNT_DESC; } /** * Read the content of the FSTATCNT field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * * \return the content of the FSTATCNT field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Get_FSTATCNT(uint32_t reg) { return ATON_CONVACC_SAMPLE_GET_FSTATCNT(reg); } /** * Write the content of the FSTATCNT field of the SAMPLE register. * * \param[in] reg is the value of the SAMPLE register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FSTATCNT field belonging to SAMPLE register */ static inline uint32_t ATON_CONVACC_SAMPLE_Set_FSTATCNT(uint32_t reg, uint32_t data) { return ATON_CONVACC_SAMPLE_SET_FSTATCNT(reg, data); } /* ****************************************************** DFORMAT register of one of the CONVACC Units ****************************************************** */ /** Offset of the DFORMAT register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_DFORMAT_OFFSET 0x10UL /** Reset value of the DFORMAT register of the CONVACC Unit. */ #define ATON_CONVACC_DFORMAT_DT \ (ATON_CONVACC_DFORMAT_INSHIFT_DT << ATON_CONVACC_DFORMAT_INSHIFT_LSB) | \ (ATON_CONVACC_DFORMAT_FRNDMODE_DT << ATON_CONVACC_DFORMAT_FRNDMODE_LSB) | \ (ATON_CONVACC_DFORMAT_OUTSHIFT_DT << ATON_CONVACC_DFORMAT_OUTSHIFT_LSB) | \ (ATON_CONVACC_DFORMAT_ORNDMODE_DT << ATON_CONVACC_DFORMAT_ORNDMODE_LSB) | \ (ATON_CONVACC_DFORMAT_ROUND_DT << ATON_CONVACC_DFORMAT_ROUND_LSB) | \ (ATON_CONVACC_DFORMAT_SAT_DT << ATON_CONVACC_DFORMAT_SAT_LSB) | \ (ATON_CONVACC_DFORMAT_RAW_DT << ATON_CONVACC_DFORMAT_RAW_LSB) | \ (ATON_CONVACC_DFORMAT_OBYTES_DT << ATON_CONVACC_DFORMAT_OBYTES_LSB) | \ (ATON_CONVACC_DFORMAT_FBYTES_DT << ATON_CONVACC_DFORMAT_FBYTES_LSB) | \ (ATON_CONVACC_DFORMAT_FSHIFT_DT << ATON_CONVACC_DFORMAT_FSHIFT_LSB) | \ (ATON_CONVACC_DFORMAT_FROUND_DT << ATON_CONVACC_DFORMAT_FROUND_LSB) | \ (ATON_CONVACC_DFORMAT_FSAT_DT << ATON_CONVACC_DFORMAT_FSAT_LSB) /** Description of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_DESC "Data format" /** Address of the DFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_DFORMAT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_DFORMAT_OFFSET) /** Get the content of the DFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_DFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_DFORMAT_ADDR(UNIT))) /** Set the content of the DFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_DFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_DFORMAT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DFORMAT register. * * \return the description of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_GetDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_DESC; } /** * Get the offset of the DFORMAT register. * * \return the offset of DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_GetOffset(void) { return ATON_CONVACC_DFORMAT_OFFSET; } /** * Get the address of the DFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the DFORMAT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of DFORMAT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_DFORMAT_GetAddr(uint32_t instance) { return ATON_CONVACC_DFORMAT_ADDR(instance); } /** * Read the content of the DFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the DFORMAT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of DFORMAT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_DFORMAT_Get(uint32_t instance) { return ATON_CONVACC_DFORMAT_GET(instance); } /** * Write the content of the DFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the DFORMAT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_DFORMAT_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_DFORMAT_SET(instance, data); } /* --------------------------------------------------------- INSHIFT field of the DFORMAT register ---------------------------------------------------------- */ /** Description of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_INSHIFT_DESC "Accumulator data input signed left shift" /** Offset of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_INSHIFT_LSB 0UL /** Size in bits of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_INSHIFT_W (6UL) /** Mask for retrieving the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_INSHIFT_MASK ATON_FIELD_MASK(0UL, 6UL) /** Reset value of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_INSHIFT_DT 0x8UL /** Access rights of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_INSHIFT_AC "RW" /** Check whether access to the INSHIFT field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_INSHIFT_S 0 /** Check whether access to the INSHIFT field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_INSHIFT_P 0 /** Read the content of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_INSHIFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_INSHIFT_LSB, ATON_CONVACC_DFORMAT_INSHIFT_W) /** Modify the content of the INSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_INSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_INSHIFT_LSB, ATON_CONVACC_DFORMAT_INSHIFT_W, DATA) /** * Get the description of the INSHIFT field of DFORMAT register. * * \return the description of the INSHIFT field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_INSHIFT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_INSHIFT_DESC; } /** * Read the content of the INSHIFT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the INSHIFT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_INSHIFT(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_INSHIFT(reg); } /** * Write the content of the INSHIFT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the INSHIFT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_INSHIFT(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_INSHIFT(reg, data); } /* --------------------------------------------------------- FRNDMODE field of the DFORMAT register --------------------------------------------------------- */ /** Description of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_DESC "Input feature rounding mode. For more information see section: Rounding and Saturation" /** Offset of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_LSB 6UL /** Size in bits of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_W (2UL) /** Mask for retrieving the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_MASK ATON_FIELD_MASK(6UL, 2UL) /** Reset value of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_DT 0x0UL /** Access rights of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_AC "RW" /** Check whether access to the FRNDMODE field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_S 0 /** Check whether access to the FRNDMODE field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_FRNDMODE_P 0 /** Read the content of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_FRNDMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FRNDMODE_LSB, ATON_CONVACC_DFORMAT_FRNDMODE_W) /** Modify the content of the FRNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_FRNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FRNDMODE_LSB, ATON_CONVACC_DFORMAT_FRNDMODE_W, DATA) /** * Get the description of the FRNDMODE field of DFORMAT register. * * \return the description of the FRNDMODE field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_FRNDMODE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_FRNDMODE_DESC; } /** * Read the content of the FRNDMODE field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the FRNDMODE field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_FRNDMODE(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_FRNDMODE(reg); } /** * Write the content of the FRNDMODE field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FRNDMODE field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_FRNDMODE(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_FRNDMODE(reg, data); } /* --------------------------------------------------------- OUTSHIFT field of the DFORMAT register --------------------------------------------------------- */ /** Description of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_DESC "Result data output signed right shift" /** Offset of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_LSB 8UL /** Size in bits of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_W (6UL) /** Mask for retrieving the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_MASK ATON_FIELD_MASK(8UL, 6UL) /** Reset value of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_DT 0x8UL /** Access rights of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_AC "RW" /** Check whether access to the OUTSHIFT field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_S 0 /** Check whether access to the OUTSHIFT field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_OUTSHIFT_P 0 /** Read the content of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_OUTSHIFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_OUTSHIFT_LSB, ATON_CONVACC_DFORMAT_OUTSHIFT_W) /** Modify the content of the OUTSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_OUTSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_OUTSHIFT_LSB, ATON_CONVACC_DFORMAT_OUTSHIFT_W, DATA) /** * Get the description of the OUTSHIFT field of DFORMAT register. * * \return the description of the OUTSHIFT field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_OUTSHIFT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_OUTSHIFT_DESC; } /** * Read the content of the OUTSHIFT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the OUTSHIFT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_OUTSHIFT(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_OUTSHIFT(reg); } /** * Write the content of the OUTSHIFT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the OUTSHIFT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_OUTSHIFT(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_OUTSHIFT(reg, data); } /* --------------------------------------------------------- ORNDMODE field of the DFORMAT register --------------------------------------------------------- */ /** Description of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_DESC "Output data rounding mode. For more information see section: Rounding and Saturation" /** Offset of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_LSB 14UL /** Size in bits of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_W (2UL) /** Mask for retrieving the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_DT 0x0UL /** Access rights of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_AC "RW" /** Check whether access to the ORNDMODE field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_S 0 /** Check whether access to the ORNDMODE field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_ORNDMODE_P 0 /** Read the content of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_ORNDMODE(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_ORNDMODE_LSB, ATON_CONVACC_DFORMAT_ORNDMODE_W) /** Modify the content of the ORNDMODE field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_ORNDMODE(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_ORNDMODE_LSB, ATON_CONVACC_DFORMAT_ORNDMODE_W, DATA) /** * Get the description of the ORNDMODE field of DFORMAT register. * * \return the description of the ORNDMODE field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_ORNDMODE_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_ORNDMODE_DESC; } /** * Read the content of the ORNDMODE field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the ORNDMODE field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_ORNDMODE(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_ORNDMODE(reg); } /** * Write the content of the ORNDMODE field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ORNDMODE field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_ORNDMODE(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_ORNDMODE(reg, data); } /* ---------------------------------------------------------- ROUND field of the DFORMAT register ----------------------------------------------------------- */ /** Description of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ROUND_DESC "Output data rounding after right shift" /** Offset of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ROUND_LSB 16UL /** Size in bits of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ROUND_W (1UL) /** Mask for retrieving the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ROUND_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ROUND_DT 0x0UL /** Access rights of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_ROUND_AC "RW" /** Check whether access to the ROUND field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_ROUND_S 0 /** Check whether access to the ROUND field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_ROUND_P 0 /** Read the content of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_ROUND(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_ROUND_LSB, ATON_CONVACC_DFORMAT_ROUND_W) /** Modify the content of the ROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_ROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_ROUND_LSB, ATON_CONVACC_DFORMAT_ROUND_W, DATA) /** * Get the description of the ROUND field of DFORMAT register. * * \return the description of the ROUND field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_ROUND_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_ROUND_DESC; } /** * Read the content of the ROUND field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the ROUND field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_ROUND(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_ROUND(reg); } /** * Write the content of the ROUND field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUND field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_ROUND(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_ROUND(reg, data); } /* ----------------------------------------------------------- SAT field of the DFORMAT register ------------------------------------------------------------ */ /** Description of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SAT_DESC "Output saturation" /** Offset of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SAT_LSB 17UL /** Size in bits of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SAT_W (1UL) /** Mask for retrieving the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SAT_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SAT_DT 0x0UL /** Access rights of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SAT_AC "RW" /** Check whether access to the SAT field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_SAT_S 0 /** Check whether access to the SAT field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_SAT_P 0 /** Read the content of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_SAT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_SAT_LSB, ATON_CONVACC_DFORMAT_SAT_W) /** Modify the content of the SAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_SAT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_SAT_LSB, ATON_CONVACC_DFORMAT_SAT_W, DATA) /** * Get the description of the SAT field of DFORMAT register. * * \return the description of the SAT field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_SAT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_SAT_DESC; } /** * Read the content of the SAT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the SAT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_SAT(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_SAT(reg); } /** * Write the content of the SAT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SAT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_SAT(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_SAT(reg, data); } /* ----------------------------------------------------------- RAW field of the DFORMAT register ------------------------------------------------------------ */ /** Description of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_RAW_DESC "Use RAW file output format" /** Offset of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_RAW_LSB 18UL /** Size in bits of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_RAW_W (1UL) /** Mask for retrieving the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_RAW_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_RAW_DT 0x0UL /** Access rights of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_RAW_AC "RW" /** Check whether access to the RAW field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_RAW_S 0 /** Check whether access to the RAW field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_RAW_P 0 /** Read the content of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_RAW(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_RAW_LSB, ATON_CONVACC_DFORMAT_RAW_W) /** Modify the content of the RAW field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_RAW(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_RAW_LSB, ATON_CONVACC_DFORMAT_RAW_W, DATA) /** * Get the description of the RAW field of DFORMAT register. * * \return the description of the RAW field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_RAW_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_RAW_DESC; } /** * Read the content of the RAW field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the RAW field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_RAW(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_RAW(reg); } /** * Write the content of the RAW field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAW field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_RAW(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_RAW(reg, data); } /* ---------------------------------------------------------- OBYTES field of the DFORMAT register ---------------------------------------------------------- */ /** Description of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OBYTES_DESC "Output data width in bytes" /** Offset of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OBYTES_LSB 20UL /** Size in bits of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OBYTES_W (2UL) /** Mask for retrieving the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OBYTES_MASK ATON_FIELD_MASK(20UL, 2UL) /** Reset value of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OBYTES_DT 0x3UL /** Access rights of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_OBYTES_AC "RW" /** Check whether access to the OBYTES field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_OBYTES_S 0 /** Check whether access to the OBYTES field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_OBYTES_P 0 /** Read the content of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_OBYTES(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_OBYTES_LSB, ATON_CONVACC_DFORMAT_OBYTES_W) /** Modify the content of the OBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_OBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_OBYTES_LSB, ATON_CONVACC_DFORMAT_OBYTES_W, DATA) /** * Get the description of the OBYTES field of DFORMAT register. * * \return the description of the OBYTES field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_OBYTES_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_OBYTES_DESC; } /** * Read the content of the OBYTES field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the OBYTES field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_OBYTES(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_OBYTES(reg); } /** * Write the content of the OBYTES field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the OBYTES field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_OBYTES(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_OBYTES(reg, data); } /* ---------------------------------------------------------- FBYTES field of the DFORMAT register ---------------------------------------------------------- */ /** Description of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FBYTES_DESC "Input data width in bytes" /** Offset of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FBYTES_LSB 22UL /** Size in bits of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FBYTES_W (2UL) /** Mask for retrieving the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FBYTES_MASK ATON_FIELD_MASK(22UL, 2UL) /** Reset value of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FBYTES_DT 0x2UL /** Access rights of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FBYTES_AC "RW" /** Check whether access to the FBYTES field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_FBYTES_S 0 /** Check whether access to the FBYTES field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_FBYTES_P 0 /** Read the content of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_FBYTES(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FBYTES_LSB, ATON_CONVACC_DFORMAT_FBYTES_W) /** Modify the content of the FBYTES field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_FBYTES(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FBYTES_LSB, ATON_CONVACC_DFORMAT_FBYTES_W, DATA) /** * Get the description of the FBYTES field of DFORMAT register. * * \return the description of the FBYTES field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_FBYTES_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_FBYTES_DESC; } /** * Read the content of the FBYTES field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the FBYTES field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_FBYTES(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_FBYTES(reg); } /** * Write the content of the FBYTES field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the FBYTES field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_FBYTES(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_FBYTES(reg, data); } /* ---------------------------------------------------------- FSHIFT field of the DFORMAT register ---------------------------------------------------------- */ /** Description of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSHIFT_DESC "Input feature data shift. Range 39:0. No shift 16" /** Offset of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSHIFT_LSB 24UL /** Size in bits of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSHIFT_W (6UL) /** Mask for retrieving the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSHIFT_MASK ATON_FIELD_MASK(24UL, 6UL) /** Reset value of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSHIFT_DT 0x10UL /** Access rights of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSHIFT_AC "RW" /** Check whether access to the FSHIFT field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_FSHIFT_S 0 /** Check whether access to the FSHIFT field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_FSHIFT_P 0 /** Read the content of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_FSHIFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FSHIFT_LSB, ATON_CONVACC_DFORMAT_FSHIFT_W) /** Modify the content of the FSHIFT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_FSHIFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FSHIFT_LSB, ATON_CONVACC_DFORMAT_FSHIFT_W, DATA) /** * Get the description of the FSHIFT field of DFORMAT register. * * \return the description of the FSHIFT field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_FSHIFT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_FSHIFT_DESC; } /** * Read the content of the FSHIFT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the FSHIFT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_FSHIFT(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_FSHIFT(reg); } /** * Write the content of the FSHIFT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 6-bit value that must be written to the field * * \return the new content of the FSHIFT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_FSHIFT(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_FSHIFT(reg, data); } /* ---------------------------------------------------------- FROUND field of the DFORMAT register ---------------------------------------------------------- */ /** Description of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FROUND_DESC "Input feature data rounding" /** Offset of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FROUND_LSB 30UL /** Size in bits of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FROUND_W (1UL) /** Mask for retrieving the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FROUND_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FROUND_DT 0x0UL /** Access rights of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FROUND_AC "RW" /** Check whether access to the FROUND field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_FROUND_S 0 /** Check whether access to the FROUND field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_FROUND_P 0 /** Read the content of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_FROUND(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FROUND_LSB, ATON_CONVACC_DFORMAT_FROUND_W) /** Modify the content of the FROUND field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_FROUND(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FROUND_LSB, ATON_CONVACC_DFORMAT_FROUND_W, DATA) /** * Get the description of the FROUND field of DFORMAT register. * * \return the description of the FROUND field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_FROUND_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_FROUND_DESC; } /** * Read the content of the FROUND field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the FROUND field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_FROUND(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_FROUND(reg); } /** * Write the content of the FROUND field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FROUND field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_FROUND(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_FROUND(reg, data); } /* ----------------------------------------------------------- FSAT field of the DFORMAT register ----------------------------------------------------------- */ /** Description of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSAT_DESC "Input feature data saturation" /** Offset of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSAT_LSB 31UL /** Size in bits of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSAT_W (1UL) /** Mask for retrieving the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSAT_MASK ATON_FIELD_MASK(31UL, 1UL) /** Reset value of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSAT_DT 0x0UL /** Access rights of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_FSAT_AC "RW" /** Check whether access to the FSAT field of the DFORMAT register is secured or not. */ #define ATON_CONVACC_DFORMAT_FSAT_S 0 /** Check whether access to the FSAT field of the DFORMAT register is privileged or not. */ #define ATON_CONVACC_DFORMAT_FSAT_P 0 /** Read the content of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_GET_FSAT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_DFORMAT_FSAT_LSB, ATON_CONVACC_DFORMAT_FSAT_W) /** Modify the content of the FSAT field of the DFORMAT register. */ #define ATON_CONVACC_DFORMAT_SET_FSAT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_DFORMAT_FSAT_LSB, ATON_CONVACC_DFORMAT_FSAT_W, DATA) /** * Get the description of the FSAT field of DFORMAT register. * * \return the description of the FSAT field of DFORMAT register */ static inline const int8_t *ATON_CONVACC_DFORMAT_FSAT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_DFORMAT_FSAT_DESC; } /** * Read the content of the FSAT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the FSAT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Get_FSAT(uint32_t reg) { return ATON_CONVACC_DFORMAT_GET_FSAT(reg); } /** * Write the content of the FSAT field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the FSAT field belonging to DFORMAT register */ static inline uint32_t ATON_CONVACC_DFORMAT_Set_FSAT(uint32_t reg, uint32_t data) { return ATON_CONVACC_DFORMAT_SET_FSAT(reg, data); } /* ****************************************************** FFORMAT register of one of the CONVACC Units ****************************************************** */ /** Offset of the FFORMAT register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_FFORMAT_OFFSET 0x14UL /** Reset value of the FFORMAT register of the CONVACC Unit. */ #define ATON_CONVACC_FFORMAT_DT \ (ATON_CONVACC_FFORMAT_WIDTH_DT << ATON_CONVACC_FFORMAT_WIDTH_LSB) | \ (ATON_CONVACC_FFORMAT_HEIGHT_DT << ATON_CONVACC_FFORMAT_HEIGHT_LSB) /** Description of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_DESC "Feature Data input dimensions" /** Address of the FFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_FFORMAT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FFORMAT_OFFSET) /** Get the content of the FFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_FFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FFORMAT_ADDR(UNIT))) /** Set the content of the FFORMAT register of one of the CONVACC Units. */ #define ATON_CONVACC_FFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FFORMAT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FFORMAT register. * * \return the description of FFORMAT register */ static inline const int8_t *ATON_CONVACC_FFORMAT_GetDesc(void) { return (const int8_t *)ATON_CONVACC_FFORMAT_DESC; } /** * Get the offset of the FFORMAT register. * * \return the offset of FFORMAT register */ static inline uint32_t ATON_CONVACC_FFORMAT_GetOffset(void) { return ATON_CONVACC_FFORMAT_OFFSET; } /** * Get the address of the FFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FFORMAT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of FFORMAT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FFORMAT_GetAddr(uint32_t instance) { return ATON_CONVACC_FFORMAT_ADDR(instance); } /** * Read the content of the FFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FFORMAT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of FFORMAT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FFORMAT_Get(uint32_t instance) { return ATON_CONVACC_FFORMAT_GET(instance); } /** * Write the content of the FFORMAT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FFORMAT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_FFORMAT_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_FFORMAT_SET(instance, data); } /* ---------------------------------------------------------- WIDTH field of the FFORMAT register ----------------------------------------------------------- */ /** Description of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_WIDTH_DESC "Feature data width (automatically updated for raster scan data streams)" /** Offset of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_WIDTH_LSB 0UL /** Size in bits of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_WIDTH_W (16UL) /** Mask for retrieving the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_WIDTH_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_WIDTH_DT 0xffffUL /** Access rights of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_WIDTH_AC "RW" /** Check whether access to the WIDTH field of the FFORMAT register is secured or not. */ #define ATON_CONVACC_FFORMAT_WIDTH_S 0 /** Check whether access to the WIDTH field of the FFORMAT register is privileged or not. */ #define ATON_CONVACC_FFORMAT_WIDTH_P 0 /** Read the content of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_GET_WIDTH(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FFORMAT_WIDTH_LSB, ATON_CONVACC_FFORMAT_WIDTH_W) /** Modify the content of the WIDTH field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_SET_WIDTH(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FFORMAT_WIDTH_LSB, ATON_CONVACC_FFORMAT_WIDTH_W, DATA) /** * Get the description of the WIDTH field of FFORMAT register. * * \return the description of the WIDTH field of FFORMAT register */ static inline const int8_t *ATON_CONVACC_FFORMAT_WIDTH_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FFORMAT_WIDTH_DESC; } /** * Read the content of the WIDTH field of the FFORMAT register. * * \param[in] reg is the value of the FFORMAT register * * \return the content of the WIDTH field belonging to FFORMAT register */ static inline uint32_t ATON_CONVACC_FFORMAT_Get_WIDTH(uint32_t reg) { return ATON_CONVACC_FFORMAT_GET_WIDTH(reg); } /** * Write the content of the WIDTH field of the FFORMAT register. * * \param[in] reg is the value of the FFORMAT register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the WIDTH field belonging to FFORMAT register */ static inline uint32_t ATON_CONVACC_FFORMAT_Set_WIDTH(uint32_t reg, uint32_t data) { return ATON_CONVACC_FFORMAT_SET_WIDTH(reg, data); } /* ---------------------------------------------------------- HEIGHT field of the FFORMAT register ---------------------------------------------------------- */ /** Description of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_HEIGHT_DESC "Feature data height (automatically updated for raster scan data streams)" /** Offset of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_HEIGHT_LSB 16UL /** Size in bits of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_HEIGHT_W (16UL) /** Mask for retrieving the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_HEIGHT_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_HEIGHT_DT 0xffffUL /** Access rights of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_HEIGHT_AC "RW" /** Check whether access to the HEIGHT field of the FFORMAT register is secured or not. */ #define ATON_CONVACC_FFORMAT_HEIGHT_S 0 /** Check whether access to the HEIGHT field of the FFORMAT register is privileged or not. */ #define ATON_CONVACC_FFORMAT_HEIGHT_P 0 /** Read the content of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_GET_HEIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FFORMAT_HEIGHT_LSB, ATON_CONVACC_FFORMAT_HEIGHT_W) /** Modify the content of the HEIGHT field of the FFORMAT register. */ #define ATON_CONVACC_FFORMAT_SET_HEIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FFORMAT_HEIGHT_LSB, ATON_CONVACC_FFORMAT_HEIGHT_W, DATA) /** * Get the description of the HEIGHT field of FFORMAT register. * * \return the description of the HEIGHT field of FFORMAT register */ static inline const int8_t *ATON_CONVACC_FFORMAT_HEIGHT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FFORMAT_HEIGHT_DESC; } /** * Read the content of the HEIGHT field of the FFORMAT register. * * \param[in] reg is the value of the FFORMAT register * * \return the content of the HEIGHT field belonging to FFORMAT register */ static inline uint32_t ATON_CONVACC_FFORMAT_Get_HEIGHT(uint32_t reg) { return ATON_CONVACC_FFORMAT_GET_HEIGHT(reg); } /** * Write the content of the HEIGHT field of the FFORMAT register. * * \param[in] reg is the value of the FFORMAT register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the HEIGHT field belonging to FFORMAT register */ static inline uint32_t ATON_CONVACC_FFORMAT_Set_HEIGHT(uint32_t reg, uint32_t data) { return ATON_CONVACC_FFORMAT_SET_HEIGHT(reg, data); } /* ****************************************************** FHCROP register of one of the CONVACC Units ******************************************************* */ /** Offset of the FHCROP register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_FHCROP_OFFSET 0x18UL /** Reset value of the FHCROP register of the CONVACC Unit. */ #define ATON_CONVACC_FHCROP_DT \ (ATON_CONVACC_FHCROP_LEFT_DT << ATON_CONVACC_FHCROP_LEFT_LSB) | \ (ATON_CONVACC_FHCROP_RIGHT_DT << ATON_CONVACC_FHCROP_RIGHT_LSB) /** Description of the FHCROP register. */ #define ATON_CONVACC_FHCROP_DESC "Horizontal feature data cropping" /** Address of the FHCROP register of one of the CONVACC Units. */ #define ATON_CONVACC_FHCROP_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FHCROP_OFFSET) /** Get the content of the FHCROP register of one of the CONVACC Units. */ #define ATON_CONVACC_FHCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FHCROP_ADDR(UNIT))) /** Set the content of the FHCROP register of one of the CONVACC Units. */ #define ATON_CONVACC_FHCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FHCROP_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FHCROP register. * * \return the description of FHCROP register */ static inline const int8_t *ATON_CONVACC_FHCROP_GetDesc(void) { return (const int8_t *)ATON_CONVACC_FHCROP_DESC; } /** * Get the offset of the FHCROP register. * * \return the offset of FHCROP register */ static inline uint32_t ATON_CONVACC_FHCROP_GetOffset(void) { return ATON_CONVACC_FHCROP_OFFSET; } /** * Get the address of the FHCROP register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FHCROP register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of FHCROP register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FHCROP_GetAddr(uint32_t instance) { return ATON_CONVACC_FHCROP_ADDR(instance); } /** * Read the content of the FHCROP register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FHCROP register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of FHCROP register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FHCROP_Get(uint32_t instance) { return ATON_CONVACC_FHCROP_GET(instance); } /** * Write the content of the FHCROP register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FHCROP register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_FHCROP_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_FHCROP_SET(instance, data); } /* ----------------------------------------------------------- LEFT field of the FHCROP register ------------------------------------------------------------ */ /** Description of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_LEFT_DESC "Left feature data boundary" /** Offset of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_LEFT_LSB 0UL /** Size in bits of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_LEFT_W (16UL) /** Mask for retrieving the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_LEFT_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_LEFT_DT 0x0UL /** Access rights of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_LEFT_AC "RW" /** Check whether access to the LEFT field of the FHCROP register is secured or not. */ #define ATON_CONVACC_FHCROP_LEFT_S 0 /** Check whether access to the LEFT field of the FHCROP register is privileged or not. */ #define ATON_CONVACC_FHCROP_LEFT_P 0 /** Read the content of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_GET_LEFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FHCROP_LEFT_LSB, ATON_CONVACC_FHCROP_LEFT_W) /** Modify the content of the LEFT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_SET_LEFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FHCROP_LEFT_LSB, ATON_CONVACC_FHCROP_LEFT_W, DATA) /** * Get the description of the LEFT field of FHCROP register. * * \return the description of the LEFT field of FHCROP register */ static inline const int8_t *ATON_CONVACC_FHCROP_LEFT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FHCROP_LEFT_DESC; } /** * Read the content of the LEFT field of the FHCROP register. * * \param[in] reg is the value of the FHCROP register * * \return the content of the LEFT field belonging to FHCROP register */ static inline uint32_t ATON_CONVACC_FHCROP_Get_LEFT(uint32_t reg) { return ATON_CONVACC_FHCROP_GET_LEFT(reg); } /** * Write the content of the LEFT field of the FHCROP register. * * \param[in] reg is the value of the FHCROP register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the LEFT field belonging to FHCROP register */ static inline uint32_t ATON_CONVACC_FHCROP_Set_LEFT(uint32_t reg, uint32_t data) { return ATON_CONVACC_FHCROP_SET_LEFT(reg, data); } /* ----------------------------------------------------------- RIGHT field of the FHCROP register ----------------------------------------------------------- */ /** Description of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_RIGHT_DESC "Right feature data boundary" /** Offset of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_RIGHT_LSB 16UL /** Size in bits of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_RIGHT_W (16UL) /** Mask for retrieving the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_RIGHT_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_RIGHT_DT 0xffffUL /** Access rights of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_RIGHT_AC "RW" /** Check whether access to the RIGHT field of the FHCROP register is secured or not. */ #define ATON_CONVACC_FHCROP_RIGHT_S 0 /** Check whether access to the RIGHT field of the FHCROP register is privileged or not. */ #define ATON_CONVACC_FHCROP_RIGHT_P 0 /** Read the content of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_GET_RIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FHCROP_RIGHT_LSB, ATON_CONVACC_FHCROP_RIGHT_W) /** Modify the content of the RIGHT field of the FHCROP register. */ #define ATON_CONVACC_FHCROP_SET_RIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FHCROP_RIGHT_LSB, ATON_CONVACC_FHCROP_RIGHT_W, DATA) /** * Get the description of the RIGHT field of FHCROP register. * * \return the description of the RIGHT field of FHCROP register */ static inline const int8_t *ATON_CONVACC_FHCROP_RIGHT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FHCROP_RIGHT_DESC; } /** * Read the content of the RIGHT field of the FHCROP register. * * \param[in] reg is the value of the FHCROP register * * \return the content of the RIGHT field belonging to FHCROP register */ static inline uint32_t ATON_CONVACC_FHCROP_Get_RIGHT(uint32_t reg) { return ATON_CONVACC_FHCROP_GET_RIGHT(reg); } /** * Write the content of the RIGHT field of the FHCROP register. * * \param[in] reg is the value of the FHCROP register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the RIGHT field belonging to FHCROP register */ static inline uint32_t ATON_CONVACC_FHCROP_Set_RIGHT(uint32_t reg, uint32_t data) { return ATON_CONVACC_FHCROP_SET_RIGHT(reg, data); } /* ****************************************************** FVCROP register of one of the CONVACC Units ******************************************************* */ /** Offset of the FVCROP register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_FVCROP_OFFSET 0x1cUL /** Reset value of the FVCROP register of the CONVACC Unit. */ #define ATON_CONVACC_FVCROP_DT \ (ATON_CONVACC_FVCROP_TOP_DT << ATON_CONVACC_FVCROP_TOP_LSB) | \ (ATON_CONVACC_FVCROP_BOTTOM_DT << ATON_CONVACC_FVCROP_BOTTOM_LSB) /** Description of the FVCROP register. */ #define ATON_CONVACC_FVCROP_DESC "Vertical feature data cropping" /** Address of the FVCROP register of one of the CONVACC Units. */ #define ATON_CONVACC_FVCROP_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FVCROP_OFFSET) /** Get the content of the FVCROP register of one of the CONVACC Units. */ #define ATON_CONVACC_FVCROP_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FVCROP_ADDR(UNIT))) /** Set the content of the FVCROP register of one of the CONVACC Units. */ #define ATON_CONVACC_FVCROP_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FVCROP_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FVCROP register. * * \return the description of FVCROP register */ static inline const int8_t *ATON_CONVACC_FVCROP_GetDesc(void) { return (const int8_t *)ATON_CONVACC_FVCROP_DESC; } /** * Get the offset of the FVCROP register. * * \return the offset of FVCROP register */ static inline uint32_t ATON_CONVACC_FVCROP_GetOffset(void) { return ATON_CONVACC_FVCROP_OFFSET; } /** * Get the address of the FVCROP register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FVCROP register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of FVCROP register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FVCROP_GetAddr(uint32_t instance) { return ATON_CONVACC_FVCROP_ADDR(instance); } /** * Read the content of the FVCROP register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FVCROP register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of FVCROP register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FVCROP_Get(uint32_t instance) { return ATON_CONVACC_FVCROP_GET(instance); } /** * Write the content of the FVCROP register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FVCROP register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_FVCROP_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_FVCROP_SET(instance, data); } /* ------------------------------------------------------------ TOP field of the FVCROP register ------------------------------------------------------------ */ /** Description of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_TOP_DESC "Top feature data boundary" /** Offset of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_TOP_LSB 0UL /** Size in bits of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_TOP_W (16UL) /** Mask for retrieving the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_TOP_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_TOP_DT 0x0UL /** Access rights of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_TOP_AC "RW" /** Check whether access to the TOP field of the FVCROP register is secured or not. */ #define ATON_CONVACC_FVCROP_TOP_S 0 /** Check whether access to the TOP field of the FVCROP register is privileged or not. */ #define ATON_CONVACC_FVCROP_TOP_P 0 /** Read the content of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_GET_TOP(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FVCROP_TOP_LSB, ATON_CONVACC_FVCROP_TOP_W) /** Modify the content of the TOP field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_SET_TOP(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FVCROP_TOP_LSB, ATON_CONVACC_FVCROP_TOP_W, DATA) /** * Get the description of the TOP field of FVCROP register. * * \return the description of the TOP field of FVCROP register */ static inline const int8_t *ATON_CONVACC_FVCROP_TOP_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FVCROP_TOP_DESC; } /** * Read the content of the TOP field of the FVCROP register. * * \param[in] reg is the value of the FVCROP register * * \return the content of the TOP field belonging to FVCROP register */ static inline uint32_t ATON_CONVACC_FVCROP_Get_TOP(uint32_t reg) { return ATON_CONVACC_FVCROP_GET_TOP(reg); } /** * Write the content of the TOP field of the FVCROP register. * * \param[in] reg is the value of the FVCROP register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the TOP field belonging to FVCROP register */ static inline uint32_t ATON_CONVACC_FVCROP_Set_TOP(uint32_t reg, uint32_t data) { return ATON_CONVACC_FVCROP_SET_TOP(reg, data); } /* ---------------------------------------------------------- BOTTOM field of the FVCROP register ----------------------------------------------------------- */ /** Description of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_BOTTOM_DESC "Bottom feature data boundary" /** Offset of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_BOTTOM_LSB 16UL /** Size in bits of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_BOTTOM_W (16UL) /** Mask for retrieving the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_BOTTOM_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_BOTTOM_DT 0xffffUL /** Access rights of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_BOTTOM_AC "RW" /** Check whether access to the BOTTOM field of the FVCROP register is secured or not. */ #define ATON_CONVACC_FVCROP_BOTTOM_S 0 /** Check whether access to the BOTTOM field of the FVCROP register is privileged or not. */ #define ATON_CONVACC_FVCROP_BOTTOM_P 0 /** Read the content of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_GET_BOTTOM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FVCROP_BOTTOM_LSB, ATON_CONVACC_FVCROP_BOTTOM_W) /** Modify the content of the BOTTOM field of the FVCROP register. */ #define ATON_CONVACC_FVCROP_SET_BOTTOM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FVCROP_BOTTOM_LSB, ATON_CONVACC_FVCROP_BOTTOM_W, DATA) /** * Get the description of the BOTTOM field of FVCROP register. * * \return the description of the BOTTOM field of FVCROP register */ static inline const int8_t *ATON_CONVACC_FVCROP_BOTTOM_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FVCROP_BOTTOM_DESC; } /** * Read the content of the BOTTOM field of the FVCROP register. * * \param[in] reg is the value of the FVCROP register * * \return the content of the BOTTOM field belonging to FVCROP register */ static inline uint32_t ATON_CONVACC_FVCROP_Get_BOTTOM(uint32_t reg) { return ATON_CONVACC_FVCROP_GET_BOTTOM(reg); } /** * Write the content of the BOTTOM field of the FVCROP register. * * \param[in] reg is the value of the FVCROP register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the BOTTOM field belonging to FVCROP register */ static inline uint32_t ATON_CONVACC_FVCROP_Set_BOTTOM(uint32_t reg, uint32_t data) { return ATON_CONVACC_FVCROP_SET_BOTTOM(reg, data); } /* ******************************************************* KFILT register of one of the CONVACC Units ******************************************************* */ /** Offset of the KFILT register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_KFILT_OFFSET 0x20UL /** Reset value of the KFILT register of the CONVACC Unit. */ #define ATON_CONVACC_KFILT_DT \ (ATON_CONVACC_KFILT_TOT_DT << ATON_CONVACC_KFILT_TOT_LSB) | \ (ATON_CONVACC_KFILT_FIRST_DT << ATON_CONVACC_KFILT_FIRST_LSB) | \ (ATON_CONVACC_KFILT_LAST_DT << ATON_CONVACC_KFILT_LAST_LSB) | \ (ATON_CONVACC_KFILT_IDX_DT << ATON_CONVACC_KFILT_IDX_LSB) /** Description of the KFILT register. */ #define ATON_CONVACC_KFILT_DESC "Kernel filter" /** Address of the KFILT register of one of the CONVACC Units. */ #define ATON_CONVACC_KFILT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_KFILT_OFFSET) /** Get the content of the KFILT register of one of the CONVACC Units. */ #define ATON_CONVACC_KFILT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFILT_ADDR(UNIT))) /** Set the content of the KFILT register of one of the CONVACC Units. */ #define ATON_CONVACC_KFILT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_KFILT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of KFILT register. * * \return the description of KFILT register */ static inline const int8_t *ATON_CONVACC_KFILT_GetDesc(void) { return (const int8_t *)ATON_CONVACC_KFILT_DESC; } /** * Get the offset of the KFILT register. * * \return the offset of KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_GetOffset(void) { return ATON_CONVACC_KFILT_OFFSET; } /** * Get the address of the KFILT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFILT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of KFILT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_KFILT_GetAddr(uint32_t instance) { return ATON_CONVACC_KFILT_ADDR(instance); } /** * Read the content of the KFILT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFILT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of KFILT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_KFILT_Get(uint32_t instance) { return ATON_CONVACC_KFILT_GET(instance); } /** * Write the content of the KFILT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the KFILT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_KFILT_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_KFILT_SET(instance, data); } /* ------------------------------------------------------------ TOT field of the KFILT register ------------------------------------------------------------- */ /** Description of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_TOT_DESC "Total number of kernels" /** Offset of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_TOT_LSB 0UL /** Size in bits of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_TOT_W (8UL) /** Mask for retrieving the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_TOT_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_TOT_DT 0x1UL /** Access rights of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_TOT_AC "RW" /** Check whether access to the TOT field of the KFILT register is secured or not. */ #define ATON_CONVACC_KFILT_TOT_S 0 /** Check whether access to the TOT field of the KFILT register is privileged or not. */ #define ATON_CONVACC_KFILT_TOT_P 0 /** Read the content of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_GET_TOT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_TOT_LSB, ATON_CONVACC_KFILT_TOT_W) /** Modify the content of the TOT field of the KFILT register. */ #define ATON_CONVACC_KFILT_SET_TOT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFILT_TOT_LSB, ATON_CONVACC_KFILT_TOT_W, DATA) /** * Get the description of the TOT field of KFILT register. * * \return the description of the TOT field of KFILT register */ static inline const int8_t *ATON_CONVACC_KFILT_TOT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFILT_TOT_DESC; } /** * Read the content of the TOT field of the KFILT register. * * \param[in] reg is the value of the KFILT register * * \return the content of the TOT field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Get_TOT(uint32_t reg) { return ATON_CONVACC_KFILT_GET_TOT(reg); } /** * Write the content of the TOT field of the KFILT register. * * \param[in] reg is the value of the KFILT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the TOT field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Set_TOT(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFILT_SET_TOT(reg, data); } /* ----------------------------------------------------------- FIRST field of the KFILT register ------------------------------------------------------------ */ /** Description of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_FIRST_DESC "First kernel" /** Offset of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_FIRST_LSB 8UL /** Size in bits of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_FIRST_W (8UL) /** Mask for retrieving the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_FIRST_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_FIRST_DT 0x0UL /** Access rights of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_FIRST_AC "RW" /** Check whether access to the FIRST field of the KFILT register is secured or not. */ #define ATON_CONVACC_KFILT_FIRST_S 0 /** Check whether access to the FIRST field of the KFILT register is privileged or not. */ #define ATON_CONVACC_KFILT_FIRST_P 0 /** Read the content of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_GET_FIRST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_FIRST_LSB, ATON_CONVACC_KFILT_FIRST_W) /** Modify the content of the FIRST field of the KFILT register. */ #define ATON_CONVACC_KFILT_SET_FIRST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFILT_FIRST_LSB, ATON_CONVACC_KFILT_FIRST_W, DATA) /** * Get the description of the FIRST field of KFILT register. * * \return the description of the FIRST field of KFILT register */ static inline const int8_t *ATON_CONVACC_KFILT_FIRST_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFILT_FIRST_DESC; } /** * Read the content of the FIRST field of the KFILT register. * * \param[in] reg is the value of the KFILT register * * \return the content of the FIRST field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Get_FIRST(uint32_t reg) { return ATON_CONVACC_KFILT_GET_FIRST(reg); } /** * Write the content of the FIRST field of the KFILT register. * * \param[in] reg is the value of the KFILT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FIRST field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Set_FIRST(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFILT_SET_FIRST(reg, data); } /* ------------------------------------------------------------ LAST field of the KFILT register ------------------------------------------------------------ */ /** Description of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_LAST_DESC "Last kernel" /** Offset of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_LAST_LSB 16UL /** Size in bits of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_LAST_W (8UL) /** Mask for retrieving the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_LAST_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_LAST_DT 0x0UL /** Access rights of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_LAST_AC "RW" /** Check whether access to the LAST field of the KFILT register is secured or not. */ #define ATON_CONVACC_KFILT_LAST_S 0 /** Check whether access to the LAST field of the KFILT register is privileged or not. */ #define ATON_CONVACC_KFILT_LAST_P 0 /** Read the content of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_GET_LAST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_LAST_LSB, ATON_CONVACC_KFILT_LAST_W) /** Modify the content of the LAST field of the KFILT register. */ #define ATON_CONVACC_KFILT_SET_LAST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_KFILT_LAST_LSB, ATON_CONVACC_KFILT_LAST_W, DATA) /** * Get the description of the LAST field of KFILT register. * * \return the description of the LAST field of KFILT register */ static inline const int8_t *ATON_CONVACC_KFILT_LAST_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFILT_LAST_DESC; } /** * Read the content of the LAST field of the KFILT register. * * \param[in] reg is the value of the KFILT register * * \return the content of the LAST field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Get_LAST(uint32_t reg) { return ATON_CONVACC_KFILT_GET_LAST(reg); } /** * Write the content of the LAST field of the KFILT register. * * \param[in] reg is the value of the KFILT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the LAST field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Set_LAST(uint32_t reg, uint32_t data) { return ATON_CONVACC_KFILT_SET_LAST(reg, data); } /* ------------------------------------------------------------ IDX field of the KFILT register ------------------------------------------------------------- */ /** Description of the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_IDX_DESC "Current kernel" /** Offset of the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_IDX_LSB 24UL /** Size in bits of the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_IDX_W (8UL) /** Mask for retrieving the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_IDX_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_IDX_DT 0x0UL /** Access rights of the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_IDX_AC "R" /** Check whether access to the IDX field of the KFILT register is secured or not. */ #define ATON_CONVACC_KFILT_IDX_S 0 /** Check whether access to the IDX field of the KFILT register is privileged or not. */ #define ATON_CONVACC_KFILT_IDX_P 0 /** Read the content of the IDX field of the KFILT register. */ #define ATON_CONVACC_KFILT_GET_IDX(REG) ATON_GET_FIELD(REG, ATON_CONVACC_KFILT_IDX_LSB, ATON_CONVACC_KFILT_IDX_W) /** * Get the description of the IDX field of KFILT register. * * \return the description of the IDX field of KFILT register */ static inline const int8_t *ATON_CONVACC_KFILT_IDX_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_KFILT_IDX_DESC; } /** * Read the content of the IDX field of the KFILT register. * * \param[in] reg is the value of the KFILT register * * \return the content of the IDX field belonging to KFILT register */ static inline uint32_t ATON_CONVACC_KFILT_Get_IDX(uint32_t reg) { return ATON_CONVACC_KFILT_GET_IDX(reg); } /* ******************************************************* AFILT register of one of the CONVACC Units ******************************************************* */ /** Offset of the AFILT register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_AFILT_OFFSET 0x24UL /** Reset value of the AFILT register of the CONVACC Unit. */ #define ATON_CONVACC_AFILT_DT \ (ATON_CONVACC_AFILT_TOT_DT << ATON_CONVACC_AFILT_TOT_LSB) | \ (ATON_CONVACC_AFILT_FIRST_DT << ATON_CONVACC_AFILT_FIRST_LSB) | \ (ATON_CONVACC_AFILT_LAST_DT << ATON_CONVACC_AFILT_LAST_LSB) | \ (ATON_CONVACC_AFILT_IDX_DT << ATON_CONVACC_AFILT_IDX_LSB) /** Description of the AFILT register. */ #define ATON_CONVACC_AFILT_DESC "Accumulator filter" /** Address of the AFILT register of one of the CONVACC Units. */ #define ATON_CONVACC_AFILT_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_AFILT_OFFSET) /** Get the content of the AFILT register of one of the CONVACC Units. */ #define ATON_CONVACC_AFILT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_AFILT_ADDR(UNIT))) /** Set the content of the AFILT register of one of the CONVACC Units. */ #define ATON_CONVACC_AFILT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_AFILT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of AFILT register. * * \return the description of AFILT register */ static inline const int8_t *ATON_CONVACC_AFILT_GetDesc(void) { return (const int8_t *)ATON_CONVACC_AFILT_DESC; } /** * Get the offset of the AFILT register. * * \return the offset of AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_GetOffset(void) { return ATON_CONVACC_AFILT_OFFSET; } /** * Get the address of the AFILT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the AFILT register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of AFILT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_AFILT_GetAddr(uint32_t instance) { return ATON_CONVACC_AFILT_ADDR(instance); } /** * Read the content of the AFILT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the AFILT register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of AFILT register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_AFILT_Get(uint32_t instance) { return ATON_CONVACC_AFILT_GET(instance); } /** * Write the content of the AFILT register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the AFILT register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_AFILT_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_AFILT_SET(instance, data); } /* ------------------------------------------------------------ TOT field of the AFILT register ------------------------------------------------------------- */ /** Description of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_TOT_DESC "Total number of accumulation tensors" /** Offset of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_TOT_LSB 0UL /** Size in bits of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_TOT_W (8UL) /** Mask for retrieving the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_TOT_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_TOT_DT 0x1UL /** Access rights of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_TOT_AC "RW" /** Check whether access to the TOT field of the AFILT register is secured or not. */ #define ATON_CONVACC_AFILT_TOT_S 0 /** Check whether access to the TOT field of the AFILT register is privileged or not. */ #define ATON_CONVACC_AFILT_TOT_P 0 /** Read the content of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_GET_TOT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_TOT_LSB, ATON_CONVACC_AFILT_TOT_W) /** Modify the content of the TOT field of the AFILT register. */ #define ATON_CONVACC_AFILT_SET_TOT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_AFILT_TOT_LSB, ATON_CONVACC_AFILT_TOT_W, DATA) /** * Get the description of the TOT field of AFILT register. * * \return the description of the TOT field of AFILT register */ static inline const int8_t *ATON_CONVACC_AFILT_TOT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_AFILT_TOT_DESC; } /** * Read the content of the TOT field of the AFILT register. * * \param[in] reg is the value of the AFILT register * * \return the content of the TOT field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Get_TOT(uint32_t reg) { return ATON_CONVACC_AFILT_GET_TOT(reg); } /** * Write the content of the TOT field of the AFILT register. * * \param[in] reg is the value of the AFILT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the TOT field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Set_TOT(uint32_t reg, uint32_t data) { return ATON_CONVACC_AFILT_SET_TOT(reg, data); } /* ----------------------------------------------------------- FIRST field of the AFILT register ------------------------------------------------------------ */ /** Description of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_FIRST_DESC "First accumulation tensor" /** Offset of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_FIRST_LSB 8UL /** Size in bits of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_FIRST_W (8UL) /** Mask for retrieving the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_FIRST_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_FIRST_DT 0x0UL /** Access rights of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_FIRST_AC "RW" /** Check whether access to the FIRST field of the AFILT register is secured or not. */ #define ATON_CONVACC_AFILT_FIRST_S 0 /** Check whether access to the FIRST field of the AFILT register is privileged or not. */ #define ATON_CONVACC_AFILT_FIRST_P 0 /** Read the content of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_GET_FIRST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_FIRST_LSB, ATON_CONVACC_AFILT_FIRST_W) /** Modify the content of the FIRST field of the AFILT register. */ #define ATON_CONVACC_AFILT_SET_FIRST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_AFILT_FIRST_LSB, ATON_CONVACC_AFILT_FIRST_W, DATA) /** * Get the description of the FIRST field of AFILT register. * * \return the description of the FIRST field of AFILT register */ static inline const int8_t *ATON_CONVACC_AFILT_FIRST_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_AFILT_FIRST_DESC; } /** * Read the content of the FIRST field of the AFILT register. * * \param[in] reg is the value of the AFILT register * * \return the content of the FIRST field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Get_FIRST(uint32_t reg) { return ATON_CONVACC_AFILT_GET_FIRST(reg); } /** * Write the content of the FIRST field of the AFILT register. * * \param[in] reg is the value of the AFILT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the FIRST field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Set_FIRST(uint32_t reg, uint32_t data) { return ATON_CONVACC_AFILT_SET_FIRST(reg, data); } /* ------------------------------------------------------------ LAST field of the AFILT register ------------------------------------------------------------ */ /** Description of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_LAST_DESC "Last accumulation tensor" /** Offset of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_LAST_LSB 16UL /** Size in bits of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_LAST_W (8UL) /** Mask for retrieving the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_LAST_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_LAST_DT 0x0UL /** Access rights of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_LAST_AC "RW" /** Check whether access to the LAST field of the AFILT register is secured or not. */ #define ATON_CONVACC_AFILT_LAST_S 0 /** Check whether access to the LAST field of the AFILT register is privileged or not. */ #define ATON_CONVACC_AFILT_LAST_P 0 /** Read the content of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_GET_LAST(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_LAST_LSB, ATON_CONVACC_AFILT_LAST_W) /** Modify the content of the LAST field of the AFILT register. */ #define ATON_CONVACC_AFILT_SET_LAST(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_AFILT_LAST_LSB, ATON_CONVACC_AFILT_LAST_W, DATA) /** * Get the description of the LAST field of AFILT register. * * \return the description of the LAST field of AFILT register */ static inline const int8_t *ATON_CONVACC_AFILT_LAST_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_AFILT_LAST_DESC; } /** * Read the content of the LAST field of the AFILT register. * * \param[in] reg is the value of the AFILT register * * \return the content of the LAST field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Get_LAST(uint32_t reg) { return ATON_CONVACC_AFILT_GET_LAST(reg); } /** * Write the content of the LAST field of the AFILT register. * * \param[in] reg is the value of the AFILT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the LAST field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Set_LAST(uint32_t reg, uint32_t data) { return ATON_CONVACC_AFILT_SET_LAST(reg, data); } /* ------------------------------------------------------------ IDX field of the AFILT register ------------------------------------------------------------- */ /** Description of the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_IDX_DESC "Current accumulation tensor" /** Offset of the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_IDX_LSB 24UL /** Size in bits of the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_IDX_W (8UL) /** Mask for retrieving the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_IDX_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_IDX_DT 0x0UL /** Access rights of the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_IDX_AC "R" /** Check whether access to the IDX field of the AFILT register is secured or not. */ #define ATON_CONVACC_AFILT_IDX_S 0 /** Check whether access to the IDX field of the AFILT register is privileged or not. */ #define ATON_CONVACC_AFILT_IDX_P 0 /** Read the content of the IDX field of the AFILT register. */ #define ATON_CONVACC_AFILT_GET_IDX(REG) ATON_GET_FIELD(REG, ATON_CONVACC_AFILT_IDX_LSB, ATON_CONVACC_AFILT_IDX_W) /** * Get the description of the IDX field of AFILT register. * * \return the description of the IDX field of AFILT register */ static inline const int8_t *ATON_CONVACC_AFILT_IDX_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_AFILT_IDX_DESC; } /** * Read the content of the IDX field of the AFILT register. * * \param[in] reg is the value of the AFILT register * * \return the content of the IDX field belonging to AFILT register */ static inline uint32_t ATON_CONVACC_AFILT_Get_IDX(uint32_t reg) { return ATON_CONVACC_AFILT_GET_IDX(reg); } /* ****************************************************** ZFRAME register of one of the CONVACC Units ******************************************************* */ /** Offset of the ZFRAME register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_ZFRAME_OFFSET 0x28UL /** Reset value of the ZFRAME register of the CONVACC Unit. */ #define ATON_CONVACC_ZFRAME_DT \ (ATON_CONVACC_ZFRAME_LEFT_DT << ATON_CONVACC_ZFRAME_LEFT_LSB) | \ (ATON_CONVACC_ZFRAME_RIGHT_DT << ATON_CONVACC_ZFRAME_RIGHT_LSB) | \ (ATON_CONVACC_ZFRAME_TOP_DT << ATON_CONVACC_ZFRAME_TOP_LSB) | \ (ATON_CONVACC_ZFRAME_BOTTOM_DT << ATON_CONVACC_ZFRAME_BOTTOM_LSB) /** Description of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_DESC "Zero Frame" /** Address of the ZFRAME register of one of the CONVACC Units. */ #define ATON_CONVACC_ZFRAME_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_ZFRAME_OFFSET) /** Get the content of the ZFRAME register of one of the CONVACC Units. */ #define ATON_CONVACC_ZFRAME_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFRAME_ADDR(UNIT))) /** Set the content of the ZFRAME register of one of the CONVACC Units. */ #define ATON_CONVACC_ZFRAME_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFRAME_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ZFRAME register. * * \return the description of ZFRAME register */ static inline const int8_t *ATON_CONVACC_ZFRAME_GetDesc(void) { return (const int8_t *)ATON_CONVACC_ZFRAME_DESC; } /** * Get the offset of the ZFRAME register. * * \return the offset of ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_GetOffset(void) { return ATON_CONVACC_ZFRAME_OFFSET; } /** * Get the address of the ZFRAME register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFRAME register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of ZFRAME register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_ZFRAME_GetAddr(uint32_t instance) { return ATON_CONVACC_ZFRAME_ADDR(instance); } /** * Read the content of the ZFRAME register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFRAME register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of ZFRAME register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_ZFRAME_Get(uint32_t instance) { return ATON_CONVACC_ZFRAME_GET(instance); } /** * Write the content of the ZFRAME register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFRAME register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_ZFRAME_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_ZFRAME_SET(instance, data); } /* ----------------------------------------------------------- LEFT field of the ZFRAME register ------------------------------------------------------------ */ /** Description of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_LEFT_DESC "Width of left zero frame" /** Offset of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_LEFT_LSB 0UL /** Size in bits of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_LEFT_W (8UL) /** Mask for retrieving the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_LEFT_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_LEFT_DT 0x0UL /** Access rights of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_LEFT_AC "RW" /** Check whether access to the LEFT field of the ZFRAME register is secured or not. */ #define ATON_CONVACC_ZFRAME_LEFT_S 0 /** Check whether access to the LEFT field of the ZFRAME register is privileged or not. */ #define ATON_CONVACC_ZFRAME_LEFT_P 0 /** Read the content of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_GET_LEFT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_LEFT_LSB, ATON_CONVACC_ZFRAME_LEFT_W) /** Modify the content of the LEFT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_SET_LEFT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_LEFT_LSB, ATON_CONVACC_ZFRAME_LEFT_W, DATA) /** * Get the description of the LEFT field of ZFRAME register. * * \return the description of the LEFT field of ZFRAME register */ static inline const int8_t *ATON_CONVACC_ZFRAME_LEFT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ZFRAME_LEFT_DESC; } /** * Read the content of the LEFT field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * * \return the content of the LEFT field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Get_LEFT(uint32_t reg) { return ATON_CONVACC_ZFRAME_GET_LEFT(reg); } /** * Write the content of the LEFT field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the LEFT field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Set_LEFT(uint32_t reg, uint32_t data) { return ATON_CONVACC_ZFRAME_SET_LEFT(reg, data); } /* ----------------------------------------------------------- RIGHT field of the ZFRAME register ----------------------------------------------------------- */ /** Description of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_RIGHT_DESC "Width of right zero frame" /** Offset of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_RIGHT_LSB 8UL /** Size in bits of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_RIGHT_W (8UL) /** Mask for retrieving the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_RIGHT_MASK ATON_FIELD_MASK(8UL, 8UL) /** Reset value of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_RIGHT_DT 0x0UL /** Access rights of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_RIGHT_AC "RW" /** Check whether access to the RIGHT field of the ZFRAME register is secured or not. */ #define ATON_CONVACC_ZFRAME_RIGHT_S 0 /** Check whether access to the RIGHT field of the ZFRAME register is privileged or not. */ #define ATON_CONVACC_ZFRAME_RIGHT_P 0 /** Read the content of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_GET_RIGHT(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_RIGHT_LSB, ATON_CONVACC_ZFRAME_RIGHT_W) /** Modify the content of the RIGHT field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_SET_RIGHT(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_RIGHT_LSB, ATON_CONVACC_ZFRAME_RIGHT_W, DATA) /** * Get the description of the RIGHT field of ZFRAME register. * * \return the description of the RIGHT field of ZFRAME register */ static inline const int8_t *ATON_CONVACC_ZFRAME_RIGHT_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ZFRAME_RIGHT_DESC; } /** * Read the content of the RIGHT field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * * \return the content of the RIGHT field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Get_RIGHT(uint32_t reg) { return ATON_CONVACC_ZFRAME_GET_RIGHT(reg); } /** * Write the content of the RIGHT field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the RIGHT field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Set_RIGHT(uint32_t reg, uint32_t data) { return ATON_CONVACC_ZFRAME_SET_RIGHT(reg, data); } /* ------------------------------------------------------------ TOP field of the ZFRAME register ------------------------------------------------------------ */ /** Description of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_TOP_DESC "Width of top zero frame" /** Offset of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_TOP_LSB 16UL /** Size in bits of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_TOP_W (8UL) /** Mask for retrieving the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_TOP_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_TOP_DT 0x0UL /** Access rights of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_TOP_AC "RW" /** Check whether access to the TOP field of the ZFRAME register is secured or not. */ #define ATON_CONVACC_ZFRAME_TOP_S 0 /** Check whether access to the TOP field of the ZFRAME register is privileged or not. */ #define ATON_CONVACC_ZFRAME_TOP_P 0 /** Read the content of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_GET_TOP(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_TOP_LSB, ATON_CONVACC_ZFRAME_TOP_W) /** Modify the content of the TOP field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_SET_TOP(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_TOP_LSB, ATON_CONVACC_ZFRAME_TOP_W, DATA) /** * Get the description of the TOP field of ZFRAME register. * * \return the description of the TOP field of ZFRAME register */ static inline const int8_t *ATON_CONVACC_ZFRAME_TOP_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ZFRAME_TOP_DESC; } /** * Read the content of the TOP field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * * \return the content of the TOP field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Get_TOP(uint32_t reg) { return ATON_CONVACC_ZFRAME_GET_TOP(reg); } /** * Write the content of the TOP field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the TOP field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Set_TOP(uint32_t reg, uint32_t data) { return ATON_CONVACC_ZFRAME_SET_TOP(reg, data); } /* ---------------------------------------------------------- BOTTOM field of the ZFRAME register ----------------------------------------------------------- */ /** Description of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_BOTTOM_DESC "Width of bottom zero frame" /** Offset of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_BOTTOM_LSB 24UL /** Size in bits of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_BOTTOM_W (8UL) /** Mask for retrieving the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_BOTTOM_MASK ATON_FIELD_MASK(24UL, 8UL) /** Reset value of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_BOTTOM_DT 0x0UL /** Access rights of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_BOTTOM_AC "RW" /** Check whether access to the BOTTOM field of the ZFRAME register is secured or not. */ #define ATON_CONVACC_ZFRAME_BOTTOM_S 0 /** Check whether access to the BOTTOM field of the ZFRAME register is privileged or not. */ #define ATON_CONVACC_ZFRAME_BOTTOM_P 0 /** Read the content of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_GET_BOTTOM(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFRAME_BOTTOM_LSB, ATON_CONVACC_ZFRAME_BOTTOM_W) /** Modify the content of the BOTTOM field of the ZFRAME register. */ #define ATON_CONVACC_ZFRAME_SET_BOTTOM(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFRAME_BOTTOM_LSB, ATON_CONVACC_ZFRAME_BOTTOM_W, DATA) /** * Get the description of the BOTTOM field of ZFRAME register. * * \return the description of the BOTTOM field of ZFRAME register */ static inline const int8_t *ATON_CONVACC_ZFRAME_BOTTOM_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ZFRAME_BOTTOM_DESC; } /** * Read the content of the BOTTOM field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * * \return the content of the BOTTOM field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Get_BOTTOM(uint32_t reg) { return ATON_CONVACC_ZFRAME_GET_BOTTOM(reg); } /** * Write the content of the BOTTOM field of the ZFRAME register. * * \param[in] reg is the value of the ZFRAME register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the BOTTOM field belonging to ZFRAME register */ static inline uint32_t ATON_CONVACC_ZFRAME_Set_BOTTOM(uint32_t reg, uint32_t data) { return ATON_CONVACC_ZFRAME_SET_BOTTOM(reg, data); } /* ******************************************************* ITER register of one of the CONVACC Units ******************************************************** */ /** Offset of the ITER register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_ITER_OFFSET 0x2cUL /** Reset value of the ITER register of the CONVACC Unit. */ #define ATON_CONVACC_ITER_DT \ (ATON_CONVACC_ITER_PERIOD_DT << ATON_CONVACC_ITER_PERIOD_LSB) | \ (ATON_CONVACC_ITER_NUMBER_DT << ATON_CONVACC_ITER_NUMBER_LSB) | \ (ATON_CONVACC_ITER_OFFSET_DT << ATON_CONVACC_ITER_OFFSET_LSB) | \ (ATON_CONVACC_ITER_IDX_DT << ATON_CONVACC_ITER_IDX_LSB) /** Description of the ITER register. */ #define ATON_CONVACC_ITER_DESC "Iteration Control" /** Address of the ITER register of one of the CONVACC Units. */ #define ATON_CONVACC_ITER_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_ITER_OFFSET) /** Get the content of the ITER register of one of the CONVACC Units. */ #define ATON_CONVACC_ITER_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ITER_ADDR(UNIT))) /** Set the content of the ITER register of one of the CONVACC Units. */ #define ATON_CONVACC_ITER_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ITER_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ITER register. * * \return the description of ITER register */ static inline const int8_t *ATON_CONVACC_ITER_GetDesc(void) { return (const int8_t *)ATON_CONVACC_ITER_DESC; } /** * Get the offset of the ITER register. * * \return the offset of ITER register */ static inline uint32_t ATON_CONVACC_ITER_GetOffset(void) { return ATON_CONVACC_ITER_OFFSET; } /** * Get the address of the ITER register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ITER register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of ITER register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_ITER_GetAddr(uint32_t instance) { return ATON_CONVACC_ITER_ADDR(instance); } /** * Read the content of the ITER register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ITER register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of ITER register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_ITER_Get(uint32_t instance) { return ATON_CONVACC_ITER_GET(instance); } /** * Write the content of the ITER register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ITER register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_ITER_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_ITER_SET(instance, data); } /* ----------------------------------------------------------- PERIOD field of the ITER register ------------------------------------------------------------ */ /** Description of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_PERIOD_DESC "Iteration period" /** Offset of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_PERIOD_LSB 0UL /** Size in bits of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_PERIOD_W (16UL) /** Mask for retrieving the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_PERIOD_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_PERIOD_DT 0x0UL /** Access rights of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_PERIOD_AC "RW" /** Check whether access to the PERIOD field of the ITER register is secured or not. */ #define ATON_CONVACC_ITER_PERIOD_S 0 /** Check whether access to the PERIOD field of the ITER register is privileged or not. */ #define ATON_CONVACC_ITER_PERIOD_P 0 /** Read the content of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_GET_PERIOD(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_PERIOD_LSB, ATON_CONVACC_ITER_PERIOD_W) /** Modify the content of the PERIOD field of the ITER register. */ #define ATON_CONVACC_ITER_SET_PERIOD(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ITER_PERIOD_LSB, ATON_CONVACC_ITER_PERIOD_W, DATA) /** * Get the description of the PERIOD field of ITER register. * * \return the description of the PERIOD field of ITER register */ static inline const int8_t *ATON_CONVACC_ITER_PERIOD_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ITER_PERIOD_DESC; } /** * Read the content of the PERIOD field of the ITER register. * * \param[in] reg is the value of the ITER register * * \return the content of the PERIOD field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Get_PERIOD(uint32_t reg) { return ATON_CONVACC_ITER_GET_PERIOD(reg); } /** * Write the content of the PERIOD field of the ITER register. * * \param[in] reg is the value of the ITER register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the PERIOD field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Set_PERIOD(uint32_t reg, uint32_t data) { return ATON_CONVACC_ITER_SET_PERIOD(reg, data); } /* ----------------------------------------------------------- NUMBER field of the ITER register ------------------------------------------------------------ */ /** Description of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_NUMBER_DESC "Number of iterations" /** Offset of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_NUMBER_LSB 16UL /** Size in bits of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_NUMBER_W (4UL) /** Mask for retrieving the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_NUMBER_MASK ATON_FIELD_MASK(16UL, 4UL) /** Reset value of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_NUMBER_DT 0x0UL /** Access rights of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_NUMBER_AC "RW" /** Check whether access to the NUMBER field of the ITER register is secured or not. */ #define ATON_CONVACC_ITER_NUMBER_S 0 /** Check whether access to the NUMBER field of the ITER register is privileged or not. */ #define ATON_CONVACC_ITER_NUMBER_P 0 /** Read the content of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_GET_NUMBER(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_NUMBER_LSB, ATON_CONVACC_ITER_NUMBER_W) /** Modify the content of the NUMBER field of the ITER register. */ #define ATON_CONVACC_ITER_SET_NUMBER(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ITER_NUMBER_LSB, ATON_CONVACC_ITER_NUMBER_W, DATA) /** * Get the description of the NUMBER field of ITER register. * * \return the description of the NUMBER field of ITER register */ static inline const int8_t *ATON_CONVACC_ITER_NUMBER_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ITER_NUMBER_DESC; } /** * Read the content of the NUMBER field of the ITER register. * * \param[in] reg is the value of the ITER register * * \return the content of the NUMBER field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Get_NUMBER(uint32_t reg) { return ATON_CONVACC_ITER_GET_NUMBER(reg); } /** * Write the content of the NUMBER field of the ITER register. * * \param[in] reg is the value of the ITER register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the NUMBER field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Set_NUMBER(uint32_t reg, uint32_t data) { return ATON_CONVACC_ITER_SET_NUMBER(reg, data); } /* ----------------------------------------------------------- OFFSET field of the ITER register ------------------------------------------------------------ */ /** Description of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_OFFSET_DESC "Vertical offset per iteration" /** Offset of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_OFFSET_LSB 20UL /** Size in bits of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_OFFSET_W (2UL) /** Mask for retrieving the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_OFFSET_MASK ATON_FIELD_MASK(20UL, 2UL) /** Reset value of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_OFFSET_DT 0x0UL /** Access rights of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_OFFSET_AC "RW" /** Check whether access to the OFFSET field of the ITER register is secured or not. */ #define ATON_CONVACC_ITER_OFFSET_S 0 /** Check whether access to the OFFSET field of the ITER register is privileged or not. */ #define ATON_CONVACC_ITER_OFFSET_P 0 /** Read the content of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_GET_OFFSET(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_OFFSET_LSB, ATON_CONVACC_ITER_OFFSET_W) /** Modify the content of the OFFSET field of the ITER register. */ #define ATON_CONVACC_ITER_SET_OFFSET(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ITER_OFFSET_LSB, ATON_CONVACC_ITER_OFFSET_W, DATA) /** * Get the description of the OFFSET field of ITER register. * * \return the description of the OFFSET field of ITER register */ static inline const int8_t *ATON_CONVACC_ITER_OFFSET_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ITER_OFFSET_DESC; } /** * Read the content of the OFFSET field of the ITER register. * * \param[in] reg is the value of the ITER register * * \return the content of the OFFSET field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Get_OFFSET(uint32_t reg) { return ATON_CONVACC_ITER_GET_OFFSET(reg); } /** * Write the content of the OFFSET field of the ITER register. * * \param[in] reg is the value of the ITER register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the OFFSET field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Set_OFFSET(uint32_t reg, uint32_t data) { return ATON_CONVACC_ITER_SET_OFFSET(reg, data); } /* ------------------------------------------------------------- IDX field of the ITER register ------------------------------------------------------------- */ /** Description of the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_IDX_DESC "Current iteration index" /** Offset of the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_IDX_LSB 24UL /** Size in bits of the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_IDX_W (4UL) /** Mask for retrieving the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_IDX_MASK ATON_FIELD_MASK(24UL, 4UL) /** Reset value of the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_IDX_DT 0x0UL /** Access rights of the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_IDX_AC "R" /** Check whether access to the IDX field of the ITER register is secured or not. */ #define ATON_CONVACC_ITER_IDX_S 0 /** Check whether access to the IDX field of the ITER register is privileged or not. */ #define ATON_CONVACC_ITER_IDX_P 0 /** Read the content of the IDX field of the ITER register. */ #define ATON_CONVACC_ITER_GET_IDX(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ITER_IDX_LSB, ATON_CONVACC_ITER_IDX_W) /** * Get the description of the IDX field of ITER register. * * \return the description of the IDX field of ITER register */ static inline const int8_t *ATON_CONVACC_ITER_IDX_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ITER_IDX_DESC; } /** * Read the content of the IDX field of the ITER register. * * \param[in] reg is the value of the ITER register * * \return the content of the IDX field belonging to ITER register */ static inline uint32_t ATON_CONVACC_ITER_Get_IDX(uint32_t reg) { return ATON_CONVACC_ITER_GET_IDX(reg); } /* ******************************************************* FSUB register of one of the CONVACC Units ******************************************************** */ /** Offset of the FSUB register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_FSUB_OFFSET 0x30UL /** Reset value of the FSUB register of the CONVACC Unit. */ #define ATON_CONVACC_FSUB_DT \ (ATON_CONVACC_FSUB_FSUB_DT << ATON_CONVACC_FSUB_FSUB_LSB) /** Description of the FSUB register. */ #define ATON_CONVACC_FSUB_DESC "Feature data subtract" /** Address of the FSUB register of one of the CONVACC Units. */ #define ATON_CONVACC_FSUB_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_FSUB_OFFSET) /** Get the content of the FSUB register of one of the CONVACC Units. */ #define ATON_CONVACC_FSUB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FSUB_ADDR(UNIT))) /** Set the content of the FSUB register of one of the CONVACC Units. */ #define ATON_CONVACC_FSUB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_FSUB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FSUB register. * * \return the description of FSUB register */ static inline const int8_t *ATON_CONVACC_FSUB_GetDesc(void) { return (const int8_t *)ATON_CONVACC_FSUB_DESC; } /** * Get the offset of the FSUB register. * * \return the offset of FSUB register */ static inline uint32_t ATON_CONVACC_FSUB_GetOffset(void) { return ATON_CONVACC_FSUB_OFFSET; } /** * Get the address of the FSUB register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FSUB register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of FSUB register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FSUB_GetAddr(uint32_t instance) { return ATON_CONVACC_FSUB_ADDR(instance); } /** * Read the content of the FSUB register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FSUB register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of FSUB register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_FSUB_Get(uint32_t instance) { return ATON_CONVACC_FSUB_GET(instance); } /** * Write the content of the FSUB register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the FSUB register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_FSUB_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_FSUB_SET(instance, data); } /* ------------------------------------------------------------ FSUB field of the FSUB register ------------------------------------------------------------- */ /** Description of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_FSUB_DESC "Feature data subtract value" /** Offset of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_FSUB_LSB 0UL /** Size in bits of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_FSUB_W (24UL) /** Mask for retrieving the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_FSUB_MASK ATON_FIELD_MASK(0UL, 24UL) /** Reset value of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_FSUB_DT 0x0UL /** Access rights of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_FSUB_AC "RW" /** Check whether access to the FSUB field of the FSUB register is secured or not. */ #define ATON_CONVACC_FSUB_FSUB_S 0 /** Check whether access to the FSUB field of the FSUB register is privileged or not. */ #define ATON_CONVACC_FSUB_FSUB_P 0 /** Read the content of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_GET_FSUB(REG) ATON_GET_FIELD(REG, ATON_CONVACC_FSUB_FSUB_LSB, ATON_CONVACC_FSUB_FSUB_W) /** Modify the content of the FSUB field of the FSUB register. */ #define ATON_CONVACC_FSUB_SET_FSUB(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_FSUB_FSUB_LSB, ATON_CONVACC_FSUB_FSUB_W, DATA) /** * Get the description of the FSUB field of FSUB register. * * \return the description of the FSUB field of FSUB register */ static inline const int8_t *ATON_CONVACC_FSUB_FSUB_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_FSUB_FSUB_DESC; } /** * Read the content of the FSUB field of the FSUB register. * * \param[in] reg is the value of the FSUB register * * \return the content of the FSUB field belonging to FSUB register */ static inline uint32_t ATON_CONVACC_FSUB_Get_FSUB(uint32_t reg) { return ATON_CONVACC_FSUB_GET_FSUB(reg); } /** * Write the content of the FSUB field of the FSUB register. * * \param[in] reg is the value of the FSUB register * \param[in] data is 24-bit value that must be written to the field * * \return the new content of the FSUB field belonging to FSUB register */ static inline uint32_t ATON_CONVACC_FSUB_Set_FSUB(uint32_t reg, uint32_t data) { return ATON_CONVACC_FSUB_SET_FSUB(reg, data); } /* ****************************************************** ZFBIAS register of one of the CONVACC Units ******************************************************* */ /** Offset of the ZFBIAS register from the base address of the CONVACC Unit. */ #define ATON_CONVACC_ZFBIAS_OFFSET 0x34UL /** Reset value of the ZFBIAS register of the CONVACC Unit. */ #define ATON_CONVACC_ZFBIAS_DT \ (ATON_CONVACC_ZFBIAS_ZFBIAS_DT << ATON_CONVACC_ZFBIAS_ZFBIAS_LSB) /** Description of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_DESC "Zero Frame Bias" /** Address of the ZFBIAS register of one of the CONVACC Units. */ #define ATON_CONVACC_ZFBIAS_ADDR(UNIT) (ATON_CONVACC_BASE(UNIT) + ATON_CONVACC_ZFBIAS_OFFSET) /** Get the content of the ZFBIAS register of one of the CONVACC Units. */ #define ATON_CONVACC_ZFBIAS_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFBIAS_ADDR(UNIT))) /** Set the content of the ZFBIAS register of one of the CONVACC Units. */ #define ATON_CONVACC_ZFBIAS_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_CONVACC_ZFBIAS_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ZFBIAS register. * * \return the description of ZFBIAS register */ static inline const int8_t *ATON_CONVACC_ZFBIAS_GetDesc(void) { return (const int8_t *)ATON_CONVACC_ZFBIAS_DESC; } /** * Get the offset of the ZFBIAS register. * * \return the offset of ZFBIAS register */ static inline uint32_t ATON_CONVACC_ZFBIAS_GetOffset(void) { return ATON_CONVACC_ZFBIAS_OFFSET; } /** * Get the address of the ZFBIAS register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFBIAS register whose address must be returned * (it must be instance \< 4<\em>) * * \return the address of ZFBIAS register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_ZFBIAS_GetAddr(uint32_t instance) { return ATON_CONVACC_ZFBIAS_ADDR(instance); } /** * Read the content of the ZFBIAS register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFBIAS register whose content must be retrieved * (it must be instance \< 4<\em>) * * \return the content of ZFBIAS register belonging to Unit having index \e instance among the CONVACC Units */ static inline uint32_t ATON_CONVACC_ZFBIAS_Get(uint32_t instance) { return ATON_CONVACC_ZFBIAS_GET(instance); } /** * Write the content of the ZFBIAS register. * * \param[in] instance is the index of the Unit (among the CONVACC Units) containing the ZFBIAS register whose content must be modified * (it must be instance \< 4<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_CONVACC_ZFBIAS_Set(uint32_t instance, uint32_t data) { ATON_CONVACC_ZFBIAS_SET(instance, data); } /* ---------------------------------------------------------- ZFBIAS field of the ZFBIAS register ----------------------------------------------------------- */ /** Description of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_DESC "Bias added to zero frames" /** Offset of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_LSB 0UL /** Size in bits of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_W (16UL) /** Mask for retrieving the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_DT 0x0UL /** Access rights of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_AC "RW" /** Check whether access to the ZFBIAS field of the ZFBIAS register is secured or not. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_S 0 /** Check whether access to the ZFBIAS field of the ZFBIAS register is privileged or not. */ #define ATON_CONVACC_ZFBIAS_ZFBIAS_P 0 /** Read the content of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_GET_ZFBIAS(REG) ATON_GET_FIELD(REG, ATON_CONVACC_ZFBIAS_ZFBIAS_LSB, ATON_CONVACC_ZFBIAS_ZFBIAS_W) /** Modify the content of the ZFBIAS field of the ZFBIAS register. */ #define ATON_CONVACC_ZFBIAS_SET_ZFBIAS(REG, DATA) ATON_SET_FIELD(REG, ATON_CONVACC_ZFBIAS_ZFBIAS_LSB, ATON_CONVACC_ZFBIAS_ZFBIAS_W, DATA) /** * Get the description of the ZFBIAS field of ZFBIAS register. * * \return the description of the ZFBIAS field of ZFBIAS register */ static inline const int8_t *ATON_CONVACC_ZFBIAS_ZFBIAS_GetdDesc(void) { return (const int8_t *)ATON_CONVACC_ZFBIAS_ZFBIAS_DESC; } /** * Read the content of the ZFBIAS field of the ZFBIAS register. * * \param[in] reg is the value of the ZFBIAS register * * \return the content of the ZFBIAS field belonging to ZFBIAS register */ static inline uint32_t ATON_CONVACC_ZFBIAS_Get_ZFBIAS(uint32_t reg) { return ATON_CONVACC_ZFBIAS_GET_ZFBIAS(reg); } /** * Write the content of the ZFBIAS field of the ZFBIAS register. * * \param[in] reg is the value of the ZFBIAS register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the ZFBIAS field belonging to ZFBIAS register */ static inline uint32_t ATON_CONVACC_ZFBIAS_Set_ZFBIAS(uint32_t reg, uint32_t data) { return ATON_CONVACC_ZFBIAS_SET_ZFBIAS(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* DECUN Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of DECUN Unit instances. */ #define ATON_DECUN_NUM 2 /** * \name Structures, macros and functions of the DECUN Units */ /*@{*/ /** * Registers of the DECUN Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e BFORMAT register (Number of Codebooks and Codevectors). */ uint32_t BFORMAT; /** \e DFORMAT register (CV data format). */ uint32_t DFORMAT; /** \e FFORMAT register (Number of batches). */ uint32_t FFORMAT; } ATON_DECUN_t; /** Return the pointer to one of the DECUN Units. */ #define ATON_DECUN(UNIT) ((ATON_DECUN_t *)(intptr_t)ATON_DECUN_BASE(UNIT)) /** Name of one of the DECUN Units. */ #define ATON_DECUN_NAME(UNIT) \ (((UNIT) == 0) ? "DECUN0" : \ (((UNIT) == 1) ? "DECUN1" : "")) /** Version of the DECUN Units. */ #define ATON_DECUN_VERSION "1.10" /** Description of one of the DECUN Units. */ #define ATON_DECUN_DESC(UNIT) \ (((UNIT) == 0) ? "Decompression Unit 0" : \ (((UNIT) == 1) ? "Decompression Unit 1" : "")) /** Base address of one of the DECUN Units. */ #define ATON_DECUN_BASE(UNIT) \ (ATON_BASE + 0x13000UL + ((UNIT) * 0x1000UL)) /** Size in bytes of the DECUN Units. */ #define ATON_DECUN_SIZE 0x1000UL /** * Get the name of one of the DECUN Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 2<\em>) * * \return the name of Unit having index \e instance among the DECUN Units */ static inline const int8_t *ATON_DECUN_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"DECUN0"; break; case 1: str = (const int8_t *)"DECUN1"; break; default: break; } return str; } /** * Get the description of one of the DECUN Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 2<\em>) * * \return the description of Unit having index \e instance among the DECUN Units */ static inline const int8_t *ATON_DECUN_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Decompression Unit 0"; break; case 1: str = (const int8_t *)"Decompression Unit 1"; break; default: break; } return str; } /** * Get the version of the DECUN Units. * * \return the version of the DECUN Units */ static inline const int8_t *ATON_DECUN_GetVersion(void) { return (const int8_t *)ATON_DECUN_VERSION; } /** * Get the base address of one of the DECUN Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 2<\em>) * * \return the base address of Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_GetBase(uint32_t instance) { return ATON_DECUN_BASE(instance); } /** * Get the size in bytes of the DECUN Units. * * \return the size in bytes of the DECUN Units */ static inline uint32_t ATON_DECUN_GetSize(void) { return ATON_DECUN_SIZE; } /* ******************************************************** CTRL register of one of the DECUN Units ********************************************************* */ /** Offset of the CTRL register from the base address of the DECUN Unit. */ #define ATON_DECUN_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the DECUN Unit. */ #define ATON_DECUN_CTRL_DT \ (ATON_DECUN_CTRL_EN_DT << ATON_DECUN_CTRL_EN_LSB) | \ (ATON_DECUN_CTRL_CLR_DT << ATON_DECUN_CTRL_CLR_LSB) | \ (ATON_DECUN_CTRL_DUALIN_DT << ATON_DECUN_CTRL_DUALIN_LSB) | \ (ATON_DECUN_CTRL_OW_DT << ATON_DECUN_CTRL_OW_LSB) | \ (ATON_DECUN_CTRL_PAGEADDR_DT << ATON_DECUN_CTRL_PAGEADDR_LSB) | \ (ATON_DECUN_CTRL_CONFCLR_DT << ATON_DECUN_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_DECUN_CTRL_DESC "Control register" /** Address of the CTRL register of one of the DECUN Units. */ #define ATON_DECUN_CTRL_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_CTRL_OFFSET) /** Get the content of the CTRL register of one of the DECUN Units. */ #define ATON_DECUN_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the DECUN Units. */ #define ATON_DECUN_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_GetDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_DECUN_CTRL_GetOffset(void) { return ATON_DECUN_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the CTRL register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_CTRL_GetAddr(uint32_t instance) { return ATON_DECUN_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_CTRL_Get(uint32_t instance) { return ATON_DECUN_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the CTRL register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DECUN_CTRL_Set(uint32_t instance, uint32_t data) { ATON_DECUN_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_EN_DESC "Enable the Decompression Unit" /** Offset of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_DECUN_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_DECUN_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_EN_LSB, ATON_DECUN_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_DECUN_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_EN_LSB, ATON_DECUN_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Get_EN(uint32_t reg) { return ATON_DECUN_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_DECUN_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_DECUN_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_DECUN_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_CLR_LSB, ATON_DECUN_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_DECUN_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_CLR_LSB, ATON_DECUN_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Get_CLR(uint32_t reg) { return ATON_DECUN_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_DECUN_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- DUALIN field of the CTRL register ------------------------------------------------------------ */ /** Description of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_DUALIN_DESC "Disable the kernel writing stream link" /** Offset of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_DUALIN_LSB 2UL /** Size in bits of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_DUALIN_W (1UL) /** Mask for retrieving the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_DUALIN_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_DUALIN_DT 0x0UL /** Access rights of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_DUALIN_AC "RW" /** Check whether access to the DUALIN field of the CTRL register is secured or not. */ #define ATON_DECUN_CTRL_DUALIN_S 0 /** Check whether access to the DUALIN field of the CTRL register is privileged or not. */ #define ATON_DECUN_CTRL_DUALIN_P 0 /** Read the content of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_GET_DUALIN(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_DUALIN_LSB, ATON_DECUN_CTRL_DUALIN_W) /** Modify the content of the DUALIN field of the CTRL register. */ #define ATON_DECUN_CTRL_SET_DUALIN(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_DUALIN_LSB, ATON_DECUN_CTRL_DUALIN_W, DATA) /** * Get the description of the DUALIN field of CTRL register. * * \return the description of the DUALIN field of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_DUALIN_GetdDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_DUALIN_DESC; } /** * Read the content of the DUALIN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the DUALIN field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Get_DUALIN(uint32_t reg) { return ATON_DECUN_CTRL_GET_DUALIN(reg); } /** * Write the content of the DUALIN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the DUALIN field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Set_DUALIN(uint32_t reg, uint32_t data) { return ATON_DECUN_CTRL_SET_DUALIN(reg, data); } /* ------------------------------------------------------------- OW field of the CTRL register -------------------------------------------------------------- */ /** Description of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_OW_DESC "Enable of CBs overwriting" /** Offset of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_OW_LSB 3UL /** Size in bits of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_OW_W (1UL) /** Mask for retrieving the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_OW_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_OW_DT 0x0UL /** Access rights of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_OW_AC "RW" /** Check whether access to the OW field of the CTRL register is secured or not. */ #define ATON_DECUN_CTRL_OW_S 0 /** Check whether access to the OW field of the CTRL register is privileged or not. */ #define ATON_DECUN_CTRL_OW_P 0 /** Read the content of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_GET_OW(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_OW_LSB, ATON_DECUN_CTRL_OW_W) /** Modify the content of the OW field of the CTRL register. */ #define ATON_DECUN_CTRL_SET_OW(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_OW_LSB, ATON_DECUN_CTRL_OW_W, DATA) /** * Get the description of the OW field of CTRL register. * * \return the description of the OW field of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_OW_GetdDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_OW_DESC; } /** * Read the content of the OW field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the OW field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Get_OW(uint32_t reg) { return ATON_DECUN_CTRL_GET_OW(reg); } /** * Write the content of the OW field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OW field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Set_OW(uint32_t reg, uint32_t data) { return ATON_DECUN_CTRL_SET_OW(reg, data); } /* ---------------------------------------------------------- PAGEADDR field of the CTRL register ----------------------------------------------------------- */ /** Description of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_PAGEADDR_DESC "Choose the Page to w/r in the memory from the bus" /** Offset of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_PAGEADDR_LSB 4UL /** Size in bits of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_PAGEADDR_W (2UL) /** Mask for retrieving the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_PAGEADDR_MASK ATON_FIELD_MASK(4UL, 2UL) /** Reset value of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_PAGEADDR_DT 0x0UL /** Access rights of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_PAGEADDR_AC "RW" /** Check whether access to the PAGEADDR field of the CTRL register is secured or not. */ #define ATON_DECUN_CTRL_PAGEADDR_S 0 /** Check whether access to the PAGEADDR field of the CTRL register is privileged or not. */ #define ATON_DECUN_CTRL_PAGEADDR_P 0 /** Read the content of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_GET_PAGEADDR(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_PAGEADDR_LSB, ATON_DECUN_CTRL_PAGEADDR_W) /** Modify the content of the PAGEADDR field of the CTRL register. */ #define ATON_DECUN_CTRL_SET_PAGEADDR(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_PAGEADDR_LSB, ATON_DECUN_CTRL_PAGEADDR_W, DATA) /** * Get the description of the PAGEADDR field of CTRL register. * * \return the description of the PAGEADDR field of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_PAGEADDR_GetdDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_PAGEADDR_DESC; } /** * Read the content of the PAGEADDR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the PAGEADDR field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Get_PAGEADDR(uint32_t reg) { return ATON_DECUN_CTRL_GET_PAGEADDR(reg); } /** * Write the content of the PAGEADDR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the PAGEADDR field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Set_PAGEADDR(uint32_t reg, uint32_t data) { return ATON_DECUN_CTRL_SET_PAGEADDR(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_DECUN_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_DECUN_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_DECUN_CTRL_CONFCLR_LSB, ATON_DECUN_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_DECUN_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_CTRL_CONFCLR_LSB, ATON_DECUN_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_DECUN_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_DECUN_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_DECUN_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_DECUN_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_DECUN_CTRL_SET_CONFCLR(reg, data); } /* ******************************************************* VERSION register of one of the DECUN Units ******************************************************* */ /** Offset of the VERSION register from the base address of the DECUN Unit. */ #define ATON_DECUN_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the DECUN Unit. */ #define ATON_DECUN_VERSION_DT \ (ATON_DECUN_VERSION_TYPE_DT << ATON_DECUN_VERSION_TYPE_LSB) | \ (ATON_DECUN_VERSION_MINOR_DT << ATON_DECUN_VERSION_MINOR_LSB) | \ (ATON_DECUN_VERSION_MAJOR_DT << ATON_DECUN_VERSION_MAJOR_LSB) /** Description of the VERSION register. */ #define ATON_DECUN_VERSION_DESC "Version register" /** Address of the VERSION register of one of the DECUN Units. */ #define ATON_DECUN_VERSION_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_VERSION_OFFSET) /** Get the content of the VERSION register of one of the DECUN Units. */ #define ATON_DECUN_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_DECUN_VERSION_GetDesc(void) { return (const int8_t *)ATON_DECUN_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_DECUN_VERSION_GetOffset(void) { return ATON_DECUN_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the VERSION register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_VERSION_GetAddr(uint32_t instance) { return ATON_DECUN_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_VERSION_Get(uint32_t instance) { return ATON_DECUN_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_TYPE_DT 0x19UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_DECUN_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_DECUN_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_DECUN_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_DECUN_VERSION_TYPE_LSB, ATON_DECUN_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_DECUN_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DECUN_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_DECUN_VERSION_Get_TYPE(uint32_t reg) { return ATON_DECUN_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MINOR_DT 0xaUL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_DECUN_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_DECUN_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_DECUN_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_DECUN_VERSION_MINOR_LSB, ATON_DECUN_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_DECUN_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_DECUN_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_DECUN_VERSION_Get_MINOR(uint32_t reg) { return ATON_DECUN_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_DECUN_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_DECUN_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_DECUN_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_DECUN_VERSION_MAJOR_LSB, ATON_DECUN_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_DECUN_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_DECUN_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_DECUN_VERSION_Get_MAJOR(uint32_t reg) { return ATON_DECUN_VERSION_GET_MAJOR(reg); } /* ******************************************************* BFORMAT register of one of the DECUN Units ******************************************************* */ /** Offset of the BFORMAT register from the base address of the DECUN Unit. */ #define ATON_DECUN_BFORMAT_OFFSET 0x8UL /** Reset value of the BFORMAT register of the DECUN Unit. */ #define ATON_DECUN_BFORMAT_DT \ (ATON_DECUN_BFORMAT_CVS_DT << ATON_DECUN_BFORMAT_CVS_LSB) | \ (ATON_DECUN_BFORMAT_CWS_DT << ATON_DECUN_BFORMAT_CWS_LSB) | \ (ATON_DECUN_BFORMAT_OSAM_DT << ATON_DECUN_BFORMAT_OSAM_LSB) /** Description of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_DESC "Number of Codebooks and Codevectors" /** Address of the BFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_BFORMAT_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_BFORMAT_OFFSET) /** Get the content of the BFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_BFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_BFORMAT_ADDR(UNIT))) /** Set the content of the BFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_BFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_BFORMAT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of BFORMAT register. * * \return the description of BFORMAT register */ static inline const int8_t *ATON_DECUN_BFORMAT_GetDesc(void) { return (const int8_t *)ATON_DECUN_BFORMAT_DESC; } /** * Get the offset of the BFORMAT register. * * \return the offset of BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_GetOffset(void) { return ATON_DECUN_BFORMAT_OFFSET; } /** * Get the address of the BFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the BFORMAT register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of BFORMAT register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_BFORMAT_GetAddr(uint32_t instance) { return ATON_DECUN_BFORMAT_ADDR(instance); } /** * Read the content of the BFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the BFORMAT register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of BFORMAT register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_BFORMAT_Get(uint32_t instance) { return ATON_DECUN_BFORMAT_GET(instance); } /** * Write the content of the BFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the BFORMAT register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DECUN_BFORMAT_Set(uint32_t instance, uint32_t data) { ATON_DECUN_BFORMAT_SET(instance, data); } /* ----------------------------------------------------------- CVS field of the BFORMAT register ------------------------------------------------------------ */ /** Description of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CVS_DESC "Number of Codevectors per Codebook" /** Offset of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CVS_LSB 0UL /** Size in bits of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CVS_W (8UL) /** Mask for retrieving the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CVS_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CVS_DT 0x0UL /** Access rights of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CVS_AC "RW" /** Check whether access to the CVS field of the BFORMAT register is secured or not. */ #define ATON_DECUN_BFORMAT_CVS_S 0 /** Check whether access to the CVS field of the BFORMAT register is privileged or not. */ #define ATON_DECUN_BFORMAT_CVS_P 0 /** Read the content of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_GET_CVS(REG) ATON_GET_FIELD(REG, ATON_DECUN_BFORMAT_CVS_LSB, ATON_DECUN_BFORMAT_CVS_W) /** Modify the content of the CVS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_SET_CVS(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_BFORMAT_CVS_LSB, ATON_DECUN_BFORMAT_CVS_W, DATA) /** * Get the description of the CVS field of BFORMAT register. * * \return the description of the CVS field of BFORMAT register */ static inline const int8_t *ATON_DECUN_BFORMAT_CVS_GetdDesc(void) { return (const int8_t *)ATON_DECUN_BFORMAT_CVS_DESC; } /** * Read the content of the CVS field of the BFORMAT register. * * \param[in] reg is the value of the BFORMAT register * * \return the content of the CVS field belonging to BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_Get_CVS(uint32_t reg) { return ATON_DECUN_BFORMAT_GET_CVS(reg); } /** * Write the content of the CVS field of the BFORMAT register. * * \param[in] reg is the value of the BFORMAT register * \param[in] data is 8-bit value that must be written to the field * * \return the new content of the CVS field belonging to BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_Set_CVS(uint32_t reg, uint32_t data) { return ATON_DECUN_BFORMAT_SET_CVS(reg, data); } /* ----------------------------------------------------------- CWS field of the BFORMAT register ------------------------------------------------------------ */ /** Description of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CWS_DESC "Number of Codewords per Codevectors" /** Offset of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CWS_LSB 8UL /** Size in bits of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CWS_W (3UL) /** Mask for retrieving the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CWS_MASK ATON_FIELD_MASK(8UL, 3UL) /** Reset value of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CWS_DT 0x0UL /** Access rights of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_CWS_AC "RW" /** Check whether access to the CWS field of the BFORMAT register is secured or not. */ #define ATON_DECUN_BFORMAT_CWS_S 0 /** Check whether access to the CWS field of the BFORMAT register is privileged or not. */ #define ATON_DECUN_BFORMAT_CWS_P 0 /** Read the content of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_GET_CWS(REG) ATON_GET_FIELD(REG, ATON_DECUN_BFORMAT_CWS_LSB, ATON_DECUN_BFORMAT_CWS_W) /** Modify the content of the CWS field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_SET_CWS(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_BFORMAT_CWS_LSB, ATON_DECUN_BFORMAT_CWS_W, DATA) /** * Get the description of the CWS field of BFORMAT register. * * \return the description of the CWS field of BFORMAT register */ static inline const int8_t *ATON_DECUN_BFORMAT_CWS_GetdDesc(void) { return (const int8_t *)ATON_DECUN_BFORMAT_CWS_DESC; } /** * Read the content of the CWS field of the BFORMAT register. * * \param[in] reg is the value of the BFORMAT register * * \return the content of the CWS field belonging to BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_Get_CWS(uint32_t reg) { return ATON_DECUN_BFORMAT_GET_CWS(reg); } /** * Write the content of the CWS field of the BFORMAT register. * * \param[in] reg is the value of the BFORMAT register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the CWS field belonging to BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_Set_CWS(uint32_t reg, uint32_t data) { return ATON_DECUN_BFORMAT_SET_CWS(reg, data); } /* ----------------------------------------------------------- OSAM field of the BFORMAT register ----------------------------------------------------------- */ /** Description of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_OSAM_DESC "Number of read Codewords from the last CV" /** Offset of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_OSAM_LSB 12UL /** Size in bits of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_OSAM_W (3UL) /** Mask for retrieving the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_OSAM_MASK ATON_FIELD_MASK(12UL, 3UL) /** Reset value of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_OSAM_DT 0x0UL /** Access rights of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_OSAM_AC "RW" /** Check whether access to the OSAM field of the BFORMAT register is secured or not. */ #define ATON_DECUN_BFORMAT_OSAM_S 0 /** Check whether access to the OSAM field of the BFORMAT register is privileged or not. */ #define ATON_DECUN_BFORMAT_OSAM_P 0 /** Read the content of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_GET_OSAM(REG) ATON_GET_FIELD(REG, ATON_DECUN_BFORMAT_OSAM_LSB, ATON_DECUN_BFORMAT_OSAM_W) /** Modify the content of the OSAM field of the BFORMAT register. */ #define ATON_DECUN_BFORMAT_SET_OSAM(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_BFORMAT_OSAM_LSB, ATON_DECUN_BFORMAT_OSAM_W, DATA) /** * Get the description of the OSAM field of BFORMAT register. * * \return the description of the OSAM field of BFORMAT register */ static inline const int8_t *ATON_DECUN_BFORMAT_OSAM_GetdDesc(void) { return (const int8_t *)ATON_DECUN_BFORMAT_OSAM_DESC; } /** * Read the content of the OSAM field of the BFORMAT register. * * \param[in] reg is the value of the BFORMAT register * * \return the content of the OSAM field belonging to BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_Get_OSAM(uint32_t reg) { return ATON_DECUN_BFORMAT_GET_OSAM(reg); } /** * Write the content of the OSAM field of the BFORMAT register. * * \param[in] reg is the value of the BFORMAT register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the OSAM field belonging to BFORMAT register */ static inline uint32_t ATON_DECUN_BFORMAT_Set_OSAM(uint32_t reg, uint32_t data) { return ATON_DECUN_BFORMAT_SET_OSAM(reg, data); } /* ******************************************************* DFORMAT register of one of the DECUN Units ******************************************************* */ /** Offset of the DFORMAT register from the base address of the DECUN Unit. */ #define ATON_DECUN_DFORMAT_OFFSET 0xcUL /** Reset value of the DFORMAT register of the DECUN Unit. */ #define ATON_DECUN_DFORMAT_DT \ (ATON_DECUN_DFORMAT_CV8_DT << ATON_DECUN_DFORMAT_CV8_LSB) | \ (ATON_DECUN_DFORMAT_RAWLINE_DT << ATON_DECUN_DFORMAT_RAWLINE_LSB) /** Description of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_DESC "CV data format" /** Address of the DFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_DFORMAT_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_DFORMAT_OFFSET) /** Get the content of the DFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_DFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_DFORMAT_ADDR(UNIT))) /** Set the content of the DFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_DFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_DFORMAT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of DFORMAT register. * * \return the description of DFORMAT register */ static inline const int8_t *ATON_DECUN_DFORMAT_GetDesc(void) { return (const int8_t *)ATON_DECUN_DFORMAT_DESC; } /** * Get the offset of the DFORMAT register. * * \return the offset of DFORMAT register */ static inline uint32_t ATON_DECUN_DFORMAT_GetOffset(void) { return ATON_DECUN_DFORMAT_OFFSET; } /** * Get the address of the DFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the DFORMAT register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of DFORMAT register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_DFORMAT_GetAddr(uint32_t instance) { return ATON_DECUN_DFORMAT_ADDR(instance); } /** * Read the content of the DFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the DFORMAT register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of DFORMAT register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_DFORMAT_Get(uint32_t instance) { return ATON_DECUN_DFORMAT_GET(instance); } /** * Write the content of the DFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the DFORMAT register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DECUN_DFORMAT_Set(uint32_t instance, uint32_t data) { ATON_DECUN_DFORMAT_SET(instance, data); } /* ----------------------------------------------------------- CV8 field of the DFORMAT register ------------------------------------------------------------ */ /** Description of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_CV8_DESC "CodeVector data format" /** Offset of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_CV8_LSB 0UL /** Size in bits of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_CV8_W (1UL) /** Mask for retrieving the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_CV8_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_CV8_DT 0x0UL /** Access rights of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_CV8_AC "RW" /** Check whether access to the CV8 field of the DFORMAT register is secured or not. */ #define ATON_DECUN_DFORMAT_CV8_S 0 /** Check whether access to the CV8 field of the DFORMAT register is privileged or not. */ #define ATON_DECUN_DFORMAT_CV8_P 0 /** Read the content of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_GET_CV8(REG) ATON_GET_FIELD(REG, ATON_DECUN_DFORMAT_CV8_LSB, ATON_DECUN_DFORMAT_CV8_W) /** Modify the content of the CV8 field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_SET_CV8(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_DFORMAT_CV8_LSB, ATON_DECUN_DFORMAT_CV8_W, DATA) /** * Get the description of the CV8 field of DFORMAT register. * * \return the description of the CV8 field of DFORMAT register */ static inline const int8_t *ATON_DECUN_DFORMAT_CV8_GetdDesc(void) { return (const int8_t *)ATON_DECUN_DFORMAT_CV8_DESC; } /** * Read the content of the CV8 field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the CV8 field belonging to DFORMAT register */ static inline uint32_t ATON_DECUN_DFORMAT_Get_CV8(uint32_t reg) { return ATON_DECUN_DFORMAT_GET_CV8(reg); } /** * Write the content of the CV8 field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CV8 field belonging to DFORMAT register */ static inline uint32_t ATON_DECUN_DFORMAT_Set_CV8(uint32_t reg, uint32_t data) { return ATON_DECUN_DFORMAT_SET_CV8(reg, data); } /* --------------------------------------------------------- RAWLINE field of the DFORMAT register ---------------------------------------------------------- */ /** Description of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_RAWLINE_DESC "Raw linetype output" /** Offset of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_RAWLINE_LSB 1UL /** Size in bits of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_RAWLINE_W (1UL) /** Mask for retrieving the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_RAWLINE_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_RAWLINE_DT 0x0UL /** Access rights of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_RAWLINE_AC "RW" /** Check whether access to the RAWLINE field of the DFORMAT register is secured or not. */ #define ATON_DECUN_DFORMAT_RAWLINE_S 0 /** Check whether access to the RAWLINE field of the DFORMAT register is privileged or not. */ #define ATON_DECUN_DFORMAT_RAWLINE_P 0 /** Read the content of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_GET_RAWLINE(REG) ATON_GET_FIELD(REG, ATON_DECUN_DFORMAT_RAWLINE_LSB, ATON_DECUN_DFORMAT_RAWLINE_W) /** Modify the content of the RAWLINE field of the DFORMAT register. */ #define ATON_DECUN_DFORMAT_SET_RAWLINE(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_DFORMAT_RAWLINE_LSB, ATON_DECUN_DFORMAT_RAWLINE_W, DATA) /** * Get the description of the RAWLINE field of DFORMAT register. * * \return the description of the RAWLINE field of DFORMAT register */ static inline const int8_t *ATON_DECUN_DFORMAT_RAWLINE_GetdDesc(void) { return (const int8_t *)ATON_DECUN_DFORMAT_RAWLINE_DESC; } /** * Read the content of the RAWLINE field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * * \return the content of the RAWLINE field belonging to DFORMAT register */ static inline uint32_t ATON_DECUN_DFORMAT_Get_RAWLINE(uint32_t reg) { return ATON_DECUN_DFORMAT_GET_RAWLINE(reg); } /** * Write the content of the RAWLINE field of the DFORMAT register. * * \param[in] reg is the value of the DFORMAT register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the RAWLINE field belonging to DFORMAT register */ static inline uint32_t ATON_DECUN_DFORMAT_Set_RAWLINE(uint32_t reg, uint32_t data) { return ATON_DECUN_DFORMAT_SET_RAWLINE(reg, data); } /* ******************************************************* FFORMAT register of one of the DECUN Units ******************************************************* */ /** Offset of the FFORMAT register from the base address of the DECUN Unit. */ #define ATON_DECUN_FFORMAT_OFFSET 0x10UL /** Reset value of the FFORMAT register of the DECUN Unit. */ #define ATON_DECUN_FFORMAT_DT \ (ATON_DECUN_FFORMAT_BN_DT << ATON_DECUN_FFORMAT_BN_LSB) /** Description of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_DESC "Number of batches" /** Address of the FFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_FFORMAT_ADDR(UNIT) (ATON_DECUN_BASE(UNIT) + ATON_DECUN_FFORMAT_OFFSET) /** Get the content of the FFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_FFORMAT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DECUN_FFORMAT_ADDR(UNIT))) /** Set the content of the FFORMAT register of one of the DECUN Units. */ #define ATON_DECUN_FFORMAT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DECUN_FFORMAT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FFORMAT register. * * \return the description of FFORMAT register */ static inline const int8_t *ATON_DECUN_FFORMAT_GetDesc(void) { return (const int8_t *)ATON_DECUN_FFORMAT_DESC; } /** * Get the offset of the FFORMAT register. * * \return the offset of FFORMAT register */ static inline uint32_t ATON_DECUN_FFORMAT_GetOffset(void) { return ATON_DECUN_FFORMAT_OFFSET; } /** * Get the address of the FFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the FFORMAT register whose address must be returned * (it must be instance \< 2<\em>) * * \return the address of FFORMAT register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_FFORMAT_GetAddr(uint32_t instance) { return ATON_DECUN_FFORMAT_ADDR(instance); } /** * Read the content of the FFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the FFORMAT register whose content must be retrieved * (it must be instance \< 2<\em>) * * \return the content of FFORMAT register belonging to Unit having index \e instance among the DECUN Units */ static inline uint32_t ATON_DECUN_FFORMAT_Get(uint32_t instance) { return ATON_DECUN_FFORMAT_GET(instance); } /** * Write the content of the FFORMAT register. * * \param[in] instance is the index of the Unit (among the DECUN Units) containing the FFORMAT register whose content must be modified * (it must be instance \< 2<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DECUN_FFORMAT_Set(uint32_t instance, uint32_t data) { ATON_DECUN_FFORMAT_SET(instance, data); } /* ------------------------------------------------------------ BN field of the FFORMAT register ------------------------------------------------------------ */ /** Description of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_BN_DESC "Number of batches" /** Offset of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_BN_LSB 0UL /** Size in bits of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_BN_W (10UL) /** Mask for retrieving the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_BN_MASK ATON_FIELD_MASK(0UL, 10UL) /** Reset value of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_BN_DT 0x0UL /** Access rights of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_BN_AC "RW" /** Check whether access to the BN field of the FFORMAT register is secured or not. */ #define ATON_DECUN_FFORMAT_BN_S 0 /** Check whether access to the BN field of the FFORMAT register is privileged or not. */ #define ATON_DECUN_FFORMAT_BN_P 0 /** Read the content of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_GET_BN(REG) ATON_GET_FIELD(REG, ATON_DECUN_FFORMAT_BN_LSB, ATON_DECUN_FFORMAT_BN_W) /** Modify the content of the BN field of the FFORMAT register. */ #define ATON_DECUN_FFORMAT_SET_BN(REG, DATA) ATON_SET_FIELD(REG, ATON_DECUN_FFORMAT_BN_LSB, ATON_DECUN_FFORMAT_BN_W, DATA) /** * Get the description of the BN field of FFORMAT register. * * \return the description of the BN field of FFORMAT register */ static inline const int8_t *ATON_DECUN_FFORMAT_BN_GetdDesc(void) { return (const int8_t *)ATON_DECUN_FFORMAT_BN_DESC; } /** * Read the content of the BN field of the FFORMAT register. * * \param[in] reg is the value of the FFORMAT register * * \return the content of the BN field belonging to FFORMAT register */ static inline uint32_t ATON_DECUN_FFORMAT_Get_BN(uint32_t reg) { return ATON_DECUN_FFORMAT_GET_BN(reg); } /** * Write the content of the BN field of the FFORMAT register. * * \param[in] reg is the value of the FFORMAT register * \param[in] data is 10-bit value that must be written to the field * * \return the new content of the BN field belonging to FFORMAT register */ static inline uint32_t ATON_DECUN_FFORMAT_Set_BN(uint32_t reg, uint32_t data) { return ATON_DECUN_FFORMAT_SET_BN(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* RECBUF Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of RECBUF Unit instances. */ #define ATON_RECBUF_NUM 1 /** * \name Structures, macros and functions of the RECBUF Units */ /*@{*/ /** * Registers of the RECBUF Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e FORMAT0 register (Number of Input used channels and linetype for Input Stream 0). */ uint32_t FORMAT0; /** \e FORMAT1 register (Number of Input/Output used channels and linetype for Output Stream 1). */ uint32_t FORMAT1; /** \e FORMAT2 register (Number of Input/Output used channels and linetype for Output Stream 2). */ uint32_t FORMAT2; } ATON_RECBUF_t; /** Return the pointer to one of the RECBUF Units. */ #define ATON_RECBUF(UNIT) ((ATON_RECBUF_t *)(intptr_t)ATON_RECBUF_BASE(UNIT)) /** Name of one of the RECBUF Units. */ #define ATON_RECBUF_NAME(UNIT) \ (((UNIT) == 0) ? "RECBUF0" : "") /** Version of the RECBUF Units. */ #define ATON_RECBUF_VERSION "3.2" /** Description of one of the RECBUF Units. */ #define ATON_RECBUF_DESC(UNIT) \ (((UNIT) == 0) ? "Reconfigurable Buffer 0" : "") /** Base address of one of the RECBUF Units. */ #define ATON_RECBUF_BASE(UNIT) \ (ATON_BASE + 0x1d000UL + ((UNIT) * 0x0UL)) /** Size in bytes of the RECBUF Units. */ #define ATON_RECBUF_SIZE 0x1000UL /** * Get the name of one of the RECBUF Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) * * \return the name of Unit having index \e instance among the RECBUF Units */ static inline const int8_t *ATON_RECBUF_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"RECBUF0"; break; default: break; } return str; } /** * Get the description of one of the RECBUF Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) * * \return the description of Unit having index \e instance among the RECBUF Units */ static inline const int8_t *ATON_RECBUF_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Reconfigurable Buffer 0"; break; default: break; } return str; } /** * Get the version of the RECBUF Units. * * \return the version of the RECBUF Units */ static inline const int8_t *ATON_RECBUF_GetVersion(void) { return (const int8_t *)ATON_RECBUF_VERSION; } /** * Get the base address of one of the RECBUF Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) * * \return the base address of Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_GetBase(uint32_t instance) { return ATON_RECBUF_BASE(instance); } /** * Get the size in bytes of the RECBUF Units. * * \return the size in bytes of the RECBUF Units */ static inline uint32_t ATON_RECBUF_GetSize(void) { return ATON_RECBUF_SIZE; } /* ******************************************************** CTRL register of one of the RECBUF Units ******************************************************** */ /** Offset of the CTRL register from the base address of the RECBUF Unit. */ #define ATON_RECBUF_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the RECBUF Unit. */ #define ATON_RECBUF_CTRL_DT \ (ATON_RECBUF_CTRL_EN_DT << ATON_RECBUF_CTRL_EN_LSB) | \ (ATON_RECBUF_CTRL_CLR_DT << ATON_RECBUF_CTRL_CLR_LSB) | \ (ATON_RECBUF_CTRL_CONFCLR_DT << ATON_RECBUF_CTRL_CONFCLR_LSB) | \ (ATON_RECBUF_CTRL_ILL_DT << ATON_RECBUF_CTRL_ILL_LSB) /** Description of the CTRL register. */ #define ATON_RECBUF_CTRL_DESC "Control register" /** Address of the CTRL register of one of the RECBUF Units. */ #define ATON_RECBUF_CTRL_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_CTRL_OFFSET) /** Get the content of the CTRL register of one of the RECBUF Units. */ #define ATON_RECBUF_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the RECBUF Units. */ #define ATON_RECBUF_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_RECBUF_CTRL_GetDesc(void) { return (const int8_t *)ATON_RECBUF_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_GetOffset(void) { return ATON_RECBUF_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the CTRL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_CTRL_GetAddr(uint32_t instance) { return ATON_RECBUF_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_CTRL_Get(uint32_t instance) { return ATON_RECBUF_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the CTRL register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_RECBUF_CTRL_Set(uint32_t instance, uint32_t data) { ATON_RECBUF_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_EN_DESC "Enable the Interrupt Controller" /** Offset of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_RECBUF_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_RECBUF_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_EN_LSB, ATON_RECBUF_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_RECBUF_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_EN_LSB, ATON_RECBUF_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_RECBUF_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Get_EN(uint32_t reg) { return ATON_RECBUF_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_RECBUF_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_RECBUF_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_RECBUF_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_CLR_LSB, ATON_RECBUF_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_CLR_LSB, ATON_RECBUF_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_RECBUF_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Get_CLR(uint32_t reg) { return ATON_RECBUF_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_RECBUF_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_RECBUF_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_RECBUF_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_CONFCLR_LSB, ATON_RECBUF_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_RECBUF_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_CONFCLR_LSB, ATON_RECBUF_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_RECBUF_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_RECBUF_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_RECBUF_CTRL_SET_CONFCLR(reg, data); } /* ------------------------------------------------------------- ILL field of the CTRL register ------------------------------------------------------------- */ /** Description of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_ILL_DESC "Illegal Configuration register" /** Offset of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_ILL_LSB 31UL /** Size in bits of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_ILL_W (1UL) /** Mask for retrieving the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_ILL_MASK ATON_FIELD_MASK(31UL, 1UL) /** Reset value of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_ILL_DT 0x0UL /** Access rights of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_ILL_AC "RW" /** Check whether access to the ILL field of the CTRL register is secured or not. */ #define ATON_RECBUF_CTRL_ILL_S 0 /** Check whether access to the ILL field of the CTRL register is privileged or not. */ #define ATON_RECBUF_CTRL_ILL_P 0 /** Read the content of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_GET_ILL(REG) ATON_GET_FIELD(REG, ATON_RECBUF_CTRL_ILL_LSB, ATON_RECBUF_CTRL_ILL_W) /** Modify the content of the ILL field of the CTRL register. */ #define ATON_RECBUF_CTRL_SET_ILL(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_CTRL_ILL_LSB, ATON_RECBUF_CTRL_ILL_W, DATA) /** * Get the description of the ILL field of CTRL register. * * \return the description of the ILL field of CTRL register */ static inline const int8_t *ATON_RECBUF_CTRL_ILL_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_CTRL_ILL_DESC; } /** * Read the content of the ILL field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the ILL field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Get_ILL(uint32_t reg) { return ATON_RECBUF_CTRL_GET_ILL(reg); } /** * Write the content of the ILL field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ILL field belonging to CTRL register */ static inline uint32_t ATON_RECBUF_CTRL_Set_ILL(uint32_t reg, uint32_t data) { return ATON_RECBUF_CTRL_SET_ILL(reg, data); } /* ****************************************************** VERSION register of one of the RECBUF Units ******************************************************* */ /** Offset of the VERSION register from the base address of the RECBUF Unit. */ #define ATON_RECBUF_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the RECBUF Unit. */ #define ATON_RECBUF_VERSION_DT \ (ATON_RECBUF_VERSION_TYPE_DT << ATON_RECBUF_VERSION_TYPE_LSB) | \ (ATON_RECBUF_VERSION_MINOR_DT << ATON_RECBUF_VERSION_MINOR_LSB) | \ (ATON_RECBUF_VERSION_MAJOR_DT << ATON_RECBUF_VERSION_MAJOR_LSB) /** Description of the VERSION register. */ #define ATON_RECBUF_VERSION_DESC "Version register" /** Address of the VERSION register of one of the RECBUF Units. */ #define ATON_RECBUF_VERSION_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_VERSION_OFFSET) /** Get the content of the VERSION register of one of the RECBUF Units. */ #define ATON_RECBUF_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_RECBUF_VERSION_GetDesc(void) { return (const int8_t *)ATON_RECBUF_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_RECBUF_VERSION_GetOffset(void) { return ATON_RECBUF_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the VERSION register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_VERSION_GetAddr(uint32_t instance) { return ATON_RECBUF_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_VERSION_Get(uint32_t instance) { return ATON_RECBUF_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_TYPE_DT 0x20UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_RECBUF_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_RECBUF_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_RECBUF_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_RECBUF_VERSION_TYPE_LSB, ATON_RECBUF_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_RECBUF_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_RECBUF_VERSION_Get_TYPE(uint32_t reg) { return ATON_RECBUF_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MINOR_DT 0x2UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_RECBUF_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_RECBUF_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_VERSION_MINOR_LSB, ATON_RECBUF_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_RECBUF_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_RECBUF_VERSION_Get_MINOR(uint32_t reg) { return ATON_RECBUF_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MAJOR_DT 0x3UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_RECBUF_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_RECBUF_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_RECBUF_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_RECBUF_VERSION_MAJOR_LSB, ATON_RECBUF_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_RECBUF_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_RECBUF_VERSION_Get_MAJOR(uint32_t reg) { return ATON_RECBUF_VERSION_GET_MAJOR(reg); } /* ****************************************************** FORMAT0 register of one of the RECBUF Units ******************************************************* */ /** Offset of the FORMAT0 register from the base address of the RECBUF Unit. */ #define ATON_RECBUF_FORMAT0_OFFSET 0x8UL /** Reset value of the FORMAT0 register of the RECBUF Unit. */ #define ATON_RECBUF_FORMAT0_DT \ (ATON_RECBUF_FORMAT0_ACTCHIN_DT << ATON_RECBUF_FORMAT0_ACTCHIN_LSB) | \ (ATON_RECBUF_FORMAT0_MEMBMARK_DT << ATON_RECBUF_FORMAT0_MEMBMARK_LSB) /** Description of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_DESC "Number of Input used channels and linetype for Input Stream 0" /** Address of the FORMAT0 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT0_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_FORMAT0_OFFSET) /** Get the content of the FORMAT0 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT0_ADDR(UNIT))) /** Set the content of the FORMAT0 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FORMAT0 register. * * \return the description of FORMAT0 register */ static inline const int8_t *ATON_RECBUF_FORMAT0_GetDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT0_DESC; } /** * Get the offset of the FORMAT0 register. * * \return the offset of FORMAT0 register */ static inline uint32_t ATON_RECBUF_FORMAT0_GetOffset(void) { return ATON_RECBUF_FORMAT0_OFFSET; } /** * Get the address of the FORMAT0 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of FORMAT0 register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_FORMAT0_GetAddr(uint32_t instance) { return ATON_RECBUF_FORMAT0_ADDR(instance); } /** * Read the content of the FORMAT0 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of FORMAT0 register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_FORMAT0_Get(uint32_t instance) { return ATON_RECBUF_FORMAT0_GET(instance); } /** * Write the content of the FORMAT0 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_RECBUF_FORMAT0_Set(uint32_t instance, uint32_t data) { ATON_RECBUF_FORMAT0_SET(instance, data); } /* --------------------------------------------------------- ACTCHIN field of the FORMAT0 register ---------------------------------------------------------- */ /** Description of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_DESC "Number of Active Input Channels" /** Offset of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_LSB 0UL /** Size in bits of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_W (2UL) /** Mask for retrieving the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_DT 0x0UL /** Access rights of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_AC "RW" /** Check whether access to the ACTCHIN field of the FORMAT0 register is secured or not. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_S 0 /** Check whether access to the ACTCHIN field of the FORMAT0 register is privileged or not. */ #define ATON_RECBUF_FORMAT0_ACTCHIN_P 0 /** Read the content of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_GET_ACTCHIN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT0_ACTCHIN_LSB, ATON_RECBUF_FORMAT0_ACTCHIN_W) /** Modify the content of the ACTCHIN field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_SET_ACTCHIN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT0_ACTCHIN_LSB, ATON_RECBUF_FORMAT0_ACTCHIN_W, DATA) /** * Get the description of the ACTCHIN field of FORMAT0 register. * * \return the description of the ACTCHIN field of FORMAT0 register */ static inline const int8_t *ATON_RECBUF_FORMAT0_ACTCHIN_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT0_ACTCHIN_DESC; } /** * Read the content of the ACTCHIN field of the FORMAT0 register. * * \param[in] reg is the value of the FORMAT0 register * * \return the content of the ACTCHIN field belonging to FORMAT0 register */ static inline uint32_t ATON_RECBUF_FORMAT0_Get_ACTCHIN(uint32_t reg) { return ATON_RECBUF_FORMAT0_GET_ACTCHIN(reg); } /** * Write the content of the ACTCHIN field of the FORMAT0 register. * * \param[in] reg is the value of the FORMAT0 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ACTCHIN field belonging to FORMAT0 register */ static inline uint32_t ATON_RECBUF_FORMAT0_Set_ACTCHIN(uint32_t reg, uint32_t data) { return ATON_RECBUF_FORMAT0_SET_ACTCHIN(reg, data); } /* --------------------------------------------------------- MEMBMARK field of the FORMAT0 register --------------------------------------------------------- */ /** Description of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_DESC "Bookmark for the RAM Partitioning for Input Stream 0" /** Offset of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_LSB 4UL /** Size in bits of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_W (10UL) /** Mask for retrieving the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_MASK ATON_FIELD_MASK(4UL, 10UL) /** Reset value of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_DT 0x0UL /** Access rights of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_AC "RW" /** Check whether access to the MEMBMARK field of the FORMAT0 register is secured or not. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_S 0 /** Check whether access to the MEMBMARK field of the FORMAT0 register is privileged or not. */ #define ATON_RECBUF_FORMAT0_MEMBMARK_P 0 /** Read the content of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_GET_MEMBMARK(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT0_MEMBMARK_LSB, ATON_RECBUF_FORMAT0_MEMBMARK_W) /** Modify the content of the MEMBMARK field of the FORMAT0 register. */ #define ATON_RECBUF_FORMAT0_SET_MEMBMARK(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT0_MEMBMARK_LSB, ATON_RECBUF_FORMAT0_MEMBMARK_W, DATA) /** * Get the description of the MEMBMARK field of FORMAT0 register. * * \return the description of the MEMBMARK field of FORMAT0 register */ static inline const int8_t *ATON_RECBUF_FORMAT0_MEMBMARK_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT0_MEMBMARK_DESC; } /** * Read the content of the MEMBMARK field of the FORMAT0 register. * * \param[in] reg is the value of the FORMAT0 register * * \return the content of the MEMBMARK field belonging to FORMAT0 register */ static inline uint32_t ATON_RECBUF_FORMAT0_Get_MEMBMARK(uint32_t reg) { return ATON_RECBUF_FORMAT0_GET_MEMBMARK(reg); } /** * Write the content of the MEMBMARK field of the FORMAT0 register. * * \param[in] reg is the value of the FORMAT0 register * \param[in] data is 10-bit value that must be written to the field * * \return the new content of the MEMBMARK field belonging to FORMAT0 register */ static inline uint32_t ATON_RECBUF_FORMAT0_Set_MEMBMARK(uint32_t reg, uint32_t data) { return ATON_RECBUF_FORMAT0_SET_MEMBMARK(reg, data); } /* ****************************************************** FORMAT1 register of one of the RECBUF Units ******************************************************* */ /** Offset of the FORMAT1 register from the base address of the RECBUF Unit. */ #define ATON_RECBUF_FORMAT1_OFFSET 0xcUL /** Reset value of the FORMAT1 register of the RECBUF Unit. */ #define ATON_RECBUF_FORMAT1_DT \ (ATON_RECBUF_FORMAT1_ACTCHIN_DT << ATON_RECBUF_FORMAT1_ACTCHIN_LSB) | \ (ATON_RECBUF_FORMAT1_MEMBMARK_DT << ATON_RECBUF_FORMAT1_MEMBMARK_LSB) /** Description of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_DESC "Number of Input/Output used channels and linetype for Output Stream 1" /** Address of the FORMAT1 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT1_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_FORMAT1_OFFSET) /** Get the content of the FORMAT1 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT1_ADDR(UNIT))) /** Set the content of the FORMAT1 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FORMAT1 register. * * \return the description of FORMAT1 register */ static inline const int8_t *ATON_RECBUF_FORMAT1_GetDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT1_DESC; } /** * Get the offset of the FORMAT1 register. * * \return the offset of FORMAT1 register */ static inline uint32_t ATON_RECBUF_FORMAT1_GetOffset(void) { return ATON_RECBUF_FORMAT1_OFFSET; } /** * Get the address of the FORMAT1 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of FORMAT1 register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_FORMAT1_GetAddr(uint32_t instance) { return ATON_RECBUF_FORMAT1_ADDR(instance); } /** * Read the content of the FORMAT1 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of FORMAT1 register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_FORMAT1_Get(uint32_t instance) { return ATON_RECBUF_FORMAT1_GET(instance); } /** * Write the content of the FORMAT1 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_RECBUF_FORMAT1_Set(uint32_t instance, uint32_t data) { ATON_RECBUF_FORMAT1_SET(instance, data); } /* --------------------------------------------------------- ACTCHIN field of the FORMAT1 register ---------------------------------------------------------- */ /** Description of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_DESC "Number of Active Input Channels" /** Offset of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_LSB 0UL /** Size in bits of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_W (2UL) /** Mask for retrieving the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_DT 0x0UL /** Access rights of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_AC "RW" /** Check whether access to the ACTCHIN field of the FORMAT1 register is secured or not. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_S 0 /** Check whether access to the ACTCHIN field of the FORMAT1 register is privileged or not. */ #define ATON_RECBUF_FORMAT1_ACTCHIN_P 0 /** Read the content of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_GET_ACTCHIN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT1_ACTCHIN_LSB, ATON_RECBUF_FORMAT1_ACTCHIN_W) /** Modify the content of the ACTCHIN field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_SET_ACTCHIN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT1_ACTCHIN_LSB, ATON_RECBUF_FORMAT1_ACTCHIN_W, DATA) /** * Get the description of the ACTCHIN field of FORMAT1 register. * * \return the description of the ACTCHIN field of FORMAT1 register */ static inline const int8_t *ATON_RECBUF_FORMAT1_ACTCHIN_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT1_ACTCHIN_DESC; } /** * Read the content of the ACTCHIN field of the FORMAT1 register. * * \param[in] reg is the value of the FORMAT1 register * * \return the content of the ACTCHIN field belonging to FORMAT1 register */ static inline uint32_t ATON_RECBUF_FORMAT1_Get_ACTCHIN(uint32_t reg) { return ATON_RECBUF_FORMAT1_GET_ACTCHIN(reg); } /** * Write the content of the ACTCHIN field of the FORMAT1 register. * * \param[in] reg is the value of the FORMAT1 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ACTCHIN field belonging to FORMAT1 register */ static inline uint32_t ATON_RECBUF_FORMAT1_Set_ACTCHIN(uint32_t reg, uint32_t data) { return ATON_RECBUF_FORMAT1_SET_ACTCHIN(reg, data); } /* --------------------------------------------------------- MEMBMARK field of the FORMAT1 register --------------------------------------------------------- */ /** Description of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_DESC "Bookmark for the RAM Partitioning for Input Stream 0" /** Offset of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_LSB 4UL /** Size in bits of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_W (10UL) /** Mask for retrieving the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_MASK ATON_FIELD_MASK(4UL, 10UL) /** Reset value of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_DT 0x0UL /** Access rights of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_AC "RW" /** Check whether access to the MEMBMARK field of the FORMAT1 register is secured or not. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_S 0 /** Check whether access to the MEMBMARK field of the FORMAT1 register is privileged or not. */ #define ATON_RECBUF_FORMAT1_MEMBMARK_P 0 /** Read the content of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_GET_MEMBMARK(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT1_MEMBMARK_LSB, ATON_RECBUF_FORMAT1_MEMBMARK_W) /** Modify the content of the MEMBMARK field of the FORMAT1 register. */ #define ATON_RECBUF_FORMAT1_SET_MEMBMARK(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT1_MEMBMARK_LSB, ATON_RECBUF_FORMAT1_MEMBMARK_W, DATA) /** * Get the description of the MEMBMARK field of FORMAT1 register. * * \return the description of the MEMBMARK field of FORMAT1 register */ static inline const int8_t *ATON_RECBUF_FORMAT1_MEMBMARK_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT1_MEMBMARK_DESC; } /** * Read the content of the MEMBMARK field of the FORMAT1 register. * * \param[in] reg is the value of the FORMAT1 register * * \return the content of the MEMBMARK field belonging to FORMAT1 register */ static inline uint32_t ATON_RECBUF_FORMAT1_Get_MEMBMARK(uint32_t reg) { return ATON_RECBUF_FORMAT1_GET_MEMBMARK(reg); } /** * Write the content of the MEMBMARK field of the FORMAT1 register. * * \param[in] reg is the value of the FORMAT1 register * \param[in] data is 10-bit value that must be written to the field * * \return the new content of the MEMBMARK field belonging to FORMAT1 register */ static inline uint32_t ATON_RECBUF_FORMAT1_Set_MEMBMARK(uint32_t reg, uint32_t data) { return ATON_RECBUF_FORMAT1_SET_MEMBMARK(reg, data); } /* ****************************************************** FORMAT2 register of one of the RECBUF Units ******************************************************* */ /** Offset of the FORMAT2 register from the base address of the RECBUF Unit. */ #define ATON_RECBUF_FORMAT2_OFFSET 0x10UL /** Reset value of the FORMAT2 register of the RECBUF Unit. */ #define ATON_RECBUF_FORMAT2_DT \ (ATON_RECBUF_FORMAT2_ACTCHIN_DT << ATON_RECBUF_FORMAT2_ACTCHIN_LSB) | \ (ATON_RECBUF_FORMAT2_MEMBMARK_DT << ATON_RECBUF_FORMAT2_MEMBMARK_LSB) /** Description of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_DESC "Number of Input/Output used channels and linetype for Output Stream 2" /** Address of the FORMAT2 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT2_ADDR(UNIT) (ATON_RECBUF_BASE(UNIT) + ATON_RECBUF_FORMAT2_OFFSET) /** Get the content of the FORMAT2 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT2_ADDR(UNIT))) /** Set the content of the FORMAT2 register of one of the RECBUF Units. */ #define ATON_RECBUF_FORMAT2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_RECBUF_FORMAT2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of FORMAT2 register. * * \return the description of FORMAT2 register */ static inline const int8_t *ATON_RECBUF_FORMAT2_GetDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT2_DESC; } /** * Get the offset of the FORMAT2 register. * * \return the offset of FORMAT2 register */ static inline uint32_t ATON_RECBUF_FORMAT2_GetOffset(void) { return ATON_RECBUF_FORMAT2_OFFSET; } /** * Get the address of the FORMAT2 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT2 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of FORMAT2 register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_FORMAT2_GetAddr(uint32_t instance) { return ATON_RECBUF_FORMAT2_ADDR(instance); } /** * Read the content of the FORMAT2 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT2 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of FORMAT2 register belonging to Unit having index \e instance among the RECBUF Units */ static inline uint32_t ATON_RECBUF_FORMAT2_Get(uint32_t instance) { return ATON_RECBUF_FORMAT2_GET(instance); } /** * Write the content of the FORMAT2 register. * * \param[in] instance is the index of the Unit (among the RECBUF Units) containing the FORMAT2 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_RECBUF_FORMAT2_Set(uint32_t instance, uint32_t data) { ATON_RECBUF_FORMAT2_SET(instance, data); } /* --------------------------------------------------------- ACTCHIN field of the FORMAT2 register ---------------------------------------------------------- */ /** Description of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_DESC "Number of Active Input Channels" /** Offset of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_LSB 0UL /** Size in bits of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_W (2UL) /** Mask for retrieving the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_MASK ATON_FIELD_MASK(0UL, 2UL) /** Reset value of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_DT 0x0UL /** Access rights of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_AC "RW" /** Check whether access to the ACTCHIN field of the FORMAT2 register is secured or not. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_S 0 /** Check whether access to the ACTCHIN field of the FORMAT2 register is privileged or not. */ #define ATON_RECBUF_FORMAT2_ACTCHIN_P 0 /** Read the content of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_GET_ACTCHIN(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT2_ACTCHIN_LSB, ATON_RECBUF_FORMAT2_ACTCHIN_W) /** Modify the content of the ACTCHIN field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_SET_ACTCHIN(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT2_ACTCHIN_LSB, ATON_RECBUF_FORMAT2_ACTCHIN_W, DATA) /** * Get the description of the ACTCHIN field of FORMAT2 register. * * \return the description of the ACTCHIN field of FORMAT2 register */ static inline const int8_t *ATON_RECBUF_FORMAT2_ACTCHIN_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT2_ACTCHIN_DESC; } /** * Read the content of the ACTCHIN field of the FORMAT2 register. * * \param[in] reg is the value of the FORMAT2 register * * \return the content of the ACTCHIN field belonging to FORMAT2 register */ static inline uint32_t ATON_RECBUF_FORMAT2_Get_ACTCHIN(uint32_t reg) { return ATON_RECBUF_FORMAT2_GET_ACTCHIN(reg); } /** * Write the content of the ACTCHIN field of the FORMAT2 register. * * \param[in] reg is the value of the FORMAT2 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the ACTCHIN field belonging to FORMAT2 register */ static inline uint32_t ATON_RECBUF_FORMAT2_Set_ACTCHIN(uint32_t reg, uint32_t data) { return ATON_RECBUF_FORMAT2_SET_ACTCHIN(reg, data); } /* --------------------------------------------------------- MEMBMARK field of the FORMAT2 register --------------------------------------------------------- */ /** Description of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_DESC "Bookmark for the RAM Partitioning for Input Stream 0" /** Offset of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_LSB 4UL /** Size in bits of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_W (10UL) /** Mask for retrieving the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_MASK ATON_FIELD_MASK(4UL, 10UL) /** Reset value of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_DT 0x0UL /** Access rights of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_AC "RW" /** Check whether access to the MEMBMARK field of the FORMAT2 register is secured or not. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_S 0 /** Check whether access to the MEMBMARK field of the FORMAT2 register is privileged or not. */ #define ATON_RECBUF_FORMAT2_MEMBMARK_P 0 /** Read the content of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_GET_MEMBMARK(REG) ATON_GET_FIELD(REG, ATON_RECBUF_FORMAT2_MEMBMARK_LSB, ATON_RECBUF_FORMAT2_MEMBMARK_W) /** Modify the content of the MEMBMARK field of the FORMAT2 register. */ #define ATON_RECBUF_FORMAT2_SET_MEMBMARK(REG, DATA) ATON_SET_FIELD(REG, ATON_RECBUF_FORMAT2_MEMBMARK_LSB, ATON_RECBUF_FORMAT2_MEMBMARK_W, DATA) /** * Get the description of the MEMBMARK field of FORMAT2 register. * * \return the description of the MEMBMARK field of FORMAT2 register */ static inline const int8_t *ATON_RECBUF_FORMAT2_MEMBMARK_GetdDesc(void) { return (const int8_t *)ATON_RECBUF_FORMAT2_MEMBMARK_DESC; } /** * Read the content of the MEMBMARK field of the FORMAT2 register. * * \param[in] reg is the value of the FORMAT2 register * * \return the content of the MEMBMARK field belonging to FORMAT2 register */ static inline uint32_t ATON_RECBUF_FORMAT2_Get_MEMBMARK(uint32_t reg) { return ATON_RECBUF_FORMAT2_GET_MEMBMARK(reg); } /** * Write the content of the MEMBMARK field of the FORMAT2 register. * * \param[in] reg is the value of the FORMAT2 register * \param[in] data is 10-bit value that must be written to the field * * \return the new content of the MEMBMARK field belonging to FORMAT2 register */ static inline uint32_t ATON_RECBUF_FORMAT2_Set_MEMBMARK(uint32_t reg, uint32_t data) { return ATON_RECBUF_FORMAT2_SET_MEMBMARK(reg, data); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* EPOCHCTRL Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of EPOCHCTRL Unit instances. */ #define ATON_EPOCHCTRL_NUM 1 /** * \name Structures, macros and functions of the EPOCHCTRL Units */ /*@{*/ /** * Registers of the EPOCHCTRL Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e ADDR register (Blob fetch address). */ uint32_t ADDR; /** \e IRQ register (Interrupt status register). */ uint32_t IRQ; /** \e ENCR_LSB register (Encryption ID LSB (RO when CTRL.RUNNING)). */ uint32_t ENCR_LSB; /** \e ENCR_MSB register (Encryption ID MSB (RO when CTRL.RUNNING)). */ uint32_t ENCR_MSB; /** \e CID_CACHE register (Compartment ID / Cache register (RO when CTRL.RUNNING)). */ uint32_t CID_CACHE; /** \e LABEL register (Label register). */ uint32_t LABEL; /** \e BC register (Blob opcode counter). */ uint32_t BC; /** \e ACC register (Accumulator). */ uint32_t ACC; } ATON_EPOCHCTRL_t; /** Return the pointer to one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL(UNIT) ((ATON_EPOCHCTRL_t *)(intptr_t)ATON_EPOCHCTRL_BASE(UNIT)) /** Name of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_NAME(UNIT) \ (((UNIT) == 0) ? "EPOCHCTRL0" : "") /** Version of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_VERSION "1.1" /** Description of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_DESC(UNIT) \ (((UNIT) == 0) ? "Epoch Controller 0" : "") /** Base address of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_BASE(UNIT) \ (ATON_BASE + 0x1e000UL + ((UNIT) * 0x0UL)) /** Size in bytes of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_SIZE 0x1000UL /** * Get the name of one of the EPOCHCTRL Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) * * \return the name of Unit having index \e instance among the EPOCHCTRL Units */ static inline const int8_t *ATON_EPOCHCTRL_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"EPOCHCTRL0"; break; default: break; } return str; } /** * Get the description of one of the EPOCHCTRL Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) * * \return the description of Unit having index \e instance among the EPOCHCTRL Units */ static inline const int8_t *ATON_EPOCHCTRL_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Epoch Controller 0"; break; default: break; } return str; } /** * Get the version of the EPOCHCTRL Units. * * \return the version of the EPOCHCTRL Units */ static inline const int8_t *ATON_EPOCHCTRL_GetVersion(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION; } /** * Get the base address of one of the EPOCHCTRL Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) * * \return the base address of Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_GetBase(uint32_t instance) { return ATON_EPOCHCTRL_BASE(instance); } /** * Get the size in bytes of the EPOCHCTRL Units. * * \return the size in bytes of the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_GetSize(void) { return ATON_EPOCHCTRL_SIZE; } /* ****************************************************** CTRL register of one of the EPOCHCTRL Units ******************************************************* */ /** Offset of the CTRL register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_CTRL_DT \ (ATON_EPOCHCTRL_CTRL_EN_DT << ATON_EPOCHCTRL_CTRL_EN_LSB) | \ (ATON_EPOCHCTRL_CTRL_CLR_DT << ATON_EPOCHCTRL_CTRL_CLR_LSB) | \ (ATON_EPOCHCTRL_CTRL_AUTOCLR_DT << ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB) | \ (ATON_EPOCHCTRL_CTRL_SM_DT << ATON_EPOCHCTRL_CTRL_SM_LSB) | \ (ATON_EPOCHCTRL_CTRL_CONFCLR_DT << ATON_EPOCHCTRL_CTRL_CONFCLR_LSB) | \ (ATON_EPOCHCTRL_CTRL_RUNNING_DT << ATON_EPOCHCTRL_CTRL_RUNNING_LSB) /** Description of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_DESC "Control register" /** Address of the CTRL register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_CTRL_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_CTRL_OFFSET) /** Get the content of the CTRL register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_GetOffset(void) { return ATON_EPOCHCTRL_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CTRL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_CTRL_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get(uint32_t instance) { return ATON_EPOCHCTRL_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CTRL register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_EPOCHCTRL_CTRL_Set(uint32_t instance, uint32_t data) { ATON_EPOCHCTRL_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_EN_DESC "Enables the Epoch Controller" /** Offset of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_EPOCHCTRL_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_EPOCHCTRL_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_EN_LSB, ATON_EPOCHCTRL_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_EN_LSB, ATON_EPOCHCTRL_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_EN(uint32_t reg) { return ATON_EPOCHCTRL_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CLR_DESC "Clears all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_EPOCHCTRL_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_EPOCHCTRL_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CLR_LSB, ATON_EPOCHCTRL_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CLR_LSB, ATON_EPOCHCTRL_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_CLR(uint32_t reg) { return ATON_EPOCHCTRL_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- AUTOCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_DESC "Autoclear on stop (RO when CTRL.RUNNING)" /** Offset of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB 2UL /** Size in bits of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_W (1UL) /** Mask for retrieving the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_DT 0x0UL /** Access rights of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_AC "RW" /** Check whether access to the AUTOCLR field of the CTRL register is secured or not. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_S 0 /** Check whether access to the AUTOCLR field of the CTRL register is privileged or not. */ #define ATON_EPOCHCTRL_CTRL_AUTOCLR_P 0 /** Read the content of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_GET_AUTOCLR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB, ATON_EPOCHCTRL_CTRL_AUTOCLR_W) /** Modify the content of the AUTOCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SET_AUTOCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_AUTOCLR_LSB, ATON_EPOCHCTRL_CTRL_AUTOCLR_W, DATA) /** * Get the description of the AUTOCLR field of CTRL register. * * \return the description of the AUTOCLR field of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_AUTOCLR_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_AUTOCLR_DESC; } /** * Read the content of the AUTOCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the AUTOCLR field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_AUTOCLR(uint32_t reg) { return ATON_EPOCHCTRL_CTRL_GET_AUTOCLR(reg); } /** * Write the content of the AUTOCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the AUTOCLR field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_AUTOCLR(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CTRL_SET_AUTOCLR(reg, data); } /* ------------------------------------------------------------- SM field of the CTRL register -------------------------------------------------------------- */ /** Description of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SM_DESC "Step mode (RO when CTRL.RUNNING)" /** Offset of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SM_LSB 3UL /** Size in bits of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SM_W (1UL) /** Mask for retrieving the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SM_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SM_DT 0x0UL /** Access rights of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SM_AC "RW" /** Check whether access to the SM field of the CTRL register is secured or not. */ #define ATON_EPOCHCTRL_CTRL_SM_S 0 /** Check whether access to the SM field of the CTRL register is privileged or not. */ #define ATON_EPOCHCTRL_CTRL_SM_P 0 /** Read the content of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_GET_SM(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_SM_LSB, ATON_EPOCHCTRL_CTRL_SM_W) /** Modify the content of the SM field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SET_SM(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_SM_LSB, ATON_EPOCHCTRL_CTRL_SM_W, DATA) /** * Get the description of the SM field of CTRL register. * * \return the description of the SM field of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_SM_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_SM_DESC; } /** * Read the content of the SM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the SM field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_SM(uint32_t reg) { return ATON_EPOCHCTRL_CTRL_GET_SM(reg); } /** * Write the content of the SM field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SM field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_SM(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CTRL_SET_SM(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_DESC "Clear Configuration registers (autocleared) (RO when CTRL.RUNNING)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_EPOCHCTRL_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CONFCLR_LSB, ATON_EPOCHCTRL_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CTRL_CONFCLR_LSB, ATON_EPOCHCTRL_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_EPOCHCTRL_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CTRL_SET_CONFCLR(reg, data); } /* ----------------------------------------------------------- RUNNING field of the CTRL register ----------------------------------------------------------- */ /** Description of the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_DESC "Running condition" /** Offset of the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_LSB 31UL /** Size in bits of the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_W (1UL) /** Mask for retrieving the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_MASK ATON_FIELD_MASK(31UL, 1UL) /** Reset value of the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_DT 0x0UL /** Access rights of the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_AC "R" /** Check whether access to the RUNNING field of the CTRL register is secured or not. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_S 0 /** Check whether access to the RUNNING field of the CTRL register is privileged or not. */ #define ATON_EPOCHCTRL_CTRL_RUNNING_P 0 /** Read the content of the RUNNING field of the CTRL register. */ #define ATON_EPOCHCTRL_CTRL_GET_RUNNING(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CTRL_RUNNING_LSB, ATON_EPOCHCTRL_CTRL_RUNNING_W) /** * Get the description of the RUNNING field of CTRL register. * * \return the description of the RUNNING field of CTRL register */ static inline const int8_t *ATON_EPOCHCTRL_CTRL_RUNNING_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CTRL_RUNNING_DESC; } /** * Read the content of the RUNNING field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the RUNNING field belonging to CTRL register */ static inline uint32_t ATON_EPOCHCTRL_CTRL_Get_RUNNING(uint32_t reg) { return ATON_EPOCHCTRL_CTRL_GET_RUNNING(reg); } /* ***************************************************** VERSION register of one of the EPOCHCTRL Units ***************************************************** */ /** Offset of the VERSION register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_VERSION_DT \ (ATON_EPOCHCTRL_VERSION_TYPE_DT << ATON_EPOCHCTRL_VERSION_TYPE_LSB) | \ (ATON_EPOCHCTRL_VERSION_MINOR_DT << ATON_EPOCHCTRL_VERSION_MINOR_LSB) | \ (ATON_EPOCHCTRL_VERSION_MAJOR_DT << ATON_EPOCHCTRL_VERSION_MAJOR_LSB) | \ (ATON_EPOCHCTRL_VERSION_I_IRQ_DT << ATON_EPOCHCTRL_VERSION_I_IRQ_LSB) | \ (ATON_EPOCHCTRL_VERSION_ENCR_DT << ATON_EPOCHCTRL_VERSION_ENCR_LSB) | \ (ATON_EPOCHCTRL_VERSION_CACHE_DT << ATON_EPOCHCTRL_VERSION_CACHE_LSB) | \ (ATON_EPOCHCTRL_VERSION_CID_DT << ATON_EPOCHCTRL_VERSION_CID_LSB) | \ (ATON_EPOCHCTRL_VERSION_EXTSYNC_DT << ATON_EPOCHCTRL_VERSION_EXTSYNC_LSB) /** Description of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_DESC "Version register" /** Address of the VERSION register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_VERSION_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_VERSION_OFFSET) /** Get the content of the VERSION register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_GetOffset(void) { return ATON_EPOCHCTRL_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the VERSION register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_VERSION_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get(uint32_t instance) { return ATON_EPOCHCTRL_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_TYPE_DT 0x21UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_TYPE_LSB, ATON_EPOCHCTRL_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_TYPE(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MINOR_DT 0x1UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_MINOR_LSB, ATON_EPOCHCTRL_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_MINOR(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_MAJOR_LSB, ATON_EPOCHCTRL_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_MAJOR(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- I_IRQ field of the VERSION register ----------------------------------------------------------- */ /** Description of the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_DESC "Number of interrupt monitored" /** Offset of the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_LSB 16UL /** Size in bits of the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_W (8UL) /** Mask for retrieving the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_MASK ATON_FIELD_MASK(16UL, 8UL) /** Reset value of the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_DT 0x4UL /** Access rights of the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_AC "R" /** Check whether access to the I_IRQ field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_S 0 /** Check whether access to the I_IRQ field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_I_IRQ_P 0 /** Read the content of the I_IRQ field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_I_IRQ(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_I_IRQ_LSB, ATON_EPOCHCTRL_VERSION_I_IRQ_W) /** * Get the description of the I_IRQ field of VERSION register. * * \return the description of the I_IRQ field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_I_IRQ_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_I_IRQ_DESC; } /** * Read the content of the I_IRQ field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the I_IRQ field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_I_IRQ(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_I_IRQ(reg); } /* ----------------------------------------------------------- ENCR field of the VERSION register ----------------------------------------------------------- */ /** Description of the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_ENCR_DESC "Encription support" /** Offset of the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_ENCR_LSB 24UL /** Size in bits of the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_ENCR_W (1UL) /** Mask for retrieving the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_ENCR_MASK ATON_FIELD_MASK(24UL, 1UL) /** Reset value of the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_ENCR_DT 0x1UL /** Access rights of the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_ENCR_AC "R" /** Check whether access to the ENCR field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_ENCR_S 0 /** Check whether access to the ENCR field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_ENCR_P 0 /** Read the content of the ENCR field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_ENCR(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_ENCR_LSB, ATON_EPOCHCTRL_VERSION_ENCR_W) /** * Get the description of the ENCR field of VERSION register. * * \return the description of the ENCR field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_ENCR_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_ENCR_DESC; } /** * Read the content of the ENCR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the ENCR field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_ENCR(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_ENCR(reg); } /* ---------------------------------------------------------- CACHE field of the VERSION register ----------------------------------------------------------- */ /** Description of the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CACHE_DESC "Cache support" /** Offset of the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CACHE_LSB 25UL /** Size in bits of the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CACHE_W (1UL) /** Mask for retrieving the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CACHE_MASK ATON_FIELD_MASK(25UL, 1UL) /** Reset value of the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CACHE_DT 0x1UL /** Access rights of the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CACHE_AC "R" /** Check whether access to the CACHE field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_CACHE_S 0 /** Check whether access to the CACHE field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_CACHE_P 0 /** Read the content of the CACHE field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_CACHE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_CACHE_LSB, ATON_EPOCHCTRL_VERSION_CACHE_W) /** * Get the description of the CACHE field of VERSION register. * * \return the description of the CACHE field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_CACHE_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_CACHE_DESC; } /** * Read the content of the CACHE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the CACHE field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_CACHE(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_CACHE(reg); } /* ----------------------------------------------------------- CID field of the VERSION register ------------------------------------------------------------ */ /** Description of the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CID_DESC "Compartment ID support" /** Offset of the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CID_LSB 26UL /** Size in bits of the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CID_W (1UL) /** Mask for retrieving the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CID_MASK ATON_FIELD_MASK(26UL, 1UL) /** Reset value of the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CID_DT 0x1UL /** Access rights of the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_CID_AC "R" /** Check whether access to the CID field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_CID_S 0 /** Check whether access to the CID field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_CID_P 0 /** Read the content of the CID field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_CID(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_CID_LSB, ATON_EPOCHCTRL_VERSION_CID_W) /** * Get the description of the CID field of VERSION register. * * \return the description of the CID field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_CID_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_CID_DESC; } /** * Read the content of the CID field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the CID field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_CID(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_CID(reg); } /* --------------------------------------------------------- EXTSYNC field of the VERSION register ---------------------------------------------------------- */ /** Description of the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_DESC "External triggers support" /** Offset of the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_LSB 27UL /** Size in bits of the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_W (1UL) /** Mask for retrieving the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_MASK ATON_FIELD_MASK(27UL, 1UL) /** Reset value of the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_DT 0x1UL /** Access rights of the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_AC "R" /** Check whether access to the EXTSYNC field of the VERSION register is secured or not. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_S 0 /** Check whether access to the EXTSYNC field of the VERSION register is privileged or not. */ #define ATON_EPOCHCTRL_VERSION_EXTSYNC_P 0 /** Read the content of the EXTSYNC field of the VERSION register. */ #define ATON_EPOCHCTRL_VERSION_GET_EXTSYNC(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_VERSION_EXTSYNC_LSB, ATON_EPOCHCTRL_VERSION_EXTSYNC_W) /** * Get the description of the EXTSYNC field of VERSION register. * * \return the description of the EXTSYNC field of VERSION register */ static inline const int8_t *ATON_EPOCHCTRL_VERSION_EXTSYNC_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_VERSION_EXTSYNC_DESC; } /** * Read the content of the EXTSYNC field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the EXTSYNC field belonging to VERSION register */ static inline uint32_t ATON_EPOCHCTRL_VERSION_Get_EXTSYNC(uint32_t reg) { return ATON_EPOCHCTRL_VERSION_GET_EXTSYNC(reg); } /* ****************************************************** ADDR register of one of the EPOCHCTRL Units ******************************************************* */ /** Offset of the ADDR register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ADDR_OFFSET 0x8UL /** Reset value of the ADDR register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ADDR_DT \ (ATON_EPOCHCTRL_ADDR_REG_DT << ATON_EPOCHCTRL_ADDR_REG_LSB) /** Description of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_DESC "Blob fetch address" /** Address of the ADDR register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ADDR_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ADDR_OFFSET) /** Get the content of the ADDR register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ADDR_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ADDR_ADDR(UNIT))) /** Set the content of the ADDR register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ADDR_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ADDR_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ADDR register. * * \return the description of ADDR register */ static inline const int8_t *ATON_EPOCHCTRL_ADDR_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ADDR_DESC; } /** * Get the offset of the ADDR register. * * \return the offset of ADDR register */ static inline uint32_t ATON_EPOCHCTRL_ADDR_GetOffset(void) { return ATON_EPOCHCTRL_ADDR_OFFSET; } /** * Get the address of the ADDR register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ADDR register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of ADDR register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ADDR_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_ADDR_ADDR(instance); } /** * Read the content of the ADDR register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ADDR register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of ADDR register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ADDR_Get(uint32_t instance) { return ATON_EPOCHCTRL_ADDR_GET(instance); } /** * Write the content of the ADDR register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ADDR register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_EPOCHCTRL_ADDR_Set(uint32_t instance, uint32_t data) { ATON_EPOCHCTRL_ADDR_SET(instance, data); } /* ------------------------------------------------------------- REG field of the ADDR register ------------------------------------------------------------- */ /** Description of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_REG_DESC "Blob fetch address. Must be 64 bit aligned (values not 64 bits aligned will be refused) (RO when CTRL.RUNNING)" /** Offset of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_REG_LSB 0UL /** Size in bits of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_REG_W (32UL) /** Mask for retrieving the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_REG_DT 0x0UL /** Access rights of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_REG_AC "RW" /** Check whether access to the REG field of the ADDR register is secured or not. */ #define ATON_EPOCHCTRL_ADDR_REG_S 0 /** Check whether access to the REG field of the ADDR register is privileged or not. */ #define ATON_EPOCHCTRL_ADDR_REG_P 0 /** Read the content of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_GET_REG(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ADDR_REG_LSB, ATON_EPOCHCTRL_ADDR_REG_W) /** Modify the content of the REG field of the ADDR register. */ #define ATON_EPOCHCTRL_ADDR_SET_REG(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ADDR_REG_LSB, ATON_EPOCHCTRL_ADDR_REG_W, DATA) /** * Get the description of the REG field of ADDR register. * * \return the description of the REG field of ADDR register */ static inline const int8_t *ATON_EPOCHCTRL_ADDR_REG_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ADDR_REG_DESC; } /** * Read the content of the REG field of the ADDR register. * * \param[in] reg is the value of the ADDR register * * \return the content of the REG field belonging to ADDR register */ static inline uint32_t ATON_EPOCHCTRL_ADDR_Get_REG(uint32_t reg) { return ATON_EPOCHCTRL_ADDR_GET_REG(reg); } /** * Write the content of the REG field of the ADDR register. * * \param[in] reg is the value of the ADDR register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the REG field belonging to ADDR register */ static inline uint32_t ATON_EPOCHCTRL_ADDR_Set_REG(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_ADDR_SET_REG(reg, data); } /* ******************************************************* IRQ register of one of the EPOCHCTRL Units ******************************************************* */ /** Offset of the IRQ register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_IRQ_OFFSET 0xcUL /** Reset value of the IRQ register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_IRQ_DT \ (ATON_EPOCHCTRL_IRQ_IRQ_DT << ATON_EPOCHCTRL_IRQ_IRQ_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DT << ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_CONF_DT << ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_START_DT << ATON_EPOCHCTRL_IRQ_ERR_START_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DT << ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DT << ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_SRC_DT << ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB) | \ (ATON_EPOCHCTRL_IRQ_ERR_EVT_DT << ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB) | \ (ATON_EPOCHCTRL_IRQ_SM_DT << ATON_EPOCHCTRL_IRQ_SM_LSB) /** Description of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_DESC "Interrupt status register" /** Address of the IRQ register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_IRQ_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_IRQ_OFFSET) /** Get the content of the IRQ register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_IRQ_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_IRQ_ADDR(UNIT))) /** Set the content of the IRQ register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_IRQ_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_IRQ_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of IRQ register. * * \return the description of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_DESC; } /** * Get the offset of the IRQ register. * * \return the offset of IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_GetOffset(void) { return ATON_EPOCHCTRL_IRQ_OFFSET; } /** * Get the address of the IRQ register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the IRQ register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of IRQ register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_IRQ_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_IRQ_ADDR(instance); } /** * Read the content of the IRQ register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the IRQ register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of IRQ register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get(uint32_t instance) { return ATON_EPOCHCTRL_IRQ_GET(instance); } /** * Write the content of the IRQ register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the IRQ register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_EPOCHCTRL_IRQ_Set(uint32_t instance, uint32_t data) { ATON_EPOCHCTRL_IRQ_SET(instance, data); } /* ------------------------------------------------------------- IRQ field of the IRQ register -------------------------------------------------------------- */ /** Description of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_IRQ_DESC "Interrupt status (write 1 to acknowledge)" /** Offset of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_IRQ_LSB 0UL /** Size in bits of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_IRQ_W (1UL) /** Mask for retrieving the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_IRQ_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_IRQ_DT 0x0UL /** Access rights of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_IRQ_AC "RW" /** Check whether access to the IRQ field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_IRQ_S 0 /** Check whether access to the IRQ field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_IRQ_P 0 /** Read the content of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_IRQ(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_IRQ_LSB, ATON_EPOCHCTRL_IRQ_IRQ_W) /** Modify the content of the IRQ field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_IRQ(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_IRQ_LSB, ATON_EPOCHCTRL_IRQ_IRQ_W, DATA) /** * Get the description of the IRQ field of IRQ register. * * \return the description of the IRQ field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_IRQ_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_IRQ_DESC; } /** * Read the content of the IRQ field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the IRQ field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_IRQ(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_IRQ(reg); } /** * Write the content of the IRQ field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the IRQ field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_IRQ(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_IRQ(reg, data); } /* --------------------------------------------------------- ERR_BUSPORT field of the IRQ register ---------------------------------------------------------- */ /** Description of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DESC "Error on busport IF interrupt status (write 1 to acknowledge)" /** Offset of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB 1UL /** Size in bits of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_W (1UL) /** Mask for retrieving the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DT 0x0UL /** Access rights of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_AC "RW" /** Check whether access to the ERR_BUSPORT field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_S 0 /** Check whether access to the ERR_BUSPORT field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_P 0 /** Read the content of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_BUSPORT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_W) /** Modify the content of the ERR_BUSPORT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_BUSPORT(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_LSB, ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_W, DATA) /** * Get the description of the ERR_BUSPORT field of IRQ register. * * \return the description of the ERR_BUSPORT field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_BUSPORT_DESC; } /** * Read the content of the ERR_BUSPORT field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_BUSPORT field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_BUSPORT(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_BUSPORT(reg); } /** * Write the content of the ERR_BUSPORT field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_BUSPORT field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_BUSPORT(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_BUSPORT(reg, data); } /* ----------------------------------------------------------- ERR_CONF field of the IRQ register ----------------------------------------------------------- */ /** Description of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_DESC "Error on configuration IF interrupt status (write 1 to acknowledge)" /** Offset of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB 2UL /** Size in bits of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_W (1UL) /** Mask for retrieving the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_MASK ATON_FIELD_MASK(2UL, 1UL) /** Reset value of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_DT 0x0UL /** Access rights of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_AC "RW" /** Check whether access to the ERR_CONF field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_S 0 /** Check whether access to the ERR_CONF field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_CONF_P 0 /** Read the content of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_CONF(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB, ATON_EPOCHCTRL_IRQ_ERR_CONF_W) /** Modify the content of the ERR_CONF field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_CONF(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_CONF_LSB, ATON_EPOCHCTRL_IRQ_ERR_CONF_W, DATA) /** * Get the description of the ERR_CONF field of IRQ register. * * \return the description of the ERR_CONF field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_CONF_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_CONF_DESC; } /** * Read the content of the ERR_CONF field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_CONF field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_CONF(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_CONF(reg); } /** * Write the content of the ERR_CONF field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_CONF field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_CONF(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_CONF(reg, data); } /* ---------------------------------------------------------- ERR_START field of the IRQ register ----------------------------------------------------------- */ /** Description of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_DESC "Error on start (wrong blob ID) interrupt status (write 1 to acknowledge)" /** Offset of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_LSB 3UL /** Size in bits of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_W (1UL) /** Mask for retrieving the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_DT 0x0UL /** Access rights of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_AC "RW" /** Check whether access to the ERR_START field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_S 0 /** Check whether access to the ERR_START field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_START_P 0 /** Read the content of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_START(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_START_LSB, ATON_EPOCHCTRL_IRQ_ERR_START_W) /** Modify the content of the ERR_START field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_START(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_START_LSB, ATON_EPOCHCTRL_IRQ_ERR_START_W, DATA) /** * Get the description of the ERR_START field of IRQ register. * * \return the description of the ERR_START field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_START_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_START_DESC; } /** * Read the content of the ERR_START field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_START field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_START(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_START(reg); } /** * Write the content of the ERR_START field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_START field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_START(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_START(reg, data); } /* --------------------------------------------------------- ERR_TIMEOUT field of the IRQ register ---------------------------------------------------------- */ /** Description of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DESC "Error on timeout interrupt status (write 1 to acknowledge)" /** Offset of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB 4UL /** Size in bits of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_W (1UL) /** Mask for retrieving the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DT 0x0UL /** Access rights of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_AC "RW" /** Check whether access to the ERR_TIMEOUT field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_S 0 /** Check whether access to the ERR_TIMEOUT field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_P 0 /** Read the content of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_TIMEOUT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_W) /** Modify the content of the ERR_TIMEOUT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_TIMEOUT(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_LSB, ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_W, DATA) /** * Get the description of the ERR_TIMEOUT field of IRQ register. * * \return the description of the ERR_TIMEOUT field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_TIMEOUT_DESC; } /** * Read the content of the ERR_TIMEOUT field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_TIMEOUT field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_TIMEOUT(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_TIMEOUT(reg); } /** * Write the content of the ERR_TIMEOUT field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_TIMEOUT field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_TIMEOUT(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_TIMEOUT(reg, data); } /* ---------------------------------------------------------- ERR_UNKOP field of the IRQ register ----------------------------------------------------------- */ /** Description of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DESC "Error on unknown opcode intwerrupt status (write 1 to acknowledge)" /** Offset of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB 5UL /** Size in bits of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_W (1UL) /** Mask for retrieving the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DT 0x0UL /** Access rights of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_AC "RW" /** Check whether access to the ERR_UNKOP field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_S 0 /** Check whether access to the ERR_UNKOP field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_UNKOP_P 0 /** Read the content of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_UNKOP(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_W) /** Modify the content of the ERR_UNKOP field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_UNKOP(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_LSB, ATON_EPOCHCTRL_IRQ_ERR_UNKOP_W, DATA) /** * Get the description of the ERR_UNKOP field of IRQ register. * * \return the description of the ERR_UNKOP field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_UNKOP_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_UNKOP_DESC; } /** * Read the content of the ERR_UNKOP field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_UNKOP field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_UNKOP(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_UNKOP(reg); } /** * Write the content of the ERR_UNKOP field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_UNKOP field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_UNKOP(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_UNKOP(reg, data); } /* ----------------------------------------------------------- ERR_SRC field of the IRQ register ------------------------------------------------------------ */ /** Description of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_DESC "Error on not supported source selection in WFI or WFT opcode" /** Offset of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB 6UL /** Size in bits of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_W (1UL) /** Mask for retrieving the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_MASK ATON_FIELD_MASK(6UL, 1UL) /** Reset value of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_DT 0x0UL /** Access rights of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_AC "RW" /** Check whether access to the ERR_SRC field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_S 0 /** Check whether access to the ERR_SRC field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_SRC_P 0 /** Read the content of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_SRC(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB, ATON_EPOCHCTRL_IRQ_ERR_SRC_W) /** Modify the content of the ERR_SRC field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_SRC(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_SRC_LSB, ATON_EPOCHCTRL_IRQ_ERR_SRC_W, DATA) /** * Get the description of the ERR_SRC field of IRQ register. * * \return the description of the ERR_SRC field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_SRC_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_SRC_DESC; } /** * Read the content of the ERR_SRC field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_SRC field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_SRC(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_SRC(reg); } /** * Write the content of the ERR_SRC field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_SRC field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_SRC(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_SRC(reg, data); } /* ----------------------------------------------------------- ERR_EVT field of the IRQ register ------------------------------------------------------------ */ /** Description of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_DESC "Error on too big number of events to wait in WFT opcode" /** Offset of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB 7UL /** Size in bits of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_W (1UL) /** Mask for retrieving the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_MASK ATON_FIELD_MASK(7UL, 1UL) /** Reset value of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_DT 0x0UL /** Access rights of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_AC "RW" /** Check whether access to the ERR_EVT field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_S 0 /** Check whether access to the ERR_EVT field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_ERR_EVT_P 0 /** Read the content of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_ERR_EVT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB, ATON_EPOCHCTRL_IRQ_ERR_EVT_W) /** Modify the content of the ERR_EVT field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_ERR_EVT(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_ERR_EVT_LSB, ATON_EPOCHCTRL_IRQ_ERR_EVT_W, DATA) /** * Get the description of the ERR_EVT field of IRQ register. * * \return the description of the ERR_EVT field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_ERR_EVT_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_ERR_EVT_DESC; } /** * Read the content of the ERR_EVT field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the ERR_EVT field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_ERR_EVT(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_ERR_EVT(reg); } /** * Write the content of the ERR_EVT field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ERR_EVT field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_ERR_EVT(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_ERR_EVT(reg, data); } /* -------------------------------------------------------------- SM field of the IRQ register -------------------------------------------------------------- */ /** Description of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SM_DESC "Step mode trigger (write 1 to trigger, write 0 has no effect). Read 1 if the opcode is executing" /** Offset of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SM_LSB 16UL /** Size in bits of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SM_W (1UL) /** Mask for retrieving the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SM_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SM_DT 0x0UL /** Access rights of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SM_AC "RW" /** Check whether access to the SM field of the IRQ register is secured or not. */ #define ATON_EPOCHCTRL_IRQ_SM_S 0 /** Check whether access to the SM field of the IRQ register is privileged or not. */ #define ATON_EPOCHCTRL_IRQ_SM_P 0 /** Read the content of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_GET_SM(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_IRQ_SM_LSB, ATON_EPOCHCTRL_IRQ_SM_W) /** Modify the content of the SM field of the IRQ register. */ #define ATON_EPOCHCTRL_IRQ_SET_SM(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_IRQ_SM_LSB, ATON_EPOCHCTRL_IRQ_SM_W, DATA) /** * Get the description of the SM field of IRQ register. * * \return the description of the SM field of IRQ register */ static inline const int8_t *ATON_EPOCHCTRL_IRQ_SM_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_IRQ_SM_DESC; } /** * Read the content of the SM field of the IRQ register. * * \param[in] reg is the value of the IRQ register * * \return the content of the SM field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Get_SM(uint32_t reg) { return ATON_EPOCHCTRL_IRQ_GET_SM(reg); } /** * Write the content of the SM field of the IRQ register. * * \param[in] reg is the value of the IRQ register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SM field belonging to IRQ register */ static inline uint32_t ATON_EPOCHCTRL_IRQ_Set_SM(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_IRQ_SET_SM(reg, data); } /* **************************************************** ENCR_LSB register of one of the EPOCHCTRL Units ***************************************************** */ /** Offset of the ENCR_LSB register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ENCR_LSB_OFFSET 0x10UL /** Reset value of the ENCR_LSB register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ENCR_LSB_DT \ (ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DT << ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB) /** Description of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" /** Address of the ENCR_LSB register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ENCR_LSB_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ENCR_LSB_OFFSET) /** Get the content of the ENCR_LSB register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ENCR_LSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_LSB_ADDR(UNIT))) /** Set the content of the ENCR_LSB register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ENCR_LSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_LSB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ENCR_LSB register. * * \return the description of ENCR_LSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_LSB_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_LSB_DESC; } /** * Get the offset of the ENCR_LSB register. * * \return the offset of ENCR_LSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_GetOffset(void) { return ATON_EPOCHCTRL_ENCR_LSB_OFFSET; } /** * Get the address of the ENCR_LSB register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_LSB register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of ENCR_LSB register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_ENCR_LSB_ADDR(instance); } /** * Read the content of the ENCR_LSB register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_LSB register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of ENCR_LSB register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_Get(uint32_t instance) { return ATON_EPOCHCTRL_ENCR_LSB_GET(instance); } /** * Write the content of the ENCR_LSB register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_LSB register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_EPOCHCTRL_ENCR_LSB_Set(uint32_t instance, uint32_t data) { ATON_EPOCHCTRL_ENCR_LSB_SET(instance, data); } /* --------------------------------------------------------- ID_LSB field of the ENCR_LSB register ---------------------------------------------------------- */ /** Description of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DESC "Encryption ID LSB (RO when CTRL.RUNNING)" /** Offset of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB 0UL /** Size in bits of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_W (32UL) /** Mask for retrieving the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DT 0x0UL /** Access rights of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_AC "RW" /** Check whether access to the ID_LSB field of the ENCR_LSB register is secured or not. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_S 0 /** Check whether access to the ID_LSB field of the ENCR_LSB register is privileged or not. */ #define ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_P 0 /** Read the content of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_GET_ID_LSB(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_W) /** Modify the content of the ID_LSB field of the ENCR_LSB register. */ #define ATON_EPOCHCTRL_ENCR_LSB_SET_ID_LSB(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_LSB, ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_W, DATA) /** * Get the description of the ID_LSB field of ENCR_LSB register. * * \return the description of the ID_LSB field of ENCR_LSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_LSB_ID_LSB_DESC; } /** * Read the content of the ID_LSB field of the ENCR_LSB register. * * \param[in] reg is the value of the ENCR_LSB register * * \return the content of the ID_LSB field belonging to ENCR_LSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_Get_ID_LSB(uint32_t reg) { return ATON_EPOCHCTRL_ENCR_LSB_GET_ID_LSB(reg); } /** * Write the content of the ID_LSB field of the ENCR_LSB register. * * \param[in] reg is the value of the ENCR_LSB register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the ID_LSB field belonging to ENCR_LSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_LSB_Set_ID_LSB(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_ENCR_LSB_SET_ID_LSB(reg, data); } /* **************************************************** ENCR_MSB register of one of the EPOCHCTRL Units ***************************************************** */ /** Offset of the ENCR_MSB register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ENCR_MSB_OFFSET 0x14UL /** Reset value of the ENCR_MSB register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ENCR_MSB_DT \ (ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DT << ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB) | \ (ATON_EPOCHCTRL_ENCR_MSB_EN_DT << ATON_EPOCHCTRL_ENCR_MSB_EN_LSB) | \ (ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DT << ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB) | \ (ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DT << ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB) /** Description of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" /** Address of the ENCR_MSB register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ENCR_MSB_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ENCR_MSB_OFFSET) /** Get the content of the ENCR_MSB register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ENCR_MSB_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_MSB_ADDR(UNIT))) /** Set the content of the ENCR_MSB register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ENCR_MSB_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ENCR_MSB_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of ENCR_MSB register. * * \return the description of ENCR_MSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_DESC; } /** * Get the offset of the ENCR_MSB register. * * \return the offset of ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_GetOffset(void) { return ATON_EPOCHCTRL_ENCR_MSB_OFFSET; } /** * Get the address of the ENCR_MSB register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_MSB register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of ENCR_MSB register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_ENCR_MSB_ADDR(instance); } /** * Read the content of the ENCR_MSB register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_MSB register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of ENCR_MSB register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get(uint32_t instance) { return ATON_EPOCHCTRL_ENCR_MSB_GET(instance); } /** * Write the content of the ENCR_MSB register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ENCR_MSB register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_EPOCHCTRL_ENCR_MSB_Set(uint32_t instance, uint32_t data) { ATON_EPOCHCTRL_ENCR_MSB_SET(instance, data); } /* --------------------------------------------------------- ID_MSB field of the ENCR_MSB register ---------------------------------------------------------- */ /** Description of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DESC "Encryption ID MSB (RO when CTRL.RUNNING)" /** Offset of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB 0UL /** Size in bits of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_W (11UL) /** Mask for retrieving the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_MASK ATON_FIELD_MASK(0UL, 11UL) /** Reset value of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DT 0x0UL /** Access rights of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_AC "RW" /** Check whether access to the ID_MSB field of the ENCR_MSB register is secured or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_S 0 /** Check whether access to the ID_MSB field of the ENCR_MSB register is privileged or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_P 0 /** Read the content of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_GET_ID_MSB(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_W) /** Modify the content of the ID_MSB field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_SET_ID_MSB(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_LSB, ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_W, DATA) /** * Get the description of the ID_MSB field of ENCR_MSB register. * * \return the description of the ID_MSB field of ENCR_MSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_ID_MSB_DESC; } /** * Read the content of the ID_MSB field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the ID_MSB field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_ID_MSB(uint32_t reg) { return ATON_EPOCHCTRL_ENCR_MSB_GET_ID_MSB(reg); } /** * Write the content of the ID_MSB field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 11-bit value that must be written to the field * * \return the new content of the ID_MSB field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_ID_MSB(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_ENCR_MSB_SET_ID_MSB(reg, data); } /* ----------------------------------------------------------- EN field of the ENCR_MSB register ------------------------------------------------------------ */ /** Description of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_DESC "Encryption enable (RO when CTRL.RUNNING)" /** Offset of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_LSB 12UL /** Size in bits of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_W (1UL) /** Mask for retrieving the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_MASK ATON_FIELD_MASK(12UL, 1UL) /** Reset value of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_DT 0x0UL /** Access rights of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_AC "RW" /** Check whether access to the EN field of the ENCR_MSB register is secured or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_S 0 /** Check whether access to the EN field of the ENCR_MSB register is privileged or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_EN_P 0 /** Read the content of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_GET_EN(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_EN_LSB, ATON_EPOCHCTRL_ENCR_MSB_EN_W) /** Modify the content of the EN field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_EN_LSB, ATON_EPOCHCTRL_ENCR_MSB_EN_W, DATA) /** * Get the description of the EN field of ENCR_MSB register. * * \return the description of the EN field of ENCR_MSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_EN_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_EN_DESC; } /** * Read the content of the EN field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the EN field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_EN(uint32_t reg) { return ATON_EPOCHCTRL_ENCR_MSB_GET_EN(reg); } /** * Write the content of the EN field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_EN(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_ENCR_MSB_SET_EN(reg, data); } /* --------------------------------------------------------- ROUNDS field of the ENCR_MSB register ---------------------------------------------------------- */ /** Description of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DESC "Encryption number of rounds: 0->12, 1->9 (RO when CTRL.RUNNING)" /** Offset of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB 13UL /** Size in bits of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_W (1UL) /** Mask for retrieving the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_MASK ATON_FIELD_MASK(13UL, 1UL) /** Reset value of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DT 0x0UL /** Access rights of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_AC "RW" /** Check whether access to the ROUNDS field of the ENCR_MSB register is secured or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_S 0 /** Check whether access to the ROUNDS field of the ENCR_MSB register is privileged or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_P 0 /** Read the content of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_GET_ROUNDS(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_W) /** Modify the content of the ROUNDS field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_SET_ROUNDS(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_LSB, ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_W, DATA) /** * Get the description of the ROUNDS field of ENCR_MSB register. * * \return the description of the ROUNDS field of ENCR_MSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_ROUNDS_DESC; } /** * Read the content of the ROUNDS field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the ROUNDS field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_ROUNDS(uint32_t reg) { return ATON_EPOCHCTRL_ENCR_MSB_GET_ROUNDS(reg); } /** * Write the content of the ROUNDS field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ROUNDS field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_ROUNDS(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_ENCR_MSB_SET_ROUNDS(reg, data); } /* --------------------------------------------------------- KEY_SEL field of the ENCR_MSB register --------------------------------------------------------- */ /** Description of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DESC "Encryption key selection (RO when CTRL.RUNNING)" /** Offset of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB 14UL /** Size in bits of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_W (2UL) /** Mask for retrieving the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DT 0x0UL /** Access rights of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_AC "RW" /** Check whether access to the KEY_SEL field of the ENCR_MSB register is secured or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_S 0 /** Check whether access to the KEY_SEL field of the ENCR_MSB register is privileged or not. */ #define ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_P 0 /** Read the content of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_GET_KEY_SEL(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_W) /** Modify the content of the KEY_SEL field of the ENCR_MSB register. */ #define ATON_EPOCHCTRL_ENCR_MSB_SET_KEY_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_LSB, ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_W, DATA) /** * Get the description of the KEY_SEL field of ENCR_MSB register. * * \return the description of the KEY_SEL field of ENCR_MSB register */ static inline const int8_t *ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ENCR_MSB_KEY_SEL_DESC; } /** * Read the content of the KEY_SEL field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * * \return the content of the KEY_SEL field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Get_KEY_SEL(uint32_t reg) { return ATON_EPOCHCTRL_ENCR_MSB_GET_KEY_SEL(reg); } /** * Write the content of the KEY_SEL field of the ENCR_MSB register. * * \param[in] reg is the value of the ENCR_MSB register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the KEY_SEL field belonging to ENCR_MSB register */ static inline uint32_t ATON_EPOCHCTRL_ENCR_MSB_Set_KEY_SEL(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_ENCR_MSB_SET_KEY_SEL(reg, data); } /* **************************************************** CID_CACHE register of one of the EPOCHCTRL Units **************************************************** */ /** Offset of the CID_CACHE register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_CID_CACHE_OFFSET 0x18UL /** Reset value of the CID_CACHE register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_CID_CACHE_DT \ (ATON_EPOCHCTRL_CID_CACHE_CID_DT << ATON_EPOCHCTRL_CID_CACHE_CID_LSB) | \ (ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DT << ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB) | \ (ATON_EPOCHCTRL_CID_CACHE_ALLOC_DT << ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB) | \ (ATON_EPOCHCTRL_CID_CACHE_PFETCH_DT << ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB) | \ (ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DT << ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB) /** Description of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_DESC "Compartment ID / Cache register (RO when CTRL.RUNNING)" /** Address of the CID_CACHE register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_CID_CACHE_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_CID_CACHE_OFFSET) /** Get the content of the CID_CACHE register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_CID_CACHE_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CID_CACHE_ADDR(UNIT))) /** Set the content of the CID_CACHE register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_CID_CACHE_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_CID_CACHE_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CID_CACHE register. * * \return the description of CID_CACHE register */ static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_DESC; } /** * Get the offset of the CID_CACHE register. * * \return the offset of CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_GetOffset(void) { return ATON_EPOCHCTRL_CID_CACHE_OFFSET; } /** * Get the address of the CID_CACHE register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CID_CACHE register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CID_CACHE register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_CID_CACHE_ADDR(instance); } /** * Read the content of the CID_CACHE register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CID_CACHE register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CID_CACHE register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get(uint32_t instance) { return ATON_EPOCHCTRL_CID_CACHE_GET(instance); } /** * Write the content of the CID_CACHE register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the CID_CACHE register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_EPOCHCTRL_CID_CACHE_Set(uint32_t instance, uint32_t data) { ATON_EPOCHCTRL_CID_CACHE_SET(instance, data); } /* ---------------------------------------------------------- CID field of the CID_CACHE register ----------------------------------------------------------- */ /** Description of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_DESC "Compartment ID (RO when CTRL.RUNNING)" /** Offset of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_LSB 0UL /** Size in bits of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_W (3UL) /** Mask for retrieving the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_MASK ATON_FIELD_MASK(0UL, 3UL) /** Reset value of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_DT 0x0UL /** Access rights of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_AC "RW" /** Check whether access to the CID field of the CID_CACHE register is secured or not. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_S 0 /** Check whether access to the CID field of the CID_CACHE register is privileged or not. */ #define ATON_EPOCHCTRL_CID_CACHE_CID_P 0 /** Read the content of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_GET_CID(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CID_LSB, ATON_EPOCHCTRL_CID_CACHE_CID_W) /** Modify the content of the CID field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_SET_CID(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CID_LSB, ATON_EPOCHCTRL_CID_CACHE_CID_W, DATA) /** * Get the description of the CID field of CID_CACHE register. * * \return the description of the CID field of CID_CACHE register */ static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_CID_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_CID_DESC; } /** * Read the content of the CID field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the CID field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_CID(uint32_t reg) { return ATON_EPOCHCTRL_CID_CACHE_GET_CID(reg); } /** * Write the content of the CID field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 3-bit value that must be written to the field * * \return the new content of the CID field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_CID(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CID_CACHE_SET_CID(reg, data); } /* ------------------------------------------------------- CACHEABLE field of the CID_CACHE register -------------------------------------------------------- */ /** Description of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DESC "Cacheable (RO when CTRL.RUNNING)" /** Offset of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB 3UL /** Size in bits of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_W (1UL) /** Mask for retrieving the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_MASK ATON_FIELD_MASK(3UL, 1UL) /** Reset value of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DT 0x0UL /** Access rights of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_AC "RW" /** Check whether access to the CACHEABLE field of the CID_CACHE register is secured or not. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_S 0 /** Check whether access to the CACHEABLE field of the CID_CACHE register is privileged or not. */ #define ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_P 0 /** Read the content of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_GET_CACHEABLE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_W) /** Modify the content of the CACHEABLE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_SET_CACHEABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_LSB, ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_W, DATA) /** * Get the description of the CACHEABLE field of CID_CACHE register. * * \return the description of the CACHEABLE field of CID_CACHE register */ static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_CACHEABLE_DESC; } /** * Read the content of the CACHEABLE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the CACHEABLE field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_CACHEABLE(uint32_t reg) { return ATON_EPOCHCTRL_CID_CACHE_GET_CACHEABLE(reg); } /** * Write the content of the CACHEABLE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CACHEABLE field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_CACHEABLE(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CID_CACHE_SET_CACHEABLE(reg, data); } /* --------------------------------------------------------- ALLOC field of the CID_CACHE register ---------------------------------------------------------- */ /** Description of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_DESC "Allocate (RO when CTRL.RUNNING)" /** Offset of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB 4UL /** Size in bits of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_W (1UL) /** Mask for retrieving the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_MASK ATON_FIELD_MASK(4UL, 1UL) /** Reset value of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_DT 0x0UL /** Access rights of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_AC "RW" /** Check whether access to the ALLOC field of the CID_CACHE register is secured or not. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_S 0 /** Check whether access to the ALLOC field of the CID_CACHE register is privileged or not. */ #define ATON_EPOCHCTRL_CID_CACHE_ALLOC_P 0 /** Read the content of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_GET_ALLOC(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB, ATON_EPOCHCTRL_CID_CACHE_ALLOC_W) /** Modify the content of the ALLOC field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_SET_ALLOC(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_ALLOC_LSB, ATON_EPOCHCTRL_CID_CACHE_ALLOC_W, DATA) /** * Get the description of the ALLOC field of CID_CACHE register. * * \return the description of the ALLOC field of CID_CACHE register */ static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_ALLOC_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_ALLOC_DESC; } /** * Read the content of the ALLOC field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the ALLOC field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_ALLOC(uint32_t reg) { return ATON_EPOCHCTRL_CID_CACHE_GET_ALLOC(reg); } /** * Write the content of the ALLOC field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the ALLOC field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_ALLOC(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CID_CACHE_SET_ALLOC(reg, data); } /* --------------------------------------------------------- PFETCH field of the CID_CACHE register --------------------------------------------------------- */ /** Description of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_DESC "Prefetch (RO when CTRL.RUNNING)" /** Offset of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB 5UL /** Size in bits of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_W (1UL) /** Mask for retrieving the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_MASK ATON_FIELD_MASK(5UL, 1UL) /** Reset value of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_DT 0x0UL /** Access rights of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_AC "RW" /** Check whether access to the PFETCH field of the CID_CACHE register is secured or not. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_S 0 /** Check whether access to the PFETCH field of the CID_CACHE register is privileged or not. */ #define ATON_EPOCHCTRL_CID_CACHE_PFETCH_P 0 /** Read the content of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_GET_PFETCH(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB, ATON_EPOCHCTRL_CID_CACHE_PFETCH_W) /** Modify the content of the PFETCH field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_SET_PFETCH(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_PFETCH_LSB, ATON_EPOCHCTRL_CID_CACHE_PFETCH_W, DATA) /** * Get the description of the PFETCH field of CID_CACHE register. * * \return the description of the PFETCH field of CID_CACHE register */ static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_PFETCH_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_PFETCH_DESC; } /** * Read the content of the PFETCH field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the PFETCH field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_PFETCH(uint32_t reg) { return ATON_EPOCHCTRL_CID_CACHE_GET_PFETCH(reg); } /** * Write the content of the PFETCH field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the PFETCH field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_PFETCH(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CID_CACHE_SET_PFETCH(reg, data); } /* -------------------------------------------------------- LINESIZE field of the CID_CACHE register -------------------------------------------------------- */ /** Description of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DESC "Line size: 0 -> 64B, 1 -> 128B, 2 -> 256B, 3 -> 512B (RO when CTRL.RUNNING)" /** Offset of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB 6UL /** Size in bits of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_W (2UL) /** Mask for retrieving the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_MASK ATON_FIELD_MASK(6UL, 2UL) /** Reset value of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DT 0x0UL /** Access rights of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_AC "RW" /** Check whether access to the LINESIZE field of the CID_CACHE register is secured or not. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_S 0 /** Check whether access to the LINESIZE field of the CID_CACHE register is privileged or not. */ #define ATON_EPOCHCTRL_CID_CACHE_LINESIZE_P 0 /** Read the content of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_GET_LINESIZE(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_W) /** Modify the content of the LINESIZE field of the CID_CACHE register. */ #define ATON_EPOCHCTRL_CID_CACHE_SET_LINESIZE(REG, DATA) ATON_SET_FIELD(REG, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_LSB, ATON_EPOCHCTRL_CID_CACHE_LINESIZE_W, DATA) /** * Get the description of the LINESIZE field of CID_CACHE register. * * \return the description of the LINESIZE field of CID_CACHE register */ static inline const int8_t *ATON_EPOCHCTRL_CID_CACHE_LINESIZE_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_CID_CACHE_LINESIZE_DESC; } /** * Read the content of the LINESIZE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * * \return the content of the LINESIZE field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Get_LINESIZE(uint32_t reg) { return ATON_EPOCHCTRL_CID_CACHE_GET_LINESIZE(reg); } /** * Write the content of the LINESIZE field of the CID_CACHE register. * * \param[in] reg is the value of the CID_CACHE register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the LINESIZE field belonging to CID_CACHE register */ static inline uint32_t ATON_EPOCHCTRL_CID_CACHE_Set_LINESIZE(uint32_t reg, uint32_t data) { return ATON_EPOCHCTRL_CID_CACHE_SET_LINESIZE(reg, data); } /* ****************************************************** LABEL register of one of the EPOCHCTRL Units ****************************************************** */ /** Offset of the LABEL register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_LABEL_OFFSET 0x1cUL /** Reset value of the LABEL register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_LABEL_DT \ (ATON_EPOCHCTRL_LABEL_REG_DT << ATON_EPOCHCTRL_LABEL_REG_LSB) /** Description of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_DESC "Label register" /** Address of the LABEL register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_LABEL_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_LABEL_OFFSET) /** Get the content of the LABEL register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_LABEL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_LABEL_ADDR(UNIT))) /** * Get the description of LABEL register. * * \return the description of LABEL register */ static inline const int8_t *ATON_EPOCHCTRL_LABEL_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_LABEL_DESC; } /** * Get the offset of the LABEL register. * * \return the offset of LABEL register */ static inline uint32_t ATON_EPOCHCTRL_LABEL_GetOffset(void) { return ATON_EPOCHCTRL_LABEL_OFFSET; } /** * Get the address of the LABEL register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the LABEL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of LABEL register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_LABEL_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_LABEL_ADDR(instance); } /** * Read the content of the LABEL register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the LABEL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of LABEL register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_LABEL_Get(uint32_t instance) { return ATON_EPOCHCTRL_LABEL_GET(instance); } /* ------------------------------------------------------------ REG field of the LABEL register ------------------------------------------------------------- */ /** Description of the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_REG_DESC "Label value" /** Offset of the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_REG_LSB 0UL /** Size in bits of the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_REG_W (27UL) /** Mask for retrieving the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_REG_MASK ATON_FIELD_MASK(0UL, 27UL) /** Reset value of the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_REG_DT 0x0UL /** Access rights of the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_REG_AC "R" /** Check whether access to the REG field of the LABEL register is secured or not. */ #define ATON_EPOCHCTRL_LABEL_REG_S 0 /** Check whether access to the REG field of the LABEL register is privileged or not. */ #define ATON_EPOCHCTRL_LABEL_REG_P 0 /** Read the content of the REG field of the LABEL register. */ #define ATON_EPOCHCTRL_LABEL_GET_REG(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_LABEL_REG_LSB, ATON_EPOCHCTRL_LABEL_REG_W) /** * Get the description of the REG field of LABEL register. * * \return the description of the REG field of LABEL register */ static inline const int8_t *ATON_EPOCHCTRL_LABEL_REG_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_LABEL_REG_DESC; } /** * Read the content of the REG field of the LABEL register. * * \param[in] reg is the value of the LABEL register * * \return the content of the REG field belonging to LABEL register */ static inline uint32_t ATON_EPOCHCTRL_LABEL_Get_REG(uint32_t reg) { return ATON_EPOCHCTRL_LABEL_GET_REG(reg); } /* ******************************************************* BC register of one of the EPOCHCTRL Units ******************************************************** */ /** Offset of the BC register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_BC_OFFSET 0x20UL /** Reset value of the BC register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_BC_DT \ (ATON_EPOCHCTRL_BC_CNT_DT << ATON_EPOCHCTRL_BC_CNT_LSB) /** Description of the BC register. */ #define ATON_EPOCHCTRL_BC_DESC "Blob opcode counter" /** Address of the BC register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_BC_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_BC_OFFSET) /** Get the content of the BC register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_BC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_BC_ADDR(UNIT))) /** * Get the description of BC register. * * \return the description of BC register */ static inline const int8_t *ATON_EPOCHCTRL_BC_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_BC_DESC; } /** * Get the offset of the BC register. * * \return the offset of BC register */ static inline uint32_t ATON_EPOCHCTRL_BC_GetOffset(void) { return ATON_EPOCHCTRL_BC_OFFSET; } /** * Get the address of the BC register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the BC register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of BC register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_BC_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_BC_ADDR(instance); } /** * Read the content of the BC register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the BC register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of BC register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_BC_Get(uint32_t instance) { return ATON_EPOCHCTRL_BC_GET(instance); } /* -------------------------------------------------------------- CNT field of the BC register -------------------------------------------------------------- */ /** Description of the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_CNT_DESC "Blob opcode counter" /** Offset of the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_CNT_LSB 0UL /** Size in bits of the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_CNT_W (16UL) /** Mask for retrieving the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_CNT_MASK ATON_FIELD_MASK(0UL, 16UL) /** Reset value of the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_CNT_DT 0x0UL /** Access rights of the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_CNT_AC "R" /** Check whether access to the CNT field of the BC register is secured or not. */ #define ATON_EPOCHCTRL_BC_CNT_S 0 /** Check whether access to the CNT field of the BC register is privileged or not. */ #define ATON_EPOCHCTRL_BC_CNT_P 0 /** Read the content of the CNT field of the BC register. */ #define ATON_EPOCHCTRL_BC_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_BC_CNT_LSB, ATON_EPOCHCTRL_BC_CNT_W) /** * Get the description of the CNT field of BC register. * * \return the description of the CNT field of BC register */ static inline const int8_t *ATON_EPOCHCTRL_BC_CNT_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_BC_CNT_DESC; } /** * Read the content of the CNT field of the BC register. * * \param[in] reg is the value of the BC register * * \return the content of the CNT field belonging to BC register */ static inline uint32_t ATON_EPOCHCTRL_BC_Get_CNT(uint32_t reg) { return ATON_EPOCHCTRL_BC_GET_CNT(reg); } /* ******************************************************* ACC register of one of the EPOCHCTRL Units ******************************************************* */ /** Offset of the ACC register from the base address of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ACC_OFFSET 0x24UL /** Reset value of the ACC register of the EPOCHCTRL Unit. */ #define ATON_EPOCHCTRL_ACC_DT \ (ATON_EPOCHCTRL_ACC_REG_DT << ATON_EPOCHCTRL_ACC_REG_LSB) /** Description of the ACC register. */ #define ATON_EPOCHCTRL_ACC_DESC "Accumulator" /** Address of the ACC register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ACC_ADDR(UNIT) (ATON_EPOCHCTRL_BASE(UNIT) + ATON_EPOCHCTRL_ACC_OFFSET) /** Get the content of the ACC register of one of the EPOCHCTRL Units. */ #define ATON_EPOCHCTRL_ACC_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_EPOCHCTRL_ACC_ADDR(UNIT))) /** * Get the description of ACC register. * * \return the description of ACC register */ static inline const int8_t *ATON_EPOCHCTRL_ACC_GetDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ACC_DESC; } /** * Get the offset of the ACC register. * * \return the offset of ACC register */ static inline uint32_t ATON_EPOCHCTRL_ACC_GetOffset(void) { return ATON_EPOCHCTRL_ACC_OFFSET; } /** * Get the address of the ACC register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ACC register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of ACC register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ACC_GetAddr(uint32_t instance) { return ATON_EPOCHCTRL_ACC_ADDR(instance); } /** * Read the content of the ACC register. * * \param[in] instance is the index of the Unit (among the EPOCHCTRL Units) containing the ACC register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of ACC register belonging to Unit having index \e instance among the EPOCHCTRL Units */ static inline uint32_t ATON_EPOCHCTRL_ACC_Get(uint32_t instance) { return ATON_EPOCHCTRL_ACC_GET(instance); } /* ------------------------------------------------------------- REG field of the ACC register -------------------------------------------------------------- */ /** Description of the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_REG_DESC "Accumulator value" /** Offset of the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_REG_LSB 0UL /** Size in bits of the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_REG_W (32UL) /** Mask for retrieving the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_REG_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_REG_DT 0x0UL /** Access rights of the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_REG_AC "R" /** Check whether access to the REG field of the ACC register is secured or not. */ #define ATON_EPOCHCTRL_ACC_REG_S 0 /** Check whether access to the REG field of the ACC register is privileged or not. */ #define ATON_EPOCHCTRL_ACC_REG_P 0 /** Read the content of the REG field of the ACC register. */ #define ATON_EPOCHCTRL_ACC_GET_REG(REG) ATON_GET_FIELD(REG, ATON_EPOCHCTRL_ACC_REG_LSB, ATON_EPOCHCTRL_ACC_REG_W) /** * Get the description of the REG field of ACC register. * * \return the description of the REG field of ACC register */ static inline const int8_t *ATON_EPOCHCTRL_ACC_REG_GetdDesc(void) { return (const int8_t *)ATON_EPOCHCTRL_ACC_REG_DESC; } /** * Read the content of the REG field of the ACC register. * * \param[in] reg is the value of the ACC register * * \return the content of the REG field belonging to ACC register */ static inline uint32_t ATON_EPOCHCTRL_ACC_Get_REG(uint32_t reg) { return ATON_EPOCHCTRL_ACC_GET_REG(reg); } /*@}*/ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* */ /* DEBUG_TRACE Units */ /* */ /* ---------------------------------------------------------------------------------------------------------------------------------------------------------- */ /** Number of DEBUG_TRACE Unit instances. */ #define ATON_DEBUG_TRACE_NUM 1 /** * \name Structures, macros and functions of the DEBUG_TRACE Units */ /*@{*/ /** * Registers of the DEBUG_TRACE Units */ typedef volatile struct { /** \e CTRL register (Control register). */ uint32_t CTRL; /** \e VERSION register (Version register). */ uint32_t VERSION; /** \e LOW_ILINK_STATES register (Monitor Input Link 1). */ uint32_t LOW_ILINK_STATES; /** \e HIGH_ILINK_STATES register (Monitor Input Link 2). */ uint32_t HIGH_ILINK_STATES; /** \e LOW_OLINK_STATES register (Monitor Output Link 1). */ uint32_t LOW_OLINK_STATES; /** \e HIGH_OLINK_STATES register (Monitor Output Link 2). */ uint32_t HIGH_OLINK_STATES; // ...other registers that cannot be defined in this structure... } ATON_DEBUG_TRACE_t; /** Return the pointer to one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE(UNIT) ((ATON_DEBUG_TRACE_t *)(intptr_t)ATON_DEBUG_TRACE_BASE(UNIT)) /** Name of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_NAME(UNIT) \ (((UNIT) == 0) ? "DEBUG_TRACE0" : "") /** Version of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_VERSION "1.1" /** Description of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_DESC(UNIT) \ (((UNIT) == 0) ? "Debug Trace 0" : "") /** Base address of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_BASE(UNIT) \ (ATON_BASE + 0x1f000UL + ((UNIT) * 0x0UL)) /** Size in bytes of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_SIZE 0x1000UL /** * Get the name of one of the DEBUG_TRACE Units. * * \param[in] instance is the index of the Unit whose name must be returned (it must be idx \< 1<\em>) * * \return the name of Unit having index \e instance among the DEBUG_TRACE Units */ static inline const int8_t *ATON_DEBUG_TRACE_GetName(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"DEBUG_TRACE0"; break; default: break; } return str; } /** * Get the description of one of the DEBUG_TRACE Units. * * \param[in] instance is the index of the Unit whose description must be returned (it must be idx \< 1<\em>) * * \return the description of Unit having index \e instance among the DEBUG_TRACE Units */ static inline const int8_t *ATON_DEBUG_TRACE_GetDesc(uint32_t instance) { const int8_t *str = NULL; switch (instance) { case 0: str = (const int8_t *)"Debug Trace 0"; break; default: break; } return str; } /** * Get the version of the DEBUG_TRACE Units. * * \return the version of the DEBUG_TRACE Units */ static inline const int8_t *ATON_DEBUG_TRACE_GetVersion(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION; } /** * Get the base address of one of the DEBUG_TRACE Units. * * \param[in] instance is the index of the Unit whose base address must be returned (it must be idx \< 1<\em>) * * \return the base address of Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_GetBase(uint32_t instance) { return ATON_DEBUG_TRACE_BASE(instance); } /** * Get the size in bytes of the DEBUG_TRACE Units. * * \return the size in bytes of the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_GetSize(void) { return ATON_DEBUG_TRACE_SIZE; } /* ***************************************************** CTRL register of one of the DEBUG_TRACE Units ****************************************************** */ /** Offset of the CTRL register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_CTRL_OFFSET 0x0UL /** Reset value of the CTRL register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_CTRL_DT \ (ATON_DEBUG_TRACE_CTRL_EN_DT << ATON_DEBUG_TRACE_CTRL_EN_LSB) | \ (ATON_DEBUG_TRACE_CTRL_CLR_DT << ATON_DEBUG_TRACE_CTRL_CLR_LSB) | \ (ATON_DEBUG_TRACE_CTRL_CONFCLR_DT << ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB) /** Description of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_DESC "Control register" /** Address of the CTRL register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_CTRL_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_CTRL_OFFSET) /** Get the content of the CTRL register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_CTRL_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_CTRL_ADDR(UNIT))) /** Set the content of the CTRL register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_CTRL_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_CTRL_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of CTRL register. * * \return the description of CTRL register */ static inline const int8_t *ATON_DEBUG_TRACE_CTRL_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_CTRL_DESC; } /** * Get the offset of the CTRL register. * * \return the offset of CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_GetOffset(void) { return ATON_DEBUG_TRACE_CTRL_OFFSET; } /** * Get the address of the CTRL register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the CTRL register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of CTRL register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_CTRL_ADDR(instance); } /** * Read the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the CTRL register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of CTRL register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get(uint32_t instance) { return ATON_DEBUG_TRACE_CTRL_GET(instance); } /** * Write the content of the CTRL register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the CTRL register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_CTRL_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_CTRL_SET(instance, data); } /* ------------------------------------------------------------- EN field of the CTRL register -------------------------------------------------------------- */ /** Description of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_EN_DESC "Enable the Debug Trace Unit" /** Offset of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_EN_LSB 0UL /** Size in bits of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_EN_W (1UL) /** Mask for retrieving the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_EN_DT 0x0UL /** Access rights of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_EN_AC "RW" /** Check whether access to the EN field of the CTRL register is secured or not. */ #define ATON_DEBUG_TRACE_CTRL_EN_S 0 /** Check whether access to the EN field of the CTRL register is privileged or not. */ #define ATON_DEBUG_TRACE_CTRL_EN_P 0 /** Read the content of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_EN_LSB, ATON_DEBUG_TRACE_CTRL_EN_W) /** Modify the content of the EN field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_EN_LSB, ATON_DEBUG_TRACE_CTRL_EN_W, DATA) /** * Get the description of the EN field of CTRL register. * * \return the description of the EN field of CTRL register */ static inline const int8_t *ATON_DEBUG_TRACE_CTRL_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_CTRL_EN_DESC; } /** * Read the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the EN field belonging to CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_CTRL_GET_EN(reg); } /** * Write the content of the EN field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_CTRL_SET_EN(reg, data); } /* ------------------------------------------------------------- CLR field of the CTRL register ------------------------------------------------------------- */ /** Description of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CLR_DESC "Clear all pipeline registers" /** Offset of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CLR_LSB 1UL /** Size in bits of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CLR_W (1UL) /** Mask for retrieving the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CLR_MASK ATON_FIELD_MASK(1UL, 1UL) /** Reset value of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CLR_DT 0x0UL /** Access rights of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CLR_AC "RW" /** Check whether access to the CLR field of the CTRL register is secured or not. */ #define ATON_DEBUG_TRACE_CTRL_CLR_S 0 /** Check whether access to the CLR field of the CTRL register is privileged or not. */ #define ATON_DEBUG_TRACE_CTRL_CLR_P 0 /** Read the content of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_GET_CLR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CLR_LSB, ATON_DEBUG_TRACE_CTRL_CLR_W) /** Modify the content of the CLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_SET_CLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CLR_LSB, ATON_DEBUG_TRACE_CTRL_CLR_W, DATA) /** * Get the description of the CLR field of CTRL register. * * \return the description of the CLR field of CTRL register */ static inline const int8_t *ATON_DEBUG_TRACE_CTRL_CLR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_CTRL_CLR_DESC; } /** * Read the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get_CLR(uint32_t reg) { return ATON_DEBUG_TRACE_CTRL_GET_CLR(reg); } /** * Write the content of the CLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CLR field belonging to CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Set_CLR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_CTRL_SET_CLR(reg, data); } /* ----------------------------------------------------------- CONFCLR field of the CTRL register ----------------------------------------------------------- */ /** Description of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_DESC "Clear Configuration registers (auto cleared)" /** Offset of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB 30UL /** Size in bits of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_W (1UL) /** Mask for retrieving the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_MASK ATON_FIELD_MASK(30UL, 1UL) /** Reset value of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_DT 0x0UL /** Access rights of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_AC "RW" /** Check whether access to the CONFCLR field of the CTRL register is secured or not. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_S 0 /** Check whether access to the CONFCLR field of the CTRL register is privileged or not. */ #define ATON_DEBUG_TRACE_CTRL_CONFCLR_P 0 /** Read the content of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_GET_CONFCLR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB, ATON_DEBUG_TRACE_CTRL_CONFCLR_W) /** Modify the content of the CONFCLR field of the CTRL register. */ #define ATON_DEBUG_TRACE_CTRL_SET_CONFCLR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_CTRL_CONFCLR_LSB, ATON_DEBUG_TRACE_CTRL_CONFCLR_W, DATA) /** * Get the description of the CONFCLR field of CTRL register. * * \return the description of the CONFCLR field of CTRL register */ static inline const int8_t *ATON_DEBUG_TRACE_CTRL_CONFCLR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_CTRL_CONFCLR_DESC; } /** * Read the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * * \return the content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Get_CONFCLR(uint32_t reg) { return ATON_DEBUG_TRACE_CTRL_GET_CONFCLR(reg); } /** * Write the content of the CONFCLR field of the CTRL register. * * \param[in] reg is the value of the CTRL register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CONFCLR field belonging to CTRL register */ static inline uint32_t ATON_DEBUG_TRACE_CTRL_Set_CONFCLR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_CTRL_SET_CONFCLR(reg, data); } /* **************************************************** VERSION register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the VERSION register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_VERSION_OFFSET 0x4UL /** Reset value of the VERSION register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_VERSION_DT \ (ATON_DEBUG_TRACE_VERSION_TYPE_DT << ATON_DEBUG_TRACE_VERSION_TYPE_LSB) | \ (ATON_DEBUG_TRACE_VERSION_MINOR_DT << ATON_DEBUG_TRACE_VERSION_MINOR_LSB) | \ (ATON_DEBUG_TRACE_VERSION_MAJOR_DT << ATON_DEBUG_TRACE_VERSION_MAJOR_LSB) | \ (ATON_DEBUG_TRACE_VERSION_NRSIG_DT << ATON_DEBUG_TRACE_VERSION_NRSIG_LSB) | \ (ATON_DEBUG_TRACE_VERSION_NRTRIG_DT << ATON_DEBUG_TRACE_VERSION_NRTRIG_LSB) /** Description of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_DESC "Version register" /** Address of the VERSION register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_VERSION_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_VERSION_OFFSET) /** Get the content of the VERSION register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_VERSION_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_VERSION_ADDR(UNIT))) /** * Get the description of VERSION register. * * \return the description of VERSION register */ static inline const int8_t *ATON_DEBUG_TRACE_VERSION_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION_DESC; } /** * Get the offset of the VERSION register. * * \return the offset of VERSION register */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_GetOffset(void) { return ATON_DEBUG_TRACE_VERSION_OFFSET; } /** * Get the address of the VERSION register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the VERSION register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of VERSION register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_VERSION_ADDR(instance); } /** * Read the content of the VERSION register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the VERSION register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of VERSION register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get(uint32_t instance) { return ATON_DEBUG_TRACE_VERSION_GET(instance); } /* ----------------------------------------------------------- TYPE field of the VERSION register ----------------------------------------------------------- */ /** Description of the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_DESC "Block type" /** Offset of the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_LSB 0UL /** Size in bits of the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_W (8UL) /** Mask for retrieving the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_MASK ATON_FIELD_MASK(0UL, 8UL) /** Reset value of the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_DT 0x22UL /** Access rights of the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_AC "R" /** Check whether access to the TYPE field of the VERSION register is secured or not. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_S 0 /** Check whether access to the TYPE field of the VERSION register is privileged or not. */ #define ATON_DEBUG_TRACE_VERSION_TYPE_P 0 /** Read the content of the TYPE field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_GET_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_TYPE_LSB, ATON_DEBUG_TRACE_VERSION_TYPE_W) /** * Get the description of the TYPE field of VERSION register. * * \return the description of the TYPE field of VERSION register */ static inline const int8_t *ATON_DEBUG_TRACE_VERSION_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION_TYPE_DESC; } /** * Read the content of the TYPE field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the TYPE field belonging to VERSION register */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_VERSION_GET_TYPE(reg); } /* ---------------------------------------------------------- MINOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_DESC "Block minor version" /** Offset of the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_LSB 8UL /** Size in bits of the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_W (4UL) /** Mask for retrieving the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_MASK ATON_FIELD_MASK(8UL, 4UL) /** Reset value of the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_DT 0x1UL /** Access rights of the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_AC "R" /** Check whether access to the MINOR field of the VERSION register is secured or not. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_S 0 /** Check whether access to the MINOR field of the VERSION register is privileged or not. */ #define ATON_DEBUG_TRACE_VERSION_MINOR_P 0 /** Read the content of the MINOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_GET_MINOR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_MINOR_LSB, ATON_DEBUG_TRACE_VERSION_MINOR_W) /** * Get the description of the MINOR field of VERSION register. * * \return the description of the MINOR field of VERSION register */ static inline const int8_t *ATON_DEBUG_TRACE_VERSION_MINOR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION_MINOR_DESC; } /** * Read the content of the MINOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MINOR field belonging to VERSION register */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_MINOR(uint32_t reg) { return ATON_DEBUG_TRACE_VERSION_GET_MINOR(reg); } /* ---------------------------------------------------------- MAJOR field of the VERSION register ----------------------------------------------------------- */ /** Description of the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_DESC "Block major version" /** Offset of the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_LSB 12UL /** Size in bits of the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_W (4UL) /** Mask for retrieving the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_MASK ATON_FIELD_MASK(12UL, 4UL) /** Reset value of the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_DT 0x1UL /** Access rights of the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_AC "R" /** Check whether access to the MAJOR field of the VERSION register is secured or not. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_S 0 /** Check whether access to the MAJOR field of the VERSION register is privileged or not. */ #define ATON_DEBUG_TRACE_VERSION_MAJOR_P 0 /** Read the content of the MAJOR field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_GET_MAJOR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_MAJOR_LSB, ATON_DEBUG_TRACE_VERSION_MAJOR_W) /** * Get the description of the MAJOR field of VERSION register. * * \return the description of the MAJOR field of VERSION register */ static inline const int8_t *ATON_DEBUG_TRACE_VERSION_MAJOR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION_MAJOR_DESC; } /** * Read the content of the MAJOR field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the MAJOR field belonging to VERSION register */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_MAJOR(uint32_t reg) { return ATON_DEBUG_TRACE_VERSION_GET_MAJOR(reg); } /* ---------------------------------------------------------- NRSIG field of the VERSION register ----------------------------------------------------------- */ /** Description of the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_DESC "Number of observable signals" /** Offset of the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_LSB 16UL /** Size in bits of the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_W (10UL) /** Mask for retrieving the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_MASK ATON_FIELD_MASK(16UL, 10UL) /** Reset value of the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_DT 0x1ffUL /** Access rights of the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_AC "R" /** Check whether access to the NRSIG field of the VERSION register is secured or not. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_S 0 /** Check whether access to the NRSIG field of the VERSION register is privileged or not. */ #define ATON_DEBUG_TRACE_VERSION_NRSIG_P 0 /** Read the content of the NRSIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_GET_NRSIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_NRSIG_LSB, ATON_DEBUG_TRACE_VERSION_NRSIG_W) /** * Get the description of the NRSIG field of VERSION register. * * \return the description of the NRSIG field of VERSION register */ static inline const int8_t *ATON_DEBUG_TRACE_VERSION_NRSIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION_NRSIG_DESC; } /** * Read the content of the NRSIG field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the NRSIG field belonging to VERSION register */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_NRSIG(uint32_t reg) { return ATON_DEBUG_TRACE_VERSION_GET_NRSIG(reg); } /* ---------------------------------------------------------- NRTRIG field of the VERSION register ---------------------------------------------------------- */ /** Description of the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_DESC "Number of trigger events supported" /** Offset of the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_LSB 26UL /** Size in bits of the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_W (6UL) /** Mask for retrieving the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_MASK ATON_FIELD_MASK(26UL, 6UL) /** Reset value of the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_DT 0x8UL /** Access rights of the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_AC "R" /** Check whether access to the NRTRIG field of the VERSION register is secured or not. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_S 0 /** Check whether access to the NRTRIG field of the VERSION register is privileged or not. */ #define ATON_DEBUG_TRACE_VERSION_NRTRIG_P 0 /** Read the content of the NRTRIG field of the VERSION register. */ #define ATON_DEBUG_TRACE_VERSION_GET_NRTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_VERSION_NRTRIG_LSB, ATON_DEBUG_TRACE_VERSION_NRTRIG_W) /** * Get the description of the NRTRIG field of VERSION register. * * \return the description of the NRTRIG field of VERSION register */ static inline const int8_t *ATON_DEBUG_TRACE_VERSION_NRTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_VERSION_NRTRIG_DESC; } /** * Read the content of the NRTRIG field of the VERSION register. * * \param[in] reg is the value of the VERSION register * * \return the content of the NRTRIG field belonging to VERSION register */ static inline uint32_t ATON_DEBUG_TRACE_VERSION_Get_NRTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_VERSION_GET_NRTRIG(reg); } /* *********************************************** LOW_ILINK_STATES register of one of the DEBUG_TRACE Units ************************************************ */ /** Offset of the LOW_ILINK_STATES register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_OFFSET 0x8UL /** Reset value of the LOW_ILINK_STATES register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_DT \ (ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_LSB) /** Description of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_DESC "Monitor Input Link 1" /** Address of the LOW_ILINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_LOW_ILINK_STATES_OFFSET) /** Get the content of the LOW_ILINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_LOW_ILINK_STATES_ADDR(UNIT))) /** * Get the description of LOW_ILINK_STATES register. * * \return the description of LOW_ILINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_LOW_ILINK_STATES_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_LOW_ILINK_STATES_DESC; } /** * Get the offset of the LOW_ILINK_STATES register. * * \return the offset of LOW_ILINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_GetOffset(void) { return ATON_DEBUG_TRACE_LOW_ILINK_STATES_OFFSET; } /** * Get the address of the LOW_ILINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_ILINK_STATES register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of LOW_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_LOW_ILINK_STATES_ADDR(instance); } /** * Read the content of the LOW_ILINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_ILINK_STATES register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of LOW_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_Get(uint32_t instance) { return ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET(instance); } /* ----------------------------------------------------- STALLS field of the LOW_ILINK_STATES register ------------------------------------------------------ */ /** Description of the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DESC "Monitor Stream Switch input link stalls 0-31" /** Offset of the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_LSB 0UL /** Size in bits of the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_W (32UL) /** Mask for retrieving the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DT 0x0UL /** Access rights of the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_AC "R" /** Check whether access to the STALLS field of the LOW_ILINK_STATES register is secured or not. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_S 0 /** Check whether access to the STALLS field of the LOW_ILINK_STATES register is privileged or not. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_P 0 /** Read the content of the STALLS field of the LOW_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_W) /** * Get the description of the STALLS field of LOW_ILINK_STATES register. * * \return the description of the STALLS field of LOW_ILINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_LOW_ILINK_STATES_STALLS_DESC; } /** * Read the content of the STALLS field of the LOW_ILINK_STATES register. * * \param[in] reg is the value of the LOW_ILINK_STATES register * * \return the content of the STALLS field belonging to LOW_ILINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_LOW_ILINK_STATES_Get_STALLS(uint32_t reg) { return ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET_STALLS(reg); } /* *********************************************** HIGH_ILINK_STATES register of one of the DEBUG_TRACE Units *********************************************** */ /** Offset of the HIGH_ILINK_STATES register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_OFFSET 0xcUL /** Reset value of the HIGH_ILINK_STATES register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_DT \ (ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_LSB) /** Description of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_DESC "Monitor Input Link 2" /** Address of the HIGH_ILINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_HIGH_ILINK_STATES_OFFSET) /** Get the content of the HIGH_ILINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_HIGH_ILINK_STATES_ADDR(UNIT))) /** * Get the description of HIGH_ILINK_STATES register. * * \return the description of HIGH_ILINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_HIGH_ILINK_STATES_DESC; } /** * Get the offset of the HIGH_ILINK_STATES register. * * \return the offset of HIGH_ILINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GetOffset(void) { return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_OFFSET; } /** * Get the address of the HIGH_ILINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_ILINK_STATES register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of HIGH_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_ADDR(instance); } /** * Read the content of the HIGH_ILINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_ILINK_STATES register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of HIGH_ILINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_Get(uint32_t instance) { return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET(instance); } /* ----------------------------------------------------- STALLS field of the HIGH_ILINK_STATES register ----------------------------------------------------- */ /** Description of the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DESC "Monitor Stream Switch input link stalls 32-63" /** Offset of the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_LSB 0UL /** Size in bits of the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_W (32UL) /** Mask for retrieving the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DT 0x0UL /** Access rights of the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_AC "R" /** Check whether access to the STALLS field of the HIGH_ILINK_STATES register is secured or not. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_S 0 /** Check whether access to the STALLS field of the HIGH_ILINK_STATES register is privileged or not. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_P 0 /** Read the content of the STALLS field of the HIGH_ILINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_W) /** * Get the description of the STALLS field of HIGH_ILINK_STATES register. * * \return the description of the STALLS field of HIGH_ILINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_HIGH_ILINK_STATES_STALLS_DESC; } /** * Read the content of the STALLS field of the HIGH_ILINK_STATES register. * * \param[in] reg is the value of the HIGH_ILINK_STATES register * * \return the content of the STALLS field belonging to HIGH_ILINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_ILINK_STATES_Get_STALLS(uint32_t reg) { return ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET_STALLS(reg); } /* *********************************************** LOW_OLINK_STATES register of one of the DEBUG_TRACE Units ************************************************ */ /** Offset of the LOW_OLINK_STATES register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_OFFSET 0x10UL /** Reset value of the LOW_OLINK_STATES register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_DT \ (ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_LSB) /** Description of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_DESC "Monitor Output Link 1" /** Address of the LOW_OLINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_LOW_OLINK_STATES_OFFSET) /** Get the content of the LOW_OLINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_LOW_OLINK_STATES_ADDR(UNIT))) /** * Get the description of LOW_OLINK_STATES register. * * \return the description of LOW_OLINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_LOW_OLINK_STATES_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_LOW_OLINK_STATES_DESC; } /** * Get the offset of the LOW_OLINK_STATES register. * * \return the offset of LOW_OLINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_GetOffset(void) { return ATON_DEBUG_TRACE_LOW_OLINK_STATES_OFFSET; } /** * Get the address of the LOW_OLINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_OLINK_STATES register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of LOW_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_LOW_OLINK_STATES_ADDR(instance); } /** * Read the content of the LOW_OLINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the LOW_OLINK_STATES register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of LOW_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_Get(uint32_t instance) { return ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET(instance); } /* ----------------------------------------------------- STALLS field of the LOW_OLINK_STATES register ------------------------------------------------------ */ /** Description of the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DESC "Monitor Stream Switch output link stalls 0-31" /** Offset of the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_LSB 0UL /** Size in bits of the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_W (32UL) /** Mask for retrieving the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DT 0x0UL /** Access rights of the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_AC "R" /** Check whether access to the STALLS field of the LOW_OLINK_STATES register is secured or not. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_S 0 /** Check whether access to the STALLS field of the LOW_OLINK_STATES register is privileged or not. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_P 0 /** Read the content of the STALLS field of the LOW_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_W) /** * Get the description of the STALLS field of LOW_OLINK_STATES register. * * \return the description of the STALLS field of LOW_OLINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_LOW_OLINK_STATES_STALLS_DESC; } /** * Read the content of the STALLS field of the LOW_OLINK_STATES register. * * \param[in] reg is the value of the LOW_OLINK_STATES register * * \return the content of the STALLS field belonging to LOW_OLINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_LOW_OLINK_STATES_Get_STALLS(uint32_t reg) { return ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET_STALLS(reg); } /* *********************************************** HIGH_OLINK_STATES register of one of the DEBUG_TRACE Units *********************************************** */ /** Offset of the HIGH_OLINK_STATES register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_OFFSET 0x14UL /** Reset value of the HIGH_OLINK_STATES register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_DT \ (ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DT << ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_LSB) /** Description of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_DESC "Monitor Output Link 2" /** Address of the HIGH_OLINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_HIGH_OLINK_STATES_OFFSET) /** Get the content of the HIGH_OLINK_STATES register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_HIGH_OLINK_STATES_ADDR(UNIT))) /** * Get the description of HIGH_OLINK_STATES register. * * \return the description of HIGH_OLINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_HIGH_OLINK_STATES_DESC; } /** * Get the offset of the HIGH_OLINK_STATES register. * * \return the offset of HIGH_OLINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GetOffset(void) { return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_OFFSET; } /** * Get the address of the HIGH_OLINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_OLINK_STATES register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of HIGH_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_ADDR(instance); } /** * Read the content of the HIGH_OLINK_STATES register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the HIGH_OLINK_STATES register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of HIGH_OLINK_STATES register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_Get(uint32_t instance) { return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET(instance); } /* ----------------------------------------------------- STALLS field of the HIGH_OLINK_STATES register ----------------------------------------------------- */ /** Description of the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DESC "Monitor Stream Switch output link stalls 32-63" /** Offset of the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_LSB 0UL /** Size in bits of the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_W (32UL) /** Mask for retrieving the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DT 0x0UL /** Access rights of the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_AC "R" /** Check whether access to the STALLS field of the HIGH_OLINK_STATES register is secured or not. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_S 0 /** Check whether access to the STALLS field of the HIGH_OLINK_STATES register is privileged or not. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_P 0 /** Read the content of the STALLS field of the HIGH_OLINK_STATES register. */ #define ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET_STALLS(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_LSB, ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_W) /** * Get the description of the STALLS field of HIGH_OLINK_STATES register. * * \return the description of the STALLS field of HIGH_OLINK_STATES register */ static inline const int8_t *ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_HIGH_OLINK_STATES_STALLS_DESC; } /** * Read the content of the STALLS field of the HIGH_OLINK_STATES register. * * \param[in] reg is the value of the HIGH_OLINK_STATES register * * \return the content of the STALLS field belonging to HIGH_OLINK_STATES register */ static inline uint32_t ATON_DEBUG_TRACE_HIGH_OLINK_STATES_Get_STALLS(uint32_t reg) { return ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET_STALLS(reg); } /* **************************************************** TRIG_0 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_0 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_0_OFFSET 0x1cUL /** Reset value of the TRIG_0 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_0_DT \ (ATON_DEBUG_TRACE_TRIG_0_EN_DT << ATON_DEBUG_TRACE_TRIG_0_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_0_SEL_DT << ATON_DEBUG_TRACE_TRIG_0_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_0_OVR_DT << ATON_DEBUG_TRACE_TRIG_0_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_0_FILTER_DT << ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB) /** Description of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_DESC "Trigger Generation register 1" /** Address of the TRIG_0 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_0_OFFSET) /** Get the content of the TRIG_0 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT))) /** Set the content of the TRIG_0 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_0 register. * * \return the description of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_DESC; } /** * Get the offset of the TRIG_0 register. * * \return the offset of TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_0_OFFSET; } /** * Get the address of the TRIG_0 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_0_ADDR(instance); } /** * Read the content of the TRIG_0 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_0_GET(instance); } /** * Write the content of the TRIG_0 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_0_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_0_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_0 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_AC "RW" /** Check whether access to the EN field of the TRIG_0 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_S 0 /** Check whether access to the EN field of the TRIG_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_0_EN_P 0 /** Read the content of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EN_LSB, ATON_DEBUG_TRACE_TRIG_0_EN_W) /** Modify the content of the EN field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EN_LSB, ATON_DEBUG_TRACE_TRIG_0_EN_W, DATA) /** * Get the description of the EN field of TRIG_0 register. * * \return the description of the EN field of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_EN_DESC; } /** * Read the content of the EN field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * * \return the content of the EN field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_0_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_0_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_0 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_0 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_S 0 /** Check whether access to the SEL field of the TRIG_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_0_SEL_P 0 /** Read the content of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SEL_LSB, ATON_DEBUG_TRACE_TRIG_0_SEL_W) /** Modify the content of the SEL field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SEL_LSB, ATON_DEBUG_TRACE_TRIG_0_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_0 register. * * \return the description of the SEL field of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * * \return the content of the SEL field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_0_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_0_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_0 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_0 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_0_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_0_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_0 register. * * \return the description of the SWTRIG field of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * * \return the content of the SWTRIG field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_0_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_0_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_0 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_0 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_S 0 /** Check whether access to the OVR field of the TRIG_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_0_OVR_P 0 /** Read the content of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_OVR_LSB, ATON_DEBUG_TRACE_TRIG_0_OVR_W) /** Modify the content of the OVR field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_OVR_LSB, ATON_DEBUG_TRACE_TRIG_0_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_0 register. * * \return the description of the OVR field of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * * \return the content of the OVR field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_0_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_0_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_0 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_0 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_0 register. * * \return the description of the EVENT_TYPE field of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * * \return the content of the EVENT_TYPE field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_0_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_0_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_0 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_0 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_0_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_0_FILTER_W) /** Modify the content of the FILTER field of the TRIG_0 register. */ #define ATON_DEBUG_TRACE_TRIG_0_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_0_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_0_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_0 register. * * \return the description of the FILTER field of TRIG_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_0_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_0_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * * \return the content of the FILTER field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_0_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_0 register. * * \param[in] reg is the value of the TRIG_0 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_0 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_0_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_0_SET_FILTER(reg, data); } /* **************************************************** TRIG_1 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_1 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_1_OFFSET 0x20UL /** Reset value of the TRIG_1 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_1_DT \ (ATON_DEBUG_TRACE_TRIG_1_EN_DT << ATON_DEBUG_TRACE_TRIG_1_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_1_SEL_DT << ATON_DEBUG_TRACE_TRIG_1_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_1_OVR_DT << ATON_DEBUG_TRACE_TRIG_1_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_1_FILTER_DT << ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB) /** Description of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_DESC "Trigger Generation register 2" /** Address of the TRIG_1 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_1_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_1_OFFSET) /** Get the content of the TRIG_1 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_1_ADDR(UNIT))) /** Set the content of the TRIG_1 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_1 register. * * \return the description of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_DESC; } /** * Get the offset of the TRIG_1 register. * * \return the offset of TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_1_OFFSET; } /** * Get the address of the TRIG_1 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_1_ADDR(instance); } /** * Read the content of the TRIG_1 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_1_GET(instance); } /** * Write the content of the TRIG_1 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_1_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_1_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_1 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_AC "RW" /** Check whether access to the EN field of the TRIG_1 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_S 0 /** Check whether access to the EN field of the TRIG_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_1_EN_P 0 /** Read the content of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EN_LSB, ATON_DEBUG_TRACE_TRIG_1_EN_W) /** Modify the content of the EN field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EN_LSB, ATON_DEBUG_TRACE_TRIG_1_EN_W, DATA) /** * Get the description of the EN field of TRIG_1 register. * * \return the description of the EN field of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_EN_DESC; } /** * Read the content of the EN field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * * \return the content of the EN field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_1_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_1_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_1 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_1 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_S 0 /** Check whether access to the SEL field of the TRIG_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_1_SEL_P 0 /** Read the content of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SEL_LSB, ATON_DEBUG_TRACE_TRIG_1_SEL_W) /** Modify the content of the SEL field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SEL_LSB, ATON_DEBUG_TRACE_TRIG_1_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_1 register. * * \return the description of the SEL field of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * * \return the content of the SEL field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_1_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_1_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_1 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_1 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_1_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_1_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_1 register. * * \return the description of the SWTRIG field of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * * \return the content of the SWTRIG field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_1_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_1_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_1 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_1 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_S 0 /** Check whether access to the OVR field of the TRIG_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_1_OVR_P 0 /** Read the content of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_OVR_LSB, ATON_DEBUG_TRACE_TRIG_1_OVR_W) /** Modify the content of the OVR field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_OVR_LSB, ATON_DEBUG_TRACE_TRIG_1_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_1 register. * * \return the description of the OVR field of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * * \return the content of the OVR field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_1_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_1_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_1 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_1 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_1 register. * * \return the description of the EVENT_TYPE field of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * * \return the content of the EVENT_TYPE field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_1_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_1_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_1 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_1 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_1_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_1_FILTER_W) /** Modify the content of the FILTER field of the TRIG_1 register. */ #define ATON_DEBUG_TRACE_TRIG_1_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_1_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_1_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_1 register. * * \return the description of the FILTER field of TRIG_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_1_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_1_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * * \return the content of the FILTER field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_1_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_1 register. * * \param[in] reg is the value of the TRIG_1 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_1 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_1_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_1_SET_FILTER(reg, data); } /* **************************************************** TRIG_2 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_2 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_2_OFFSET 0x24UL /** Reset value of the TRIG_2 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_2_DT \ (ATON_DEBUG_TRACE_TRIG_2_EN_DT << ATON_DEBUG_TRACE_TRIG_2_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_2_SEL_DT << ATON_DEBUG_TRACE_TRIG_2_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_2_OVR_DT << ATON_DEBUG_TRACE_TRIG_2_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_2_FILTER_DT << ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB) /** Description of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_DESC "Trigger Generation register 3" /** Address of the TRIG_2 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_2_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_2_OFFSET) /** Get the content of the TRIG_2 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_2_ADDR(UNIT))) /** Set the content of the TRIG_2 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_2 register. * * \return the description of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_DESC; } /** * Get the offset of the TRIG_2 register. * * \return the offset of TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_2_OFFSET; } /** * Get the address of the TRIG_2 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_2 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_2_ADDR(instance); } /** * Read the content of the TRIG_2 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_2 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_2_GET(instance); } /** * Write the content of the TRIG_2 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_2 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_2_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_2_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_2 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_AC "RW" /** Check whether access to the EN field of the TRIG_2 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_S 0 /** Check whether access to the EN field of the TRIG_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_2_EN_P 0 /** Read the content of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EN_LSB, ATON_DEBUG_TRACE_TRIG_2_EN_W) /** Modify the content of the EN field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EN_LSB, ATON_DEBUG_TRACE_TRIG_2_EN_W, DATA) /** * Get the description of the EN field of TRIG_2 register. * * \return the description of the EN field of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_EN_DESC; } /** * Read the content of the EN field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * * \return the content of the EN field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_2_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_2_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_2 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_2 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_S 0 /** Check whether access to the SEL field of the TRIG_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_2_SEL_P 0 /** Read the content of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SEL_LSB, ATON_DEBUG_TRACE_TRIG_2_SEL_W) /** Modify the content of the SEL field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SEL_LSB, ATON_DEBUG_TRACE_TRIG_2_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_2 register. * * \return the description of the SEL field of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * * \return the content of the SEL field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_2_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_2_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_2 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_2 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_2_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_2_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_2 register. * * \return the description of the SWTRIG field of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * * \return the content of the SWTRIG field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_2_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_2_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_2 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_2 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_S 0 /** Check whether access to the OVR field of the TRIG_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_2_OVR_P 0 /** Read the content of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_OVR_LSB, ATON_DEBUG_TRACE_TRIG_2_OVR_W) /** Modify the content of the OVR field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_OVR_LSB, ATON_DEBUG_TRACE_TRIG_2_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_2 register. * * \return the description of the OVR field of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * * \return the content of the OVR field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_2_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_2_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_2 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_2 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_2 register. * * \return the description of the EVENT_TYPE field of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * * \return the content of the EVENT_TYPE field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_2_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_2_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_2 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_2 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_2_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_2_FILTER_W) /** Modify the content of the FILTER field of the TRIG_2 register. */ #define ATON_DEBUG_TRACE_TRIG_2_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_2_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_2_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_2 register. * * \return the description of the FILTER field of TRIG_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_2_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_2_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * * \return the content of the FILTER field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_2_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_2 register. * * \param[in] reg is the value of the TRIG_2 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_2 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_2_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_2_SET_FILTER(reg, data); } /* **************************************************** TRIG_3 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_3 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_3_OFFSET 0x28UL /** Reset value of the TRIG_3 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_3_DT \ (ATON_DEBUG_TRACE_TRIG_3_EN_DT << ATON_DEBUG_TRACE_TRIG_3_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_3_SEL_DT << ATON_DEBUG_TRACE_TRIG_3_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_3_OVR_DT << ATON_DEBUG_TRACE_TRIG_3_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_3_FILTER_DT << ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB) /** Description of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_DESC "Trigger Generation register 4" /** Address of the TRIG_3 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_3_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_3_OFFSET) /** Get the content of the TRIG_3 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_3_ADDR(UNIT))) /** Set the content of the TRIG_3 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_3_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_3 register. * * \return the description of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_DESC; } /** * Get the offset of the TRIG_3 register. * * \return the offset of TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_3_OFFSET; } /** * Get the address of the TRIG_3 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_3 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_3_ADDR(instance); } /** * Read the content of the TRIG_3 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_3 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_3_GET(instance); } /** * Write the content of the TRIG_3 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_3 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_3_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_3_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_3 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_AC "RW" /** Check whether access to the EN field of the TRIG_3 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_S 0 /** Check whether access to the EN field of the TRIG_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_3_EN_P 0 /** Read the content of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EN_LSB, ATON_DEBUG_TRACE_TRIG_3_EN_W) /** Modify the content of the EN field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EN_LSB, ATON_DEBUG_TRACE_TRIG_3_EN_W, DATA) /** * Get the description of the EN field of TRIG_3 register. * * \return the description of the EN field of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_EN_DESC; } /** * Read the content of the EN field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * * \return the content of the EN field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_3_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_3_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_3 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_3 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_S 0 /** Check whether access to the SEL field of the TRIG_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_3_SEL_P 0 /** Read the content of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SEL_LSB, ATON_DEBUG_TRACE_TRIG_3_SEL_W) /** Modify the content of the SEL field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SEL_LSB, ATON_DEBUG_TRACE_TRIG_3_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_3 register. * * \return the description of the SEL field of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * * \return the content of the SEL field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_3_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_3_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_3 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_3 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_3_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_3_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_3 register. * * \return the description of the SWTRIG field of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * * \return the content of the SWTRIG field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_3_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_3_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_3 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_3 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_S 0 /** Check whether access to the OVR field of the TRIG_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_3_OVR_P 0 /** Read the content of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_OVR_LSB, ATON_DEBUG_TRACE_TRIG_3_OVR_W) /** Modify the content of the OVR field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_OVR_LSB, ATON_DEBUG_TRACE_TRIG_3_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_3 register. * * \return the description of the OVR field of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * * \return the content of the OVR field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_3_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_3_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_3 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_3 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_3 register. * * \return the description of the EVENT_TYPE field of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * * \return the content of the EVENT_TYPE field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_3_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_3_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_3 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_3 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_3_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_3_FILTER_W) /** Modify the content of the FILTER field of the TRIG_3 register. */ #define ATON_DEBUG_TRACE_TRIG_3_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_3_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_3_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_3 register. * * \return the description of the FILTER field of TRIG_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_3_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_3_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * * \return the content of the FILTER field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_3_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_3 register. * * \param[in] reg is the value of the TRIG_3 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_3 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_3_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_3_SET_FILTER(reg, data); } /* **************************************************** TRIG_4 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_4 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_4_OFFSET 0x2cUL /** Reset value of the TRIG_4 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_4_DT \ (ATON_DEBUG_TRACE_TRIG_4_EN_DT << ATON_DEBUG_TRACE_TRIG_4_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_4_SEL_DT << ATON_DEBUG_TRACE_TRIG_4_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_4_OVR_DT << ATON_DEBUG_TRACE_TRIG_4_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_4_FILTER_DT << ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB) /** Description of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_DESC "Trigger Generation register 5" /** Address of the TRIG_4 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_4_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_4_OFFSET) /** Get the content of the TRIG_4 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_4_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_4_ADDR(UNIT))) /** Set the content of the TRIG_4 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_4_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_4_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_4 register. * * \return the description of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_DESC; } /** * Get the offset of the TRIG_4 register. * * \return the offset of TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_4_OFFSET; } /** * Get the address of the TRIG_4 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_4 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_4_ADDR(instance); } /** * Read the content of the TRIG_4 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_4 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_4_GET(instance); } /** * Write the content of the TRIG_4 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_4 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_4_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_4_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_4 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_AC "RW" /** Check whether access to the EN field of the TRIG_4 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_S 0 /** Check whether access to the EN field of the TRIG_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_4_EN_P 0 /** Read the content of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EN_LSB, ATON_DEBUG_TRACE_TRIG_4_EN_W) /** Modify the content of the EN field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EN_LSB, ATON_DEBUG_TRACE_TRIG_4_EN_W, DATA) /** * Get the description of the EN field of TRIG_4 register. * * \return the description of the EN field of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_EN_DESC; } /** * Read the content of the EN field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * * \return the content of the EN field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_4_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_4_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_4 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_4 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_S 0 /** Check whether access to the SEL field of the TRIG_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_4_SEL_P 0 /** Read the content of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SEL_LSB, ATON_DEBUG_TRACE_TRIG_4_SEL_W) /** Modify the content of the SEL field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SEL_LSB, ATON_DEBUG_TRACE_TRIG_4_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_4 register. * * \return the description of the SEL field of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * * \return the content of the SEL field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_4_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_4_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_4 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_4 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_4_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_4_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_4 register. * * \return the description of the SWTRIG field of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * * \return the content of the SWTRIG field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_4_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_4_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_4 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_4 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_S 0 /** Check whether access to the OVR field of the TRIG_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_4_OVR_P 0 /** Read the content of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_OVR_LSB, ATON_DEBUG_TRACE_TRIG_4_OVR_W) /** Modify the content of the OVR field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_OVR_LSB, ATON_DEBUG_TRACE_TRIG_4_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_4 register. * * \return the description of the OVR field of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * * \return the content of the OVR field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_4_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_4_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_4 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_4 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_4 register. * * \return the description of the EVENT_TYPE field of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * * \return the content of the EVENT_TYPE field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_4_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_4_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_4 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_4 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_4_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_4_FILTER_W) /** Modify the content of the FILTER field of the TRIG_4 register. */ #define ATON_DEBUG_TRACE_TRIG_4_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_4_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_4_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_4 register. * * \return the description of the FILTER field of TRIG_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_4_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_4_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * * \return the content of the FILTER field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_4_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_4 register. * * \param[in] reg is the value of the TRIG_4 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_4 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_4_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_4_SET_FILTER(reg, data); } /* **************************************************** TRIG_5 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_5 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_5_OFFSET 0x30UL /** Reset value of the TRIG_5 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_5_DT \ (ATON_DEBUG_TRACE_TRIG_5_EN_DT << ATON_DEBUG_TRACE_TRIG_5_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_5_SEL_DT << ATON_DEBUG_TRACE_TRIG_5_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_5_OVR_DT << ATON_DEBUG_TRACE_TRIG_5_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_5_FILTER_DT << ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB) /** Description of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_DESC "Trigger Generation register 6" /** Address of the TRIG_5 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_5_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_5_OFFSET) /** Get the content of the TRIG_5 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_5_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_5_ADDR(UNIT))) /** Set the content of the TRIG_5 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_5_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_5_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_5 register. * * \return the description of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_DESC; } /** * Get the offset of the TRIG_5 register. * * \return the offset of TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_5_OFFSET; } /** * Get the address of the TRIG_5 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_5 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_5_ADDR(instance); } /** * Read the content of the TRIG_5 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_5 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_5_GET(instance); } /** * Write the content of the TRIG_5 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_5 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_5_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_5_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_5 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_AC "RW" /** Check whether access to the EN field of the TRIG_5 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_S 0 /** Check whether access to the EN field of the TRIG_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_5_EN_P 0 /** Read the content of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EN_LSB, ATON_DEBUG_TRACE_TRIG_5_EN_W) /** Modify the content of the EN field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EN_LSB, ATON_DEBUG_TRACE_TRIG_5_EN_W, DATA) /** * Get the description of the EN field of TRIG_5 register. * * \return the description of the EN field of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_EN_DESC; } /** * Read the content of the EN field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * * \return the content of the EN field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_5_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_5_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_5 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_5 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_S 0 /** Check whether access to the SEL field of the TRIG_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_5_SEL_P 0 /** Read the content of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SEL_LSB, ATON_DEBUG_TRACE_TRIG_5_SEL_W) /** Modify the content of the SEL field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SEL_LSB, ATON_DEBUG_TRACE_TRIG_5_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_5 register. * * \return the description of the SEL field of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * * \return the content of the SEL field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_5_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_5_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_5 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_5 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_5_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_5_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_5 register. * * \return the description of the SWTRIG field of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * * \return the content of the SWTRIG field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_5_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_5_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_5 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_5 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_S 0 /** Check whether access to the OVR field of the TRIG_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_5_OVR_P 0 /** Read the content of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_OVR_LSB, ATON_DEBUG_TRACE_TRIG_5_OVR_W) /** Modify the content of the OVR field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_OVR_LSB, ATON_DEBUG_TRACE_TRIG_5_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_5 register. * * \return the description of the OVR field of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * * \return the content of the OVR field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_5_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_5_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_5 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_5 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_5 register. * * \return the description of the EVENT_TYPE field of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * * \return the content of the EVENT_TYPE field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_5_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_5_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_5 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_5 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_5_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_5_FILTER_W) /** Modify the content of the FILTER field of the TRIG_5 register. */ #define ATON_DEBUG_TRACE_TRIG_5_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_5_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_5_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_5 register. * * \return the description of the FILTER field of TRIG_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_5_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_5_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * * \return the content of the FILTER field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_5_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_5 register. * * \param[in] reg is the value of the TRIG_5 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_5 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_5_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_5_SET_FILTER(reg, data); } /* **************************************************** TRIG_6 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_6 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_6_OFFSET 0x34UL /** Reset value of the TRIG_6 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_6_DT \ (ATON_DEBUG_TRACE_TRIG_6_EN_DT << ATON_DEBUG_TRACE_TRIG_6_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_6_SEL_DT << ATON_DEBUG_TRACE_TRIG_6_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_6_OVR_DT << ATON_DEBUG_TRACE_TRIG_6_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_6_FILTER_DT << ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB) /** Description of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_DESC "Trigger Generation register 7" /** Address of the TRIG_6 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_6_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_6_OFFSET) /** Get the content of the TRIG_6 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_6_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_6_ADDR(UNIT))) /** Set the content of the TRIG_6 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_6_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_6_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_6 register. * * \return the description of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_DESC; } /** * Get the offset of the TRIG_6 register. * * \return the offset of TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_6_OFFSET; } /** * Get the address of the TRIG_6 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_6 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_6_ADDR(instance); } /** * Read the content of the TRIG_6 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_6 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_6_GET(instance); } /** * Write the content of the TRIG_6 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_6 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_6_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_6_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_6 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_AC "RW" /** Check whether access to the EN field of the TRIG_6 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_S 0 /** Check whether access to the EN field of the TRIG_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_6_EN_P 0 /** Read the content of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EN_LSB, ATON_DEBUG_TRACE_TRIG_6_EN_W) /** Modify the content of the EN field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EN_LSB, ATON_DEBUG_TRACE_TRIG_6_EN_W, DATA) /** * Get the description of the EN field of TRIG_6 register. * * \return the description of the EN field of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_EN_DESC; } /** * Read the content of the EN field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * * \return the content of the EN field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_6_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_6_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_6 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_6 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_S 0 /** Check whether access to the SEL field of the TRIG_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_6_SEL_P 0 /** Read the content of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SEL_LSB, ATON_DEBUG_TRACE_TRIG_6_SEL_W) /** Modify the content of the SEL field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SEL_LSB, ATON_DEBUG_TRACE_TRIG_6_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_6 register. * * \return the description of the SEL field of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * * \return the content of the SEL field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_6_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_6_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_6 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_6 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_6_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_6_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_6 register. * * \return the description of the SWTRIG field of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * * \return the content of the SWTRIG field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_6_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_6_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_6 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_6 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_S 0 /** Check whether access to the OVR field of the TRIG_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_6_OVR_P 0 /** Read the content of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_OVR_LSB, ATON_DEBUG_TRACE_TRIG_6_OVR_W) /** Modify the content of the OVR field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_OVR_LSB, ATON_DEBUG_TRACE_TRIG_6_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_6 register. * * \return the description of the OVR field of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * * \return the content of the OVR field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_6_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_6_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_6 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_6 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_6 register. * * \return the description of the EVENT_TYPE field of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * * \return the content of the EVENT_TYPE field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_6_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_6_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_6 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_6 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_6_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_6_FILTER_W) /** Modify the content of the FILTER field of the TRIG_6 register. */ #define ATON_DEBUG_TRACE_TRIG_6_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_6_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_6_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_6 register. * * \return the description of the FILTER field of TRIG_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_6_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_6_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * * \return the content of the FILTER field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_6_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_6 register. * * \param[in] reg is the value of the TRIG_6 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_6 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_6_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_6_SET_FILTER(reg, data); } /* **************************************************** TRIG_7 register of one of the DEBUG_TRACE Units ***************************************************** */ /** Offset of the TRIG_7 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_7_OFFSET 0x38UL /** Reset value of the TRIG_7 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_TRIG_7_DT \ (ATON_DEBUG_TRACE_TRIG_7_EN_DT << ATON_DEBUG_TRACE_TRIG_7_EN_LSB) | \ (ATON_DEBUG_TRACE_TRIG_7_SEL_DT << ATON_DEBUG_TRACE_TRIG_7_SEL_LSB) | \ (ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DT << ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB) | \ (ATON_DEBUG_TRACE_TRIG_7_OVR_DT << ATON_DEBUG_TRACE_TRIG_7_OVR_LSB) | \ (ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DT << ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_TRIG_7_FILTER_DT << ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB) /** Description of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_DESC "Trigger Generation register 8" /** Address of the TRIG_7 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_7_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_TRIG_7_OFFSET) /** Get the content of the TRIG_7 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_7_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_7_ADDR(UNIT))) /** Set the content of the TRIG_7 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_TRIG_7_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_TRIG_7_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of TRIG_7 register. * * \return the description of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_DESC; } /** * Get the offset of the TRIG_7 register. * * \return the offset of TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_GetOffset(void) { return ATON_DEBUG_TRACE_TRIG_7_OFFSET; } /** * Get the address of the TRIG_7 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_7 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of TRIG_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_7_ADDR(instance); } /** * Read the content of the TRIG_7 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_7 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of TRIG_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get(uint32_t instance) { return ATON_DEBUG_TRACE_TRIG_7_GET(instance); } /** * Write the content of the TRIG_7 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the TRIG_7 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_TRIG_7_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_TRIG_7_SET(instance, data); } /* ------------------------------------------------------------ EN field of the TRIG_7 register ------------------------------------------------------------- */ /** Description of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_DESC "Enable trigger generation" /** Offset of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_LSB 0UL /** Size in bits of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_W (1UL) /** Mask for retrieving the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_DT 0x0UL /** Access rights of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_AC "RW" /** Check whether access to the EN field of the TRIG_7 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_S 0 /** Check whether access to the EN field of the TRIG_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_7_EN_P 0 /** Read the content of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EN_LSB, ATON_DEBUG_TRACE_TRIG_7_EN_W) /** Modify the content of the EN field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EN_LSB, ATON_DEBUG_TRACE_TRIG_7_EN_W, DATA) /** * Get the description of the EN field of TRIG_7 register. * * \return the description of the EN field of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_EN_DESC; } /** * Read the content of the EN field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * * \return the content of the EN field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_7_GET_EN(reg); } /** * Write the content of the EN field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_7_SET_EN(reg, data); } /* ------------------------------------------------------------ SEL field of the TRIG_7 register ------------------------------------------------------------ */ /** Description of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_LSB 1UL /** Size in bits of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_W (9UL) /** Mask for retrieving the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_MASK ATON_FIELD_MASK(1UL, 9UL) /** Reset value of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_DT 0x0UL /** Access rights of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_AC "RW" /** Check whether access to the SEL field of the TRIG_7 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_S 0 /** Check whether access to the SEL field of the TRIG_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_7_SEL_P 0 /** Read the content of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SEL_LSB, ATON_DEBUG_TRACE_TRIG_7_SEL_W) /** Modify the content of the SEL field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SEL_LSB, ATON_DEBUG_TRACE_TRIG_7_SEL_W, DATA) /** * Get the description of the SEL field of TRIG_7 register. * * \return the description of the SEL field of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_SEL_DESC; } /** * Read the content of the SEL field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * * \return the content of the SEL field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_7_GET_SEL(reg); } /** * Write the content of the SEL field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * \param[in] data is 9-bit value that must be written to the field * * \return the new content of the SEL field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_7_SET_SEL(reg, data); } /* ---------------------------------------------------------- SWTRIG field of the TRIG_7 register ----------------------------------------------------------- */ /** Description of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DESC "SW generated trigger (autocleared)" /** Offset of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB 10UL /** Size in bits of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_W (1UL) /** Mask for retrieving the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_MASK ATON_FIELD_MASK(10UL, 1UL) /** Reset value of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DT 0x0UL /** Access rights of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_AC "RW" /** Check whether access to the SWTRIG field of the TRIG_7 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_S 0 /** Check whether access to the SWTRIG field of the TRIG_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_7_SWTRIG_P 0 /** Read the content of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_GET_SWTRIG(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_W) /** Modify the content of the SWTRIG field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SET_SWTRIG(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_LSB, ATON_DEBUG_TRACE_TRIG_7_SWTRIG_W, DATA) /** * Get the description of the SWTRIG field of TRIG_7 register. * * \return the description of the SWTRIG field of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_SWTRIG_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_SWTRIG_DESC; } /** * Read the content of the SWTRIG field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * * \return the content of the SWTRIG field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_SWTRIG(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_7_GET_SWTRIG(reg); } /** * Write the content of the SWTRIG field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the SWTRIG field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_SWTRIG(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_7_SET_SWTRIG(reg, data); } /* ------------------------------------------------------------ OVR field of the TRIG_7 register ------------------------------------------------------------ */ /** Description of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_DESC "Multiple events detected within 10 clock periods" /** Offset of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_LSB 11UL /** Size in bits of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_W (1UL) /** Mask for retrieving the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_MASK ATON_FIELD_MASK(11UL, 1UL) /** Reset value of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_DT 0x0UL /** Access rights of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_AC "RW" /** Check whether access to the OVR field of the TRIG_7 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_S 0 /** Check whether access to the OVR field of the TRIG_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_7_OVR_P 0 /** Read the content of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_GET_OVR(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_OVR_LSB, ATON_DEBUG_TRACE_TRIG_7_OVR_W) /** Modify the content of the OVR field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SET_OVR(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_OVR_LSB, ATON_DEBUG_TRACE_TRIG_7_OVR_W, DATA) /** * Get the description of the OVR field of TRIG_7 register. * * \return the description of the OVR field of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_OVR_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_OVR_DESC; } /** * Read the content of the OVR field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * * \return the content of the OVR field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_OVR(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_7_GET_OVR(reg); } /** * Write the content of the OVR field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the OVR field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_OVR(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_7_SET_OVR(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the TRIG_7 register --------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the TRIG_7 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the TRIG_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of TRIG_7 register. * * \return the description of the EVENT_TYPE field of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * * \return the content of the EVENT_TYPE field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_7_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_7_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- FILTER field of the TRIG_7 register ----------------------------------------------------------- */ /** Description of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_DESC "Number of events to detect before sending a trigger" /** Offset of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB 16UL /** Size in bits of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_W (16UL) /** Mask for retrieving the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_MASK ATON_FIELD_MASK(16UL, 16UL) /** Reset value of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_DT 0x1UL /** Access rights of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_AC "RW" /** Check whether access to the FILTER field of the TRIG_7 register is secured or not. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_S 0 /** Check whether access to the FILTER field of the TRIG_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_TRIG_7_FILTER_P 0 /** Read the content of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_GET_FILTER(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_7_FILTER_W) /** Modify the content of the FILTER field of the TRIG_7 register. */ #define ATON_DEBUG_TRACE_TRIG_7_SET_FILTER(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_TRIG_7_FILTER_LSB, ATON_DEBUG_TRACE_TRIG_7_FILTER_W, DATA) /** * Get the description of the FILTER field of TRIG_7 register. * * \return the description of the FILTER field of TRIG_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_TRIG_7_FILTER_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_TRIG_7_FILTER_DESC; } /** * Read the content of the FILTER field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * * \return the content of the FILTER field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Get_FILTER(uint32_t reg) { return ATON_DEBUG_TRACE_TRIG_7_GET_FILTER(reg); } /** * Write the content of the FILTER field of the TRIG_7 register. * * \param[in] reg is the value of the TRIG_7 register * \param[in] data is 16-bit value that must be written to the field * * \return the new content of the FILTER field belonging to TRIG_7 register */ static inline uint32_t ATON_DEBUG_TRACE_TRIG_7_Set_FILTER(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_TRIG_7_SET_FILTER(reg, data); } /* **************************************************** EVENT_0 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_0 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_0_OFFSET 0x40UL /** Reset value of the EVENT_0 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_0_DT \ (ATON_DEBUG_TRACE_EVENT_0_EN_DT << ATON_DEBUG_TRACE_EVENT_0_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_SEL_DT << ATON_DEBUG_TRACE_EVENT_0_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_WRAP_DT << ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB) /** Description of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_DESC "Observer register 1" /** Address of the EVENT_0 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_0_OFFSET) /** Get the content of the EVENT_0 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_0_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT))) /** Set the content of the EVENT_0 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_0_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_0 register. * * \return the description of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_DESC; } /** * Get the offset of the EVENT_0 register. * * \return the offset of EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_0_OFFSET; } /** * Get the address of the EVENT_0 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_0_ADDR(instance); } /** * Read the content of the EVENT_0 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_0 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_0_GET(instance); } /** * Write the content of the EVENT_0 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_0_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_0_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_0 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_AC "RW" /** Check whether access to the EN field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_S 0 /** Check whether access to the EN field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_EN_P 0 /** Read the content of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_EN_W) /** Modify the content of the EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_EN_W, DATA) /** * Get the description of the EN field of EVENT_0 register. * * \return the description of the EN field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_EN_DESC; } /** * Read the content of the EN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the EN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_0 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_S 0 /** Check whether access to the SEL field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_SEL_P 0 /** Read the content of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_SEL_W) /** Modify the content of the SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_0 register. * * \return the description of the SEL field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the SEL field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_0 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_0 register. * * \return the description of the EVENT_TYPE field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the EVENT_TYPE field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_0 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_0_WRAP_W) /** Modify the content of the WRAP field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_0_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_0 register. * * \return the description of the WRAP field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the WRAP field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_0 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_0 register. * * \return the description of the CNT_DOWN field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the CNT_DOWN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_0 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_0 register. * * \return the description of the INT_DISABLE field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the INT_DISABLE field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_0 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_0 register. * * \return the description of the START_EVENT_EN field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the START_EVENT_EN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_0 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_0 register. * * \return the description of the STOP_EVENT_EN field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_0 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_0 register. * * \return the description of the START_EVENT_SEL field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_0 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_0 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_0 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_0 register. */ #define ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_0 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_0 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_0 register. * * \param[in] reg is the value of the EVENT_0 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_0 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_1 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_1 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_1_OFFSET 0x44UL /** Reset value of the EVENT_1 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_1_DT \ (ATON_DEBUG_TRACE_EVENT_1_EN_DT << ATON_DEBUG_TRACE_EVENT_1_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_SEL_DT << ATON_DEBUG_TRACE_EVENT_1_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_WRAP_DT << ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB) /** Description of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_DESC "Observer register 2" /** Address of the EVENT_1 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_1_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_1_OFFSET) /** Get the content of the EVENT_1 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_1_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_ADDR(UNIT))) /** Set the content of the EVENT_1 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_1_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_1 register. * * \return the description of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_DESC; } /** * Get the offset of the EVENT_1 register. * * \return the offset of EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_1_OFFSET; } /** * Get the address of the EVENT_1 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_1_ADDR(instance); } /** * Read the content of the EVENT_1 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_1 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_1_GET(instance); } /** * Write the content of the EVENT_1 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_1_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_1_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_1 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_AC "RW" /** Check whether access to the EN field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_S 0 /** Check whether access to the EN field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_EN_P 0 /** Read the content of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_EN_W) /** Modify the content of the EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_EN_W, DATA) /** * Get the description of the EN field of EVENT_1 register. * * \return the description of the EN field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_EN_DESC; } /** * Read the content of the EN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the EN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_1 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_S 0 /** Check whether access to the SEL field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_SEL_P 0 /** Read the content of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_SEL_W) /** Modify the content of the SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_1 register. * * \return the description of the SEL field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the SEL field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_1 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_1 register. * * \return the description of the EVENT_TYPE field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the EVENT_TYPE field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_1 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_1_WRAP_W) /** Modify the content of the WRAP field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_1_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_1 register. * * \return the description of the WRAP field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the WRAP field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_1 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_1 register. * * \return the description of the CNT_DOWN field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the CNT_DOWN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_1 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_1 register. * * \return the description of the INT_DISABLE field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the INT_DISABLE field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_1 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_1 register. * * \return the description of the START_EVENT_EN field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the START_EVENT_EN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_1 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_1 register. * * \return the description of the STOP_EVENT_EN field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_1 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_1 register. * * \return the description of the START_EVENT_SEL field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_1 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_1 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_1 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_1 register. */ #define ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_1 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_1 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_1 register. * * \param[in] reg is the value of the EVENT_1 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_1 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_2 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_2 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_2_OFFSET 0x48UL /** Reset value of the EVENT_2 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_2_DT \ (ATON_DEBUG_TRACE_EVENT_2_EN_DT << ATON_DEBUG_TRACE_EVENT_2_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_SEL_DT << ATON_DEBUG_TRACE_EVENT_2_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_WRAP_DT << ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB) /** Description of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_DESC "Observer register 3" /** Address of the EVENT_2 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_2_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_2_OFFSET) /** Get the content of the EVENT_2 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_2_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_ADDR(UNIT))) /** Set the content of the EVENT_2 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_2_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_2 register. * * \return the description of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_DESC; } /** * Get the offset of the EVENT_2 register. * * \return the offset of EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_2_OFFSET; } /** * Get the address of the EVENT_2 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_2_ADDR(instance); } /** * Read the content of the EVENT_2 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_2 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_2_GET(instance); } /** * Write the content of the EVENT_2 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_2_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_2_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_2 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_AC "RW" /** Check whether access to the EN field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_S 0 /** Check whether access to the EN field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_EN_P 0 /** Read the content of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_EN_W) /** Modify the content of the EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_EN_W, DATA) /** * Get the description of the EN field of EVENT_2 register. * * \return the description of the EN field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_EN_DESC; } /** * Read the content of the EN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the EN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_2 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_S 0 /** Check whether access to the SEL field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_SEL_P 0 /** Read the content of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_SEL_W) /** Modify the content of the SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_2 register. * * \return the description of the SEL field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the SEL field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_2 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_2 register. * * \return the description of the EVENT_TYPE field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the EVENT_TYPE field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_2 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_2_WRAP_W) /** Modify the content of the WRAP field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_2_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_2 register. * * \return the description of the WRAP field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the WRAP field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_2 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_2 register. * * \return the description of the CNT_DOWN field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the CNT_DOWN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_2 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_2 register. * * \return the description of the INT_DISABLE field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the INT_DISABLE field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_2 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_2 register. * * \return the description of the START_EVENT_EN field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the START_EVENT_EN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_2 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_2 register. * * \return the description of the STOP_EVENT_EN field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_2 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_2 register. * * \return the description of the START_EVENT_SEL field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_2 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_2 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_2 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_2 register. */ #define ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_2 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_2 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_2 register. * * \param[in] reg is the value of the EVENT_2 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_2 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_3 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_3 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_3_OFFSET 0x4cUL /** Reset value of the EVENT_3 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_3_DT \ (ATON_DEBUG_TRACE_EVENT_3_EN_DT << ATON_DEBUG_TRACE_EVENT_3_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_SEL_DT << ATON_DEBUG_TRACE_EVENT_3_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_WRAP_DT << ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB) /** Description of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_DESC "Observer register 4" /** Address of the EVENT_3 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_3_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_3_OFFSET) /** Get the content of the EVENT_3 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_3_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_ADDR(UNIT))) /** Set the content of the EVENT_3 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_3_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_3 register. * * \return the description of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_DESC; } /** * Get the offset of the EVENT_3 register. * * \return the offset of EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_3_OFFSET; } /** * Get the address of the EVENT_3 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_3_ADDR(instance); } /** * Read the content of the EVENT_3 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_3 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_3_GET(instance); } /** * Write the content of the EVENT_3 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_3_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_3_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_3 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_AC "RW" /** Check whether access to the EN field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_S 0 /** Check whether access to the EN field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_EN_P 0 /** Read the content of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_EN_W) /** Modify the content of the EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_EN_W, DATA) /** * Get the description of the EN field of EVENT_3 register. * * \return the description of the EN field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_EN_DESC; } /** * Read the content of the EN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the EN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_3 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_S 0 /** Check whether access to the SEL field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_SEL_P 0 /** Read the content of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_SEL_W) /** Modify the content of the SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_3 register. * * \return the description of the SEL field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the SEL field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_3 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_3 register. * * \return the description of the EVENT_TYPE field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the EVENT_TYPE field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_3 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_3_WRAP_W) /** Modify the content of the WRAP field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_3_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_3 register. * * \return the description of the WRAP field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the WRAP field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_3 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_3 register. * * \return the description of the CNT_DOWN field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the CNT_DOWN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_3 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_3 register. * * \return the description of the INT_DISABLE field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the INT_DISABLE field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_3 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_3 register. * * \return the description of the START_EVENT_EN field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the START_EVENT_EN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_3 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_3 register. * * \return the description of the STOP_EVENT_EN field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_3 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_3 register. * * \return the description of the START_EVENT_SEL field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_3 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_3 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_3 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_3 register. */ #define ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_3 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_3 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_3 register. * * \param[in] reg is the value of the EVENT_3 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_3 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_4 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_4 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_4_OFFSET 0x50UL /** Reset value of the EVENT_4 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_4_DT \ (ATON_DEBUG_TRACE_EVENT_4_EN_DT << ATON_DEBUG_TRACE_EVENT_4_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_SEL_DT << ATON_DEBUG_TRACE_EVENT_4_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_WRAP_DT << ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB) /** Description of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_DESC "Observer register 5" /** Address of the EVENT_4 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_4_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_4_OFFSET) /** Get the content of the EVENT_4 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_4_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_ADDR(UNIT))) /** Set the content of the EVENT_4 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_4_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_4 register. * * \return the description of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_DESC; } /** * Get the offset of the EVENT_4 register. * * \return the offset of EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_4_OFFSET; } /** * Get the address of the EVENT_4 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_4_ADDR(instance); } /** * Read the content of the EVENT_4 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_4 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_4_GET(instance); } /** * Write the content of the EVENT_4 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_4_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_4_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_4 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_AC "RW" /** Check whether access to the EN field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_S 0 /** Check whether access to the EN field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_EN_P 0 /** Read the content of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_EN_W) /** Modify the content of the EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_EN_W, DATA) /** * Get the description of the EN field of EVENT_4 register. * * \return the description of the EN field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_EN_DESC; } /** * Read the content of the EN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the EN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_4 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_S 0 /** Check whether access to the SEL field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_SEL_P 0 /** Read the content of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_SEL_W) /** Modify the content of the SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_4 register. * * \return the description of the SEL field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the SEL field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_4 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_4 register. * * \return the description of the EVENT_TYPE field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the EVENT_TYPE field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_4 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_4_WRAP_W) /** Modify the content of the WRAP field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_4_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_4 register. * * \return the description of the WRAP field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the WRAP field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_4 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_4 register. * * \return the description of the CNT_DOWN field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the CNT_DOWN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_4 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_4 register. * * \return the description of the INT_DISABLE field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the INT_DISABLE field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_4 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_4 register. * * \return the description of the START_EVENT_EN field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the START_EVENT_EN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_4 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_4 register. * * \return the description of the STOP_EVENT_EN field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_4 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_4 register. * * \return the description of the START_EVENT_SEL field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_4 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_4 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_4 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_4 register. */ #define ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_4 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_4 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_4 register. * * \param[in] reg is the value of the EVENT_4 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_4 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_5 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_5 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_5_OFFSET 0x54UL /** Reset value of the EVENT_5 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_5_DT \ (ATON_DEBUG_TRACE_EVENT_5_EN_DT << ATON_DEBUG_TRACE_EVENT_5_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_SEL_DT << ATON_DEBUG_TRACE_EVENT_5_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_WRAP_DT << ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB) /** Description of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_DESC "Observer register 6" /** Address of the EVENT_5 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_5_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_5_OFFSET) /** Get the content of the EVENT_5 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_5_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_ADDR(UNIT))) /** Set the content of the EVENT_5 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_5_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_5 register. * * \return the description of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_DESC; } /** * Get the offset of the EVENT_5 register. * * \return the offset of EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_5_OFFSET; } /** * Get the address of the EVENT_5 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_5_ADDR(instance); } /** * Read the content of the EVENT_5 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_5 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_5_GET(instance); } /** * Write the content of the EVENT_5 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_5_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_5_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_5 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_AC "RW" /** Check whether access to the EN field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_S 0 /** Check whether access to the EN field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_EN_P 0 /** Read the content of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_EN_W) /** Modify the content of the EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_EN_W, DATA) /** * Get the description of the EN field of EVENT_5 register. * * \return the description of the EN field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_EN_DESC; } /** * Read the content of the EN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the EN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_5 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_S 0 /** Check whether access to the SEL field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_SEL_P 0 /** Read the content of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_SEL_W) /** Modify the content of the SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_5 register. * * \return the description of the SEL field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the SEL field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_5 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_5 register. * * \return the description of the EVENT_TYPE field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the EVENT_TYPE field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_5 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_5_WRAP_W) /** Modify the content of the WRAP field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_5_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_5 register. * * \return the description of the WRAP field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the WRAP field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_5 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_5 register. * * \return the description of the CNT_DOWN field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the CNT_DOWN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_5 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_5 register. * * \return the description of the INT_DISABLE field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the INT_DISABLE field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_5 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_5 register. * * \return the description of the START_EVENT_EN field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the START_EVENT_EN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_5 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_5 register. * * \return the description of the STOP_EVENT_EN field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_5 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_5 register. * * \return the description of the START_EVENT_SEL field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_5 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_5 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_5 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_5 register. */ #define ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_5 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_5 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_5 register. * * \param[in] reg is the value of the EVENT_5 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_5 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_6 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_6 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_6_OFFSET 0x58UL /** Reset value of the EVENT_6 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_6_DT \ (ATON_DEBUG_TRACE_EVENT_6_EN_DT << ATON_DEBUG_TRACE_EVENT_6_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_SEL_DT << ATON_DEBUG_TRACE_EVENT_6_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_WRAP_DT << ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB) /** Description of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_DESC "Observer register 7" /** Address of the EVENT_6 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_6_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_6_OFFSET) /** Get the content of the EVENT_6 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_6_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_ADDR(UNIT))) /** Set the content of the EVENT_6 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_6_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_6 register. * * \return the description of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_DESC; } /** * Get the offset of the EVENT_6 register. * * \return the offset of EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_6_OFFSET; } /** * Get the address of the EVENT_6 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_6_ADDR(instance); } /** * Read the content of the EVENT_6 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_6 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_6_GET(instance); } /** * Write the content of the EVENT_6 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_6_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_6_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_6 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_AC "RW" /** Check whether access to the EN field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_S 0 /** Check whether access to the EN field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_EN_P 0 /** Read the content of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_EN_W) /** Modify the content of the EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_EN_W, DATA) /** * Get the description of the EN field of EVENT_6 register. * * \return the description of the EN field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_EN_DESC; } /** * Read the content of the EN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the EN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_6 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_S 0 /** Check whether access to the SEL field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_SEL_P 0 /** Read the content of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_SEL_W) /** Modify the content of the SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_6 register. * * \return the description of the SEL field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the SEL field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_6 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_6 register. * * \return the description of the EVENT_TYPE field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the EVENT_TYPE field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_6 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_6_WRAP_W) /** Modify the content of the WRAP field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_6_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_6 register. * * \return the description of the WRAP field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the WRAP field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_6 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_6 register. * * \return the description of the CNT_DOWN field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the CNT_DOWN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_6 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_6 register. * * \return the description of the INT_DISABLE field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the INT_DISABLE field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_6 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_6 register. * * \return the description of the START_EVENT_EN field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the START_EVENT_EN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_6 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_6 register. * * \return the description of the STOP_EVENT_EN field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_6 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_6 register. * * \return the description of the START_EVENT_SEL field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_6 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_6 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_6 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_6 register. */ #define ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_6 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_6 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_6 register. * * \param[in] reg is the value of the EVENT_6 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_6 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_7 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_7 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_7_OFFSET 0x5cUL /** Reset value of the EVENT_7 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_7_DT \ (ATON_DEBUG_TRACE_EVENT_7_EN_DT << ATON_DEBUG_TRACE_EVENT_7_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_SEL_DT << ATON_DEBUG_TRACE_EVENT_7_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_WRAP_DT << ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB) /** Description of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_DESC "Observer register 8" /** Address of the EVENT_7 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_7_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_7_OFFSET) /** Get the content of the EVENT_7 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_7_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_ADDR(UNIT))) /** Set the content of the EVENT_7 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_7_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_7 register. * * \return the description of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_DESC; } /** * Get the offset of the EVENT_7 register. * * \return the offset of EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_7_OFFSET; } /** * Get the address of the EVENT_7 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_7_ADDR(instance); } /** * Read the content of the EVENT_7 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_7 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_7_GET(instance); } /** * Write the content of the EVENT_7 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_7_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_7_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_7 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_AC "RW" /** Check whether access to the EN field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_S 0 /** Check whether access to the EN field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_EN_P 0 /** Read the content of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_EN_W) /** Modify the content of the EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_EN_W, DATA) /** * Get the description of the EN field of EVENT_7 register. * * \return the description of the EN field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_EN_DESC; } /** * Read the content of the EN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the EN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_7 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_S 0 /** Check whether access to the SEL field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_SEL_P 0 /** Read the content of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_SEL_W) /** Modify the content of the SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_7 register. * * \return the description of the SEL field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the SEL field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_7 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_7 register. * * \return the description of the EVENT_TYPE field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the EVENT_TYPE field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_7 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_7_WRAP_W) /** Modify the content of the WRAP field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_7_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_7 register. * * \return the description of the WRAP field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the WRAP field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_7 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_7 register. * * \return the description of the CNT_DOWN field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the CNT_DOWN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_7 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_7 register. * * \return the description of the INT_DISABLE field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the INT_DISABLE field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_7 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_7 register. * * \return the description of the START_EVENT_EN field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the START_EVENT_EN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_7 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_7 register. * * \return the description of the STOP_EVENT_EN field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_7 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_7 register. * * \return the description of the START_EVENT_SEL field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_7 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_7 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_7 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_7 register. */ #define ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_7 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_7 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_7 register. * * \param[in] reg is the value of the EVENT_7 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_7 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_8 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_8 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_8_OFFSET 0x60UL /** Reset value of the EVENT_8 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_8_DT \ (ATON_DEBUG_TRACE_EVENT_8_EN_DT << ATON_DEBUG_TRACE_EVENT_8_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_SEL_DT << ATON_DEBUG_TRACE_EVENT_8_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_WRAP_DT << ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB) /** Description of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_DESC "Observer register 9" /** Address of the EVENT_8 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_8_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_8_OFFSET) /** Get the content of the EVENT_8 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_8_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_ADDR(UNIT))) /** Set the content of the EVENT_8 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_8_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_8 register. * * \return the description of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_DESC; } /** * Get the offset of the EVENT_8 register. * * \return the offset of EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_8_OFFSET; } /** * Get the address of the EVENT_8 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_8 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_8_ADDR(instance); } /** * Read the content of the EVENT_8 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_8 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_8_GET(instance); } /** * Write the content of the EVENT_8 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_8_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_8_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_8 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_AC "RW" /** Check whether access to the EN field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_S 0 /** Check whether access to the EN field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_EN_P 0 /** Read the content of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_EN_W) /** Modify the content of the EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_EN_W, DATA) /** * Get the description of the EN field of EVENT_8 register. * * \return the description of the EN field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_EN_DESC; } /** * Read the content of the EN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the EN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_8 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_S 0 /** Check whether access to the SEL field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_SEL_P 0 /** Read the content of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_SEL_W) /** Modify the content of the SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_8 register. * * \return the description of the SEL field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the SEL field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_8 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_8 register. * * \return the description of the EVENT_TYPE field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the EVENT_TYPE field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_8 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_8_WRAP_W) /** Modify the content of the WRAP field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_8_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_8 register. * * \return the description of the WRAP field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the WRAP field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_8 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_8 register. * * \return the description of the CNT_DOWN field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the CNT_DOWN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_8 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_8 register. * * \return the description of the INT_DISABLE field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the INT_DISABLE field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_8 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_8 register. * * \return the description of the START_EVENT_EN field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the START_EVENT_EN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_8 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_8 register. * * \return the description of the STOP_EVENT_EN field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_8 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_8 register. * * \return the description of the START_EVENT_SEL field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_8 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_8 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_8 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_8 register. */ #define ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_8 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_8 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_8 register. * * \param[in] reg is the value of the EVENT_8 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_8 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_SET_STOP_EVENT_SEL(reg, data); } /* **************************************************** EVENT_9 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_9 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_9_OFFSET 0x64UL /** Reset value of the EVENT_9 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_9_DT \ (ATON_DEBUG_TRACE_EVENT_9_EN_DT << ATON_DEBUG_TRACE_EVENT_9_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_SEL_DT << ATON_DEBUG_TRACE_EVENT_9_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_WRAP_DT << ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB) /** Description of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_DESC "Observer register 10" /** Address of the EVENT_9 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_9_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_9_OFFSET) /** Get the content of the EVENT_9 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_9_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_ADDR(UNIT))) /** Set the content of the EVENT_9 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_9_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_9 register. * * \return the description of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_DESC; } /** * Get the offset of the EVENT_9 register. * * \return the offset of EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_9_OFFSET; } /** * Get the address of the EVENT_9 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_9 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_9_ADDR(instance); } /** * Read the content of the EVENT_9 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_9 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_9_GET(instance); } /** * Write the content of the EVENT_9 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_9_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_9_SET(instance, data); } /* ------------------------------------------------------------ EN field of the EVENT_9 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_AC "RW" /** Check whether access to the EN field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_S 0 /** Check whether access to the EN field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_EN_P 0 /** Read the content of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_EN_W) /** Modify the content of the EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_EN_W, DATA) /** * Get the description of the EN field of EVENT_9 register. * * \return the description of the EN field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_EN_DESC; } /** * Read the content of the EN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the EN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_9 register ------------------------------------------------------------ */ /** Description of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_S 0 /** Check whether access to the SEL field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_SEL_P 0 /** Read the content of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_SEL_W) /** Modify the content of the SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_9 register. * * \return the description of the SEL field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the SEL field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_SEL(reg, data); } /* -------------------------------------------------------- EVENT_TYPE field of the EVENT_9 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_9 register. * * \return the description of the EVENT_TYPE field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the EVENT_TYPE field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_EVENT_TYPE(reg, data); } /* ----------------------------------------------------------- WRAP field of the EVENT_9 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_9_WRAP_W) /** Modify the content of the WRAP field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_9_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_9 register. * * \return the description of the WRAP field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the WRAP field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_WRAP(reg, data); } /* --------------------------------------------------------- CNT_DOWN field of the EVENT_9 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_9 register. * * \return the description of the CNT_DOWN field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the CNT_DOWN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_9 register -------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_9 register. * * \return the description of the INT_DISABLE field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the INT_DISABLE field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_INT_DISABLE(reg, data); } /* ------------------------------------------------------ START_EVENT_EN field of the EVENT_9 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_9 register. * * \return the description of the START_EVENT_EN field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the START_EVENT_EN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_9 register ------------------------------------------------------- */ /** Description of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_9 register. * * \return the description of the STOP_EVENT_EN field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_9 register ------------------------------------------------------ */ /** Description of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_9 register. * * \return the description of the START_EVENT_SEL field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_START_EVENT_SEL(reg, data); } /* ------------------------------------------------------ STOP_EVENT_SEL field of the EVENT_9 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_9 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_9 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_9 register. */ #define ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_9 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_9 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_9 register. * * \param[in] reg is the value of the EVENT_9 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_9 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_SET_STOP_EVENT_SEL(reg, data); } /* *************************************************** EVENT_10 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_10 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_10_OFFSET 0x68UL /** Reset value of the EVENT_10 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_10_DT \ (ATON_DEBUG_TRACE_EVENT_10_EN_DT << ATON_DEBUG_TRACE_EVENT_10_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_SEL_DT << ATON_DEBUG_TRACE_EVENT_10_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_WRAP_DT << ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB) /** Description of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_DESC "Observer register 11" /** Address of the EVENT_10 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_10_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_10_OFFSET) /** Get the content of the EVENT_10 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_10_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_ADDR(UNIT))) /** Set the content of the EVENT_10 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_10_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_10 register. * * \return the description of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_DESC; } /** * Get the offset of the EVENT_10 register. * * \return the offset of EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_10_OFFSET; } /** * Get the address of the EVENT_10 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_10 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_10_ADDR(instance); } /** * Read the content of the EVENT_10 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_10 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_10_GET(instance); } /** * Write the content of the EVENT_10 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_10_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_10_SET(instance, data); } /* ----------------------------------------------------------- EN field of the EVENT_10 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_AC "RW" /** Check whether access to the EN field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_S 0 /** Check whether access to the EN field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_EN_P 0 /** Read the content of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_EN_W) /** Modify the content of the EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_EN_W, DATA) /** * Get the description of the EN field of EVENT_10 register. * * \return the description of the EN field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_EN_DESC; } /** * Read the content of the EN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the EN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_10 register ----------------------------------------------------------- */ /** Description of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_S 0 /** Check whether access to the SEL field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_SEL_P 0 /** Read the content of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_SEL_W) /** Modify the content of the SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_10 register. * * \return the description of the SEL field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the SEL field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_SEL(reg, data); } /* ------------------------------------------------------- EVENT_TYPE field of the EVENT_10 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_10 register. * * \return the description of the EVENT_TYPE field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the EVENT_TYPE field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- WRAP field of the EVENT_10 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_10_WRAP_W) /** Modify the content of the WRAP field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_10_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_10 register. * * \return the description of the WRAP field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the WRAP field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_WRAP(reg, data); } /* -------------------------------------------------------- CNT_DOWN field of the EVENT_10 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_10 register. * * \return the description of the CNT_DOWN field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the CNT_DOWN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_10 register ------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_10 register. * * \return the description of the INT_DISABLE field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the INT_DISABLE field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_INT_DISABLE(reg, data); } /* ----------------------------------------------------- START_EVENT_EN field of the EVENT_10 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_10 register. * * \return the description of the START_EVENT_EN field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the START_EVENT_EN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_10 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_10 register. * * \return the description of the STOP_EVENT_EN field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_10 register ----------------------------------------------------- */ /** Description of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_10 register. * * \return the description of the START_EVENT_SEL field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_START_EVENT_SEL(reg, data); } /* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_10 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_10 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_10 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_10 register. */ #define ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_10 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_10 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_10 register. * * \param[in] reg is the value of the EVENT_10 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_10 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_SET_STOP_EVENT_SEL(reg, data); } /* *************************************************** EVENT_11 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_11 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_11_OFFSET 0x6cUL /** Reset value of the EVENT_11 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_11_DT \ (ATON_DEBUG_TRACE_EVENT_11_EN_DT << ATON_DEBUG_TRACE_EVENT_11_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_SEL_DT << ATON_DEBUG_TRACE_EVENT_11_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_WRAP_DT << ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB) /** Description of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_DESC "Observer register 12" /** Address of the EVENT_11 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_11_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_11_OFFSET) /** Get the content of the EVENT_11 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_11_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_ADDR(UNIT))) /** Set the content of the EVENT_11 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_11_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_11 register. * * \return the description of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_DESC; } /** * Get the offset of the EVENT_11 register. * * \return the offset of EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_11_OFFSET; } /** * Get the address of the EVENT_11 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_11 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_11_ADDR(instance); } /** * Read the content of the EVENT_11 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_11 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_11_GET(instance); } /** * Write the content of the EVENT_11 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_11_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_11_SET(instance, data); } /* ----------------------------------------------------------- EN field of the EVENT_11 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_AC "RW" /** Check whether access to the EN field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_S 0 /** Check whether access to the EN field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_EN_P 0 /** Read the content of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_EN_W) /** Modify the content of the EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_EN_W, DATA) /** * Get the description of the EN field of EVENT_11 register. * * \return the description of the EN field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_EN_DESC; } /** * Read the content of the EN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the EN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_11 register ----------------------------------------------------------- */ /** Description of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_S 0 /** Check whether access to the SEL field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_SEL_P 0 /** Read the content of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_SEL_W) /** Modify the content of the SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_11 register. * * \return the description of the SEL field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the SEL field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_SEL(reg, data); } /* ------------------------------------------------------- EVENT_TYPE field of the EVENT_11 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_11 register. * * \return the description of the EVENT_TYPE field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the EVENT_TYPE field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- WRAP field of the EVENT_11 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_11_WRAP_W) /** Modify the content of the WRAP field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_11_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_11 register. * * \return the description of the WRAP field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the WRAP field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_WRAP(reg, data); } /* -------------------------------------------------------- CNT_DOWN field of the EVENT_11 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_11 register. * * \return the description of the CNT_DOWN field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the CNT_DOWN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_11 register ------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_11 register. * * \return the description of the INT_DISABLE field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the INT_DISABLE field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_INT_DISABLE(reg, data); } /* ----------------------------------------------------- START_EVENT_EN field of the EVENT_11 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_11 register. * * \return the description of the START_EVENT_EN field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the START_EVENT_EN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_11 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_11 register. * * \return the description of the STOP_EVENT_EN field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_11 register ----------------------------------------------------- */ /** Description of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_11 register. * * \return the description of the START_EVENT_SEL field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_START_EVENT_SEL(reg, data); } /* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_11 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_11 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_11 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_11 register. */ #define ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_11 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_11 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_11 register. * * \param[in] reg is the value of the EVENT_11 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_11 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_SET_STOP_EVENT_SEL(reg, data); } /* *************************************************** EVENT_12 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_12 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_12_OFFSET 0x70UL /** Reset value of the EVENT_12 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_12_DT \ (ATON_DEBUG_TRACE_EVENT_12_EN_DT << ATON_DEBUG_TRACE_EVENT_12_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_SEL_DT << ATON_DEBUG_TRACE_EVENT_12_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_WRAP_DT << ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB) /** Description of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_DESC "Observer register 13" /** Address of the EVENT_12 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_12_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_12_OFFSET) /** Get the content of the EVENT_12 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_12_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_ADDR(UNIT))) /** Set the content of the EVENT_12 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_12_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_12 register. * * \return the description of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_DESC; } /** * Get the offset of the EVENT_12 register. * * \return the offset of EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_12_OFFSET; } /** * Get the address of the EVENT_12 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_12 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_12_ADDR(instance); } /** * Read the content of the EVENT_12 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_12 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_12_GET(instance); } /** * Write the content of the EVENT_12 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_12_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_12_SET(instance, data); } /* ----------------------------------------------------------- EN field of the EVENT_12 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_AC "RW" /** Check whether access to the EN field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_S 0 /** Check whether access to the EN field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_EN_P 0 /** Read the content of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_EN_W) /** Modify the content of the EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_EN_W, DATA) /** * Get the description of the EN field of EVENT_12 register. * * \return the description of the EN field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_EN_DESC; } /** * Read the content of the EN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the EN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_12 register ----------------------------------------------------------- */ /** Description of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_S 0 /** Check whether access to the SEL field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_SEL_P 0 /** Read the content of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_SEL_W) /** Modify the content of the SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_12 register. * * \return the description of the SEL field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the SEL field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_SEL(reg, data); } /* ------------------------------------------------------- EVENT_TYPE field of the EVENT_12 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_12 register. * * \return the description of the EVENT_TYPE field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the EVENT_TYPE field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- WRAP field of the EVENT_12 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_12_WRAP_W) /** Modify the content of the WRAP field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_12_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_12 register. * * \return the description of the WRAP field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the WRAP field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_WRAP(reg, data); } /* -------------------------------------------------------- CNT_DOWN field of the EVENT_12 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_12 register. * * \return the description of the CNT_DOWN field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the CNT_DOWN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_12 register ------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_12 register. * * \return the description of the INT_DISABLE field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the INT_DISABLE field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_INT_DISABLE(reg, data); } /* ----------------------------------------------------- START_EVENT_EN field of the EVENT_12 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_12 register. * * \return the description of the START_EVENT_EN field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the START_EVENT_EN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_12 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_12 register. * * \return the description of the STOP_EVENT_EN field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_12 register ----------------------------------------------------- */ /** Description of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_12 register. * * \return the description of the START_EVENT_SEL field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_START_EVENT_SEL(reg, data); } /* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_12 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_12 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_12 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_12 register. */ #define ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_12 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_12 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_12 register. * * \param[in] reg is the value of the EVENT_12 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_12 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_SET_STOP_EVENT_SEL(reg, data); } /* *************************************************** EVENT_13 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_13 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_13_OFFSET 0x74UL /** Reset value of the EVENT_13 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_13_DT \ (ATON_DEBUG_TRACE_EVENT_13_EN_DT << ATON_DEBUG_TRACE_EVENT_13_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_SEL_DT << ATON_DEBUG_TRACE_EVENT_13_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_WRAP_DT << ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB) /** Description of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_DESC "Observer register 14" /** Address of the EVENT_13 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_13_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_13_OFFSET) /** Get the content of the EVENT_13 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_13_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_ADDR(UNIT))) /** Set the content of the EVENT_13 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_13_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_13 register. * * \return the description of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_DESC; } /** * Get the offset of the EVENT_13 register. * * \return the offset of EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_13_OFFSET; } /** * Get the address of the EVENT_13 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_13 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_13_ADDR(instance); } /** * Read the content of the EVENT_13 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_13 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_13_GET(instance); } /** * Write the content of the EVENT_13 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_13_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_13_SET(instance, data); } /* ----------------------------------------------------------- EN field of the EVENT_13 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_AC "RW" /** Check whether access to the EN field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_S 0 /** Check whether access to the EN field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_EN_P 0 /** Read the content of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_EN_W) /** Modify the content of the EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_EN_W, DATA) /** * Get the description of the EN field of EVENT_13 register. * * \return the description of the EN field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_EN_DESC; } /** * Read the content of the EN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the EN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_13 register ----------------------------------------------------------- */ /** Description of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_S 0 /** Check whether access to the SEL field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_SEL_P 0 /** Read the content of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_SEL_W) /** Modify the content of the SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_13 register. * * \return the description of the SEL field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the SEL field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_SEL(reg, data); } /* ------------------------------------------------------- EVENT_TYPE field of the EVENT_13 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_13 register. * * \return the description of the EVENT_TYPE field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the EVENT_TYPE field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- WRAP field of the EVENT_13 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_13_WRAP_W) /** Modify the content of the WRAP field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_13_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_13 register. * * \return the description of the WRAP field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the WRAP field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_WRAP(reg, data); } /* -------------------------------------------------------- CNT_DOWN field of the EVENT_13 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_13 register. * * \return the description of the CNT_DOWN field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the CNT_DOWN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_13 register ------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_13 register. * * \return the description of the INT_DISABLE field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the INT_DISABLE field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_INT_DISABLE(reg, data); } /* ----------------------------------------------------- START_EVENT_EN field of the EVENT_13 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_13 register. * * \return the description of the START_EVENT_EN field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the START_EVENT_EN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_13 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_13 register. * * \return the description of the STOP_EVENT_EN field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_13 register ----------------------------------------------------- */ /** Description of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_13 register. * * \return the description of the START_EVENT_SEL field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_START_EVENT_SEL(reg, data); } /* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_13 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_13 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_13 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_13 register. */ #define ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_13 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_13 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_13 register. * * \param[in] reg is the value of the EVENT_13 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_13 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_SET_STOP_EVENT_SEL(reg, data); } /* *************************************************** EVENT_14 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_14 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_14_OFFSET 0x78UL /** Reset value of the EVENT_14 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_14_DT \ (ATON_DEBUG_TRACE_EVENT_14_EN_DT << ATON_DEBUG_TRACE_EVENT_14_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_SEL_DT << ATON_DEBUG_TRACE_EVENT_14_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_WRAP_DT << ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB) /** Description of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_DESC "Observer register 15" /** Address of the EVENT_14 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_14_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_14_OFFSET) /** Get the content of the EVENT_14 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_14_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_ADDR(UNIT))) /** Set the content of the EVENT_14 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_14_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_14 register. * * \return the description of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_DESC; } /** * Get the offset of the EVENT_14 register. * * \return the offset of EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_14_OFFSET; } /** * Get the address of the EVENT_14 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_14 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_14_ADDR(instance); } /** * Read the content of the EVENT_14 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_14 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_14_GET(instance); } /** * Write the content of the EVENT_14 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_14_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_14_SET(instance, data); } /* ----------------------------------------------------------- EN field of the EVENT_14 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_AC "RW" /** Check whether access to the EN field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_S 0 /** Check whether access to the EN field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_EN_P 0 /** Read the content of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_EN_W) /** Modify the content of the EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_EN_W, DATA) /** * Get the description of the EN field of EVENT_14 register. * * \return the description of the EN field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_EN_DESC; } /** * Read the content of the EN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the EN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_14 register ----------------------------------------------------------- */ /** Description of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_S 0 /** Check whether access to the SEL field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_SEL_P 0 /** Read the content of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_SEL_W) /** Modify the content of the SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_14 register. * * \return the description of the SEL field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the SEL field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_SEL(reg, data); } /* ------------------------------------------------------- EVENT_TYPE field of the EVENT_14 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_14 register. * * \return the description of the EVENT_TYPE field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the EVENT_TYPE field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- WRAP field of the EVENT_14 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_14_WRAP_W) /** Modify the content of the WRAP field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_14_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_14 register. * * \return the description of the WRAP field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the WRAP field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_WRAP(reg, data); } /* -------------------------------------------------------- CNT_DOWN field of the EVENT_14 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_14 register. * * \return the description of the CNT_DOWN field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the CNT_DOWN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_14 register ------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_14 register. * * \return the description of the INT_DISABLE field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the INT_DISABLE field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_INT_DISABLE(reg, data); } /* ----------------------------------------------------- START_EVENT_EN field of the EVENT_14 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_14 register. * * \return the description of the START_EVENT_EN field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the START_EVENT_EN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_14 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_14 register. * * \return the description of the STOP_EVENT_EN field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_14 register ----------------------------------------------------- */ /** Description of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_14 register. * * \return the description of the START_EVENT_SEL field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_START_EVENT_SEL(reg, data); } /* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_14 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_14 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_14 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_14 register. */ #define ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_14 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_14 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_14 register. * * \param[in] reg is the value of the EVENT_14 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_14 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_SET_STOP_EVENT_SEL(reg, data); } /* *************************************************** EVENT_15 register of one of the DEBUG_TRACE Units **************************************************** */ /** Offset of the EVENT_15 register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_15_OFFSET 0x7cUL /** Reset value of the EVENT_15 register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_15_DT \ (ATON_DEBUG_TRACE_EVENT_15_EN_DT << ATON_DEBUG_TRACE_EVENT_15_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_SEL_DT << ATON_DEBUG_TRACE_EVENT_15_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DT << ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_WRAP_DT << ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DT << ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DT << ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DT << ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB) | \ (ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DT << ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB) /** Description of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_DESC "Observer register 16" /** Address of the EVENT_15 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_15_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_15_OFFSET) /** Get the content of the EVENT_15 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_15_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_ADDR(UNIT))) /** Set the content of the EVENT_15 register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_15_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_15 register. * * \return the description of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_DESC; } /** * Get the offset of the EVENT_15 register. * * \return the offset of EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_15_OFFSET; } /** * Get the address of the EVENT_15 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15 register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_15 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_15_ADDR(instance); } /** * Read the content of the EVENT_15 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15 register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_15 register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_15_GET(instance); } /** * Write the content of the EVENT_15 register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15 register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_15_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_15_SET(instance, data); } /* ----------------------------------------------------------- EN field of the EVENT_15 register ------------------------------------------------------------ */ /** Description of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_DESC "Enable observer" /** Offset of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_LSB 0UL /** Size in bits of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_W (1UL) /** Mask for retrieving the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_MASK ATON_FIELD_MASK(0UL, 1UL) /** Reset value of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_DT 0x0UL /** Access rights of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_AC "RW" /** Check whether access to the EN field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_S 0 /** Check whether access to the EN field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_EN_P 0 /** Read the content of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_EN_W) /** Modify the content of the EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_EN_W, DATA) /** * Get the description of the EN field of EVENT_15 register. * * \return the description of the EN field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_EN_DESC; } /** * Read the content of the EN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the EN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_EN(reg); } /** * Write the content of the EN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the EN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_EN(reg, data); } /* ----------------------------------------------------------- SEL field of the EVENT_15 register ----------------------------------------------------------- */ /** Description of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_DESC "Select signal to be monitored" /** Offset of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_LSB 1UL /** Size in bits of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_W (13UL) /** Mask for retrieving the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_MASK ATON_FIELD_MASK(1UL, 13UL) /** Reset value of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_DT 0x0UL /** Access rights of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_AC "RW" /** Check whether access to the SEL field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_S 0 /** Check whether access to the SEL field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_SEL_P 0 /** Read the content of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_SEL_W) /** Modify the content of the SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_SEL_W, DATA) /** * Get the description of the SEL field of EVENT_15 register. * * \return the description of the SEL field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_SEL_DESC; } /** * Read the content of the SEL field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the SEL field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_SEL(reg); } /** * Write the content of the SEL field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 13-bit value that must be written to the field * * \return the new content of the SEL field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_SEL(reg, data); } /* ------------------------------------------------------- EVENT_TYPE field of the EVENT_15 register -------------------------------------------------------- */ /** Description of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DESC "Type of event to be detected (0: level low; 1: level high; 2: positive edge; 3: negative edge)" /** Offset of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB 14UL /** Size in bits of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_W (2UL) /** Mask for retrieving the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_MASK ATON_FIELD_MASK(14UL, 2UL) /** Reset value of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DT 0x0UL /** Access rights of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_AC "RW" /** Check whether access to the EVENT_TYPE field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_S 0 /** Check whether access to the EVENT_TYPE field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_P 0 /** Read the content of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_EVENT_TYPE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_W) /** Modify the content of the EVENT_TYPE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_EVENT_TYPE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_LSB, ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_W, DATA) /** * Get the description of the EVENT_TYPE field of EVENT_15 register. * * \return the description of the EVENT_TYPE field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_EVENT_TYPE_DESC; } /** * Read the content of the EVENT_TYPE field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the EVENT_TYPE field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_EVENT_TYPE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_EVENT_TYPE(reg); } /** * Write the content of the EVENT_TYPE field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 2-bit value that must be written to the field * * \return the new content of the EVENT_TYPE field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_EVENT_TYPE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_EVENT_TYPE(reg, data); } /* ---------------------------------------------------------- WRAP field of the EVENT_15 register ----------------------------------------------------------- */ /** Description of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_DESC "Wrap around in case of overflow else block at 0xffffffff" /** Offset of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB 16UL /** Size in bits of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_W (1UL) /** Mask for retrieving the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_MASK ATON_FIELD_MASK(16UL, 1UL) /** Reset value of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_DT 0x0UL /** Access rights of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_AC "RW" /** Check whether access to the WRAP field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_S 0 /** Check whether access to the WRAP field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_WRAP_P 0 /** Read the content of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_WRAP(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_15_WRAP_W) /** Modify the content of the WRAP field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_WRAP(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_WRAP_LSB, ATON_DEBUG_TRACE_EVENT_15_WRAP_W, DATA) /** * Get the description of the WRAP field of EVENT_15 register. * * \return the description of the WRAP field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_WRAP_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_WRAP_DESC; } /** * Read the content of the WRAP field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the WRAP field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_WRAP(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_WRAP(reg); } /** * Write the content of the WRAP field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the WRAP field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_WRAP(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_WRAP(reg, data); } /* -------------------------------------------------------- CNT_DOWN field of the EVENT_15 register --------------------------------------------------------- */ /** Description of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DESC "Decrement the counter and interrupt when 0 is reached" /** Offset of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB 17UL /** Size in bits of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_W (1UL) /** Mask for retrieving the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_MASK ATON_FIELD_MASK(17UL, 1UL) /** Reset value of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DT 0x0UL /** Access rights of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_AC "RW" /** Check whether access to the CNT_DOWN field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_S 0 /** Check whether access to the CNT_DOWN field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_P 0 /** Read the content of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_CNT_DOWN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_W) /** Modify the content of the CNT_DOWN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_CNT_DOWN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_W, DATA) /** * Get the description of the CNT_DOWN field of EVENT_15 register. * * \return the description of the CNT_DOWN field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_CNT_DOWN_DESC; } /** * Read the content of the CNT_DOWN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the CNT_DOWN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_CNT_DOWN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_CNT_DOWN(reg); } /** * Write the content of the CNT_DOWN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the CNT_DOWN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_CNT_DOWN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_CNT_DOWN(reg, data); } /* ------------------------------------------------------- INT_DISABLE field of the EVENT_15 register ------------------------------------------------------- */ /** Description of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DESC "Mask interrupt for the related observer" /** Offset of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB 18UL /** Size in bits of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_W (1UL) /** Mask for retrieving the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_MASK ATON_FIELD_MASK(18UL, 1UL) /** Reset value of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DT 0x0UL /** Access rights of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_AC "RW" /** Check whether access to the INT_DISABLE field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_S 0 /** Check whether access to the INT_DISABLE field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_P 0 /** Read the content of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_INT_DISABLE(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_W) /** Modify the content of the INT_DISABLE field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_INT_DISABLE(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_LSB, ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_W, DATA) /** * Get the description of the INT_DISABLE field of EVENT_15 register. * * \return the description of the INT_DISABLE field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_INT_DISABLE_DESC; } /** * Read the content of the INT_DISABLE field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the INT_DISABLE field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_INT_DISABLE(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_INT_DISABLE(reg); } /** * Write the content of the INT_DISABLE field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the INT_DISABLE field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_INT_DISABLE(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_INT_DISABLE(reg, data); } /* ----------------------------------------------------- START_EVENT_EN field of the EVENT_15 register ------------------------------------------------------ */ /** Description of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DESC "Enable the observer counter based on an event detected by another observer" /** Offset of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB 19UL /** Size in bits of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_W (1UL) /** Mask for retrieving the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_MASK ATON_FIELD_MASK(19UL, 1UL) /** Reset value of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DT 0x0UL /** Access rights of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_AC "RW" /** Check whether access to the START_EVENT_EN field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_S 0 /** Check whether access to the START_EVENT_EN field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_P 0 /** Read the content of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_W) /** Modify the content of the START_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_W, DATA) /** * Get the description of the START_EVENT_EN field of EVENT_15 register. * * \return the description of the START_EVENT_EN field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_START_EVENT_EN_DESC; } /** * Read the content of the START_EVENT_EN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the START_EVENT_EN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_START_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_EN(reg); } /** * Write the content of the START_EVENT_EN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the START_EVENT_EN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_START_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_EN(reg, data); } /* ------------------------------------------------------ STOP_EVENT_EN field of the EVENT_15 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DESC "Stop the observer counter based on an event detected by another observer" /** Offset of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB 20UL /** Size in bits of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_W (1UL) /** Mask for retrieving the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_MASK ATON_FIELD_MASK(20UL, 1UL) /** Reset value of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DT 0x0UL /** Access rights of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_AC "RW" /** Check whether access to the STOP_EVENT_EN field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_S 0 /** Check whether access to the STOP_EVENT_EN field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_P 0 /** Read the content of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_EN(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_W) /** Modify the content of the STOP_EVENT_EN field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_EN(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_W, DATA) /** * Get the description of the STOP_EVENT_EN field of EVENT_15 register. * * \return the description of the STOP_EVENT_EN field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_EN_DESC; } /** * Read the content of the STOP_EVENT_EN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the STOP_EVENT_EN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_STOP_EVENT_EN(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_EN(reg); } /** * Write the content of the STOP_EVENT_EN field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 1-bit value that must be written to the field * * \return the new content of the STOP_EVENT_EN field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_STOP_EVENT_EN(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_EN(reg, data); } /* ----------------------------------------------------- START_EVENT_SEL field of the EVENT_15 register ----------------------------------------------------- */ /** Description of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DESC "Select the observer which generates the start signal (not valid if START_EVENT_EN = 0)" /** Offset of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB 21UL /** Size in bits of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_W (4UL) /** Mask for retrieving the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_MASK ATON_FIELD_MASK(21UL, 4UL) /** Reset value of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DT 0x0UL /** Access rights of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_AC "RW" /** Check whether access to the START_EVENT_SEL field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_S 0 /** Check whether access to the START_EVENT_SEL field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_P 0 /** Read the content of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_W) /** Modify the content of the START_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_W, DATA) /** * Get the description of the START_EVENT_SEL field of EVENT_15 register. * * \return the description of the START_EVENT_SEL field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_START_EVENT_SEL_DESC; } /** * Read the content of the START_EVENT_SEL field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the START_EVENT_SEL field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_START_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_START_EVENT_SEL(reg); } /** * Write the content of the START_EVENT_SEL field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the START_EVENT_SEL field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_START_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_START_EVENT_SEL(reg, data); } /* ----------------------------------------------------- STOP_EVENT_SEL field of the EVENT_15 register ------------------------------------------------------ */ /** Description of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DESC "Select the observer which generates the stop signal (not valid if STOP_EVENT_EN = 0)" /** Offset of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB 25UL /** Size in bits of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_W (4UL) /** Mask for retrieving the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_MASK ATON_FIELD_MASK(25UL, 4UL) /** Reset value of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DT 0x0UL /** Access rights of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_AC "RW" /** Check whether access to the STOP_EVENT_SEL field of the EVENT_15 register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_S 0 /** Check whether access to the STOP_EVENT_SEL field of the EVENT_15 register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_P 0 /** Read the content of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_SEL(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_W) /** Modify the content of the STOP_EVENT_SEL field of the EVENT_15 register. */ #define ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_SEL(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_LSB, ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_W, DATA) /** * Get the description of the STOP_EVENT_SEL field of EVENT_15 register. * * \return the description of the STOP_EVENT_SEL field of EVENT_15 register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_STOP_EVENT_SEL_DESC; } /** * Read the content of the STOP_EVENT_SEL field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * * \return the content of the STOP_EVENT_SEL field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Get_STOP_EVENT_SEL(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_GET_STOP_EVENT_SEL(reg); } /** * Write the content of the STOP_EVENT_SEL field of the EVENT_15 register. * * \param[in] reg is the value of the EVENT_15 register * \param[in] data is 4-bit value that must be written to the field * * \return the new content of the STOP_EVENT_SEL field belonging to EVENT_15 register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_Set_STOP_EVENT_SEL(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_SET_STOP_EVENT_SEL(reg, data); } /* ************************************************** EVENT_0_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_0_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_OFFSET 0x84UL /** Reset value of the EVENT_0_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB) /** Description of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_DESC "Observer counter register 1" /** Address of the EVENT_0_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_0_CNT_OFFSET) /** Get the content of the EVENT_0_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT))) /** Set the content of the EVENT_0_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_0_CNT register. * * \return the description of EVENT_0_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_CNT_DESC; } /** * Get the offset of the EVENT_0_CNT register. * * \return the offset of EVENT_0_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_0_CNT_OFFSET; } /** * Get the address of the EVENT_0_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_0_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(instance); } /** * Read the content of the EVENT_0_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_0_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_0_CNT_GET(instance); } /** * Write the content of the EVENT_0_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_0_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_0_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_0_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_0_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_0_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_0_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_0_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_0_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_0_CNT register. * * \return the description of the CNT field of EVENT_0_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_0_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_0_CNT register. * * \param[in] reg is the value of the EVENT_0_CNT register * * \return the content of the CNT field belonging to EVENT_0_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_0_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_0_CNT register. * * \param[in] reg is the value of the EVENT_0_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_0_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_0_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_0_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_1_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_1_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_OFFSET 0x88UL /** Reset value of the EVENT_1_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB) /** Description of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_DESC "Observer counter register 2" /** Address of the EVENT_1_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_1_CNT_OFFSET) /** Get the content of the EVENT_1_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(UNIT))) /** Set the content of the EVENT_1_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_1_CNT register. * * \return the description of EVENT_1_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_CNT_DESC; } /** * Get the offset of the EVENT_1_CNT register. * * \return the offset of EVENT_1_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_1_CNT_OFFSET; } /** * Get the address of the EVENT_1_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_1_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_1_CNT_ADDR(instance); } /** * Read the content of the EVENT_1_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_1_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_1_CNT_GET(instance); } /** * Write the content of the EVENT_1_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_1_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_1_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_1_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_1_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_1_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_1_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_1_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_1_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_1_CNT register. * * \return the description of the CNT field of EVENT_1_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_1_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_1_CNT register. * * \param[in] reg is the value of the EVENT_1_CNT register * * \return the content of the CNT field belonging to EVENT_1_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_1_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_1_CNT register. * * \param[in] reg is the value of the EVENT_1_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_1_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_1_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_1_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_2_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_2_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_OFFSET 0x8cUL /** Reset value of the EVENT_2_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB) /** Description of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_DESC "Observer counter register 3" /** Address of the EVENT_2_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_2_CNT_OFFSET) /** Get the content of the EVENT_2_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(UNIT))) /** Set the content of the EVENT_2_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_2_CNT register. * * \return the description of EVENT_2_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_CNT_DESC; } /** * Get the offset of the EVENT_2_CNT register. * * \return the offset of EVENT_2_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_2_CNT_OFFSET; } /** * Get the address of the EVENT_2_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_2_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_2_CNT_ADDR(instance); } /** * Read the content of the EVENT_2_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_2_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_2_CNT_GET(instance); } /** * Write the content of the EVENT_2_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_2_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_2_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_2_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_2_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_2_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_2_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_2_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_2_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_2_CNT register. * * \return the description of the CNT field of EVENT_2_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_2_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_2_CNT register. * * \param[in] reg is the value of the EVENT_2_CNT register * * \return the content of the CNT field belonging to EVENT_2_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_2_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_2_CNT register. * * \param[in] reg is the value of the EVENT_2_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_2_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_2_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_2_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_3_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_3_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_OFFSET 0x90UL /** Reset value of the EVENT_3_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB) /** Description of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_DESC "Observer counter register 4" /** Address of the EVENT_3_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_3_CNT_OFFSET) /** Get the content of the EVENT_3_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(UNIT))) /** Set the content of the EVENT_3_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_3_CNT register. * * \return the description of EVENT_3_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_CNT_DESC; } /** * Get the offset of the EVENT_3_CNT register. * * \return the offset of EVENT_3_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_3_CNT_OFFSET; } /** * Get the address of the EVENT_3_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_3_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_3_CNT_ADDR(instance); } /** * Read the content of the EVENT_3_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_3_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_3_CNT_GET(instance); } /** * Write the content of the EVENT_3_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_3_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_3_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_3_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_3_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_3_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_3_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_3_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_3_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_3_CNT register. * * \return the description of the CNT field of EVENT_3_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_3_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_3_CNT register. * * \param[in] reg is the value of the EVENT_3_CNT register * * \return the content of the CNT field belonging to EVENT_3_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_3_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_3_CNT register. * * \param[in] reg is the value of the EVENT_3_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_3_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_3_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_3_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_4_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_4_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_OFFSET 0x94UL /** Reset value of the EVENT_4_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB) /** Description of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_DESC "Observer counter register 5" /** Address of the EVENT_4_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_4_CNT_OFFSET) /** Get the content of the EVENT_4_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(UNIT))) /** Set the content of the EVENT_4_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_4_CNT register. * * \return the description of EVENT_4_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_CNT_DESC; } /** * Get the offset of the EVENT_4_CNT register. * * \return the offset of EVENT_4_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_4_CNT_OFFSET; } /** * Get the address of the EVENT_4_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_4_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_4_CNT_ADDR(instance); } /** * Read the content of the EVENT_4_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_4_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_4_CNT_GET(instance); } /** * Write the content of the EVENT_4_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_4_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_4_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_4_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_4_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_4_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_4_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_4_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_4_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_4_CNT register. * * \return the description of the CNT field of EVENT_4_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_4_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_4_CNT register. * * \param[in] reg is the value of the EVENT_4_CNT register * * \return the content of the CNT field belonging to EVENT_4_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_4_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_4_CNT register. * * \param[in] reg is the value of the EVENT_4_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_4_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_4_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_4_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_5_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_5_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_OFFSET 0x98UL /** Reset value of the EVENT_5_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB) /** Description of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_DESC "Observer counter register 6" /** Address of the EVENT_5_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_5_CNT_OFFSET) /** Get the content of the EVENT_5_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(UNIT))) /** Set the content of the EVENT_5_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_5_CNT register. * * \return the description of EVENT_5_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_CNT_DESC; } /** * Get the offset of the EVENT_5_CNT register. * * \return the offset of EVENT_5_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_5_CNT_OFFSET; } /** * Get the address of the EVENT_5_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_5_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_5_CNT_ADDR(instance); } /** * Read the content of the EVENT_5_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_5_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_5_CNT_GET(instance); } /** * Write the content of the EVENT_5_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_5_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_5_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_5_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_5_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_5_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_5_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_5_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_5_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_5_CNT register. * * \return the description of the CNT field of EVENT_5_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_5_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_5_CNT register. * * \param[in] reg is the value of the EVENT_5_CNT register * * \return the content of the CNT field belonging to EVENT_5_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_5_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_5_CNT register. * * \param[in] reg is the value of the EVENT_5_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_5_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_5_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_5_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_6_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_6_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_OFFSET 0x9cUL /** Reset value of the EVENT_6_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB) /** Description of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_DESC "Observer counter register 7" /** Address of the EVENT_6_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_6_CNT_OFFSET) /** Get the content of the EVENT_6_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(UNIT))) /** Set the content of the EVENT_6_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_6_CNT register. * * \return the description of EVENT_6_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_CNT_DESC; } /** * Get the offset of the EVENT_6_CNT register. * * \return the offset of EVENT_6_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_6_CNT_OFFSET; } /** * Get the address of the EVENT_6_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_6_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_6_CNT_ADDR(instance); } /** * Read the content of the EVENT_6_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_6_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_6_CNT_GET(instance); } /** * Write the content of the EVENT_6_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_6_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_6_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_6_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_6_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_6_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_6_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_6_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_6_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_6_CNT register. * * \return the description of the CNT field of EVENT_6_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_6_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_6_CNT register. * * \param[in] reg is the value of the EVENT_6_CNT register * * \return the content of the CNT field belonging to EVENT_6_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_6_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_6_CNT register. * * \param[in] reg is the value of the EVENT_6_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_6_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_6_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_6_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_7_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_7_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_OFFSET 0xa0UL /** Reset value of the EVENT_7_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB) /** Description of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_DESC "Observer counter register 8" /** Address of the EVENT_7_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_7_CNT_OFFSET) /** Get the content of the EVENT_7_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(UNIT))) /** Set the content of the EVENT_7_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_7_CNT register. * * \return the description of EVENT_7_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_CNT_DESC; } /** * Get the offset of the EVENT_7_CNT register. * * \return the offset of EVENT_7_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_7_CNT_OFFSET; } /** * Get the address of the EVENT_7_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_7_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_7_CNT_ADDR(instance); } /** * Read the content of the EVENT_7_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_7_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_7_CNT_GET(instance); } /** * Write the content of the EVENT_7_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_7_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_7_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_7_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_7_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_7_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_7_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_7_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_7_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_7_CNT register. * * \return the description of the CNT field of EVENT_7_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_7_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_7_CNT register. * * \param[in] reg is the value of the EVENT_7_CNT register * * \return the content of the CNT field belonging to EVENT_7_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_7_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_7_CNT register. * * \param[in] reg is the value of the EVENT_7_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_7_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_7_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_7_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_8_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_8_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_OFFSET 0xa4UL /** Reset value of the EVENT_8_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB) /** Description of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_DESC "Observer counter register 9" /** Address of the EVENT_8_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_8_CNT_OFFSET) /** Get the content of the EVENT_8_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(UNIT))) /** Set the content of the EVENT_8_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_8_CNT register. * * \return the description of EVENT_8_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_CNT_DESC; } /** * Get the offset of the EVENT_8_CNT register. * * \return the offset of EVENT_8_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_8_CNT_OFFSET; } /** * Get the address of the EVENT_8_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_8_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_8_CNT_ADDR(instance); } /** * Read the content of the EVENT_8_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_8_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_8_CNT_GET(instance); } /** * Write the content of the EVENT_8_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_8_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_8_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_8_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_8_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_8_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_8_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_8_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_8_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_8_CNT register. * * \return the description of the CNT field of EVENT_8_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_8_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_8_CNT register. * * \param[in] reg is the value of the EVENT_8_CNT register * * \return the content of the CNT field belonging to EVENT_8_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_8_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_8_CNT register. * * \param[in] reg is the value of the EVENT_8_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_8_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_8_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_8_CNT_SET_CNT(reg, data); } /* ************************************************** EVENT_9_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_9_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_OFFSET 0xa8UL /** Reset value of the EVENT_9_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB) /** Description of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_DESC "Observer counter register 10" /** Address of the EVENT_9_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_9_CNT_OFFSET) /** Get the content of the EVENT_9_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(UNIT))) /** Set the content of the EVENT_9_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_9_CNT register. * * \return the description of EVENT_9_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_CNT_DESC; } /** * Get the offset of the EVENT_9_CNT register. * * \return the offset of EVENT_9_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_9_CNT_OFFSET; } /** * Get the address of the EVENT_9_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_9_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_9_CNT_ADDR(instance); } /** * Read the content of the EVENT_9_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_9_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_9_CNT_GET(instance); } /** * Write the content of the EVENT_9_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_9_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_9_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_9_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_9_CNT register ---------------------------------------------------------- */ /** Description of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_9_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_9_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_9_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_9_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_9_CNT register. * * \return the description of the CNT field of EVENT_9_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_9_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_9_CNT register. * * \param[in] reg is the value of the EVENT_9_CNT register * * \return the content of the CNT field belonging to EVENT_9_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_9_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_9_CNT register. * * \param[in] reg is the value of the EVENT_9_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_9_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_9_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_9_CNT_SET_CNT(reg, data); } /* ************************************************* EVENT_10_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_10_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_OFFSET 0xacUL /** Reset value of the EVENT_10_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB) /** Description of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_DESC "Observer counter register 11" /** Address of the EVENT_10_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_10_CNT_OFFSET) /** Get the content of the EVENT_10_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(UNIT))) /** Set the content of the EVENT_10_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_10_CNT register. * * \return the description of EVENT_10_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_CNT_DESC; } /** * Get the offset of the EVENT_10_CNT register. * * \return the offset of EVENT_10_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_10_CNT_OFFSET; } /** * Get the address of the EVENT_10_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_10_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_10_CNT_ADDR(instance); } /** * Read the content of the EVENT_10_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_10_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_10_CNT_GET(instance); } /** * Write the content of the EVENT_10_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_10_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_10_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_10_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_10_CNT register --------------------------------------------------------- */ /** Description of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_10_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_10_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_10_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_10_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_10_CNT register. * * \return the description of the CNT field of EVENT_10_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_10_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_10_CNT register. * * \param[in] reg is the value of the EVENT_10_CNT register * * \return the content of the CNT field belonging to EVENT_10_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_10_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_10_CNT register. * * \param[in] reg is the value of the EVENT_10_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_10_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_10_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_10_CNT_SET_CNT(reg, data); } /* ************************************************* EVENT_11_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_11_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_OFFSET 0xb0UL /** Reset value of the EVENT_11_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB) /** Description of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_DESC "Observer counter register 12" /** Address of the EVENT_11_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_11_CNT_OFFSET) /** Get the content of the EVENT_11_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(UNIT))) /** Set the content of the EVENT_11_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_11_CNT register. * * \return the description of EVENT_11_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_CNT_DESC; } /** * Get the offset of the EVENT_11_CNT register. * * \return the offset of EVENT_11_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_11_CNT_OFFSET; } /** * Get the address of the EVENT_11_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_11_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_11_CNT_ADDR(instance); } /** * Read the content of the EVENT_11_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_11_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_11_CNT_GET(instance); } /** * Write the content of the EVENT_11_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_11_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_11_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_11_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_11_CNT register --------------------------------------------------------- */ /** Description of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_11_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_11_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_11_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_11_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_11_CNT register. * * \return the description of the CNT field of EVENT_11_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_11_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_11_CNT register. * * \param[in] reg is the value of the EVENT_11_CNT register * * \return the content of the CNT field belonging to EVENT_11_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_11_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_11_CNT register. * * \param[in] reg is the value of the EVENT_11_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_11_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_11_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_11_CNT_SET_CNT(reg, data); } /* ************************************************* EVENT_12_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_12_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_OFFSET 0xb4UL /** Reset value of the EVENT_12_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB) /** Description of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_DESC "Observer counter register 13" /** Address of the EVENT_12_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_12_CNT_OFFSET) /** Get the content of the EVENT_12_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(UNIT))) /** Set the content of the EVENT_12_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_12_CNT register. * * \return the description of EVENT_12_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_CNT_DESC; } /** * Get the offset of the EVENT_12_CNT register. * * \return the offset of EVENT_12_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_12_CNT_OFFSET; } /** * Get the address of the EVENT_12_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_12_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_12_CNT_ADDR(instance); } /** * Read the content of the EVENT_12_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_12_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_12_CNT_GET(instance); } /** * Write the content of the EVENT_12_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_12_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_12_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_12_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_12_CNT register --------------------------------------------------------- */ /** Description of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_12_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_12_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_12_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_12_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_12_CNT register. * * \return the description of the CNT field of EVENT_12_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_12_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_12_CNT register. * * \param[in] reg is the value of the EVENT_12_CNT register * * \return the content of the CNT field belonging to EVENT_12_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_12_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_12_CNT register. * * \param[in] reg is the value of the EVENT_12_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_12_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_12_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_12_CNT_SET_CNT(reg, data); } /* ************************************************* EVENT_13_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_13_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_OFFSET 0xb8UL /** Reset value of the EVENT_13_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB) /** Description of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_DESC "Observer counter register 14" /** Address of the EVENT_13_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_13_CNT_OFFSET) /** Get the content of the EVENT_13_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(UNIT))) /** Set the content of the EVENT_13_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_13_CNT register. * * \return the description of EVENT_13_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_CNT_DESC; } /** * Get the offset of the EVENT_13_CNT register. * * \return the offset of EVENT_13_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_13_CNT_OFFSET; } /** * Get the address of the EVENT_13_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_13_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_13_CNT_ADDR(instance); } /** * Read the content of the EVENT_13_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_13_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_13_CNT_GET(instance); } /** * Write the content of the EVENT_13_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_13_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_13_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_13_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_13_CNT register --------------------------------------------------------- */ /** Description of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_13_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_13_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_13_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_13_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_13_CNT register. * * \return the description of the CNT field of EVENT_13_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_13_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_13_CNT register. * * \param[in] reg is the value of the EVENT_13_CNT register * * \return the content of the CNT field belonging to EVENT_13_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_13_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_13_CNT register. * * \param[in] reg is the value of the EVENT_13_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_13_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_13_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_13_CNT_SET_CNT(reg, data); } /* ************************************************* EVENT_14_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_14_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_OFFSET 0xbcUL /** Reset value of the EVENT_14_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB) /** Description of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_DESC "Observer counter register 15" /** Address of the EVENT_14_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_14_CNT_OFFSET) /** Get the content of the EVENT_14_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(UNIT))) /** Set the content of the EVENT_14_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_14_CNT register. * * \return the description of EVENT_14_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_CNT_DESC; } /** * Get the offset of the EVENT_14_CNT register. * * \return the offset of EVENT_14_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_14_CNT_OFFSET; } /** * Get the address of the EVENT_14_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_14_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_14_CNT_ADDR(instance); } /** * Read the content of the EVENT_14_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_14_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_14_CNT_GET(instance); } /** * Write the content of the EVENT_14_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_14_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_14_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_14_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_14_CNT register --------------------------------------------------------- */ /** Description of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_14_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_14_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_14_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_14_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_14_CNT register. * * \return the description of the CNT field of EVENT_14_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_14_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_14_CNT register. * * \param[in] reg is the value of the EVENT_14_CNT register * * \return the content of the CNT field belonging to EVENT_14_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_14_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_14_CNT register. * * \param[in] reg is the value of the EVENT_14_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_14_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_14_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_14_CNT_SET_CNT(reg, data); } /* ************************************************* EVENT_15_CNT register of one of the DEBUG_TRACE Units ************************************************** */ /** Offset of the EVENT_15_CNT register from the base address of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_OFFSET 0xc0UL /** Reset value of the EVENT_15_CNT register of the DEBUG_TRACE Unit. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DT \ (ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DT << ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB) /** Description of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_DESC "Observer counter register 16" /** Address of the EVENT_15_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(UNIT) (ATON_DEBUG_TRACE_BASE(UNIT) + ATON_DEBUG_TRACE_EVENT_15_CNT_OFFSET) /** Get the content of the EVENT_15_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_GET(UNIT) (*((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(UNIT))) /** Set the content of the EVENT_15_CNT register of one of the DEBUG_TRACE Units. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_SET(UNIT, DATA) do { *((volatile uint32_t *)(uintptr_t)ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(UNIT)) = (DATA); } while (0); /** * Get the description of EVENT_15_CNT register. * * \return the description of EVENT_15_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_CNT_GetDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_CNT_DESC; } /** * Get the offset of the EVENT_15_CNT register. * * \return the offset of EVENT_15_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_GetOffset(void) { return ATON_DEBUG_TRACE_EVENT_15_CNT_OFFSET; } /** * Get the address of the EVENT_15_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15_CNT register whose address must be returned * (it must be instance \< 1<\em>) * * \return the address of EVENT_15_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_GetAddr(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_15_CNT_ADDR(instance); } /** * Read the content of the EVENT_15_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15_CNT register whose content must be retrieved * (it must be instance \< 1<\em>) * * \return the content of EVENT_15_CNT register belonging to Unit having index \e instance among the DEBUG_TRACE Units */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_Get(uint32_t instance) { return ATON_DEBUG_TRACE_EVENT_15_CNT_GET(instance); } /** * Write the content of the EVENT_15_CNT register. * * \param[in] instance is the index of the Unit (among the DEBUG_TRACE Units) containing the EVENT_15_CNT register whose content must be modified * (it must be instance \< 1<\em>) * \param[in] data is 32-bit value that must be written to the register */ static inline void ATON_DEBUG_TRACE_EVENT_15_CNT_Set(uint32_t instance, uint32_t data) { ATON_DEBUG_TRACE_EVENT_15_CNT_SET(instance, data); } /* --------------------------------------------------------- CNT field of the EVENT_15_CNT register --------------------------------------------------------- */ /** Description of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DESC "Event counter" /** Offset of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB 0UL /** Size in bits of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_W (32UL) /** Mask for retrieving the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_MASK ATON_FIELD_MASK(0UL, 32UL) /** Reset value of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DT 0x0UL /** Access rights of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_AC "RW" /** Check whether access to the CNT field of the EVENT_15_CNT register is secured or not. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_S 0 /** Check whether access to the CNT field of the EVENT_15_CNT register is privileged or not. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_P 0 /** Read the content of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_GET_CNT(REG) ATON_GET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_W) /** Modify the content of the CNT field of the EVENT_15_CNT register. */ #define ATON_DEBUG_TRACE_EVENT_15_CNT_SET_CNT(REG, DATA) ATON_SET_FIELD(REG, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_LSB, ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_W, DATA) /** * Get the description of the CNT field of EVENT_15_CNT register. * * \return the description of the CNT field of EVENT_15_CNT register */ static inline const int8_t *ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_GetdDesc(void) { return (const int8_t *)ATON_DEBUG_TRACE_EVENT_15_CNT_CNT_DESC; } /** * Read the content of the CNT field of the EVENT_15_CNT register. * * \param[in] reg is the value of the EVENT_15_CNT register * * \return the content of the CNT field belonging to EVENT_15_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_Get_CNT(uint32_t reg) { return ATON_DEBUG_TRACE_EVENT_15_CNT_GET_CNT(reg); } /** * Write the content of the CNT field of the EVENT_15_CNT register. * * \param[in] reg is the value of the EVENT_15_CNT register * \param[in] data is 32-bit value that must be written to the field * * \return the new content of the CNT field belonging to EVENT_15_CNT register */ static inline uint32_t ATON_DEBUG_TRACE_EVENT_15_CNT_Set_CNT(uint32_t reg, uint32_t data) { return ATON_DEBUG_TRACE_EVENT_15_CNT_SET_CNT(reg, data); } /*@}*/ #ifdef __cplusplus } #endif #endif // #ifndef ATON_H