0x433 STMicroelectronics MCU Cortex-M4 STM32F401xD/E STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0x8 RW Write protection active Write protection not active WRP0 0x10 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x8 RW Write protection active Write protection not active WRP0 0x0 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i