0x472 STMicroelectronics MCU Cortex-M33 STM32L5xx STM32L5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0x00 RWE Single Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Single 0x8 Dual 0x8 Dual 0x8 Single 0x8 Single 0x8 Dual 0x8 Dual 0x8 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0xFF RWE Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW Secure area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW