0x484 STMicroelectronics MCU Cortex-M33 STM32H56x/573 STM32H5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0xFF RWE Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x10 Dual 0x10 Dual 0x10 Dual 0x10 Dual 0x10 Dual 0x10 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0xFF RWE Single 0x10 Single 0x10 Single 0x10 Single 0x10 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Product state PRODUCT_STATE Life state code. 0x8 0x8 R Open Provisioning, Debug partially opened (only non-secure) iRoT-provisioned, Debug partially opened (only non-secure) TZ-Closed, Debug partially opened (only non-secure) Closed, Debug disabled, regression is possible Locked PRODUCT_STATE Life state code. 0x8 0x8 W Open Provisioning, Debug partially opened (only non-secure) iRoT-provisioned, Debug partially opened (only non-secure) TZ-Closed, Debug partially opened (only non-secure) Closed, Debug disabled, regression is possible Locked BOR Level BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R disabled enabled BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W disabled enabled User Configuration IO_VDD_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDD_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x11 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x11 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 R Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 W Independent watchdog frozen in system standby mode Independent watchdog keep running in standby Stop mode. BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 R OEM-iRoT (user flash) selected ST-iRoT (system flash) selected BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 W OEM-iRoT (user flash) selected ST-iRoT (system flash) selected SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 R a reset is generated when entering Stop or Stop2 mode on core domain no reset generated when entering Stop or Stop2 mode on core domain NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 W a reset is generated when entering Stop or Stop2 mode on core domain no reset generated when entering Stop or Stop2 mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain User Configuration 2 TZEN Trust Zone Enable configuration bits 0x18 0x8 R Trust zone disabled Trust zone enabled SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 R SRAM3 ECC check enabled SRAM3 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x3 0x1 R SRAM2 erase when system reset SRAM2 not erased when a system reset occurs SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 0x2 0x1 R SRAM1 and SRAM3 erased when a system reset occurs SRAM1 and SRAM3 not erased when a system reset occurs TZEN Trust Zone Enable configuration bits 0x18 0x8 W Trust zone disabled Trust zone enabled SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 W SRAM3 ECC check enabled SRAM3 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x3 0x1 W SRAM2 erase when system reset SRAM2 not erased when a system reset occurs SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 0x2 0x1 W SRAM1 and SRAM3 erased when a system reset occurs SRAM1 and SRAM3 not erased when a system reset occurs Boot Configuration NSBOOTADD Non secure unique boot entry address 0x8 0x18 R NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings 0x0 0x8 R The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). NSBOOTADD Non secure unique boot entry address 0x8 0x18 W NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings 0x0 0x8 W The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOT_LOCK A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0x0 0x8 R The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOTADD Unique Boot Entry Secure Adress 0x8 0x18 R SECBOOT_LOCK A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0x0 0x8 W The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOTADD Unique Boot Entry Secure Adress. 0x8 0x18 W Bank1 - Flash watermark area definition SECWM1_STRT Bank 1 security WM area 1 start sector 0x0 0x7 R SECWM1_END Bank 1 security WM area 1 end sector 0x10 0x7 R SECWM1_STRT Bank 1 security WM area 1 start sector 0x0 0x7 W SECWM1_END Bank 1 security WM area 1 end sector 0x10 0x7 W Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 W Bank2 - Flash watermark area definition SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 R SECWM2_END Bank 2 security WM area end sector 0x10 0x7 R SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 R SECWM2_END Bank 2 security WM area end sector 0x10 0x7 R SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 W SECWM2_END Bank 2 security WM area end sector 0x10 0x7 W SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 W SECWM2_END Bank 2 security WM area end sector 0x10 0x7 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash data bank 1 sectors EDATA1_EN Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used EDATA1_STRT EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 R EDATA1_EN Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used EDATA1_STRT EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 W Flash data bank 2 sectors EDATA2_EN Bank2 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used EDATA2_STRT EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 R EDATA2_EN Bank2 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used EDATA2_STRT EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 W Flash HDP bank 1 HDP1_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 R HDP1_END HDP barrier end set in number of 8kb sectors 0x10 0x7 R HDP1_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 W HDP1_END HDP barrier end set in number of 8kb sectors 0x10 0x7 W Flash HDP bank 2 HDP2_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 R HDP2_END HDP barrier end set in number of 8kb sectors 0x10 0x7 R HDP2_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 W HDP2_END HDP barrier end set in number of 8kb sectors 0x10 0x7 W Product state PRODUCT_STATE Life state code. 0x8 0x8 R Open Provisioning, Debug partially opened (only non-secure) iRoT-provisioned, Debug partially opened (only non-secure) TZ-Closed, Debug partially opened (only non-secure) Closed, Debug disabled, regression is possible Locked PRODUCT_STATE Life state code. 0x8 0x8 W Open Provisioning, Debug partially opened (only non-secure) iRoT-provisioned, Debug partially opened (only non-secure) TZ-Closed, Debug partially opened (only non-secure) Closed, Debug disabled, regression is possible Locked BOR Level BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R disabled enabled BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W disabled enabled User Configuration IO_VDD_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDD_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x11 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x11 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 R Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 W Independent watchdog frozen in system standby mode Independent watchdog keep running in standby Stop mode. BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 R OEM-iRoT (user flash) selected ST-iRoT (system flash) selected BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 W OEM-iRoT (user flash) selected ST-iRoT (system flash) selected SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 R a reset is generated when entering Stop or Stop2 mode on core domain no reset generated when entering Stop or Stop2 mode on core domain NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 W a reset is generated when entering Stop or Stop2 mode on core domain no reset generated when entering Stop or Stop2 mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain User Configuration 2 TZEN Trust Zone Enable configuration bits 0x18 0x8 R Trust zone disabled Trust zone enabled SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 R SRAM3 ECC check enabled SRAM3 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x3 0x1 R SRAM2 erase when system reset SRAM2 not erased when a system reset occurs SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 0x2 0x1 R SRAM1 and SRAM3 erased when a system reset occurs SRAM1 and SRAM3 not erased when a system reset occurs TZEN Trust Zone Enable configuration bits 0x18 0x8 W Trust zone disabled Trust zone enabled SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 W SRAM3 ECC check enabled SRAM3 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x3 0x1 W SRAM2 erase when system reset SRAM2 not erased when a system reset occurs SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 0x2 0x1 W SRAM1 and SRAM3 erased when a system reset occurs SRAM1 and SRAM3 not erased when a system reset occurs Boot Configuration NSBOOTADD Non secure unique boot entry address 0x8 0x18 R NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings 0x0 0x8 R The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). NSBOOTADD Non secure unique boot entry address 0x8 0x18 W NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings 0x0 0x8 W The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOT_LOCK A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0x0 0x8 R The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOTADD Unique Boot Entry Secure Adress 0x8 0x18 R SECBOOT_LOCK A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0x0 0x8 W The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOTADD Unique Boot Entry Secure Adress. 0x8 0x18 W Bank1 - Flash watermark area definition SECWM1_STRT Bank 1 security WM area 1 start sector 0x0 0x7 R SECWM1_END Bank 1 security WM area 1 end sector 0x10 0x7 R SECWM1_STRT Bank 1 security WM area 1 start sector 0x0 0x7 W SECWM1_END Bank 1 security WM area 1 end sector 0x10 0x7 W Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 W Bank2 - Flash watermark area definition SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 R SECWM2_END Bank 2 security WM area end sector 0x10 0x7 R SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 R SECWM2_END Bank 2 security WM area end sector 0x10 0x7 R SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 W SECWM2_END Bank 2 security WM area end sector 0x10 0x7 W SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 W SECWM2_END Bank 2 security WM area end sector 0x10 0x7 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash data bank 1 sectors EDATA1_EN Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used EDATA1_STRT EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 R EDATA1_EN Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used EDATA1_STRT EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 W Flash data bank 2 sectors EDATA2_EN Bank2 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used EDATA2_STRT EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 R EDATA2_EN Bank2 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used EDATA2_STRT EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 W Flash HDP bank 1 HDP1_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 R HDP1_END HDP barrier end set in number of 8kb sectors 0x10 0x7 R HDP1_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 W HDP1_END HDP barrier end set in number of 8kb sectors 0x10 0x7 W Flash HDP bank 2 HDP2_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 R HDP2_END HDP barrier end set in number of 8kb sectors 0x10 0x7 R HDP2_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 W HDP2_END HDP barrier end set in number of 8kb sectors 0x10 0x7 W Product state PRODUCT_STATE Life state code. 0x8 0x8 R Open Provisioning, Debug partially opened (only non-secure) iRoT-provisioned, Debug partially opened (only non-secure) TZ-Closed, Debug partially opened (only non-secure) Closed, Debug disabled, regression is possible Locked PRODUCT_STATE Life state code. 0x8 0x8 W Open Provisioning, Debug partially opened (only non-secure) iRoT-provisioned, Debug partially opened (only non-secure) TZ-Closed, Debug partially opened (only non-secure) Closed, Debug disabled, regression is possible Locked BOR Level BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R disabled enabled BORH_EN Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W disabled enabled User Configuration IO_VDD_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDD_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x11 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x11 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 R Independent watchdog frozen in system standby mode Independent watchdog keep running in system standby mode. IWDG_STDBY Standby mode freeze option status bit. 0x15 0x1 W Independent watchdog frozen in system standby mode Independent watchdog keep running in standby Stop mode. BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 R OEM-iRoT (user flash) selected ST-iRoT (system flash) selected BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 W OEM-iRoT (user flash) selected ST-iRoT (system flash) selected SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 R a reset is generated when entering Stop or Stop2 mode on core domain no reset generated when entering Stop or Stop2 mode on core domain NRST_STOP Core domain Stop entry reset option status bit. 0x6 0x1 W a reset is generated when entering Stop or Stop2 mode on core domain no reset generated when entering Stop or Stop2 mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDBY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain User Configuration 2 TZEN Trust Zone Enable configuration bits 0x18 0x8 R Trust zone disabled Trust zone enabled SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 R SRAM3 ECC check enabled SRAM3 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x3 0x1 R SRAM2 erase when system reset SRAM2 not erased when a system reset occurs SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 0x2 0x1 R SRAM1 and SRAM3 erased when a system reset occurs SRAM1 and SRAM3 not erased when a system reset occurs TZEN Trust Zone Enable configuration bits 0x18 0x8 W Trust zone disabled Trust zone enabled SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 W SRAM3 ECC check enabled SRAM3 ECC check disabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W BKPRAM ECC check enabled BKPRAM ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x3 0x1 W SRAM2 erase when system reset SRAM2 not erased when a system reset occurs SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 0x2 0x1 W SRAM1 and SRAM3 erased when a system reset occurs SRAM1 and SRAM3 not erased when a system reset occurs Boot Configuration NSBOOTADD Non secure unique boot entry address 0x8 0x18 R NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings 0x0 0x8 R The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). NSBOOTADD Non secure unique boot entry address 0x8 0x18 W NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings 0x0 0x8 W The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOT_LOCK A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0x0 0x8 R The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOTADD Unique Boot Entry Secure Adress 0x8 0x18 R SECBOOT_LOCK A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0x0 0x8 W The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). SECBOOTADD Unique Boot Entry Secure Adress. 0x8 0x18 W Bank1 - Flash watermark area definition SECWM1_STRT Bank 1 security WM area 1 start sector 0x0 0x7 R SECWM1_END Bank 1 security WM area 1 end sector 0x10 0x7 R SECWM1_STRT Bank 1 security WM area 1 start sector 0x0 0x7 W SECWM1_END Bank 1 security WM area 1 end sector 0x10 0x7 W Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash data bank 1 sectors EDATA1_EN Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used EDATA1_STRT EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 R EDATA1_EN Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used EDATA1_STRT EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 W Flash HDP bank 1 HDP1_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 R HDP1_END HDP barrier end set in number of 8kb sectors 0x10 0x7 R HDP1_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 W HDP1_END HDP barrier end set in number of 8kb sectors 0x10 0x7 W Bank2 - Flash watermark area definition SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 R SECWM2_END Bank 2 security WM area end sector 0x10 0x7 R SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 R SECWM2_END Bank 2 security WM area end sector 0x10 0x7 R SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 W SECWM2_END Bank 2 security WM area end sector 0x10 0x7 W SECWM2_STRT Bank 2 security WM area start sector 0x0 0x7 W SECWM2_END Bank 2 security WM area end sector 0x10 0x7 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 W Flash data bank 2 sectors EDATA2_EN Bank2 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used EDATA2_STRT EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 R EDATA2_EN Bank2 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used EDATA2_STRT EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 W Flash HDP bank 2 HDP2_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 R HDP2_END HDP barrier end set in number of 8kb sectors 0x10 0x7 R HDP2_STRT HDP barrier start set in number of 8kb sectors 0x0 0x7 W HDP2_END HDP barrier end set in number of 8kb sectors 0x10 0x7 W