0x489 STMicroelectronics MCU Cortex-M0+ STM32U0xx STM32U0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV This bitfield contains the VDD supply level threshold that activates/releases the reset 0x8 0x3 RW BOR level 0, reset level threshold around 1.7 V BOR level 1, reset level threshold around 2.0 V BOR level 2, reset level threshold around 2.2 V BOR level 3, reset level threshold around 2.5 V BOR level 4, reset level threshold around 2.8 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW RAM_PARITY_CHECK enable RAM_PARITY_CHECK disable BKPSRAM_HW_ERASE_DISABLE 0x17 0x1 RW Backup SRAM is erased on system reset Backup SRAM content is kept when a system reset occurs NBOOT_SEL 0x18 0x1 RW BOOT0 pin (legacy mode) NBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset input only Standard GPIO:only internal RESET is possible Bidirectional reset:The NRST pin is configured in reset input/output (legacy) mode BDRST 0x15 0x1 RW Backup domain not reset on shutdown exit Reset of backup domaine(RTC registers and backup registers)forsed on shutdown exit IRHEN 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level Write Protection WRP1A_STRT Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect 0x0 0x7 RW WRP1A_END End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. 0x10 0x7 RW WRP1B_STRT Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect 0x0 0x7 RW WRP1B_END End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect 0x10 0x7 RW FLASH security HDP1_PEND Securable memory area size 0x0 0x7 RW BOOT_lOCK Used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory HDP1EN Hide protection area enable 0x18 0x8 RW no HDP area or any value other than 0xB4 HDP area enabled Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV This bitfield contains the VDD supply level threshold that activates/releases the reset 0x8 0x3 RW BOR level 0, reset level threshold around 1.7 V BOR level 1, reset level threshold around 2.0 V BOR level 2, reset level threshold around 2.2 V BOR level 3, reset level threshold around 2.5 V BOR level 4, reset level threshold around 2.8 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW RAM_PARITY_CHECK enable RAM_PARITY_CHECK disable BKPSRAM_HW_ERASE_DISABLE 0x17 0x1 RW Backup SRAM is erased on system reset Backup SRAM content is kept when a system reset occurs NBOOT_SEL 0x18 0x1 RW BOOT0 pin (legacy mode) NBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset input only Standard GPIO:only internal RESET is possible Bidirectional reset:The NRST pin is configured in reset input/output (legacy) mode BDRST 0x15 0x1 RW Backup domain not reset on shutdown exit Reset of backup domaine(RTC registers and backup registers)forsed on shutdown exit IRHEN 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level Write Protection WRP1A_STRT Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect 0x0 0x7 RW WRP1A_END End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. 0x10 0x7 RW WRP1B_STRT Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect 0x0 0x7 RW WRP1B_END End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect 0x10 0x7 RW FLASH security HDP1_PEND Securable memory area size 0x0 0x7 RW BOOT_lOCK Used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory HDP1EN Hide protection area enable 0x18 0x8 RW no HDP area or any value other than 0xB4 HDP area enabled