0x492 STMicroelectronics MCU Cortex-M33 STM32WBA52/54/55 STM32WBA ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0xFF RWE Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode SRAM1_RST SRAM1 erase upon system reset 0xF 0x1 RW SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 PE check enabled SRAM2 PE check disabled SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW Write Protection WRPA_PSTRT WPR first area "A" start page 0x0 0x7 RW WRPA_PEND WPR first area "A" end page 0x10 0x7 RW UNLOCK_A WPR first area A unlock 0x1F 0x1 RW WRPA start and end pages locked WRPA start and end pages unlocked WRPB_PSTRT WPR second area "B" start page 0x0 0x7 RW WRPB_PEND WPR second area "B" end page 0x10 0x7 RW UNLOCK_B WPR second area B unlock 0x1F 0x1 RW WRPB start and end pages locked WRPB start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode SRAM1_RST SRAM1 erase upon system reset 0xF 0x1 RW SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area SECWM_PSTRT Start page of secure area 0x0 0x7 RW SECWM_PEND End page of first secure area 0x10 0x7 RW HDP_PEND End page of secure hide protection area 0x10 0x7 RW HDPEN Secure Hide protection first area enable 0x1F 0x1 RW No secHDP area HDP first area is enabled Write Protection 1 WRPA_PSTRT WPR first area "A" start page 0x0 0x7 RW WRPA_PEND WPR first area "A" end page 0x10 0x7 RW UNLOCK_A WPR first area A unlock 0x1F 0x1 RW WRPA start and end pages locked WRPA start and end pages unlocked WRPB_PSTRT WPR second area "B" start page 0x0 0x7 RW WRPB_PEND WPR second area "B" end page 0x10 0x7 RW UNLOCK_B WPR second area B unlock 0x1F 0x1 RW WRPB start and end pages locked WRPB start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode SRAM1_RST SRAM1 erase upon system reset 0xF 0x1 RW SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area SECWM_PSTRT Start page of first secure area 0x0 0x7 RW SECWM_PEND End page of first secure area 0x10 0x7 RW HDP_PEND End page of secure hide protection area 0x10 0x7 RW HDPEN Secure Hide protection area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled Write Protection WRPA_PSTRT WPR area A "A" start page 0x0 0x7 RW WRPA_PEND WPR area A "A" end page 0x10 0x7 RW UNLOCK_A WPR area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRPB_PSTRT WPR area B "B" start page 0x0 0x7 RW WRPB_PEND WPR area B "B" end page 0x10 0x7 RW UNLOCK_B WPR area B unlock 0x1F 0x1 RW WRPB start and end pages locked WRPB start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 1, read protection of memories Level 2, chip protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode SRAM1_RST SRAM1 erase upon system reset 0xF 0x1 RW SRAM1 erased when a system reset occurs SRAM1 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled Boot Configuration NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area SECWM_PSTRT Start page of first secure area 0x0 0x7 RW SECWM_PEND End page of first secure area 0x10 0x7 RW HDP_PEND End page of secure hide protection area 0x10 0x7 RW HDPEN Secure Hide protection area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled Write Protection WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK_1A Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK_1B Bank 1 WPR second area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked RDP Level 1 Password OEM1KEYR1 OEM1 least significant bytes key 0x0 0x20 RW OEM1KEYR2 OEM1 most significant bytes key 0x0 0x20 RW RDP Level 2 Password OEM2KEYR1 OEM2 least significant bytes key 0x0 0x20 RW OEM2KEYR2 OEM2 most significant bytes key 0x0 0x20 RW