0x495 STMicroelectronics MCU Cortex-M0+/M4 STM32WB5x/35xx STM32WB ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0xFF RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 Boot selected based on nBOOT1 nBOOT0=1 Boot from main Flash nBOOT1 0x17 0x1 RW Boot from code area if BOOT0=0 otherwise embedded SRAM Boot from code area if BOOT0=0 otherwise system Flash nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDGSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes - 1 ESE 0x8 0x1 R Security disabled Security enabled PCROP Protection PCROP1A_STRT Flash Area 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Area 2 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW Security Configuration Option bytes - 2 SFSA Secure Flash start address 0x0 0x8 RW FSD 0x8 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD If FSD=1 : SRAM2b is non-secure. If FSD=0 : 0x1E 0x1 RW SRAM2b is secure SRAM2b is non-secure SNBRSA SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. 0x19 0x5 RW BRSD If FSD=1 : SRAM2a is non-secure. If FSD=0 : 0x17 0x1 RW SRAM2a is secure SRAM2a is non-secure SBRSA SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. 0x12 0x5 RW SBRV Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. 0x0 0x12 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 Boot selected based on nBOOT1 nBOOT0=1 Boot from main Flash nBOOT1 0x17 0x1 RW Boot from Flash if nBoot0=0 otherwise embedded SRAM Boot from Flash if nBoot0=0 otherwise system memory nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDGSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE 0x8 0x1 R Security disabled Security enabled SFSA Secure Flash start address 0x0 0x8 RW FSD 0x8 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD If FSD=1 : SRAM2b is non-secure. If FSD=0 : 0x1E 0x1 RW SRAM2b is secure SRAM2b is non-secure SNBRSA SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. 0x19 0x5 RW BRSD If FSD=1: SRAM2a is non-secure. If FSD=0 : 0x17 0x1 RW SRAM2a is secure SRAM2a is non-secure SBRSA SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. 0x12 0x5 RW SBRV Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. 0x0 0x12 RW PCROP Protection PCROP1A_STRT Flash Area 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Area 2 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW