0x501 STMicroelectronics MPU Cortex-A7 STM32MP13xx STM32MP ARM 32-bit Cortex-A7 based device, CPU clock up to 600MHz Embedded SRAM Storage 0xFF RWE Single OTP Memory Configuration RW Struct version version Structure version 0x0 0x20 R Global Status Structure global state 0x0 0x20 R OTP0 Data0 Data 0x0 0x20 R Status0 Status 0x4 0x20 R OTP1 Data1 Data 0x0 0x20 R Status1 Status 0x4 0x20 R RPN RPN Coding 0x0 0xC R STM32MP131A STM32MP131C STM32MP131D STM32MP131F STM32MP133A STM32MP133C STM32MP133D STM32MP133F STM32MP135A STM32MP135C STM32MP135D STM32MP135F OTP2 Data2 Data 0x0 0x20 R Status2 Status 0x4 0x20 R OTP3 Data3 Data 0x0 0x20 RW Status3 Status 0x4 0x20 R qspi_not_default_af 0:QSPI uses default hard coded AFmux 1:QSPI no default AFmux 0x0 0x1 RW emmc_if_id 0:Source is default SDMMC2 1:SDMMC1 2: SDMMC2 0x1 0x2 RW sd_if_id 0:Source is default SDMMC1 1:SDMMC1 2:SDMMC2 0x4 0x2 RW no_cpu_pll 0:PLLs for CPU/AXI are enable 1:PLLs for CPU/AXI are disable 0x5 0x1 RW no_usb_dp_pullup 0:USB DP pull-up is set 1: USB DP pull-up is not set 0x6 0x1 RW uart_instances_disabled Disable instance 0x1: Reserved 0x2: USART2 0x4: USART3 0x8: USART4 0x10: USART5 0x20: USART6 0x40: USART7 0x80: USART8 0x7 0x8 RW no_data_cache 0:Data cache is used by bootrom 1:Data cache is not used by bootrom 0xF 0x1 RW boot_source_disable Disable boot source 0x1: FMC 0x2: QSPI NOR 0x4: eMMC 0x8: SD 0x10: UART 0x20: USB 0x40: QSPI NAND 0x17 0x8 RW second_boot_source 0:NOT defined 1:FMC NAND 2:QSPI NOR 3:eMMC 4:SD 5:QSPI NAND 0x18 0x3 RW primary_boot_source 0:NOT defined 1:FMC NAND 2:QSPI NOR 3:eMMC 4:SD 5:QSPI NAND 0x1B 0x3 RW HSE value 0: HSE is autodetected 1: 24 MHz 2: 25 MHz 3: 26 MHz 0x1E 0x2 RW OTP4 Data4 Data 0x0 0x20 RW Status4 Status 0x4 0x20 R OTP5 Data5 Data 0x0 0x20 RW Status5 Status 0x4 0x20 R mode0 0x0 0x4 RW afmux0 AF mux value between 0 and 15 0x4 0x4 RW pin0 pin id between 0 and 15 for GPIOA to GPIOJ and between 0 and 7 for GPIOK and GPIOZ 0x8 0x4 RW port0 0: Unused 1: Bank A 2: Bank B 3: Bank C 4: Bank D 5: Bank E 6: Bank F 7: Bank G 8: Bank H 9: Bank I 10-15: Unused 0xC 0x4 RW mode1 idem CFG5 mode0 0x10 0x4 RW afmux1 idem CFG5 afmux0 0x14 0x4 RW pin1 idem CFG5 pin0 0x18 0x4 RW port1 idem CFG5 port0 0x1C 0x4 RW OTP6 Data6 Data 0x0 0x20 RW Status6 Status 0x4 0x20 R mode2 idem CFG5 port0 0x0 0x4 RW afmux2 idem CFG5 port0 0x4 0x4 RW pin2 idem CFG5 port0 0x8 0x4 RW port2 idem CFG5 port0 0xC 0x4 RW mode3 idem CFG5 port0 0x10 0x4 RW afmux3 idem CFG5 port0 0x14 0x4 RW pin3 idem CFG5 port0 0x18 0x4 RW port3 idem CFG5 port0 0x1C 0x4 RW OTP7 Data7 Data 0x0 0x20 RW Status7 Status 0x4 0x20 R mode4 idem CFG5 port0 0x0 0x4 RW afmux4 idem CFG5 port0 0x4 0x4 RW pin4 idem CFG5 port0 0x8 0x4 RW port4 idem CFG5 port0 0xC 0x4 RW mode5 idem CFG5 port0 0x10 0x4 RW afmux5 idem CFG5 port0 0x14 0x4 RW pin5 idem CFG5 port0 0x18 0x4 RW port5 idem CFG5 port0 0x1C 0x4 RW OTP8 Data8 Data 0x0 0x20 R Status8 Status 0x4 0x20 R OTP9 Data9 Data 0x0 0x20 RW Status9 Status 0x4 0x20 R boot_traces_disabled 0: No 1: Yes 0x0 0x1 RW hse_frequency_autodetection_disable 0: No 1: Yes 0x1 0x1 RW hse_bypass_detection_disable 0: No 1: Yes 0x2 0x1 RW emmc_128k_boot_partition 0: No 1: Yes 0x4 0x1 RW ssp_req 0x5 0x1 RW ssp_success 0x6 0x1 RW fsbl_decrypt_prio 0: Use CRYP 1: Use SAES 0x7 0x1 RW spinand_need_plane_select 0:SPI NAND plane select not need 1:SPI NAND plane select is needed 0xE 0x1 RW nand_number_of_ecc_bits 0xF 0x3 RW nand_bus_width 0:8 bit 1:16 bit 0x12 0x1 RW nand_nb_of_blocks Number of blocks in unit of 256 blocks 0x13 0x8 RW nand_block_size 0:64 pages per block 1:128 pages per block 2:256 pages per block 0x1B 0x2 RW nand_page_size 0:2 Kbytes 1:4 Kbytes 2:8 Kbytes 0x1D 0x2 RW nand_param_stored_in_otp 0:No 1:Nand parameters bits 15 to 30 are used 0x1F 0x1 RW OTP10 Data10 Data 0x0 0x20 RW Status10 Status 0x4 0x20 R OTP11 Data11 Data 0x0 0x20 RW Status11 Status 0x4 0x20 R OTP12 Data12 Data 0x0 0x20 R Status12 Status 0x4 0x20 R OTP13 Data13 Data 0x0 0x20 R Status13 Status 0x4 0x20 R OTP14 Data14 Data 0x0 0x20 R Status14 Status 0x4 0x20 R OTP15 Data15 Data 0x0 0x20 R Status15 Status 0x4 0x20 R OTP16 Data16 Data 0x0 0x20 R Status16 Status 0x4 0x20 R I/O compensation trim Used for I/O calibration 0x6 0x4 RW 1V8 reference trim 1V8 Regulator Trim 0xC 0x4 RW LSI trim 0x10 0x6 RW 1V1 reference trim 1V1 Regulator Trim 0x16 0x5 RW OTP17 Data17 Data 0x0 0x20 R Status17 Status 0x4 0x20 R CSITRIM CSI Trim 0x0 0x8 RW HSITRIM HSI Trim 0x8 0xC RW TEMPHTRIM High temperature threshold trimming 0x14 0x4 RW TEMPLTRIM Low temperature threshold trimming 0x18 0x4 RW VBATHTRIM High VBAT threshold trimming 0x1C 0x4 RW OTP18 Data18 Data 0x0 0x20 RW Status18 Status 0x4 0x20 R IWDG1_HW IWDG1 start 0:Start by software 1:Auto start 0x3 0x1 RW IWDG2_HW IWDG2 start 0:Start by software 1:Auto start 0x4 0x1 RW IWDG1_FZ_STOP IWDG1 freeze in Stop 0:No 1:Yes 0x5 0x1 RW IWDG2_FZ_STOP IWDG2 freeze in Stop 0:No 1:Yes 0x6 0x1 RW IWDG1_FZ_STANDBY IWDG1 freeze in Standby 0:No 1:Yes 0x7 0x1 RW IWDG2_FZ_STANDBY IWDG2 freeze in Standby 0:No 1:Yes 0x8 0x1 RW RNG_BYPASS_DISABLE RNG noise observation 0:Enable 1:Disable 0x9 0x1 RW SELINBORH 00: BOR Disabled 01: BOR = 2.1V 10: BOR = 2.4V 11: BOR = 2.7V 0xB 0x2 RW PRODUCT_BELOW_2V5 Required when VDD is below 2.5 V to allow the SYSCFG high speed lowvoltage enable registers HSLVEN bits to be taken into account. 0xD 0x1 RW OTP19 Data19 Data 0x0 0x20 R Status19 Status 0x4 0x20 R TS1_FMT0 DTS frequency measured freq at T0 0x0 0x10 RW TS1_RAMP_COEF DTS ramp coefficient 0x10 0x10 RW OTP20 Data20 Data 0x0 0x20 R Status20 Status 0x4 0x20 R TRIM_DTP_R DTS R Trim 0x0 0x7 RW TS1_T0 DTS T0 value 0x7 0x2 RW VREFINT_CAL ADC VBG measurement to correct for VREF 0x10 0x10 RW OTP21 Data21 Data 0x0 0x20 R Status21 Status 0x4 0x20 R VREFBUFTRIM 6 trim bits for each of 4 VREFBUF settings 0x0 0x18 RW SD1COMPCELL VDDSD1 I/O calibration 0x18 0x4 RW SD2COMPCELL VDDSD2 I/O calibration 0x1c 0x4 RW OTP22 Data22 Data 0x0 0x20 R Status24 Status 0x4 0x20 R OTP23 Data23 Data 0x0 0x20 R Status24 Status 0x4 0x20 R TS_CAL1 ADC TEMP measurement at T0 0x0 0x10 RW TS_CAL2 ADC TEMP measurement at T1 0x10 0x10 RW OTP24 Data24 Data 0x0 0x20 RW Status24 Status 0x4 0x20 R OTP25 Data25 Data 0x0 0x20 RW Status25 Status 0x4 0x20 R OTP26 Data26 Data 0x0 0x20 RW Status26 Status 0x4 0x20 R OTP27 Data27 Data 0x0 0x20 RW Status27 Status 0x4 0x20 R OTP28 Data28 Data 0x0 0x20 RW Status28 Status 0x4 0x20 R OTP29 Data29 Data 0x0 0x20 RW Status29 Status 0x4 0x20 R OTP30 Data30 Data 0x0 0x20 RW Status30 Status 0x4 0x20 R OTP31 Data31 Data 0x0 0x20 RW Status31 Status 0x4 0x20 R OTP32 Data32 Data 0x0 0x20 R Status32 Status 0x4 0x20 R OTP33 Data33 Data 0x0 0x20 R Status33 Status 0x4 0x20 R OTP34 Data34 Data 0x0 0x20 R Status34 Status 0x4 0x20 R OTP35 Data Data35 0x0 0x20 R Status35 Status 0x4 0x20 R OTP36 Data36 Data 0x0 0x20 R Status36 Status 0x4 0x20 R OTP37 Data37 Data 0x0 0x20 R Status37 Status 0x4 0x20 R OTP38 Data38 Data 0x0 0x20 R Status38 Status 0x4 0x20 R OTP39 Data39 Data 0x0 0x20 R Status39 Status 0x4 0x20 R OTP40 Data40 Data 0x0 0x20 R Status40 Status 0x4 0x20 R OTP41 Data41 Data 0x0 0x20 R Status41 Status 0x4 0x20 R OTP42 Data42 Data 0x0 0x20 R Status42 Status 0x4 0x20 R OTP43 Data43 Data 0x0 0x20 R Status43 Status 0x4 0x20 R OTP44 Data44 Data 0x0 0x20 R Status44 Status 0x4 0x20 R OTP45 Data45 Data 0x0 0x20 R Status45 Status 0x4 0x20 R OTP46 Data46 Data 0x0 0x20 R Status46 Status 0x4 0x20 R OTP47 Data47 Data 0x0 0x20 R Status47 Status 0x4 0x20 R OTP48 Data48 Data 0x0 0x20 R Status48 Status 0x4 0x20 R OTP49 Data49 Data 0x0 0x20 R Status49 Status 0x4 0x20 R OTP50 Data50 Data 0x0 0x20 R Status50 Status 0x4 0x20 R OTP51 Data51 Data 0x0 0x20 R Status51 Status 0x4 0x20 R OTP52 Data52 Data 0x0 0x20 R Status52 Status 0x4 0x20 R OTP53 Data53 Data 0x0 0x20 R Status53 Status 0x4 0x20 R OTP54 Data54 Data 0x0 0x20 R Status54 Status 0x4 0x20 R OTP55 Data55 Data 0x0 0x20 R Status55 Status 0x4 0x20 R OTP56 Data56 Data 0x0 0x20 RW Status56 Status 0x4 0x20 R OTP57 Data57 Data 0x0 0x20 RW Status57 Status 0x4 0x20 R OTP58 Data58 Data 0x0 0x20 RW Status58 Status 0x4 0x20 R OTP59 Data59 Data 0x0 0x20 RW Status59 Status 0x4 0x20 R OTP60 Data60 Data 0x0 0x20 RW Status60 Status 0x4 0x20 R OTP61 Data61 Data 0x0 0x20 RW Status61 Status 0x4 0x20 R OTP62 Data62 Data 0x0 0x20 RW Status62 Status 0x4 0x20 R OTP63 Data63 Data 0x0 0x20 RW Status63 Status 0x4 0x20 R OTP64 Data64 Data 0x0 0x20 RW Status64 Status 0x4 0x20 R OTP65 Data65 Data 0x0 0x20 RW Status65 Status 0x4 0x20 R OTP66 Data66 Data 0x0 0x20 RW Status66 Status 0x4 0x20 R OTP67 Data67 Data 0x0 0x20 RW Status67 Status 0x4 0x20 R OTP68 Data68 Data 0x0 0x20 RW Status68 Status 0x4 0x20 R OTP69 Data69 Data 0x0 0x20 RW Status69 Status 0x4 0x20 R OTP70 Data70 Data 0x0 0x20 RW Status70 Status 0x4 0x20 R OTP71 Data71 Data 0x0 0x20 RW Status71 Status 0x4 0x20 R OTP72 Data72 Data 0x0 0x20 RW Status72 Status 0x4 0x20 R OTP73 Data73 Data 0x0 0x20 RW Status73 Status 0x4 0x20 R OTP74 Data74 Data 0x0 0x20 RW Status74 Status 0x4 0x20 R OTP75 Data75 Data 0x0 0x20 RW Status75 Status 0x4 0x20 R OTP76 Data76 Data 0x0 0x20 RW Status76 Status 0x4 0x20 R OTP77 Data77 Data 0x0 0x20 RW Status77 Status 0x4 0x20 R OTP78 Data78 Data 0x0 0x20 RW Status78 Status 0x4 0x20 R OTP79 Data79 Data 0x0 0x20 RW Status79 Status 0x4 0x20 R OTP80 Data80 Data 0x0 0x20 RW Status80 Status 0x4 0x20 R OTP81 Data81 Data 0x0 0x20 RW Status81 Status 0x4 0x20 R OTP82 Data82 Data 0x0 0x20 RW Status82 Status 0x4 0x20 R OTP83 Data83 Data 0x0 0x20 RW Status83 Status 0x4 0x20 R OTP84 Data84 Data 0x0 0x20 RW Status84 Status 0x4 0x20 R OTP85 Data85 Data 0x0 0x20 RW Status85 Status 0x4 0x20 R OTP86 Data86 Data 0x0 0x20 RW Status86 Status 0x4 0x20 R OTP87 Data87 Data 0x0 0x20 RW Status87 Status 0x4 0x20 R OTP88 Data88 Data 0x0 0x20 RW Status88 Status 0x4 0x20 R OTP89 Data89 Data 0x0 0x20 RW Status89 Status 0x4 0x20 R OTP90 Data90 Data 0x0 0x20 RW Status90 Status 0x4 0x20 R OTP91 Data91 Data 0x0 0x20 RW Status91 Status 0x4 0x20 R OTP92 Data92 Data 0x0 0x20 RW Status92 Status 0x4 0x20 R OTP93 Data93 Data 0x0 0x20 RW Status93 Status 0x4 0x20 R OTP94 Data94 Data 0x0 0x20 RW Status94 Status 0x4 0x20 R OTP95 Data95 Data 0x0 0x20 RW Status95 Status 0x4 0x20 R