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562 lines
21 KiB
C
562 lines
21 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* HM01B0 driver.
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*/
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#include "omv_boardconfig.h"
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#if (OMV_HM01B0_ENABLE == 1)
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "py/mphal.h"
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#include "omv_i2c.h"
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#include "omv_csi.h"
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#include "hm01b0.h"
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#define HIMAX_BOOT_RETRY (10)
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#define HIMAX_LINE_LEN_PCK_FULL 0x178
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#define HIMAX_FRAME_LENGTH_FULL 0x109
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#define HIMAX_LINE_LEN_PCK_QVGA 0x178
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#define HIMAX_FRAME_LENGTH_QVGA 0x104
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#define HIMAX_LINE_LEN_PCK_QQVGA 0x178
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#define HIMAX_FRAME_LENGTH_QQVGA 0x084
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static const uint16_t default_regs[][2] = {
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{BLC_TGT, 0x08}, // BLC target :8 at 8 bit mode
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{BLC2_TGT, 0x08}, // BLI target :8 at 8 bit mode
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{0x3044, 0x0A}, // Increase CDS time for settling
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{0x3045, 0x00}, // Make symmetric for cds_tg and rst_tg
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{0x3047, 0x0A}, // Increase CDS time for settling
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{0x3050, 0xC0}, // Make negative offset up to 4x
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{0x3051, 0x42},
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{0x3052, 0x50},
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{0x3053, 0x00},
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{0x3054, 0x03}, // tuning sf sig clamping as lowest
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{0x3055, 0xF7}, // tuning dsun
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{0x3056, 0xF8}, // increase adc nonoverlap clk
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{0x3057, 0x29}, // increase adc pwr for missing code
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{0x3058, 0x1F}, // turn on dsun
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{0x3059, 0x1E},
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{0x3064, 0x00},
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{0x3065, 0x04}, // pad pull 0
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{ANA_Register_17, 0x00}, // Disable internal oscillator
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{BLC_CFG, 0x43}, // BLC_on, IIR
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{0x1001, 0x43}, // BLC dithering en
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{0x1002, 0x43}, // blc_darkpixel_thd
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{0x0350, 0x7F}, // Dgain Control
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{BLI_EN, 0x01}, // BLI enable
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{0x1003, 0x00}, // BLI Target [Def: 0x20]
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{DPC_CTRL, 0x01}, // DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2
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{0x1009, 0xA0}, // cluster hot pixel th
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{0x100A, 0x60}, // cluster cold pixel th
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{SINGLE_THR_HOT, 0x90}, // single hot pixel th
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{SINGLE_THR_COLD, 0x40}, // single cold pixel th
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{0x1012, 0x00}, // Sync. shift disable
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{STATISTIC_CTRL, 0x07}, // AE stat en | MD LROI stat en | magic
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{0x2003, 0x00},
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{0x2004, 0x1C},
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{0x2007, 0x00},
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{0x2008, 0x58},
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{0x200B, 0x00},
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{0x200C, 0x7A},
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{0x200F, 0x00},
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{0x2010, 0xB8},
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{0x2013, 0x00},
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{0x2014, 0x58},
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{0x2017, 0x00},
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{0x2018, 0x9B},
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{AE_CTRL, 0x01}, //Automatic Exposure
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{AE_TARGET_MEAN, 0x64}, //AE target mean [Def: 0x3C]
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{AE_MIN_MEAN, 0x0A}, //AE min target mean [Def: 0x0A]
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{CONVERGE_IN_TH, 0x03}, //Converge in threshold [Def: 0x03]
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{CONVERGE_OUT_TH, 0x05}, //Converge out threshold [Def: 0x05]
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{MAX_INTG_H, (HIMAX_FRAME_LENGTH_QVGA - 2) >> 8}, //Maximum INTG High Byte [Def: 0x01]
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{MAX_INTG_L, (HIMAX_FRAME_LENGTH_QVGA - 2) & 0xFF}, //Maximum INTG Low Byte [Def: 0x54]
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{MAX_AGAIN_FULL, 0x04}, //Maximum Analog gain in full frame mode [Def: 0x03]
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{MAX_AGAIN_BIN2, 0x04}, //Maximum Analog gain in bin2 mode [Def: 0x04]
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{MAX_DGAIN, 0xC0},
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{INTEGRATION_H, 0x01}, //Integration H [Def: 0x01]
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{INTEGRATION_L, 0x08}, //Integration L [Def: 0x08]
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{ANALOG_GAIN, 0x00}, //Analog Global Gain [Def: 0x00]
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{DAMPING_FACTOR, 0x20}, //Damping Factor [Def: 0x20]
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{DIGITAL_GAIN_H, 0x01}, //Digital Gain High [Def: 0x01]
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{DIGITAL_GAIN_L, 0x00}, //Digital Gain Low [Def: 0x00]
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{FS_CTRL, 0x00}, //Flicker Control
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{FS_60HZ_H, 0x00},
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{FS_60HZ_L, 0x3C},
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{FS_50HZ_H, 0x00},
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{FS_50HZ_L, 0x32},
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{MD_CTRL, 0x00},
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{FRAME_LEN_LINES_H, HIMAX_FRAME_LENGTH_QVGA >> 8},
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{FRAME_LEN_LINES_L, HIMAX_FRAME_LENGTH_QVGA & 0xFF},
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{LINE_LEN_PCK_H, HIMAX_LINE_LEN_PCK_QVGA >> 8},
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{LINE_LEN_PCK_L, HIMAX_LINE_LEN_PCK_QVGA & 0xFF},
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{QVGA_WIN_EN, 0x01}, // Enable QVGA window readout
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{0x0383, 0x01},
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{0x0387, 0x01},
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{0x0390, 0x00},
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{0x3011, 0x70},
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{0x3059, 0x02},
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{OSC_CLK_DIV, 0x0B},
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{IMG_ORIENTATION, 0x00}, // change the orientation
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{0x0104, 0x01},
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//============= End of regs marker ==================
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{0x0000, 0x00},
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};
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static int reset(omv_csi_t *csi) {
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// Reset csi.
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uint8_t reg = 0xff;
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for (int retry = HIMAX_BOOT_RETRY; retry >= 0 && reg != HIMAX_MODE_STANDBY; retry--) {
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if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, SW_RESET, HIMAX_RESET) != 0) {
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return -1;
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}
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mp_hal_delay_ms(1);
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if (omv_i2c_readb2(csi->i2c, csi->slv_addr, MODE_SELECT, ®) != 0) {
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return -1;
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}
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if (reg == HIMAX_MODE_STANDBY) {
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break;
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} else if (retry == 0) {
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return -1;
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}
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mp_hal_delay_ms(10);
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}
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// Write default registers
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int ret = 0;
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for (int i = 0; default_regs[i][0] && ret == 0; i++) {
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
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}
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// Set PCLK polarity.
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, PCLK_POLARITY, (0x20 | PCLK_FALLING_EDGE));
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// Set mode to streaming
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MODE_SELECT, HIMAX_MODE_STREAMING);
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return ret;
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}
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static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
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uint8_t reg_data;
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if (omv_i2c_readb2(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
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return -1;
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}
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return reg_data;
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}
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static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
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return omv_i2c_writeb2(csi->i2c, csi->slv_addr, reg_addr, reg_data);
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}
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static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
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int ret = 0;
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switch (pixformat) {
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case PIXFORMAT_BAYER:
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case PIXFORMAT_GRAYSCALE:
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break;
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default:
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return -1;
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}
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return ret;
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}
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static const uint16_t FULL_regs[][2] = {
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{0x0383, 0x01},
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{0x0387, 0x01},
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{0x0390, 0x00},
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{QVGA_WIN_EN, 0x00},// Disable QVGA window readout
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{MAX_INTG_H, (HIMAX_FRAME_LENGTH_FULL - 2) >> 8},
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{MAX_INTG_L, (HIMAX_FRAME_LENGTH_FULL - 2) & 0xFF},
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{FRAME_LEN_LINES_H, (HIMAX_FRAME_LENGTH_FULL >> 8)},
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{FRAME_LEN_LINES_L, (HIMAX_FRAME_LENGTH_FULL & 0xFF)},
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{LINE_LEN_PCK_H, (HIMAX_LINE_LEN_PCK_FULL >> 8)},
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{LINE_LEN_PCK_L, (HIMAX_LINE_LEN_PCK_FULL & 0xFF)},
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{GRP_PARAM_HOLD, 0x01},
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//============= End of regs marker ==================
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{0x0000, 0x00},
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};
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static const uint16_t QVGA_regs[][2] = {
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{0x0383, 0x01},
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{0x0387, 0x01},
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{0x0390, 0x00},
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{QVGA_WIN_EN, 0x01},// Enable QVGA window readout
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{MAX_INTG_H, (HIMAX_FRAME_LENGTH_QVGA - 2) >> 8},
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{MAX_INTG_L, (HIMAX_FRAME_LENGTH_QVGA - 2) & 0xFF},
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{FRAME_LEN_LINES_H, (HIMAX_FRAME_LENGTH_QVGA >> 8)},
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{FRAME_LEN_LINES_L, (HIMAX_FRAME_LENGTH_QVGA & 0xFF)},
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{LINE_LEN_PCK_H, (HIMAX_LINE_LEN_PCK_QVGA >> 8)},
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{LINE_LEN_PCK_L, (HIMAX_LINE_LEN_PCK_QVGA & 0xFF)},
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{GRP_PARAM_HOLD, 0x01},
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//============= End of regs marker ==================
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{0x0000, 0x00},
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};
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static const uint16_t QQVGA_regs[][2] = {
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{0x0383, 0x03},
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{0x0387, 0x03},
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{0x0390, 0x03},
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{QVGA_WIN_EN, 0x01},// Enable QVGA window readout
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{MAX_INTG_H, (HIMAX_FRAME_LENGTH_QQVGA - 2) >> 8},
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{MAX_INTG_L, (HIMAX_FRAME_LENGTH_QQVGA - 2) & 0xFF},
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{FRAME_LEN_LINES_H, (HIMAX_FRAME_LENGTH_QQVGA >> 8)},
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{FRAME_LEN_LINES_L, (HIMAX_FRAME_LENGTH_QQVGA & 0xFF)},
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{LINE_LEN_PCK_H, (HIMAX_LINE_LEN_PCK_QQVGA >> 8)},
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{LINE_LEN_PCK_L, (HIMAX_LINE_LEN_PCK_QQVGA & 0xFF)},
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{GRP_PARAM_HOLD, 0x01},
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//============= End of regs marker ==================
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{0x0000, 0x00},
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};
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static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
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int ret = 0;
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uint16_t w = csi->resolution[framesize][0];
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uint16_t h = csi->resolution[framesize][1];
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switch (framesize) {
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case OMV_CSI_FRAMESIZE_QVGA:
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for (int i = 0; QVGA_regs[i][0] && ret == 0; i++) {
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, QVGA_regs[i][0], QVGA_regs[i][1]);
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}
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break;
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case OMV_CSI_FRAMESIZE_QQVGA:
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for (int i = 0; QQVGA_regs[i][0] && ret == 0; i++) {
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, QQVGA_regs[i][0], QQVGA_regs[i][1]);
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}
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break;
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case OMV_CSI_FRAMESIZE_CUSTOM:
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case OMV_CSI_FRAMESIZE_320X320:
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if (w != 320 || h != 320) {
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ret = -1;
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break;
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}
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for (int i = 0; FULL_regs[i][0] && ret == 0; i++) {
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FULL_regs[i][0], FULL_regs[i][1]);
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}
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break;
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default:
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ret = -1;
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}
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return ret;
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}
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static int set_framerate(omv_csi_t *csi, int framerate) {
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uint8_t osc_div = 0;
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bool highres = false;
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if (csi->framesize == OMV_CSI_FRAMESIZE_INVALID
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|| csi->framesize == OMV_CSI_FRAMESIZE_QVGA
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|| csi->framesize == OMV_CSI_FRAMESIZE_320X320) {
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highres = true;
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}
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if (framerate <= 15) {
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osc_div = (highres == true) ? 0x01 : 0x00;
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} else if (framerate <= 30) {
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osc_div = (highres == true) ? 0x02 : 0x01;
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} else if (framerate <= 60) {
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osc_div = (highres == true) ? 0x03 : 0x02;
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} else {
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osc_div = 0x03; // Set to the max possible FPS at this resolution.
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}
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return omv_i2c_writeb2(csi->i2c, csi->slv_addr, OSC_CLK_DIV, 0x08 | osc_div);
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}
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static int set_brightness(omv_csi_t *csi, int level) {
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uint8_t ae_mean;
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// Simulate brightness levels by setting AE loop target mean.
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switch (level) {
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case 0:
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ae_mean = 60;
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break;
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case 1:
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ae_mean = 80;
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break;
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case 2:
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ae_mean = 100;
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break;
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case 3:
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ae_mean = 127;
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break;
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default:
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ae_mean = 60;
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}
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return omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_TARGET_MEAN, ae_mean);
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}
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static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
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int ret = 0;
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int gain = 0x0;
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switch (gainceiling) {
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case OMV_CSI_GAINCEILING_2X:
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gain = 0x01;
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break;
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case OMV_CSI_GAINCEILING_4X:
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gain = 0x02;
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break;
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case OMV_CSI_GAINCEILING_8X:
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gain = 0x03;
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break;
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case OMV_CSI_GAINCEILING_16X:
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gain = 0x04;
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break;
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default:
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return -1;
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}
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_FULL, gain);
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_BIN2, gain);
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return ret;
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}
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static int set_colorbar(omv_csi_t *csi, int enable) {
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return omv_i2c_writeb2(csi->i2c, csi->slv_addr, TEST_PATTERN_MODE, enable & 0x1);
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}
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static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
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int ret = 0;
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if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
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gain_db = IM_CLAMP(gain_db, 0.0f, 24.0f);
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int gain = fast_ceilf(logf(expf((gain_db / 20.0f) * M_LN10)) / M_LN2);
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 0); // Must disable AE
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ANALOG_GAIN, ((gain & 0x7) << 4));
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
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} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
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gain_db_ceiling = IM_CLAMP(gain_db_ceiling, 0.0f, 24.0f);
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int gain = fast_ceilf(logf(expf((gain_db_ceiling / 20.0f) * M_LN10) / M_LN2));
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_FULL, (gain & 0x7));
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_BIN2, (gain & 0x7));
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ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 1);
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}
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return ret;
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}
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static int get_gain_db(omv_csi_t *csi, float *gain_db) {
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uint8_t gain;
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if (omv_i2c_readb2(csi->i2c, csi->slv_addr, ANALOG_GAIN, &gain) != 0) {
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return -1;
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}
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*gain_db = fast_floorf(log10f(1 << (gain >> 4)) * 20.0f);
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return 0;
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}
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static int get_vt_pix_clk(omv_csi_t *csi, uint32_t *vt_pix_clk) {
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uint8_t reg;
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if (omv_i2c_readb2(csi->i2c, csi->slv_addr, OSC_CLK_DIV, ®) != 0) {
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return -1;
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}
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// 00 -> MCLK / 8
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// 01 -> MCLK / 4
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// 10 -> MCLK / 2
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// 11 -> MCLK / 1
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uint32_t vt_sys_div = 8 / (1 << (reg & 0x03));
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// vt_pix_clk = MCLK / vt_sys_div
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*vt_pix_clk = OMV_CSI_CLK_FREQUENCY / vt_sys_div;
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|
return 0;
|
|
}
|
|
|
|
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
|
int ret = 0;
|
|
|
|
if (enable) {
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 1);
|
|
} else {
|
|
uint32_t line_len;
|
|
uint32_t frame_len;
|
|
uint32_t coarse_int;
|
|
uint32_t vt_pix_clk = 0;
|
|
|
|
switch (csi->framesize) {
|
|
case OMV_CSI_FRAMESIZE_320X320:
|
|
line_len = HIMAX_LINE_LEN_PCK_FULL;
|
|
frame_len = HIMAX_FRAME_LENGTH_FULL;
|
|
break;
|
|
case OMV_CSI_FRAMESIZE_QVGA:
|
|
line_len = HIMAX_LINE_LEN_PCK_QVGA;
|
|
frame_len = HIMAX_FRAME_LENGTH_QVGA;
|
|
break;
|
|
case OMV_CSI_FRAMESIZE_QQVGA:
|
|
line_len = HIMAX_LINE_LEN_PCK_QQVGA;
|
|
frame_len = HIMAX_FRAME_LENGTH_QQVGA;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
ret |= get_vt_pix_clk(csi, &vt_pix_clk);
|
|
coarse_int = fast_roundf(exposure_us * (vt_pix_clk / 1000000.0f) / line_len);
|
|
|
|
if (coarse_int < 2) {
|
|
coarse_int = 2;
|
|
} else if (coarse_int > (frame_len - 2)) {
|
|
coarse_int = frame_len - 2;
|
|
}
|
|
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 0);
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, INTEGRATION_H, coarse_int >> 8);
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, INTEGRATION_L, coarse_int & 0xff);
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
|
int ret = 0;
|
|
uint32_t line_len;
|
|
uint32_t coarse_int = 0;
|
|
uint32_t vt_pix_clk = 0;
|
|
if (csi->framesize == OMV_CSI_FRAMESIZE_QVGA) {
|
|
line_len = HIMAX_LINE_LEN_PCK_QVGA;
|
|
} else {
|
|
line_len = HIMAX_LINE_LEN_PCK_QQVGA;
|
|
}
|
|
ret |= get_vt_pix_clk(csi, &vt_pix_clk);
|
|
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, INTEGRATION_H, &((uint8_t *) &coarse_int)[1]);
|
|
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, INTEGRATION_L, &((uint8_t *) &coarse_int)[0]);
|
|
*exposure_us = fast_roundf(coarse_int * line_len / (vt_pix_clk / 1000000.0f));
|
|
return ret;
|
|
}
|
|
|
|
static int set_hmirror(omv_csi_t *csi, int enable) {
|
|
uint8_t reg;
|
|
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, ®);
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_HMIRROR(reg, enable));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
|
return ret;
|
|
}
|
|
|
|
static int set_vflip(omv_csi_t *csi, int enable) {
|
|
uint8_t reg;
|
|
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, ®);
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_VMIRROR(reg, enable));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
|
return ret;
|
|
}
|
|
|
|
static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
|
int ret = 0;
|
|
|
|
switch (request) {
|
|
case OMV_CSI_IOCTL_HIMAX_OSC_ENABLE: {
|
|
uint32_t enable = va_arg(ap, uint32_t);
|
|
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, ANA_Register_17, enable ? 1:0);
|
|
mp_hal_delay_ms(100);
|
|
break;
|
|
}
|
|
|
|
case OMV_CSI_IOCTL_HIMAX_MD_ENABLE: {
|
|
uint32_t enable = va_arg(ap, uint32_t);
|
|
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_CTRL, enable ? 1:0);
|
|
break;
|
|
}
|
|
|
|
case OMV_CSI_IOCTL_HIMAX_MD_WINDOW: {
|
|
uint32_t x1 = va_arg(ap, uint32_t);
|
|
uint32_t y1 = va_arg(ap, uint32_t);
|
|
uint32_t x2 = va_arg(ap, uint32_t) + x1;
|
|
uint32_t y2 = va_arg(ap, uint32_t) + y1;
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_START_H, (x1 >> 8));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_START_L, (x1 & 0xff));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_START_H, (y1 >> 8));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_START_L, (y1 & 0xff));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_END_H, (x2 >> 8));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_END_L, (x2 & 0xff));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_END_H, (y2 >> 8));
|
|
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_END_L, (y2 & 0xff));
|
|
break;
|
|
}
|
|
|
|
case OMV_CSI_IOCTL_HIMAX_MD_THRESHOLD: {
|
|
uint32_t threshold = va_arg(ap, uint32_t);
|
|
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_THL, threshold);
|
|
break;
|
|
}
|
|
|
|
case OMV_CSI_IOCTL_HIMAX_MD_CLEAR: {
|
|
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, I2C_CLEAR, 1);
|
|
break;
|
|
}
|
|
|
|
default: {
|
|
ret = -1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int hm01b0_init(omv_csi_t *csi) {
|
|
// Initialize csi structure.
|
|
csi->reset = reset;
|
|
csi->read_reg = read_reg;
|
|
csi->write_reg = write_reg;
|
|
csi->set_pixformat = set_pixformat;
|
|
csi->set_framesize = set_framesize;
|
|
csi->set_framerate = set_framerate;
|
|
csi->set_brightness = set_brightness;
|
|
csi->set_gainceiling = set_gainceiling;
|
|
csi->set_colorbar = set_colorbar;
|
|
csi->set_auto_gain = set_auto_gain;
|
|
csi->get_gain_db = get_gain_db;
|
|
csi->set_auto_exposure = set_auto_exposure;
|
|
csi->get_exposure_us = get_exposure_us;
|
|
csi->set_hmirror = set_hmirror;
|
|
csi->set_vflip = set_vflip;
|
|
csi->ioctl = ioctl;
|
|
|
|
// Set csi flags
|
|
csi->vsync_pol = 0;
|
|
csi->hsync_pol = 0;
|
|
csi->pixck_pol = 0;
|
|
csi->frame_sync = 0;
|
|
csi->mono_bpp = 1;
|
|
|
|
return 0;
|
|
}
|
|
#endif //(OMV_HM01B0_ENABLE == 1)
|