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Old header files are no longer needed. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
477 lines
15 KiB
C
477 lines
15 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* OV7670 driver.
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*/
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#include "omv_boardconfig.h"
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#if (OMV_OV7670_ENABLE == 1)
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "omv_i2c.h"
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#include "omv_csi.h"
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#include "ov7670.h"
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#include "py/mphal.h"
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static const uint8_t default_regs[][2] = {
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// OV7670 reference registers
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#if (OMV_OV7670_CLKRC == 0)
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{ CLKRC, CLKRC_PRESCALER_BYPASS },
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#else
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{ CLKRC, OMV_OV7670_CLKRC },
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#endif
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{ TSLB, 0x04 },
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{ COM7, 0x00 },
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{ HSTART, 0x13 },
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{ HSTOP, 0x01 },
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{ HREF, 0xb6 },
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{ VSTART, 0x02 },
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{ VSTOP, 0x7a },
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{ VREF, 0x0a },
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{ COM3, 0x00 },
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{ COM14, 0x00 },
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{ SCALING_XSC, 0x3a },
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{ SCALING_YSC, 0x35 },
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{ SCALING_DCWCTR, 0x11 },
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{ SCALING_PCLK_DIV, 0xf0 },
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{ SCALING_PCLK, 0x02 },
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/* Gamma curve values */
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{ SLOP, 0x20 },
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{ GAM1, 0x10 },
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{ GAM2, 0x1e },
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{ GAM3, 0x35 },
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{ GAM4, 0x5a },
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{ GAM5, 0x69 },
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{ GAM6, 0x76 },
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{ GAM7, 0x80 },
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{ GAM8, 0x88 },
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{ GAM9, 0x8f },
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{ GAM10, 0x96 },
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{ GAM11, 0xa3 },
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{ GAM12, 0xaf },
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{ GAM13, 0xc4 },
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{ GAM14, 0xd7 },
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{ GAM15, 0xe8 },
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/* AGC and AEC parameters */
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{ COM8, COM8_FAST_AEC | COM8_AEC_STEP | COM8_BANDF_EN },
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{ GAIN, 0x00 },
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{ AECH, 0x00 },
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{ COM4, 0x40 },
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{ COM9, 0x18 },
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{ BD50MAX, 0x05 },
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{ BD60MAX, 0x07 },
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{ AEW, 0x95 },
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{ AEB, 0x33 },
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{ VPT, 0xe3 },
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{ HAECC1, 0x78 },
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{ HAECC2, 0x68 },
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{ 0xa1, 0x03 },
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{ HAECC3, 0xd8 },
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{ HAECC4, 0xd8 },
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{ HAECC5, 0xf0 },
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{ HAECC6, 0x90 },
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{ HAECC7, 0x94 },
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{ COM8, COM8_FAST_AEC | COM8_AEC_STEP | COM8_BANDF_EN | COM8_AGC_EN | COM8_AEC_EN },
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/* Almost all of these are magic "reserved" values. */
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{ COM5, 0x61 },
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{ COM6, 0x4b },
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{ 0x16, 0x02 },
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{ 0x21, 0x02 },
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{ 0x22, 0x91 },
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{ 0x29, 0x07 },
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{ 0x33, 0x0b },
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{ 0x35, 0x0b },
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{ 0x37, 0x1d },
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{ 0x38, 0x71 },
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{ 0x39, 0x2a },
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{ COM12, 0x78 },
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{ 0x4d, 0x40 },
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{ 0x4e, 0x20 },
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{ GFIX, 0x00 },
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{ 0x6b, 0x00 }, // PLL Bypass
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{ 0x74, 0x10 },
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{ 0x8d, 0x4f },
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{ 0x8e, 0x00 },
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{ 0x8f, 0x00 },
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{ 0x90, 0x00 },
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{ 0x91, 0x00 },
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{ 0x96, 0x00 },
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{ 0x9a, 0x00 },
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{ 0xb0, 0x84 },
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{ 0xb1, 0x0c },
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{ 0xb2, 0x0e },
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{ 0xb3, 0x82 },
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{ 0xb8, 0x0a },
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{ 0x43, 0x0a },
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{ 0x44, 0xf0 },
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{ 0x45, 0x34 },
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{ 0x46, 0x58 },
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{ 0x47, 0x28 },
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{ 0x48, 0x3a },
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{ 0x59, 0x88 },
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{ 0x5a, 0x88 },
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{ 0x5b, 0x44 },
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{ 0x5c, 0x67 },
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{ 0x5d, 0x49 },
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{ 0x5e, 0x0e },
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{ 0x6c, 0x0a },
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{ 0x6d, 0x55 },
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{ 0x6e, 0x11 },
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{ 0x6f, 0x9e },
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{ 0x6a, 0x40 },
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{ BLUE, 0x40 },
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{ RED, 0x60 },
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{ COM8, COM8_FAST_AEC | COM8_AEC_STEP | COM8_BANDF_EN | COM8_AGC_EN | COM8_AEC_EN | COM8_AWB_EN },
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/* Matrix coefficients */
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{ MTX1, 0x80 },
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{ MTX2, 0x80 },
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{ MTX3, 0x00 },
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{ MTX4, 0x22 },
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{ MTX5, 0x5e },
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{ MTX6, 0x80 },
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{ MTXS, 0x9e },
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{ COM16, COM16_AWB_GAIN_EN },
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{ EDGE, 0x00 },
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{ 0x75, 0x05 },
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{ 0x76, 0xe1 },
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{ 0x4c, 0x00 },
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{ 0x77, 0x01 },
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{ COM13, 0xc3 },
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{ 0x4b, 0x09 },
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{ 0xc9, 0x60 },
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{ COM16, 0x38 },
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{ 0x56, 0x40 },
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{ 0x34, 0x11 },
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{ COM11, COM11_AEC_BANDF | COM11_HZAUTO_EN },
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{ 0xa4, 0x88 },
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{ 0x96, 0x00 },
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{ 0x97, 0x30 },
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{ 0x98, 0x20 },
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{ 0x99, 0x30 },
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{ 0x9a, 0x84 },
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{ 0x9b, 0x29 },
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{ 0x9c, 0x03 },
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{ 0x9d, 0x4c },
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{ 0x9e, 0x3f },
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{ 0x78, 0x04 },
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{ 0x79, 0x01 },
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{ 0xc8, 0xf0 },
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{ 0x79, 0x0f },
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{ 0xc8, 0x00 },
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{ 0x79, 0x10 },
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{ 0xc8, 0x7e },
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{ 0x79, 0x0a },
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{ 0xc8, 0x80 },
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{ 0x79, 0x0b },
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{ 0xc8, 0x01 },
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{ 0x79, 0x0c },
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{ 0xc8, 0x0f },
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{ 0x79, 0x0d },
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{ 0xc8, 0x20 },
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{ 0x79, 0x09 },
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{ 0xc8, 0x80 },
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{ 0x79, 0x02 },
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{ 0xc8, 0xc0 },
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{ 0x79, 0x03 },
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{ 0xc8, 0x40 },
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{ 0x79, 0x05 },
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{ 0xc8, 0x30 },
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{ 0x79, 0x26 },
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{ 0xFF, 0xFF },
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};
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#if (OMV_OV7670_VERSION == 75)
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static const uint8_t rgb565_regs[][2] = {
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{ COM7, COM7_RGB_FMT }, /* Selects RGB mode */
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{ RGB444, 0x00 }, /* No RGB444 please */
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{ COM1, 0x00 }, /* CCIR601 */
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{ COM15, COM15_OUT_00_FF | COM15_FMT_RGB565},
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{ COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
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{ 0x4f, 0xb3 }, /* "matrix coefficient 1" */
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{ 0x50, 0xb3 }, /* "matrix coefficient 2" */
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{ 0x51, 0x00 }, /* "matrix Coefficient 3" */
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{ 0x52, 0x3d }, /* "matrix coefficient 4" */
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{ 0x53, 0xa7 }, /* "matrix coefficient 5" */
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{ 0x54, 0xe4 }, /* "matrix coefficient 6" */
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{ COM13, COM13_GAMMA_EN | COM13_UVSAT_AUTO },
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{ 0xFF, 0xFF }
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};
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#elif (OMV_OV7670_VERSION == 70)
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static const uint8_t rgb565_regs[][2] = {
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{ COM7, COM7_RGB_FMT }, /* Selects RGB mode */
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{ RGB444, 0 }, /* No RGB444 please */
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{ COM1, 0x0 }, /* CCIR601 */
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{ COM15, COM15_FMT_RGB565 | COM15_OUT_00_FF},
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{ COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
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{ MTX1, 0xb3 }, /* "matrix coefficient 1" */
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{ MTX2, 0xb3 }, /* "matrix coefficient 2" */
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{ MTX3, 0 }, /* vb */
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{ MTX4, 0x3d }, /* "matrix coefficient 4" */
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{ MTX5, 0xa7 }, /* "matrix coefficient 5" */
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{ MTX6, 0xe4 }, /* "matrix coefficient 6" */
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{ COM13, COM13_UVSAT_AUTO },
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{ 0xFF, 0xFF }
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};
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#else
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#error "OV767x variant is Not defined."
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#endif
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// TODO: These registers probably need to be fixed too.
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static const uint8_t yuv422_regs[][2] = {
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{ COM7, 0x00 }, /* Selects YUV mode */
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{ RGB444, 0x00 }, /* No RGB444 please */
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{ COM1, 0x00 }, /* CCIR601 */
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{ COM15, COM15_OUT_00_FF },
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{ COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
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{ 0x4f, 0x80 }, /* "matrix coefficient 1" */
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{ 0x50, 0x80 }, /* "matrix coefficient 2" */
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{ 0x51, 0x00 }, /* vb */
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{ 0x52, 0x22 }, /* "matrix coefficient 4" */
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{ 0x53, 0x5e }, /* "matrix coefficient 5" */
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{ 0x54, 0x80 }, /* "matrix coefficient 6" */
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{ COM13, COM13_GAMMA_EN | COM13_UVSAT_AUTO },
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{ 0xFF, 0xFF }
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};
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static const uint8_t vga_regs[][2] = {
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{ COM3, 0x00 },
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{ COM14, 0x00 },
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{ 0x72, 0x11 }, // downsample by 4
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{ 0x73, 0xf0 }, // divide by 4
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{ HSTART, 0x13 },
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{ HSTOP, 0x01 },
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{ HREF, 0xb6 },
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{ VSTART, 0x03 },
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{ VSTOP, 0x00 },
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{ VREF, 0x0a },
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{ 0xFF, 0xFF },
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};
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#if (OMV_OV7670_VERSION == 75)
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static const uint8_t qvga_regs[][2] = {
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{ COM3, COM3_DCW_EN },
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{ COM14, 0x11 }, // Divide by 2
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{ 0x72, 0x22 }, // This has no effect on OV7675
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{ 0x73, 0xf2 }, // This has no effect on OV7675
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{ HSTART, 0x15 },
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{ HSTOP, 0x03 },
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{ HREF, 0xC0 },
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{ VSTART, 0x03 },
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{ VSTOP, 0x7B },
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{ VREF, 0xF0 },
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{ 0xFF, 0xFF },
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};
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#else
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static const uint8_t qvga_regs[][2] = {
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{ COM3, COM3_DCW_EN },
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{ COM14, 0x19 },
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{ 0x72, 0x11 }, // downsample by 2
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{ 0x73, 0xf1 }, // divide by 2
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{ HSTART, 0x15 },
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{ HSTOP, 0x04 },
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{ HREF, 0xa4 },
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{ VSTART, 0x02 },
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{ VSTOP, 0x7a },
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{ VREF, 0x0a },
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{ 0XFF, 0XFF },
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};
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#endif
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#if (OMV_OV7670_VERSION == 75)
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static const uint8_t qqvga_regs[][2] = {
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{ COM3, COM3_DCW_EN },
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{ COM14, 0x11 }, // Divide by 2
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{ 0x72, 0x22 }, // This has no effect on OV7675
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{ 0x73, 0xf2 }, // This has no effect on OV7675
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{ HSTART, 0x16 },
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{ HSTOP, 0x04 },
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{ HREF, 0xa4 },
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{ VSTART, 0x22 },
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{ VSTOP, 0x7a },
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{ VREF, 0xfa },
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{ 0xFF, 0xFF },
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};
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#else
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static const uint8_t qqvga_regs[][2] = {
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{ COM3, COM3_DCW_EN },
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{ COM14, 0x1a},
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{ 0x72, 0x22 }, // downsample by 4
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{ 0x73, 0xf2 }, // divide by 4
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{ HSTART, 0x16 },
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{ HSTOP, 0x04 },
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{ HREF, 0xa4 },
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{ VSTART, 0x02 },
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{ VSTOP, 0x7a },
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{ VREF, 0x0a },
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{ 0XFF, 0XFF },
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};
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#endif
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static int reset(omv_csi_t *csi) {
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// Reset all registers
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int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, COM7_RESET);
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// Delay 2 ms
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mp_hal_delay_ms(2);
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// Write default registers
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for (int i = 0; default_regs[i][0] != 0xff; i++) {
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
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}
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// Delay 300 ms
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if (!csi->disable_delays) {
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mp_hal_delay_ms(300);
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}
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return ret;
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}
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static int sleep(omv_csi_t *csi, int enable) {
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uint8_t reg;
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int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM2, ®);
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if (enable) {
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reg |= COM2_SOFT_SLEEP;
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} else {
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reg &= ~COM2_SOFT_SLEEP;
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}
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// Write back register
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return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM2, reg) | ret;
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}
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static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
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uint8_t reg_data;
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if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
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return -1;
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}
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return reg_data;
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}
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static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
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return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg_addr, reg_data);
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}
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static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
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int ret = 0;
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const uint8_t(*regs)[2];
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switch (pixformat) {
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case PIXFORMAT_RGB565:
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regs = rgb565_regs;
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break;
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case PIXFORMAT_YUV422:
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case PIXFORMAT_GRAYSCALE:
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regs = yuv422_regs;
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break;
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default:
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return -1;
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}
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// Write pixel format registers
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for (int i = 0; regs[i][0] != 0xff; i++) {
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
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}
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return ret;
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}
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static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
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int ret = 0;
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const uint8_t(*regs)[2];
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switch (framesize) {
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case OMV_CSI_FRAMESIZE_VGA:
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regs = vga_regs;
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break;
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case OMV_CSI_FRAMESIZE_QVGA:
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regs = qvga_regs;
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break;
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case OMV_CSI_FRAMESIZE_QQVGA:
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regs = qqvga_regs;
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break;
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default:
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return -1;
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}
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// Write pixel format registers
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for (int i = 0; regs[i][0] != 0xFF; i++) {
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
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}
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return ret;
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}
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static int set_hmirror(omv_csi_t *csi, int enable) {
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uint8_t val;
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int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, MVFP, &val);
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ret |=
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omv_i2c_writeb(csi->i2c, csi->slv_addr, MVFP,
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enable ? (val | MVFP_MIRROR) : (val & (~MVFP_MIRROR)));
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return ret;
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}
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static int set_vflip(omv_csi_t *csi, int enable) {
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uint8_t val;
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int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, MVFP, &val);
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ret |=
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omv_i2c_writeb(csi->i2c, csi->slv_addr, MVFP,
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enable ? (val | MVFP_VFLIP) : (val & (~MVFP_VFLIP)));
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return ret;
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}
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int ov7670_init(omv_csi_t *csi) {
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// Initialize csi structure.
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csi->reset = reset;
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csi->sleep = sleep;
|
|
csi->read_reg = read_reg;
|
|
csi->write_reg = write_reg;
|
|
csi->set_pixformat = set_pixformat;
|
|
csi->set_framesize = set_framesize;
|
|
csi->set_hmirror = set_hmirror;
|
|
csi->set_vflip = set_vflip;
|
|
|
|
// Set csi flags
|
|
csi->vsync_pol = 1;
|
|
csi->hsync_pol = 0;
|
|
csi->pixck_pol = 1;
|
|
csi->frame_sync = 0;
|
|
csi->mono_bpp = 2;
|
|
csi->rgb_swap = 1;
|
|
csi->yuv_format = SUBFORMAT_ID_YVU422;
|
|
|
|
return 0;
|
|
}
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#endif // (OMV_OV7670_ENABLE == 1)
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