mirror of
https://github.com/openmv/openmv.git
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198 lines
6.2 KiB
C
198 lines
6.2 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2023 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* GPIO port for imxrt.
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*/
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#include <stdint.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "py/mphal.h"
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#include "fsl_gpio.h"
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#include "fsl_iomuxc.h"
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#include "mimxrt_hal.h"
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#include "omv_boardconfig.h"
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#include "omv_gpio.h"
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#include "omv_common.h"
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#define IOMUXC_SET_REG(base, reg, val) *((volatile uint32_t *) ((((uint32_t) base) << 16) | reg)) = (val)
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extern omv_gpio_irq_descr_t *const gpio_irq_descr_table[MIMXRT_PAD_COUNT];
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static uint32_t omv_gpio_irq_get_gpio(omv_gpio_t pin) {
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const imxrt_pad_t *pad = pin->pad;
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GPIO_Type *gpio_all[] = GPIO_BASE_PTRS;
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for (size_t i = 1; i < OMV_ARRAY_SIZE(gpio_all); i++) {
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if (pad->port == gpio_all[i]) {
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return i;
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}
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}
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return 0;
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}
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static uint32_t omv_gpio_irq_get_irqn(omv_gpio_t pin) {
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const imxrt_pad_t *pad = pin->pad;
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uint32_t gpio = omv_gpio_irq_get_gpio(pin);
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uint8_t low_irqs[] = GPIO_COMBINED_LOW_IRQS;
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uint8_t high_irqs[] = GPIO_COMBINED_HIGH_IRQS;
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return (pad->pin < 16) ? low_irqs[gpio] : high_irqs[gpio];
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}
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static omv_gpio_irq_descr_t *omv_gpio_irq_get_descr(omv_gpio_t pin) {
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const imxrt_pad_t *pad = pin->pad;
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uint32_t gpio = omv_gpio_irq_get_gpio(pin);
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if (gpio && gpio_irq_descr_table[gpio]) {
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return &gpio_irq_descr_table[gpio][pad->pin];
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}
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return NULL;
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}
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static const imxrt_pad_af_t *omv_gpio_find_af(omv_gpio_t pin, uint32_t af) {
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static const imxrt_pad_af_t af_gpio = {5, 0, 0};
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if (af == 5) {
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return &af_gpio;
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}
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const imxrt_pad_t *pad = pin->pad;
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for (size_t i = 0; i < pad->af_count; i++) {
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if (af == pad->af_list[i].idx) {
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return &pad->af_list[i];
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}
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}
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return NULL;
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}
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void omv_gpio_config(omv_gpio_t pin, uint32_t mode, uint32_t pull, uint32_t speed, uint32_t af) {
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const imxrt_pad_t *pad = pin->pad;
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af = ((af == -1) ? pin->af : af);
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const imxrt_pad_af_t *pad_af = omv_gpio_find_af(pin, af);
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if (pad_af == NULL) {
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return;
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}
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uint16_t pad_config = (mode | pull | speed) & 0x1FFFF;
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uint16_t mux_config = IOMUXC_MUX_CTL(MUX_MODE, af) | IOMUXC_MUX_CTL(SION, pin->sion);
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IOMUXC_SET_REG(pad->iomux_base, pad->mux_register, mux_config);
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if (pad_af->input_register) {
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// Input register always uses IOMUXC_BASE
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uint32_t iomux_base = ((uint32_t) IOMUXC_BASE) >> 16;
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IOMUXC_SET_REG(iomux_base, pad_af->input_register, pad_af->input_daisy);
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}
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IOMUXC_SET_REG(pad->iomux_base, pad->cfg_register, pad_config);
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// If pad was configured for GPIO module, set the pin config.
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gpio_pin_config_t pin_config = { 0 };
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switch (mode) {
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case OMV_GPIO_MODE_ALT:
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case OMV_GPIO_MODE_ALT_OD: {
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// No GPIO config.
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return;
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}
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case OMV_GPIO_MODE_INPUT: {
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pin_config.direction = kGPIO_DigitalInput;
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GPIO_PinInit(pad->port, pad->pin, &pin_config);
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break;
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}
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case OMV_GPIO_MODE_OUTPUT:
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case OMV_GPIO_MODE_OUTPUT_OD: {
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pin_config.direction = kGPIO_DigitalOutput;
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pin_config.outputLogic = 1;
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break;
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}
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case OMV_GPIO_MODE_IT_FALL: {
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pin_config.interruptMode = kGPIO_IntFallingEdge;
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break;
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}
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case OMV_GPIO_MODE_IT_RISE: {
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pin_config.interruptMode = kGPIO_IntRisingEdge;
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break;
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}
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case OMV_GPIO_MODE_IT_BOTH: {
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pin_config.interruptMode = kGPIO_IntRisingOrFallingEdge;
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break;
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}
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}
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GPIO_PinInit(pad->port, pad->pin, &pin_config);
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}
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void omv_gpio_deinit(omv_gpio_t pin) {
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}
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bool omv_gpio_read(omv_gpio_t pin) {
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const imxrt_pad_t *pad = pin->pad;
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return GPIO_PinRead(pad->port, pad->pin);
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}
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void omv_gpio_write(omv_gpio_t pin, bool value) {
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const imxrt_pad_t *pad = pin->pad;
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GPIO_PinWrite(pad->port, pad->pin, value);
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}
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void omv_gpio_irq_register(omv_gpio_t pin, omv_gpio_callback_t callback, void *data) {
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omv_gpio_irq_descr_t *irq_descr = omv_gpio_irq_get_descr(pin);
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if (irq_descr) {
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irq_descr->enabled = true;
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irq_descr->data = data;
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irq_descr->callback = callback;
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}
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}
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void omv_gpio_irq_enable(omv_gpio_t pin, bool enable) {
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const imxrt_pad_t *pad = pin->pad;
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uint32_t irqn = omv_gpio_irq_get_irqn(pin);
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omv_gpio_irq_descr_t *irq_descr = omv_gpio_irq_get_descr(pin);
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if (irq_descr == NULL) {
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return;
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}
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if (!enable) {
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GPIO_PortDisableInterrupts(pad->port, 1U << pad->pin);
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GPIO_PortClearInterruptFlags(pad->port, ~(0U));
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DisableIRQ(irqn);
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} else {
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GPIO_PortClearInterruptFlags(pad->port, ~(0U));
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GPIO_PortEnableInterrupts(pad->port, 1U << pad->pin);
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NVIC_SetPriority(irqn, IRQ_PRI_EXTINT);
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EnableIRQ(irqn);
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}
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irq_descr->enabled = enable;
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}
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void omv_gpio_irq_handler(GPIO_Type *gpio, uint32_t gpio_nr, uint32_t pin_nr) {
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omv_gpio_irq_descr_t *irq_descr = NULL;
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if (gpio_irq_descr_table[gpio_nr]) {
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irq_descr = &gpio_irq_descr_table[gpio_nr][pin_nr];
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if (irq_descr->enabled && irq_descr->callback) {
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irq_descr->callback(irq_descr->data);
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}
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}
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}
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