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71 lines
3.5 KiB
C
71 lines
3.5 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* AXI QoS Setup
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*/
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#ifndef __AXIQOS_H__
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#define __AXIQOS_H__
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#define OMV_AXI_GPV_BASE 0x51000000
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#define OMV_AXI_GPV_QOS_BASE ((OMV_AXI_GPV_BASE) +0x41100)
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#define OMV_AXI_GPV_QOS_R_BASE(x) ((OMV_AXI_GPV_QOS_BASE) +(0x1000 * (x)) + 0x0)
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#define OMV_AXI_GPV_QOS_W_BASE(x) ((OMV_AXI_GPV_QOS_BASE) +(0x1000 * (x)) + 0x4)
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#define OMV_AXI_QOS_D2_AHB_R_ADDRESS OMV_AXI_GPV_QOS_R_BASE(1)
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#define OMV_AXI_QOS_D2_AHB_R_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_D2_AHB_R_ADDRESS)) = (x)
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#define OMV_AXI_QOS_D2_AHB_W_ADDRESS OMV_AXI_GPV_QOS_W_BASE(1)
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#define OMV_AXI_QOS_D2_AHB_W_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_D2_AHB_W_ADDRESS)) = (x)
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#define OMV_AXI_QOS_C_M7_R_ADDRESS OMV_AXI_GPV_QOS_R_BASE(2)
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#define OMV_AXI_QOS_C_M7_R_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_C_M7_R_ADDRESS)) = (x)
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#define OMV_AXI_QOS_C_M7_W_ADDRESS OMV_AXI_GPV_QOS_W_BASE(2)
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#define OMV_AXI_QOS_C_M7_W_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_C_M7_W_ADDRESS)) = (x)
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#define OMV_AXI_QOS_SDMMC1_R_ADDRESS OMV_AXI_GPV_QOS_R_BASE(3)
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#define OMV_AXI_QOS_SDMMC1_R_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_SDMMC1_R_ADDRESS)) = (x)
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#define OMV_AXI_QOS_SDMMC1_W_ADDRESS OMV_AXI_GPV_QOS_W_BASE(3)
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#define OMV_AXI_QOS_SDMMC1_W_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_SDMMC1_W_ADDRESS)) = (x)
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#define OMV_AXI_QOS_MDMA_R_ADDRESS OMV_AXI_GPV_QOS_R_BASE(4)
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#define OMV_AXI_QOS_MDMA_R_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_MDMA_R_ADDRESS)) = (x)
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#define OMV_AXI_QOS_MDMA_W_ADDRESS OMV_AXI_GPV_QOS_W_BASE(4)
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#define OMV_AXI_QOS_MDMA_W_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_MDMA_W_ADDRESS)) = (x)
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#define OMV_AXI_QOS_DMA2D_R_ADDRESS OMV_AXI_GPV_QOS_R_BASE(5)
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#define OMV_AXI_QOS_DMA2D_R_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_DMA2D_R_ADDRESS)) = (x)
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#define OMV_AXI_QOS_DMA2D_W_ADDRESS OMV_AXI_GPV_QOS_W_BASE(5)
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#define OMV_AXI_QOS_DMA2D_W_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_DMA2D_W_ADDRESS)) = (x)
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#define OMV_AXI_QOS_LTDC_R_ADDRESS OMV_AXI_GPV_QOS_R_BASE(6)
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#define OMV_AXI_QOS_LTDC_R_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_LTDC_R_ADDRESS)) = (x)
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#define OMV_AXI_QOS_LTDC_W_ADDRESS OMV_AXI_GPV_QOS_W_BASE(6)
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#define OMV_AXI_QOS_LTDC_W_SET(x) *((volatile uint32_t *) (OMV_AXI_QOS_LTDC_W_ADDRESS)) = (x)
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#endif // __AXIQOS_H__
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