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https://github.com/openmv/openmv.git
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174 lines
4.4 KiB
C
174 lines
4.4 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* STM32 Nema HAL layer.
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*/
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#include <stdlib.h>
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#include STM32_HAL_H
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#include "omv_boardconfig.h"
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#if (OMV_GPU_NEMA == 1)
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#include "py/mphal.h"
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#include "irq.h"
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#include "omv_common.h"
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#include "nema_core.h"
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#include "nema_sys_defs.h"
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#ifndef OMV_GPU_NEMA_RING_SIZE
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#define OMV_GPU_NEMA_RING_SIZE 1024
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#endif
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volatile static int last_cl_id = -1;
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static GPU2D_HandleTypeDef gpu2d = { 0 };
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static nema_ringbuffer_t ring_buf = {{0}};
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#if OMV_GPU_NEMA_MM_STATIC
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uint8_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(RING_BUFFER[OMV_GPU_NEMA_RING_SIZE], 32), ".dma_buffer");
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#endif
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int32_t nema_sys_init(void) {
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// Initialize GPU2D
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gpu2d.Instance = GPU2D;
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HAL_GPU2D_Init(&gpu2d);
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// Configure and enable texture cache
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HAL_ICACHE_DeInit();
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HAL_ICACHE_Disable();
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HAL_ICACHE_WaitForInvalidateComplete();
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HAL_ICACHE_ConfigAssociativityMode(ICACHE_4WAYS);
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HAL_ICACHE_Enable();
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// Allocate ring buffer.
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#if OMV_GPU_NEMA_MM_STATIC
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ring_buf.bo.fd = 0;
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ring_buf.bo.size = sizeof(RING_BUFFER);
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ring_buf.bo.base_virt = RING_BUFFER;
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ring_buf.bo.base_phys = (uint32_t) RING_BUFFER;
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#else
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ring_buf.bo = nema_buffer_create(OMV_GPU_NEMA_RING_SIZE);
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#endif
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// Initialize ring buffer.
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if (nema_rb_init(&ring_buf, 1) != 0) {
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return -1;
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}
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last_cl_id = -1;
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NVIC_SetPriority(GPU2D_IRQn, IRQ_PRI_GPU);
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NVIC_EnableIRQ(GPU2D_IRQn);
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NVIC_SetPriority(GPU2D_ER_IRQn, IRQ_PRI_GPU);
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NVIC_EnableIRQ(GPU2D_ER_IRQn);
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return 0;
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}
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int nema_wait_irq_cl(int cl_id) {
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while (last_cl_id < cl_id) {
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__WFI();
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}
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return 0;
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}
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int nema_wait_irq_brk(int brk_id) {
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while (nema_reg_read(GPU2D_BREAKPOINT) == 0U) {
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__WFI();
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}
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return 0;
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}
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uint32_t nema_reg_read(uint32_t reg) {
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return HAL_GPU2D_ReadRegister(&gpu2d, reg);
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}
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void nema_reg_write(uint32_t reg, uint32_t value) {
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HAL_GPU2D_WriteRegister(&gpu2d, reg, value);
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}
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nema_buffer_t nema_buffer_create(int size) {
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nema_buffer_t bo = {
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.base_virt = nema_host_malloc(size),
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.base_phys = (uint32_t) bo.base_virt,
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.size = size,
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};
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return bo;
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}
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nema_buffer_t nema_buffer_create_pool(int pool, int size) {
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return nema_buffer_create(size);
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}
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void *nema_buffer_map(nema_buffer_t *bo) {
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return bo->base_virt;
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}
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void nema_buffer_unmap(nema_buffer_t *bo) {
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UNUSED(bo);
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}
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void nema_buffer_destroy(nema_buffer_t *bo) {
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nema_host_free(bo->base_virt);
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}
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uintptr_t nema_buffer_phys(nema_buffer_t *bo) {
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return bo->base_phys;
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}
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void nema_buffer_flush(nema_buffer_t *bo) {
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#if !OMV_GPU_NEMA_MM_STATIC
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SCB_CleanInvalidateDCache_by_Addr((uint32_t *) bo->base_virt, bo->size);
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#endif
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}
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void nema_host_free(void *ptr) {
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if (ptr) {
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free(ptr);
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}
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}
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void *nema_host_malloc(unsigned size) {
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return aligned_alloc(OMV_CACHE_LINE_SIZE, OMV_ALIGN_TO(size, OMV_CACHE_LINE_SIZE));
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}
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int nema_mutex_lock(int mutex_id) {
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return 0;
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}
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int nema_mutex_unlock(int mutex_id) {
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return 0;
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}
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void GPU2D_IRQHandler(void) {
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HAL_GPU2D_IRQHandler(&gpu2d);
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}
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void GPU2D_ER_IRQHandler(void) {
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HAL_GPU2D_ER_IRQHandler(&gpu2d);
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}
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void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *gpu2d, uint32_t CmdListID) {
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last_cl_id = CmdListID;
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}
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#endif // OMV_GPU_NEMA
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